clang/test/OpenMP/distribute_simd_reduction_codegen.cpp

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
   2 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1
   3 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
   4 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1
   5 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3
   6 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
   7 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3
   8
   9 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5
  10 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
  11 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK5
  12 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7
  13 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
  14 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK7
  15
  16 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9
  17 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
  18 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++  -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9
  19
  20 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11
  21 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
  22 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++  -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11
  23
  24 // expected-no-diagnostics
  25 #ifndef HEADER
  26 #define HEADER
  27
  28 template <typename T>
  29 T tmain() {
  30   T t_var = T();
  31   T vec[] = {1, 2};
  32 #pragma omp target
  33 #pragma omp teams
  34 #pragma omp distribute simd reduction(+: t_var)
  35   for (int i = 0; i < 2; ++i) {
  36     t_var += (T) i;
  37   }
  38   return T();
  39 }
  40
  41 int main() {
  42   static int sivar;
  43 #ifdef LAMBDA
  44   [&]() {
  45 #pragma omp target
  46 #pragma omp teams
  47 #pragma omp distribute simd reduction(+: sivar)
  48   for (int i = 0; i < 2; ++i) {
  49
  50     // Skip global and bound tid vars
  51
  52
  53     sivar += i;
  54
  55     [&]() {
  56
  57       sivar += 4;
  58
  59     }();
  60   }
  61   }();
  62   return 0;
  63 #else
  64 #pragma omp target
  65 #pragma omp teams
  66 #pragma omp distribute simd reduction(+: sivar)
  67   for (int i = 0; i < 2; ++i) {
  68     sivar += i;
  69   }
  70   return tmain<int>();
  71 #endif
  72 }
  73
  74
  75
  76 // Skip global and bound tid vars
  77
  78
  79
  80
  81 // Skip global and bound tid vars
  82
  83
  84 #endif
  85 // CHECK1-LABEL: define {{[^@]+}}@main
  86 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
  87 // CHECK1-NEXT:  entry:
  88 // CHECK1-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
  89 // CHECK1-NEXT:    [[SIVAR_CASTED:%.*]] = alloca i64, align 8
  90 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8
  91 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8
  92 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8
  93 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
  94 // CHECK1-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
  95 // CHECK1-NEXT:    store i32 0, ptr [[RETVAL]], align 4
  96 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4
  97 // CHECK1-NEXT:    store i32 [[TMP0]], ptr [[SIVAR_CASTED]], align 4
  98 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8
  99 // CHECK1-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
 100 // CHECK1-NEXT:    store i64 [[TMP1]], ptr [[TMP2]], align 8
 101 // CHECK1-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
 102 // CHECK1-NEXT:    store i64 [[TMP1]], ptr [[TMP3]], align 8
 103 // CHECK1-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
 104 // CHECK1-NEXT:    store ptr null, ptr [[TMP4]], align 8
 105 // CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
 106 // CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
 107 // CHECK1-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
 108 // CHECK1-NEXT:    store i32 2, ptr [[TMP7]], align 4
 109 // CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
 110 // CHECK1-NEXT:    store i32 1, ptr [[TMP8]], align 4
 111 // CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
 112 // CHECK1-NEXT:    store ptr [[TMP5]], ptr [[TMP9]], align 8
 113 // CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
 114 // CHECK1-NEXT:    store ptr [[TMP6]], ptr [[TMP10]], align 8
 115 // CHECK1-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
 116 // CHECK1-NEXT:    store ptr @.offload_sizes, ptr [[TMP11]], align 8
 117 // CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
 118 // CHECK1-NEXT:    store ptr @.offload_maptypes, ptr [[TMP12]], align 8
 119 // CHECK1-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
 120 // CHECK1-NEXT:    store ptr null, ptr [[TMP13]], align 8
 121 // CHECK1-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
 122 // CHECK1-NEXT:    store ptr null, ptr [[TMP14]], align 8
 123 // CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
 124 // CHECK1-NEXT:    store i64 2, ptr [[TMP15]], align 8
 125 // CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
 126 // CHECK1-NEXT:    store i64 0, ptr [[TMP16]], align 8
 127 // CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
 128 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP17]], align 4
 129 // CHECK1-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
 130 // CHECK1-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP18]], align 4
 131 // CHECK1-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
 132 // CHECK1-NEXT:    store i32 0, ptr [[TMP19]], align 4
 133 // CHECK1-NEXT:    [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64.region_id, ptr [[KERNEL_ARGS]])
 134 // CHECK1-NEXT:    [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
 135 // CHECK1-NEXT:    br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
 136 // CHECK1:       omp_offload.failed:
 137 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64(i64 [[TMP1]]) #[[ATTR2:[0-9]+]]
 138 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
 139 // CHECK1:       omp_offload.cont:
 140 // CHECK1-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v()
 141 // CHECK1-NEXT:    ret i32 [[CALL]]
 142 //
 143 //
 144 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64
 145 // CHECK1-SAME: (i64 noundef [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] {
 146 // CHECK1-NEXT:  entry:
 147 // CHECK1-NEXT:    [[SIVAR_ADDR:%.*]] = alloca i64, align 8
 148 // CHECK1-NEXT:    store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8
 149 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64.omp_outlined, ptr [[SIVAR_ADDR]])
 150 // CHECK1-NEXT:    ret void
 151 //
 152 //
 153 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64.omp_outlined
 154 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] {
 155 // CHECK1-NEXT:  entry:
 156 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 157 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 158 // CHECK1-NEXT:    [[SIVAR_ADDR:%.*]] = alloca ptr, align 8
 159 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 160 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 161 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
 162 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
 163 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 164 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 165 // CHECK1-NEXT:    [[SIVAR1:%.*]] = alloca i32, align 4
 166 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
 167 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 168 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 169 // CHECK1-NEXT:    store ptr [[SIVAR]], ptr [[SIVAR_ADDR]], align 8
 170 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8
 171 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
 172 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
 173 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 174 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 175 // CHECK1-NEXT:    store i32 0, ptr [[SIVAR1]], align 4
 176 // CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 177 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
 178 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
 179 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 180 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1
 181 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 182 // CHECK1:       cond.true:
 183 // CHECK1-NEXT:    br label [[COND_END:%.*]]
 184 // CHECK1:       cond.false:
 185 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 186 // CHECK1-NEXT:    br label [[COND_END]]
 187 // CHECK1:       cond.end:
 188 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
 189 // CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
 190 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
 191 // CHECK1-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
 192 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 193 // CHECK1:       omp.inner.for.cond:
 194 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5:![0-9]+]]
 195 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP5]]
 196 // CHECK1-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
 197 // CHECK1-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 198 // CHECK1:       omp.inner.for.body:
 199 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]]
 200 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
 201 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
 202 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]]
 203 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]]
 204 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[SIVAR1]], align 4, !llvm.access.group [[ACC_GRP5]]
 205 // CHECK1-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]
 206 // CHECK1-NEXT:    store i32 [[ADD3]], ptr [[SIVAR1]], align 4, !llvm.access.group [[ACC_GRP5]]
 207 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 208 // CHECK1:       omp.body.continue:
 209 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 210 // CHECK1:       omp.inner.for.inc:
 211 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]]
 212 // CHECK1-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1
 213 // CHECK1-NEXT:    store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]]
 214 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
 215 // CHECK1:       omp.inner.for.end:
 216 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
 217 // CHECK1:       omp.loop.exit:
 218 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])
 219 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
 220 // CHECK1-NEXT:    [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
 221 // CHECK1-NEXT:    br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
 222 // CHECK1:       .omp.final.then:
 223 // CHECK1-NEXT:    store i32 2, ptr [[I]], align 4
 224 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
 225 // CHECK1:       .omp.final.done:
 226 // CHECK1-NEXT:    [[TMP14:%.*]] = load i32, ptr [[TMP0]], align 4
 227 // CHECK1-NEXT:    [[TMP15:%.*]] = load i32, ptr [[SIVAR1]], align 4
 228 // CHECK1-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
 229 // CHECK1-NEXT:    store i32 [[ADD5]], ptr [[TMP0]], align 4
 230 // CHECK1-NEXT:    ret void
 231 //
 232 //
 233 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
 234 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] comdat {
 235 // CHECK1-NEXT:  entry:
 236 // CHECK1-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
 237 // CHECK1-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
 238 // CHECK1-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i64, align 8
 239 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8
 240 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8
 241 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8
 242 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 243 // CHECK1-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
 244 // CHECK1-NEXT:    store i32 0, ptr [[T_VAR]], align 4
 245 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false)
 246 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[T_VAR]], align 4
 247 // CHECK1-NEXT:    store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 4
 248 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8
 249 // CHECK1-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
 250 // CHECK1-NEXT:    store i64 [[TMP1]], ptr [[TMP2]], align 8
 251 // CHECK1-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
 252 // CHECK1-NEXT:    store i64 [[TMP1]], ptr [[TMP3]], align 8
 253 // CHECK1-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
 254 // CHECK1-NEXT:    store ptr null, ptr [[TMP4]], align 8
 255 // CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
 256 // CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
 257 // CHECK1-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
 258 // CHECK1-NEXT:    store i32 2, ptr [[TMP7]], align 4
 259 // CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
 260 // CHECK1-NEXT:    store i32 1, ptr [[TMP8]], align 4
 261 // CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
 262 // CHECK1-NEXT:    store ptr [[TMP5]], ptr [[TMP9]], align 8
 263 // CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
 264 // CHECK1-NEXT:    store ptr [[TMP6]], ptr [[TMP10]], align 8
 265 // CHECK1-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
 266 // CHECK1-NEXT:    store ptr @.offload_sizes.1, ptr [[TMP11]], align 8
 267 // CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
 268 // CHECK1-NEXT:    store ptr @.offload_maptypes.2, ptr [[TMP12]], align 8
 269 // CHECK1-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
 270 // CHECK1-NEXT:    store ptr null, ptr [[TMP13]], align 8
 271 // CHECK1-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
 272 // CHECK1-NEXT:    store ptr null, ptr [[TMP14]], align 8
 273 // CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
 274 // CHECK1-NEXT:    store i64 2, ptr [[TMP15]], align 8
 275 // CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
 276 // CHECK1-NEXT:    store i64 0, ptr [[TMP16]], align 8
 277 // CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
 278 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP17]], align 4
 279 // CHECK1-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
 280 // CHECK1-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP18]], align 4
 281 // CHECK1-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
 282 // CHECK1-NEXT:    store i32 0, ptr [[TMP19]], align 4
 283 // CHECK1-NEXT:    [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.region_id, ptr [[KERNEL_ARGS]])
 284 // CHECK1-NEXT:    [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
 285 // CHECK1-NEXT:    br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
 286 // CHECK1:       omp_offload.failed:
 287 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32(i64 [[TMP1]]) #[[ATTR2]]
 288 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
 289 // CHECK1:       omp_offload.cont:
 290 // CHECK1-NEXT:    ret i32 0
 291 //
 292 //
 293 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32
 294 // CHECK1-SAME: (i64 noundef [[T_VAR:%.*]]) #[[ATTR1]] {
 295 // CHECK1-NEXT:  entry:
 296 // CHECK1-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i64, align 8
 297 // CHECK1-NEXT:    store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
 298 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined, ptr [[T_VAR_ADDR]])
 299 // CHECK1-NEXT:    ret void
 300 //
 301 //
 302 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined
 303 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] {
 304 // CHECK1-NEXT:  entry:
 305 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 306 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 307 // CHECK1-NEXT:    [[T_VAR_ADDR:%.*]] = alloca ptr, align 8
 308 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 309 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 310 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
 311 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
 312 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 313 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 314 // CHECK1-NEXT:    [[T_VAR1:%.*]] = alloca i32, align 4
 315 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
 316 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 317 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 318 // CHECK1-NEXT:    store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
 319 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8
 320 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
 321 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
 322 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 323 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 324 // CHECK1-NEXT:    store i32 0, ptr [[T_VAR1]], align 4
 325 // CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 326 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
 327 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
 328 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 329 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1
 330 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 331 // CHECK1:       cond.true:
 332 // CHECK1-NEXT:    br label [[COND_END:%.*]]
 333 // CHECK1:       cond.false:
 334 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 335 // CHECK1-NEXT:    br label [[COND_END]]
 336 // CHECK1:       cond.end:
 337 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
 338 // CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
 339 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
 340 // CHECK1-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
 341 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 342 // CHECK1:       omp.inner.for.cond:
 343 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11:![0-9]+]]
 344 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP11]]
 345 // CHECK1-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
 346 // CHECK1-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 347 // CHECK1:       omp.inner.for.body:
 348 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]
 349 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
 350 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
 351 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]]
 352 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]]
 353 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[T_VAR1]], align 4, !llvm.access.group [[ACC_GRP11]]
 354 // CHECK1-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]
 355 // CHECK1-NEXT:    store i32 [[ADD3]], ptr [[T_VAR1]], align 4, !llvm.access.group [[ACC_GRP11]]
 356 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 357 // CHECK1:       omp.body.continue:
 358 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 359 // CHECK1:       omp.inner.for.inc:
 360 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]
 361 // CHECK1-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1
 362 // CHECK1-NEXT:    store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]
 363 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
 364 // CHECK1:       omp.inner.for.end:
 365 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
 366 // CHECK1:       omp.loop.exit:
 367 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])
 368 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
 369 // CHECK1-NEXT:    [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
 370 // CHECK1-NEXT:    br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
 371 // CHECK1:       .omp.final.then:
 372 // CHECK1-NEXT:    store i32 2, ptr [[I]], align 4
 373 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
 374 // CHECK1:       .omp.final.done:
 375 // CHECK1-NEXT:    [[TMP14:%.*]] = load i32, ptr [[TMP0]], align 4
 376 // CHECK1-NEXT:    [[TMP15:%.*]] = load i32, ptr [[T_VAR1]], align 4
 377 // CHECK1-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
 378 // CHECK1-NEXT:    store i32 [[ADD5]], ptr [[TMP0]], align 4
 379 // CHECK1-NEXT:    ret void
 380 //
 381 //
 382 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
 383 // CHECK1-SAME: () #[[ATTR5:[0-9]+]] {
 384 // CHECK1-NEXT:  entry:
 385 // CHECK1-NEXT:    call void @__tgt_register_requires(i64 1)
 386 // CHECK1-NEXT:    ret void
 387 //
 388 //
 389 // CHECK3-LABEL: define {{[^@]+}}@main
 390 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] {
 391 // CHECK3-NEXT:  entry:
 392 // CHECK3-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
 393 // CHECK3-NEXT:    [[SIVAR_CASTED:%.*]] = alloca i32, align 4
 394 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 4
 395 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 4
 396 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 4
 397 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 398 // CHECK3-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
 399 // CHECK3-NEXT:    store i32 0, ptr [[RETVAL]], align 4
 400 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4
 401 // CHECK3-NEXT:    store i32 [[TMP0]], ptr [[SIVAR_CASTED]], align 4
 402 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[SIVAR_CASTED]], align 4
 403 // CHECK3-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
 404 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[TMP2]], align 4
 405 // CHECK3-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
 406 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[TMP3]], align 4
 407 // CHECK3-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
 408 // CHECK3-NEXT:    store ptr null, ptr [[TMP4]], align 4
 409 // CHECK3-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
 410 // CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
 411 // CHECK3-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
 412 // CHECK3-NEXT:    store i32 2, ptr [[TMP7]], align 4
 413 // CHECK3-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
 414 // CHECK3-NEXT:    store i32 1, ptr [[TMP8]], align 4
 415 // CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
 416 // CHECK3-NEXT:    store ptr [[TMP5]], ptr [[TMP9]], align 4
 417 // CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
 418 // CHECK3-NEXT:    store ptr [[TMP6]], ptr [[TMP10]], align 4
 419 // CHECK3-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
 420 // CHECK3-NEXT:    store ptr @.offload_sizes, ptr [[TMP11]], align 4
 421 // CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
 422 // CHECK3-NEXT:    store ptr @.offload_maptypes, ptr [[TMP12]], align 4
 423 // CHECK3-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
 424 // CHECK3-NEXT:    store ptr null, ptr [[TMP13]], align 4
 425 // CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
 426 // CHECK3-NEXT:    store ptr null, ptr [[TMP14]], align 4
 427 // CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
 428 // CHECK3-NEXT:    store i64 2, ptr [[TMP15]], align 8
 429 // CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
 430 // CHECK3-NEXT:    store i64 0, ptr [[TMP16]], align 8
 431 // CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
 432 // CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP17]], align 4
 433 // CHECK3-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
 434 // CHECK3-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP18]], align 4
 435 // CHECK3-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
 436 // CHECK3-NEXT:    store i32 0, ptr [[TMP19]], align 4
 437 // CHECK3-NEXT:    [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64.region_id, ptr [[KERNEL_ARGS]])
 438 // CHECK3-NEXT:    [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
 439 // CHECK3-NEXT:    br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
 440 // CHECK3:       omp_offload.failed:
 441 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64(i32 [[TMP1]]) #[[ATTR2:[0-9]+]]
 442 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]
 443 // CHECK3:       omp_offload.cont:
 444 // CHECK3-NEXT:    [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()
 445 // CHECK3-NEXT:    ret i32 [[CALL]]
 446 //
 447 //
 448 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64
 449 // CHECK3-SAME: (i32 noundef [[SIVAR:%.*]]) #[[ATTR1:[0-9]+]] {
 450 // CHECK3-NEXT:  entry:
 451 // CHECK3-NEXT:    [[SIVAR_ADDR:%.*]] = alloca i32, align 4
 452 // CHECK3-NEXT:    store i32 [[SIVAR]], ptr [[SIVAR_ADDR]], align 4
 453 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64.omp_outlined, ptr [[SIVAR_ADDR]])
 454 // CHECK3-NEXT:    ret void
 455 //
 456 //
 457 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l64.omp_outlined
 458 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR1]] {
 459 // CHECK3-NEXT:  entry:
 460 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
 461 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
 462 // CHECK3-NEXT:    [[SIVAR_ADDR:%.*]] = alloca ptr, align 4
 463 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 464 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 465 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
 466 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
 467 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 468 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 469 // CHECK3-NEXT:    [[SIVAR1:%.*]] = alloca i32, align 4
 470 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
 471 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
 472 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
 473 // CHECK3-NEXT:    store ptr [[SIVAR]], ptr [[SIVAR_ADDR]], align 4
 474 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 4
 475 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
 476 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
 477 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 478 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 479 // CHECK3-NEXT:    store i32 0, ptr [[SIVAR1]], align 4
 480 // CHECK3-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
 481 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
 482 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
 483 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 484 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1
 485 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 486 // CHECK3:       cond.true:
 487 // CHECK3-NEXT:    br label [[COND_END:%.*]]
 488 // CHECK3:       cond.false:
 489 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 490 // CHECK3-NEXT:    br label [[COND_END]]
 491 // CHECK3:       cond.end:
 492 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
 493 // CHECK3-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
 494 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
 495 // CHECK3-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
 496 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 497 // CHECK3:       omp.inner.for.cond:
 498 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]]
 499 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP6]]
 500 // CHECK3-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
 501 // CHECK3-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 502 // CHECK3:       omp.inner.for.body:
 503 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
 504 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
 505 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
 506 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]]
 507 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]]
 508 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[SIVAR1]], align 4, !llvm.access.group [[ACC_GRP6]]
 509 // CHECK3-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]
 510 // CHECK3-NEXT:    store i32 [[ADD3]], ptr [[SIVAR1]], align 4, !llvm.access.group [[ACC_GRP6]]
 511 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 512 // CHECK3:       omp.body.continue:
 513 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 514 // CHECK3:       omp.inner.for.inc:
 515 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
 516 // CHECK3-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1
 517 // CHECK3-NEXT:    store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
 518 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
 519 // CHECK3:       omp.inner.for.end:
 520 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
 521 // CHECK3:       omp.loop.exit:
 522 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])
 523 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
 524 // CHECK3-NEXT:    [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
 525 // CHECK3-NEXT:    br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
 526 // CHECK3:       .omp.final.then:
 527 // CHECK3-NEXT:    store i32 2, ptr [[I]], align 4
 528 // CHECK3-NEXT:    br label [[DOTOMP_FINAL_DONE]]
 529 // CHECK3:       .omp.final.done:
 530 // CHECK3-NEXT:    [[TMP14:%.*]] = load i32, ptr [[TMP0]], align 4
 531 // CHECK3-NEXT:    [[TMP15:%.*]] = load i32, ptr [[SIVAR1]], align 4
 532 // CHECK3-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
 533 // CHECK3-NEXT:    store i32 [[ADD5]], ptr [[TMP0]], align 4
 534 // CHECK3-NEXT:    ret void
 535 //
 536 //
 537 // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
 538 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] comdat {
 539 // CHECK3-NEXT:  entry:
 540 // CHECK3-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
 541 // CHECK3-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
 542 // CHECK3-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i32, align 4
 543 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 4
 544 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 4
 545 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 4
 546 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 547 // CHECK3-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
 548 // CHECK3-NEXT:    store i32 0, ptr [[T_VAR]], align 4
 549 // CHECK3-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false)
 550 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[T_VAR]], align 4
 551 // CHECK3-NEXT:    store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 4
 552 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4
 553 // CHECK3-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
 554 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[TMP2]], align 4
 555 // CHECK3-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
 556 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[TMP3]], align 4
 557 // CHECK3-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
 558 // CHECK3-NEXT:    store ptr null, ptr [[TMP4]], align 4
 559 // CHECK3-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
 560 // CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
 561 // CHECK3-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
 562 // CHECK3-NEXT:    store i32 2, ptr [[TMP7]], align 4
 563 // CHECK3-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
 564 // CHECK3-NEXT:    store i32 1, ptr [[TMP8]], align 4
 565 // CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
 566 // CHECK3-NEXT:    store ptr [[TMP5]], ptr [[TMP9]], align 4
 567 // CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
 568 // CHECK3-NEXT:    store ptr [[TMP6]], ptr [[TMP10]], align 4
 569 // CHECK3-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
 570 // CHECK3-NEXT:    store ptr @.offload_sizes.1, ptr [[TMP11]], align 4
 571 // CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
 572 // CHECK3-NEXT:    store ptr @.offload_maptypes.2, ptr [[TMP12]], align 4
 573 // CHECK3-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
 574 // CHECK3-NEXT:    store ptr null, ptr [[TMP13]], align 4
 575 // CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
 576 // CHECK3-NEXT:    store ptr null, ptr [[TMP14]], align 4
 577 // CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
 578 // CHECK3-NEXT:    store i64 2, ptr [[TMP15]], align 8
 579 // CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
 580 // CHECK3-NEXT:    store i64 0, ptr [[TMP16]], align 8
 581 // CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
 582 // CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP17]], align 4
 583 // CHECK3-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
 584 // CHECK3-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP18]], align 4
 585 // CHECK3-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
 586 // CHECK3-NEXT:    store i32 0, ptr [[TMP19]], align 4
 587 // CHECK3-NEXT:    [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.region_id, ptr [[KERNEL_ARGS]])
 588 // CHECK3-NEXT:    [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
 589 // CHECK3-NEXT:    br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
 590 // CHECK3:       omp_offload.failed:
 591 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32(i32 [[TMP1]]) #[[ATTR2]]
 592 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]
 593 // CHECK3:       omp_offload.cont:
 594 // CHECK3-NEXT:    ret i32 0
 595 //
 596 //
 597 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32
 598 // CHECK3-SAME: (i32 noundef [[T_VAR:%.*]]) #[[ATTR1]] {
 599 // CHECK3-NEXT:  entry:
 600 // CHECK3-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i32, align 4
 601 // CHECK3-NEXT:    store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4
 602 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined, ptr [[T_VAR_ADDR]])
 603 // CHECK3-NEXT:    ret void
 604 //
 605 //
 606 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l32.omp_outlined
 607 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR1]] {
 608 // CHECK3-NEXT:  entry:
 609 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
 610 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
 611 // CHECK3-NEXT:    [[T_VAR_ADDR:%.*]] = alloca ptr, align 4
 612 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 613 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 614 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
 615 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
 616 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 617 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 618 // CHECK3-NEXT:    [[T_VAR1:%.*]] = alloca i32, align 4
 619 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
 620 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
 621 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
 622 // CHECK3-NEXT:    store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 4
 623 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 4
 624 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
 625 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
 626 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 627 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 628 // CHECK3-NEXT:    store i32 0, ptr [[T_VAR1]], align 4
 629 // CHECK3-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
 630 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
 631 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
 632 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 633 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1
 634 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 635 // CHECK3:       cond.true:
 636 // CHECK3-NEXT:    br label [[COND_END:%.*]]
 637 // CHECK3:       cond.false:
 638 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 639 // CHECK3-NEXT:    br label [[COND_END]]
 640 // CHECK3:       cond.end:
 641 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
 642 // CHECK3-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
 643 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
 644 // CHECK3-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
 645 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 646 // CHECK3:       omp.inner.for.cond:
 647 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12:![0-9]+]]
 648 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP12]]
 649 // CHECK3-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
 650 // CHECK3-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 651 // CHECK3:       omp.inner.for.body:
 652 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]
 653 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
 654 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
 655 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]]
 656 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]]
 657 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[T_VAR1]], align 4, !llvm.access.group [[ACC_GRP12]]
 658 // CHECK3-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]
 659 // CHECK3-NEXT:    store i32 [[ADD3]], ptr [[T_VAR1]], align 4, !llvm.access.group [[ACC_GRP12]]
 660 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 661 // CHECK3:       omp.body.continue:
 662 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 663 // CHECK3:       omp.inner.for.inc:
 664 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]
 665 // CHECK3-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1
 666 // CHECK3-NEXT:    store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]
 667 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
 668 // CHECK3:       omp.inner.for.end:
 669 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
 670 // CHECK3:       omp.loop.exit:
 671 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])
 672 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
 673 // CHECK3-NEXT:    [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
 674 // CHECK3-NEXT:    br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
 675 // CHECK3:       .omp.final.then:
 676 // CHECK3-NEXT:    store i32 2, ptr [[I]], align 4
 677 // CHECK3-NEXT:    br label [[DOTOMP_FINAL_DONE]]
 678 // CHECK3:       .omp.final.done:
 679 // CHECK3-NEXT:    [[TMP14:%.*]] = load i32, ptr [[TMP0]], align 4
 680 // CHECK3-NEXT:    [[TMP15:%.*]] = load i32, ptr [[T_VAR1]], align 4
 681 // CHECK3-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
 682 // CHECK3-NEXT:    store i32 [[ADD5]], ptr [[TMP0]], align 4
 683 // CHECK3-NEXT:    ret void
 684 //
 685 //
 686 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
 687 // CHECK3-SAME: () #[[ATTR5:[0-9]+]] {
 688 // CHECK3-NEXT:  entry:
 689 // CHECK3-NEXT:    call void @__tgt_register_requires(i64 1)
 690 // CHECK3-NEXT:    ret void
 691 //
 692 //
 693 // CHECK5-LABEL: define {{[^@]+}}@main
 694 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] {
 695 // CHECK5-NEXT:  entry:
 696 // CHECK5-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
 697 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 698 // CHECK5-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
 699 // CHECK5-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
 700 // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 701 // CHECK5-NEXT:    [[I:%.*]] = alloca i32, align 4
 702 // CHECK5-NEXT:    [[SIVAR:%.*]] = alloca i32, align 4
 703 // CHECK5-NEXT:    store i32 0, ptr [[RETVAL]], align 4
 704 // CHECK5-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
 705 // CHECK5-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
 706 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
 707 // CHECK5-NEXT:    store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4
 708 // CHECK5-NEXT:    store i32 0, ptr [[SIVAR]], align 4
 709 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 710 // CHECK5:       omp.inner.for.cond:
 711 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]]
 712 // CHECK5-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP2]]
 713 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
 714 // CHECK5-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 715 // CHECK5:       omp.inner.for.body:
 716 // CHECK5-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
 717 // CHECK5-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
 718 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
 719 // CHECK5-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]
 720 // CHECK5-NEXT:    [[TMP4:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]
 721 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP2]]
 722 // CHECK5-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP5]], [[TMP4]]
 723 // CHECK5-NEXT:    store i32 [[ADD1]], ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP2]]
 724 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 725 // CHECK5:       omp.body.continue:
 726 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 727 // CHECK5:       omp.inner.for.inc:
 728 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
 729 // CHECK5-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP6]], 1
 730 // CHECK5-NEXT:    store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
 731 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
 732 // CHECK5:       omp.inner.for.end:
 733 // CHECK5-NEXT:    store i32 2, ptr [[I]], align 4
 734 // CHECK5-NEXT:    [[TMP7:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4
 735 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, ptr [[SIVAR]], align 4
 736 // CHECK5-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP7]], [[TMP8]]
 737 // CHECK5-NEXT:    store i32 [[ADD3]], ptr @_ZZ4mainE5sivar, align 4
 738 // CHECK5-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v()
 739 // CHECK5-NEXT:    ret i32 [[CALL]]
 740 //
 741 //
 742 // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
 743 // CHECK5-SAME: () #[[ATTR1:[0-9]+]] comdat {
 744 // CHECK5-NEXT:  entry:
 745 // CHECK5-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
 746 // CHECK5-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
 747 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 748 // CHECK5-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
 749 // CHECK5-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
 750 // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 751 // CHECK5-NEXT:    [[I:%.*]] = alloca i32, align 4
 752 // CHECK5-NEXT:    [[T_VAR1:%.*]] = alloca i32, align 4
 753 // CHECK5-NEXT:    store i32 0, ptr [[T_VAR]], align 4
 754 // CHECK5-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false)
 755 // CHECK5-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
 756 // CHECK5-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
 757 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
 758 // CHECK5-NEXT:    store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4
 759 // CHECK5-NEXT:    store i32 0, ptr [[T_VAR1]], align 4
 760 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 761 // CHECK5:       omp.inner.for.cond:
 762 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]]
 763 // CHECK5-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP6]]
 764 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
 765 // CHECK5-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 766 // CHECK5:       omp.inner.for.body:
 767 // CHECK5-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
 768 // CHECK5-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
 769 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
 770 // CHECK5-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]]
 771 // CHECK5-NEXT:    [[TMP4:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]]
 772 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, ptr [[T_VAR1]], align 4, !llvm.access.group [[ACC_GRP6]]
 773 // CHECK5-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP5]], [[TMP4]]
 774 // CHECK5-NEXT:    store i32 [[ADD2]], ptr [[T_VAR1]], align 4, !llvm.access.group [[ACC_GRP6]]
 775 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 776 // CHECK5:       omp.body.continue:
 777 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 778 // CHECK5:       omp.inner.for.inc:
 779 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
 780 // CHECK5-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP6]], 1
 781 // CHECK5-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
 782 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
 783 // CHECK5:       omp.inner.for.end:
 784 // CHECK5-NEXT:    store i32 2, ptr [[I]], align 4
 785 // CHECK5-NEXT:    [[TMP7:%.*]] = load i32, ptr [[T_VAR]], align 4
 786 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, ptr [[T_VAR1]], align 4
 787 // CHECK5-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP7]], [[TMP8]]
 788 // CHECK5-NEXT:    store i32 [[ADD4]], ptr [[T_VAR]], align 4
 789 // CHECK5-NEXT:    ret i32 0
 790 //
 791 //
 792 // CHECK7-LABEL: define {{[^@]+}}@main
 793 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] {
 794 // CHECK7-NEXT:  entry:
 795 // CHECK7-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
 796 // CHECK7-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 797 // CHECK7-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
 798 // CHECK7-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
 799 // CHECK7-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 800 // CHECK7-NEXT:    [[I:%.*]] = alloca i32, align 4
 801 // CHECK7-NEXT:    [[SIVAR:%.*]] = alloca i32, align 4
 802 // CHECK7-NEXT:    store i32 0, ptr [[RETVAL]], align 4
 803 // CHECK7-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
 804 // CHECK7-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
 805 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
 806 // CHECK7-NEXT:    store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4
 807 // CHECK7-NEXT:    store i32 0, ptr [[SIVAR]], align 4
 808 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 809 // CHECK7:       omp.inner.for.cond:
 810 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3:![0-9]+]]
 811 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP3]]
 812 // CHECK7-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
 813 // CHECK7-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 814 // CHECK7:       omp.inner.for.body:
 815 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]
 816 // CHECK7-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
 817 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
 818 // CHECK7-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]]
 819 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]]
 820 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP3]]
 821 // CHECK7-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP5]], [[TMP4]]
 822 // CHECK7-NEXT:    store i32 [[ADD1]], ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP3]]
 823 // CHECK7-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 824 // CHECK7:       omp.body.continue:
 825 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 826 // CHECK7:       omp.inner.for.inc:
 827 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]
 828 // CHECK7-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP6]], 1
 829 // CHECK7-NEXT:    store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]
 830 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
 831 // CHECK7:       omp.inner.for.end:
 832 // CHECK7-NEXT:    store i32 2, ptr [[I]], align 4
 833 // CHECK7-NEXT:    [[TMP7:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4
 834 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, ptr [[SIVAR]], align 4
 835 // CHECK7-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP7]], [[TMP8]]
 836 // CHECK7-NEXT:    store i32 [[ADD3]], ptr @_ZZ4mainE5sivar, align 4
 837 // CHECK7-NEXT:    [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()
 838 // CHECK7-NEXT:    ret i32 [[CALL]]
 839 //
 840 //
 841 // CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
 842 // CHECK7-SAME: () #[[ATTR1:[0-9]+]] comdat {
 843 // CHECK7-NEXT:  entry:
 844 // CHECK7-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
 845 // CHECK7-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
 846 // CHECK7-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 847 // CHECK7-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
 848 // CHECK7-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
 849 // CHECK7-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 850 // CHECK7-NEXT:    [[I:%.*]] = alloca i32, align 4
 851 // CHECK7-NEXT:    [[T_VAR1:%.*]] = alloca i32, align 4
 852 // CHECK7-NEXT:    store i32 0, ptr [[T_VAR]], align 4
 853 // CHECK7-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false)
 854 // CHECK7-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
 855 // CHECK7-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
 856 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
 857 // CHECK7-NEXT:    store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4
 858 // CHECK7-NEXT:    store i32 0, ptr [[T_VAR1]], align 4
 859 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 860 // CHECK7:       omp.inner.for.cond:
 861 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7:![0-9]+]]
 862 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP7]]
 863 // CHECK7-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
 864 // CHECK7-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 865 // CHECK7:       omp.inner.for.body:
 866 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]]
 867 // CHECK7-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
 868 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
 869 // CHECK7-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]]
 870 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]]
 871 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, ptr [[T_VAR1]], align 4, !llvm.access.group [[ACC_GRP7]]
 872 // CHECK7-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP5]], [[TMP4]]
 873 // CHECK7-NEXT:    store i32 [[ADD2]], ptr [[T_VAR1]], align 4, !llvm.access.group [[ACC_GRP7]]
 874 // CHECK7-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 875 // CHECK7:       omp.body.continue:
 876 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 877 // CHECK7:       omp.inner.for.inc:
 878 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]]
 879 // CHECK7-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP6]], 1
 880 // CHECK7-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]]
 881 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
 882 // CHECK7:       omp.inner.for.end:
 883 // CHECK7-NEXT:    store i32 2, ptr [[I]], align 4
 884 // CHECK7-NEXT:    [[TMP7:%.*]] = load i32, ptr [[T_VAR]], align 4
 885 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, ptr [[T_VAR1]], align 4
 886 // CHECK7-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP7]], [[TMP8]]
 887 // CHECK7-NEXT:    store i32 [[ADD4]], ptr [[T_VAR]], align 4
 888 // CHECK7-NEXT:    ret i32 0
 889 //
 890 //
 891 // CHECK9-LABEL: define {{[^@]+}}@main
 892 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] {
 893 // CHECK9-NEXT:  entry:
 894 // CHECK9-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
 895 // CHECK9-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
 896 // CHECK9-NEXT:    store i32 0, ptr [[RETVAL]], align 4
 897 // CHECK9-NEXT:    call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])
 898 // CHECK9-NEXT:    ret i32 0
 899 //
 900 //
 901 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l45
 902 // CHECK9-SAME: (i64 noundef [[SIVAR:%.*]]) #[[ATTR2:[0-9]+]] {
 903 // CHECK9-NEXT:  entry:
 904 // CHECK9-NEXT:    [[SIVAR_ADDR:%.*]] = alloca i64, align 8
 905 // CHECK9-NEXT:    store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8
 906 // CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l45.omp_outlined, ptr [[SIVAR_ADDR]])
 907 // CHECK9-NEXT:    ret void
 908 //
 909 //
 910 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l45.omp_outlined
 911 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SIVAR:%.*]]) #[[ATTR2]] {
 912 // CHECK9-NEXT:  entry:
 913 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 914 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 915 // CHECK9-NEXT:    [[SIVAR_ADDR:%.*]] = alloca ptr, align 8
 916 // CHECK9-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 917 // CHECK9-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 918 // CHECK9-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
 919 // CHECK9-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
 920 // CHECK9-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 921 // CHECK9-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 922 // CHECK9-NEXT:    [[SIVAR1:%.*]] = alloca i32, align 4
 923 // CHECK9-NEXT:    [[I:%.*]] = alloca i32, align 4
 924 // CHECK9-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8
 925 // CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 926 // CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 927 // CHECK9-NEXT:    store ptr [[SIVAR]], ptr [[SIVAR_ADDR]], align 8
 928 // CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[SIVAR_ADDR]], align 8
 929 // CHECK9-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
 930 // CHECK9-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
 931 // CHECK9-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 932 // CHECK9-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 933 // CHECK9-NEXT:    store i32 0, ptr [[SIVAR1]], align 4
 934 // CHECK9-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 935 // CHECK9-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
 936 // CHECK9-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
 937 // CHECK9-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 938 // CHECK9-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1
 939 // CHECK9-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 940 // CHECK9:       cond.true:
 941 // CHECK9-NEXT:    br label [[COND_END:%.*]]
 942 // CHECK9:       cond.false:
 943 // CHECK9-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 944 // CHECK9-NEXT:    br label [[COND_END]]
 945 // CHECK9:       cond.end:
 946 // CHECK9-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
 947 // CHECK9-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
 948 // CHECK9-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
 949 // CHECK9-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
 950 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 951 // CHECK9:       omp.inner.for.cond:
 952 // CHECK9-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4:![0-9]+]]
 953 // CHECK9-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP4]]
 954 // CHECK9-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
 955 // CHECK9-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 956 // CHECK9:       omp.inner.for.body:
 957 // CHECK9-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]]
 958 // CHECK9-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
 959 // CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
 960 // CHECK9-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP4]]
 961 // CHECK9-NEXT:    [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP4]]
 962 // CHECK9-NEXT:    [[TMP10:%.*]] = load i32, ptr [[SIVAR1]], align 4, !llvm.access.group [[ACC_GRP4]]
 963 // CHECK9-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]
 964 // CHECK9-NEXT:    store i32 [[ADD3]], ptr [[SIVAR1]], align 4, !llvm.access.group [[ACC_GRP4]]
 965 // CHECK9-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0
 966 // CHECK9-NEXT:    store ptr [[SIVAR1]], ptr [[TMP11]], align 8, !llvm.access.group [[ACC_GRP4]]
 967 // CHECK9-NEXT:    call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(8) [[REF_TMP]]), !llvm.access.group [[ACC_GRP4]]
 968 // CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 969 // CHECK9:       omp.body.continue:
 970 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 971 // CHECK9:       omp.inner.for.inc:
 972 // CHECK9-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]]
 973 // CHECK9-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
 974 // CHECK9-NEXT:    store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]]
 975 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
 976 // CHECK9:       omp.inner.for.end:
 977 // CHECK9-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
 978 // CHECK9:       omp.loop.exit:
 979 // CHECK9-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])
 980 // CHECK9-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
 981 // CHECK9-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
 982 // CHECK9-NEXT:    br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
 983 // CHECK9:       .omp.final.then:
 984 // CHECK9-NEXT:    store i32 2, ptr [[I]], align 4
 985 // CHECK9-NEXT:    br label [[DOTOMP_FINAL_DONE]]
 986 // CHECK9:       .omp.final.done:
 987 // CHECK9-NEXT:    [[TMP15:%.*]] = load i32, ptr [[TMP0]], align 4
 988 // CHECK9-NEXT:    [[TMP16:%.*]] = load i32, ptr [[SIVAR1]], align 4
 989 // CHECK9-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
 990 // CHECK9-NEXT:    store i32 [[ADD5]], ptr [[TMP0]], align 4
 991 // CHECK9-NEXT:    ret void
 992 //
 993 //
 994 // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
 995 // CHECK9-SAME: () #[[ATTR4:[0-9]+]] {
 996 // CHECK9-NEXT:  entry:
 997 // CHECK9-NEXT:    call void @__tgt_register_requires(i64 1)
 998 // CHECK9-NEXT:    ret void
 999 //
1000 //
1001 // CHECK11-LABEL: define {{[^@]+}}@main
1002 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] {
1003 // CHECK11-NEXT:  entry:
1004 // CHECK11-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
1005 // CHECK11-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
1006 // CHECK11-NEXT:    store i32 0, ptr [[RETVAL]], align 4
1007 // CHECK11-NEXT:    call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])
1008 // CHECK11-NEXT:    ret i32 0
1009 //