clang/test/OpenMP/irbuilder_unroll_partial_factor_for_collapse.c

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_  size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
   2 // RUN: %clang_cc1 -fopenmp-enable-irbuilder -verify -fopenmp -x c -triple x86_64-unknown-unknown -emit-llvm %s -o - | FileCheck %s
   3 // expected-no-diagnostics
   4
   5 #ifndef HEADER
   6 #define HEADER
   7
   8 void unroll_partial_factor_for_collapse(int m, float *a, float *b, float *c, float *d) {
   9 #pragma omp for collapse(2)
  10   for (int i = 0; i < m; i++) {
  11 #pragma omp unroll partial(4)
  12     for (int j = 0; j < 8; j++) {
  13       a[i] += b[i] + c[i] * d[j];
  14     }
  15   }
  16 }
  17
  18 #endif // HEADER
  19
  20 // CHECK-LABEL: define {{[^@]+}}@unroll_partial_factor_for_collapse
  21 // CHECK-SAME: (i32 noundef [[M:%.*]], ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] {
  22 // CHECK-NEXT:  entry:
  23 // CHECK-NEXT:    [[M_ADDR:%.*]] = alloca i32, align 4
  24 // CHECK-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
  25 // CHECK-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
  26 // CHECK-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
  27 // CHECK-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
  28 // CHECK-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
  29 // CHECK-NEXT:    [[TMP:%.*]] = alloca i32, align 4
  30 // CHECK-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
  31 // CHECK-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
  32 // CHECK-NEXT:    [[J:%.*]] = alloca i32, align 4
  33 // CHECK-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 8
  34 // CHECK-NEXT:    [[I:%.*]] = alloca i32, align 4
  35 // CHECK-NEXT:    [[DOTUNROLLED_IV_J:%.*]] = alloca i32, align 4
  36 // CHECK-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
  37 // CHECK-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
  38 // CHECK-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
  39 // CHECK-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
  40 // CHECK-NEXT:    [[I6:%.*]] = alloca i32, align 4
  41 // CHECK-NEXT:    [[DOTUNROLLED_IV_J7:%.*]] = alloca i32, align 4
  42 // CHECK-NEXT:    [[DOTUNROLL_INNER_IV_J:%.*]] = alloca i32, align 4
  43 // CHECK-NEXT:    store i32 [[M]], ptr [[M_ADDR]], align 4
  44 // CHECK-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
  45 // CHECK-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
  46 // CHECK-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
  47 // CHECK-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
  48 // CHECK-NEXT:    [[TMP0:%.*]] = load i32, ptr [[M_ADDR]], align 4
  49 // CHECK-NEXT:    store i32 [[TMP0]], ptr [[DOTCAPTURE_EXPR_]], align 4
  50 // CHECK-NEXT:    store i32 0, ptr [[J]], align 4
  51 // CHECK-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
  52 // CHECK-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP1]], 0
  53 // CHECK-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1
  54 // CHECK-NEXT:    [[CONV:%.*]] = sext i32 [[DIV]] to i64
  55 // CHECK-NEXT:    [[MUL:%.*]] = mul nsw i64 [[CONV]], 2
  56 // CHECK-NEXT:    [[SUB3:%.*]] = sub nsw i64 [[MUL]], 1
  57 // CHECK-NEXT:    store i64 [[SUB3]], ptr [[DOTCAPTURE_EXPR_2]], align 8
  58 // CHECK-NEXT:    store i32 0, ptr [[I]], align 4
  59 // CHECK-NEXT:    store i32 0, ptr [[DOTUNROLLED_IV_J]], align 4
  60 // CHECK-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
  61 // CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP2]]
  62 // CHECK-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
  63 // CHECK:       omp.precond.then:
  64 // CHECK-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8
  65 // CHECK-NEXT:    [[TMP3:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_2]], align 8
  66 // CHECK-NEXT:    store i64 [[TMP3]], ptr [[DOTOMP_UB]], align 8
  67 // CHECK-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8
  68 // CHECK-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
  69 // CHECK-NEXT:    [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3:[0-9]+]])
  70 // CHECK-NEXT:    call void @__kmpc_for_static_init_8(ptr @[[GLOB1:[0-9]+]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
  71 // CHECK-NEXT:    [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
  72 // CHECK-NEXT:    [[TMP5:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_2]], align 8
  73 // CHECK-NEXT:    [[CMP8:%.*]] = icmp sgt i64 [[TMP4]], [[TMP5]]
  74 // CHECK-NEXT:    br i1 [[CMP8]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
  75 // CHECK:       cond.true:
  76 // CHECK-NEXT:    [[TMP6:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_2]], align 8
  77 // CHECK-NEXT:    br label [[COND_END:%.*]]
  78 // CHECK:       cond.false:
  79 // CHECK-NEXT:    [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
  80 // CHECK-NEXT:    br label [[COND_END]]
  81 // CHECK:       cond.end:
  82 // CHECK-NEXT:    [[COND:%.*]] = phi i64 [ [[TMP6]], [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
  83 // CHECK-NEXT:    store i64 [[COND]], ptr [[DOTOMP_UB]], align 8
  84 // CHECK-NEXT:    [[TMP8:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
  85 // CHECK-NEXT:    store i64 [[TMP8]], ptr [[DOTOMP_IV]], align 8
  86 // CHECK-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
  87 // CHECK:       omp.inner.for.cond:
  88 // CHECK-NEXT:    [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
  89 // CHECK-NEXT:    [[TMP10:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
  90 // CHECK-NEXT:    [[CMP10:%.*]] = icmp sle i64 [[TMP9]], [[TMP10]]
  91 // CHECK-NEXT:    br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
  92 // CHECK:       omp.inner.for.body:
  93 // CHECK-NEXT:    [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
  94 // CHECK-NEXT:    [[DIV12:%.*]] = sdiv i64 [[TMP11]], 2
  95 // CHECK-NEXT:    [[MUL13:%.*]] = mul nsw i64 [[DIV12]], 1
  96 // CHECK-NEXT:    [[ADD:%.*]] = add nsw i64 0, [[MUL13]]
  97 // CHECK-NEXT:    [[CONV14:%.*]] = trunc i64 [[ADD]] to i32
  98 // CHECK-NEXT:    store i32 [[CONV14]], ptr [[I6]], align 4
  99 // CHECK-NEXT:    [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
 100 // CHECK-NEXT:    [[TMP13:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
 101 // CHECK-NEXT:    [[DIV15:%.*]] = sdiv i64 [[TMP13]], 2
 102 // CHECK-NEXT:    [[MUL16:%.*]] = mul nsw i64 [[DIV15]], 2
 103 // CHECK-NEXT:    [[SUB17:%.*]] = sub nsw i64 [[TMP12]], [[MUL16]]
 104 // CHECK-NEXT:    [[MUL18:%.*]] = mul nsw i64 [[SUB17]], 4
 105 // CHECK-NEXT:    [[ADD19:%.*]] = add nsw i64 0, [[MUL18]]
 106 // CHECK-NEXT:    [[CONV20:%.*]] = trunc i64 [[ADD19]] to i32
 107 // CHECK-NEXT:    store i32 [[CONV20]], ptr [[DOTUNROLLED_IV_J7]], align 4
 108 // CHECK-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTUNROLLED_IV_J7]], align 4
 109 // CHECK-NEXT:    store i32 [[TMP14]], ptr [[DOTUNROLL_INNER_IV_J]], align 4
 110 // CHECK-NEXT:    br label [[FOR_COND:%.*]]
 111 // CHECK:       for.cond:
 112 // CHECK-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTUNROLL_INNER_IV_J]], align 4
 113 // CHECK-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTUNROLLED_IV_J7]], align 4
 114 // CHECK-NEXT:    [[ADD21:%.*]] = add nsw i32 [[TMP16]], 4
 115 // CHECK-NEXT:    [[CMP22:%.*]] = icmp slt i32 [[TMP15]], [[ADD21]]
 116 // CHECK-NEXT:    br i1 [[CMP22]], label [[LAND_RHS:%.*]], label [[LAND_END:%.*]]
 117 // CHECK:       land.rhs:
 118 // CHECK-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTUNROLL_INNER_IV_J]], align 4
 119 // CHECK-NEXT:    [[CMP24:%.*]] = icmp slt i32 [[TMP17]], 8
 120 // CHECK-NEXT:    br label [[LAND_END]]
 121 // CHECK:       land.end:
 122 // CHECK-NEXT:    [[TMP18:%.*]] = phi i1 [ false, [[FOR_COND]] ], [ [[CMP24]], [[LAND_RHS]] ]
 123 // CHECK-NEXT:    br i1 [[TMP18]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
 124 // CHECK:       for.body:
 125 // CHECK-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTUNROLL_INNER_IV_J]], align 4
 126 // CHECK-NEXT:    [[MUL26:%.*]] = mul nsw i32 [[TMP19]], 1
 127 // CHECK-NEXT:    [[ADD27:%.*]] = add nsw i32 0, [[MUL26]]
 128 // CHECK-NEXT:    store i32 [[ADD27]], ptr [[J]], align 4
 129 // CHECK-NEXT:    [[TMP20:%.*]] = load ptr, ptr [[B_ADDR]], align 8
 130 // CHECK-NEXT:    [[TMP21:%.*]] = load i32, ptr [[I6]], align 4
 131 // CHECK-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP21]] to i64
 132 // CHECK-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP20]], i64 [[IDXPROM]]
 133 // CHECK-NEXT:    [[TMP22:%.*]] = load float, ptr [[ARRAYIDX]], align 4
 134 // CHECK-NEXT:    [[TMP23:%.*]] = load ptr, ptr [[C_ADDR]], align 8
 135 // CHECK-NEXT:    [[TMP24:%.*]] = load i32, ptr [[I6]], align 4
 136 // CHECK-NEXT:    [[IDXPROM28:%.*]] = sext i32 [[TMP24]] to i64
 137 // CHECK-NEXT:    [[ARRAYIDX29:%.*]] = getelementptr inbounds float, ptr [[TMP23]], i64 [[IDXPROM28]]
 138 // CHECK-NEXT:    [[TMP25:%.*]] = load float, ptr [[ARRAYIDX29]], align 4
 139 // CHECK-NEXT:    [[TMP26:%.*]] = load ptr, ptr [[D_ADDR]], align 8
 140 // CHECK-NEXT:    [[TMP27:%.*]] = load i32, ptr [[J]], align 4
 141 // CHECK-NEXT:    [[IDXPROM30:%.*]] = sext i32 [[TMP27]] to i64
 142 // CHECK-NEXT:    [[ARRAYIDX31:%.*]] = getelementptr inbounds float, ptr [[TMP26]], i64 [[IDXPROM30]]
 143 // CHECK-NEXT:    [[TMP28:%.*]] = load float, ptr [[ARRAYIDX31]], align 4
 144 // CHECK-NEXT:    [[MUL32:%.*]] = fmul float [[TMP25]], [[TMP28]]
 145 // CHECK-NEXT:    [[ADD33:%.*]] = fadd float [[TMP22]], [[MUL32]]
 146 // CHECK-NEXT:    [[TMP29:%.*]] = load ptr, ptr [[A_ADDR]], align 8
 147 // CHECK-NEXT:    [[TMP30:%.*]] = load i32, ptr [[I6]], align 4
 148 // CHECK-NEXT:    [[IDXPROM34:%.*]] = sext i32 [[TMP30]] to i64
 149 // CHECK-NEXT:    [[ARRAYIDX35:%.*]] = getelementptr inbounds float, ptr [[TMP29]], i64 [[IDXPROM34]]
 150 // CHECK-NEXT:    [[TMP31:%.*]] = load float, ptr [[ARRAYIDX35]], align 4
 151 // CHECK-NEXT:    [[ADD36:%.*]] = fadd float [[TMP31]], [[ADD33]]
 152 // CHECK-NEXT:    store float [[ADD36]], ptr [[ARRAYIDX35]], align 4
 153 // CHECK-NEXT:    br label [[FOR_INC:%.*]]
 154 // CHECK:       for.inc:
 155 // CHECK-NEXT:    [[TMP32:%.*]] = load i32, ptr [[DOTUNROLL_INNER_IV_J]], align 4
 156 // CHECK-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP32]], 1
 157 // CHECK-NEXT:    store i32 [[INC]], ptr [[DOTUNROLL_INNER_IV_J]], align 4
 158 // CHECK-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
 159 // CHECK:       for.end:
 160 // CHECK-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 161 // CHECK:       omp.body.continue:
 162 // CHECK-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 163 // CHECK:       omp.inner.for.inc:
 164 // CHECK-NEXT:    [[TMP33:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
 165 // CHECK-NEXT:    [[ADD37:%.*]] = add nsw i64 [[TMP33]], 1
 166 // CHECK-NEXT:    store i64 [[ADD37]], ptr [[DOTOMP_IV]], align 8
 167 // CHECK-NEXT:    br label [[OMP_INNER_FOR_COND]]
 168 // CHECK:       omp.inner.for.end:
 169 // CHECK-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
 170 // CHECK:       omp.loop.exit:
 171 // CHECK-NEXT:    [[OMP_GLOBAL_THREAD_NUM38:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB5:[0-9]+]])
 172 // CHECK-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM38]])
 173 // CHECK-NEXT:    br label [[OMP_PRECOND_END]]
 174 // CHECK:       omp.precond.end:
 175 // CHECK-NEXT:    [[OMP_GLOBAL_THREAD_NUM39:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB7:[0-9]+]])
 176 // CHECK-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB6:[0-9]+]], i32 [[OMP_GLOBAL_THREAD_NUM39]])
 177 // CHECK-NEXT:    ret void
 178 //