clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_codegen.cpp

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
   2 // Test target codegen - host bc file has to be created first.
   3 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc
   4 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK1
   5 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -fopenmp-optimistic-collapse -o - | FileCheck %s --check-prefix=CHECK2
   6 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple i386-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm-bc %s -o %t-x86-host.bc
   7 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK3
   8 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -fexceptions -fcxx-exceptions -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK3
   9
  10 // expected-no-diagnostics
  11 #ifndef HEADER
  12 #define HEADER
  13
  14 #define N 1000
  15 #define M 10
  16
  17 template<typename tx>
  18 tx ftemplate(int n) {
  19   tx a[N];
  20   short aa[N];
  21   tx b[10];
  22   tx c[M][M];
  23   tx f = n;
  24   tx l;
  25   int k;
  26   tx *v;
  27
  28 #pragma omp target teams distribute parallel for lastprivate(l) dist_schedule(static,128) schedule(static,32)
  29   for(int i = 0; i < n; i++) {
  30     a[i] = 1;
  31     l = i;
  32   }
  33
  34 #pragma omp target teams distribute parallel for map(tofrom: aa) num_teams(M) thread_limit(64)
  35   for(int i = 0; i < n; i++) {
  36     aa[i] += 1;
  37   }
  38
  39 #pragma omp target teams distribute parallel for map(tofrom:a, aa, b) if(target: n>40) proc_bind(spread)
  40   for(int i = 0; i < 10; i++) {
  41     b[i] += 1;
  42   }
  43
  44 #pragma omp target teams distribute parallel for collapse(2) firstprivate(f) private(k)
  45   for(int i = 0; i < M; i++) {
  46     for(int j = 0; j < M; j++) {
  47       k = M;
  48       c[i][j] = i + j * f + k;
  49     }
  50   }
  51
  52 #pragma omp target teams distribute parallel for collapse(2)
  53   for(int i = 0; i < n; i++) {
  54     for(int j = 0; j < n; j++) {
  55       c[i][j] = i + j;
  56     }
  57   }
  58
  59 #pragma omp target teams distribute parallel for map(a, v[:N])
  60   for(int i = 0; i < n; i++)
  61     a[i] = v[i];
  62   return a[0];
  63 }
  64
  65 int bar(int n){
  66   int a = 0;
  67
  68   a += ftemplate<int>(n);
  69
  70   return a;
  71 }
  72
  73 #endif
  74 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28
  75 // CHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 noundef [[L:%.*]]) #[[ATTR0:[0-9]+]] {
  76 // CHECK1-NEXT:  entry:
  77 // CHECK1-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
  78 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
  79 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
  80 // CHECK1-NEXT:    [[L_ADDR:%.*]] = alloca i64, align 8
  81 // CHECK1-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8
  82 // CHECK1-NEXT:    [[L_CASTED:%.*]] = alloca i64, align 8
  83 // CHECK1-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
  84 // CHECK1-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
  85 // CHECK1-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
  86 // CHECK1-NEXT:    store i64 [[N]], ptr [[N_ADDR]], align 8
  87 // CHECK1-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
  88 // CHECK1-NEXT:    store i64 [[L]], ptr [[L_ADDR]], align 8
  89 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
  90 // CHECK1-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28_kernel_environment, ptr [[DYN_PTR]])
  91 // CHECK1-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
  92 // CHECK1-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
  93 // CHECK1:       user_code.entry:
  94 // CHECK1-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
  95 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4
  96 // CHECK1-NEXT:    store i32 [[TMP3]], ptr [[N_CASTED]], align 4
  97 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8
  98 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[L_ADDR]], align 4
  99 // CHECK1-NEXT:    store i32 [[TMP5]], ptr [[L_CASTED]], align 4
 100 // CHECK1-NEXT:    [[TMP6:%.*]] = load i64, ptr [[L_CASTED]], align 8
 101 // CHECK1-NEXT:    store i32 0, ptr [[DOTZERO_ADDR]], align 4
 102 // CHECK1-NEXT:    store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4
 103 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i64 [[TMP4]], ptr [[TMP0]], i64 [[TMP6]]) #[[ATTR2:[0-9]+]]
 104 // CHECK1-NEXT:    call void @__kmpc_target_deinit()
 105 // CHECK1-NEXT:    ret void
 106 // CHECK1:       worker.exit:
 107 // CHECK1-NEXT:    ret void
 108 //
 109 //
 110 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28_omp_outlined
 111 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 noundef [[L:%.*]]) #[[ATTR1:[0-9]+]] {
 112 // CHECK1-NEXT:  entry:
 113 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 114 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 115 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
 116 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
 117 // CHECK1-NEXT:    [[L_ADDR:%.*]] = alloca i64, align 8
 118 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 119 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 120 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
 121 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
 122 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
 123 // CHECK1-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
 124 // CHECK1-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
 125 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 126 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 127 // CHECK1-NEXT:    [[I3:%.*]] = alloca i32, align 4
 128 // CHECK1-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8
 129 // CHECK1-NEXT:    [[L_CASTED:%.*]] = alloca i64, align 8
 130 // CHECK1-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [5 x ptr], align 8
 131 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 132 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 133 // CHECK1-NEXT:    store i64 [[N]], ptr [[N_ADDR]], align 8
 134 // CHECK1-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
 135 // CHECK1-NEXT:    store i64 [[L]], ptr [[L_ADDR]], align 8
 136 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
 137 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
 138 // CHECK1-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
 139 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
 140 // CHECK1-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
 141 // CHECK1-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1
 142 // CHECK1-NEXT:    [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
 143 // CHECK1-NEXT:    store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
 144 // CHECK1-NEXT:    store i32 0, ptr [[I]], align 4
 145 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
 146 // CHECK1-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]
 147 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
 148 // CHECK1:       omp.precond.then:
 149 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
 150 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
 151 // CHECK1-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_COMB_UB]], align 4
 152 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 153 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 154 // CHECK1-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 155 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
 156 // CHECK1-NEXT:    call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP6]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 128)
 157 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 158 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
 159 // CHECK1-NEXT:    [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]]
 160 // CHECK1-NEXT:    br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 161 // CHECK1:       cond.true:
 162 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
 163 // CHECK1-NEXT:    br label [[COND_END:%.*]]
 164 // CHECK1:       cond.false:
 165 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 166 // CHECK1-NEXT:    br label [[COND_END]]
 167 // CHECK1:       cond.end:
 168 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
 169 // CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
 170 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
 171 // CHECK1-NEXT:    store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 4
 172 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 173 // CHECK1:       omp.inner.for.cond:
 174 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 175 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
 176 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP13]], 1
 177 // CHECK1-NEXT:    [[CMP5:%.*]] = icmp slt i32 [[TMP12]], [[ADD]]
 178 // CHECK1-NEXT:    br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 179 // CHECK1:       omp.inner.for.body:
 180 // CHECK1-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
 181 // CHECK1-NEXT:    [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
 182 // CHECK1-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 183 // CHECK1-NEXT:    [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
 184 // CHECK1-NEXT:    [[TMP18:%.*]] = load i32, ptr [[N_ADDR]], align 4
 185 // CHECK1-NEXT:    store i32 [[TMP18]], ptr [[N_CASTED]], align 4
 186 // CHECK1-NEXT:    [[TMP19:%.*]] = load i64, ptr [[N_CASTED]], align 8
 187 // CHECK1-NEXT:    [[TMP20:%.*]] = load i32, ptr [[L_ADDR]], align 4
 188 // CHECK1-NEXT:    store i32 [[TMP20]], ptr [[L_CASTED]], align 4
 189 // CHECK1-NEXT:    [[TMP21:%.*]] = load i64, ptr [[L_CASTED]], align 8
 190 // CHECK1-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
 191 // CHECK1-NEXT:    [[TMP23:%.*]] = inttoptr i64 [[TMP15]] to ptr
 192 // CHECK1-NEXT:    store ptr [[TMP23]], ptr [[TMP22]], align 8
 193 // CHECK1-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
 194 // CHECK1-NEXT:    [[TMP25:%.*]] = inttoptr i64 [[TMP17]] to ptr
 195 // CHECK1-NEXT:    store ptr [[TMP25]], ptr [[TMP24]], align 8
 196 // CHECK1-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
 197 // CHECK1-NEXT:    [[TMP27:%.*]] = inttoptr i64 [[TMP19]] to ptr
 198 // CHECK1-NEXT:    store ptr [[TMP27]], ptr [[TMP26]], align 8
 199 // CHECK1-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3
 200 // CHECK1-NEXT:    store ptr [[TMP0]], ptr [[TMP28]], align 8
 201 // CHECK1-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 4
 202 // CHECK1-NEXT:    [[TMP30:%.*]] = inttoptr i64 [[TMP21]] to ptr
 203 // CHECK1-NEXT:    store ptr [[TMP30]], ptr [[TMP29]], align 8
 204 // CHECK1-NEXT:    [[TMP31:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 205 // CHECK1-NEXT:    [[TMP32:%.*]] = load i32, ptr [[TMP31]], align 4
 206 // CHECK1-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP32]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 5)
 207 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 208 // CHECK1:       omp.inner.for.inc:
 209 // CHECK1-NEXT:    [[TMP33:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 210 // CHECK1-NEXT:    [[TMP34:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
 211 // CHECK1-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP33]], [[TMP34]]
 212 // CHECK1-NEXT:    store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4
 213 // CHECK1-NEXT:    [[TMP35:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
 214 // CHECK1-NEXT:    [[TMP36:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
 215 // CHECK1-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP35]], [[TMP36]]
 216 // CHECK1-NEXT:    store i32 [[ADD7]], ptr [[DOTOMP_COMB_LB]], align 4
 217 // CHECK1-NEXT:    [[TMP37:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 218 // CHECK1-NEXT:    [[TMP38:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
 219 // CHECK1-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP37]], [[TMP38]]
 220 // CHECK1-NEXT:    store i32 [[ADD8]], ptr [[DOTOMP_COMB_UB]], align 4
 221 // CHECK1-NEXT:    [[TMP39:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 222 // CHECK1-NEXT:    [[TMP40:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
 223 // CHECK1-NEXT:    [[CMP9:%.*]] = icmp sgt i32 [[TMP39]], [[TMP40]]
 224 // CHECK1-NEXT:    br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]]
 225 // CHECK1:       cond.true10:
 226 // CHECK1-NEXT:    [[TMP41:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
 227 // CHECK1-NEXT:    br label [[COND_END12:%.*]]
 228 // CHECK1:       cond.false11:
 229 // CHECK1-NEXT:    [[TMP42:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 230 // CHECK1-NEXT:    br label [[COND_END12]]
 231 // CHECK1:       cond.end12:
 232 // CHECK1-NEXT:    [[COND13:%.*]] = phi i32 [ [[TMP41]], [[COND_TRUE10]] ], [ [[TMP42]], [[COND_FALSE11]] ]
 233 // CHECK1-NEXT:    store i32 [[COND13]], ptr [[DOTOMP_COMB_UB]], align 4
 234 // CHECK1-NEXT:    [[TMP43:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
 235 // CHECK1-NEXT:    store i32 [[TMP43]], ptr [[DOTOMP_IV]], align 4
 236 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]
 237 // CHECK1:       omp.inner.for.end:
 238 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
 239 // CHECK1:       omp.loop.exit:
 240 // CHECK1-NEXT:    [[TMP44:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 241 // CHECK1-NEXT:    [[TMP45:%.*]] = load i32, ptr [[TMP44]], align 4
 242 // CHECK1-NEXT:    call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP45]])
 243 // CHECK1-NEXT:    [[TMP46:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
 244 // CHECK1-NEXT:    [[TMP47:%.*]] = icmp ne i32 [[TMP46]], 0
 245 // CHECK1-NEXT:    br i1 [[TMP47]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
 246 // CHECK1:       .omp.lastprivate.then:
 247 // CHECK1-NEXT:    [[TMP48:%.*]] = load i32, ptr [[L_ADDR]], align 4
 248 // CHECK1-NEXT:    store i32 [[TMP48]], ptr [[L_ADDR]], align 4
 249 // CHECK1-NEXT:    br label [[DOTOMP_LASTPRIVATE_DONE]]
 250 // CHECK1:       .omp.lastprivate.done:
 251 // CHECK1-NEXT:    br label [[OMP_PRECOND_END]]
 252 // CHECK1:       omp.precond.end:
 253 // CHECK1-NEXT:    ret void
 254 //
 255 //
 256 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28_omp_outlined_omp_outlined
 257 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 noundef [[L:%.*]]) #[[ATTR1]] {
 258 // CHECK1-NEXT:  entry:
 259 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 260 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 261 // CHECK1-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
 262 // CHECK1-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
 263 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
 264 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
 265 // CHECK1-NEXT:    [[L_ADDR:%.*]] = alloca i64, align 8
 266 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 267 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 268 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
 269 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
 270 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
 271 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
 272 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
 273 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 274 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 275 // CHECK1-NEXT:    [[I4:%.*]] = alloca i32, align 4
 276 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 277 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 278 // CHECK1-NEXT:    store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
 279 // CHECK1-NEXT:    store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
 280 // CHECK1-NEXT:    store i64 [[N]], ptr [[N_ADDR]], align 8
 281 // CHECK1-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
 282 // CHECK1-NEXT:    store i64 [[L]], ptr [[L_ADDR]], align 8
 283 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
 284 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
 285 // CHECK1-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
 286 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
 287 // CHECK1-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
 288 // CHECK1-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1
 289 // CHECK1-NEXT:    [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
 290 // CHECK1-NEXT:    store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
 291 // CHECK1-NEXT:    store i32 0, ptr [[I]], align 4
 292 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
 293 // CHECK1-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]
 294 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
 295 // CHECK1:       omp.precond.then:
 296 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
 297 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
 298 // CHECK1-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4
 299 // CHECK1-NEXT:    [[TMP5:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
 300 // CHECK1-NEXT:    [[CONV:%.*]] = trunc i64 [[TMP5]] to i32
 301 // CHECK1-NEXT:    [[TMP6:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
 302 // CHECK1-NEXT:    [[CONV3:%.*]] = trunc i64 [[TMP6]] to i32
 303 // CHECK1-NEXT:    store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
 304 // CHECK1-NEXT:    store i32 [[CONV3]], ptr [[DOTOMP_UB]], align 4
 305 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 306 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 307 // CHECK1-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 308 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
 309 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB3:[0-9]+]], i32 [[TMP8]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 32)
 310 // CHECK1-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
 311 // CHECK1:       omp.dispatch.cond:
 312 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 313 // CHECK1-NEXT:    [[TMP10:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
 314 // CHECK1-NEXT:    [[CONV5:%.*]] = trunc i64 [[TMP10]] to i32
 315 // CHECK1-NEXT:    [[CMP6:%.*]] = icmp sgt i32 [[TMP9]], [[CONV5]]
 316 // CHECK1-NEXT:    br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 317 // CHECK1:       cond.true:
 318 // CHECK1-NEXT:    [[TMP11:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
 319 // CHECK1-NEXT:    [[CONV7:%.*]] = trunc i64 [[TMP11]] to i32
 320 // CHECK1-NEXT:    br label [[COND_END:%.*]]
 321 // CHECK1:       cond.false:
 322 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 323 // CHECK1-NEXT:    br label [[COND_END]]
 324 // CHECK1:       cond.end:
 325 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ [[CONV7]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
 326 // CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
 327 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
 328 // CHECK1-NEXT:    store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4
 329 // CHECK1-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 330 // CHECK1-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 331 // CHECK1-NEXT:    [[CMP8:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
 332 // CHECK1-NEXT:    br i1 [[CMP8]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
 333 // CHECK1:       omp.dispatch.body:
 334 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 335 // CHECK1:       omp.inner.for.cond:
 336 // CHECK1-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 337 // CHECK1-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 338 // CHECK1-NEXT:    [[CMP9:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
 339 // CHECK1-NEXT:    br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 340 // CHECK1:       omp.inner.for.body:
 341 // CHECK1-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 342 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
 343 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
 344 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[I4]], align 4
 345 // CHECK1-NEXT:    [[TMP19:%.*]] = load i32, ptr [[I4]], align 4
 346 // CHECK1-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64
 347 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]]
 348 // CHECK1-NEXT:    store i32 1, ptr [[ARRAYIDX]], align 4
 349 // CHECK1-NEXT:    [[TMP20:%.*]] = load i32, ptr [[I4]], align 4
 350 // CHECK1-NEXT:    store i32 [[TMP20]], ptr [[L_ADDR]], align 4
 351 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 352 // CHECK1:       omp.body.continue:
 353 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 354 // CHECK1:       omp.inner.for.inc:
 355 // CHECK1-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 356 // CHECK1-NEXT:    [[ADD10:%.*]] = add nsw i32 [[TMP21]], 1
 357 // CHECK1-NEXT:    store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4
 358 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]
 359 // CHECK1:       omp.inner.for.end:
 360 // CHECK1-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
 361 // CHECK1:       omp.dispatch.inc:
 362 // CHECK1-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
 363 // CHECK1-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
 364 // CHECK1-NEXT:    [[ADD11:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]
 365 // CHECK1-NEXT:    store i32 [[ADD11]], ptr [[DOTOMP_LB]], align 4
 366 // CHECK1-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 367 // CHECK1-NEXT:    [[TMP25:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
 368 // CHECK1-NEXT:    [[ADD12:%.*]] = add nsw i32 [[TMP24]], [[TMP25]]
 369 // CHECK1-NEXT:    store i32 [[ADD12]], ptr [[DOTOMP_UB]], align 4
 370 // CHECK1-NEXT:    br label [[OMP_DISPATCH_COND]]
 371 // CHECK1:       omp.dispatch.end:
 372 // CHECK1-NEXT:    [[TMP26:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 373 // CHECK1-NEXT:    [[TMP27:%.*]] = load i32, ptr [[TMP26]], align 4
 374 // CHECK1-NEXT:    call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP27]])
 375 // CHECK1-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
 376 // CHECK1-NEXT:    [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0
 377 // CHECK1-NEXT:    br i1 [[TMP29]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
 378 // CHECK1:       .omp.lastprivate.then:
 379 // CHECK1-NEXT:    [[TMP30:%.*]] = load i32, ptr [[L_ADDR]], align 4
 380 // CHECK1-NEXT:    store i32 [[TMP30]], ptr [[L_ADDR]], align 4
 381 // CHECK1-NEXT:    br label [[DOTOMP_LASTPRIVATE_DONE]]
 382 // CHECK1:       .omp.lastprivate.done:
 383 // CHECK1-NEXT:    br label [[OMP_PRECOND_END]]
 384 // CHECK1:       omp.precond.end:
 385 // CHECK1-NEXT:    ret void
 386 //
 387 //
 388 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34
 389 // CHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR4:[0-9]+]] {
 390 // CHECK1-NEXT:  entry:
 391 // CHECK1-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
 392 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
 393 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca ptr, align 8
 394 // CHECK1-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8
 395 // CHECK1-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
 396 // CHECK1-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
 397 // CHECK1-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
 398 // CHECK1-NEXT:    store i64 [[N]], ptr [[N_ADDR]], align 8
 399 // CHECK1-NEXT:    store ptr [[AA]], ptr [[AA_ADDR]], align 8
 400 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8
 401 // CHECK1-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_kernel_environment, ptr [[DYN_PTR]])
 402 // CHECK1-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
 403 // CHECK1-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
 404 // CHECK1:       user_code.entry:
 405 // CHECK1-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
 406 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4
 407 // CHECK1-NEXT:    store i32 [[TMP3]], ptr [[N_CASTED]], align 4
 408 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8
 409 // CHECK1-NEXT:    store i32 0, ptr [[DOTZERO_ADDR]], align 4
 410 // CHECK1-NEXT:    store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4
 411 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i64 [[TMP4]], ptr [[TMP0]]) #[[ATTR2]]
 412 // CHECK1-NEXT:    call void @__kmpc_target_deinit()
 413 // CHECK1-NEXT:    ret void
 414 // CHECK1:       worker.exit:
 415 // CHECK1-NEXT:    ret void
 416 //
 417 //
 418 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_omp_outlined
 419 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR1]] {
 420 // CHECK1-NEXT:  entry:
 421 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 422 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 423 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
 424 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca ptr, align 8
 425 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 426 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 427 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
 428 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
 429 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
 430 // CHECK1-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
 431 // CHECK1-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
 432 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 433 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 434 // CHECK1-NEXT:    [[I3:%.*]] = alloca i32, align 4
 435 // CHECK1-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8
 436 // CHECK1-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [4 x ptr], align 8
 437 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 438 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 439 // CHECK1-NEXT:    store i64 [[N]], ptr [[N_ADDR]], align 8
 440 // CHECK1-NEXT:    store ptr [[AA]], ptr [[AA_ADDR]], align 8
 441 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8
 442 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
 443 // CHECK1-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
 444 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
 445 // CHECK1-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
 446 // CHECK1-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1
 447 // CHECK1-NEXT:    [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
 448 // CHECK1-NEXT:    store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
 449 // CHECK1-NEXT:    store i32 0, ptr [[I]], align 4
 450 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
 451 // CHECK1-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]
 452 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
 453 // CHECK1:       omp.precond.then:
 454 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
 455 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
 456 // CHECK1-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_COMB_UB]], align 4
 457 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 458 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 459 // CHECK1-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
 460 // CHECK1-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 461 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
 462 // CHECK1-NEXT:    call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP6]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
 463 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 464 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
 465 // CHECK1-NEXT:    [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]]
 466 // CHECK1-NEXT:    br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 467 // CHECK1:       cond.true:
 468 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
 469 // CHECK1-NEXT:    br label [[COND_END:%.*]]
 470 // CHECK1:       cond.false:
 471 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 472 // CHECK1-NEXT:    br label [[COND_END]]
 473 // CHECK1:       cond.end:
 474 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
 475 // CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
 476 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
 477 // CHECK1-NEXT:    store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 4
 478 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 479 // CHECK1:       omp.inner.for.cond:
 480 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 481 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
 482 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP13]], 1
 483 // CHECK1-NEXT:    [[CMP5:%.*]] = icmp slt i32 [[TMP12]], [[ADD]]
 484 // CHECK1-NEXT:    br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 485 // CHECK1:       omp.inner.for.body:
 486 // CHECK1-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
 487 // CHECK1-NEXT:    [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
 488 // CHECK1-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 489 // CHECK1-NEXT:    [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
 490 // CHECK1-NEXT:    [[TMP18:%.*]] = load i32, ptr [[N_ADDR]], align 4
 491 // CHECK1-NEXT:    store i32 [[TMP18]], ptr [[N_CASTED]], align 4
 492 // CHECK1-NEXT:    [[TMP19:%.*]] = load i64, ptr [[N_CASTED]], align 8
 493 // CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
 494 // CHECK1-NEXT:    [[TMP21:%.*]] = inttoptr i64 [[TMP15]] to ptr
 495 // CHECK1-NEXT:    store ptr [[TMP21]], ptr [[TMP20]], align 8
 496 // CHECK1-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
 497 // CHECK1-NEXT:    [[TMP23:%.*]] = inttoptr i64 [[TMP17]] to ptr
 498 // CHECK1-NEXT:    store ptr [[TMP23]], ptr [[TMP22]], align 8
 499 // CHECK1-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
 500 // CHECK1-NEXT:    [[TMP25:%.*]] = inttoptr i64 [[TMP19]] to ptr
 501 // CHECK1-NEXT:    store ptr [[TMP25]], ptr [[TMP24]], align 8
 502 // CHECK1-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3
 503 // CHECK1-NEXT:    store ptr [[TMP0]], ptr [[TMP26]], align 8
 504 // CHECK1-NEXT:    [[TMP27:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 505 // CHECK1-NEXT:    [[TMP28:%.*]] = load i32, ptr [[TMP27]], align 4
 506 // CHECK1-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP28]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 4)
 507 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 508 // CHECK1:       omp.inner.for.inc:
 509 // CHECK1-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 510 // CHECK1-NEXT:    [[TMP30:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
 511 // CHECK1-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP29]], [[TMP30]]
 512 // CHECK1-NEXT:    store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4
 513 // CHECK1-NEXT:    [[TMP31:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
 514 // CHECK1-NEXT:    [[TMP32:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
 515 // CHECK1-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP31]], [[TMP32]]
 516 // CHECK1-NEXT:    store i32 [[ADD7]], ptr [[DOTOMP_COMB_LB]], align 4
 517 // CHECK1-NEXT:    [[TMP33:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 518 // CHECK1-NEXT:    [[TMP34:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
 519 // CHECK1-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP33]], [[TMP34]]
 520 // CHECK1-NEXT:    store i32 [[ADD8]], ptr [[DOTOMP_COMB_UB]], align 4
 521 // CHECK1-NEXT:    [[TMP35:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 522 // CHECK1-NEXT:    [[TMP36:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
 523 // CHECK1-NEXT:    [[CMP9:%.*]] = icmp sgt i32 [[TMP35]], [[TMP36]]
 524 // CHECK1-NEXT:    br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]]
 525 // CHECK1:       cond.true10:
 526 // CHECK1-NEXT:    [[TMP37:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
 527 // CHECK1-NEXT:    br label [[COND_END12:%.*]]
 528 // CHECK1:       cond.false11:
 529 // CHECK1-NEXT:    [[TMP38:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 530 // CHECK1-NEXT:    br label [[COND_END12]]
 531 // CHECK1:       cond.end12:
 532 // CHECK1-NEXT:    [[COND13:%.*]] = phi i32 [ [[TMP37]], [[COND_TRUE10]] ], [ [[TMP38]], [[COND_FALSE11]] ]
 533 // CHECK1-NEXT:    store i32 [[COND13]], ptr [[DOTOMP_COMB_UB]], align 4
 534 // CHECK1-NEXT:    [[TMP39:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
 535 // CHECK1-NEXT:    store i32 [[TMP39]], ptr [[DOTOMP_IV]], align 4
 536 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]
 537 // CHECK1:       omp.inner.for.end:
 538 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
 539 // CHECK1:       omp.loop.exit:
 540 // CHECK1-NEXT:    [[TMP40:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 541 // CHECK1-NEXT:    [[TMP41:%.*]] = load i32, ptr [[TMP40]], align 4
 542 // CHECK1-NEXT:    call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP41]])
 543 // CHECK1-NEXT:    br label [[OMP_PRECOND_END]]
 544 // CHECK1:       omp.precond.end:
 545 // CHECK1-NEXT:    ret void
 546 //
 547 //
 548 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_omp_outlined_omp_outlined
 549 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR1]] {
 550 // CHECK1-NEXT:  entry:
 551 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 552 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 553 // CHECK1-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
 554 // CHECK1-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
 555 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
 556 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca ptr, align 8
 557 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 558 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 559 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
 560 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
 561 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
 562 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
 563 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
 564 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 565 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 566 // CHECK1-NEXT:    [[I4:%.*]] = alloca i32, align 4
 567 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 568 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 569 // CHECK1-NEXT:    store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
 570 // CHECK1-NEXT:    store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
 571 // CHECK1-NEXT:    store i64 [[N]], ptr [[N_ADDR]], align 8
 572 // CHECK1-NEXT:    store ptr [[AA]], ptr [[AA_ADDR]], align 8
 573 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8
 574 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
 575 // CHECK1-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
 576 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
 577 // CHECK1-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
 578 // CHECK1-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1
 579 // CHECK1-NEXT:    [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
 580 // CHECK1-NEXT:    store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
 581 // CHECK1-NEXT:    store i32 0, ptr [[I]], align 4
 582 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
 583 // CHECK1-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]
 584 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
 585 // CHECK1:       omp.precond.then:
 586 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
 587 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
 588 // CHECK1-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4
 589 // CHECK1-NEXT:    [[TMP5:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
 590 // CHECK1-NEXT:    [[CONV:%.*]] = trunc i64 [[TMP5]] to i32
 591 // CHECK1-NEXT:    [[TMP6:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
 592 // CHECK1-NEXT:    [[CONV3:%.*]] = trunc i64 [[TMP6]] to i32
 593 // CHECK1-NEXT:    store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
 594 // CHECK1-NEXT:    store i32 [[CONV3]], ptr [[DOTOMP_UB]], align 4
 595 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 596 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 597 // CHECK1-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 598 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
 599 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP8]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
 600 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
 601 // CHECK1-NEXT:    store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4
 602 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 603 // CHECK1:       omp.inner.for.cond:
 604 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 605 // CHECK1-NEXT:    [[CONV5:%.*]] = sext i32 [[TMP10]] to i64
 606 // CHECK1-NEXT:    [[TMP11:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
 607 // CHECK1-NEXT:    [[CMP6:%.*]] = icmp ule i64 [[CONV5]], [[TMP11]]
 608 // CHECK1-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 609 // CHECK1:       omp.inner.for.body:
 610 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 611 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
 612 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
 613 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[I4]], align 4
 614 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, ptr [[I4]], align 4
 615 // CHECK1-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64
 616 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], ptr [[TMP0]], i64 0, i64 [[IDXPROM]]
 617 // CHECK1-NEXT:    [[TMP14:%.*]] = load i16, ptr [[ARRAYIDX]], align 2
 618 // CHECK1-NEXT:    [[CONV7:%.*]] = sext i16 [[TMP14]] to i32
 619 // CHECK1-NEXT:    [[ADD8:%.*]] = add nsw i32 [[CONV7]], 1
 620 // CHECK1-NEXT:    [[CONV9:%.*]] = trunc i32 [[ADD8]] to i16
 621 // CHECK1-NEXT:    store i16 [[CONV9]], ptr [[ARRAYIDX]], align 2
 622 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 623 // CHECK1:       omp.body.continue:
 624 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 625 // CHECK1:       omp.inner.for.inc:
 626 // CHECK1-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 627 // CHECK1-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
 628 // CHECK1-NEXT:    [[ADD10:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
 629 // CHECK1-NEXT:    store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4
 630 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]
 631 // CHECK1:       omp.inner.for.end:
 632 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
 633 // CHECK1:       omp.loop.exit:
 634 // CHECK1-NEXT:    [[TMP17:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 635 // CHECK1-NEXT:    [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 4
 636 // CHECK1-NEXT:    call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP18]])
 637 // CHECK1-NEXT:    br label [[OMP_PRECOND_END]]
 638 // CHECK1:       omp.precond.end:
 639 // CHECK1-NEXT:    ret void
 640 //
 641 //
 642 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l39
 643 // CHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
 644 // CHECK1-NEXT:  entry:
 645 // CHECK1-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
 646 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
 647 // CHECK1-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
 648 // CHECK1-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
 649 // CHECK1-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
 650 // CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
 651 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
 652 // CHECK1-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l39_kernel_environment, ptr [[DYN_PTR]])
 653 // CHECK1-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
 654 // CHECK1-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
 655 // CHECK1:       user_code.entry:
 656 // CHECK1-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
 657 // CHECK1-NEXT:    store i32 0, ptr [[DOTZERO_ADDR]], align 4
 658 // CHECK1-NEXT:    store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4
 659 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l39_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]]) #[[ATTR2]]
 660 // CHECK1-NEXT:    call void @__kmpc_target_deinit()
 661 // CHECK1-NEXT:    ret void
 662 // CHECK1:       worker.exit:
 663 // CHECK1-NEXT:    ret void
 664 //
 665 //
 666 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l39_omp_outlined
 667 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
 668 // CHECK1-NEXT:  entry:
 669 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 670 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 671 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
 672 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 673 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 674 // CHECK1-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
 675 // CHECK1-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
 676 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 677 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 678 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
 679 // CHECK1-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x ptr], align 8
 680 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 681 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 682 // CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
 683 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
 684 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
 685 // CHECK1-NEXT:    store i32 9, ptr [[DOTOMP_COMB_UB]], align 4
 686 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 687 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 688 // CHECK1-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
 689 // CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 690 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
 691 // CHECK1-NEXT:    call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP2]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
 692 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 693 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
 694 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 695 // CHECK1:       cond.true:
 696 // CHECK1-NEXT:    br label [[COND_END:%.*]]
 697 // CHECK1:       cond.false:
 698 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 699 // CHECK1-NEXT:    br label [[COND_END]]
 700 // CHECK1:       cond.end:
 701 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
 702 // CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
 703 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
 704 // CHECK1-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
 705 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 706 // CHECK1:       omp.inner.for.cond:
 707 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 708 // CHECK1-NEXT:    [[CMP1:%.*]] = icmp slt i32 [[TMP6]], 10
 709 // CHECK1-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 710 // CHECK1:       omp.inner.for.body:
 711 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
 712 // CHECK1-NEXT:    [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
 713 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 714 // CHECK1-NEXT:    [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
 715 // CHECK1-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
 716 // CHECK1-NEXT:    [[TMP12:%.*]] = inttoptr i64 [[TMP8]] to ptr
 717 // CHECK1-NEXT:    store ptr [[TMP12]], ptr [[TMP11]], align 8
 718 // CHECK1-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
 719 // CHECK1-NEXT:    [[TMP14:%.*]] = inttoptr i64 [[TMP10]] to ptr
 720 // CHECK1-NEXT:    store ptr [[TMP14]], ptr [[TMP13]], align 8
 721 // CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
 722 // CHECK1-NEXT:    store ptr [[TMP0]], ptr [[TMP15]], align 8
 723 // CHECK1-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l39_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 3)
 724 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 725 // CHECK1:       omp.inner.for.inc:
 726 // CHECK1-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 727 // CHECK1-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
 728 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
 729 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
 730 // CHECK1-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
 731 // CHECK1-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
 732 // CHECK1-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
 733 // CHECK1-NEXT:    store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4
 734 // CHECK1-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 735 // CHECK1-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
 736 // CHECK1-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]
 737 // CHECK1-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4
 738 // CHECK1-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 739 // CHECK1-NEXT:    [[CMP4:%.*]] = icmp sgt i32 [[TMP22]], 9
 740 // CHECK1-NEXT:    br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
 741 // CHECK1:       cond.true5:
 742 // CHECK1-NEXT:    br label [[COND_END7:%.*]]
 743 // CHECK1:       cond.false6:
 744 // CHECK1-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 745 // CHECK1-NEXT:    br label [[COND_END7]]
 746 // CHECK1:       cond.end7:
 747 // CHECK1-NEXT:    [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP23]], [[COND_FALSE6]] ]
 748 // CHECK1-NEXT:    store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4
 749 // CHECK1-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
 750 // CHECK1-NEXT:    store i32 [[TMP24]], ptr [[DOTOMP_IV]], align 4
 751 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]
 752 // CHECK1:       omp.inner.for.end:
 753 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
 754 // CHECK1:       omp.loop.exit:
 755 // CHECK1-NEXT:    call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP2]])
 756 // CHECK1-NEXT:    ret void
 757 //
 758 //
 759 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l39_omp_outlined_omp_outlined
 760 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
 761 // CHECK1-NEXT:  entry:
 762 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 763 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 764 // CHECK1-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
 765 // CHECK1-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
 766 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
 767 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 768 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 769 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
 770 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
 771 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 772 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 773 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
 774 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 775 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 776 // CHECK1-NEXT:    store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
 777 // CHECK1-NEXT:    store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
 778 // CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
 779 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
 780 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
 781 // CHECK1-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4
 782 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
 783 // CHECK1-NEXT:    [[CONV:%.*]] = trunc i64 [[TMP1]] to i32
 784 // CHECK1-NEXT:    [[TMP2:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
 785 // CHECK1-NEXT:    [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32
 786 // CHECK1-NEXT:    store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
 787 // CHECK1-NEXT:    store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4
 788 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 789 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 790 // CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 791 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
 792 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP4]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
 793 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
 794 // CHECK1-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
 795 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 796 // CHECK1:       omp.inner.for.cond:
 797 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 798 // CHECK1-NEXT:    [[CONV2:%.*]] = sext i32 [[TMP6]] to i64
 799 // CHECK1-NEXT:    [[TMP7:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
 800 // CHECK1-NEXT:    [[CMP:%.*]] = icmp ule i64 [[CONV2]], [[TMP7]]
 801 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 802 // CHECK1:       omp.inner.for.body:
 803 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 804 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
 805 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
 806 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[I]], align 4
 807 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[I]], align 4
 808 // CHECK1-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64
 809 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]]
 810 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
 811 // CHECK1-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
 812 // CHECK1-NEXT:    store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4
 813 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 814 // CHECK1:       omp.body.continue:
 815 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 816 // CHECK1:       omp.inner.for.inc:
 817 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 818 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
 819 // CHECK1-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
 820 // CHECK1-NEXT:    store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4
 821 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]
 822 // CHECK1:       omp.inner.for.end:
 823 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
 824 // CHECK1:       omp.loop.exit:
 825 // CHECK1-NEXT:    call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP4]])
 826 // CHECK1-NEXT:    ret void
 827 //
 828 //
 829 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l44
 830 // CHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i64 noundef [[F:%.*]]) #[[ATTR0]] {
 831 // CHECK1-NEXT:  entry:
 832 // CHECK1-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
 833 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
 834 // CHECK1-NEXT:    [[F_ADDR:%.*]] = alloca i64, align 8
 835 // CHECK1-NEXT:    [[F_CASTED:%.*]] = alloca i64, align 8
 836 // CHECK1-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
 837 // CHECK1-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
 838 // CHECK1-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
 839 // CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
 840 // CHECK1-NEXT:    store i64 [[F]], ptr [[F_ADDR]], align 8
 841 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8
 842 // CHECK1-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l44_kernel_environment, ptr [[DYN_PTR]])
 843 // CHECK1-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
 844 // CHECK1-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
 845 // CHECK1:       user_code.entry:
 846 // CHECK1-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
 847 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[F_ADDR]], align 4
 848 // CHECK1-NEXT:    store i32 [[TMP3]], ptr [[F_CASTED]], align 4
 849 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, ptr [[F_CASTED]], align 8
 850 // CHECK1-NEXT:    store i32 0, ptr [[DOTZERO_ADDR]], align 4
 851 // CHECK1-NEXT:    store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4
 852 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l44_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]], i64 [[TMP4]]) #[[ATTR2]]
 853 // CHECK1-NEXT:    call void @__kmpc_target_deinit()
 854 // CHECK1-NEXT:    ret void
 855 // CHECK1:       worker.exit:
 856 // CHECK1-NEXT:    ret void
 857 //
 858 //
 859 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l44_omp_outlined
 860 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i64 noundef [[F:%.*]]) #[[ATTR1]] {
 861 // CHECK1-NEXT:  entry:
 862 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 863 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 864 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
 865 // CHECK1-NEXT:    [[F_ADDR:%.*]] = alloca i64, align 8
 866 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 867 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 868 // CHECK1-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
 869 // CHECK1-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
 870 // CHECK1-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
 871 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 872 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 873 // CHECK1-NEXT:    [[K:%.*]] = alloca i32, align 4
 874 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
 875 // CHECK1-NEXT:    [[J:%.*]] = alloca i32, align 4
 876 // CHECK1-NEXT:    [[F_CASTED:%.*]] = alloca i64, align 8
 877 // CHECK1-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [4 x ptr], align 8
 878 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 879 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 880 // CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
 881 // CHECK1-NEXT:    store i64 [[F]], ptr [[F_ADDR]], align 8
 882 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8
 883 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
 884 // CHECK1-NEXT:    store i32 99, ptr [[DOTOMP_COMB_UB]], align 4
 885 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 886 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 887 // CHECK1-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
 888 // CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 889 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
 890 // CHECK1-NEXT:    call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP2]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
 891 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 892 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 99
 893 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 894 // CHECK1:       cond.true:
 895 // CHECK1-NEXT:    br label [[COND_END:%.*]]
 896 // CHECK1:       cond.false:
 897 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 898 // CHECK1-NEXT:    br label [[COND_END]]
 899 // CHECK1:       cond.end:
 900 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
 901 // CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
 902 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
 903 // CHECK1-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
 904 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 905 // CHECK1:       omp.inner.for.cond:
 906 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 907 // CHECK1-NEXT:    [[CMP2:%.*]] = icmp slt i32 [[TMP6]], 100
 908 // CHECK1-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 909 // CHECK1:       omp.inner.for.body:
 910 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
 911 // CHECK1-NEXT:    [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
 912 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 913 // CHECK1-NEXT:    [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
 914 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[F_ADDR]], align 4
 915 // CHECK1-NEXT:    store i32 [[TMP11]], ptr [[F_CASTED]], align 4
 916 // CHECK1-NEXT:    [[TMP12:%.*]] = load i64, ptr [[F_CASTED]], align 8
 917 // CHECK1-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
 918 // CHECK1-NEXT:    [[TMP14:%.*]] = inttoptr i64 [[TMP8]] to ptr
 919 // CHECK1-NEXT:    store ptr [[TMP14]], ptr [[TMP13]], align 8
 920 // CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
 921 // CHECK1-NEXT:    [[TMP16:%.*]] = inttoptr i64 [[TMP10]] to ptr
 922 // CHECK1-NEXT:    store ptr [[TMP16]], ptr [[TMP15]], align 8
 923 // CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
 924 // CHECK1-NEXT:    store ptr [[TMP0]], ptr [[TMP17]], align 8
 925 // CHECK1-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3
 926 // CHECK1-NEXT:    [[TMP19:%.*]] = inttoptr i64 [[TMP12]] to ptr
 927 // CHECK1-NEXT:    store ptr [[TMP19]], ptr [[TMP18]], align 8
 928 // CHECK1-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l44_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 4)
 929 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 930 // CHECK1:       omp.inner.for.inc:
 931 // CHECK1-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 932 // CHECK1-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
 933 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]
 934 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
 935 // CHECK1-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
 936 // CHECK1-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
 937 // CHECK1-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]
 938 // CHECK1-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_COMB_LB]], align 4
 939 // CHECK1-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 940 // CHECK1-NEXT:    [[TMP25:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
 941 // CHECK1-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP24]], [[TMP25]]
 942 // CHECK1-NEXT:    store i32 [[ADD4]], ptr [[DOTOMP_COMB_UB]], align 4
 943 // CHECK1-NEXT:    [[TMP26:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 944 // CHECK1-NEXT:    [[CMP5:%.*]] = icmp sgt i32 [[TMP26]], 99
 945 // CHECK1-NEXT:    br i1 [[CMP5]], label [[COND_TRUE6:%.*]], label [[COND_FALSE7:%.*]]
 946 // CHECK1:       cond.true6:
 947 // CHECK1-NEXT:    br label [[COND_END8:%.*]]
 948 // CHECK1:       cond.false7:
 949 // CHECK1-NEXT:    [[TMP27:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 950 // CHECK1-NEXT:    br label [[COND_END8]]
 951 // CHECK1:       cond.end8:
 952 // CHECK1-NEXT:    [[COND9:%.*]] = phi i32 [ 99, [[COND_TRUE6]] ], [ [[TMP27]], [[COND_FALSE7]] ]
 953 // CHECK1-NEXT:    store i32 [[COND9]], ptr [[DOTOMP_COMB_UB]], align 4
 954 // CHECK1-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
 955 // CHECK1-NEXT:    store i32 [[TMP28]], ptr [[DOTOMP_IV]], align 4
 956 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]
 957 // CHECK1:       omp.inner.for.end:
 958 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
 959 // CHECK1:       omp.loop.exit:
 960 // CHECK1-NEXT:    call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP2]])
 961 // CHECK1-NEXT:    ret void
 962 //
 963 //
 964 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l44_omp_outlined_omp_outlined
 965 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i64 noundef [[F:%.*]]) #[[ATTR1]] {
 966 // CHECK1-NEXT:  entry:
 967 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 968 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 969 // CHECK1-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
 970 // CHECK1-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
 971 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
 972 // CHECK1-NEXT:    [[F_ADDR:%.*]] = alloca i64, align 8
 973 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 974 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 975 // CHECK1-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
 976 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
 977 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
 978 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 979 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 980 // CHECK1-NEXT:    [[K:%.*]] = alloca i32, align 4
 981 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
 982 // CHECK1-NEXT:    [[J:%.*]] = alloca i32, align 4
 983 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 984 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 985 // CHECK1-NEXT:    store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
 986 // CHECK1-NEXT:    store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
 987 // CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
 988 // CHECK1-NEXT:    store i64 [[F]], ptr [[F_ADDR]], align 8
 989 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8
 990 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
 991 // CHECK1-NEXT:    store i32 99, ptr [[DOTOMP_UB]], align 4
 992 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
 993 // CHECK1-NEXT:    [[CONV:%.*]] = trunc i64 [[TMP1]] to i32
 994 // CHECK1-NEXT:    [[TMP2:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
 995 // CHECK1-NEXT:    [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32
 996 // CHECK1-NEXT:    store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
 997 // CHECK1-NEXT:    store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4
 998 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 999 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1000 // CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1001 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
1002 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP4]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
1003 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1004 // CHECK1-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
1005 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1006 // CHECK1:       omp.inner.for.cond:
1007 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1008 // CHECK1-NEXT:    [[CONV3:%.*]] = sext i32 [[TMP6]] to i64
1009 // CHECK1-NEXT:    [[TMP7:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
1010 // CHECK1-NEXT:    [[CMP:%.*]] = icmp ule i64 [[CONV3]], [[TMP7]]
1011 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1012 // CHECK1:       omp.inner.for.body:
1013 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1014 // CHECK1-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP8]], 10
1015 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
1016 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1017 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[I]], align 4
1018 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1019 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1020 // CHECK1-NEXT:    [[DIV4:%.*]] = sdiv i32 [[TMP10]], 10
1021 // CHECK1-NEXT:    [[MUL5:%.*]] = mul nsw i32 [[DIV4]], 10
1022 // CHECK1-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL5]]
1023 // CHECK1-NEXT:    [[MUL6:%.*]] = mul nsw i32 [[SUB]], 1
1024 // CHECK1-NEXT:    [[ADD7:%.*]] = add nsw i32 0, [[MUL6]]
1025 // CHECK1-NEXT:    store i32 [[ADD7]], ptr [[J]], align 4
1026 // CHECK1-NEXT:    store i32 10, ptr [[K]], align 4
1027 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 4
1028 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[J]], align 4
1029 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, ptr [[F_ADDR]], align 4
1030 // CHECK1-NEXT:    [[MUL8:%.*]] = mul nsw i32 [[TMP12]], [[TMP13]]
1031 // CHECK1-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP11]], [[MUL8]]
1032 // CHECK1-NEXT:    [[TMP14:%.*]] = load i32, ptr [[K]], align 4
1033 // CHECK1-NEXT:    [[ADD10:%.*]] = add nsw i32 [[ADD9]], [[TMP14]]
1034 // CHECK1-NEXT:    [[TMP15:%.*]] = load i32, ptr [[I]], align 4
1035 // CHECK1-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64
1036 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP0]], i64 0, i64 [[IDXPROM]]
1037 // CHECK1-NEXT:    [[TMP16:%.*]] = load i32, ptr [[J]], align 4
1038 // CHECK1-NEXT:    [[IDXPROM11:%.*]] = sext i32 [[TMP16]] to i64
1039 // CHECK1-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM11]]
1040 // CHECK1-NEXT:    store i32 [[ADD10]], ptr [[ARRAYIDX12]], align 4
1041 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1042 // CHECK1:       omp.body.continue:
1043 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1044 // CHECK1:       omp.inner.for.inc:
1045 // CHECK1-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1046 // CHECK1-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
1047 // CHECK1-NEXT:    [[ADD13:%.*]] = add nsw i32 [[TMP17]], [[TMP18]]
1048 // CHECK1-NEXT:    store i32 [[ADD13]], ptr [[DOTOMP_IV]], align 4
1049 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]
1050 // CHECK1:       omp.inner.for.end:
1051 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1052 // CHECK1:       omp.loop.exit:
1053 // CHECK1-NEXT:    call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP4]])
1054 // CHECK1-NEXT:    ret void
1055 //
1056 //
1057 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l52
1058 // CHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR0]] {
1059 // CHECK1-NEXT:  entry:
1060 // CHECK1-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
1061 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
1062 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
1063 // CHECK1-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8
1064 // CHECK1-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
1065 // CHECK1-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
1066 // CHECK1-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
1067 // CHECK1-NEXT:    store i64 [[N]], ptr [[N_ADDR]], align 8
1068 // CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
1069 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8
1070 // CHECK1-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l52_kernel_environment, ptr [[DYN_PTR]])
1071 // CHECK1-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
1072 // CHECK1-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
1073 // CHECK1:       user_code.entry:
1074 // CHECK1-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
1075 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4
1076 // CHECK1-NEXT:    store i32 [[TMP3]], ptr [[N_CASTED]], align 4
1077 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8
1078 // CHECK1-NEXT:    store i32 0, ptr [[DOTZERO_ADDR]], align 4
1079 // CHECK1-NEXT:    store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4
1080 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l52_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i64 [[TMP4]], ptr [[TMP0]]) #[[ATTR2]]
1081 // CHECK1-NEXT:    call void @__kmpc_target_deinit()
1082 // CHECK1-NEXT:    ret void
1083 // CHECK1:       worker.exit:
1084 // CHECK1-NEXT:    ret void
1085 //
1086 //
1087 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l52_omp_outlined
1088 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR1]] {
1089 // CHECK1-NEXT:  entry:
1090 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1091 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1092 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
1093 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
1094 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
1095 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1096 // CHECK1-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
1097 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
1098 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
1099 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8
1100 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
1101 // CHECK1-NEXT:    [[J:%.*]] = alloca i32, align 4
1102 // CHECK1-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i64, align 8
1103 // CHECK1-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i64, align 8
1104 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
1105 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1106 // CHECK1-NEXT:    [[I9:%.*]] = alloca i32, align 4
1107 // CHECK1-NEXT:    [[J10:%.*]] = alloca i32, align 4
1108 // CHECK1-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8
1109 // CHECK1-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [4 x ptr], align 8
1110 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1111 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1112 // CHECK1-NEXT:    store i64 [[N]], ptr [[N_ADDR]], align 8
1113 // CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
1114 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8
1115 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
1116 // CHECK1-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
1117 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
1118 // CHECK1-NEXT:    store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_2]], align 4
1119 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1120 // CHECK1-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
1121 // CHECK1-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1
1122 // CHECK1-NEXT:    [[CONV:%.*]] = sext i32 [[DIV]] to i64
1123 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
1124 // CHECK1-NEXT:    [[SUB4:%.*]] = sub nsw i32 [[TMP4]], 0
1125 // CHECK1-NEXT:    [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1
1126 // CHECK1-NEXT:    [[CONV6:%.*]] = sext i32 [[DIV5]] to i64
1127 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]]
1128 // CHECK1-NEXT:    [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1
1129 // CHECK1-NEXT:    store i64 [[SUB7]], ptr [[DOTCAPTURE_EXPR_3]], align 8
1130 // CHECK1-NEXT:    store i32 0, ptr [[I]], align 4
1131 // CHECK1-NEXT:    store i32 0, ptr [[J]], align 4
1132 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1133 // CHECK1-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP5]]
1134 // CHECK1-NEXT:    br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]]
1135 // CHECK1:       land.lhs.true:
1136 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
1137 // CHECK1-NEXT:    [[CMP8:%.*]] = icmp slt i32 0, [[TMP6]]
1138 // CHECK1-NEXT:    br i1 [[CMP8]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]]
1139 // CHECK1:       omp.precond.then:
1140 // CHECK1-NEXT:    store i64 0, ptr [[DOTOMP_COMB_LB]], align 8
1141 // CHECK1-NEXT:    [[TMP7:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_3]], align 8
1142 // CHECK1-NEXT:    store i64 [[TMP7]], ptr [[DOTOMP_COMB_UB]], align 8
1143 // CHECK1-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8
1144 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1145 // CHECK1-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
1146 // CHECK1-NEXT:    [[CONV11:%.*]] = zext i32 [[NVPTX_NUM_THREADS]] to i64
1147 // CHECK1-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1148 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
1149 // CHECK1-NEXT:    call void @__kmpc_distribute_static_init_8(ptr @[[GLOB2]], i32 [[TMP9]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 [[CONV11]])
1150 // CHECK1-NEXT:    [[TMP10:%.*]] = load i64, ptr [[DOTOMP_COMB_UB]], align 8
1151 // CHECK1-NEXT:    [[TMP11:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_3]], align 8
1152 // CHECK1-NEXT:    [[CMP12:%.*]] = icmp sgt i64 [[TMP10]], [[TMP11]]
1153 // CHECK1-NEXT:    br i1 [[CMP12]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1154 // CHECK1:       cond.true:
1155 // CHECK1-NEXT:    [[TMP12:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_3]], align 8
1156 // CHECK1-NEXT:    br label [[COND_END:%.*]]
1157 // CHECK1:       cond.false:
1158 // CHECK1-NEXT:    [[TMP13:%.*]] = load i64, ptr [[DOTOMP_COMB_UB]], align 8
1159 // CHECK1-NEXT:    br label [[COND_END]]
1160 // CHECK1:       cond.end:
1161 // CHECK1-NEXT:    [[COND:%.*]] = phi i64 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ]
1162 // CHECK1-NEXT:    store i64 [[COND]], ptr [[DOTOMP_COMB_UB]], align 8
1163 // CHECK1-NEXT:    [[TMP14:%.*]] = load i64, ptr [[DOTOMP_COMB_LB]], align 8
1164 // CHECK1-NEXT:    store i64 [[TMP14]], ptr [[DOTOMP_IV]], align 8
1165 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1166 // CHECK1:       omp.inner.for.cond:
1167 // CHECK1-NEXT:    [[TMP15:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
1168 // CHECK1-NEXT:    [[TMP16:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_3]], align 8
1169 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i64 [[TMP16]], 1
1170 // CHECK1-NEXT:    [[CMP13:%.*]] = icmp slt i64 [[TMP15]], [[ADD]]
1171 // CHECK1-NEXT:    br i1 [[CMP13]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1172 // CHECK1:       omp.inner.for.body:
1173 // CHECK1-NEXT:    [[TMP17:%.*]] = load i64, ptr [[DOTOMP_COMB_LB]], align 8
1174 // CHECK1-NEXT:    [[TMP18:%.*]] = load i64, ptr [[DOTOMP_COMB_UB]], align 8
1175 // CHECK1-NEXT:    [[TMP19:%.*]] = load i32, ptr [[N_ADDR]], align 4
1176 // CHECK1-NEXT:    store i32 [[TMP19]], ptr [[N_CASTED]], align 4
1177 // CHECK1-NEXT:    [[TMP20:%.*]] = load i64, ptr [[N_CASTED]], align 8
1178 // CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
1179 // CHECK1-NEXT:    [[TMP22:%.*]] = inttoptr i64 [[TMP17]] to ptr
1180 // CHECK1-NEXT:    store ptr [[TMP22]], ptr [[TMP21]], align 8
1181 // CHECK1-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
1182 // CHECK1-NEXT:    [[TMP24:%.*]] = inttoptr i64 [[TMP18]] to ptr
1183 // CHECK1-NEXT:    store ptr [[TMP24]], ptr [[TMP23]], align 8
1184 // CHECK1-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
1185 // CHECK1-NEXT:    [[TMP26:%.*]] = inttoptr i64 [[TMP20]] to ptr
1186 // CHECK1-NEXT:    store ptr [[TMP26]], ptr [[TMP25]], align 8
1187 // CHECK1-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3
1188 // CHECK1-NEXT:    store ptr [[TMP0]], ptr [[TMP27]], align 8
1189 // CHECK1-NEXT:    [[TMP28:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1190 // CHECK1-NEXT:    [[TMP29:%.*]] = load i32, ptr [[TMP28]], align 4
1191 // CHECK1-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP29]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l52_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 4)
1192 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1193 // CHECK1:       omp.inner.for.inc:
1194 // CHECK1-NEXT:    [[TMP30:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
1195 // CHECK1-NEXT:    [[TMP31:%.*]] = load i64, ptr [[DOTOMP_STRIDE]], align 8
1196 // CHECK1-NEXT:    [[ADD14:%.*]] = add nsw i64 [[TMP30]], [[TMP31]]
1197 // CHECK1-NEXT:    store i64 [[ADD14]], ptr [[DOTOMP_IV]], align 8
1198 // CHECK1-NEXT:    [[TMP32:%.*]] = load i64, ptr [[DOTOMP_COMB_LB]], align 8
1199 // CHECK1-NEXT:    [[TMP33:%.*]] = load i64, ptr [[DOTOMP_STRIDE]], align 8
1200 // CHECK1-NEXT:    [[ADD15:%.*]] = add nsw i64 [[TMP32]], [[TMP33]]
1201 // CHECK1-NEXT:    store i64 [[ADD15]], ptr [[DOTOMP_COMB_LB]], align 8
1202 // CHECK1-NEXT:    [[TMP34:%.*]] = load i64, ptr [[DOTOMP_COMB_UB]], align 8
1203 // CHECK1-NEXT:    [[TMP35:%.*]] = load i64, ptr [[DOTOMP_STRIDE]], align 8
1204 // CHECK1-NEXT:    [[ADD16:%.*]] = add nsw i64 [[TMP34]], [[TMP35]]
1205 // CHECK1-NEXT:    store i64 [[ADD16]], ptr [[DOTOMP_COMB_UB]], align 8
1206 // CHECK1-NEXT:    [[TMP36:%.*]] = load i64, ptr [[DOTOMP_COMB_UB]], align 8
1207 // CHECK1-NEXT:    [[TMP37:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_3]], align 8
1208 // CHECK1-NEXT:    [[CMP17:%.*]] = icmp sgt i64 [[TMP36]], [[TMP37]]
1209 // CHECK1-NEXT:    br i1 [[CMP17]], label [[COND_TRUE18:%.*]], label [[COND_FALSE19:%.*]]
1210 // CHECK1:       cond.true18:
1211 // CHECK1-NEXT:    [[TMP38:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_3]], align 8
1212 // CHECK1-NEXT:    br label [[COND_END20:%.*]]
1213 // CHECK1:       cond.false19:
1214 // CHECK1-NEXT:    [[TMP39:%.*]] = load i64, ptr [[DOTOMP_COMB_UB]], align 8
1215 // CHECK1-NEXT:    br label [[COND_END20]]
1216 // CHECK1:       cond.end20:
1217 // CHECK1-NEXT:    [[COND21:%.*]] = phi i64 [ [[TMP38]], [[COND_TRUE18]] ], [ [[TMP39]], [[COND_FALSE19]] ]
1218 // CHECK1-NEXT:    store i64 [[COND21]], ptr [[DOTOMP_COMB_UB]], align 8
1219 // CHECK1-NEXT:    [[TMP40:%.*]] = load i64, ptr [[DOTOMP_COMB_LB]], align 8
1220 // CHECK1-NEXT:    store i64 [[TMP40]], ptr [[DOTOMP_IV]], align 8
1221 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]
1222 // CHECK1:       omp.inner.for.end:
1223 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1224 // CHECK1:       omp.loop.exit:
1225 // CHECK1-NEXT:    [[TMP41:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1226 // CHECK1-NEXT:    [[TMP42:%.*]] = load i32, ptr [[TMP41]], align 4
1227 // CHECK1-NEXT:    call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP42]])
1228 // CHECK1-NEXT:    br label [[OMP_PRECOND_END]]
1229 // CHECK1:       omp.precond.end:
1230 // CHECK1-NEXT:    ret void
1231 //
1232 //
1233 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l52_omp_outlined_omp_outlined
1234 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR1]] {
1235 // CHECK1-NEXT:  entry:
1236 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1237 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1238 // CHECK1-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
1239 // CHECK1-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
1240 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
1241 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
1242 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
1243 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1244 // CHECK1-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
1245 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
1246 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
1247 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8
1248 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
1249 // CHECK1-NEXT:    [[J:%.*]] = alloca i32, align 4
1250 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
1251 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
1252 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
1253 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1254 // CHECK1-NEXT:    [[I9:%.*]] = alloca i32, align 4
1255 // CHECK1-NEXT:    [[J10:%.*]] = alloca i32, align 4
1256 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1257 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1258 // CHECK1-NEXT:    store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
1259 // CHECK1-NEXT:    store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
1260 // CHECK1-NEXT:    store i64 [[N]], ptr [[N_ADDR]], align 8
1261 // CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
1262 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8
1263 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
1264 // CHECK1-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
1265 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
1266 // CHECK1-NEXT:    store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_2]], align 4
1267 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1268 // CHECK1-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
1269 // CHECK1-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1
1270 // CHECK1-NEXT:    [[CONV:%.*]] = sext i32 [[DIV]] to i64
1271 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
1272 // CHECK1-NEXT:    [[SUB4:%.*]] = sub nsw i32 [[TMP4]], 0
1273 // CHECK1-NEXT:    [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1
1274 // CHECK1-NEXT:    [[CONV6:%.*]] = sext i32 [[DIV5]] to i64
1275 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]]
1276 // CHECK1-NEXT:    [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1
1277 // CHECK1-NEXT:    store i64 [[SUB7]], ptr [[DOTCAPTURE_EXPR_3]], align 8
1278 // CHECK1-NEXT:    store i32 0, ptr [[I]], align 4
1279 // CHECK1-NEXT:    store i32 0, ptr [[J]], align 4
1280 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1281 // CHECK1-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP5]]
1282 // CHECK1-NEXT:    br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]]
1283 // CHECK1:       land.lhs.true:
1284 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
1285 // CHECK1-NEXT:    [[CMP8:%.*]] = icmp slt i32 0, [[TMP6]]
1286 // CHECK1-NEXT:    br i1 [[CMP8]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]]
1287 // CHECK1:       omp.precond.then:
1288 // CHECK1-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8
1289 // CHECK1-NEXT:    [[TMP7:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_3]], align 8
1290 // CHECK1-NEXT:    store i64 [[TMP7]], ptr [[DOTOMP_UB]], align 8
1291 // CHECK1-NEXT:    [[TMP8:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
1292 // CHECK1-NEXT:    [[TMP9:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
1293 // CHECK1-NEXT:    store i64 [[TMP8]], ptr [[DOTOMP_LB]], align 8
1294 // CHECK1-NEXT:    store i64 [[TMP9]], ptr [[DOTOMP_UB]], align 8
1295 // CHECK1-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8
1296 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1297 // CHECK1-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1298 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4
1299 // CHECK1-NEXT:    call void @__kmpc_for_static_init_8(ptr @[[GLOB3]], i32 [[TMP11]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
1300 // CHECK1-NEXT:    [[TMP12:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
1301 // CHECK1-NEXT:    store i64 [[TMP12]], ptr [[DOTOMP_IV]], align 8
1302 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1303 // CHECK1:       omp.inner.for.cond:
1304 // CHECK1-NEXT:    [[TMP13:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
1305 // CHECK1-NEXT:    [[TMP14:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
1306 // CHECK1-NEXT:    [[CMP11:%.*]] = icmp ule i64 [[TMP13]], [[TMP14]]
1307 // CHECK1-NEXT:    br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1308 // CHECK1:       omp.inner.for.body:
1309 // CHECK1-NEXT:    [[TMP15:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
1310 // CHECK1-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
1311 // CHECK1-NEXT:    [[SUB12:%.*]] = sub nsw i32 [[TMP16]], 0
1312 // CHECK1-NEXT:    [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1
1313 // CHECK1-NEXT:    [[MUL14:%.*]] = mul nsw i32 1, [[DIV13]]
1314 // CHECK1-NEXT:    [[CONV15:%.*]] = sext i32 [[MUL14]] to i64
1315 // CHECK1-NEXT:    [[DIV16:%.*]] = sdiv i64 [[TMP15]], [[CONV15]]
1316 // CHECK1-NEXT:    [[MUL17:%.*]] = mul nsw i64 [[DIV16]], 1
1317 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i64 0, [[MUL17]]
1318 // CHECK1-NEXT:    [[CONV18:%.*]] = trunc i64 [[ADD]] to i32
1319 // CHECK1-NEXT:    store i32 [[CONV18]], ptr [[I9]], align 4
1320 // CHECK1-NEXT:    [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
1321 // CHECK1-NEXT:    [[TMP18:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
1322 // CHECK1-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
1323 // CHECK1-NEXT:    [[SUB19:%.*]] = sub nsw i32 [[TMP19]], 0
1324 // CHECK1-NEXT:    [[DIV20:%.*]] = sdiv i32 [[SUB19]], 1
1325 // CHECK1-NEXT:    [[MUL21:%.*]] = mul nsw i32 1, [[DIV20]]
1326 // CHECK1-NEXT:    [[CONV22:%.*]] = sext i32 [[MUL21]] to i64
1327 // CHECK1-NEXT:    [[DIV23:%.*]] = sdiv i64 [[TMP18]], [[CONV22]]
1328 // CHECK1-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
1329 // CHECK1-NEXT:    [[SUB24:%.*]] = sub nsw i32 [[TMP20]], 0
1330 // CHECK1-NEXT:    [[DIV25:%.*]] = sdiv i32 [[SUB24]], 1
1331 // CHECK1-NEXT:    [[MUL26:%.*]] = mul nsw i32 1, [[DIV25]]
1332 // CHECK1-NEXT:    [[CONV27:%.*]] = sext i32 [[MUL26]] to i64
1333 // CHECK1-NEXT:    [[MUL28:%.*]] = mul nsw i64 [[DIV23]], [[CONV27]]
1334 // CHECK1-NEXT:    [[SUB29:%.*]] = sub nsw i64 [[TMP17]], [[MUL28]]
1335 // CHECK1-NEXT:    [[MUL30:%.*]] = mul nsw i64 [[SUB29]], 1
1336 // CHECK1-NEXT:    [[ADD31:%.*]] = add nsw i64 0, [[MUL30]]
1337 // CHECK1-NEXT:    [[CONV32:%.*]] = trunc i64 [[ADD31]] to i32
1338 // CHECK1-NEXT:    store i32 [[CONV32]], ptr [[J10]], align 4
1339 // CHECK1-NEXT:    [[TMP21:%.*]] = load i32, ptr [[I9]], align 4
1340 // CHECK1-NEXT:    [[TMP22:%.*]] = load i32, ptr [[J10]], align 4
1341 // CHECK1-NEXT:    [[ADD33:%.*]] = add nsw i32 [[TMP21]], [[TMP22]]
1342 // CHECK1-NEXT:    [[TMP23:%.*]] = load i32, ptr [[I9]], align 4
1343 // CHECK1-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64
1344 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP0]], i64 0, i64 [[IDXPROM]]
1345 // CHECK1-NEXT:    [[TMP24:%.*]] = load i32, ptr [[J10]], align 4
1346 // CHECK1-NEXT:    [[IDXPROM34:%.*]] = sext i32 [[TMP24]] to i64
1347 // CHECK1-NEXT:    [[ARRAYIDX35:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM34]]
1348 // CHECK1-NEXT:    store i32 [[ADD33]], ptr [[ARRAYIDX35]], align 4
1349 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1350 // CHECK1:       omp.body.continue:
1351 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1352 // CHECK1:       omp.inner.for.inc:
1353 // CHECK1-NEXT:    [[TMP25:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
1354 // CHECK1-NEXT:    [[TMP26:%.*]] = load i64, ptr [[DOTOMP_STRIDE]], align 8
1355 // CHECK1-NEXT:    [[ADD36:%.*]] = add nsw i64 [[TMP25]], [[TMP26]]
1356 // CHECK1-NEXT:    store i64 [[ADD36]], ptr [[DOTOMP_IV]], align 8
1357 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]
1358 // CHECK1:       omp.inner.for.end:
1359 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1360 // CHECK1:       omp.loop.exit:
1361 // CHECK1-NEXT:    [[TMP27:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1362 // CHECK1-NEXT:    [[TMP28:%.*]] = load i32, ptr [[TMP27]], align 4
1363 // CHECK1-NEXT:    call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP28]])
1364 // CHECK1-NEXT:    br label [[OMP_PRECOND_END]]
1365 // CHECK1:       omp.precond.end:
1366 // CHECK1-NEXT:    ret void
1367 //
1368 //
1369 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l59
1370 // CHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], ptr noundef [[V:%.*]]) #[[ATTR0]] {
1371 // CHECK1-NEXT:  entry:
1372 // CHECK1-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
1373 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
1374 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
1375 // CHECK1-NEXT:    [[V_ADDR:%.*]] = alloca ptr, align 8
1376 // CHECK1-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8
1377 // CHECK1-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
1378 // CHECK1-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
1379 // CHECK1-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
1380 // CHECK1-NEXT:    store i64 [[N]], ptr [[N_ADDR]], align 8
1381 // CHECK1-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
1382 // CHECK1-NEXT:    store ptr [[V]], ptr [[V_ADDR]], align 8
1383 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
1384 // CHECK1-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l59_kernel_environment, ptr [[DYN_PTR]])
1385 // CHECK1-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
1386 // CHECK1-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
1387 // CHECK1:       user_code.entry:
1388 // CHECK1-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
1389 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4
1390 // CHECK1-NEXT:    store i32 [[TMP3]], ptr [[N_CASTED]], align 4
1391 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8
1392 // CHECK1-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[V_ADDR]], align 8
1393 // CHECK1-NEXT:    store i32 0, ptr [[DOTZERO_ADDR]], align 4
1394 // CHECK1-NEXT:    store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4
1395 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l59_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i64 [[TMP4]], ptr [[TMP0]], ptr [[TMP5]]) #[[ATTR2]]
1396 // CHECK1-NEXT:    call void @__kmpc_target_deinit()
1397 // CHECK1-NEXT:    ret void
1398 // CHECK1:       worker.exit:
1399 // CHECK1-NEXT:    ret void
1400 //
1401 //
1402 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l59_omp_outlined
1403 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], ptr noundef [[V:%.*]]) #[[ATTR1]] {
1404 // CHECK1-NEXT:  entry:
1405 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1406 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1407 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
1408 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
1409 // CHECK1-NEXT:    [[V_ADDR:%.*]] = alloca ptr, align 8
1410 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1411 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1412 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
1413 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
1414 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
1415 // CHECK1-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
1416 // CHECK1-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
1417 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1418 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1419 // CHECK1-NEXT:    [[I3:%.*]] = alloca i32, align 4
1420 // CHECK1-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8
1421 // CHECK1-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [5 x ptr], align 8
1422 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1423 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1424 // CHECK1-NEXT:    store i64 [[N]], ptr [[N_ADDR]], align 8
1425 // CHECK1-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
1426 // CHECK1-NEXT:    store ptr [[V]], ptr [[V_ADDR]], align 8
1427 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
1428 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
1429 // CHECK1-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
1430 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1431 // CHECK1-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
1432 // CHECK1-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1
1433 // CHECK1-NEXT:    [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
1434 // CHECK1-NEXT:    store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
1435 // CHECK1-NEXT:    store i32 0, ptr [[I]], align 4
1436 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1437 // CHECK1-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]
1438 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
1439 // CHECK1:       omp.precond.then:
1440 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
1441 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
1442 // CHECK1-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_COMB_UB]], align 4
1443 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1444 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1445 // CHECK1-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
1446 // CHECK1-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1447 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
1448 // CHECK1-NEXT:    call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP6]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
1449 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1450 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
1451 // CHECK1-NEXT:    [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]]
1452 // CHECK1-NEXT:    br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1453 // CHECK1:       cond.true:
1454 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
1455 // CHECK1-NEXT:    br label [[COND_END:%.*]]
1456 // CHECK1:       cond.false:
1457 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1458 // CHECK1-NEXT:    br label [[COND_END]]
1459 // CHECK1:       cond.end:
1460 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
1461 // CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
1462 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
1463 // CHECK1-NEXT:    store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 4
1464 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1465 // CHECK1:       omp.inner.for.cond:
1466 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1467 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
1468 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP13]], 1
1469 // CHECK1-NEXT:    [[CMP5:%.*]] = icmp slt i32 [[TMP12]], [[ADD]]
1470 // CHECK1-NEXT:    br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1471 // CHECK1:       omp.inner.for.body:
1472 // CHECK1-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
1473 // CHECK1-NEXT:    [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
1474 // CHECK1-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1475 // CHECK1-NEXT:    [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
1476 // CHECK1-NEXT:    [[TMP18:%.*]] = load i32, ptr [[N_ADDR]], align 4
1477 // CHECK1-NEXT:    store i32 [[TMP18]], ptr [[N_CASTED]], align 4
1478 // CHECK1-NEXT:    [[TMP19:%.*]] = load i64, ptr [[N_CASTED]], align 8
1479 // CHECK1-NEXT:    [[TMP20:%.*]] = load ptr, ptr [[V_ADDR]], align 8
1480 // CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
1481 // CHECK1-NEXT:    [[TMP22:%.*]] = inttoptr i64 [[TMP15]] to ptr
1482 // CHECK1-NEXT:    store ptr [[TMP22]], ptr [[TMP21]], align 8
1483 // CHECK1-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
1484 // CHECK1-NEXT:    [[TMP24:%.*]] = inttoptr i64 [[TMP17]] to ptr
1485 // CHECK1-NEXT:    store ptr [[TMP24]], ptr [[TMP23]], align 8
1486 // CHECK1-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
1487 // CHECK1-NEXT:    [[TMP26:%.*]] = inttoptr i64 [[TMP19]] to ptr
1488 // CHECK1-NEXT:    store ptr [[TMP26]], ptr [[TMP25]], align 8
1489 // CHECK1-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3
1490 // CHECK1-NEXT:    store ptr [[TMP0]], ptr [[TMP27]], align 8
1491 // CHECK1-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 4
1492 // CHECK1-NEXT:    store ptr [[TMP20]], ptr [[TMP28]], align 8
1493 // CHECK1-NEXT:    [[TMP29:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1494 // CHECK1-NEXT:    [[TMP30:%.*]] = load i32, ptr [[TMP29]], align 4
1495 // CHECK1-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP30]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l59_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 5)
1496 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1497 // CHECK1:       omp.inner.for.inc:
1498 // CHECK1-NEXT:    [[TMP31:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1499 // CHECK1-NEXT:    [[TMP32:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
1500 // CHECK1-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP31]], [[TMP32]]
1501 // CHECK1-NEXT:    store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4
1502 // CHECK1-NEXT:    [[TMP33:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
1503 // CHECK1-NEXT:    [[TMP34:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
1504 // CHECK1-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP33]], [[TMP34]]
1505 // CHECK1-NEXT:    store i32 [[ADD7]], ptr [[DOTOMP_COMB_LB]], align 4
1506 // CHECK1-NEXT:    [[TMP35:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1507 // CHECK1-NEXT:    [[TMP36:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
1508 // CHECK1-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP35]], [[TMP36]]
1509 // CHECK1-NEXT:    store i32 [[ADD8]], ptr [[DOTOMP_COMB_UB]], align 4
1510 // CHECK1-NEXT:    [[TMP37:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1511 // CHECK1-NEXT:    [[TMP38:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
1512 // CHECK1-NEXT:    [[CMP9:%.*]] = icmp sgt i32 [[TMP37]], [[TMP38]]
1513 // CHECK1-NEXT:    br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]]
1514 // CHECK1:       cond.true10:
1515 // CHECK1-NEXT:    [[TMP39:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
1516 // CHECK1-NEXT:    br label [[COND_END12:%.*]]
1517 // CHECK1:       cond.false11:
1518 // CHECK1-NEXT:    [[TMP40:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1519 // CHECK1-NEXT:    br label [[COND_END12]]
1520 // CHECK1:       cond.end12:
1521 // CHECK1-NEXT:    [[COND13:%.*]] = phi i32 [ [[TMP39]], [[COND_TRUE10]] ], [ [[TMP40]], [[COND_FALSE11]] ]
1522 // CHECK1-NEXT:    store i32 [[COND13]], ptr [[DOTOMP_COMB_UB]], align 4
1523 // CHECK1-NEXT:    [[TMP41:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
1524 // CHECK1-NEXT:    store i32 [[TMP41]], ptr [[DOTOMP_IV]], align 4
1525 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]
1526 // CHECK1:       omp.inner.for.end:
1527 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1528 // CHECK1:       omp.loop.exit:
1529 // CHECK1-NEXT:    [[TMP42:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1530 // CHECK1-NEXT:    [[TMP43:%.*]] = load i32, ptr [[TMP42]], align 4
1531 // CHECK1-NEXT:    call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP43]])
1532 // CHECK1-NEXT:    br label [[OMP_PRECOND_END]]
1533 // CHECK1:       omp.precond.end:
1534 // CHECK1-NEXT:    ret void
1535 //
1536 //
1537 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l59_omp_outlined_omp_outlined
1538 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], ptr noundef [[V:%.*]]) #[[ATTR1]] {
1539 // CHECK1-NEXT:  entry:
1540 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1541 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1542 // CHECK1-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
1543 // CHECK1-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
1544 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
1545 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
1546 // CHECK1-NEXT:    [[V_ADDR:%.*]] = alloca ptr, align 8
1547 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1548 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1549 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
1550 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
1551 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
1552 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1553 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1554 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1555 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1556 // CHECK1-NEXT:    [[I4:%.*]] = alloca i32, align 4
1557 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1558 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1559 // CHECK1-NEXT:    store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
1560 // CHECK1-NEXT:    store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
1561 // CHECK1-NEXT:    store i64 [[N]], ptr [[N_ADDR]], align 8
1562 // CHECK1-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
1563 // CHECK1-NEXT:    store ptr [[V]], ptr [[V_ADDR]], align 8
1564 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
1565 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
1566 // CHECK1-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
1567 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1568 // CHECK1-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
1569 // CHECK1-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1
1570 // CHECK1-NEXT:    [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
1571 // CHECK1-NEXT:    store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
1572 // CHECK1-NEXT:    store i32 0, ptr [[I]], align 4
1573 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1574 // CHECK1-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]
1575 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
1576 // CHECK1:       omp.precond.then:
1577 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
1578 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
1579 // CHECK1-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4
1580 // CHECK1-NEXT:    [[TMP5:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
1581 // CHECK1-NEXT:    [[CONV:%.*]] = trunc i64 [[TMP5]] to i32
1582 // CHECK1-NEXT:    [[TMP6:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
1583 // CHECK1-NEXT:    [[CONV3:%.*]] = trunc i64 [[TMP6]] to i32
1584 // CHECK1-NEXT:    store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
1585 // CHECK1-NEXT:    store i32 [[CONV3]], ptr [[DOTOMP_UB]], align 4
1586 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1587 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1588 // CHECK1-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1589 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
1590 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP8]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
1591 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1592 // CHECK1-NEXT:    store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4
1593 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1594 // CHECK1:       omp.inner.for.cond:
1595 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1596 // CHECK1-NEXT:    [[CONV5:%.*]] = sext i32 [[TMP10]] to i64
1597 // CHECK1-NEXT:    [[TMP11:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
1598 // CHECK1-NEXT:    [[CMP6:%.*]] = icmp ule i64 [[CONV5]], [[TMP11]]
1599 // CHECK1-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1600 // CHECK1:       omp.inner.for.body:
1601 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1602 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
1603 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1604 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[I4]], align 4
1605 // CHECK1-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[V_ADDR]], align 8
1606 // CHECK1-NEXT:    [[TMP14:%.*]] = load i32, ptr [[I4]], align 4
1607 // CHECK1-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64
1608 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP13]], i64 [[IDXPROM]]
1609 // CHECK1-NEXT:    [[TMP15:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
1610 // CHECK1-NEXT:    [[TMP16:%.*]] = load i32, ptr [[I4]], align 4
1611 // CHECK1-NEXT:    [[IDXPROM7:%.*]] = sext i32 [[TMP16]] to i64
1612 // CHECK1-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM7]]
1613 // CHECK1-NEXT:    store i32 [[TMP15]], ptr [[ARRAYIDX8]], align 4
1614 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1615 // CHECK1:       omp.body.continue:
1616 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1617 // CHECK1:       omp.inner.for.inc:
1618 // CHECK1-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1619 // CHECK1-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
1620 // CHECK1-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP17]], [[TMP18]]
1621 // CHECK1-NEXT:    store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4
1622 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]
1623 // CHECK1:       omp.inner.for.end:
1624 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1625 // CHECK1:       omp.loop.exit:
1626 // CHECK1-NEXT:    [[TMP19:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1627 // CHECK1-NEXT:    [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4
1628 // CHECK1-NEXT:    call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP20]])
1629 // CHECK1-NEXT:    br label [[OMP_PRECOND_END]]
1630 // CHECK1:       omp.precond.end:
1631 // CHECK1-NEXT:    ret void
1632 //
1633 //
1634 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28
1635 // CHECK2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 noundef [[L:%.*]]) #[[ATTR0:[0-9]+]] {
1636 // CHECK2-NEXT:  entry:
1637 // CHECK2-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
1638 // CHECK2-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
1639 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
1640 // CHECK2-NEXT:    [[L_ADDR:%.*]] = alloca i64, align 8
1641 // CHECK2-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8
1642 // CHECK2-NEXT:    [[L_CASTED:%.*]] = alloca i64, align 8
1643 // CHECK2-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
1644 // CHECK2-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
1645 // CHECK2-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
1646 // CHECK2-NEXT:    store i64 [[N]], ptr [[N_ADDR]], align 8
1647 // CHECK2-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
1648 // CHECK2-NEXT:    store i64 [[L]], ptr [[L_ADDR]], align 8
1649 // CHECK2-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
1650 // CHECK2-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28_kernel_environment, ptr [[DYN_PTR]])
1651 // CHECK2-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
1652 // CHECK2-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
1653 // CHECK2:       user_code.entry:
1654 // CHECK2-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
1655 // CHECK2-NEXT:    [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4
1656 // CHECK2-NEXT:    store i32 [[TMP3]], ptr [[N_CASTED]], align 4
1657 // CHECK2-NEXT:    [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8
1658 // CHECK2-NEXT:    [[TMP5:%.*]] = load i32, ptr [[L_ADDR]], align 4
1659 // CHECK2-NEXT:    store i32 [[TMP5]], ptr [[L_CASTED]], align 4
1660 // CHECK2-NEXT:    [[TMP6:%.*]] = load i64, ptr [[L_CASTED]], align 8
1661 // CHECK2-NEXT:    store i32 0, ptr [[DOTZERO_ADDR]], align 4
1662 // CHECK2-NEXT:    store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4
1663 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i64 [[TMP4]], ptr [[TMP0]], i64 [[TMP6]]) #[[ATTR2:[0-9]+]]
1664 // CHECK2-NEXT:    call void @__kmpc_target_deinit()
1665 // CHECK2-NEXT:    ret void
1666 // CHECK2:       worker.exit:
1667 // CHECK2-NEXT:    ret void
1668 //
1669 //
1670 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28_omp_outlined
1671 // CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 noundef [[L:%.*]]) #[[ATTR1:[0-9]+]] {
1672 // CHECK2-NEXT:  entry:
1673 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1674 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1675 // CHECK2-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
1676 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
1677 // CHECK2-NEXT:    [[L_ADDR:%.*]] = alloca i64, align 8
1678 // CHECK2-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1679 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1680 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
1681 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
1682 // CHECK2-NEXT:    [[I:%.*]] = alloca i32, align 4
1683 // CHECK2-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
1684 // CHECK2-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
1685 // CHECK2-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1686 // CHECK2-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1687 // CHECK2-NEXT:    [[I3:%.*]] = alloca i32, align 4
1688 // CHECK2-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8
1689 // CHECK2-NEXT:    [[L_CASTED:%.*]] = alloca i64, align 8
1690 // CHECK2-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [5 x ptr], align 8
1691 // CHECK2-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1692 // CHECK2-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1693 // CHECK2-NEXT:    store i64 [[N]], ptr [[N_ADDR]], align 8
1694 // CHECK2-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
1695 // CHECK2-NEXT:    store i64 [[L]], ptr [[L_ADDR]], align 8
1696 // CHECK2-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
1697 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
1698 // CHECK2-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
1699 // CHECK2-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1700 // CHECK2-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
1701 // CHECK2-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1
1702 // CHECK2-NEXT:    [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
1703 // CHECK2-NEXT:    store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
1704 // CHECK2-NEXT:    store i32 0, ptr [[I]], align 4
1705 // CHECK2-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1706 // CHECK2-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]
1707 // CHECK2-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
1708 // CHECK2:       omp.precond.then:
1709 // CHECK2-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
1710 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
1711 // CHECK2-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_COMB_UB]], align 4
1712 // CHECK2-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1713 // CHECK2-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1714 // CHECK2-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1715 // CHECK2-NEXT:    [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
1716 // CHECK2-NEXT:    call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP6]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 128)
1717 // CHECK2-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1718 // CHECK2-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
1719 // CHECK2-NEXT:    [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]]
1720 // CHECK2-NEXT:    br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1721 // CHECK2:       cond.true:
1722 // CHECK2-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
1723 // CHECK2-NEXT:    br label [[COND_END:%.*]]
1724 // CHECK2:       cond.false:
1725 // CHECK2-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1726 // CHECK2-NEXT:    br label [[COND_END]]
1727 // CHECK2:       cond.end:
1728 // CHECK2-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
1729 // CHECK2-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
1730 // CHECK2-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
1731 // CHECK2-NEXT:    store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 4
1732 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1733 // CHECK2:       omp.inner.for.cond:
1734 // CHECK2-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1735 // CHECK2-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
1736 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP13]], 1
1737 // CHECK2-NEXT:    [[CMP5:%.*]] = icmp slt i32 [[TMP12]], [[ADD]]
1738 // CHECK2-NEXT:    br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1739 // CHECK2:       omp.inner.for.body:
1740 // CHECK2-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
1741 // CHECK2-NEXT:    [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
1742 // CHECK2-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1743 // CHECK2-NEXT:    [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
1744 // CHECK2-NEXT:    [[TMP18:%.*]] = load i32, ptr [[N_ADDR]], align 4
1745 // CHECK2-NEXT:    store i32 [[TMP18]], ptr [[N_CASTED]], align 4
1746 // CHECK2-NEXT:    [[TMP19:%.*]] = load i64, ptr [[N_CASTED]], align 8
1747 // CHECK2-NEXT:    [[TMP20:%.*]] = load i32, ptr [[L_ADDR]], align 4
1748 // CHECK2-NEXT:    store i32 [[TMP20]], ptr [[L_CASTED]], align 4
1749 // CHECK2-NEXT:    [[TMP21:%.*]] = load i64, ptr [[L_CASTED]], align 8
1750 // CHECK2-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
1751 // CHECK2-NEXT:    [[TMP23:%.*]] = inttoptr i64 [[TMP15]] to ptr
1752 // CHECK2-NEXT:    store ptr [[TMP23]], ptr [[TMP22]], align 8
1753 // CHECK2-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
1754 // CHECK2-NEXT:    [[TMP25:%.*]] = inttoptr i64 [[TMP17]] to ptr
1755 // CHECK2-NEXT:    store ptr [[TMP25]], ptr [[TMP24]], align 8
1756 // CHECK2-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
1757 // CHECK2-NEXT:    [[TMP27:%.*]] = inttoptr i64 [[TMP19]] to ptr
1758 // CHECK2-NEXT:    store ptr [[TMP27]], ptr [[TMP26]], align 8
1759 // CHECK2-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3
1760 // CHECK2-NEXT:    store ptr [[TMP0]], ptr [[TMP28]], align 8
1761 // CHECK2-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 4
1762 // CHECK2-NEXT:    [[TMP30:%.*]] = inttoptr i64 [[TMP21]] to ptr
1763 // CHECK2-NEXT:    store ptr [[TMP30]], ptr [[TMP29]], align 8
1764 // CHECK2-NEXT:    [[TMP31:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1765 // CHECK2-NEXT:    [[TMP32:%.*]] = load i32, ptr [[TMP31]], align 4
1766 // CHECK2-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP32]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 5)
1767 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1768 // CHECK2:       omp.inner.for.inc:
1769 // CHECK2-NEXT:    [[TMP33:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1770 // CHECK2-NEXT:    [[TMP34:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
1771 // CHECK2-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP33]], [[TMP34]]
1772 // CHECK2-NEXT:    store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4
1773 // CHECK2-NEXT:    [[TMP35:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
1774 // CHECK2-NEXT:    [[TMP36:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
1775 // CHECK2-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP35]], [[TMP36]]
1776 // CHECK2-NEXT:    store i32 [[ADD7]], ptr [[DOTOMP_COMB_LB]], align 4
1777 // CHECK2-NEXT:    [[TMP37:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1778 // CHECK2-NEXT:    [[TMP38:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
1779 // CHECK2-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP37]], [[TMP38]]
1780 // CHECK2-NEXT:    store i32 [[ADD8]], ptr [[DOTOMP_COMB_UB]], align 4
1781 // CHECK2-NEXT:    [[TMP39:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1782 // CHECK2-NEXT:    [[TMP40:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
1783 // CHECK2-NEXT:    [[CMP9:%.*]] = icmp sgt i32 [[TMP39]], [[TMP40]]
1784 // CHECK2-NEXT:    br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]]
1785 // CHECK2:       cond.true10:
1786 // CHECK2-NEXT:    [[TMP41:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
1787 // CHECK2-NEXT:    br label [[COND_END12:%.*]]
1788 // CHECK2:       cond.false11:
1789 // CHECK2-NEXT:    [[TMP42:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1790 // CHECK2-NEXT:    br label [[COND_END12]]
1791 // CHECK2:       cond.end12:
1792 // CHECK2-NEXT:    [[COND13:%.*]] = phi i32 [ [[TMP41]], [[COND_TRUE10]] ], [ [[TMP42]], [[COND_FALSE11]] ]
1793 // CHECK2-NEXT:    store i32 [[COND13]], ptr [[DOTOMP_COMB_UB]], align 4
1794 // CHECK2-NEXT:    [[TMP43:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
1795 // CHECK2-NEXT:    store i32 [[TMP43]], ptr [[DOTOMP_IV]], align 4
1796 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND]]
1797 // CHECK2:       omp.inner.for.end:
1798 // CHECK2-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1799 // CHECK2:       omp.loop.exit:
1800 // CHECK2-NEXT:    [[TMP44:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1801 // CHECK2-NEXT:    [[TMP45:%.*]] = load i32, ptr [[TMP44]], align 4
1802 // CHECK2-NEXT:    call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP45]])
1803 // CHECK2-NEXT:    [[TMP46:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
1804 // CHECK2-NEXT:    [[TMP47:%.*]] = icmp ne i32 [[TMP46]], 0
1805 // CHECK2-NEXT:    br i1 [[TMP47]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
1806 // CHECK2:       .omp.lastprivate.then:
1807 // CHECK2-NEXT:    [[TMP48:%.*]] = load i32, ptr [[L_ADDR]], align 4
1808 // CHECK2-NEXT:    store i32 [[TMP48]], ptr [[L_ADDR]], align 4
1809 // CHECK2-NEXT:    br label [[DOTOMP_LASTPRIVATE_DONE]]
1810 // CHECK2:       .omp.lastprivate.done:
1811 // CHECK2-NEXT:    br label [[OMP_PRECOND_END]]
1812 // CHECK2:       omp.precond.end:
1813 // CHECK2-NEXT:    ret void
1814 //
1815 //
1816 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28_omp_outlined_omp_outlined
1817 // CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 noundef [[L:%.*]]) #[[ATTR1]] {
1818 // CHECK2-NEXT:  entry:
1819 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1820 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1821 // CHECK2-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
1822 // CHECK2-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
1823 // CHECK2-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
1824 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
1825 // CHECK2-NEXT:    [[L_ADDR:%.*]] = alloca i64, align 8
1826 // CHECK2-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1827 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1828 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
1829 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
1830 // CHECK2-NEXT:    [[I:%.*]] = alloca i32, align 4
1831 // CHECK2-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1832 // CHECK2-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1833 // CHECK2-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1834 // CHECK2-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1835 // CHECK2-NEXT:    [[I4:%.*]] = alloca i32, align 4
1836 // CHECK2-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1837 // CHECK2-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1838 // CHECK2-NEXT:    store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
1839 // CHECK2-NEXT:    store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
1840 // CHECK2-NEXT:    store i64 [[N]], ptr [[N_ADDR]], align 8
1841 // CHECK2-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
1842 // CHECK2-NEXT:    store i64 [[L]], ptr [[L_ADDR]], align 8
1843 // CHECK2-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
1844 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
1845 // CHECK2-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
1846 // CHECK2-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1847 // CHECK2-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
1848 // CHECK2-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1
1849 // CHECK2-NEXT:    [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
1850 // CHECK2-NEXT:    store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
1851 // CHECK2-NEXT:    store i32 0, ptr [[I]], align 4
1852 // CHECK2-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1853 // CHECK2-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]
1854 // CHECK2-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
1855 // CHECK2:       omp.precond.then:
1856 // CHECK2-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
1857 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
1858 // CHECK2-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4
1859 // CHECK2-NEXT:    [[TMP5:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
1860 // CHECK2-NEXT:    [[CONV:%.*]] = trunc i64 [[TMP5]] to i32
1861 // CHECK2-NEXT:    [[TMP6:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
1862 // CHECK2-NEXT:    [[CONV3:%.*]] = trunc i64 [[TMP6]] to i32
1863 // CHECK2-NEXT:    store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
1864 // CHECK2-NEXT:    store i32 [[CONV3]], ptr [[DOTOMP_UB]], align 4
1865 // CHECK2-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1866 // CHECK2-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1867 // CHECK2-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1868 // CHECK2-NEXT:    [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
1869 // CHECK2-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB3:[0-9]+]], i32 [[TMP8]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 32)
1870 // CHECK2-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
1871 // CHECK2:       omp.dispatch.cond:
1872 // CHECK2-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1873 // CHECK2-NEXT:    [[TMP10:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
1874 // CHECK2-NEXT:    [[CONV5:%.*]] = trunc i64 [[TMP10]] to i32
1875 // CHECK2-NEXT:    [[CMP6:%.*]] = icmp sgt i32 [[TMP9]], [[CONV5]]
1876 // CHECK2-NEXT:    br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1877 // CHECK2:       cond.true:
1878 // CHECK2-NEXT:    [[TMP11:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
1879 // CHECK2-NEXT:    [[CONV7:%.*]] = trunc i64 [[TMP11]] to i32
1880 // CHECK2-NEXT:    br label [[COND_END:%.*]]
1881 // CHECK2:       cond.false:
1882 // CHECK2-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1883 // CHECK2-NEXT:    br label [[COND_END]]
1884 // CHECK2:       cond.end:
1885 // CHECK2-NEXT:    [[COND:%.*]] = phi i32 [ [[CONV7]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
1886 // CHECK2-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
1887 // CHECK2-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1888 // CHECK2-NEXT:    store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4
1889 // CHECK2-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1890 // CHECK2-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1891 // CHECK2-NEXT:    [[CMP8:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
1892 // CHECK2-NEXT:    br i1 [[CMP8]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
1893 // CHECK2:       omp.dispatch.body:
1894 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1895 // CHECK2:       omp.inner.for.cond:
1896 // CHECK2-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1897 // CHECK2-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1898 // CHECK2-NEXT:    [[CMP9:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
1899 // CHECK2-NEXT:    br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1900 // CHECK2:       omp.inner.for.body:
1901 // CHECK2-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1902 // CHECK2-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
1903 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1904 // CHECK2-NEXT:    store i32 [[ADD]], ptr [[I4]], align 4
1905 // CHECK2-NEXT:    [[TMP19:%.*]] = load i32, ptr [[I4]], align 4
1906 // CHECK2-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64
1907 // CHECK2-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]]
1908 // CHECK2-NEXT:    store i32 1, ptr [[ARRAYIDX]], align 4
1909 // CHECK2-NEXT:    [[TMP20:%.*]] = load i32, ptr [[I4]], align 4
1910 // CHECK2-NEXT:    store i32 [[TMP20]], ptr [[L_ADDR]], align 4
1911 // CHECK2-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1912 // CHECK2:       omp.body.continue:
1913 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1914 // CHECK2:       omp.inner.for.inc:
1915 // CHECK2-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1916 // CHECK2-NEXT:    [[ADD10:%.*]] = add nsw i32 [[TMP21]], 1
1917 // CHECK2-NEXT:    store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4
1918 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND]]
1919 // CHECK2:       omp.inner.for.end:
1920 // CHECK2-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
1921 // CHECK2:       omp.dispatch.inc:
1922 // CHECK2-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1923 // CHECK2-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
1924 // CHECK2-NEXT:    [[ADD11:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]
1925 // CHECK2-NEXT:    store i32 [[ADD11]], ptr [[DOTOMP_LB]], align 4
1926 // CHECK2-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1927 // CHECK2-NEXT:    [[TMP25:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
1928 // CHECK2-NEXT:    [[ADD12:%.*]] = add nsw i32 [[TMP24]], [[TMP25]]
1929 // CHECK2-NEXT:    store i32 [[ADD12]], ptr [[DOTOMP_UB]], align 4
1930 // CHECK2-NEXT:    br label [[OMP_DISPATCH_COND]]
1931 // CHECK2:       omp.dispatch.end:
1932 // CHECK2-NEXT:    [[TMP26:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1933 // CHECK2-NEXT:    [[TMP27:%.*]] = load i32, ptr [[TMP26]], align 4
1934 // CHECK2-NEXT:    call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP27]])
1935 // CHECK2-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
1936 // CHECK2-NEXT:    [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0
1937 // CHECK2-NEXT:    br i1 [[TMP29]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
1938 // CHECK2:       .omp.lastprivate.then:
1939 // CHECK2-NEXT:    [[TMP30:%.*]] = load i32, ptr [[L_ADDR]], align 4
1940 // CHECK2-NEXT:    store i32 [[TMP30]], ptr [[L_ADDR]], align 4
1941 // CHECK2-NEXT:    br label [[DOTOMP_LASTPRIVATE_DONE]]
1942 // CHECK2:       .omp.lastprivate.done:
1943 // CHECK2-NEXT:    br label [[OMP_PRECOND_END]]
1944 // CHECK2:       omp.precond.end:
1945 // CHECK2-NEXT:    ret void
1946 //
1947 //
1948 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34
1949 // CHECK2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR4:[0-9]+]] {
1950 // CHECK2-NEXT:  entry:
1951 // CHECK2-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
1952 // CHECK2-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
1953 // CHECK2-NEXT:    [[AA_ADDR:%.*]] = alloca ptr, align 8
1954 // CHECK2-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8
1955 // CHECK2-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
1956 // CHECK2-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
1957 // CHECK2-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
1958 // CHECK2-NEXT:    store i64 [[N]], ptr [[N_ADDR]], align 8
1959 // CHECK2-NEXT:    store ptr [[AA]], ptr [[AA_ADDR]], align 8
1960 // CHECK2-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8
1961 // CHECK2-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_kernel_environment, ptr [[DYN_PTR]])
1962 // CHECK2-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
1963 // CHECK2-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
1964 // CHECK2:       user_code.entry:
1965 // CHECK2-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
1966 // CHECK2-NEXT:    [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4
1967 // CHECK2-NEXT:    store i32 [[TMP3]], ptr [[N_CASTED]], align 4
1968 // CHECK2-NEXT:    [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8
1969 // CHECK2-NEXT:    store i32 0, ptr [[DOTZERO_ADDR]], align 4
1970 // CHECK2-NEXT:    store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4
1971 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i64 [[TMP4]], ptr [[TMP0]]) #[[ATTR2]]
1972 // CHECK2-NEXT:    call void @__kmpc_target_deinit()
1973 // CHECK2-NEXT:    ret void
1974 // CHECK2:       worker.exit:
1975 // CHECK2-NEXT:    ret void
1976 //
1977 //
1978 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_omp_outlined
1979 // CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR1]] {
1980 // CHECK2-NEXT:  entry:
1981 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1982 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1983 // CHECK2-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
1984 // CHECK2-NEXT:    [[AA_ADDR:%.*]] = alloca ptr, align 8
1985 // CHECK2-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1986 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1987 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
1988 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
1989 // CHECK2-NEXT:    [[I:%.*]] = alloca i32, align 4
1990 // CHECK2-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
1991 // CHECK2-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
1992 // CHECK2-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1993 // CHECK2-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1994 // CHECK2-NEXT:    [[I3:%.*]] = alloca i32, align 4
1995 // CHECK2-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8
1996 // CHECK2-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [4 x ptr], align 8
1997 // CHECK2-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1998 // CHECK2-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1999 // CHECK2-NEXT:    store i64 [[N]], ptr [[N_ADDR]], align 8
2000 // CHECK2-NEXT:    store ptr [[AA]], ptr [[AA_ADDR]], align 8
2001 // CHECK2-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8
2002 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
2003 // CHECK2-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
2004 // CHECK2-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
2005 // CHECK2-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
2006 // CHECK2-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1
2007 // CHECK2-NEXT:    [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
2008 // CHECK2-NEXT:    store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
2009 // CHECK2-NEXT:    store i32 0, ptr [[I]], align 4
2010 // CHECK2-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
2011 // CHECK2-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]
2012 // CHECK2-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
2013 // CHECK2:       omp.precond.then:
2014 // CHECK2-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
2015 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
2016 // CHECK2-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_COMB_UB]], align 4
2017 // CHECK2-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
2018 // CHECK2-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2019 // CHECK2-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
2020 // CHECK2-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
2021 // CHECK2-NEXT:    [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
2022 // CHECK2-NEXT:    call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP6]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
2023 // CHECK2-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2024 // CHECK2-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
2025 // CHECK2-NEXT:    [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]]
2026 // CHECK2-NEXT:    br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2027 // CHECK2:       cond.true:
2028 // CHECK2-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
2029 // CHECK2-NEXT:    br label [[COND_END:%.*]]
2030 // CHECK2:       cond.false:
2031 // CHECK2-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2032 // CHECK2-NEXT:    br label [[COND_END]]
2033 // CHECK2:       cond.end:
2034 // CHECK2-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
2035 // CHECK2-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
2036 // CHECK2-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
2037 // CHECK2-NEXT:    store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 4
2038 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2039 // CHECK2:       omp.inner.for.cond:
2040 // CHECK2-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2041 // CHECK2-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
2042 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP13]], 1
2043 // CHECK2-NEXT:    [[CMP5:%.*]] = icmp slt i32 [[TMP12]], [[ADD]]
2044 // CHECK2-NEXT:    br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2045 // CHECK2:       omp.inner.for.body:
2046 // CHECK2-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
2047 // CHECK2-NEXT:    [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
2048 // CHECK2-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2049 // CHECK2-NEXT:    [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
2050 // CHECK2-NEXT:    [[TMP18:%.*]] = load i32, ptr [[N_ADDR]], align 4
2051 // CHECK2-NEXT:    store i32 [[TMP18]], ptr [[N_CASTED]], align 4
2052 // CHECK2-NEXT:    [[TMP19:%.*]] = load i64, ptr [[N_CASTED]], align 8
2053 // CHECK2-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
2054 // CHECK2-NEXT:    [[TMP21:%.*]] = inttoptr i64 [[TMP15]] to ptr
2055 // CHECK2-NEXT:    store ptr [[TMP21]], ptr [[TMP20]], align 8
2056 // CHECK2-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
2057 // CHECK2-NEXT:    [[TMP23:%.*]] = inttoptr i64 [[TMP17]] to ptr
2058 // CHECK2-NEXT:    store ptr [[TMP23]], ptr [[TMP22]], align 8
2059 // CHECK2-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
2060 // CHECK2-NEXT:    [[TMP25:%.*]] = inttoptr i64 [[TMP19]] to ptr
2061 // CHECK2-NEXT:    store ptr [[TMP25]], ptr [[TMP24]], align 8
2062 // CHECK2-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3
2063 // CHECK2-NEXT:    store ptr [[TMP0]], ptr [[TMP26]], align 8
2064 // CHECK2-NEXT:    [[TMP27:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
2065 // CHECK2-NEXT:    [[TMP28:%.*]] = load i32, ptr [[TMP27]], align 4
2066 // CHECK2-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP28]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 4)
2067 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2068 // CHECK2:       omp.inner.for.inc:
2069 // CHECK2-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2070 // CHECK2-NEXT:    [[TMP30:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
2071 // CHECK2-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP29]], [[TMP30]]
2072 // CHECK2-NEXT:    store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4
2073 // CHECK2-NEXT:    [[TMP31:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
2074 // CHECK2-NEXT:    [[TMP32:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
2075 // CHECK2-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP31]], [[TMP32]]
2076 // CHECK2-NEXT:    store i32 [[ADD7]], ptr [[DOTOMP_COMB_LB]], align 4
2077 // CHECK2-NEXT:    [[TMP33:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2078 // CHECK2-NEXT:    [[TMP34:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
2079 // CHECK2-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP33]], [[TMP34]]
2080 // CHECK2-NEXT:    store i32 [[ADD8]], ptr [[DOTOMP_COMB_UB]], align 4
2081 // CHECK2-NEXT:    [[TMP35:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2082 // CHECK2-NEXT:    [[TMP36:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
2083 // CHECK2-NEXT:    [[CMP9:%.*]] = icmp sgt i32 [[TMP35]], [[TMP36]]
2084 // CHECK2-NEXT:    br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]]
2085 // CHECK2:       cond.true10:
2086 // CHECK2-NEXT:    [[TMP37:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
2087 // CHECK2-NEXT:    br label [[COND_END12:%.*]]
2088 // CHECK2:       cond.false11:
2089 // CHECK2-NEXT:    [[TMP38:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2090 // CHECK2-NEXT:    br label [[COND_END12]]
2091 // CHECK2:       cond.end12:
2092 // CHECK2-NEXT:    [[COND13:%.*]] = phi i32 [ [[TMP37]], [[COND_TRUE10]] ], [ [[TMP38]], [[COND_FALSE11]] ]
2093 // CHECK2-NEXT:    store i32 [[COND13]], ptr [[DOTOMP_COMB_UB]], align 4
2094 // CHECK2-NEXT:    [[TMP39:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
2095 // CHECK2-NEXT:    store i32 [[TMP39]], ptr [[DOTOMP_IV]], align 4
2096 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND]]
2097 // CHECK2:       omp.inner.for.end:
2098 // CHECK2-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2099 // CHECK2:       omp.loop.exit:
2100 // CHECK2-NEXT:    [[TMP40:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
2101 // CHECK2-NEXT:    [[TMP41:%.*]] = load i32, ptr [[TMP40]], align 4
2102 // CHECK2-NEXT:    call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP41]])
2103 // CHECK2-NEXT:    br label [[OMP_PRECOND_END]]
2104 // CHECK2:       omp.precond.end:
2105 // CHECK2-NEXT:    ret void
2106 //
2107 //
2108 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_omp_outlined_omp_outlined
2109 // CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR1]] {
2110 // CHECK2-NEXT:  entry:
2111 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
2112 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
2113 // CHECK2-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
2114 // CHECK2-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
2115 // CHECK2-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
2116 // CHECK2-NEXT:    [[AA_ADDR:%.*]] = alloca ptr, align 8
2117 // CHECK2-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2118 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2119 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
2120 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
2121 // CHECK2-NEXT:    [[I:%.*]] = alloca i32, align 4
2122 // CHECK2-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2123 // CHECK2-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2124 // CHECK2-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2125 // CHECK2-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2126 // CHECK2-NEXT:    [[I4:%.*]] = alloca i32, align 4
2127 // CHECK2-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
2128 // CHECK2-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
2129 // CHECK2-NEXT:    store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
2130 // CHECK2-NEXT:    store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
2131 // CHECK2-NEXT:    store i64 [[N]], ptr [[N_ADDR]], align 8
2132 // CHECK2-NEXT:    store ptr [[AA]], ptr [[AA_ADDR]], align 8
2133 // CHECK2-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8
2134 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
2135 // CHECK2-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
2136 // CHECK2-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
2137 // CHECK2-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
2138 // CHECK2-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1
2139 // CHECK2-NEXT:    [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
2140 // CHECK2-NEXT:    store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
2141 // CHECK2-NEXT:    store i32 0, ptr [[I]], align 4
2142 // CHECK2-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
2143 // CHECK2-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]
2144 // CHECK2-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
2145 // CHECK2:       omp.precond.then:
2146 // CHECK2-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
2147 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
2148 // CHECK2-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4
2149 // CHECK2-NEXT:    [[TMP5:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
2150 // CHECK2-NEXT:    [[CONV:%.*]] = trunc i64 [[TMP5]] to i32
2151 // CHECK2-NEXT:    [[TMP6:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
2152 // CHECK2-NEXT:    [[CONV3:%.*]] = trunc i64 [[TMP6]] to i32
2153 // CHECK2-NEXT:    store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
2154 // CHECK2-NEXT:    store i32 [[CONV3]], ptr [[DOTOMP_UB]], align 4
2155 // CHECK2-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
2156 // CHECK2-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2157 // CHECK2-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
2158 // CHECK2-NEXT:    [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
2159 // CHECK2-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP8]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
2160 // CHECK2-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
2161 // CHECK2-NEXT:    store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4
2162 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2163 // CHECK2:       omp.inner.for.cond:
2164 // CHECK2-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2165 // CHECK2-NEXT:    [[CONV5:%.*]] = sext i32 [[TMP10]] to i64
2166 // CHECK2-NEXT:    [[TMP11:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
2167 // CHECK2-NEXT:    [[CMP6:%.*]] = icmp ule i64 [[CONV5]], [[TMP11]]
2168 // CHECK2-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2169 // CHECK2:       omp.inner.for.body:
2170 // CHECK2-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2171 // CHECK2-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
2172 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2173 // CHECK2-NEXT:    store i32 [[ADD]], ptr [[I4]], align 4
2174 // CHECK2-NEXT:    [[TMP13:%.*]] = load i32, ptr [[I4]], align 4
2175 // CHECK2-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64
2176 // CHECK2-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], ptr [[TMP0]], i64 0, i64 [[IDXPROM]]
2177 // CHECK2-NEXT:    [[TMP14:%.*]] = load i16, ptr [[ARRAYIDX]], align 2
2178 // CHECK2-NEXT:    [[CONV7:%.*]] = sext i16 [[TMP14]] to i32
2179 // CHECK2-NEXT:    [[ADD8:%.*]] = add nsw i32 [[CONV7]], 1
2180 // CHECK2-NEXT:    [[CONV9:%.*]] = trunc i32 [[ADD8]] to i16
2181 // CHECK2-NEXT:    store i16 [[CONV9]], ptr [[ARRAYIDX]], align 2
2182 // CHECK2-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2183 // CHECK2:       omp.body.continue:
2184 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2185 // CHECK2:       omp.inner.for.inc:
2186 // CHECK2-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2187 // CHECK2-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
2188 // CHECK2-NEXT:    [[ADD10:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
2189 // CHECK2-NEXT:    store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4
2190 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND]]
2191 // CHECK2:       omp.inner.for.end:
2192 // CHECK2-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2193 // CHECK2:       omp.loop.exit:
2194 // CHECK2-NEXT:    [[TMP17:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
2195 // CHECK2-NEXT:    [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 4
2196 // CHECK2-NEXT:    call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP18]])
2197 // CHECK2-NEXT:    br label [[OMP_PRECOND_END]]
2198 // CHECK2:       omp.precond.end:
2199 // CHECK2-NEXT:    ret void
2200 //
2201 //
2202 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l39
2203 // CHECK2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
2204 // CHECK2-NEXT:  entry:
2205 // CHECK2-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
2206 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
2207 // CHECK2-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
2208 // CHECK2-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
2209 // CHECK2-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
2210 // CHECK2-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
2211 // CHECK2-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
2212 // CHECK2-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l39_kernel_environment, ptr [[DYN_PTR]])
2213 // CHECK2-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
2214 // CHECK2-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
2215 // CHECK2:       user_code.entry:
2216 // CHECK2-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
2217 // CHECK2-NEXT:    store i32 0, ptr [[DOTZERO_ADDR]], align 4
2218 // CHECK2-NEXT:    store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4
2219 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l39_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]]) #[[ATTR2]]
2220 // CHECK2-NEXT:    call void @__kmpc_target_deinit()
2221 // CHECK2-NEXT:    ret void
2222 // CHECK2:       worker.exit:
2223 // CHECK2-NEXT:    ret void
2224 //
2225 //
2226 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l39_omp_outlined
2227 // CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
2228 // CHECK2-NEXT:  entry:
2229 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
2230 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
2231 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
2232 // CHECK2-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2233 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2234 // CHECK2-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
2235 // CHECK2-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
2236 // CHECK2-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2237 // CHECK2-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2238 // CHECK2-NEXT:    [[I:%.*]] = alloca i32, align 4
2239 // CHECK2-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x ptr], align 8
2240 // CHECK2-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
2241 // CHECK2-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
2242 // CHECK2-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
2243 // CHECK2-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
2244 // CHECK2-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
2245 // CHECK2-NEXT:    store i32 9, ptr [[DOTOMP_COMB_UB]], align 4
2246 // CHECK2-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
2247 // CHECK2-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2248 // CHECK2-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
2249 // CHECK2-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
2250 // CHECK2-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
2251 // CHECK2-NEXT:    call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP2]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
2252 // CHECK2-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2253 // CHECK2-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
2254 // CHECK2-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2255 // CHECK2:       cond.true:
2256 // CHECK2-NEXT:    br label [[COND_END:%.*]]
2257 // CHECK2:       cond.false:
2258 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2259 // CHECK2-NEXT:    br label [[COND_END]]
2260 // CHECK2:       cond.end:
2261 // CHECK2-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
2262 // CHECK2-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
2263 // CHECK2-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
2264 // CHECK2-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
2265 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2266 // CHECK2:       omp.inner.for.cond:
2267 // CHECK2-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2268 // CHECK2-NEXT:    [[CMP1:%.*]] = icmp slt i32 [[TMP6]], 10
2269 // CHECK2-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2270 // CHECK2:       omp.inner.for.body:
2271 // CHECK2-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
2272 // CHECK2-NEXT:    [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
2273 // CHECK2-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2274 // CHECK2-NEXT:    [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
2275 // CHECK2-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
2276 // CHECK2-NEXT:    [[TMP12:%.*]] = inttoptr i64 [[TMP8]] to ptr
2277 // CHECK2-NEXT:    store ptr [[TMP12]], ptr [[TMP11]], align 8
2278 // CHECK2-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
2279 // CHECK2-NEXT:    [[TMP14:%.*]] = inttoptr i64 [[TMP10]] to ptr
2280 // CHECK2-NEXT:    store ptr [[TMP14]], ptr [[TMP13]], align 8
2281 // CHECK2-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
2282 // CHECK2-NEXT:    store ptr [[TMP0]], ptr [[TMP15]], align 8
2283 // CHECK2-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l39_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 3)
2284 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2285 // CHECK2:       omp.inner.for.inc:
2286 // CHECK2-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2287 // CHECK2-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
2288 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
2289 // CHECK2-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
2290 // CHECK2-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
2291 // CHECK2-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
2292 // CHECK2-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
2293 // CHECK2-NEXT:    store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4
2294 // CHECK2-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2295 // CHECK2-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
2296 // CHECK2-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]
2297 // CHECK2-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4
2298 // CHECK2-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2299 // CHECK2-NEXT:    [[CMP4:%.*]] = icmp sgt i32 [[TMP22]], 9
2300 // CHECK2-NEXT:    br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
2301 // CHECK2:       cond.true5:
2302 // CHECK2-NEXT:    br label [[COND_END7:%.*]]
2303 // CHECK2:       cond.false6:
2304 // CHECK2-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2305 // CHECK2-NEXT:    br label [[COND_END7]]
2306 // CHECK2:       cond.end7:
2307 // CHECK2-NEXT:    [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP23]], [[COND_FALSE6]] ]
2308 // CHECK2-NEXT:    store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4
2309 // CHECK2-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
2310 // CHECK2-NEXT:    store i32 [[TMP24]], ptr [[DOTOMP_IV]], align 4
2311 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND]]
2312 // CHECK2:       omp.inner.for.end:
2313 // CHECK2-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2314 // CHECK2:       omp.loop.exit:
2315 // CHECK2-NEXT:    call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP2]])
2316 // CHECK2-NEXT:    ret void
2317 //
2318 //
2319 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l39_omp_outlined_omp_outlined
2320 // CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
2321 // CHECK2-NEXT:  entry:
2322 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
2323 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
2324 // CHECK2-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
2325 // CHECK2-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
2326 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
2327 // CHECK2-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2328 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2329 // CHECK2-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2330 // CHECK2-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2331 // CHECK2-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2332 // CHECK2-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2333 // CHECK2-NEXT:    [[I:%.*]] = alloca i32, align 4
2334 // CHECK2-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
2335 // CHECK2-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
2336 // CHECK2-NEXT:    store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
2337 // CHECK2-NEXT:    store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
2338 // CHECK2-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
2339 // CHECK2-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
2340 // CHECK2-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
2341 // CHECK2-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4
2342 // CHECK2-NEXT:    [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
2343 // CHECK2-NEXT:    [[CONV:%.*]] = trunc i64 [[TMP1]] to i32
2344 // CHECK2-NEXT:    [[TMP2:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
2345 // CHECK2-NEXT:    [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32
2346 // CHECK2-NEXT:    store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
2347 // CHECK2-NEXT:    store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4
2348 // CHECK2-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
2349 // CHECK2-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2350 // CHECK2-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
2351 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
2352 // CHECK2-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP4]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
2353 // CHECK2-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
2354 // CHECK2-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
2355 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2356 // CHECK2:       omp.inner.for.cond:
2357 // CHECK2-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2358 // CHECK2-NEXT:    [[CONV2:%.*]] = sext i32 [[TMP6]] to i64
2359 // CHECK2-NEXT:    [[TMP7:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
2360 // CHECK2-NEXT:    [[CMP:%.*]] = icmp ule i64 [[CONV2]], [[TMP7]]
2361 // CHECK2-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2362 // CHECK2:       omp.inner.for.body:
2363 // CHECK2-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2364 // CHECK2-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
2365 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2366 // CHECK2-NEXT:    store i32 [[ADD]], ptr [[I]], align 4
2367 // CHECK2-NEXT:    [[TMP9:%.*]] = load i32, ptr [[I]], align 4
2368 // CHECK2-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64
2369 // CHECK2-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]]
2370 // CHECK2-NEXT:    [[TMP10:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
2371 // CHECK2-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
2372 // CHECK2-NEXT:    store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4
2373 // CHECK2-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2374 // CHECK2:       omp.body.continue:
2375 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2376 // CHECK2:       omp.inner.for.inc:
2377 // CHECK2-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2378 // CHECK2-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
2379 // CHECK2-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
2380 // CHECK2-NEXT:    store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4
2381 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND]]
2382 // CHECK2:       omp.inner.for.end:
2383 // CHECK2-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2384 // CHECK2:       omp.loop.exit:
2385 // CHECK2-NEXT:    call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP4]])
2386 // CHECK2-NEXT:    ret void
2387 //
2388 //
2389 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l44
2390 // CHECK2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i64 noundef [[F:%.*]]) #[[ATTR0]] {
2391 // CHECK2-NEXT:  entry:
2392 // CHECK2-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
2393 // CHECK2-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
2394 // CHECK2-NEXT:    [[F_ADDR:%.*]] = alloca i64, align 8
2395 // CHECK2-NEXT:    [[F_CASTED:%.*]] = alloca i64, align 8
2396 // CHECK2-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
2397 // CHECK2-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
2398 // CHECK2-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
2399 // CHECK2-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
2400 // CHECK2-NEXT:    store i64 [[F]], ptr [[F_ADDR]], align 8
2401 // CHECK2-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8
2402 // CHECK2-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l44_kernel_environment, ptr [[DYN_PTR]])
2403 // CHECK2-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
2404 // CHECK2-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
2405 // CHECK2:       user_code.entry:
2406 // CHECK2-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
2407 // CHECK2-NEXT:    [[TMP3:%.*]] = load i32, ptr [[F_ADDR]], align 4
2408 // CHECK2-NEXT:    store i32 [[TMP3]], ptr [[F_CASTED]], align 4
2409 // CHECK2-NEXT:    [[TMP4:%.*]] = load i64, ptr [[F_CASTED]], align 8
2410 // CHECK2-NEXT:    store i32 0, ptr [[DOTZERO_ADDR]], align 4
2411 // CHECK2-NEXT:    store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4
2412 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l44_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]], i64 [[TMP4]]) #[[ATTR2]]
2413 // CHECK2-NEXT:    call void @__kmpc_target_deinit()
2414 // CHECK2-NEXT:    ret void
2415 // CHECK2:       worker.exit:
2416 // CHECK2-NEXT:    ret void
2417 //
2418 //
2419 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l44_omp_outlined
2420 // CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i64 noundef [[F:%.*]]) #[[ATTR1]] {
2421 // CHECK2-NEXT:  entry:
2422 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
2423 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
2424 // CHECK2-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
2425 // CHECK2-NEXT:    [[F_ADDR:%.*]] = alloca i64, align 8
2426 // CHECK2-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2427 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2428 // CHECK2-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
2429 // CHECK2-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
2430 // CHECK2-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
2431 // CHECK2-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2432 // CHECK2-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2433 // CHECK2-NEXT:    [[K:%.*]] = alloca i32, align 4
2434 // CHECK2-NEXT:    [[I:%.*]] = alloca i32, align 4
2435 // CHECK2-NEXT:    [[J:%.*]] = alloca i32, align 4
2436 // CHECK2-NEXT:    [[F_CASTED:%.*]] = alloca i64, align 8
2437 // CHECK2-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [4 x ptr], align 8
2438 // CHECK2-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
2439 // CHECK2-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
2440 // CHECK2-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
2441 // CHECK2-NEXT:    store i64 [[F]], ptr [[F_ADDR]], align 8
2442 // CHECK2-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8
2443 // CHECK2-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
2444 // CHECK2-NEXT:    store i32 99, ptr [[DOTOMP_COMB_UB]], align 4
2445 // CHECK2-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
2446 // CHECK2-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2447 // CHECK2-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
2448 // CHECK2-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
2449 // CHECK2-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
2450 // CHECK2-NEXT:    call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP2]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
2451 // CHECK2-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2452 // CHECK2-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 99
2453 // CHECK2-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2454 // CHECK2:       cond.true:
2455 // CHECK2-NEXT:    br label [[COND_END:%.*]]
2456 // CHECK2:       cond.false:
2457 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2458 // CHECK2-NEXT:    br label [[COND_END]]
2459 // CHECK2:       cond.end:
2460 // CHECK2-NEXT:    [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
2461 // CHECK2-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
2462 // CHECK2-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
2463 // CHECK2-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
2464 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2465 // CHECK2:       omp.inner.for.cond:
2466 // CHECK2-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2467 // CHECK2-NEXT:    [[CMP2:%.*]] = icmp slt i32 [[TMP6]], 100
2468 // CHECK2-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2469 // CHECK2:       omp.inner.for.body:
2470 // CHECK2-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
2471 // CHECK2-NEXT:    [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
2472 // CHECK2-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2473 // CHECK2-NEXT:    [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
2474 // CHECK2-NEXT:    [[TMP11:%.*]] = load i32, ptr [[F_ADDR]], align 4
2475 // CHECK2-NEXT:    store i32 [[TMP11]], ptr [[F_CASTED]], align 4
2476 // CHECK2-NEXT:    [[TMP12:%.*]] = load i64, ptr [[F_CASTED]], align 8
2477 // CHECK2-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
2478 // CHECK2-NEXT:    [[TMP14:%.*]] = inttoptr i64 [[TMP8]] to ptr
2479 // CHECK2-NEXT:    store ptr [[TMP14]], ptr [[TMP13]], align 8
2480 // CHECK2-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
2481 // CHECK2-NEXT:    [[TMP16:%.*]] = inttoptr i64 [[TMP10]] to ptr
2482 // CHECK2-NEXT:    store ptr [[TMP16]], ptr [[TMP15]], align 8
2483 // CHECK2-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
2484 // CHECK2-NEXT:    store ptr [[TMP0]], ptr [[TMP17]], align 8
2485 // CHECK2-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3
2486 // CHECK2-NEXT:    [[TMP19:%.*]] = inttoptr i64 [[TMP12]] to ptr
2487 // CHECK2-NEXT:    store ptr [[TMP19]], ptr [[TMP18]], align 8
2488 // CHECK2-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l44_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 4)
2489 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2490 // CHECK2:       omp.inner.for.inc:
2491 // CHECK2-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2492 // CHECK2-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
2493 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]
2494 // CHECK2-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
2495 // CHECK2-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
2496 // CHECK2-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
2497 // CHECK2-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]
2498 // CHECK2-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_COMB_LB]], align 4
2499 // CHECK2-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2500 // CHECK2-NEXT:    [[TMP25:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
2501 // CHECK2-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP24]], [[TMP25]]
2502 // CHECK2-NEXT:    store i32 [[ADD4]], ptr [[DOTOMP_COMB_UB]], align 4
2503 // CHECK2-NEXT:    [[TMP26:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2504 // CHECK2-NEXT:    [[CMP5:%.*]] = icmp sgt i32 [[TMP26]], 99
2505 // CHECK2-NEXT:    br i1 [[CMP5]], label [[COND_TRUE6:%.*]], label [[COND_FALSE7:%.*]]
2506 // CHECK2:       cond.true6:
2507 // CHECK2-NEXT:    br label [[COND_END8:%.*]]
2508 // CHECK2:       cond.false7:
2509 // CHECK2-NEXT:    [[TMP27:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2510 // CHECK2-NEXT:    br label [[COND_END8]]
2511 // CHECK2:       cond.end8:
2512 // CHECK2-NEXT:    [[COND9:%.*]] = phi i32 [ 99, [[COND_TRUE6]] ], [ [[TMP27]], [[COND_FALSE7]] ]
2513 // CHECK2-NEXT:    store i32 [[COND9]], ptr [[DOTOMP_COMB_UB]], align 4
2514 // CHECK2-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
2515 // CHECK2-NEXT:    store i32 [[TMP28]], ptr [[DOTOMP_IV]], align 4
2516 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND]]
2517 // CHECK2:       omp.inner.for.end:
2518 // CHECK2-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2519 // CHECK2:       omp.loop.exit:
2520 // CHECK2-NEXT:    call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP2]])
2521 // CHECK2-NEXT:    ret void
2522 //
2523 //
2524 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l44_omp_outlined_omp_outlined
2525 // CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i64 noundef [[F:%.*]]) #[[ATTR1]] {
2526 // CHECK2-NEXT:  entry:
2527 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
2528 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
2529 // CHECK2-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
2530 // CHECK2-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
2531 // CHECK2-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
2532 // CHECK2-NEXT:    [[F_ADDR:%.*]] = alloca i64, align 8
2533 // CHECK2-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2534 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2535 // CHECK2-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
2536 // CHECK2-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2537 // CHECK2-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2538 // CHECK2-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2539 // CHECK2-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2540 // CHECK2-NEXT:    [[K:%.*]] = alloca i32, align 4
2541 // CHECK2-NEXT:    [[I:%.*]] = alloca i32, align 4
2542 // CHECK2-NEXT:    [[J:%.*]] = alloca i32, align 4
2543 // CHECK2-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
2544 // CHECK2-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
2545 // CHECK2-NEXT:    store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
2546 // CHECK2-NEXT:    store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
2547 // CHECK2-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
2548 // CHECK2-NEXT:    store i64 [[F]], ptr [[F_ADDR]], align 8
2549 // CHECK2-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8
2550 // CHECK2-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
2551 // CHECK2-NEXT:    store i32 99, ptr [[DOTOMP_UB]], align 4
2552 // CHECK2-NEXT:    [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
2553 // CHECK2-NEXT:    [[CONV:%.*]] = trunc i64 [[TMP1]] to i32
2554 // CHECK2-NEXT:    [[TMP2:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
2555 // CHECK2-NEXT:    [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32
2556 // CHECK2-NEXT:    store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
2557 // CHECK2-NEXT:    store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4
2558 // CHECK2-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
2559 // CHECK2-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2560 // CHECK2-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
2561 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
2562 // CHECK2-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP4]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
2563 // CHECK2-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
2564 // CHECK2-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
2565 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2566 // CHECK2:       omp.inner.for.cond:
2567 // CHECK2-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2568 // CHECK2-NEXT:    [[CONV3:%.*]] = sext i32 [[TMP6]] to i64
2569 // CHECK2-NEXT:    [[TMP7:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
2570 // CHECK2-NEXT:    [[CMP:%.*]] = icmp ule i64 [[CONV3]], [[TMP7]]
2571 // CHECK2-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2572 // CHECK2:       omp.inner.for.body:
2573 // CHECK2-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2574 // CHECK2-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP8]], 10
2575 // CHECK2-NEXT:    [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
2576 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2577 // CHECK2-NEXT:    store i32 [[ADD]], ptr [[I]], align 4
2578 // CHECK2-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2579 // CHECK2-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2580 // CHECK2-NEXT:    [[DIV4:%.*]] = sdiv i32 [[TMP10]], 10
2581 // CHECK2-NEXT:    [[MUL5:%.*]] = mul nsw i32 [[DIV4]], 10
2582 // CHECK2-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL5]]
2583 // CHECK2-NEXT:    [[MUL6:%.*]] = mul nsw i32 [[SUB]], 1
2584 // CHECK2-NEXT:    [[ADD7:%.*]] = add nsw i32 0, [[MUL6]]
2585 // CHECK2-NEXT:    store i32 [[ADD7]], ptr [[J]], align 4
2586 // CHECK2-NEXT:    store i32 10, ptr [[K]], align 4
2587 // CHECK2-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 4
2588 // CHECK2-NEXT:    [[TMP12:%.*]] = load i32, ptr [[J]], align 4
2589 // CHECK2-NEXT:    [[TMP13:%.*]] = load i32, ptr [[F_ADDR]], align 4
2590 // CHECK2-NEXT:    [[MUL8:%.*]] = mul nsw i32 [[TMP12]], [[TMP13]]
2591 // CHECK2-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP11]], [[MUL8]]
2592 // CHECK2-NEXT:    [[TMP14:%.*]] = load i32, ptr [[K]], align 4
2593 // CHECK2-NEXT:    [[ADD10:%.*]] = add nsw i32 [[ADD9]], [[TMP14]]
2594 // CHECK2-NEXT:    [[TMP15:%.*]] = load i32, ptr [[I]], align 4
2595 // CHECK2-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64
2596 // CHECK2-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP0]], i64 0, i64 [[IDXPROM]]
2597 // CHECK2-NEXT:    [[TMP16:%.*]] = load i32, ptr [[J]], align 4
2598 // CHECK2-NEXT:    [[IDXPROM11:%.*]] = sext i32 [[TMP16]] to i64
2599 // CHECK2-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM11]]
2600 // CHECK2-NEXT:    store i32 [[ADD10]], ptr [[ARRAYIDX12]], align 4
2601 // CHECK2-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2602 // CHECK2:       omp.body.continue:
2603 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2604 // CHECK2:       omp.inner.for.inc:
2605 // CHECK2-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2606 // CHECK2-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
2607 // CHECK2-NEXT:    [[ADD13:%.*]] = add nsw i32 [[TMP17]], [[TMP18]]
2608 // CHECK2-NEXT:    store i32 [[ADD13]], ptr [[DOTOMP_IV]], align 4
2609 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND]]
2610 // CHECK2:       omp.inner.for.end:
2611 // CHECK2-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2612 // CHECK2:       omp.loop.exit:
2613 // CHECK2-NEXT:    call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP4]])
2614 // CHECK2-NEXT:    ret void
2615 //
2616 //
2617 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l52
2618 // CHECK2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR0]] {
2619 // CHECK2-NEXT:  entry:
2620 // CHECK2-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
2621 // CHECK2-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
2622 // CHECK2-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
2623 // CHECK2-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8
2624 // CHECK2-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
2625 // CHECK2-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
2626 // CHECK2-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
2627 // CHECK2-NEXT:    store i64 [[N]], ptr [[N_ADDR]], align 8
2628 // CHECK2-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
2629 // CHECK2-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8
2630 // CHECK2-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l52_kernel_environment, ptr [[DYN_PTR]])
2631 // CHECK2-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
2632 // CHECK2-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
2633 // CHECK2:       user_code.entry:
2634 // CHECK2-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
2635 // CHECK2-NEXT:    [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4
2636 // CHECK2-NEXT:    store i32 [[TMP3]], ptr [[N_CASTED]], align 4
2637 // CHECK2-NEXT:    [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8
2638 // CHECK2-NEXT:    store i32 0, ptr [[DOTZERO_ADDR]], align 4
2639 // CHECK2-NEXT:    store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4
2640 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l52_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i64 [[TMP4]], ptr [[TMP0]]) #[[ATTR2]]
2641 // CHECK2-NEXT:    call void @__kmpc_target_deinit()
2642 // CHECK2-NEXT:    ret void
2643 // CHECK2:       worker.exit:
2644 // CHECK2-NEXT:    ret void
2645 //
2646 //
2647 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l52_omp_outlined
2648 // CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR1]] {
2649 // CHECK2-NEXT:  entry:
2650 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
2651 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
2652 // CHECK2-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
2653 // CHECK2-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
2654 // CHECK2-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2655 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2656 // CHECK2-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
2657 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
2658 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
2659 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4
2660 // CHECK2-NEXT:    [[I:%.*]] = alloca i32, align 4
2661 // CHECK2-NEXT:    [[J:%.*]] = alloca i32, align 4
2662 // CHECK2-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
2663 // CHECK2-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
2664 // CHECK2-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2665 // CHECK2-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2666 // CHECK2-NEXT:    [[I8:%.*]] = alloca i32, align 4
2667 // CHECK2-NEXT:    [[J9:%.*]] = alloca i32, align 4
2668 // CHECK2-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8
2669 // CHECK2-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [4 x ptr], align 8
2670 // CHECK2-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
2671 // CHECK2-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
2672 // CHECK2-NEXT:    store i64 [[N]], ptr [[N_ADDR]], align 8
2673 // CHECK2-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
2674 // CHECK2-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8
2675 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
2676 // CHECK2-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
2677 // CHECK2-NEXT:    [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
2678 // CHECK2-NEXT:    store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_2]], align 4
2679 // CHECK2-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
2680 // CHECK2-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
2681 // CHECK2-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1
2682 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
2683 // CHECK2-NEXT:    [[SUB4:%.*]] = sub nsw i32 [[TMP4]], 0
2684 // CHECK2-NEXT:    [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1
2685 // CHECK2-NEXT:    [[MUL:%.*]] = mul nsw i32 [[DIV]], [[DIV5]]
2686 // CHECK2-NEXT:    [[SUB6:%.*]] = sub nsw i32 [[MUL]], 1
2687 // CHECK2-NEXT:    store i32 [[SUB6]], ptr [[DOTCAPTURE_EXPR_3]], align 4
2688 // CHECK2-NEXT:    store i32 0, ptr [[I]], align 4
2689 // CHECK2-NEXT:    store i32 0, ptr [[J]], align 4
2690 // CHECK2-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
2691 // CHECK2-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP5]]
2692 // CHECK2-NEXT:    br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]]
2693 // CHECK2:       land.lhs.true:
2694 // CHECK2-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
2695 // CHECK2-NEXT:    [[CMP7:%.*]] = icmp slt i32 0, [[TMP6]]
2696 // CHECK2-NEXT:    br i1 [[CMP7]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]]
2697 // CHECK2:       omp.precond.then:
2698 // CHECK2-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
2699 // CHECK2-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4
2700 // CHECK2-NEXT:    store i32 [[TMP7]], ptr [[DOTOMP_COMB_UB]], align 4
2701 // CHECK2-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
2702 // CHECK2-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2703 // CHECK2-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
2704 // CHECK2-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
2705 // CHECK2-NEXT:    [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
2706 // CHECK2-NEXT:    call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP9]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
2707 // CHECK2-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2708 // CHECK2-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4
2709 // CHECK2-NEXT:    [[CMP10:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]]
2710 // CHECK2-NEXT:    br i1 [[CMP10]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2711 // CHECK2:       cond.true:
2712 // CHECK2-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4
2713 // CHECK2-NEXT:    br label [[COND_END:%.*]]
2714 // CHECK2:       cond.false:
2715 // CHECK2-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2716 // CHECK2-NEXT:    br label [[COND_END]]
2717 // CHECK2:       cond.end:
2718 // CHECK2-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ]
2719 // CHECK2-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
2720 // CHECK2-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
2721 // CHECK2-NEXT:    store i32 [[TMP14]], ptr [[DOTOMP_IV]], align 4
2722 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2723 // CHECK2:       omp.inner.for.cond:
2724 // CHECK2-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2725 // CHECK2-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4
2726 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP16]], 1
2727 // CHECK2-NEXT:    [[CMP11:%.*]] = icmp slt i32 [[TMP15]], [[ADD]]
2728 // CHECK2-NEXT:    br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2729 // CHECK2:       omp.inner.for.body:
2730 // CHECK2-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
2731 // CHECK2-NEXT:    [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
2732 // CHECK2-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2733 // CHECK2-NEXT:    [[TMP20:%.*]] = zext i32 [[TMP19]] to i64
2734 // CHECK2-NEXT:    [[TMP21:%.*]] = load i32, ptr [[N_ADDR]], align 4
2735 // CHECK2-NEXT:    store i32 [[TMP21]], ptr [[N_CASTED]], align 4
2736 // CHECK2-NEXT:    [[TMP22:%.*]] = load i64, ptr [[N_CASTED]], align 8
2737 // CHECK2-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
2738 // CHECK2-NEXT:    [[TMP24:%.*]] = inttoptr i64 [[TMP18]] to ptr
2739 // CHECK2-NEXT:    store ptr [[TMP24]], ptr [[TMP23]], align 8
2740 // CHECK2-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
2741 // CHECK2-NEXT:    [[TMP26:%.*]] = inttoptr i64 [[TMP20]] to ptr
2742 // CHECK2-NEXT:    store ptr [[TMP26]], ptr [[TMP25]], align 8
2743 // CHECK2-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
2744 // CHECK2-NEXT:    [[TMP28:%.*]] = inttoptr i64 [[TMP22]] to ptr
2745 // CHECK2-NEXT:    store ptr [[TMP28]], ptr [[TMP27]], align 8
2746 // CHECK2-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3
2747 // CHECK2-NEXT:    store ptr [[TMP0]], ptr [[TMP29]], align 8
2748 // CHECK2-NEXT:    [[TMP30:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
2749 // CHECK2-NEXT:    [[TMP31:%.*]] = load i32, ptr [[TMP30]], align 4
2750 // CHECK2-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP31]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l52_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 4)
2751 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2752 // CHECK2:       omp.inner.for.inc:
2753 // CHECK2-NEXT:    [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2754 // CHECK2-NEXT:    [[TMP33:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
2755 // CHECK2-NEXT:    [[ADD12:%.*]] = add nsw i32 [[TMP32]], [[TMP33]]
2756 // CHECK2-NEXT:    store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4
2757 // CHECK2-NEXT:    [[TMP34:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
2758 // CHECK2-NEXT:    [[TMP35:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
2759 // CHECK2-NEXT:    [[ADD13:%.*]] = add nsw i32 [[TMP34]], [[TMP35]]
2760 // CHECK2-NEXT:    store i32 [[ADD13]], ptr [[DOTOMP_COMB_LB]], align 4
2761 // CHECK2-NEXT:    [[TMP36:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2762 // CHECK2-NEXT:    [[TMP37:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
2763 // CHECK2-NEXT:    [[ADD14:%.*]] = add nsw i32 [[TMP36]], [[TMP37]]
2764 // CHECK2-NEXT:    store i32 [[ADD14]], ptr [[DOTOMP_COMB_UB]], align 4
2765 // CHECK2-NEXT:    [[TMP38:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2766 // CHECK2-NEXT:    [[TMP39:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4
2767 // CHECK2-NEXT:    [[CMP15:%.*]] = icmp sgt i32 [[TMP38]], [[TMP39]]
2768 // CHECK2-NEXT:    br i1 [[CMP15]], label [[COND_TRUE16:%.*]], label [[COND_FALSE17:%.*]]
2769 // CHECK2:       cond.true16:
2770 // CHECK2-NEXT:    [[TMP40:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4
2771 // CHECK2-NEXT:    br label [[COND_END18:%.*]]
2772 // CHECK2:       cond.false17:
2773 // CHECK2-NEXT:    [[TMP41:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2774 // CHECK2-NEXT:    br label [[COND_END18]]
2775 // CHECK2:       cond.end18:
2776 // CHECK2-NEXT:    [[COND19:%.*]] = phi i32 [ [[TMP40]], [[COND_TRUE16]] ], [ [[TMP41]], [[COND_FALSE17]] ]
2777 // CHECK2-NEXT:    store i32 [[COND19]], ptr [[DOTOMP_COMB_UB]], align 4
2778 // CHECK2-NEXT:    [[TMP42:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
2779 // CHECK2-NEXT:    store i32 [[TMP42]], ptr [[DOTOMP_IV]], align 4
2780 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND]]
2781 // CHECK2:       omp.inner.for.end:
2782 // CHECK2-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2783 // CHECK2:       omp.loop.exit:
2784 // CHECK2-NEXT:    [[TMP43:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
2785 // CHECK2-NEXT:    [[TMP44:%.*]] = load i32, ptr [[TMP43]], align 4
2786 // CHECK2-NEXT:    call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP44]])
2787 // CHECK2-NEXT:    br label [[OMP_PRECOND_END]]
2788 // CHECK2:       omp.precond.end:
2789 // CHECK2-NEXT:    ret void
2790 //
2791 //
2792 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l52_omp_outlined_omp_outlined
2793 // CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR1]] {
2794 // CHECK2-NEXT:  entry:
2795 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
2796 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
2797 // CHECK2-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
2798 // CHECK2-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
2799 // CHECK2-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
2800 // CHECK2-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
2801 // CHECK2-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2802 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2803 // CHECK2-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
2804 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
2805 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
2806 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4
2807 // CHECK2-NEXT:    [[I:%.*]] = alloca i32, align 4
2808 // CHECK2-NEXT:    [[J:%.*]] = alloca i32, align 4
2809 // CHECK2-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2810 // CHECK2-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2811 // CHECK2-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2812 // CHECK2-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2813 // CHECK2-NEXT:    [[I9:%.*]] = alloca i32, align 4
2814 // CHECK2-NEXT:    [[J10:%.*]] = alloca i32, align 4
2815 // CHECK2-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
2816 // CHECK2-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
2817 // CHECK2-NEXT:    store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
2818 // CHECK2-NEXT:    store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
2819 // CHECK2-NEXT:    store i64 [[N]], ptr [[N_ADDR]], align 8
2820 // CHECK2-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
2821 // CHECK2-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8
2822 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
2823 // CHECK2-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
2824 // CHECK2-NEXT:    [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
2825 // CHECK2-NEXT:    store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_2]], align 4
2826 // CHECK2-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
2827 // CHECK2-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
2828 // CHECK2-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1
2829 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
2830 // CHECK2-NEXT:    [[SUB4:%.*]] = sub nsw i32 [[TMP4]], 0
2831 // CHECK2-NEXT:    [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1
2832 // CHECK2-NEXT:    [[MUL:%.*]] = mul nsw i32 [[DIV]], [[DIV5]]
2833 // CHECK2-NEXT:    [[SUB6:%.*]] = sub nsw i32 [[MUL]], 1
2834 // CHECK2-NEXT:    store i32 [[SUB6]], ptr [[DOTCAPTURE_EXPR_3]], align 4
2835 // CHECK2-NEXT:    store i32 0, ptr [[I]], align 4
2836 // CHECK2-NEXT:    store i32 0, ptr [[J]], align 4
2837 // CHECK2-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
2838 // CHECK2-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP5]]
2839 // CHECK2-NEXT:    br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]]
2840 // CHECK2:       land.lhs.true:
2841 // CHECK2-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
2842 // CHECK2-NEXT:    [[CMP7:%.*]] = icmp slt i32 0, [[TMP6]]
2843 // CHECK2-NEXT:    br i1 [[CMP7]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]]
2844 // CHECK2:       omp.precond.then:
2845 // CHECK2-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
2846 // CHECK2-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4
2847 // CHECK2-NEXT:    store i32 [[TMP7]], ptr [[DOTOMP_UB]], align 4
2848 // CHECK2-NEXT:    [[TMP8:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
2849 // CHECK2-NEXT:    [[CONV:%.*]] = trunc i64 [[TMP8]] to i32
2850 // CHECK2-NEXT:    [[TMP9:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
2851 // CHECK2-NEXT:    [[CONV8:%.*]] = trunc i64 [[TMP9]] to i32
2852 // CHECK2-NEXT:    store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
2853 // CHECK2-NEXT:    store i32 [[CONV8]], ptr [[DOTOMP_UB]], align 4
2854 // CHECK2-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
2855 // CHECK2-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2856 // CHECK2-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
2857 // CHECK2-NEXT:    [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4
2858 // CHECK2-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP11]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
2859 // CHECK2-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
2860 // CHECK2-NEXT:    store i32 [[TMP12]], ptr [[DOTOMP_IV]], align 4
2861 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2862 // CHECK2:       omp.inner.for.cond:
2863 // CHECK2-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2864 // CHECK2-NEXT:    [[CONV11:%.*]] = sext i32 [[TMP13]] to i64
2865 // CHECK2-NEXT:    [[TMP14:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
2866 // CHECK2-NEXT:    [[CMP12:%.*]] = icmp ule i64 [[CONV11]], [[TMP14]]
2867 // CHECK2-NEXT:    br i1 [[CMP12]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2868 // CHECK2:       omp.inner.for.body:
2869 // CHECK2-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2870 // CHECK2-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
2871 // CHECK2-NEXT:    [[SUB13:%.*]] = sub nsw i32 [[TMP16]], 0
2872 // CHECK2-NEXT:    [[DIV14:%.*]] = sdiv i32 [[SUB13]], 1
2873 // CHECK2-NEXT:    [[MUL15:%.*]] = mul nsw i32 1, [[DIV14]]
2874 // CHECK2-NEXT:    [[DIV16:%.*]] = sdiv i32 [[TMP15]], [[MUL15]]
2875 // CHECK2-NEXT:    [[MUL17:%.*]] = mul nsw i32 [[DIV16]], 1
2876 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL17]]
2877 // CHECK2-NEXT:    store i32 [[ADD]], ptr [[I9]], align 4
2878 // CHECK2-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2879 // CHECK2-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2880 // CHECK2-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
2881 // CHECK2-NEXT:    [[SUB18:%.*]] = sub nsw i32 [[TMP19]], 0
2882 // CHECK2-NEXT:    [[DIV19:%.*]] = sdiv i32 [[SUB18]], 1
2883 // CHECK2-NEXT:    [[MUL20:%.*]] = mul nsw i32 1, [[DIV19]]
2884 // CHECK2-NEXT:    [[DIV21:%.*]] = sdiv i32 [[TMP18]], [[MUL20]]
2885 // CHECK2-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
2886 // CHECK2-NEXT:    [[SUB22:%.*]] = sub nsw i32 [[TMP20]], 0
2887 // CHECK2-NEXT:    [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1
2888 // CHECK2-NEXT:    [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]]
2889 // CHECK2-NEXT:    [[MUL25:%.*]] = mul nsw i32 [[DIV21]], [[MUL24]]
2890 // CHECK2-NEXT:    [[SUB26:%.*]] = sub nsw i32 [[TMP17]], [[MUL25]]
2891 // CHECK2-NEXT:    [[MUL27:%.*]] = mul nsw i32 [[SUB26]], 1
2892 // CHECK2-NEXT:    [[ADD28:%.*]] = add nsw i32 0, [[MUL27]]
2893 // CHECK2-NEXT:    store i32 [[ADD28]], ptr [[J10]], align 4
2894 // CHECK2-NEXT:    [[TMP21:%.*]] = load i32, ptr [[I9]], align 4
2895 // CHECK2-NEXT:    [[TMP22:%.*]] = load i32, ptr [[J10]], align 4
2896 // CHECK2-NEXT:    [[ADD29:%.*]] = add nsw i32 [[TMP21]], [[TMP22]]
2897 // CHECK2-NEXT:    [[TMP23:%.*]] = load i32, ptr [[I9]], align 4
2898 // CHECK2-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64
2899 // CHECK2-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP0]], i64 0, i64 [[IDXPROM]]
2900 // CHECK2-NEXT:    [[TMP24:%.*]] = load i32, ptr [[J10]], align 4
2901 // CHECK2-NEXT:    [[IDXPROM30:%.*]] = sext i32 [[TMP24]] to i64
2902 // CHECK2-NEXT:    [[ARRAYIDX31:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM30]]
2903 // CHECK2-NEXT:    store i32 [[ADD29]], ptr [[ARRAYIDX31]], align 4
2904 // CHECK2-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2905 // CHECK2:       omp.body.continue:
2906 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2907 // CHECK2:       omp.inner.for.inc:
2908 // CHECK2-NEXT:    [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2909 // CHECK2-NEXT:    [[TMP26:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
2910 // CHECK2-NEXT:    [[ADD32:%.*]] = add nsw i32 [[TMP25]], [[TMP26]]
2911 // CHECK2-NEXT:    store i32 [[ADD32]], ptr [[DOTOMP_IV]], align 4
2912 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND]]
2913 // CHECK2:       omp.inner.for.end:
2914 // CHECK2-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2915 // CHECK2:       omp.loop.exit:
2916 // CHECK2-NEXT:    [[TMP27:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
2917 // CHECK2-NEXT:    [[TMP28:%.*]] = load i32, ptr [[TMP27]], align 4
2918 // CHECK2-NEXT:    call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP28]])
2919 // CHECK2-NEXT:    br label [[OMP_PRECOND_END]]
2920 // CHECK2:       omp.precond.end:
2921 // CHECK2-NEXT:    ret void
2922 //
2923 //
2924 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l59
2925 // CHECK2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], ptr noundef [[V:%.*]]) #[[ATTR0]] {
2926 // CHECK2-NEXT:  entry:
2927 // CHECK2-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
2928 // CHECK2-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
2929 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
2930 // CHECK2-NEXT:    [[V_ADDR:%.*]] = alloca ptr, align 8
2931 // CHECK2-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8
2932 // CHECK2-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
2933 // CHECK2-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
2934 // CHECK2-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
2935 // CHECK2-NEXT:    store i64 [[N]], ptr [[N_ADDR]], align 8
2936 // CHECK2-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
2937 // CHECK2-NEXT:    store ptr [[V]], ptr [[V_ADDR]], align 8
2938 // CHECK2-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
2939 // CHECK2-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l59_kernel_environment, ptr [[DYN_PTR]])
2940 // CHECK2-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
2941 // CHECK2-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
2942 // CHECK2:       user_code.entry:
2943 // CHECK2-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
2944 // CHECK2-NEXT:    [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4
2945 // CHECK2-NEXT:    store i32 [[TMP3]], ptr [[N_CASTED]], align 4
2946 // CHECK2-NEXT:    [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8
2947 // CHECK2-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[V_ADDR]], align 8
2948 // CHECK2-NEXT:    store i32 0, ptr [[DOTZERO_ADDR]], align 4
2949 // CHECK2-NEXT:    store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4
2950 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l59_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i64 [[TMP4]], ptr [[TMP0]], ptr [[TMP5]]) #[[ATTR2]]
2951 // CHECK2-NEXT:    call void @__kmpc_target_deinit()
2952 // CHECK2-NEXT:    ret void
2953 // CHECK2:       worker.exit:
2954 // CHECK2-NEXT:    ret void
2955 //
2956 //
2957 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l59_omp_outlined
2958 // CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], ptr noundef [[V:%.*]]) #[[ATTR1]] {
2959 // CHECK2-NEXT:  entry:
2960 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
2961 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
2962 // CHECK2-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
2963 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
2964 // CHECK2-NEXT:    [[V_ADDR:%.*]] = alloca ptr, align 8
2965 // CHECK2-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2966 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2967 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
2968 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
2969 // CHECK2-NEXT:    [[I:%.*]] = alloca i32, align 4
2970 // CHECK2-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
2971 // CHECK2-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
2972 // CHECK2-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2973 // CHECK2-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2974 // CHECK2-NEXT:    [[I3:%.*]] = alloca i32, align 4
2975 // CHECK2-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8
2976 // CHECK2-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [5 x ptr], align 8
2977 // CHECK2-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
2978 // CHECK2-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
2979 // CHECK2-NEXT:    store i64 [[N]], ptr [[N_ADDR]], align 8
2980 // CHECK2-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
2981 // CHECK2-NEXT:    store ptr [[V]], ptr [[V_ADDR]], align 8
2982 // CHECK2-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
2983 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
2984 // CHECK2-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
2985 // CHECK2-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
2986 // CHECK2-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
2987 // CHECK2-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1
2988 // CHECK2-NEXT:    [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
2989 // CHECK2-NEXT:    store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
2990 // CHECK2-NEXT:    store i32 0, ptr [[I]], align 4
2991 // CHECK2-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
2992 // CHECK2-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]
2993 // CHECK2-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
2994 // CHECK2:       omp.precond.then:
2995 // CHECK2-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
2996 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
2997 // CHECK2-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_COMB_UB]], align 4
2998 // CHECK2-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
2999 // CHECK2-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
3000 // CHECK2-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
3001 // CHECK2-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
3002 // CHECK2-NEXT:    [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
3003 // CHECK2-NEXT:    call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP6]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
3004 // CHECK2-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
3005 // CHECK2-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
3006 // CHECK2-NEXT:    [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]]
3007 // CHECK2-NEXT:    br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3008 // CHECK2:       cond.true:
3009 // CHECK2-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
3010 // CHECK2-NEXT:    br label [[COND_END:%.*]]
3011 // CHECK2:       cond.false:
3012 // CHECK2-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
3013 // CHECK2-NEXT:    br label [[COND_END]]
3014 // CHECK2:       cond.end:
3015 // CHECK2-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
3016 // CHECK2-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
3017 // CHECK2-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
3018 // CHECK2-NEXT:    store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 4
3019 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
3020 // CHECK2:       omp.inner.for.cond:
3021 // CHECK2-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3022 // CHECK2-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
3023 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP13]], 1
3024 // CHECK2-NEXT:    [[CMP5:%.*]] = icmp slt i32 [[TMP12]], [[ADD]]
3025 // CHECK2-NEXT:    br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3026 // CHECK2:       omp.inner.for.body:
3027 // CHECK2-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
3028 // CHECK2-NEXT:    [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
3029 // CHECK2-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
3030 // CHECK2-NEXT:    [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
3031 // CHECK2-NEXT:    [[TMP18:%.*]] = load i32, ptr [[N_ADDR]], align 4
3032 // CHECK2-NEXT:    store i32 [[TMP18]], ptr [[N_CASTED]], align 4
3033 // CHECK2-NEXT:    [[TMP19:%.*]] = load i64, ptr [[N_CASTED]], align 8
3034 // CHECK2-NEXT:    [[TMP20:%.*]] = load ptr, ptr [[V_ADDR]], align 8
3035 // CHECK2-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
3036 // CHECK2-NEXT:    [[TMP22:%.*]] = inttoptr i64 [[TMP15]] to ptr
3037 // CHECK2-NEXT:    store ptr [[TMP22]], ptr [[TMP21]], align 8
3038 // CHECK2-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
3039 // CHECK2-NEXT:    [[TMP24:%.*]] = inttoptr i64 [[TMP17]] to ptr
3040 // CHECK2-NEXT:    store ptr [[TMP24]], ptr [[TMP23]], align 8
3041 // CHECK2-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
3042 // CHECK2-NEXT:    [[TMP26:%.*]] = inttoptr i64 [[TMP19]] to ptr
3043 // CHECK2-NEXT:    store ptr [[TMP26]], ptr [[TMP25]], align 8
3044 // CHECK2-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3
3045 // CHECK2-NEXT:    store ptr [[TMP0]], ptr [[TMP27]], align 8
3046 // CHECK2-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 4
3047 // CHECK2-NEXT:    store ptr [[TMP20]], ptr [[TMP28]], align 8
3048 // CHECK2-NEXT:    [[TMP29:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
3049 // CHECK2-NEXT:    [[TMP30:%.*]] = load i32, ptr [[TMP29]], align 4
3050 // CHECK2-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP30]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l59_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 5)
3051 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
3052 // CHECK2:       omp.inner.for.inc:
3053 // CHECK2-NEXT:    [[TMP31:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3054 // CHECK2-NEXT:    [[TMP32:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
3055 // CHECK2-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP31]], [[TMP32]]
3056 // CHECK2-NEXT:    store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4
3057 // CHECK2-NEXT:    [[TMP33:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
3058 // CHECK2-NEXT:    [[TMP34:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
3059 // CHECK2-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP33]], [[TMP34]]
3060 // CHECK2-NEXT:    store i32 [[ADD7]], ptr [[DOTOMP_COMB_LB]], align 4
3061 // CHECK2-NEXT:    [[TMP35:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
3062 // CHECK2-NEXT:    [[TMP36:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
3063 // CHECK2-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP35]], [[TMP36]]
3064 // CHECK2-NEXT:    store i32 [[ADD8]], ptr [[DOTOMP_COMB_UB]], align 4
3065 // CHECK2-NEXT:    [[TMP37:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
3066 // CHECK2-NEXT:    [[TMP38:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
3067 // CHECK2-NEXT:    [[CMP9:%.*]] = icmp sgt i32 [[TMP37]], [[TMP38]]
3068 // CHECK2-NEXT:    br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]]
3069 // CHECK2:       cond.true10:
3070 // CHECK2-NEXT:    [[TMP39:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
3071 // CHECK2-NEXT:    br label [[COND_END12:%.*]]
3072 // CHECK2:       cond.false11:
3073 // CHECK2-NEXT:    [[TMP40:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
3074 // CHECK2-NEXT:    br label [[COND_END12]]
3075 // CHECK2:       cond.end12:
3076 // CHECK2-NEXT:    [[COND13:%.*]] = phi i32 [ [[TMP39]], [[COND_TRUE10]] ], [ [[TMP40]], [[COND_FALSE11]] ]
3077 // CHECK2-NEXT:    store i32 [[COND13]], ptr [[DOTOMP_COMB_UB]], align 4
3078 // CHECK2-NEXT:    [[TMP41:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
3079 // CHECK2-NEXT:    store i32 [[TMP41]], ptr [[DOTOMP_IV]], align 4
3080 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND]]
3081 // CHECK2:       omp.inner.for.end:
3082 // CHECK2-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
3083 // CHECK2:       omp.loop.exit:
3084 // CHECK2-NEXT:    [[TMP42:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
3085 // CHECK2-NEXT:    [[TMP43:%.*]] = load i32, ptr [[TMP42]], align 4
3086 // CHECK2-NEXT:    call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP43]])
3087 // CHECK2-NEXT:    br label [[OMP_PRECOND_END]]
3088 // CHECK2:       omp.precond.end:
3089 // CHECK2-NEXT:    ret void
3090 //
3091 //
3092 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l59_omp_outlined_omp_outlined
3093 // CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], ptr noundef [[V:%.*]]) #[[ATTR1]] {
3094 // CHECK2-NEXT:  entry:
3095 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
3096 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
3097 // CHECK2-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
3098 // CHECK2-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
3099 // CHECK2-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
3100 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
3101 // CHECK2-NEXT:    [[V_ADDR:%.*]] = alloca ptr, align 8
3102 // CHECK2-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
3103 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i32, align 4
3104 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
3105 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
3106 // CHECK2-NEXT:    [[I:%.*]] = alloca i32, align 4
3107 // CHECK2-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
3108 // CHECK2-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
3109 // CHECK2-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3110 // CHECK2-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3111 // CHECK2-NEXT:    [[I4:%.*]] = alloca i32, align 4
3112 // CHECK2-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
3113 // CHECK2-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
3114 // CHECK2-NEXT:    store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
3115 // CHECK2-NEXT:    store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
3116 // CHECK2-NEXT:    store i64 [[N]], ptr [[N_ADDR]], align 8
3117 // CHECK2-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
3118 // CHECK2-NEXT:    store ptr [[V]], ptr [[V_ADDR]], align 8
3119 // CHECK2-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
3120 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
3121 // CHECK2-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
3122 // CHECK2-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
3123 // CHECK2-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
3124 // CHECK2-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1
3125 // CHECK2-NEXT:    [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
3126 // CHECK2-NEXT:    store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
3127 // CHECK2-NEXT:    store i32 0, ptr [[I]], align 4
3128 // CHECK2-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
3129 // CHECK2-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]
3130 // CHECK2-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
3131 // CHECK2:       omp.precond.then:
3132 // CHECK2-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
3133 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
3134 // CHECK2-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4
3135 // CHECK2-NEXT:    [[TMP5:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
3136 // CHECK2-NEXT:    [[CONV:%.*]] = trunc i64 [[TMP5]] to i32
3137 // CHECK2-NEXT:    [[TMP6:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
3138 // CHECK2-NEXT:    [[CONV3:%.*]] = trunc i64 [[TMP6]] to i32
3139 // CHECK2-NEXT:    store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
3140 // CHECK2-NEXT:    store i32 [[CONV3]], ptr [[DOTOMP_UB]], align 4
3141 // CHECK2-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
3142 // CHECK2-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
3143 // CHECK2-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
3144 // CHECK2-NEXT:    [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
3145 // CHECK2-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP8]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
3146 // CHECK2-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
3147 // CHECK2-NEXT:    store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4
3148 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
3149 // CHECK2:       omp.inner.for.cond:
3150 // CHECK2-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3151 // CHECK2-NEXT:    [[CONV5:%.*]] = sext i32 [[TMP10]] to i64
3152 // CHECK2-NEXT:    [[TMP11:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
3153 // CHECK2-NEXT:    [[CMP6:%.*]] = icmp ule i64 [[CONV5]], [[TMP11]]
3154 // CHECK2-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3155 // CHECK2:       omp.inner.for.body:
3156 // CHECK2-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3157 // CHECK2-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
3158 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
3159 // CHECK2-NEXT:    store i32 [[ADD]], ptr [[I4]], align 4
3160 // CHECK2-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[V_ADDR]], align 8
3161 // CHECK2-NEXT:    [[TMP14:%.*]] = load i32, ptr [[I4]], align 4
3162 // CHECK2-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64
3163 // CHECK2-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP13]], i64 [[IDXPROM]]
3164 // CHECK2-NEXT:    [[TMP15:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
3165 // CHECK2-NEXT:    [[TMP16:%.*]] = load i32, ptr [[I4]], align 4
3166 // CHECK2-NEXT:    [[IDXPROM7:%.*]] = sext i32 [[TMP16]] to i64
3167 // CHECK2-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM7]]
3168 // CHECK2-NEXT:    store i32 [[TMP15]], ptr [[ARRAYIDX8]], align 4
3169 // CHECK2-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
3170 // CHECK2:       omp.body.continue:
3171 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
3172 // CHECK2:       omp.inner.for.inc:
3173 // CHECK2-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3174 // CHECK2-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
3175 // CHECK2-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP17]], [[TMP18]]
3176 // CHECK2-NEXT:    store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4
3177 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND]]
3178 // CHECK2:       omp.inner.for.end:
3179 // CHECK2-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
3180 // CHECK2:       omp.loop.exit:
3181 // CHECK2-NEXT:    [[TMP19:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
3182 // CHECK2-NEXT:    [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4
3183 // CHECK2-NEXT:    call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP20]])
3184 // CHECK2-NEXT:    br label [[OMP_PRECOND_END]]
3185 // CHECK2:       omp.precond.end:
3186 // CHECK2-NEXT:    ret void
3187 //
3188 //
3189 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28
3190 // CHECK3-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 noundef [[L:%.*]]) #[[ATTR0:[0-9]+]] {
3191 // CHECK3-NEXT:  entry:
3192 // CHECK3-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
3193 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
3194 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 4
3195 // CHECK3-NEXT:    [[L_ADDR:%.*]] = alloca i32, align 4
3196 // CHECK3-NEXT:    [[N_CASTED:%.*]] = alloca i32, align 4
3197 // CHECK3-NEXT:    [[L_CASTED:%.*]] = alloca i32, align 4
3198 // CHECK3-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
3199 // CHECK3-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
3200 // CHECK3-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
3201 // CHECK3-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
3202 // CHECK3-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 4
3203 // CHECK3-NEXT:    store i32 [[L]], ptr [[L_ADDR]], align 4
3204 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4
3205 // CHECK3-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28_kernel_environment, ptr [[DYN_PTR]])
3206 // CHECK3-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
3207 // CHECK3-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
3208 // CHECK3:       user_code.entry:
3209 // CHECK3-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
3210 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4
3211 // CHECK3-NEXT:    store i32 [[TMP3]], ptr [[N_CASTED]], align 4
3212 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N_CASTED]], align 4
3213 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[L_ADDR]], align 4
3214 // CHECK3-NEXT:    store i32 [[TMP5]], ptr [[L_CASTED]], align 4
3215 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[L_CASTED]], align 4
3216 // CHECK3-NEXT:    store i32 0, ptr [[DOTZERO_ADDR]], align 4
3217 // CHECK3-NEXT:    store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4
3218 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i32 [[TMP4]], ptr [[TMP0]], i32 [[TMP6]]) #[[ATTR2:[0-9]+]]
3219 // CHECK3-NEXT:    call void @__kmpc_target_deinit()
3220 // CHECK3-NEXT:    ret void
3221 // CHECK3:       worker.exit:
3222 // CHECK3-NEXT:    ret void
3223 //
3224 //
3225 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28_omp_outlined
3226 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 noundef [[L:%.*]]) #[[ATTR1:[0-9]+]] {
3227 // CHECK3-NEXT:  entry:
3228 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
3229 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
3230 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
3231 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 4
3232 // CHECK3-NEXT:    [[L_ADDR:%.*]] = alloca i32, align 4
3233 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
3234 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
3235 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
3236 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
3237 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
3238 // CHECK3-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
3239 // CHECK3-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
3240 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3241 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3242 // CHECK3-NEXT:    [[I3:%.*]] = alloca i32, align 4
3243 // CHECK3-NEXT:    [[N_CASTED:%.*]] = alloca i32, align 4
3244 // CHECK3-NEXT:    [[L_CASTED:%.*]] = alloca i32, align 4
3245 // CHECK3-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [5 x ptr], align 4
3246 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
3247 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
3248 // CHECK3-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
3249 // CHECK3-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 4
3250 // CHECK3-NEXT:    store i32 [[L]], ptr [[L_ADDR]], align 4
3251 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4
3252 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
3253 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
3254 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
3255 // CHECK3-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
3256 // CHECK3-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1
3257 // CHECK3-NEXT:    [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
3258 // CHECK3-NEXT:    store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
3259 // CHECK3-NEXT:    store i32 0, ptr [[I]], align 4
3260 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
3261 // CHECK3-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]
3262 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
3263 // CHECK3:       omp.precond.then:
3264 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
3265 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
3266 // CHECK3-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_COMB_UB]], align 4
3267 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
3268 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
3269 // CHECK3-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
3270 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
3271 // CHECK3-NEXT:    call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP6]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 128)
3272 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
3273 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
3274 // CHECK3-NEXT:    [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]]
3275 // CHECK3-NEXT:    br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3276 // CHECK3:       cond.true:
3277 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
3278 // CHECK3-NEXT:    br label [[COND_END:%.*]]
3279 // CHECK3:       cond.false:
3280 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
3281 // CHECK3-NEXT:    br label [[COND_END]]
3282 // CHECK3:       cond.end:
3283 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
3284 // CHECK3-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
3285 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
3286 // CHECK3-NEXT:    store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 4
3287 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
3288 // CHECK3:       omp.inner.for.cond:
3289 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3290 // CHECK3-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
3291 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP13]], 1
3292 // CHECK3-NEXT:    [[CMP5:%.*]] = icmp slt i32 [[TMP12]], [[ADD]]
3293 // CHECK3-NEXT:    br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3294 // CHECK3:       omp.inner.for.body:
3295 // CHECK3-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
3296 // CHECK3-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
3297 // CHECK3-NEXT:    [[TMP16:%.*]] = load i32, ptr [[N_ADDR]], align 4
3298 // CHECK3-NEXT:    store i32 [[TMP16]], ptr [[N_CASTED]], align 4
3299 // CHECK3-NEXT:    [[TMP17:%.*]] = load i32, ptr [[N_CASTED]], align 4
3300 // CHECK3-NEXT:    [[TMP18:%.*]] = load i32, ptr [[L_ADDR]], align 4
3301 // CHECK3-NEXT:    store i32 [[TMP18]], ptr [[L_CASTED]], align 4
3302 // CHECK3-NEXT:    [[TMP19:%.*]] = load i32, ptr [[L_CASTED]], align 4
3303 // CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
3304 // CHECK3-NEXT:    [[TMP21:%.*]] = inttoptr i32 [[TMP14]] to ptr
3305 // CHECK3-NEXT:    store ptr [[TMP21]], ptr [[TMP20]], align 4
3306 // CHECK3-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
3307 // CHECK3-NEXT:    [[TMP23:%.*]] = inttoptr i32 [[TMP15]] to ptr
3308 // CHECK3-NEXT:    store ptr [[TMP23]], ptr [[TMP22]], align 4
3309 // CHECK3-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 2
3310 // CHECK3-NEXT:    [[TMP25:%.*]] = inttoptr i32 [[TMP17]] to ptr
3311 // CHECK3-NEXT:    store ptr [[TMP25]], ptr [[TMP24]], align 4
3312 // CHECK3-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 3
3313 // CHECK3-NEXT:    store ptr [[TMP0]], ptr [[TMP26]], align 4
3314 // CHECK3-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 4
3315 // CHECK3-NEXT:    [[TMP28:%.*]] = inttoptr i32 [[TMP19]] to ptr
3316 // CHECK3-NEXT:    store ptr [[TMP28]], ptr [[TMP27]], align 4
3317 // CHECK3-NEXT:    [[TMP29:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
3318 // CHECK3-NEXT:    [[TMP30:%.*]] = load i32, ptr [[TMP29]], align 4
3319 // CHECK3-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP30]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 5)
3320 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
3321 // CHECK3:       omp.inner.for.inc:
3322 // CHECK3-NEXT:    [[TMP31:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3323 // CHECK3-NEXT:    [[TMP32:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
3324 // CHECK3-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP31]], [[TMP32]]
3325 // CHECK3-NEXT:    store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4
3326 // CHECK3-NEXT:    [[TMP33:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
3327 // CHECK3-NEXT:    [[TMP34:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
3328 // CHECK3-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP33]], [[TMP34]]
3329 // CHECK3-NEXT:    store i32 [[ADD7]], ptr [[DOTOMP_COMB_LB]], align 4
3330 // CHECK3-NEXT:    [[TMP35:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
3331 // CHECK3-NEXT:    [[TMP36:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
3332 // CHECK3-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP35]], [[TMP36]]
3333 // CHECK3-NEXT:    store i32 [[ADD8]], ptr [[DOTOMP_COMB_UB]], align 4
3334 // CHECK3-NEXT:    [[TMP37:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
3335 // CHECK3-NEXT:    [[TMP38:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
3336 // CHECK3-NEXT:    [[CMP9:%.*]] = icmp sgt i32 [[TMP37]], [[TMP38]]
3337 // CHECK3-NEXT:    br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]]
3338 // CHECK3:       cond.true10:
3339 // CHECK3-NEXT:    [[TMP39:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
3340 // CHECK3-NEXT:    br label [[COND_END12:%.*]]
3341 // CHECK3:       cond.false11:
3342 // CHECK3-NEXT:    [[TMP40:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
3343 // CHECK3-NEXT:    br label [[COND_END12]]
3344 // CHECK3:       cond.end12:
3345 // CHECK3-NEXT:    [[COND13:%.*]] = phi i32 [ [[TMP39]], [[COND_TRUE10]] ], [ [[TMP40]], [[COND_FALSE11]] ]
3346 // CHECK3-NEXT:    store i32 [[COND13]], ptr [[DOTOMP_COMB_UB]], align 4
3347 // CHECK3-NEXT:    [[TMP41:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
3348 // CHECK3-NEXT:    store i32 [[TMP41]], ptr [[DOTOMP_IV]], align 4
3349 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]]
3350 // CHECK3:       omp.inner.for.end:
3351 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
3352 // CHECK3:       omp.loop.exit:
3353 // CHECK3-NEXT:    [[TMP42:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
3354 // CHECK3-NEXT:    [[TMP43:%.*]] = load i32, ptr [[TMP42]], align 4
3355 // CHECK3-NEXT:    call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP43]])
3356 // CHECK3-NEXT:    [[TMP44:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
3357 // CHECK3-NEXT:    [[TMP45:%.*]] = icmp ne i32 [[TMP44]], 0
3358 // CHECK3-NEXT:    br i1 [[TMP45]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
3359 // CHECK3:       .omp.lastprivate.then:
3360 // CHECK3-NEXT:    [[TMP46:%.*]] = load i32, ptr [[L_ADDR]], align 4
3361 // CHECK3-NEXT:    store i32 [[TMP46]], ptr [[L_ADDR]], align 4
3362 // CHECK3-NEXT:    br label [[DOTOMP_LASTPRIVATE_DONE]]
3363 // CHECK3:       .omp.lastprivate.done:
3364 // CHECK3-NEXT:    br label [[OMP_PRECOND_END]]
3365 // CHECK3:       omp.precond.end:
3366 // CHECK3-NEXT:    ret void
3367 //
3368 //
3369 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28_omp_outlined_omp_outlined
3370 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 noundef [[L:%.*]]) #[[ATTR1]] {
3371 // CHECK3-NEXT:  entry:
3372 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
3373 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
3374 // CHECK3-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
3375 // CHECK3-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
3376 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
3377 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 4
3378 // CHECK3-NEXT:    [[L_ADDR:%.*]] = alloca i32, align 4
3379 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
3380 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
3381 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
3382 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
3383 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
3384 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
3385 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
3386 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3387 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3388 // CHECK3-NEXT:    [[I3:%.*]] = alloca i32, align 4
3389 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
3390 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
3391 // CHECK3-NEXT:    store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4
3392 // CHECK3-NEXT:    store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
3393 // CHECK3-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
3394 // CHECK3-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 4
3395 // CHECK3-NEXT:    store i32 [[L]], ptr [[L_ADDR]], align 4
3396 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4
3397 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
3398 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
3399 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
3400 // CHECK3-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
3401 // CHECK3-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1
3402 // CHECK3-NEXT:    [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
3403 // CHECK3-NEXT:    store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
3404 // CHECK3-NEXT:    store i32 0, ptr [[I]], align 4
3405 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
3406 // CHECK3-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]
3407 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
3408 // CHECK3:       omp.precond.then:
3409 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
3410 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
3411 // CHECK3-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4
3412 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4
3413 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
3414 // CHECK3-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_LB]], align 4
3415 // CHECK3-NEXT:    store i32 [[TMP6]], ptr [[DOTOMP_UB]], align 4
3416 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
3417 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
3418 // CHECK3-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
3419 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
3420 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB3:[0-9]+]], i32 [[TMP8]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 32)
3421 // CHECK3-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
3422 // CHECK3:       omp.dispatch.cond:
3423 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
3424 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
3425 // CHECK3-NEXT:    [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]]
3426 // CHECK3-NEXT:    br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3427 // CHECK3:       cond.true:
3428 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
3429 // CHECK3-NEXT:    br label [[COND_END:%.*]]
3430 // CHECK3:       cond.false:
3431 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
3432 // CHECK3-NEXT:    br label [[COND_END]]
3433 // CHECK3:       cond.end:
3434 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
3435 // CHECK3-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
3436 // CHECK3-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
3437 // CHECK3-NEXT:    store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4
3438 // CHECK3-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3439 // CHECK3-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
3440 // CHECK3-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
3441 // CHECK3-NEXT:    br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
3442 // CHECK3:       omp.dispatch.body:
3443 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
3444 // CHECK3:       omp.inner.for.cond:
3445 // CHECK3-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3446 // CHECK3-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
3447 // CHECK3-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
3448 // CHECK3-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3449 // CHECK3:       omp.inner.for.body:
3450 // CHECK3-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3451 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
3452 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
3453 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[I3]], align 4
3454 // CHECK3-NEXT:    [[TMP19:%.*]] = load i32, ptr [[I3]], align 4
3455 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], i32 0, i32 [[TMP19]]
3456 // CHECK3-NEXT:    store i32 1, ptr [[ARRAYIDX]], align 4
3457 // CHECK3-NEXT:    [[TMP20:%.*]] = load i32, ptr [[I3]], align 4
3458 // CHECK3-NEXT:    store i32 [[TMP20]], ptr [[L_ADDR]], align 4
3459 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
3460 // CHECK3:       omp.body.continue:
3461 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
3462 // CHECK3:       omp.inner.for.inc:
3463 // CHECK3-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3464 // CHECK3-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP21]], 1
3465 // CHECK3-NEXT:    store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4
3466 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]]
3467 // CHECK3:       omp.inner.for.end:
3468 // CHECK3-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
3469 // CHECK3:       omp.dispatch.inc:
3470 // CHECK3-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
3471 // CHECK3-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
3472 // CHECK3-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]
3473 // CHECK3-NEXT:    store i32 [[ADD8]], ptr [[DOTOMP_LB]], align 4
3474 // CHECK3-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
3475 // CHECK3-NEXT:    [[TMP25:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
3476 // CHECK3-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP24]], [[TMP25]]
3477 // CHECK3-NEXT:    store i32 [[ADD9]], ptr [[DOTOMP_UB]], align 4
3478 // CHECK3-NEXT:    br label [[OMP_DISPATCH_COND]]
3479 // CHECK3:       omp.dispatch.end:
3480 // CHECK3-NEXT:    [[TMP26:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
3481 // CHECK3-NEXT:    [[TMP27:%.*]] = load i32, ptr [[TMP26]], align 4
3482 // CHECK3-NEXT:    call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP27]])
3483 // CHECK3-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
3484 // CHECK3-NEXT:    [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0
3485 // CHECK3-NEXT:    br i1 [[TMP29]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
3486 // CHECK3:       .omp.lastprivate.then:
3487 // CHECK3-NEXT:    [[TMP30:%.*]] = load i32, ptr [[L_ADDR]], align 4
3488 // CHECK3-NEXT:    store i32 [[TMP30]], ptr [[L_ADDR]], align 4
3489 // CHECK3-NEXT:    br label [[DOTOMP_LASTPRIVATE_DONE]]
3490 // CHECK3:       .omp.lastprivate.done:
3491 // CHECK3-NEXT:    br label [[OMP_PRECOND_END]]
3492 // CHECK3:       omp.precond.end:
3493 // CHECK3-NEXT:    ret void
3494 //
3495 //
3496 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34
3497 // CHECK3-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[N:%.*]], ptr noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR4:[0-9]+]] {
3498 // CHECK3-NEXT:  entry:
3499 // CHECK3-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
3500 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
3501 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca ptr, align 4
3502 // CHECK3-NEXT:    [[N_CASTED:%.*]] = alloca i32, align 4
3503 // CHECK3-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
3504 // CHECK3-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
3505 // CHECK3-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
3506 // CHECK3-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
3507 // CHECK3-NEXT:    store ptr [[AA]], ptr [[AA_ADDR]], align 4
3508 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 4
3509 // CHECK3-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_kernel_environment, ptr [[DYN_PTR]])
3510 // CHECK3-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
3511 // CHECK3-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
3512 // CHECK3:       user_code.entry:
3513 // CHECK3-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
3514 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4
3515 // CHECK3-NEXT:    store i32 [[TMP3]], ptr [[N_CASTED]], align 4
3516 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N_CASTED]], align 4
3517 // CHECK3-NEXT:    store i32 0, ptr [[DOTZERO_ADDR]], align 4
3518 // CHECK3-NEXT:    store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4
3519 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i32 [[TMP4]], ptr [[TMP0]]) #[[ATTR2]]
3520 // CHECK3-NEXT:    call void @__kmpc_target_deinit()
3521 // CHECK3-NEXT:    ret void
3522 // CHECK3:       worker.exit:
3523 // CHECK3-NEXT:    ret void
3524 //
3525 //
3526 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_omp_outlined
3527 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], ptr noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR1]] {
3528 // CHECK3-NEXT:  entry:
3529 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
3530 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
3531 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
3532 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca ptr, align 4
3533 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
3534 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
3535 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
3536 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
3537 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
3538 // CHECK3-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
3539 // CHECK3-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
3540 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3541 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3542 // CHECK3-NEXT:    [[I3:%.*]] = alloca i32, align 4
3543 // CHECK3-NEXT:    [[N_CASTED:%.*]] = alloca i32, align 4
3544 // CHECK3-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [4 x ptr], align 4
3545 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
3546 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
3547 // CHECK3-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
3548 // CHECK3-NEXT:    store ptr [[AA]], ptr [[AA_ADDR]], align 4
3549 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 4
3550 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
3551 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
3552 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
3553 // CHECK3-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
3554 // CHECK3-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1
3555 // CHECK3-NEXT:    [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
3556 // CHECK3-NEXT:    store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
3557 // CHECK3-NEXT:    store i32 0, ptr [[I]], align 4
3558 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
3559 // CHECK3-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]
3560 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
3561 // CHECK3:       omp.precond.then:
3562 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
3563 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
3564 // CHECK3-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_COMB_UB]], align 4
3565 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
3566 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
3567 // CHECK3-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
3568 // CHECK3-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
3569 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
3570 // CHECK3-NEXT:    call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP6]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
3571 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
3572 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
3573 // CHECK3-NEXT:    [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]]
3574 // CHECK3-NEXT:    br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3575 // CHECK3:       cond.true:
3576 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
3577 // CHECK3-NEXT:    br label [[COND_END:%.*]]
3578 // CHECK3:       cond.false:
3579 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
3580 // CHECK3-NEXT:    br label [[COND_END]]
3581 // CHECK3:       cond.end:
3582 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
3583 // CHECK3-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
3584 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
3585 // CHECK3-NEXT:    store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 4
3586 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
3587 // CHECK3:       omp.inner.for.cond:
3588 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3589 // CHECK3-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
3590 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP13]], 1
3591 // CHECK3-NEXT:    [[CMP5:%.*]] = icmp slt i32 [[TMP12]], [[ADD]]
3592 // CHECK3-NEXT:    br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3593 // CHECK3:       omp.inner.for.body:
3594 // CHECK3-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
3595 // CHECK3-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
3596 // CHECK3-NEXT:    [[TMP16:%.*]] = load i32, ptr [[N_ADDR]], align 4
3597 // CHECK3-NEXT:    store i32 [[TMP16]], ptr [[N_CASTED]], align 4
3598 // CHECK3-NEXT:    [[TMP17:%.*]] = load i32, ptr [[N_CASTED]], align 4
3599 // CHECK3-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
3600 // CHECK3-NEXT:    [[TMP19:%.*]] = inttoptr i32 [[TMP14]] to ptr
3601 // CHECK3-NEXT:    store ptr [[TMP19]], ptr [[TMP18]], align 4
3602 // CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
3603 // CHECK3-NEXT:    [[TMP21:%.*]] = inttoptr i32 [[TMP15]] to ptr
3604 // CHECK3-NEXT:    store ptr [[TMP21]], ptr [[TMP20]], align 4
3605 // CHECK3-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 2
3606 // CHECK3-NEXT:    [[TMP23:%.*]] = inttoptr i32 [[TMP17]] to ptr
3607 // CHECK3-NEXT:    store ptr [[TMP23]], ptr [[TMP22]], align 4
3608 // CHECK3-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 3
3609 // CHECK3-NEXT:    store ptr [[TMP0]], ptr [[TMP24]], align 4
3610 // CHECK3-NEXT:    [[TMP25:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
3611 // CHECK3-NEXT:    [[TMP26:%.*]] = load i32, ptr [[TMP25]], align 4
3612 // CHECK3-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP26]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 4)
3613 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
3614 // CHECK3:       omp.inner.for.inc:
3615 // CHECK3-NEXT:    [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3616 // CHECK3-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
3617 // CHECK3-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP27]], [[TMP28]]
3618 // CHECK3-NEXT:    store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4
3619 // CHECK3-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
3620 // CHECK3-NEXT:    [[TMP30:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
3621 // CHECK3-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP29]], [[TMP30]]
3622 // CHECK3-NEXT:    store i32 [[ADD7]], ptr [[DOTOMP_COMB_LB]], align 4
3623 // CHECK3-NEXT:    [[TMP31:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
3624 // CHECK3-NEXT:    [[TMP32:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
3625 // CHECK3-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP31]], [[TMP32]]
3626 // CHECK3-NEXT:    store i32 [[ADD8]], ptr [[DOTOMP_COMB_UB]], align 4
3627 // CHECK3-NEXT:    [[TMP33:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
3628 // CHECK3-NEXT:    [[TMP34:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
3629 // CHECK3-NEXT:    [[CMP9:%.*]] = icmp sgt i32 [[TMP33]], [[TMP34]]
3630 // CHECK3-NEXT:    br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]]
3631 // CHECK3:       cond.true10:
3632 // CHECK3-NEXT:    [[TMP35:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
3633 // CHECK3-NEXT:    br label [[COND_END12:%.*]]
3634 // CHECK3:       cond.false11:
3635 // CHECK3-NEXT:    [[TMP36:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
3636 // CHECK3-NEXT:    br label [[COND_END12]]
3637 // CHECK3:       cond.end12:
3638 // CHECK3-NEXT:    [[COND13:%.*]] = phi i32 [ [[TMP35]], [[COND_TRUE10]] ], [ [[TMP36]], [[COND_FALSE11]] ]
3639 // CHECK3-NEXT:    store i32 [[COND13]], ptr [[DOTOMP_COMB_UB]], align 4
3640 // CHECK3-NEXT:    [[TMP37:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
3641 // CHECK3-NEXT:    store i32 [[TMP37]], ptr [[DOTOMP_IV]], align 4
3642 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]]
3643 // CHECK3:       omp.inner.for.end:
3644 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
3645 // CHECK3:       omp.loop.exit:
3646 // CHECK3-NEXT:    [[TMP38:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
3647 // CHECK3-NEXT:    [[TMP39:%.*]] = load i32, ptr [[TMP38]], align 4
3648 // CHECK3-NEXT:    call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP39]])
3649 // CHECK3-NEXT:    br label [[OMP_PRECOND_END]]
3650 // CHECK3:       omp.precond.end:
3651 // CHECK3-NEXT:    ret void
3652 //
3653 //
3654 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_omp_outlined_omp_outlined
3655 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], ptr noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR1]] {
3656 // CHECK3-NEXT:  entry:
3657 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
3658 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
3659 // CHECK3-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
3660 // CHECK3-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
3661 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
3662 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca ptr, align 4
3663 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
3664 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
3665 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
3666 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
3667 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
3668 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
3669 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
3670 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3671 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3672 // CHECK3-NEXT:    [[I3:%.*]] = alloca i32, align 4
3673 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
3674 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
3675 // CHECK3-NEXT:    store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4
3676 // CHECK3-NEXT:    store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
3677 // CHECK3-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
3678 // CHECK3-NEXT:    store ptr [[AA]], ptr [[AA_ADDR]], align 4
3679 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 4
3680 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
3681 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
3682 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
3683 // CHECK3-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
3684 // CHECK3-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1
3685 // CHECK3-NEXT:    [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
3686 // CHECK3-NEXT:    store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
3687 // CHECK3-NEXT:    store i32 0, ptr [[I]], align 4
3688 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
3689 // CHECK3-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]
3690 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
3691 // CHECK3:       omp.precond.then:
3692 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
3693 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
3694 // CHECK3-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4
3695 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4
3696 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
3697 // CHECK3-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_LB]], align 4
3698 // CHECK3-NEXT:    store i32 [[TMP6]], ptr [[DOTOMP_UB]], align 4
3699 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
3700 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
3701 // CHECK3-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
3702 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
3703 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP8]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
3704 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
3705 // CHECK3-NEXT:    store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4
3706 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
3707 // CHECK3:       omp.inner.for.cond:
3708 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3709 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
3710 // CHECK3-NEXT:    [[CMP4:%.*]] = icmp ule i32 [[TMP10]], [[TMP11]]
3711 // CHECK3-NEXT:    br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3712 // CHECK3:       omp.inner.for.body:
3713 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3714 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
3715 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
3716 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[I3]], align 4
3717 // CHECK3-NEXT:    [[TMP13:%.*]] = load i32, ptr [[I3]], align 4
3718 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], ptr [[TMP0]], i32 0, i32 [[TMP13]]
3719 // CHECK3-NEXT:    [[TMP14:%.*]] = load i16, ptr [[ARRAYIDX]], align 2
3720 // CHECK3-NEXT:    [[CONV:%.*]] = sext i16 [[TMP14]] to i32
3721 // CHECK3-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV]], 1
3722 // CHECK3-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
3723 // CHECK3-NEXT:    store i16 [[CONV6]], ptr [[ARRAYIDX]], align 2
3724 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
3725 // CHECK3:       omp.body.continue:
3726 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
3727 // CHECK3:       omp.inner.for.inc:
3728 // CHECK3-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3729 // CHECK3-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
3730 // CHECK3-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
3731 // CHECK3-NEXT:    store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4
3732 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]]
3733 // CHECK3:       omp.inner.for.end:
3734 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
3735 // CHECK3:       omp.loop.exit:
3736 // CHECK3-NEXT:    [[TMP17:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
3737 // CHECK3-NEXT:    [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 4
3738 // CHECK3-NEXT:    call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP18]])
3739 // CHECK3-NEXT:    br label [[OMP_PRECOND_END]]
3740 // CHECK3:       omp.precond.end:
3741 // CHECK3-NEXT:    ret void
3742 //
3743 //
3744 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l39
3745 // CHECK3-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
3746 // CHECK3-NEXT:  entry:
3747 // CHECK3-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
3748 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
3749 // CHECK3-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
3750 // CHECK3-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
3751 // CHECK3-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
3752 // CHECK3-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
3753 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
3754 // CHECK3-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l39_kernel_environment, ptr [[DYN_PTR]])
3755 // CHECK3-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
3756 // CHECK3-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
3757 // CHECK3:       user_code.entry:
3758 // CHECK3-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
3759 // CHECK3-NEXT:    store i32 0, ptr [[DOTZERO_ADDR]], align 4
3760 // CHECK3-NEXT:    store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4
3761 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l39_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]]) #[[ATTR2]]
3762 // CHECK3-NEXT:    call void @__kmpc_target_deinit()
3763 // CHECK3-NEXT:    ret void
3764 // CHECK3:       worker.exit:
3765 // CHECK3-NEXT:    ret void
3766 //
3767 //
3768 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l39_omp_outlined
3769 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
3770 // CHECK3-NEXT:  entry:
3771 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
3772 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
3773 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
3774 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
3775 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
3776 // CHECK3-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
3777 // CHECK3-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
3778 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3779 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3780 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
3781 // CHECK3-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x ptr], align 4
3782 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
3783 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
3784 // CHECK3-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
3785 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
3786 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
3787 // CHECK3-NEXT:    store i32 9, ptr [[DOTOMP_COMB_UB]], align 4
3788 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
3789 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
3790 // CHECK3-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
3791 // CHECK3-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
3792 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
3793 // CHECK3-NEXT:    call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP2]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
3794 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
3795 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
3796 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3797 // CHECK3:       cond.true:
3798 // CHECK3-NEXT:    br label [[COND_END:%.*]]
3799 // CHECK3:       cond.false:
3800 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
3801 // CHECK3-NEXT:    br label [[COND_END]]
3802 // CHECK3:       cond.end:
3803 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
3804 // CHECK3-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
3805 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
3806 // CHECK3-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
3807 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
3808 // CHECK3:       omp.inner.for.cond:
3809 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3810 // CHECK3-NEXT:    [[CMP1:%.*]] = icmp slt i32 [[TMP6]], 10
3811 // CHECK3-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3812 // CHECK3:       omp.inner.for.body:
3813 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
3814 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
3815 // CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
3816 // CHECK3-NEXT:    [[TMP10:%.*]] = inttoptr i32 [[TMP7]] to ptr
3817 // CHECK3-NEXT:    store ptr [[TMP10]], ptr [[TMP9]], align 4
3818 // CHECK3-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
3819 // CHECK3-NEXT:    [[TMP12:%.*]] = inttoptr i32 [[TMP8]] to ptr
3820 // CHECK3-NEXT:    store ptr [[TMP12]], ptr [[TMP11]], align 4
3821 // CHECK3-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 2
3822 // CHECK3-NEXT:    store ptr [[TMP0]], ptr [[TMP13]], align 4
3823 // CHECK3-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l39_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 3)
3824 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
3825 // CHECK3:       omp.inner.for.inc:
3826 // CHECK3-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3827 // CHECK3-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
3828 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
3829 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
3830 // CHECK3-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
3831 // CHECK3-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
3832 // CHECK3-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
3833 // CHECK3-NEXT:    store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4
3834 // CHECK3-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
3835 // CHECK3-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
3836 // CHECK3-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
3837 // CHECK3-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4
3838 // CHECK3-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
3839 // CHECK3-NEXT:    [[CMP4:%.*]] = icmp sgt i32 [[TMP20]], 9
3840 // CHECK3-NEXT:    br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
3841 // CHECK3:       cond.true5:
3842 // CHECK3-NEXT:    br label [[COND_END7:%.*]]
3843 // CHECK3:       cond.false6:
3844 // CHECK3-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
3845 // CHECK3-NEXT:    br label [[COND_END7]]
3846 // CHECK3:       cond.end7:
3847 // CHECK3-NEXT:    [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP21]], [[COND_FALSE6]] ]
3848 // CHECK3-NEXT:    store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4
3849 // CHECK3-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
3850 // CHECK3-NEXT:    store i32 [[TMP22]], ptr [[DOTOMP_IV]], align 4
3851 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]]
3852 // CHECK3:       omp.inner.for.end:
3853 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
3854 // CHECK3:       omp.loop.exit:
3855 // CHECK3-NEXT:    call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP2]])
3856 // CHECK3-NEXT:    ret void
3857 //
3858 //
3859 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l39_omp_outlined_omp_outlined
3860 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
3861 // CHECK3-NEXT:  entry:
3862 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
3863 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
3864 // CHECK3-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
3865 // CHECK3-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
3866 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
3867 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
3868 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
3869 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
3870 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
3871 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3872 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3873 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
3874 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
3875 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
3876 // CHECK3-NEXT:    store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4
3877 // CHECK3-NEXT:    store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
3878 // CHECK3-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
3879 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
3880 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
3881 // CHECK3-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4
3882 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4
3883 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
3884 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[DOTOMP_LB]], align 4
3885 // CHECK3-NEXT:    store i32 [[TMP2]], ptr [[DOTOMP_UB]], align 4
3886 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
3887 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
3888 // CHECK3-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
3889 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
3890 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP4]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
3891 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
3892 // CHECK3-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
3893 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
3894 // CHECK3:       omp.inner.for.cond:
3895 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3896 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
3897 // CHECK3-NEXT:    [[CMP:%.*]] = icmp ule i32 [[TMP6]], [[TMP7]]
3898 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3899 // CHECK3:       omp.inner.for.body:
3900 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3901 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
3902 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
3903 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[I]], align 4
3904 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[I]], align 4
3905 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP9]]
3906 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
3907 // CHECK3-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP10]], 1
3908 // CHECK3-NEXT:    store i32 [[ADD1]], ptr [[ARRAYIDX]], align 4
3909 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
3910 // CHECK3:       omp.body.continue:
3911 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
3912 // CHECK3:       omp.inner.for.inc:
3913 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3914 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
3915 // CHECK3-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
3916 // CHECK3-NEXT:    store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4
3917 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]]
3918 // CHECK3:       omp.inner.for.end:
3919 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
3920 // CHECK3:       omp.loop.exit:
3921 // CHECK3-NEXT:    call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP4]])
3922 // CHECK3-NEXT:    ret void
3923 //
3924 //
3925 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l44
3926 // CHECK3-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[F:%.*]]) #[[ATTR0]] {
3927 // CHECK3-NEXT:  entry:
3928 // CHECK3-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
3929 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
3930 // CHECK3-NEXT:    [[F_ADDR:%.*]] = alloca i32, align 4
3931 // CHECK3-NEXT:    [[F_CASTED:%.*]] = alloca i32, align 4
3932 // CHECK3-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
3933 // CHECK3-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
3934 // CHECK3-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
3935 // CHECK3-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
3936 // CHECK3-NEXT:    store i32 [[F]], ptr [[F_ADDR]], align 4
3937 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 4
3938 // CHECK3-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l44_kernel_environment, ptr [[DYN_PTR]])
3939 // CHECK3-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
3940 // CHECK3-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
3941 // CHECK3:       user_code.entry:
3942 // CHECK3-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
3943 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[F_ADDR]], align 4
3944 // CHECK3-NEXT:    store i32 [[TMP3]], ptr [[F_CASTED]], align 4
3945 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[F_CASTED]], align 4
3946 // CHECK3-NEXT:    store i32 0, ptr [[DOTZERO_ADDR]], align 4
3947 // CHECK3-NEXT:    store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4
3948 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l44_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]], i32 [[TMP4]]) #[[ATTR2]]
3949 // CHECK3-NEXT:    call void @__kmpc_target_deinit()
3950 // CHECK3-NEXT:    ret void
3951 // CHECK3:       worker.exit:
3952 // CHECK3-NEXT:    ret void
3953 //
3954 //
3955 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l44_omp_outlined
3956 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[F:%.*]]) #[[ATTR1]] {
3957 // CHECK3-NEXT:  entry:
3958 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
3959 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
3960 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
3961 // CHECK3-NEXT:    [[F_ADDR:%.*]] = alloca i32, align 4
3962 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
3963 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
3964 // CHECK3-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
3965 // CHECK3-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
3966 // CHECK3-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
3967 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3968 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3969 // CHECK3-NEXT:    [[K:%.*]] = alloca i32, align 4
3970 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
3971 // CHECK3-NEXT:    [[J:%.*]] = alloca i32, align 4
3972 // CHECK3-NEXT:    [[F_CASTED:%.*]] = alloca i32, align 4
3973 // CHECK3-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [4 x ptr], align 4
3974 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
3975 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
3976 // CHECK3-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
3977 // CHECK3-NEXT:    store i32 [[F]], ptr [[F_ADDR]], align 4
3978 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 4
3979 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
3980 // CHECK3-NEXT:    store i32 99, ptr [[DOTOMP_COMB_UB]], align 4
3981 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
3982 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
3983 // CHECK3-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
3984 // CHECK3-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
3985 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
3986 // CHECK3-NEXT:    call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP2]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
3987 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
3988 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 99
3989 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3990 // CHECK3:       cond.true:
3991 // CHECK3-NEXT:    br label [[COND_END:%.*]]
3992 // CHECK3:       cond.false:
3993 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
3994 // CHECK3-NEXT:    br label [[COND_END]]
3995 // CHECK3:       cond.end:
3996 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
3997 // CHECK3-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
3998 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
3999 // CHECK3-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
4000 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
4001 // CHECK3:       omp.inner.for.cond:
4002 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4003 // CHECK3-NEXT:    [[CMP2:%.*]] = icmp slt i32 [[TMP6]], 100
4004 // CHECK3-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4005 // CHECK3:       omp.inner.for.body:
4006 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
4007 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
4008 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[F_ADDR]], align 4
4009 // CHECK3-NEXT:    store i32 [[TMP9]], ptr [[F_CASTED]], align 4
4010 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[F_CASTED]], align 4
4011 // CHECK3-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
4012 // CHECK3-NEXT:    [[TMP12:%.*]] = inttoptr i32 [[TMP7]] to ptr
4013 // CHECK3-NEXT:    store ptr [[TMP12]], ptr [[TMP11]], align 4
4014 // CHECK3-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
4015 // CHECK3-NEXT:    [[TMP14:%.*]] = inttoptr i32 [[TMP8]] to ptr
4016 // CHECK3-NEXT:    store ptr [[TMP14]], ptr [[TMP13]], align 4
4017 // CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 2
4018 // CHECK3-NEXT:    store ptr [[TMP0]], ptr [[TMP15]], align 4
4019 // CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 3
4020 // CHECK3-NEXT:    [[TMP17:%.*]] = inttoptr i32 [[TMP10]] to ptr
4021 // CHECK3-NEXT:    store ptr [[TMP17]], ptr [[TMP16]], align 4
4022 // CHECK3-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l44_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 4)
4023 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4024 // CHECK3:       omp.inner.for.inc:
4025 // CHECK3-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4026 // CHECK3-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
4027 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
4028 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
4029 // CHECK3-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
4030 // CHECK3-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
4031 // CHECK3-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]
4032 // CHECK3-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_COMB_LB]], align 4
4033 // CHECK3-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
4034 // CHECK3-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
4035 // CHECK3-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]
4036 // CHECK3-NEXT:    store i32 [[ADD4]], ptr [[DOTOMP_COMB_UB]], align 4
4037 // CHECK3-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
4038 // CHECK3-NEXT:    [[CMP5:%.*]] = icmp sgt i32 [[TMP24]], 99
4039 // CHECK3-NEXT:    br i1 [[CMP5]], label [[COND_TRUE6:%.*]], label [[COND_FALSE7:%.*]]
4040 // CHECK3:       cond.true6:
4041 // CHECK3-NEXT:    br label [[COND_END8:%.*]]
4042 // CHECK3:       cond.false7:
4043 // CHECK3-NEXT:    [[TMP25:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
4044 // CHECK3-NEXT:    br label [[COND_END8]]
4045 // CHECK3:       cond.end8:
4046 // CHECK3-NEXT:    [[COND9:%.*]] = phi i32 [ 99, [[COND_TRUE6]] ], [ [[TMP25]], [[COND_FALSE7]] ]
4047 // CHECK3-NEXT:    store i32 [[COND9]], ptr [[DOTOMP_COMB_UB]], align 4
4048 // CHECK3-NEXT:    [[TMP26:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
4049 // CHECK3-NEXT:    store i32 [[TMP26]], ptr [[DOTOMP_IV]], align 4
4050 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]]
4051 // CHECK3:       omp.inner.for.end:
4052 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
4053 // CHECK3:       omp.loop.exit:
4054 // CHECK3-NEXT:    call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP2]])
4055 // CHECK3-NEXT:    ret void
4056 //
4057 //
4058 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l44_omp_outlined_omp_outlined
4059 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[F:%.*]]) #[[ATTR1]] {
4060 // CHECK3-NEXT:  entry:
4061 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
4062 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
4063 // CHECK3-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
4064 // CHECK3-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
4065 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
4066 // CHECK3-NEXT:    [[F_ADDR:%.*]] = alloca i32, align 4
4067 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
4068 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
4069 // CHECK3-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
4070 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
4071 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
4072 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4073 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4074 // CHECK3-NEXT:    [[K:%.*]] = alloca i32, align 4
4075 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
4076 // CHECK3-NEXT:    [[J:%.*]] = alloca i32, align 4
4077 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
4078 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
4079 // CHECK3-NEXT:    store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4
4080 // CHECK3-NEXT:    store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
4081 // CHECK3-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
4082 // CHECK3-NEXT:    store i32 [[F]], ptr [[F_ADDR]], align 4
4083 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 4
4084 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
4085 // CHECK3-NEXT:    store i32 99, ptr [[DOTOMP_UB]], align 4
4086 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4
4087 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
4088 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[DOTOMP_LB]], align 4
4089 // CHECK3-NEXT:    store i32 [[TMP2]], ptr [[DOTOMP_UB]], align 4
4090 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
4091 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
4092 // CHECK3-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
4093 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
4094 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP4]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
4095 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
4096 // CHECK3-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
4097 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
4098 // CHECK3:       omp.inner.for.cond:
4099 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4100 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
4101 // CHECK3-NEXT:    [[CMP:%.*]] = icmp ule i32 [[TMP6]], [[TMP7]]
4102 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4103 // CHECK3:       omp.inner.for.body:
4104 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4105 // CHECK3-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP8]], 10
4106 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
4107 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
4108 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[I]], align 4
4109 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4110 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4111 // CHECK3-NEXT:    [[DIV2:%.*]] = sdiv i32 [[TMP10]], 10
4112 // CHECK3-NEXT:    [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 10
4113 // CHECK3-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL3]]
4114 // CHECK3-NEXT:    [[MUL4:%.*]] = mul nsw i32 [[SUB]], 1
4115 // CHECK3-NEXT:    [[ADD5:%.*]] = add nsw i32 0, [[MUL4]]
4116 // CHECK3-NEXT:    store i32 [[ADD5]], ptr [[J]], align 4
4117 // CHECK3-NEXT:    store i32 10, ptr [[K]], align 4
4118 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 4
4119 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, ptr [[J]], align 4
4120 // CHECK3-NEXT:    [[TMP13:%.*]] = load i32, ptr [[F_ADDR]], align 4
4121 // CHECK3-NEXT:    [[MUL6:%.*]] = mul nsw i32 [[TMP12]], [[TMP13]]
4122 // CHECK3-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP11]], [[MUL6]]
4123 // CHECK3-NEXT:    [[TMP14:%.*]] = load i32, ptr [[K]], align 4
4124 // CHECK3-NEXT:    [[ADD8:%.*]] = add nsw i32 [[ADD7]], [[TMP14]]
4125 // CHECK3-NEXT:    [[TMP15:%.*]] = load i32, ptr [[I]], align 4
4126 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP0]], i32 0, i32 [[TMP15]]
4127 // CHECK3-NEXT:    [[TMP16:%.*]] = load i32, ptr [[J]], align 4
4128 // CHECK3-NEXT:    [[ARRAYIDX9:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX]], i32 0, i32 [[TMP16]]
4129 // CHECK3-NEXT:    store i32 [[ADD8]], ptr [[ARRAYIDX9]], align 4
4130 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
4131 // CHECK3:       omp.body.continue:
4132 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4133 // CHECK3:       omp.inner.for.inc:
4134 // CHECK3-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4135 // CHECK3-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
4136 // CHECK3-NEXT:    [[ADD10:%.*]] = add nsw i32 [[TMP17]], [[TMP18]]
4137 // CHECK3-NEXT:    store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4
4138 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]]
4139 // CHECK3:       omp.inner.for.end:
4140 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
4141 // CHECK3:       omp.loop.exit:
4142 // CHECK3-NEXT:    call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP4]])
4143 // CHECK3-NEXT:    ret void
4144 //
4145 //
4146 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l52
4147 // CHECK3-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR0]] {
4148 // CHECK3-NEXT:  entry:
4149 // CHECK3-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
4150 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
4151 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
4152 // CHECK3-NEXT:    [[N_CASTED:%.*]] = alloca i32, align 4
4153 // CHECK3-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
4154 // CHECK3-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
4155 // CHECK3-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
4156 // CHECK3-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
4157 // CHECK3-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
4158 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 4
4159 // CHECK3-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l52_kernel_environment, ptr [[DYN_PTR]])
4160 // CHECK3-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
4161 // CHECK3-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
4162 // CHECK3:       user_code.entry:
4163 // CHECK3-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
4164 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4
4165 // CHECK3-NEXT:    store i32 [[TMP3]], ptr [[N_CASTED]], align 4
4166 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N_CASTED]], align 4
4167 // CHECK3-NEXT:    store i32 0, ptr [[DOTZERO_ADDR]], align 4
4168 // CHECK3-NEXT:    store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4
4169 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l52_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i32 [[TMP4]], ptr [[TMP0]]) #[[ATTR2]]
4170 // CHECK3-NEXT:    call void @__kmpc_target_deinit()
4171 // CHECK3-NEXT:    ret void
4172 // CHECK3:       worker.exit:
4173 // CHECK3-NEXT:    ret void
4174 //
4175 //
4176 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l52_omp_outlined
4177 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR1]] {
4178 // CHECK3-NEXT:  entry:
4179 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
4180 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
4181 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
4182 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
4183 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
4184 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
4185 // CHECK3-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
4186 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
4187 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
4188 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8
4189 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
4190 // CHECK3-NEXT:    [[J:%.*]] = alloca i32, align 4
4191 // CHECK3-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i64, align 8
4192 // CHECK3-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i64, align 8
4193 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
4194 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4195 // CHECK3-NEXT:    [[I9:%.*]] = alloca i32, align 4
4196 // CHECK3-NEXT:    [[J10:%.*]] = alloca i32, align 4
4197 // CHECK3-NEXT:    [[N_CASTED:%.*]] = alloca i32, align 4
4198 // CHECK3-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [4 x ptr], align 4
4199 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
4200 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
4201 // CHECK3-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
4202 // CHECK3-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
4203 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 4
4204 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
4205 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
4206 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
4207 // CHECK3-NEXT:    store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_2]], align 4
4208 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
4209 // CHECK3-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
4210 // CHECK3-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1
4211 // CHECK3-NEXT:    [[CONV:%.*]] = sext i32 [[DIV]] to i64
4212 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
4213 // CHECK3-NEXT:    [[SUB4:%.*]] = sub nsw i32 [[TMP4]], 0
4214 // CHECK3-NEXT:    [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1
4215 // CHECK3-NEXT:    [[CONV6:%.*]] = sext i32 [[DIV5]] to i64
4216 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]]
4217 // CHECK3-NEXT:    [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1
4218 // CHECK3-NEXT:    store i64 [[SUB7]], ptr [[DOTCAPTURE_EXPR_3]], align 8
4219 // CHECK3-NEXT:    store i32 0, ptr [[I]], align 4
4220 // CHECK3-NEXT:    store i32 0, ptr [[J]], align 4
4221 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
4222 // CHECK3-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP5]]
4223 // CHECK3-NEXT:    br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]]
4224 // CHECK3:       land.lhs.true:
4225 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
4226 // CHECK3-NEXT:    [[CMP8:%.*]] = icmp slt i32 0, [[TMP6]]
4227 // CHECK3-NEXT:    br i1 [[CMP8]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]]
4228 // CHECK3:       omp.precond.then:
4229 // CHECK3-NEXT:    store i64 0, ptr [[DOTOMP_COMB_LB]], align 8
4230 // CHECK3-NEXT:    [[TMP7:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_3]], align 8
4231 // CHECK3-NEXT:    store i64 [[TMP7]], ptr [[DOTOMP_COMB_UB]], align 8
4232 // CHECK3-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8
4233 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
4234 // CHECK3-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
4235 // CHECK3-NEXT:    [[CONV11:%.*]] = zext i32 [[NVPTX_NUM_THREADS]] to i64
4236 // CHECK3-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
4237 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
4238 // CHECK3-NEXT:    call void @__kmpc_distribute_static_init_8(ptr @[[GLOB2]], i32 [[TMP9]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 [[CONV11]])
4239 // CHECK3-NEXT:    [[TMP10:%.*]] = load i64, ptr [[DOTOMP_COMB_UB]], align 8
4240 // CHECK3-NEXT:    [[TMP11:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_3]], align 8
4241 // CHECK3-NEXT:    [[CMP12:%.*]] = icmp sgt i64 [[TMP10]], [[TMP11]]
4242 // CHECK3-NEXT:    br i1 [[CMP12]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4243 // CHECK3:       cond.true:
4244 // CHECK3-NEXT:    [[TMP12:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_3]], align 8
4245 // CHECK3-NEXT:    br label [[COND_END:%.*]]
4246 // CHECK3:       cond.false:
4247 // CHECK3-NEXT:    [[TMP13:%.*]] = load i64, ptr [[DOTOMP_COMB_UB]], align 8
4248 // CHECK3-NEXT:    br label [[COND_END]]
4249 // CHECK3:       cond.end:
4250 // CHECK3-NEXT:    [[COND:%.*]] = phi i64 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ]
4251 // CHECK3-NEXT:    store i64 [[COND]], ptr [[DOTOMP_COMB_UB]], align 8
4252 // CHECK3-NEXT:    [[TMP14:%.*]] = load i64, ptr [[DOTOMP_COMB_LB]], align 8
4253 // CHECK3-NEXT:    store i64 [[TMP14]], ptr [[DOTOMP_IV]], align 8
4254 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
4255 // CHECK3:       omp.inner.for.cond:
4256 // CHECK3-NEXT:    [[TMP15:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
4257 // CHECK3-NEXT:    [[TMP16:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_3]], align 8
4258 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i64 [[TMP16]], 1
4259 // CHECK3-NEXT:    [[CMP13:%.*]] = icmp slt i64 [[TMP15]], [[ADD]]
4260 // CHECK3-NEXT:    br i1 [[CMP13]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4261 // CHECK3:       omp.inner.for.body:
4262 // CHECK3-NEXT:    [[TMP17:%.*]] = load i64, ptr [[DOTOMP_COMB_LB]], align 8
4263 // CHECK3-NEXT:    [[TMP18:%.*]] = trunc i64 [[TMP17]] to i32
4264 // CHECK3-NEXT:    [[TMP19:%.*]] = load i64, ptr [[DOTOMP_COMB_UB]], align 8
4265 // CHECK3-NEXT:    [[TMP20:%.*]] = trunc i64 [[TMP19]] to i32
4266 // CHECK3-NEXT:    [[TMP21:%.*]] = load i32, ptr [[N_ADDR]], align 4
4267 // CHECK3-NEXT:    store i32 [[TMP21]], ptr [[N_CASTED]], align 4
4268 // CHECK3-NEXT:    [[TMP22:%.*]] = load i32, ptr [[N_CASTED]], align 4
4269 // CHECK3-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
4270 // CHECK3-NEXT:    [[TMP24:%.*]] = inttoptr i32 [[TMP18]] to ptr
4271 // CHECK3-NEXT:    store ptr [[TMP24]], ptr [[TMP23]], align 4
4272 // CHECK3-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
4273 // CHECK3-NEXT:    [[TMP26:%.*]] = inttoptr i32 [[TMP20]] to ptr
4274 // CHECK3-NEXT:    store ptr [[TMP26]], ptr [[TMP25]], align 4
4275 // CHECK3-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 2
4276 // CHECK3-NEXT:    [[TMP28:%.*]] = inttoptr i32 [[TMP22]] to ptr
4277 // CHECK3-NEXT:    store ptr [[TMP28]], ptr [[TMP27]], align 4
4278 // CHECK3-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 3
4279 // CHECK3-NEXT:    store ptr [[TMP0]], ptr [[TMP29]], align 4
4280 // CHECK3-NEXT:    [[TMP30:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
4281 // CHECK3-NEXT:    [[TMP31:%.*]] = load i32, ptr [[TMP30]], align 4
4282 // CHECK3-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP31]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l52_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 4)
4283 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4284 // CHECK3:       omp.inner.for.inc:
4285 // CHECK3-NEXT:    [[TMP32:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
4286 // CHECK3-NEXT:    [[TMP33:%.*]] = load i64, ptr [[DOTOMP_STRIDE]], align 8
4287 // CHECK3-NEXT:    [[ADD14:%.*]] = add nsw i64 [[TMP32]], [[TMP33]]
4288 // CHECK3-NEXT:    store i64 [[ADD14]], ptr [[DOTOMP_IV]], align 8
4289 // CHECK3-NEXT:    [[TMP34:%.*]] = load i64, ptr [[DOTOMP_COMB_LB]], align 8
4290 // CHECK3-NEXT:    [[TMP35:%.*]] = load i64, ptr [[DOTOMP_STRIDE]], align 8
4291 // CHECK3-NEXT:    [[ADD15:%.*]] = add nsw i64 [[TMP34]], [[TMP35]]
4292 // CHECK3-NEXT:    store i64 [[ADD15]], ptr [[DOTOMP_COMB_LB]], align 8
4293 // CHECK3-NEXT:    [[TMP36:%.*]] = load i64, ptr [[DOTOMP_COMB_UB]], align 8
4294 // CHECK3-NEXT:    [[TMP37:%.*]] = load i64, ptr [[DOTOMP_STRIDE]], align 8
4295 // CHECK3-NEXT:    [[ADD16:%.*]] = add nsw i64 [[TMP36]], [[TMP37]]
4296 // CHECK3-NEXT:    store i64 [[ADD16]], ptr [[DOTOMP_COMB_UB]], align 8
4297 // CHECK3-NEXT:    [[TMP38:%.*]] = load i64, ptr [[DOTOMP_COMB_UB]], align 8
4298 // CHECK3-NEXT:    [[TMP39:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_3]], align 8
4299 // CHECK3-NEXT:    [[CMP17:%.*]] = icmp sgt i64 [[TMP38]], [[TMP39]]
4300 // CHECK3-NEXT:    br i1 [[CMP17]], label [[COND_TRUE18:%.*]], label [[COND_FALSE19:%.*]]
4301 // CHECK3:       cond.true18:
4302 // CHECK3-NEXT:    [[TMP40:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_3]], align 8
4303 // CHECK3-NEXT:    br label [[COND_END20:%.*]]
4304 // CHECK3:       cond.false19:
4305 // CHECK3-NEXT:    [[TMP41:%.*]] = load i64, ptr [[DOTOMP_COMB_UB]], align 8
4306 // CHECK3-NEXT:    br label [[COND_END20]]
4307 // CHECK3:       cond.end20:
4308 // CHECK3-NEXT:    [[COND21:%.*]] = phi i64 [ [[TMP40]], [[COND_TRUE18]] ], [ [[TMP41]], [[COND_FALSE19]] ]
4309 // CHECK3-NEXT:    store i64 [[COND21]], ptr [[DOTOMP_COMB_UB]], align 8
4310 // CHECK3-NEXT:    [[TMP42:%.*]] = load i64, ptr [[DOTOMP_COMB_LB]], align 8
4311 // CHECK3-NEXT:    store i64 [[TMP42]], ptr [[DOTOMP_IV]], align 8
4312 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]]
4313 // CHECK3:       omp.inner.for.end:
4314 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
4315 // CHECK3:       omp.loop.exit:
4316 // CHECK3-NEXT:    [[TMP43:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
4317 // CHECK3-NEXT:    [[TMP44:%.*]] = load i32, ptr [[TMP43]], align 4
4318 // CHECK3-NEXT:    call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP44]])
4319 // CHECK3-NEXT:    br label [[OMP_PRECOND_END]]
4320 // CHECK3:       omp.precond.end:
4321 // CHECK3-NEXT:    ret void
4322 //
4323 //
4324 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l52_omp_outlined_omp_outlined
4325 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR1]] {
4326 // CHECK3-NEXT:  entry:
4327 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
4328 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
4329 // CHECK3-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
4330 // CHECK3-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
4331 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
4332 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
4333 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
4334 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
4335 // CHECK3-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
4336 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
4337 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
4338 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8
4339 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
4340 // CHECK3-NEXT:    [[J:%.*]] = alloca i32, align 4
4341 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
4342 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
4343 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
4344 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4345 // CHECK3-NEXT:    [[I11:%.*]] = alloca i32, align 4
4346 // CHECK3-NEXT:    [[J12:%.*]] = alloca i32, align 4
4347 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
4348 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
4349 // CHECK3-NEXT:    store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4
4350 // CHECK3-NEXT:    store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
4351 // CHECK3-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
4352 // CHECK3-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
4353 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 4
4354 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
4355 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
4356 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
4357 // CHECK3-NEXT:    store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_2]], align 4
4358 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
4359 // CHECK3-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
4360 // CHECK3-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1
4361 // CHECK3-NEXT:    [[CONV:%.*]] = sext i32 [[DIV]] to i64
4362 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
4363 // CHECK3-NEXT:    [[SUB4:%.*]] = sub nsw i32 [[TMP4]], 0
4364 // CHECK3-NEXT:    [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1
4365 // CHECK3-NEXT:    [[CONV6:%.*]] = sext i32 [[DIV5]] to i64
4366 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]]
4367 // CHECK3-NEXT:    [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1
4368 // CHECK3-NEXT:    store i64 [[SUB7]], ptr [[DOTCAPTURE_EXPR_3]], align 8
4369 // CHECK3-NEXT:    store i32 0, ptr [[I]], align 4
4370 // CHECK3-NEXT:    store i32 0, ptr [[J]], align 4
4371 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
4372 // CHECK3-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP5]]
4373 // CHECK3-NEXT:    br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]]
4374 // CHECK3:       land.lhs.true:
4375 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
4376 // CHECK3-NEXT:    [[CMP8:%.*]] = icmp slt i32 0, [[TMP6]]
4377 // CHECK3-NEXT:    br i1 [[CMP8]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]]
4378 // CHECK3:       omp.precond.then:
4379 // CHECK3-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8
4380 // CHECK3-NEXT:    [[TMP7:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_3]], align 8
4381 // CHECK3-NEXT:    store i64 [[TMP7]], ptr [[DOTOMP_UB]], align 8
4382 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4
4383 // CHECK3-NEXT:    [[CONV9:%.*]] = zext i32 [[TMP8]] to i64
4384 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
4385 // CHECK3-NEXT:    [[CONV10:%.*]] = zext i32 [[TMP9]] to i64
4386 // CHECK3-NEXT:    store i64 [[CONV9]], ptr [[DOTOMP_LB]], align 8
4387 // CHECK3-NEXT:    store i64 [[CONV10]], ptr [[DOTOMP_UB]], align 8
4388 // CHECK3-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8
4389 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
4390 // CHECK3-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
4391 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4
4392 // CHECK3-NEXT:    call void @__kmpc_for_static_init_8(ptr @[[GLOB3]], i32 [[TMP11]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
4393 // CHECK3-NEXT:    [[TMP12:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
4394 // CHECK3-NEXT:    store i64 [[TMP12]], ptr [[DOTOMP_IV]], align 8
4395 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
4396 // CHECK3:       omp.inner.for.cond:
4397 // CHECK3-NEXT:    [[TMP13:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
4398 // CHECK3-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
4399 // CHECK3-NEXT:    [[CONV13:%.*]] = zext i32 [[TMP14]] to i64
4400 // CHECK3-NEXT:    [[CMP14:%.*]] = icmp sle i64 [[TMP13]], [[CONV13]]
4401 // CHECK3-NEXT:    br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4402 // CHECK3:       omp.inner.for.body:
4403 // CHECK3-NEXT:    [[TMP15:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
4404 // CHECK3-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
4405 // CHECK3-NEXT:    [[SUB15:%.*]] = sub nsw i32 [[TMP16]], 0
4406 // CHECK3-NEXT:    [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1
4407 // CHECK3-NEXT:    [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]]
4408 // CHECK3-NEXT:    [[CONV18:%.*]] = sext i32 [[MUL17]] to i64
4409 // CHECK3-NEXT:    [[DIV19:%.*]] = sdiv i64 [[TMP15]], [[CONV18]]
4410 // CHECK3-NEXT:    [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1
4411 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i64 0, [[MUL20]]
4412 // CHECK3-NEXT:    [[CONV21:%.*]] = trunc i64 [[ADD]] to i32
4413 // CHECK3-NEXT:    store i32 [[CONV21]], ptr [[I11]], align 4
4414 // CHECK3-NEXT:    [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
4415 // CHECK3-NEXT:    [[TMP18:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
4416 // CHECK3-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
4417 // CHECK3-NEXT:    [[SUB22:%.*]] = sub nsw i32 [[TMP19]], 0
4418 // CHECK3-NEXT:    [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1
4419 // CHECK3-NEXT:    [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]]
4420 // CHECK3-NEXT:    [[CONV25:%.*]] = sext i32 [[MUL24]] to i64
4421 // CHECK3-NEXT:    [[DIV26:%.*]] = sdiv i64 [[TMP18]], [[CONV25]]
4422 // CHECK3-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
4423 // CHECK3-NEXT:    [[SUB27:%.*]] = sub nsw i32 [[TMP20]], 0
4424 // CHECK3-NEXT:    [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1
4425 // CHECK3-NEXT:    [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]]
4426 // CHECK3-NEXT:    [[CONV30:%.*]] = sext i32 [[MUL29]] to i64
4427 // CHECK3-NEXT:    [[MUL31:%.*]] = mul nsw i64 [[DIV26]], [[CONV30]]
4428 // CHECK3-NEXT:    [[SUB32:%.*]] = sub nsw i64 [[TMP17]], [[MUL31]]
4429 // CHECK3-NEXT:    [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 1
4430 // CHECK3-NEXT:    [[ADD34:%.*]] = add nsw i64 0, [[MUL33]]
4431 // CHECK3-NEXT:    [[CONV35:%.*]] = trunc i64 [[ADD34]] to i32
4432 // CHECK3-NEXT:    store i32 [[CONV35]], ptr [[J12]], align 4
4433 // CHECK3-NEXT:    [[TMP21:%.*]] = load i32, ptr [[I11]], align 4
4434 // CHECK3-NEXT:    [[TMP22:%.*]] = load i32, ptr [[J12]], align 4
4435 // CHECK3-NEXT:    [[ADD36:%.*]] = add nsw i32 [[TMP21]], [[TMP22]]
4436 // CHECK3-NEXT:    [[TMP23:%.*]] = load i32, ptr [[I11]], align 4
4437 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP0]], i32 0, i32 [[TMP23]]
4438 // CHECK3-NEXT:    [[TMP24:%.*]] = load i32, ptr [[J12]], align 4
4439 // CHECK3-NEXT:    [[ARRAYIDX37:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX]], i32 0, i32 [[TMP24]]
4440 // CHECK3-NEXT:    store i32 [[ADD36]], ptr [[ARRAYIDX37]], align 4
4441 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
4442 // CHECK3:       omp.body.continue:
4443 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4444 // CHECK3:       omp.inner.for.inc:
4445 // CHECK3-NEXT:    [[TMP25:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
4446 // CHECK3-NEXT:    [[TMP26:%.*]] = load i64, ptr [[DOTOMP_STRIDE]], align 8
4447 // CHECK3-NEXT:    [[ADD38:%.*]] = add nsw i64 [[TMP25]], [[TMP26]]
4448 // CHECK3-NEXT:    store i64 [[ADD38]], ptr [[DOTOMP_IV]], align 8
4449 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]]
4450 // CHECK3:       omp.inner.for.end:
4451 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
4452 // CHECK3:       omp.loop.exit:
4453 // CHECK3-NEXT:    [[TMP27:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
4454 // CHECK3-NEXT:    [[TMP28:%.*]] = load i32, ptr [[TMP27]], align 4
4455 // CHECK3-NEXT:    call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP28]])
4456 // CHECK3-NEXT:    br label [[OMP_PRECOND_END]]
4457 // CHECK3:       omp.precond.end:
4458 // CHECK3-NEXT:    ret void
4459 //
4460 //
4461 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l59
4462 // CHECK3-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], ptr noundef [[V:%.*]]) #[[ATTR0]] {
4463 // CHECK3-NEXT:  entry:
4464 // CHECK3-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
4465 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
4466 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 4
4467 // CHECK3-NEXT:    [[V_ADDR:%.*]] = alloca ptr, align 4
4468 // CHECK3-NEXT:    [[N_CASTED:%.*]] = alloca i32, align 4
4469 // CHECK3-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
4470 // CHECK3-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
4471 // CHECK3-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
4472 // CHECK3-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
4473 // CHECK3-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 4
4474 // CHECK3-NEXT:    store ptr [[V]], ptr [[V_ADDR]], align 4
4475 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4
4476 // CHECK3-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l59_kernel_environment, ptr [[DYN_PTR]])
4477 // CHECK3-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
4478 // CHECK3-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
4479 // CHECK3:       user_code.entry:
4480 // CHECK3-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
4481 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4
4482 // CHECK3-NEXT:    store i32 [[TMP3]], ptr [[N_CASTED]], align 4
4483 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N_CASTED]], align 4
4484 // CHECK3-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[V_ADDR]], align 4
4485 // CHECK3-NEXT:    store i32 0, ptr [[DOTZERO_ADDR]], align 4
4486 // CHECK3-NEXT:    store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4
4487 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l59_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i32 [[TMP4]], ptr [[TMP0]], ptr [[TMP5]]) #[[ATTR2]]
4488 // CHECK3-NEXT:    call void @__kmpc_target_deinit()
4489 // CHECK3-NEXT:    ret void
4490 // CHECK3:       worker.exit:
4491 // CHECK3-NEXT:    ret void
4492 //
4493 //
4494 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l59_omp_outlined
4495 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], ptr noundef [[V:%.*]]) #[[ATTR1]] {
4496 // CHECK3-NEXT:  entry:
4497 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
4498 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
4499 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
4500 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 4
4501 // CHECK3-NEXT:    [[V_ADDR:%.*]] = alloca ptr, align 4
4502 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
4503 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
4504 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
4505 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
4506 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
4507 // CHECK3-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
4508 // CHECK3-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
4509 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4510 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4511 // CHECK3-NEXT:    [[I3:%.*]] = alloca i32, align 4
4512 // CHECK3-NEXT:    [[N_CASTED:%.*]] = alloca i32, align 4
4513 // CHECK3-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [5 x ptr], align 4
4514 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
4515 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
4516 // CHECK3-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
4517 // CHECK3-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 4
4518 // CHECK3-NEXT:    store ptr [[V]], ptr [[V_ADDR]], align 4
4519 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4
4520 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
4521 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
4522 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
4523 // CHECK3-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
4524 // CHECK3-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1
4525 // CHECK3-NEXT:    [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
4526 // CHECK3-NEXT:    store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
4527 // CHECK3-NEXT:    store i32 0, ptr [[I]], align 4
4528 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
4529 // CHECK3-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]
4530 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
4531 // CHECK3:       omp.precond.then:
4532 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
4533 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
4534 // CHECK3-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_COMB_UB]], align 4
4535 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
4536 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
4537 // CHECK3-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
4538 // CHECK3-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
4539 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
4540 // CHECK3-NEXT:    call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP6]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
4541 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
4542 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
4543 // CHECK3-NEXT:    [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]]
4544 // CHECK3-NEXT:    br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4545 // CHECK3:       cond.true:
4546 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
4547 // CHECK3-NEXT:    br label [[COND_END:%.*]]
4548 // CHECK3:       cond.false:
4549 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
4550 // CHECK3-NEXT:    br label [[COND_END]]
4551 // CHECK3:       cond.end:
4552 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
4553 // CHECK3-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
4554 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
4555 // CHECK3-NEXT:    store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 4
4556 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
4557 // CHECK3:       omp.inner.for.cond:
4558 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4559 // CHECK3-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
4560 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP13]], 1
4561 // CHECK3-NEXT:    [[CMP5:%.*]] = icmp slt i32 [[TMP12]], [[ADD]]
4562 // CHECK3-NEXT:    br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4563 // CHECK3:       omp.inner.for.body:
4564 // CHECK3-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
4565 // CHECK3-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
4566 // CHECK3-NEXT:    [[TMP16:%.*]] = load i32, ptr [[N_ADDR]], align 4
4567 // CHECK3-NEXT:    store i32 [[TMP16]], ptr [[N_CASTED]], align 4
4568 // CHECK3-NEXT:    [[TMP17:%.*]] = load i32, ptr [[N_CASTED]], align 4
4569 // CHECK3-NEXT:    [[TMP18:%.*]] = load ptr, ptr [[V_ADDR]], align 4
4570 // CHECK3-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
4571 // CHECK3-NEXT:    [[TMP20:%.*]] = inttoptr i32 [[TMP14]] to ptr
4572 // CHECK3-NEXT:    store ptr [[TMP20]], ptr [[TMP19]], align 4
4573 // CHECK3-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
4574 // CHECK3-NEXT:    [[TMP22:%.*]] = inttoptr i32 [[TMP15]] to ptr
4575 // CHECK3-NEXT:    store ptr [[TMP22]], ptr [[TMP21]], align 4
4576 // CHECK3-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 2
4577 // CHECK3-NEXT:    [[TMP24:%.*]] = inttoptr i32 [[TMP17]] to ptr
4578 // CHECK3-NEXT:    store ptr [[TMP24]], ptr [[TMP23]], align 4
4579 // CHECK3-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 3
4580 // CHECK3-NEXT:    store ptr [[TMP0]], ptr [[TMP25]], align 4
4581 // CHECK3-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 4
4582 // CHECK3-NEXT:    store ptr [[TMP18]], ptr [[TMP26]], align 4
4583 // CHECK3-NEXT:    [[TMP27:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
4584 // CHECK3-NEXT:    [[TMP28:%.*]] = load i32, ptr [[TMP27]], align 4
4585 // CHECK3-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP28]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l59_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 5)
4586 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4587 // CHECK3:       omp.inner.for.inc:
4588 // CHECK3-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4589 // CHECK3-NEXT:    [[TMP30:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
4590 // CHECK3-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP29]], [[TMP30]]
4591 // CHECK3-NEXT:    store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4
4592 // CHECK3-NEXT:    [[TMP31:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
4593 // CHECK3-NEXT:    [[TMP32:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
4594 // CHECK3-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP31]], [[TMP32]]
4595 // CHECK3-NEXT:    store i32 [[ADD7]], ptr [[DOTOMP_COMB_LB]], align 4
4596 // CHECK3-NEXT:    [[TMP33:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
4597 // CHECK3-NEXT:    [[TMP34:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
4598 // CHECK3-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP33]], [[TMP34]]
4599 // CHECK3-NEXT:    store i32 [[ADD8]], ptr [[DOTOMP_COMB_UB]], align 4
4600 // CHECK3-NEXT:    [[TMP35:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
4601 // CHECK3-NEXT:    [[TMP36:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
4602 // CHECK3-NEXT:    [[CMP9:%.*]] = icmp sgt i32 [[TMP35]], [[TMP36]]
4603 // CHECK3-NEXT:    br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]]
4604 // CHECK3:       cond.true10:
4605 // CHECK3-NEXT:    [[TMP37:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
4606 // CHECK3-NEXT:    br label [[COND_END12:%.*]]
4607 // CHECK3:       cond.false11:
4608 // CHECK3-NEXT:    [[TMP38:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
4609 // CHECK3-NEXT:    br label [[COND_END12]]
4610 // CHECK3:       cond.end12:
4611 // CHECK3-NEXT:    [[COND13:%.*]] = phi i32 [ [[TMP37]], [[COND_TRUE10]] ], [ [[TMP38]], [[COND_FALSE11]] ]
4612 // CHECK3-NEXT:    store i32 [[COND13]], ptr [[DOTOMP_COMB_UB]], align 4
4613 // CHECK3-NEXT:    [[TMP39:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
4614 // CHECK3-NEXT:    store i32 [[TMP39]], ptr [[DOTOMP_IV]], align 4
4615 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]]
4616 // CHECK3:       omp.inner.for.end:
4617 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
4618 // CHECK3:       omp.loop.exit:
4619 // CHECK3-NEXT:    [[TMP40:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
4620 // CHECK3-NEXT:    [[TMP41:%.*]] = load i32, ptr [[TMP40]], align 4
4621 // CHECK3-NEXT:    call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP41]])
4622 // CHECK3-NEXT:    br label [[OMP_PRECOND_END]]
4623 // CHECK3:       omp.precond.end:
4624 // CHECK3-NEXT:    ret void
4625 //
4626 //
4627 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l59_omp_outlined_omp_outlined
4628 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], ptr noundef [[V:%.*]]) #[[ATTR1]] {
4629 // CHECK3-NEXT:  entry:
4630 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
4631 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
4632 // CHECK3-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
4633 // CHECK3-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
4634 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
4635 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 4
4636 // CHECK3-NEXT:    [[V_ADDR:%.*]] = alloca ptr, align 4
4637 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
4638 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
4639 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
4640 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
4641 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
4642 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
4643 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
4644 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4645 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4646 // CHECK3-NEXT:    [[I3:%.*]] = alloca i32, align 4
4647 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
4648 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
4649 // CHECK3-NEXT:    store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4
4650 // CHECK3-NEXT:    store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
4651 // CHECK3-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
4652 // CHECK3-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 4
4653 // CHECK3-NEXT:    store ptr [[V]], ptr [[V_ADDR]], align 4
4654 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4
4655 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
4656 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
4657 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
4658 // CHECK3-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
4659 // CHECK3-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1
4660 // CHECK3-NEXT:    [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
4661 // CHECK3-NEXT:    store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
4662 // CHECK3-NEXT:    store i32 0, ptr [[I]], align 4
4663 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
4664 // CHECK3-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]
4665 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
4666 // CHECK3:       omp.precond.then:
4667 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
4668 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
4669 // CHECK3-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4
4670 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4
4671 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
4672 // CHECK3-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_LB]], align 4
4673 // CHECK3-NEXT:    store i32 [[TMP6]], ptr [[DOTOMP_UB]], align 4
4674 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
4675 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
4676 // CHECK3-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
4677 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
4678 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP8]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
4679 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
4680 // CHECK3-NEXT:    store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4
4681 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
4682 // CHECK3:       omp.inner.for.cond:
4683 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4684 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
4685 // CHECK3-NEXT:    [[CMP4:%.*]] = icmp ule i32 [[TMP10]], [[TMP11]]
4686 // CHECK3-NEXT:    br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4687 // CHECK3:       omp.inner.for.body:
4688 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4689 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
4690 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
4691 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[I3]], align 4
4692 // CHECK3-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[V_ADDR]], align 4
4693 // CHECK3-NEXT:    [[TMP14:%.*]] = load i32, ptr [[I3]], align 4
4694 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP13]], i32 [[TMP14]]
4695 // CHECK3-NEXT:    [[TMP15:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
4696 // CHECK3-NEXT:    [[TMP16:%.*]] = load i32, ptr [[I3]], align 4
4697 // CHECK3-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], i32 0, i32 [[TMP16]]
4698 // CHECK3-NEXT:    store i32 [[TMP15]], ptr [[ARRAYIDX5]], align 4
4699 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
4700 // CHECK3:       omp.body.continue:
4701 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4702 // CHECK3:       omp.inner.for.inc:
4703 // CHECK3-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4704 // CHECK3-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
4705 // CHECK3-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP17]], [[TMP18]]
4706 // CHECK3-NEXT:    store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4
4707 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]]
4708 // CHECK3:       omp.inner.for.end:
4709 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
4710 // CHECK3:       omp.loop.exit:
4711 // CHECK3-NEXT:    [[TMP19:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
4712 // CHECK3-NEXT:    [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4
4713 // CHECK3-NEXT:    call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP20]])
4714 // CHECK3-NEXT:    br label [[OMP_PRECOND_END]]
4715 // CHECK3:       omp.precond.end:
4716 // CHECK3-NEXT:    ret void
4717 //