clang/test/OpenMP/nvptx_target_teams_generic_loop_codegen.cpp

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
   2 // Test target codegen - host bc file has to be created first.
   3 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc
   4 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK1
   5 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -fopenmp-optimistic-collapse -o - | FileCheck %s --check-prefix=CHECK2
   6 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple i386-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm-bc %s -o %t-x86-host.bc
   7 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK3
   8 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -fexceptions -fcxx-exceptions -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK3
   9
  10 // expected-no-diagnostics
  11 #ifndef HEADER
  12 #define HEADER
  13
  14 #define N 1000
  15 #define M 10
  16
  17 template<typename tx>
  18 tx ftemplate(int n) {
  19   tx a[N];
  20   short aa[N];
  21   tx b[10];
  22   tx c[M][M];
  23   tx f = n;
  24   tx l;
  25   int k;
  26   tx *v;
  27
  28 #pragma omp target teams loop map(tofrom: aa) num_teams(M) thread_limit(64)
  29   for(int i = 0; i < n; i++) {
  30     aa[i] += 1;
  31   }
  32
  33 #pragma omp target teams loop map(tofrom:a, aa, b) if(target: n>40)
  34   for(int i = 0; i < 10; i++) {
  35     b[i] += 1;
  36   }
  37
  38 #pragma omp target teams loop collapse(2) firstprivate(f) private(k)
  39   for(int i = 0; i < M; i++) {
  40     for(int j = 0; j < M; j++) {
  41       k = M;
  42       c[i][j] = i + j * f + k;
  43     }
  44   }
  45
  46 #pragma omp target teams loop collapse(2)
  47   for(int i = 0; i < n; i++) {
  48     for(int j = 0; j < n; j++) {
  49       c[i][j] = i + j;
  50     }
  51   }
  52
  53 #pragma omp target teams loop map(a, v[:N])
  54   for(int i = 0; i < n; i++)
  55     a[i] = v[i];
  56   return a[0];
  57 }
  58
  59 int bar(int n){
  60   int a = 0;
  61
  62   a += ftemplate<int>(n);
  63
  64   return a;
  65 }
  66
  67 #endif
  68 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28
  69 // CHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR0:[0-9]+]] {
  70 // CHECK1-NEXT:  entry:
  71 // CHECK1-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
  72 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
  73 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca ptr, align 8
  74 // CHECK1-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8
  75 // CHECK1-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
  76 // CHECK1-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
  77 // CHECK1-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
  78 // CHECK1-NEXT:    store i64 [[N]], ptr [[N_ADDR]], align 8
  79 // CHECK1-NEXT:    store ptr [[AA]], ptr [[AA_ADDR]], align 8
  80 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8
  81 // CHECK1-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28_kernel_environment, ptr [[DYN_PTR]])
  82 // CHECK1-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
  83 // CHECK1-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
  84 // CHECK1:       user_code.entry:
  85 // CHECK1-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
  86 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4
  87 // CHECK1-NEXT:    store i32 [[TMP3]], ptr [[N_CASTED]], align 4
  88 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8
  89 // CHECK1-NEXT:    store i32 0, ptr [[DOTZERO_ADDR]], align 4
  90 // CHECK1-NEXT:    store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4
  91 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i64 [[TMP4]], ptr [[TMP0]]) #[[ATTR2:[0-9]+]]
  92 // CHECK1-NEXT:    call void @__kmpc_target_deinit()
  93 // CHECK1-NEXT:    ret void
  94 // CHECK1:       worker.exit:
  95 // CHECK1-NEXT:    ret void
  96 //
  97 //
  98 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28_omp_outlined
  99 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR1:[0-9]+]] {
 100 // CHECK1-NEXT:  entry:
 101 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 102 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 103 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
 104 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca ptr, align 8
 105 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 106 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 107 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
 108 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
 109 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
 110 // CHECK1-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
 111 // CHECK1-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
 112 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 113 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 114 // CHECK1-NEXT:    [[I3:%.*]] = alloca i32, align 4
 115 // CHECK1-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8
 116 // CHECK1-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [4 x ptr], align 8
 117 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 118 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 119 // CHECK1-NEXT:    store i64 [[N]], ptr [[N_ADDR]], align 8
 120 // CHECK1-NEXT:    store ptr [[AA]], ptr [[AA_ADDR]], align 8
 121 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8
 122 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
 123 // CHECK1-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
 124 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
 125 // CHECK1-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
 126 // CHECK1-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1
 127 // CHECK1-NEXT:    [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
 128 // CHECK1-NEXT:    store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
 129 // CHECK1-NEXT:    store i32 0, ptr [[I]], align 4
 130 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
 131 // CHECK1-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]
 132 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
 133 // CHECK1:       omp.precond.then:
 134 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
 135 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
 136 // CHECK1-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_COMB_UB]], align 4
 137 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 138 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 139 // CHECK1-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
 140 // CHECK1-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 141 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
 142 // CHECK1-NEXT:    call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP6]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
 143 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 144 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
 145 // CHECK1-NEXT:    [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]]
 146 // CHECK1-NEXT:    br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 147 // CHECK1:       cond.true:
 148 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
 149 // CHECK1-NEXT:    br label [[COND_END:%.*]]
 150 // CHECK1:       cond.false:
 151 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 152 // CHECK1-NEXT:    br label [[COND_END]]
 153 // CHECK1:       cond.end:
 154 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
 155 // CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
 156 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
 157 // CHECK1-NEXT:    store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 4
 158 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 159 // CHECK1:       omp.inner.for.cond:
 160 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 161 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
 162 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP13]], 1
 163 // CHECK1-NEXT:    [[CMP5:%.*]] = icmp slt i32 [[TMP12]], [[ADD]]
 164 // CHECK1-NEXT:    br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 165 // CHECK1:       omp.inner.for.body:
 166 // CHECK1-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
 167 // CHECK1-NEXT:    [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
 168 // CHECK1-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 169 // CHECK1-NEXT:    [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
 170 // CHECK1-NEXT:    [[TMP18:%.*]] = load i32, ptr [[N_ADDR]], align 4
 171 // CHECK1-NEXT:    store i32 [[TMP18]], ptr [[N_CASTED]], align 4
 172 // CHECK1-NEXT:    [[TMP19:%.*]] = load i64, ptr [[N_CASTED]], align 8
 173 // CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
 174 // CHECK1-NEXT:    [[TMP21:%.*]] = inttoptr i64 [[TMP15]] to ptr
 175 // CHECK1-NEXT:    store ptr [[TMP21]], ptr [[TMP20]], align 8
 176 // CHECK1-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
 177 // CHECK1-NEXT:    [[TMP23:%.*]] = inttoptr i64 [[TMP17]] to ptr
 178 // CHECK1-NEXT:    store ptr [[TMP23]], ptr [[TMP22]], align 8
 179 // CHECK1-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
 180 // CHECK1-NEXT:    [[TMP25:%.*]] = inttoptr i64 [[TMP19]] to ptr
 181 // CHECK1-NEXT:    store ptr [[TMP25]], ptr [[TMP24]], align 8
 182 // CHECK1-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3
 183 // CHECK1-NEXT:    store ptr [[TMP0]], ptr [[TMP26]], align 8
 184 // CHECK1-NEXT:    [[TMP27:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 185 // CHECK1-NEXT:    [[TMP28:%.*]] = load i32, ptr [[TMP27]], align 4
 186 // CHECK1-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP28]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 4)
 187 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 188 // CHECK1:       omp.inner.for.inc:
 189 // CHECK1-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 190 // CHECK1-NEXT:    [[TMP30:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
 191 // CHECK1-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP29]], [[TMP30]]
 192 // CHECK1-NEXT:    store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4
 193 // CHECK1-NEXT:    [[TMP31:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
 194 // CHECK1-NEXT:    [[TMP32:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
 195 // CHECK1-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP31]], [[TMP32]]
 196 // CHECK1-NEXT:    store i32 [[ADD7]], ptr [[DOTOMP_COMB_LB]], align 4
 197 // CHECK1-NEXT:    [[TMP33:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 198 // CHECK1-NEXT:    [[TMP34:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
 199 // CHECK1-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP33]], [[TMP34]]
 200 // CHECK1-NEXT:    store i32 [[ADD8]], ptr [[DOTOMP_COMB_UB]], align 4
 201 // CHECK1-NEXT:    [[TMP35:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 202 // CHECK1-NEXT:    [[TMP36:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
 203 // CHECK1-NEXT:    [[CMP9:%.*]] = icmp sgt i32 [[TMP35]], [[TMP36]]
 204 // CHECK1-NEXT:    br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]]
 205 // CHECK1:       cond.true10:
 206 // CHECK1-NEXT:    [[TMP37:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
 207 // CHECK1-NEXT:    br label [[COND_END12:%.*]]
 208 // CHECK1:       cond.false11:
 209 // CHECK1-NEXT:    [[TMP38:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 210 // CHECK1-NEXT:    br label [[COND_END12]]
 211 // CHECK1:       cond.end12:
 212 // CHECK1-NEXT:    [[COND13:%.*]] = phi i32 [ [[TMP37]], [[COND_TRUE10]] ], [ [[TMP38]], [[COND_FALSE11]] ]
 213 // CHECK1-NEXT:    store i32 [[COND13]], ptr [[DOTOMP_COMB_UB]], align 4
 214 // CHECK1-NEXT:    [[TMP39:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
 215 // CHECK1-NEXT:    store i32 [[TMP39]], ptr [[DOTOMP_IV]], align 4
 216 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]
 217 // CHECK1:       omp.inner.for.end:
 218 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
 219 // CHECK1:       omp.loop.exit:
 220 // CHECK1-NEXT:    [[TMP40:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 221 // CHECK1-NEXT:    [[TMP41:%.*]] = load i32, ptr [[TMP40]], align 4
 222 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB3:[0-9]+]], i32 [[TMP41]])
 223 // CHECK1-NEXT:    br label [[OMP_PRECOND_END]]
 224 // CHECK1:       omp.precond.end:
 225 // CHECK1-NEXT:    ret void
 226 //
 227 //
 228 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28_omp_outlined_omp_outlined
 229 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR1]] {
 230 // CHECK1-NEXT:  entry:
 231 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 232 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 233 // CHECK1-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
 234 // CHECK1-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
 235 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
 236 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca ptr, align 8
 237 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 238 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 239 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
 240 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
 241 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
 242 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
 243 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
 244 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 245 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 246 // CHECK1-NEXT:    [[I4:%.*]] = alloca i32, align 4
 247 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 248 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 249 // CHECK1-NEXT:    store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
 250 // CHECK1-NEXT:    store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
 251 // CHECK1-NEXT:    store i64 [[N]], ptr [[N_ADDR]], align 8
 252 // CHECK1-NEXT:    store ptr [[AA]], ptr [[AA_ADDR]], align 8
 253 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8
 254 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
 255 // CHECK1-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
 256 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
 257 // CHECK1-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
 258 // CHECK1-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1
 259 // CHECK1-NEXT:    [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
 260 // CHECK1-NEXT:    store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
 261 // CHECK1-NEXT:    store i32 0, ptr [[I]], align 4
 262 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
 263 // CHECK1-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]
 264 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
 265 // CHECK1:       omp.precond.then:
 266 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
 267 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
 268 // CHECK1-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4
 269 // CHECK1-NEXT:    [[TMP5:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
 270 // CHECK1-NEXT:    [[CONV:%.*]] = trunc i64 [[TMP5]] to i32
 271 // CHECK1-NEXT:    [[TMP6:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
 272 // CHECK1-NEXT:    [[CONV3:%.*]] = trunc i64 [[TMP6]] to i32
 273 // CHECK1-NEXT:    store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
 274 // CHECK1-NEXT:    store i32 [[CONV3]], ptr [[DOTOMP_UB]], align 4
 275 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 276 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 277 // CHECK1-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 278 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
 279 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP8]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
 280 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
 281 // CHECK1-NEXT:    store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4
 282 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 283 // CHECK1:       omp.inner.for.cond:
 284 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 285 // CHECK1-NEXT:    [[CONV5:%.*]] = sext i32 [[TMP10]] to i64
 286 // CHECK1-NEXT:    [[TMP11:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
 287 // CHECK1-NEXT:    [[CMP6:%.*]] = icmp ule i64 [[CONV5]], [[TMP11]]
 288 // CHECK1-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 289 // CHECK1:       omp.inner.for.body:
 290 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 291 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
 292 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
 293 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[I4]], align 4
 294 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, ptr [[I4]], align 4
 295 // CHECK1-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64
 296 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], ptr [[TMP0]], i64 0, i64 [[IDXPROM]]
 297 // CHECK1-NEXT:    [[TMP14:%.*]] = load i16, ptr [[ARRAYIDX]], align 2
 298 // CHECK1-NEXT:    [[CONV7:%.*]] = sext i16 [[TMP14]] to i32
 299 // CHECK1-NEXT:    [[ADD8:%.*]] = add nsw i32 [[CONV7]], 1
 300 // CHECK1-NEXT:    [[CONV9:%.*]] = trunc i32 [[ADD8]] to i16
 301 // CHECK1-NEXT:    store i16 [[CONV9]], ptr [[ARRAYIDX]], align 2
 302 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 303 // CHECK1:       omp.body.continue:
 304 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 305 // CHECK1:       omp.inner.for.inc:
 306 // CHECK1-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 307 // CHECK1-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
 308 // CHECK1-NEXT:    [[ADD10:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
 309 // CHECK1-NEXT:    store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4
 310 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]
 311 // CHECK1:       omp.inner.for.end:
 312 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
 313 // CHECK1:       omp.loop.exit:
 314 // CHECK1-NEXT:    [[TMP17:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 315 // CHECK1-NEXT:    [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 4
 316 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP18]])
 317 // CHECK1-NEXT:    br label [[OMP_PRECOND_END]]
 318 // CHECK1:       omp.precond.end:
 319 // CHECK1-NEXT:    ret void
 320 //
 321 //
 322 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l33
 323 // CHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR4:[0-9]+]] {
 324 // CHECK1-NEXT:  entry:
 325 // CHECK1-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
 326 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
 327 // CHECK1-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
 328 // CHECK1-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
 329 // CHECK1-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
 330 // CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
 331 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
 332 // CHECK1-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l33_kernel_environment, ptr [[DYN_PTR]])
 333 // CHECK1-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
 334 // CHECK1-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
 335 // CHECK1:       user_code.entry:
 336 // CHECK1-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
 337 // CHECK1-NEXT:    store i32 0, ptr [[DOTZERO_ADDR]], align 4
 338 // CHECK1-NEXT:    store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4
 339 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l33_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]]) #[[ATTR2]]
 340 // CHECK1-NEXT:    call void @__kmpc_target_deinit()
 341 // CHECK1-NEXT:    ret void
 342 // CHECK1:       worker.exit:
 343 // CHECK1-NEXT:    ret void
 344 //
 345 //
 346 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l33_omp_outlined
 347 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
 348 // CHECK1-NEXT:  entry:
 349 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 350 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 351 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
 352 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 353 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 354 // CHECK1-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
 355 // CHECK1-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
 356 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 357 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 358 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
 359 // CHECK1-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x ptr], align 8
 360 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 361 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 362 // CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
 363 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
 364 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
 365 // CHECK1-NEXT:    store i32 9, ptr [[DOTOMP_COMB_UB]], align 4
 366 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 367 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 368 // CHECK1-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
 369 // CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 370 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
 371 // CHECK1-NEXT:    call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP2]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
 372 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 373 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
 374 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 375 // CHECK1:       cond.true:
 376 // CHECK1-NEXT:    br label [[COND_END:%.*]]
 377 // CHECK1:       cond.false:
 378 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 379 // CHECK1-NEXT:    br label [[COND_END]]
 380 // CHECK1:       cond.end:
 381 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
 382 // CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
 383 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
 384 // CHECK1-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
 385 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 386 // CHECK1:       omp.inner.for.cond:
 387 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 388 // CHECK1-NEXT:    [[CMP1:%.*]] = icmp slt i32 [[TMP6]], 10
 389 // CHECK1-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 390 // CHECK1:       omp.inner.for.body:
 391 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
 392 // CHECK1-NEXT:    [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
 393 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 394 // CHECK1-NEXT:    [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
 395 // CHECK1-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
 396 // CHECK1-NEXT:    [[TMP12:%.*]] = inttoptr i64 [[TMP8]] to ptr
 397 // CHECK1-NEXT:    store ptr [[TMP12]], ptr [[TMP11]], align 8
 398 // CHECK1-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
 399 // CHECK1-NEXT:    [[TMP14:%.*]] = inttoptr i64 [[TMP10]] to ptr
 400 // CHECK1-NEXT:    store ptr [[TMP14]], ptr [[TMP13]], align 8
 401 // CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
 402 // CHECK1-NEXT:    store ptr [[TMP0]], ptr [[TMP15]], align 8
 403 // CHECK1-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l33_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 3)
 404 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 405 // CHECK1:       omp.inner.for.inc:
 406 // CHECK1-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 407 // CHECK1-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
 408 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
 409 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
 410 // CHECK1-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
 411 // CHECK1-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
 412 // CHECK1-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
 413 // CHECK1-NEXT:    store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4
 414 // CHECK1-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 415 // CHECK1-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
 416 // CHECK1-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]
 417 // CHECK1-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4
 418 // CHECK1-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 419 // CHECK1-NEXT:    [[CMP4:%.*]] = icmp sgt i32 [[TMP22]], 9
 420 // CHECK1-NEXT:    br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
 421 // CHECK1:       cond.true5:
 422 // CHECK1-NEXT:    br label [[COND_END7:%.*]]
 423 // CHECK1:       cond.false6:
 424 // CHECK1-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 425 // CHECK1-NEXT:    br label [[COND_END7]]
 426 // CHECK1:       cond.end7:
 427 // CHECK1-NEXT:    [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP23]], [[COND_FALSE6]] ]
 428 // CHECK1-NEXT:    store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4
 429 // CHECK1-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
 430 // CHECK1-NEXT:    store i32 [[TMP24]], ptr [[DOTOMP_IV]], align 4
 431 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]
 432 // CHECK1:       omp.inner.for.end:
 433 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
 434 // CHECK1:       omp.loop.exit:
 435 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP2]])
 436 // CHECK1-NEXT:    ret void
 437 //
 438 //
 439 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l33_omp_outlined_omp_outlined
 440 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
 441 // CHECK1-NEXT:  entry:
 442 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 443 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 444 // CHECK1-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
 445 // CHECK1-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
 446 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
 447 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 448 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 449 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
 450 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
 451 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 452 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 453 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
 454 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 455 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 456 // CHECK1-NEXT:    store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
 457 // CHECK1-NEXT:    store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
 458 // CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
 459 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
 460 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
 461 // CHECK1-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4
 462 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
 463 // CHECK1-NEXT:    [[CONV:%.*]] = trunc i64 [[TMP1]] to i32
 464 // CHECK1-NEXT:    [[TMP2:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
 465 // CHECK1-NEXT:    [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32
 466 // CHECK1-NEXT:    store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
 467 // CHECK1-NEXT:    store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4
 468 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 469 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 470 // CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 471 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
 472 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP4]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
 473 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
 474 // CHECK1-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
 475 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 476 // CHECK1:       omp.inner.for.cond:
 477 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 478 // CHECK1-NEXT:    [[CONV2:%.*]] = sext i32 [[TMP6]] to i64
 479 // CHECK1-NEXT:    [[TMP7:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
 480 // CHECK1-NEXT:    [[CMP:%.*]] = icmp ule i64 [[CONV2]], [[TMP7]]
 481 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 482 // CHECK1:       omp.inner.for.body:
 483 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 484 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
 485 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
 486 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[I]], align 4
 487 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[I]], align 4
 488 // CHECK1-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64
 489 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]]
 490 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
 491 // CHECK1-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
 492 // CHECK1-NEXT:    store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4
 493 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 494 // CHECK1:       omp.body.continue:
 495 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 496 // CHECK1:       omp.inner.for.inc:
 497 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 498 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
 499 // CHECK1-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
 500 // CHECK1-NEXT:    store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4
 501 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]
 502 // CHECK1:       omp.inner.for.end:
 503 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
 504 // CHECK1:       omp.loop.exit:
 505 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP4]])
 506 // CHECK1-NEXT:    ret void
 507 //
 508 //
 509 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l38
 510 // CHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i64 noundef [[F:%.*]]) #[[ATTR4]] {
 511 // CHECK1-NEXT:  entry:
 512 // CHECK1-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
 513 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
 514 // CHECK1-NEXT:    [[F_ADDR:%.*]] = alloca i64, align 8
 515 // CHECK1-NEXT:    [[F_CASTED:%.*]] = alloca i64, align 8
 516 // CHECK1-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
 517 // CHECK1-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
 518 // CHECK1-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
 519 // CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
 520 // CHECK1-NEXT:    store i64 [[F]], ptr [[F_ADDR]], align 8
 521 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8
 522 // CHECK1-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l38_kernel_environment, ptr [[DYN_PTR]])
 523 // CHECK1-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
 524 // CHECK1-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
 525 // CHECK1:       user_code.entry:
 526 // CHECK1-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
 527 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[F_ADDR]], align 4
 528 // CHECK1-NEXT:    store i32 [[TMP3]], ptr [[F_CASTED]], align 4
 529 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, ptr [[F_CASTED]], align 8
 530 // CHECK1-NEXT:    store i32 0, ptr [[DOTZERO_ADDR]], align 4
 531 // CHECK1-NEXT:    store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4
 532 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l38_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]], i64 [[TMP4]]) #[[ATTR2]]
 533 // CHECK1-NEXT:    call void @__kmpc_target_deinit()
 534 // CHECK1-NEXT:    ret void
 535 // CHECK1:       worker.exit:
 536 // CHECK1-NEXT:    ret void
 537 //
 538 //
 539 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l38_omp_outlined
 540 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i64 noundef [[F:%.*]]) #[[ATTR1]] {
 541 // CHECK1-NEXT:  entry:
 542 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 543 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 544 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
 545 // CHECK1-NEXT:    [[F_ADDR:%.*]] = alloca i64, align 8
 546 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 547 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 548 // CHECK1-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
 549 // CHECK1-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
 550 // CHECK1-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
 551 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 552 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 553 // CHECK1-NEXT:    [[K:%.*]] = alloca i32, align 4
 554 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
 555 // CHECK1-NEXT:    [[J:%.*]] = alloca i32, align 4
 556 // CHECK1-NEXT:    [[F_CASTED:%.*]] = alloca i64, align 8
 557 // CHECK1-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [4 x ptr], align 8
 558 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 559 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 560 // CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
 561 // CHECK1-NEXT:    store i64 [[F]], ptr [[F_ADDR]], align 8
 562 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8
 563 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
 564 // CHECK1-NEXT:    store i32 99, ptr [[DOTOMP_COMB_UB]], align 4
 565 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 566 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 567 // CHECK1-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
 568 // CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 569 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
 570 // CHECK1-NEXT:    call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP2]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
 571 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 572 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 99
 573 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 574 // CHECK1:       cond.true:
 575 // CHECK1-NEXT:    br label [[COND_END:%.*]]
 576 // CHECK1:       cond.false:
 577 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 578 // CHECK1-NEXT:    br label [[COND_END]]
 579 // CHECK1:       cond.end:
 580 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
 581 // CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
 582 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
 583 // CHECK1-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
 584 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 585 // CHECK1:       omp.inner.for.cond:
 586 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 587 // CHECK1-NEXT:    [[CMP2:%.*]] = icmp slt i32 [[TMP6]], 100
 588 // CHECK1-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 589 // CHECK1:       omp.inner.for.body:
 590 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
 591 // CHECK1-NEXT:    [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
 592 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 593 // CHECK1-NEXT:    [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
 594 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[F_ADDR]], align 4
 595 // CHECK1-NEXT:    store i32 [[TMP11]], ptr [[F_CASTED]], align 4
 596 // CHECK1-NEXT:    [[TMP12:%.*]] = load i64, ptr [[F_CASTED]], align 8
 597 // CHECK1-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
 598 // CHECK1-NEXT:    [[TMP14:%.*]] = inttoptr i64 [[TMP8]] to ptr
 599 // CHECK1-NEXT:    store ptr [[TMP14]], ptr [[TMP13]], align 8
 600 // CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
 601 // CHECK1-NEXT:    [[TMP16:%.*]] = inttoptr i64 [[TMP10]] to ptr
 602 // CHECK1-NEXT:    store ptr [[TMP16]], ptr [[TMP15]], align 8
 603 // CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
 604 // CHECK1-NEXT:    store ptr [[TMP0]], ptr [[TMP17]], align 8
 605 // CHECK1-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3
 606 // CHECK1-NEXT:    [[TMP19:%.*]] = inttoptr i64 [[TMP12]] to ptr
 607 // CHECK1-NEXT:    store ptr [[TMP19]], ptr [[TMP18]], align 8
 608 // CHECK1-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l38_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 4)
 609 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 610 // CHECK1:       omp.inner.for.inc:
 611 // CHECK1-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 612 // CHECK1-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
 613 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]
 614 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
 615 // CHECK1-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
 616 // CHECK1-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
 617 // CHECK1-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]
 618 // CHECK1-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_COMB_LB]], align 4
 619 // CHECK1-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 620 // CHECK1-NEXT:    [[TMP25:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
 621 // CHECK1-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP24]], [[TMP25]]
 622 // CHECK1-NEXT:    store i32 [[ADD4]], ptr [[DOTOMP_COMB_UB]], align 4
 623 // CHECK1-NEXT:    [[TMP26:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 624 // CHECK1-NEXT:    [[CMP5:%.*]] = icmp sgt i32 [[TMP26]], 99
 625 // CHECK1-NEXT:    br i1 [[CMP5]], label [[COND_TRUE6:%.*]], label [[COND_FALSE7:%.*]]
 626 // CHECK1:       cond.true6:
 627 // CHECK1-NEXT:    br label [[COND_END8:%.*]]
 628 // CHECK1:       cond.false7:
 629 // CHECK1-NEXT:    [[TMP27:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 630 // CHECK1-NEXT:    br label [[COND_END8]]
 631 // CHECK1:       cond.end8:
 632 // CHECK1-NEXT:    [[COND9:%.*]] = phi i32 [ 99, [[COND_TRUE6]] ], [ [[TMP27]], [[COND_FALSE7]] ]
 633 // CHECK1-NEXT:    store i32 [[COND9]], ptr [[DOTOMP_COMB_UB]], align 4
 634 // CHECK1-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
 635 // CHECK1-NEXT:    store i32 [[TMP28]], ptr [[DOTOMP_IV]], align 4
 636 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]
 637 // CHECK1:       omp.inner.for.end:
 638 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
 639 // CHECK1:       omp.loop.exit:
 640 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP2]])
 641 // CHECK1-NEXT:    ret void
 642 //
 643 //
 644 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l38_omp_outlined_omp_outlined
 645 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i64 noundef [[F:%.*]]) #[[ATTR1]] {
 646 // CHECK1-NEXT:  entry:
 647 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 648 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 649 // CHECK1-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
 650 // CHECK1-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
 651 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
 652 // CHECK1-NEXT:    [[F_ADDR:%.*]] = alloca i64, align 8
 653 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 654 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 655 // CHECK1-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
 656 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
 657 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
 658 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 659 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 660 // CHECK1-NEXT:    [[K:%.*]] = alloca i32, align 4
 661 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
 662 // CHECK1-NEXT:    [[J:%.*]] = alloca i32, align 4
 663 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 664 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 665 // CHECK1-NEXT:    store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
 666 // CHECK1-NEXT:    store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
 667 // CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
 668 // CHECK1-NEXT:    store i64 [[F]], ptr [[F_ADDR]], align 8
 669 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8
 670 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
 671 // CHECK1-NEXT:    store i32 99, ptr [[DOTOMP_UB]], align 4
 672 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
 673 // CHECK1-NEXT:    [[CONV:%.*]] = trunc i64 [[TMP1]] to i32
 674 // CHECK1-NEXT:    [[TMP2:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
 675 // CHECK1-NEXT:    [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32
 676 // CHECK1-NEXT:    store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
 677 // CHECK1-NEXT:    store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4
 678 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 679 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 680 // CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 681 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
 682 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP4]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
 683 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
 684 // CHECK1-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
 685 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 686 // CHECK1:       omp.inner.for.cond:
 687 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 688 // CHECK1-NEXT:    [[CONV3:%.*]] = sext i32 [[TMP6]] to i64
 689 // CHECK1-NEXT:    [[TMP7:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
 690 // CHECK1-NEXT:    [[CMP:%.*]] = icmp ule i64 [[CONV3]], [[TMP7]]
 691 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 692 // CHECK1:       omp.inner.for.body:
 693 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 694 // CHECK1-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP8]], 10
 695 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
 696 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
 697 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[I]], align 4
 698 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 699 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 700 // CHECK1-NEXT:    [[DIV4:%.*]] = sdiv i32 [[TMP10]], 10
 701 // CHECK1-NEXT:    [[MUL5:%.*]] = mul nsw i32 [[DIV4]], 10
 702 // CHECK1-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL5]]
 703 // CHECK1-NEXT:    [[MUL6:%.*]] = mul nsw i32 [[SUB]], 1
 704 // CHECK1-NEXT:    [[ADD7:%.*]] = add nsw i32 0, [[MUL6]]
 705 // CHECK1-NEXT:    store i32 [[ADD7]], ptr [[J]], align 4
 706 // CHECK1-NEXT:    store i32 10, ptr [[K]], align 4
 707 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 4
 708 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[J]], align 4
 709 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, ptr [[F_ADDR]], align 4
 710 // CHECK1-NEXT:    [[MUL8:%.*]] = mul nsw i32 [[TMP12]], [[TMP13]]
 711 // CHECK1-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP11]], [[MUL8]]
 712 // CHECK1-NEXT:    [[TMP14:%.*]] = load i32, ptr [[K]], align 4
 713 // CHECK1-NEXT:    [[ADD10:%.*]] = add nsw i32 [[ADD9]], [[TMP14]]
 714 // CHECK1-NEXT:    [[TMP15:%.*]] = load i32, ptr [[I]], align 4
 715 // CHECK1-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64
 716 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP0]], i64 0, i64 [[IDXPROM]]
 717 // CHECK1-NEXT:    [[TMP16:%.*]] = load i32, ptr [[J]], align 4
 718 // CHECK1-NEXT:    [[IDXPROM11:%.*]] = sext i32 [[TMP16]] to i64
 719 // CHECK1-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM11]]
 720 // CHECK1-NEXT:    store i32 [[ADD10]], ptr [[ARRAYIDX12]], align 4
 721 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 722 // CHECK1:       omp.body.continue:
 723 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 724 // CHECK1:       omp.inner.for.inc:
 725 // CHECK1-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 726 // CHECK1-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
 727 // CHECK1-NEXT:    [[ADD13:%.*]] = add nsw i32 [[TMP17]], [[TMP18]]
 728 // CHECK1-NEXT:    store i32 [[ADD13]], ptr [[DOTOMP_IV]], align 4
 729 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]
 730 // CHECK1:       omp.inner.for.end:
 731 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
 732 // CHECK1:       omp.loop.exit:
 733 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP4]])
 734 // CHECK1-NEXT:    ret void
 735 //
 736 //
 737 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l46
 738 // CHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR4]] {
 739 // CHECK1-NEXT:  entry:
 740 // CHECK1-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
 741 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
 742 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
 743 // CHECK1-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8
 744 // CHECK1-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
 745 // CHECK1-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
 746 // CHECK1-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
 747 // CHECK1-NEXT:    store i64 [[N]], ptr [[N_ADDR]], align 8
 748 // CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
 749 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8
 750 // CHECK1-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l46_kernel_environment, ptr [[DYN_PTR]])
 751 // CHECK1-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
 752 // CHECK1-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
 753 // CHECK1:       user_code.entry:
 754 // CHECK1-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
 755 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4
 756 // CHECK1-NEXT:    store i32 [[TMP3]], ptr [[N_CASTED]], align 4
 757 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8
 758 // CHECK1-NEXT:    store i32 0, ptr [[DOTZERO_ADDR]], align 4
 759 // CHECK1-NEXT:    store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4
 760 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l46_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i64 [[TMP4]], ptr [[TMP0]]) #[[ATTR2]]
 761 // CHECK1-NEXT:    call void @__kmpc_target_deinit()
 762 // CHECK1-NEXT:    ret void
 763 // CHECK1:       worker.exit:
 764 // CHECK1-NEXT:    ret void
 765 //
 766 //
 767 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l46_omp_outlined
 768 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR1]] {
 769 // CHECK1-NEXT:  entry:
 770 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 771 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 772 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
 773 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
 774 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
 775 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 776 // CHECK1-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
 777 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
 778 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
 779 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8
 780 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
 781 // CHECK1-NEXT:    [[J:%.*]] = alloca i32, align 4
 782 // CHECK1-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i64, align 8
 783 // CHECK1-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i64, align 8
 784 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
 785 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 786 // CHECK1-NEXT:    [[I9:%.*]] = alloca i32, align 4
 787 // CHECK1-NEXT:    [[J10:%.*]] = alloca i32, align 4
 788 // CHECK1-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8
 789 // CHECK1-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [4 x ptr], align 8
 790 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 791 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 792 // CHECK1-NEXT:    store i64 [[N]], ptr [[N_ADDR]], align 8
 793 // CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
 794 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8
 795 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
 796 // CHECK1-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
 797 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
 798 // CHECK1-NEXT:    store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_2]], align 4
 799 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
 800 // CHECK1-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
 801 // CHECK1-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1
 802 // CHECK1-NEXT:    [[CONV:%.*]] = sext i32 [[DIV]] to i64
 803 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
 804 // CHECK1-NEXT:    [[SUB4:%.*]] = sub nsw i32 [[TMP4]], 0
 805 // CHECK1-NEXT:    [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1
 806 // CHECK1-NEXT:    [[CONV6:%.*]] = sext i32 [[DIV5]] to i64
 807 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]]
 808 // CHECK1-NEXT:    [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1
 809 // CHECK1-NEXT:    store i64 [[SUB7]], ptr [[DOTCAPTURE_EXPR_3]], align 8
 810 // CHECK1-NEXT:    store i32 0, ptr [[I]], align 4
 811 // CHECK1-NEXT:    store i32 0, ptr [[J]], align 4
 812 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
 813 // CHECK1-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP5]]
 814 // CHECK1-NEXT:    br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]]
 815 // CHECK1:       land.lhs.true:
 816 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
 817 // CHECK1-NEXT:    [[CMP8:%.*]] = icmp slt i32 0, [[TMP6]]
 818 // CHECK1-NEXT:    br i1 [[CMP8]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]]
 819 // CHECK1:       omp.precond.then:
 820 // CHECK1-NEXT:    store i64 0, ptr [[DOTOMP_COMB_LB]], align 8
 821 // CHECK1-NEXT:    [[TMP7:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_3]], align 8
 822 // CHECK1-NEXT:    store i64 [[TMP7]], ptr [[DOTOMP_COMB_UB]], align 8
 823 // CHECK1-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8
 824 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 825 // CHECK1-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
 826 // CHECK1-NEXT:    [[CONV11:%.*]] = zext i32 [[NVPTX_NUM_THREADS]] to i64
 827 // CHECK1-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 828 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
 829 // CHECK1-NEXT:    call void @__kmpc_distribute_static_init_8(ptr @[[GLOB2]], i32 [[TMP9]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 [[CONV11]])
 830 // CHECK1-NEXT:    [[TMP10:%.*]] = load i64, ptr [[DOTOMP_COMB_UB]], align 8
 831 // CHECK1-NEXT:    [[TMP11:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_3]], align 8
 832 // CHECK1-NEXT:    [[CMP12:%.*]] = icmp sgt i64 [[TMP10]], [[TMP11]]
 833 // CHECK1-NEXT:    br i1 [[CMP12]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 834 // CHECK1:       cond.true:
 835 // CHECK1-NEXT:    [[TMP12:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_3]], align 8
 836 // CHECK1-NEXT:    br label [[COND_END:%.*]]
 837 // CHECK1:       cond.false:
 838 // CHECK1-NEXT:    [[TMP13:%.*]] = load i64, ptr [[DOTOMP_COMB_UB]], align 8
 839 // CHECK1-NEXT:    br label [[COND_END]]
 840 // CHECK1:       cond.end:
 841 // CHECK1-NEXT:    [[COND:%.*]] = phi i64 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ]
 842 // CHECK1-NEXT:    store i64 [[COND]], ptr [[DOTOMP_COMB_UB]], align 8
 843 // CHECK1-NEXT:    [[TMP14:%.*]] = load i64, ptr [[DOTOMP_COMB_LB]], align 8
 844 // CHECK1-NEXT:    store i64 [[TMP14]], ptr [[DOTOMP_IV]], align 8
 845 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 846 // CHECK1:       omp.inner.for.cond:
 847 // CHECK1-NEXT:    [[TMP15:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
 848 // CHECK1-NEXT:    [[TMP16:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_3]], align 8
 849 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i64 [[TMP16]], 1
 850 // CHECK1-NEXT:    [[CMP13:%.*]] = icmp slt i64 [[TMP15]], [[ADD]]
 851 // CHECK1-NEXT:    br i1 [[CMP13]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 852 // CHECK1:       omp.inner.for.body:
 853 // CHECK1-NEXT:    [[TMP17:%.*]] = load i64, ptr [[DOTOMP_COMB_LB]], align 8
 854 // CHECK1-NEXT:    [[TMP18:%.*]] = load i64, ptr [[DOTOMP_COMB_UB]], align 8
 855 // CHECK1-NEXT:    [[TMP19:%.*]] = load i32, ptr [[N_ADDR]], align 4
 856 // CHECK1-NEXT:    store i32 [[TMP19]], ptr [[N_CASTED]], align 4
 857 // CHECK1-NEXT:    [[TMP20:%.*]] = load i64, ptr [[N_CASTED]], align 8
 858 // CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
 859 // CHECK1-NEXT:    [[TMP22:%.*]] = inttoptr i64 [[TMP17]] to ptr
 860 // CHECK1-NEXT:    store ptr [[TMP22]], ptr [[TMP21]], align 8
 861 // CHECK1-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
 862 // CHECK1-NEXT:    [[TMP24:%.*]] = inttoptr i64 [[TMP18]] to ptr
 863 // CHECK1-NEXT:    store ptr [[TMP24]], ptr [[TMP23]], align 8
 864 // CHECK1-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
 865 // CHECK1-NEXT:    [[TMP26:%.*]] = inttoptr i64 [[TMP20]] to ptr
 866 // CHECK1-NEXT:    store ptr [[TMP26]], ptr [[TMP25]], align 8
 867 // CHECK1-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3
 868 // CHECK1-NEXT:    store ptr [[TMP0]], ptr [[TMP27]], align 8
 869 // CHECK1-NEXT:    [[TMP28:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 870 // CHECK1-NEXT:    [[TMP29:%.*]] = load i32, ptr [[TMP28]], align 4
 871 // CHECK1-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP29]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l46_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 4)
 872 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 873 // CHECK1:       omp.inner.for.inc:
 874 // CHECK1-NEXT:    [[TMP30:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
 875 // CHECK1-NEXT:    [[TMP31:%.*]] = load i64, ptr [[DOTOMP_STRIDE]], align 8
 876 // CHECK1-NEXT:    [[ADD14:%.*]] = add nsw i64 [[TMP30]], [[TMP31]]
 877 // CHECK1-NEXT:    store i64 [[ADD14]], ptr [[DOTOMP_IV]], align 8
 878 // CHECK1-NEXT:    [[TMP32:%.*]] = load i64, ptr [[DOTOMP_COMB_LB]], align 8
 879 // CHECK1-NEXT:    [[TMP33:%.*]] = load i64, ptr [[DOTOMP_STRIDE]], align 8
 880 // CHECK1-NEXT:    [[ADD15:%.*]] = add nsw i64 [[TMP32]], [[TMP33]]
 881 // CHECK1-NEXT:    store i64 [[ADD15]], ptr [[DOTOMP_COMB_LB]], align 8
 882 // CHECK1-NEXT:    [[TMP34:%.*]] = load i64, ptr [[DOTOMP_COMB_UB]], align 8
 883 // CHECK1-NEXT:    [[TMP35:%.*]] = load i64, ptr [[DOTOMP_STRIDE]], align 8
 884 // CHECK1-NEXT:    [[ADD16:%.*]] = add nsw i64 [[TMP34]], [[TMP35]]
 885 // CHECK1-NEXT:    store i64 [[ADD16]], ptr [[DOTOMP_COMB_UB]], align 8
 886 // CHECK1-NEXT:    [[TMP36:%.*]] = load i64, ptr [[DOTOMP_COMB_UB]], align 8
 887 // CHECK1-NEXT:    [[TMP37:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_3]], align 8
 888 // CHECK1-NEXT:    [[CMP17:%.*]] = icmp sgt i64 [[TMP36]], [[TMP37]]
 889 // CHECK1-NEXT:    br i1 [[CMP17]], label [[COND_TRUE18:%.*]], label [[COND_FALSE19:%.*]]
 890 // CHECK1:       cond.true18:
 891 // CHECK1-NEXT:    [[TMP38:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_3]], align 8
 892 // CHECK1-NEXT:    br label [[COND_END20:%.*]]
 893 // CHECK1:       cond.false19:
 894 // CHECK1-NEXT:    [[TMP39:%.*]] = load i64, ptr [[DOTOMP_COMB_UB]], align 8
 895 // CHECK1-NEXT:    br label [[COND_END20]]
 896 // CHECK1:       cond.end20:
 897 // CHECK1-NEXT:    [[COND21:%.*]] = phi i64 [ [[TMP38]], [[COND_TRUE18]] ], [ [[TMP39]], [[COND_FALSE19]] ]
 898 // CHECK1-NEXT:    store i64 [[COND21]], ptr [[DOTOMP_COMB_UB]], align 8
 899 // CHECK1-NEXT:    [[TMP40:%.*]] = load i64, ptr [[DOTOMP_COMB_LB]], align 8
 900 // CHECK1-NEXT:    store i64 [[TMP40]], ptr [[DOTOMP_IV]], align 8
 901 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]
 902 // CHECK1:       omp.inner.for.end:
 903 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
 904 // CHECK1:       omp.loop.exit:
 905 // CHECK1-NEXT:    [[TMP41:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 906 // CHECK1-NEXT:    [[TMP42:%.*]] = load i32, ptr [[TMP41]], align 4
 907 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP42]])
 908 // CHECK1-NEXT:    br label [[OMP_PRECOND_END]]
 909 // CHECK1:       omp.precond.end:
 910 // CHECK1-NEXT:    ret void
 911 //
 912 //
 913 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l46_omp_outlined_omp_outlined
 914 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR1]] {
 915 // CHECK1-NEXT:  entry:
 916 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 917 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 918 // CHECK1-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
 919 // CHECK1-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
 920 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
 921 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
 922 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
 923 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 924 // CHECK1-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
 925 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
 926 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
 927 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8
 928 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
 929 // CHECK1-NEXT:    [[J:%.*]] = alloca i32, align 4
 930 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
 931 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
 932 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
 933 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 934 // CHECK1-NEXT:    [[I9:%.*]] = alloca i32, align 4
 935 // CHECK1-NEXT:    [[J10:%.*]] = alloca i32, align 4
 936 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 937 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 938 // CHECK1-NEXT:    store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
 939 // CHECK1-NEXT:    store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
 940 // CHECK1-NEXT:    store i64 [[N]], ptr [[N_ADDR]], align 8
 941 // CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
 942 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8
 943 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
 944 // CHECK1-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
 945 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
 946 // CHECK1-NEXT:    store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_2]], align 4
 947 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
 948 // CHECK1-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
 949 // CHECK1-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1
 950 // CHECK1-NEXT:    [[CONV:%.*]] = sext i32 [[DIV]] to i64
 951 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
 952 // CHECK1-NEXT:    [[SUB4:%.*]] = sub nsw i32 [[TMP4]], 0
 953 // CHECK1-NEXT:    [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1
 954 // CHECK1-NEXT:    [[CONV6:%.*]] = sext i32 [[DIV5]] to i64
 955 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]]
 956 // CHECK1-NEXT:    [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1
 957 // CHECK1-NEXT:    store i64 [[SUB7]], ptr [[DOTCAPTURE_EXPR_3]], align 8
 958 // CHECK1-NEXT:    store i32 0, ptr [[I]], align 4
 959 // CHECK1-NEXT:    store i32 0, ptr [[J]], align 4
 960 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
 961 // CHECK1-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP5]]
 962 // CHECK1-NEXT:    br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]]
 963 // CHECK1:       land.lhs.true:
 964 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
 965 // CHECK1-NEXT:    [[CMP8:%.*]] = icmp slt i32 0, [[TMP6]]
 966 // CHECK1-NEXT:    br i1 [[CMP8]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]]
 967 // CHECK1:       omp.precond.then:
 968 // CHECK1-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8
 969 // CHECK1-NEXT:    [[TMP7:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_3]], align 8
 970 // CHECK1-NEXT:    store i64 [[TMP7]], ptr [[DOTOMP_UB]], align 8
 971 // CHECK1-NEXT:    [[TMP8:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
 972 // CHECK1-NEXT:    [[TMP9:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
 973 // CHECK1-NEXT:    store i64 [[TMP8]], ptr [[DOTOMP_LB]], align 8
 974 // CHECK1-NEXT:    store i64 [[TMP9]], ptr [[DOTOMP_UB]], align 8
 975 // CHECK1-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8
 976 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 977 // CHECK1-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 978 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4
 979 // CHECK1-NEXT:    call void @__kmpc_for_static_init_8(ptr @[[GLOB3]], i32 [[TMP11]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
 980 // CHECK1-NEXT:    [[TMP12:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
 981 // CHECK1-NEXT:    store i64 [[TMP12]], ptr [[DOTOMP_IV]], align 8
 982 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 983 // CHECK1:       omp.inner.for.cond:
 984 // CHECK1-NEXT:    [[TMP13:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
 985 // CHECK1-NEXT:    [[TMP14:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
 986 // CHECK1-NEXT:    [[CMP11:%.*]] = icmp ule i64 [[TMP13]], [[TMP14]]
 987 // CHECK1-NEXT:    br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 988 // CHECK1:       omp.inner.for.body:
 989 // CHECK1-NEXT:    [[TMP15:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
 990 // CHECK1-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
 991 // CHECK1-NEXT:    [[SUB12:%.*]] = sub nsw i32 [[TMP16]], 0
 992 // CHECK1-NEXT:    [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1
 993 // CHECK1-NEXT:    [[MUL14:%.*]] = mul nsw i32 1, [[DIV13]]
 994 // CHECK1-NEXT:    [[CONV15:%.*]] = sext i32 [[MUL14]] to i64
 995 // CHECK1-NEXT:    [[DIV16:%.*]] = sdiv i64 [[TMP15]], [[CONV15]]
 996 // CHECK1-NEXT:    [[MUL17:%.*]] = mul nsw i64 [[DIV16]], 1
 997 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i64 0, [[MUL17]]
 998 // CHECK1-NEXT:    [[CONV18:%.*]] = trunc i64 [[ADD]] to i32
 999 // CHECK1-NEXT:    store i32 [[CONV18]], ptr [[I9]], align 4
1000 // CHECK1-NEXT:    [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
1001 // CHECK1-NEXT:    [[TMP18:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
1002 // CHECK1-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
1003 // CHECK1-NEXT:    [[SUB19:%.*]] = sub nsw i32 [[TMP19]], 0
1004 // CHECK1-NEXT:    [[DIV20:%.*]] = sdiv i32 [[SUB19]], 1
1005 // CHECK1-NEXT:    [[MUL21:%.*]] = mul nsw i32 1, [[DIV20]]
1006 // CHECK1-NEXT:    [[CONV22:%.*]] = sext i32 [[MUL21]] to i64
1007 // CHECK1-NEXT:    [[DIV23:%.*]] = sdiv i64 [[TMP18]], [[CONV22]]
1008 // CHECK1-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
1009 // CHECK1-NEXT:    [[SUB24:%.*]] = sub nsw i32 [[TMP20]], 0
1010 // CHECK1-NEXT:    [[DIV25:%.*]] = sdiv i32 [[SUB24]], 1
1011 // CHECK1-NEXT:    [[MUL26:%.*]] = mul nsw i32 1, [[DIV25]]
1012 // CHECK1-NEXT:    [[CONV27:%.*]] = sext i32 [[MUL26]] to i64
1013 // CHECK1-NEXT:    [[MUL28:%.*]] = mul nsw i64 [[DIV23]], [[CONV27]]
1014 // CHECK1-NEXT:    [[SUB29:%.*]] = sub nsw i64 [[TMP17]], [[MUL28]]
1015 // CHECK1-NEXT:    [[MUL30:%.*]] = mul nsw i64 [[SUB29]], 1
1016 // CHECK1-NEXT:    [[ADD31:%.*]] = add nsw i64 0, [[MUL30]]
1017 // CHECK1-NEXT:    [[CONV32:%.*]] = trunc i64 [[ADD31]] to i32
1018 // CHECK1-NEXT:    store i32 [[CONV32]], ptr [[J10]], align 4
1019 // CHECK1-NEXT:    [[TMP21:%.*]] = load i32, ptr [[I9]], align 4
1020 // CHECK1-NEXT:    [[TMP22:%.*]] = load i32, ptr [[J10]], align 4
1021 // CHECK1-NEXT:    [[ADD33:%.*]] = add nsw i32 [[TMP21]], [[TMP22]]
1022 // CHECK1-NEXT:    [[TMP23:%.*]] = load i32, ptr [[I9]], align 4
1023 // CHECK1-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64
1024 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP0]], i64 0, i64 [[IDXPROM]]
1025 // CHECK1-NEXT:    [[TMP24:%.*]] = load i32, ptr [[J10]], align 4
1026 // CHECK1-NEXT:    [[IDXPROM34:%.*]] = sext i32 [[TMP24]] to i64
1027 // CHECK1-NEXT:    [[ARRAYIDX35:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM34]]
1028 // CHECK1-NEXT:    store i32 [[ADD33]], ptr [[ARRAYIDX35]], align 4
1029 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1030 // CHECK1:       omp.body.continue:
1031 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1032 // CHECK1:       omp.inner.for.inc:
1033 // CHECK1-NEXT:    [[TMP25:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
1034 // CHECK1-NEXT:    [[TMP26:%.*]] = load i64, ptr [[DOTOMP_STRIDE]], align 8
1035 // CHECK1-NEXT:    [[ADD36:%.*]] = add nsw i64 [[TMP25]], [[TMP26]]
1036 // CHECK1-NEXT:    store i64 [[ADD36]], ptr [[DOTOMP_IV]], align 8
1037 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]
1038 // CHECK1:       omp.inner.for.end:
1039 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1040 // CHECK1:       omp.loop.exit:
1041 // CHECK1-NEXT:    [[TMP27:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1042 // CHECK1-NEXT:    [[TMP28:%.*]] = load i32, ptr [[TMP27]], align 4
1043 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP28]])
1044 // CHECK1-NEXT:    br label [[OMP_PRECOND_END]]
1045 // CHECK1:       omp.precond.end:
1046 // CHECK1-NEXT:    ret void
1047 //
1048 //
1049 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l53
1050 // CHECK1-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], ptr noundef [[V:%.*]]) #[[ATTR4]] {
1051 // CHECK1-NEXT:  entry:
1052 // CHECK1-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
1053 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
1054 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
1055 // CHECK1-NEXT:    [[V_ADDR:%.*]] = alloca ptr, align 8
1056 // CHECK1-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8
1057 // CHECK1-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
1058 // CHECK1-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
1059 // CHECK1-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
1060 // CHECK1-NEXT:    store i64 [[N]], ptr [[N_ADDR]], align 8
1061 // CHECK1-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
1062 // CHECK1-NEXT:    store ptr [[V]], ptr [[V_ADDR]], align 8
1063 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
1064 // CHECK1-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l53_kernel_environment, ptr [[DYN_PTR]])
1065 // CHECK1-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
1066 // CHECK1-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
1067 // CHECK1:       user_code.entry:
1068 // CHECK1-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
1069 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4
1070 // CHECK1-NEXT:    store i32 [[TMP3]], ptr [[N_CASTED]], align 4
1071 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8
1072 // CHECK1-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[V_ADDR]], align 8
1073 // CHECK1-NEXT:    store i32 0, ptr [[DOTZERO_ADDR]], align 4
1074 // CHECK1-NEXT:    store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4
1075 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l53_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i64 [[TMP4]], ptr [[TMP0]], ptr [[TMP5]]) #[[ATTR2]]
1076 // CHECK1-NEXT:    call void @__kmpc_target_deinit()
1077 // CHECK1-NEXT:    ret void
1078 // CHECK1:       worker.exit:
1079 // CHECK1-NEXT:    ret void
1080 //
1081 //
1082 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l53_omp_outlined
1083 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], ptr noundef [[V:%.*]]) #[[ATTR1]] {
1084 // CHECK1-NEXT:  entry:
1085 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1086 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1087 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
1088 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
1089 // CHECK1-NEXT:    [[V_ADDR:%.*]] = alloca ptr, align 8
1090 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1091 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1092 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
1093 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
1094 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
1095 // CHECK1-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
1096 // CHECK1-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
1097 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1098 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1099 // CHECK1-NEXT:    [[I3:%.*]] = alloca i32, align 4
1100 // CHECK1-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8
1101 // CHECK1-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [5 x ptr], align 8
1102 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1103 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1104 // CHECK1-NEXT:    store i64 [[N]], ptr [[N_ADDR]], align 8
1105 // CHECK1-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
1106 // CHECK1-NEXT:    store ptr [[V]], ptr [[V_ADDR]], align 8
1107 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
1108 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
1109 // CHECK1-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
1110 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1111 // CHECK1-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
1112 // CHECK1-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1
1113 // CHECK1-NEXT:    [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
1114 // CHECK1-NEXT:    store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
1115 // CHECK1-NEXT:    store i32 0, ptr [[I]], align 4
1116 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1117 // CHECK1-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]
1118 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
1119 // CHECK1:       omp.precond.then:
1120 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
1121 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
1122 // CHECK1-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_COMB_UB]], align 4
1123 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1124 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1125 // CHECK1-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
1126 // CHECK1-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1127 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
1128 // CHECK1-NEXT:    call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP6]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
1129 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1130 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
1131 // CHECK1-NEXT:    [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]]
1132 // CHECK1-NEXT:    br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1133 // CHECK1:       cond.true:
1134 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
1135 // CHECK1-NEXT:    br label [[COND_END:%.*]]
1136 // CHECK1:       cond.false:
1137 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1138 // CHECK1-NEXT:    br label [[COND_END]]
1139 // CHECK1:       cond.end:
1140 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
1141 // CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
1142 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
1143 // CHECK1-NEXT:    store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 4
1144 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1145 // CHECK1:       omp.inner.for.cond:
1146 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1147 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
1148 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP13]], 1
1149 // CHECK1-NEXT:    [[CMP5:%.*]] = icmp slt i32 [[TMP12]], [[ADD]]
1150 // CHECK1-NEXT:    br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1151 // CHECK1:       omp.inner.for.body:
1152 // CHECK1-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
1153 // CHECK1-NEXT:    [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
1154 // CHECK1-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1155 // CHECK1-NEXT:    [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
1156 // CHECK1-NEXT:    [[TMP18:%.*]] = load i32, ptr [[N_ADDR]], align 4
1157 // CHECK1-NEXT:    store i32 [[TMP18]], ptr [[N_CASTED]], align 4
1158 // CHECK1-NEXT:    [[TMP19:%.*]] = load i64, ptr [[N_CASTED]], align 8
1159 // CHECK1-NEXT:    [[TMP20:%.*]] = load ptr, ptr [[V_ADDR]], align 8
1160 // CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
1161 // CHECK1-NEXT:    [[TMP22:%.*]] = inttoptr i64 [[TMP15]] to ptr
1162 // CHECK1-NEXT:    store ptr [[TMP22]], ptr [[TMP21]], align 8
1163 // CHECK1-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
1164 // CHECK1-NEXT:    [[TMP24:%.*]] = inttoptr i64 [[TMP17]] to ptr
1165 // CHECK1-NEXT:    store ptr [[TMP24]], ptr [[TMP23]], align 8
1166 // CHECK1-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
1167 // CHECK1-NEXT:    [[TMP26:%.*]] = inttoptr i64 [[TMP19]] to ptr
1168 // CHECK1-NEXT:    store ptr [[TMP26]], ptr [[TMP25]], align 8
1169 // CHECK1-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3
1170 // CHECK1-NEXT:    store ptr [[TMP0]], ptr [[TMP27]], align 8
1171 // CHECK1-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 4
1172 // CHECK1-NEXT:    store ptr [[TMP20]], ptr [[TMP28]], align 8
1173 // CHECK1-NEXT:    [[TMP29:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1174 // CHECK1-NEXT:    [[TMP30:%.*]] = load i32, ptr [[TMP29]], align 4
1175 // CHECK1-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP30]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l53_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 5)
1176 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1177 // CHECK1:       omp.inner.for.inc:
1178 // CHECK1-NEXT:    [[TMP31:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1179 // CHECK1-NEXT:    [[TMP32:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
1180 // CHECK1-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP31]], [[TMP32]]
1181 // CHECK1-NEXT:    store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4
1182 // CHECK1-NEXT:    [[TMP33:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
1183 // CHECK1-NEXT:    [[TMP34:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
1184 // CHECK1-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP33]], [[TMP34]]
1185 // CHECK1-NEXT:    store i32 [[ADD7]], ptr [[DOTOMP_COMB_LB]], align 4
1186 // CHECK1-NEXT:    [[TMP35:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1187 // CHECK1-NEXT:    [[TMP36:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
1188 // CHECK1-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP35]], [[TMP36]]
1189 // CHECK1-NEXT:    store i32 [[ADD8]], ptr [[DOTOMP_COMB_UB]], align 4
1190 // CHECK1-NEXT:    [[TMP37:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1191 // CHECK1-NEXT:    [[TMP38:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
1192 // CHECK1-NEXT:    [[CMP9:%.*]] = icmp sgt i32 [[TMP37]], [[TMP38]]
1193 // CHECK1-NEXT:    br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]]
1194 // CHECK1:       cond.true10:
1195 // CHECK1-NEXT:    [[TMP39:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
1196 // CHECK1-NEXT:    br label [[COND_END12:%.*]]
1197 // CHECK1:       cond.false11:
1198 // CHECK1-NEXT:    [[TMP40:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1199 // CHECK1-NEXT:    br label [[COND_END12]]
1200 // CHECK1:       cond.end12:
1201 // CHECK1-NEXT:    [[COND13:%.*]] = phi i32 [ [[TMP39]], [[COND_TRUE10]] ], [ [[TMP40]], [[COND_FALSE11]] ]
1202 // CHECK1-NEXT:    store i32 [[COND13]], ptr [[DOTOMP_COMB_UB]], align 4
1203 // CHECK1-NEXT:    [[TMP41:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
1204 // CHECK1-NEXT:    store i32 [[TMP41]], ptr [[DOTOMP_IV]], align 4
1205 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]
1206 // CHECK1:       omp.inner.for.end:
1207 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1208 // CHECK1:       omp.loop.exit:
1209 // CHECK1-NEXT:    [[TMP42:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1210 // CHECK1-NEXT:    [[TMP43:%.*]] = load i32, ptr [[TMP42]], align 4
1211 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP43]])
1212 // CHECK1-NEXT:    br label [[OMP_PRECOND_END]]
1213 // CHECK1:       omp.precond.end:
1214 // CHECK1-NEXT:    ret void
1215 //
1216 //
1217 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l53_omp_outlined_omp_outlined
1218 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], ptr noundef [[V:%.*]]) #[[ATTR1]] {
1219 // CHECK1-NEXT:  entry:
1220 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1221 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1222 // CHECK1-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
1223 // CHECK1-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
1224 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
1225 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
1226 // CHECK1-NEXT:    [[V_ADDR:%.*]] = alloca ptr, align 8
1227 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1228 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1229 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
1230 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
1231 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
1232 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1233 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1234 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1235 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1236 // CHECK1-NEXT:    [[I4:%.*]] = alloca i32, align 4
1237 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1238 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1239 // CHECK1-NEXT:    store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
1240 // CHECK1-NEXT:    store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
1241 // CHECK1-NEXT:    store i64 [[N]], ptr [[N_ADDR]], align 8
1242 // CHECK1-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
1243 // CHECK1-NEXT:    store ptr [[V]], ptr [[V_ADDR]], align 8
1244 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
1245 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
1246 // CHECK1-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
1247 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1248 // CHECK1-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
1249 // CHECK1-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1
1250 // CHECK1-NEXT:    [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
1251 // CHECK1-NEXT:    store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
1252 // CHECK1-NEXT:    store i32 0, ptr [[I]], align 4
1253 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1254 // CHECK1-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]
1255 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
1256 // CHECK1:       omp.precond.then:
1257 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
1258 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
1259 // CHECK1-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4
1260 // CHECK1-NEXT:    [[TMP5:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
1261 // CHECK1-NEXT:    [[CONV:%.*]] = trunc i64 [[TMP5]] to i32
1262 // CHECK1-NEXT:    [[TMP6:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
1263 // CHECK1-NEXT:    [[CONV3:%.*]] = trunc i64 [[TMP6]] to i32
1264 // CHECK1-NEXT:    store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
1265 // CHECK1-NEXT:    store i32 [[CONV3]], ptr [[DOTOMP_UB]], align 4
1266 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1267 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1268 // CHECK1-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1269 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
1270 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP8]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
1271 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1272 // CHECK1-NEXT:    store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4
1273 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1274 // CHECK1:       omp.inner.for.cond:
1275 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1276 // CHECK1-NEXT:    [[CONV5:%.*]] = sext i32 [[TMP10]] to i64
1277 // CHECK1-NEXT:    [[TMP11:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
1278 // CHECK1-NEXT:    [[CMP6:%.*]] = icmp ule i64 [[CONV5]], [[TMP11]]
1279 // CHECK1-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1280 // CHECK1:       omp.inner.for.body:
1281 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1282 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
1283 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1284 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[I4]], align 4
1285 // CHECK1-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[V_ADDR]], align 8
1286 // CHECK1-NEXT:    [[TMP14:%.*]] = load i32, ptr [[I4]], align 4
1287 // CHECK1-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64
1288 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP13]], i64 [[IDXPROM]]
1289 // CHECK1-NEXT:    [[TMP15:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
1290 // CHECK1-NEXT:    [[TMP16:%.*]] = load i32, ptr [[I4]], align 4
1291 // CHECK1-NEXT:    [[IDXPROM7:%.*]] = sext i32 [[TMP16]] to i64
1292 // CHECK1-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM7]]
1293 // CHECK1-NEXT:    store i32 [[TMP15]], ptr [[ARRAYIDX8]], align 4
1294 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1295 // CHECK1:       omp.body.continue:
1296 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1297 // CHECK1:       omp.inner.for.inc:
1298 // CHECK1-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1299 // CHECK1-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
1300 // CHECK1-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP17]], [[TMP18]]
1301 // CHECK1-NEXT:    store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4
1302 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]
1303 // CHECK1:       omp.inner.for.end:
1304 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1305 // CHECK1:       omp.loop.exit:
1306 // CHECK1-NEXT:    [[TMP19:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1307 // CHECK1-NEXT:    [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4
1308 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP20]])
1309 // CHECK1-NEXT:    br label [[OMP_PRECOND_END]]
1310 // CHECK1:       omp.precond.end:
1311 // CHECK1-NEXT:    ret void
1312 //
1313 //
1314 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28
1315 // CHECK2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR0:[0-9]+]] {
1316 // CHECK2-NEXT:  entry:
1317 // CHECK2-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
1318 // CHECK2-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
1319 // CHECK2-NEXT:    [[AA_ADDR:%.*]] = alloca ptr, align 8
1320 // CHECK2-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8
1321 // CHECK2-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
1322 // CHECK2-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
1323 // CHECK2-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
1324 // CHECK2-NEXT:    store i64 [[N]], ptr [[N_ADDR]], align 8
1325 // CHECK2-NEXT:    store ptr [[AA]], ptr [[AA_ADDR]], align 8
1326 // CHECK2-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8
1327 // CHECK2-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28_kernel_environment, ptr [[DYN_PTR]])
1328 // CHECK2-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
1329 // CHECK2-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
1330 // CHECK2:       user_code.entry:
1331 // CHECK2-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
1332 // CHECK2-NEXT:    [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4
1333 // CHECK2-NEXT:    store i32 [[TMP3]], ptr [[N_CASTED]], align 4
1334 // CHECK2-NEXT:    [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8
1335 // CHECK2-NEXT:    store i32 0, ptr [[DOTZERO_ADDR]], align 4
1336 // CHECK2-NEXT:    store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4
1337 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i64 [[TMP4]], ptr [[TMP0]]) #[[ATTR2:[0-9]+]]
1338 // CHECK2-NEXT:    call void @__kmpc_target_deinit()
1339 // CHECK2-NEXT:    ret void
1340 // CHECK2:       worker.exit:
1341 // CHECK2-NEXT:    ret void
1342 //
1343 //
1344 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28_omp_outlined
1345 // CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR1:[0-9]+]] {
1346 // CHECK2-NEXT:  entry:
1347 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1348 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1349 // CHECK2-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
1350 // CHECK2-NEXT:    [[AA_ADDR:%.*]] = alloca ptr, align 8
1351 // CHECK2-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1352 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1353 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
1354 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
1355 // CHECK2-NEXT:    [[I:%.*]] = alloca i32, align 4
1356 // CHECK2-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
1357 // CHECK2-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
1358 // CHECK2-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1359 // CHECK2-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1360 // CHECK2-NEXT:    [[I3:%.*]] = alloca i32, align 4
1361 // CHECK2-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8
1362 // CHECK2-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [4 x ptr], align 8
1363 // CHECK2-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1364 // CHECK2-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1365 // CHECK2-NEXT:    store i64 [[N]], ptr [[N_ADDR]], align 8
1366 // CHECK2-NEXT:    store ptr [[AA]], ptr [[AA_ADDR]], align 8
1367 // CHECK2-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8
1368 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
1369 // CHECK2-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
1370 // CHECK2-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1371 // CHECK2-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
1372 // CHECK2-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1
1373 // CHECK2-NEXT:    [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
1374 // CHECK2-NEXT:    store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
1375 // CHECK2-NEXT:    store i32 0, ptr [[I]], align 4
1376 // CHECK2-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1377 // CHECK2-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]
1378 // CHECK2-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
1379 // CHECK2:       omp.precond.then:
1380 // CHECK2-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
1381 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
1382 // CHECK2-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_COMB_UB]], align 4
1383 // CHECK2-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1384 // CHECK2-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1385 // CHECK2-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
1386 // CHECK2-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1387 // CHECK2-NEXT:    [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
1388 // CHECK2-NEXT:    call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP6]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
1389 // CHECK2-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1390 // CHECK2-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
1391 // CHECK2-NEXT:    [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]]
1392 // CHECK2-NEXT:    br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1393 // CHECK2:       cond.true:
1394 // CHECK2-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
1395 // CHECK2-NEXT:    br label [[COND_END:%.*]]
1396 // CHECK2:       cond.false:
1397 // CHECK2-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1398 // CHECK2-NEXT:    br label [[COND_END]]
1399 // CHECK2:       cond.end:
1400 // CHECK2-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
1401 // CHECK2-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
1402 // CHECK2-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
1403 // CHECK2-NEXT:    store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 4
1404 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1405 // CHECK2:       omp.inner.for.cond:
1406 // CHECK2-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1407 // CHECK2-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
1408 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP13]], 1
1409 // CHECK2-NEXT:    [[CMP5:%.*]] = icmp slt i32 [[TMP12]], [[ADD]]
1410 // CHECK2-NEXT:    br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1411 // CHECK2:       omp.inner.for.body:
1412 // CHECK2-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
1413 // CHECK2-NEXT:    [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
1414 // CHECK2-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1415 // CHECK2-NEXT:    [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
1416 // CHECK2-NEXT:    [[TMP18:%.*]] = load i32, ptr [[N_ADDR]], align 4
1417 // CHECK2-NEXT:    store i32 [[TMP18]], ptr [[N_CASTED]], align 4
1418 // CHECK2-NEXT:    [[TMP19:%.*]] = load i64, ptr [[N_CASTED]], align 8
1419 // CHECK2-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
1420 // CHECK2-NEXT:    [[TMP21:%.*]] = inttoptr i64 [[TMP15]] to ptr
1421 // CHECK2-NEXT:    store ptr [[TMP21]], ptr [[TMP20]], align 8
1422 // CHECK2-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
1423 // CHECK2-NEXT:    [[TMP23:%.*]] = inttoptr i64 [[TMP17]] to ptr
1424 // CHECK2-NEXT:    store ptr [[TMP23]], ptr [[TMP22]], align 8
1425 // CHECK2-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
1426 // CHECK2-NEXT:    [[TMP25:%.*]] = inttoptr i64 [[TMP19]] to ptr
1427 // CHECK2-NEXT:    store ptr [[TMP25]], ptr [[TMP24]], align 8
1428 // CHECK2-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3
1429 // CHECK2-NEXT:    store ptr [[TMP0]], ptr [[TMP26]], align 8
1430 // CHECK2-NEXT:    [[TMP27:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1431 // CHECK2-NEXT:    [[TMP28:%.*]] = load i32, ptr [[TMP27]], align 4
1432 // CHECK2-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP28]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 4)
1433 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1434 // CHECK2:       omp.inner.for.inc:
1435 // CHECK2-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1436 // CHECK2-NEXT:    [[TMP30:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
1437 // CHECK2-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP29]], [[TMP30]]
1438 // CHECK2-NEXT:    store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4
1439 // CHECK2-NEXT:    [[TMP31:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
1440 // CHECK2-NEXT:    [[TMP32:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
1441 // CHECK2-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP31]], [[TMP32]]
1442 // CHECK2-NEXT:    store i32 [[ADD7]], ptr [[DOTOMP_COMB_LB]], align 4
1443 // CHECK2-NEXT:    [[TMP33:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1444 // CHECK2-NEXT:    [[TMP34:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
1445 // CHECK2-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP33]], [[TMP34]]
1446 // CHECK2-NEXT:    store i32 [[ADD8]], ptr [[DOTOMP_COMB_UB]], align 4
1447 // CHECK2-NEXT:    [[TMP35:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1448 // CHECK2-NEXT:    [[TMP36:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
1449 // CHECK2-NEXT:    [[CMP9:%.*]] = icmp sgt i32 [[TMP35]], [[TMP36]]
1450 // CHECK2-NEXT:    br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]]
1451 // CHECK2:       cond.true10:
1452 // CHECK2-NEXT:    [[TMP37:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
1453 // CHECK2-NEXT:    br label [[COND_END12:%.*]]
1454 // CHECK2:       cond.false11:
1455 // CHECK2-NEXT:    [[TMP38:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1456 // CHECK2-NEXT:    br label [[COND_END12]]
1457 // CHECK2:       cond.end12:
1458 // CHECK2-NEXT:    [[COND13:%.*]] = phi i32 [ [[TMP37]], [[COND_TRUE10]] ], [ [[TMP38]], [[COND_FALSE11]] ]
1459 // CHECK2-NEXT:    store i32 [[COND13]], ptr [[DOTOMP_COMB_UB]], align 4
1460 // CHECK2-NEXT:    [[TMP39:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
1461 // CHECK2-NEXT:    store i32 [[TMP39]], ptr [[DOTOMP_IV]], align 4
1462 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND]]
1463 // CHECK2:       omp.inner.for.end:
1464 // CHECK2-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1465 // CHECK2:       omp.loop.exit:
1466 // CHECK2-NEXT:    [[TMP40:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1467 // CHECK2-NEXT:    [[TMP41:%.*]] = load i32, ptr [[TMP40]], align 4
1468 // CHECK2-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB3:[0-9]+]], i32 [[TMP41]])
1469 // CHECK2-NEXT:    br label [[OMP_PRECOND_END]]
1470 // CHECK2:       omp.precond.end:
1471 // CHECK2-NEXT:    ret void
1472 //
1473 //
1474 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28_omp_outlined_omp_outlined
1475 // CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR1]] {
1476 // CHECK2-NEXT:  entry:
1477 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1478 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1479 // CHECK2-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
1480 // CHECK2-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
1481 // CHECK2-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
1482 // CHECK2-NEXT:    [[AA_ADDR:%.*]] = alloca ptr, align 8
1483 // CHECK2-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1484 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1485 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
1486 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
1487 // CHECK2-NEXT:    [[I:%.*]] = alloca i32, align 4
1488 // CHECK2-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1489 // CHECK2-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1490 // CHECK2-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1491 // CHECK2-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1492 // CHECK2-NEXT:    [[I4:%.*]] = alloca i32, align 4
1493 // CHECK2-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1494 // CHECK2-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1495 // CHECK2-NEXT:    store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
1496 // CHECK2-NEXT:    store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
1497 // CHECK2-NEXT:    store i64 [[N]], ptr [[N_ADDR]], align 8
1498 // CHECK2-NEXT:    store ptr [[AA]], ptr [[AA_ADDR]], align 8
1499 // CHECK2-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8
1500 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
1501 // CHECK2-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
1502 // CHECK2-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1503 // CHECK2-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
1504 // CHECK2-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1
1505 // CHECK2-NEXT:    [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
1506 // CHECK2-NEXT:    store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
1507 // CHECK2-NEXT:    store i32 0, ptr [[I]], align 4
1508 // CHECK2-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1509 // CHECK2-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]
1510 // CHECK2-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
1511 // CHECK2:       omp.precond.then:
1512 // CHECK2-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
1513 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
1514 // CHECK2-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4
1515 // CHECK2-NEXT:    [[TMP5:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
1516 // CHECK2-NEXT:    [[CONV:%.*]] = trunc i64 [[TMP5]] to i32
1517 // CHECK2-NEXT:    [[TMP6:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
1518 // CHECK2-NEXT:    [[CONV3:%.*]] = trunc i64 [[TMP6]] to i32
1519 // CHECK2-NEXT:    store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
1520 // CHECK2-NEXT:    store i32 [[CONV3]], ptr [[DOTOMP_UB]], align 4
1521 // CHECK2-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1522 // CHECK2-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1523 // CHECK2-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1524 // CHECK2-NEXT:    [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
1525 // CHECK2-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP8]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
1526 // CHECK2-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1527 // CHECK2-NEXT:    store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4
1528 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1529 // CHECK2:       omp.inner.for.cond:
1530 // CHECK2-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1531 // CHECK2-NEXT:    [[CONV5:%.*]] = sext i32 [[TMP10]] to i64
1532 // CHECK2-NEXT:    [[TMP11:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
1533 // CHECK2-NEXT:    [[CMP6:%.*]] = icmp ule i64 [[CONV5]], [[TMP11]]
1534 // CHECK2-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1535 // CHECK2:       omp.inner.for.body:
1536 // CHECK2-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1537 // CHECK2-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
1538 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1539 // CHECK2-NEXT:    store i32 [[ADD]], ptr [[I4]], align 4
1540 // CHECK2-NEXT:    [[TMP13:%.*]] = load i32, ptr [[I4]], align 4
1541 // CHECK2-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64
1542 // CHECK2-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], ptr [[TMP0]], i64 0, i64 [[IDXPROM]]
1543 // CHECK2-NEXT:    [[TMP14:%.*]] = load i16, ptr [[ARRAYIDX]], align 2
1544 // CHECK2-NEXT:    [[CONV7:%.*]] = sext i16 [[TMP14]] to i32
1545 // CHECK2-NEXT:    [[ADD8:%.*]] = add nsw i32 [[CONV7]], 1
1546 // CHECK2-NEXT:    [[CONV9:%.*]] = trunc i32 [[ADD8]] to i16
1547 // CHECK2-NEXT:    store i16 [[CONV9]], ptr [[ARRAYIDX]], align 2
1548 // CHECK2-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1549 // CHECK2:       omp.body.continue:
1550 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1551 // CHECK2:       omp.inner.for.inc:
1552 // CHECK2-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1553 // CHECK2-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
1554 // CHECK2-NEXT:    [[ADD10:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
1555 // CHECK2-NEXT:    store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4
1556 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND]]
1557 // CHECK2:       omp.inner.for.end:
1558 // CHECK2-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1559 // CHECK2:       omp.loop.exit:
1560 // CHECK2-NEXT:    [[TMP17:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1561 // CHECK2-NEXT:    [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 4
1562 // CHECK2-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP18]])
1563 // CHECK2-NEXT:    br label [[OMP_PRECOND_END]]
1564 // CHECK2:       omp.precond.end:
1565 // CHECK2-NEXT:    ret void
1566 //
1567 //
1568 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l33
1569 // CHECK2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR4:[0-9]+]] {
1570 // CHECK2-NEXT:  entry:
1571 // CHECK2-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
1572 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
1573 // CHECK2-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
1574 // CHECK2-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
1575 // CHECK2-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
1576 // CHECK2-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
1577 // CHECK2-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
1578 // CHECK2-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l33_kernel_environment, ptr [[DYN_PTR]])
1579 // CHECK2-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
1580 // CHECK2-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
1581 // CHECK2:       user_code.entry:
1582 // CHECK2-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
1583 // CHECK2-NEXT:    store i32 0, ptr [[DOTZERO_ADDR]], align 4
1584 // CHECK2-NEXT:    store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4
1585 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l33_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]]) #[[ATTR2]]
1586 // CHECK2-NEXT:    call void @__kmpc_target_deinit()
1587 // CHECK2-NEXT:    ret void
1588 // CHECK2:       worker.exit:
1589 // CHECK2-NEXT:    ret void
1590 //
1591 //
1592 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l33_omp_outlined
1593 // CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
1594 // CHECK2-NEXT:  entry:
1595 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1596 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1597 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
1598 // CHECK2-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1599 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1600 // CHECK2-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
1601 // CHECK2-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
1602 // CHECK2-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1603 // CHECK2-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1604 // CHECK2-NEXT:    [[I:%.*]] = alloca i32, align 4
1605 // CHECK2-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x ptr], align 8
1606 // CHECK2-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1607 // CHECK2-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1608 // CHECK2-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
1609 // CHECK2-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
1610 // CHECK2-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
1611 // CHECK2-NEXT:    store i32 9, ptr [[DOTOMP_COMB_UB]], align 4
1612 // CHECK2-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1613 // CHECK2-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1614 // CHECK2-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
1615 // CHECK2-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1616 // CHECK2-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
1617 // CHECK2-NEXT:    call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP2]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
1618 // CHECK2-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1619 // CHECK2-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
1620 // CHECK2-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1621 // CHECK2:       cond.true:
1622 // CHECK2-NEXT:    br label [[COND_END:%.*]]
1623 // CHECK2:       cond.false:
1624 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1625 // CHECK2-NEXT:    br label [[COND_END]]
1626 // CHECK2:       cond.end:
1627 // CHECK2-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
1628 // CHECK2-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
1629 // CHECK2-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
1630 // CHECK2-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
1631 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1632 // CHECK2:       omp.inner.for.cond:
1633 // CHECK2-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1634 // CHECK2-NEXT:    [[CMP1:%.*]] = icmp slt i32 [[TMP6]], 10
1635 // CHECK2-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1636 // CHECK2:       omp.inner.for.body:
1637 // CHECK2-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
1638 // CHECK2-NEXT:    [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
1639 // CHECK2-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1640 // CHECK2-NEXT:    [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
1641 // CHECK2-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
1642 // CHECK2-NEXT:    [[TMP12:%.*]] = inttoptr i64 [[TMP8]] to ptr
1643 // CHECK2-NEXT:    store ptr [[TMP12]], ptr [[TMP11]], align 8
1644 // CHECK2-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
1645 // CHECK2-NEXT:    [[TMP14:%.*]] = inttoptr i64 [[TMP10]] to ptr
1646 // CHECK2-NEXT:    store ptr [[TMP14]], ptr [[TMP13]], align 8
1647 // CHECK2-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
1648 // CHECK2-NEXT:    store ptr [[TMP0]], ptr [[TMP15]], align 8
1649 // CHECK2-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l33_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 3)
1650 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1651 // CHECK2:       omp.inner.for.inc:
1652 // CHECK2-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1653 // CHECK2-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
1654 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
1655 // CHECK2-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
1656 // CHECK2-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
1657 // CHECK2-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
1658 // CHECK2-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
1659 // CHECK2-NEXT:    store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4
1660 // CHECK2-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1661 // CHECK2-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
1662 // CHECK2-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]
1663 // CHECK2-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4
1664 // CHECK2-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1665 // CHECK2-NEXT:    [[CMP4:%.*]] = icmp sgt i32 [[TMP22]], 9
1666 // CHECK2-NEXT:    br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
1667 // CHECK2:       cond.true5:
1668 // CHECK2-NEXT:    br label [[COND_END7:%.*]]
1669 // CHECK2:       cond.false6:
1670 // CHECK2-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1671 // CHECK2-NEXT:    br label [[COND_END7]]
1672 // CHECK2:       cond.end7:
1673 // CHECK2-NEXT:    [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP23]], [[COND_FALSE6]] ]
1674 // CHECK2-NEXT:    store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4
1675 // CHECK2-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
1676 // CHECK2-NEXT:    store i32 [[TMP24]], ptr [[DOTOMP_IV]], align 4
1677 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND]]
1678 // CHECK2:       omp.inner.for.end:
1679 // CHECK2-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1680 // CHECK2:       omp.loop.exit:
1681 // CHECK2-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP2]])
1682 // CHECK2-NEXT:    ret void
1683 //
1684 //
1685 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l33_omp_outlined_omp_outlined
1686 // CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
1687 // CHECK2-NEXT:  entry:
1688 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1689 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1690 // CHECK2-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
1691 // CHECK2-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
1692 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
1693 // CHECK2-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1694 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1695 // CHECK2-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1696 // CHECK2-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1697 // CHECK2-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1698 // CHECK2-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1699 // CHECK2-NEXT:    [[I:%.*]] = alloca i32, align 4
1700 // CHECK2-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1701 // CHECK2-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1702 // CHECK2-NEXT:    store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
1703 // CHECK2-NEXT:    store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
1704 // CHECK2-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
1705 // CHECK2-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
1706 // CHECK2-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
1707 // CHECK2-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4
1708 // CHECK2-NEXT:    [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
1709 // CHECK2-NEXT:    [[CONV:%.*]] = trunc i64 [[TMP1]] to i32
1710 // CHECK2-NEXT:    [[TMP2:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
1711 // CHECK2-NEXT:    [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32
1712 // CHECK2-NEXT:    store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
1713 // CHECK2-NEXT:    store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4
1714 // CHECK2-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1715 // CHECK2-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1716 // CHECK2-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1717 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
1718 // CHECK2-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP4]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
1719 // CHECK2-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1720 // CHECK2-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
1721 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1722 // CHECK2:       omp.inner.for.cond:
1723 // CHECK2-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1724 // CHECK2-NEXT:    [[CONV2:%.*]] = sext i32 [[TMP6]] to i64
1725 // CHECK2-NEXT:    [[TMP7:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
1726 // CHECK2-NEXT:    [[CMP:%.*]] = icmp ule i64 [[CONV2]], [[TMP7]]
1727 // CHECK2-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1728 // CHECK2:       omp.inner.for.body:
1729 // CHECK2-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1730 // CHECK2-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
1731 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1732 // CHECK2-NEXT:    store i32 [[ADD]], ptr [[I]], align 4
1733 // CHECK2-NEXT:    [[TMP9:%.*]] = load i32, ptr [[I]], align 4
1734 // CHECK2-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64
1735 // CHECK2-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]]
1736 // CHECK2-NEXT:    [[TMP10:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
1737 // CHECK2-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
1738 // CHECK2-NEXT:    store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4
1739 // CHECK2-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1740 // CHECK2:       omp.body.continue:
1741 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1742 // CHECK2:       omp.inner.for.inc:
1743 // CHECK2-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1744 // CHECK2-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
1745 // CHECK2-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
1746 // CHECK2-NEXT:    store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4
1747 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND]]
1748 // CHECK2:       omp.inner.for.end:
1749 // CHECK2-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1750 // CHECK2:       omp.loop.exit:
1751 // CHECK2-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP4]])
1752 // CHECK2-NEXT:    ret void
1753 //
1754 //
1755 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l38
1756 // CHECK2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i64 noundef [[F:%.*]]) #[[ATTR4]] {
1757 // CHECK2-NEXT:  entry:
1758 // CHECK2-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
1759 // CHECK2-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
1760 // CHECK2-NEXT:    [[F_ADDR:%.*]] = alloca i64, align 8
1761 // CHECK2-NEXT:    [[F_CASTED:%.*]] = alloca i64, align 8
1762 // CHECK2-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
1763 // CHECK2-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
1764 // CHECK2-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
1765 // CHECK2-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
1766 // CHECK2-NEXT:    store i64 [[F]], ptr [[F_ADDR]], align 8
1767 // CHECK2-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8
1768 // CHECK2-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l38_kernel_environment, ptr [[DYN_PTR]])
1769 // CHECK2-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
1770 // CHECK2-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
1771 // CHECK2:       user_code.entry:
1772 // CHECK2-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
1773 // CHECK2-NEXT:    [[TMP3:%.*]] = load i32, ptr [[F_ADDR]], align 4
1774 // CHECK2-NEXT:    store i32 [[TMP3]], ptr [[F_CASTED]], align 4
1775 // CHECK2-NEXT:    [[TMP4:%.*]] = load i64, ptr [[F_CASTED]], align 8
1776 // CHECK2-NEXT:    store i32 0, ptr [[DOTZERO_ADDR]], align 4
1777 // CHECK2-NEXT:    store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4
1778 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l38_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]], i64 [[TMP4]]) #[[ATTR2]]
1779 // CHECK2-NEXT:    call void @__kmpc_target_deinit()
1780 // CHECK2-NEXT:    ret void
1781 // CHECK2:       worker.exit:
1782 // CHECK2-NEXT:    ret void
1783 //
1784 //
1785 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l38_omp_outlined
1786 // CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i64 noundef [[F:%.*]]) #[[ATTR1]] {
1787 // CHECK2-NEXT:  entry:
1788 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1789 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1790 // CHECK2-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
1791 // CHECK2-NEXT:    [[F_ADDR:%.*]] = alloca i64, align 8
1792 // CHECK2-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1793 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1794 // CHECK2-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
1795 // CHECK2-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
1796 // CHECK2-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
1797 // CHECK2-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1798 // CHECK2-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1799 // CHECK2-NEXT:    [[K:%.*]] = alloca i32, align 4
1800 // CHECK2-NEXT:    [[I:%.*]] = alloca i32, align 4
1801 // CHECK2-NEXT:    [[J:%.*]] = alloca i32, align 4
1802 // CHECK2-NEXT:    [[F_CASTED:%.*]] = alloca i64, align 8
1803 // CHECK2-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [4 x ptr], align 8
1804 // CHECK2-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1805 // CHECK2-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1806 // CHECK2-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
1807 // CHECK2-NEXT:    store i64 [[F]], ptr [[F_ADDR]], align 8
1808 // CHECK2-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8
1809 // CHECK2-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
1810 // CHECK2-NEXT:    store i32 99, ptr [[DOTOMP_COMB_UB]], align 4
1811 // CHECK2-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1812 // CHECK2-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1813 // CHECK2-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
1814 // CHECK2-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1815 // CHECK2-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
1816 // CHECK2-NEXT:    call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP2]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
1817 // CHECK2-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1818 // CHECK2-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 99
1819 // CHECK2-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1820 // CHECK2:       cond.true:
1821 // CHECK2-NEXT:    br label [[COND_END:%.*]]
1822 // CHECK2:       cond.false:
1823 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1824 // CHECK2-NEXT:    br label [[COND_END]]
1825 // CHECK2:       cond.end:
1826 // CHECK2-NEXT:    [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
1827 // CHECK2-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
1828 // CHECK2-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
1829 // CHECK2-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
1830 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1831 // CHECK2:       omp.inner.for.cond:
1832 // CHECK2-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1833 // CHECK2-NEXT:    [[CMP2:%.*]] = icmp slt i32 [[TMP6]], 100
1834 // CHECK2-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1835 // CHECK2:       omp.inner.for.body:
1836 // CHECK2-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
1837 // CHECK2-NEXT:    [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
1838 // CHECK2-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1839 // CHECK2-NEXT:    [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
1840 // CHECK2-NEXT:    [[TMP11:%.*]] = load i32, ptr [[F_ADDR]], align 4
1841 // CHECK2-NEXT:    store i32 [[TMP11]], ptr [[F_CASTED]], align 4
1842 // CHECK2-NEXT:    [[TMP12:%.*]] = load i64, ptr [[F_CASTED]], align 8
1843 // CHECK2-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
1844 // CHECK2-NEXT:    [[TMP14:%.*]] = inttoptr i64 [[TMP8]] to ptr
1845 // CHECK2-NEXT:    store ptr [[TMP14]], ptr [[TMP13]], align 8
1846 // CHECK2-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
1847 // CHECK2-NEXT:    [[TMP16:%.*]] = inttoptr i64 [[TMP10]] to ptr
1848 // CHECK2-NEXT:    store ptr [[TMP16]], ptr [[TMP15]], align 8
1849 // CHECK2-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
1850 // CHECK2-NEXT:    store ptr [[TMP0]], ptr [[TMP17]], align 8
1851 // CHECK2-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3
1852 // CHECK2-NEXT:    [[TMP19:%.*]] = inttoptr i64 [[TMP12]] to ptr
1853 // CHECK2-NEXT:    store ptr [[TMP19]], ptr [[TMP18]], align 8
1854 // CHECK2-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l38_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 4)
1855 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1856 // CHECK2:       omp.inner.for.inc:
1857 // CHECK2-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1858 // CHECK2-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
1859 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]
1860 // CHECK2-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
1861 // CHECK2-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
1862 // CHECK2-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
1863 // CHECK2-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]
1864 // CHECK2-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_COMB_LB]], align 4
1865 // CHECK2-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1866 // CHECK2-NEXT:    [[TMP25:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
1867 // CHECK2-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP24]], [[TMP25]]
1868 // CHECK2-NEXT:    store i32 [[ADD4]], ptr [[DOTOMP_COMB_UB]], align 4
1869 // CHECK2-NEXT:    [[TMP26:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1870 // CHECK2-NEXT:    [[CMP5:%.*]] = icmp sgt i32 [[TMP26]], 99
1871 // CHECK2-NEXT:    br i1 [[CMP5]], label [[COND_TRUE6:%.*]], label [[COND_FALSE7:%.*]]
1872 // CHECK2:       cond.true6:
1873 // CHECK2-NEXT:    br label [[COND_END8:%.*]]
1874 // CHECK2:       cond.false7:
1875 // CHECK2-NEXT:    [[TMP27:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1876 // CHECK2-NEXT:    br label [[COND_END8]]
1877 // CHECK2:       cond.end8:
1878 // CHECK2-NEXT:    [[COND9:%.*]] = phi i32 [ 99, [[COND_TRUE6]] ], [ [[TMP27]], [[COND_FALSE7]] ]
1879 // CHECK2-NEXT:    store i32 [[COND9]], ptr [[DOTOMP_COMB_UB]], align 4
1880 // CHECK2-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
1881 // CHECK2-NEXT:    store i32 [[TMP28]], ptr [[DOTOMP_IV]], align 4
1882 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND]]
1883 // CHECK2:       omp.inner.for.end:
1884 // CHECK2-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1885 // CHECK2:       omp.loop.exit:
1886 // CHECK2-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP2]])
1887 // CHECK2-NEXT:    ret void
1888 //
1889 //
1890 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l38_omp_outlined_omp_outlined
1891 // CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i64 noundef [[F:%.*]]) #[[ATTR1]] {
1892 // CHECK2-NEXT:  entry:
1893 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1894 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1895 // CHECK2-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
1896 // CHECK2-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
1897 // CHECK2-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
1898 // CHECK2-NEXT:    [[F_ADDR:%.*]] = alloca i64, align 8
1899 // CHECK2-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1900 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1901 // CHECK2-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
1902 // CHECK2-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1903 // CHECK2-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1904 // CHECK2-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1905 // CHECK2-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1906 // CHECK2-NEXT:    [[K:%.*]] = alloca i32, align 4
1907 // CHECK2-NEXT:    [[I:%.*]] = alloca i32, align 4
1908 // CHECK2-NEXT:    [[J:%.*]] = alloca i32, align 4
1909 // CHECK2-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1910 // CHECK2-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1911 // CHECK2-NEXT:    store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
1912 // CHECK2-NEXT:    store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
1913 // CHECK2-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
1914 // CHECK2-NEXT:    store i64 [[F]], ptr [[F_ADDR]], align 8
1915 // CHECK2-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8
1916 // CHECK2-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
1917 // CHECK2-NEXT:    store i32 99, ptr [[DOTOMP_UB]], align 4
1918 // CHECK2-NEXT:    [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
1919 // CHECK2-NEXT:    [[CONV:%.*]] = trunc i64 [[TMP1]] to i32
1920 // CHECK2-NEXT:    [[TMP2:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
1921 // CHECK2-NEXT:    [[CONV2:%.*]] = trunc i64 [[TMP2]] to i32
1922 // CHECK2-NEXT:    store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
1923 // CHECK2-NEXT:    store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4
1924 // CHECK2-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1925 // CHECK2-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1926 // CHECK2-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1927 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
1928 // CHECK2-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP4]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
1929 // CHECK2-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1930 // CHECK2-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
1931 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1932 // CHECK2:       omp.inner.for.cond:
1933 // CHECK2-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1934 // CHECK2-NEXT:    [[CONV3:%.*]] = sext i32 [[TMP6]] to i64
1935 // CHECK2-NEXT:    [[TMP7:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
1936 // CHECK2-NEXT:    [[CMP:%.*]] = icmp ule i64 [[CONV3]], [[TMP7]]
1937 // CHECK2-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1938 // CHECK2:       omp.inner.for.body:
1939 // CHECK2-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1940 // CHECK2-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP8]], 10
1941 // CHECK2-NEXT:    [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
1942 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1943 // CHECK2-NEXT:    store i32 [[ADD]], ptr [[I]], align 4
1944 // CHECK2-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1945 // CHECK2-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1946 // CHECK2-NEXT:    [[DIV4:%.*]] = sdiv i32 [[TMP10]], 10
1947 // CHECK2-NEXT:    [[MUL5:%.*]] = mul nsw i32 [[DIV4]], 10
1948 // CHECK2-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL5]]
1949 // CHECK2-NEXT:    [[MUL6:%.*]] = mul nsw i32 [[SUB]], 1
1950 // CHECK2-NEXT:    [[ADD7:%.*]] = add nsw i32 0, [[MUL6]]
1951 // CHECK2-NEXT:    store i32 [[ADD7]], ptr [[J]], align 4
1952 // CHECK2-NEXT:    store i32 10, ptr [[K]], align 4
1953 // CHECK2-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 4
1954 // CHECK2-NEXT:    [[TMP12:%.*]] = load i32, ptr [[J]], align 4
1955 // CHECK2-NEXT:    [[TMP13:%.*]] = load i32, ptr [[F_ADDR]], align 4
1956 // CHECK2-NEXT:    [[MUL8:%.*]] = mul nsw i32 [[TMP12]], [[TMP13]]
1957 // CHECK2-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP11]], [[MUL8]]
1958 // CHECK2-NEXT:    [[TMP14:%.*]] = load i32, ptr [[K]], align 4
1959 // CHECK2-NEXT:    [[ADD10:%.*]] = add nsw i32 [[ADD9]], [[TMP14]]
1960 // CHECK2-NEXT:    [[TMP15:%.*]] = load i32, ptr [[I]], align 4
1961 // CHECK2-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64
1962 // CHECK2-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP0]], i64 0, i64 [[IDXPROM]]
1963 // CHECK2-NEXT:    [[TMP16:%.*]] = load i32, ptr [[J]], align 4
1964 // CHECK2-NEXT:    [[IDXPROM11:%.*]] = sext i32 [[TMP16]] to i64
1965 // CHECK2-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM11]]
1966 // CHECK2-NEXT:    store i32 [[ADD10]], ptr [[ARRAYIDX12]], align 4
1967 // CHECK2-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1968 // CHECK2:       omp.body.continue:
1969 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1970 // CHECK2:       omp.inner.for.inc:
1971 // CHECK2-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1972 // CHECK2-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
1973 // CHECK2-NEXT:    [[ADD13:%.*]] = add nsw i32 [[TMP17]], [[TMP18]]
1974 // CHECK2-NEXT:    store i32 [[ADD13]], ptr [[DOTOMP_IV]], align 4
1975 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND]]
1976 // CHECK2:       omp.inner.for.end:
1977 // CHECK2-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1978 // CHECK2:       omp.loop.exit:
1979 // CHECK2-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP4]])
1980 // CHECK2-NEXT:    ret void
1981 //
1982 //
1983 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l46
1984 // CHECK2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR4]] {
1985 // CHECK2-NEXT:  entry:
1986 // CHECK2-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
1987 // CHECK2-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
1988 // CHECK2-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
1989 // CHECK2-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8
1990 // CHECK2-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
1991 // CHECK2-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
1992 // CHECK2-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
1993 // CHECK2-NEXT:    store i64 [[N]], ptr [[N_ADDR]], align 8
1994 // CHECK2-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
1995 // CHECK2-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8
1996 // CHECK2-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l46_kernel_environment, ptr [[DYN_PTR]])
1997 // CHECK2-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
1998 // CHECK2-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
1999 // CHECK2:       user_code.entry:
2000 // CHECK2-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
2001 // CHECK2-NEXT:    [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4
2002 // CHECK2-NEXT:    store i32 [[TMP3]], ptr [[N_CASTED]], align 4
2003 // CHECK2-NEXT:    [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8
2004 // CHECK2-NEXT:    store i32 0, ptr [[DOTZERO_ADDR]], align 4
2005 // CHECK2-NEXT:    store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4
2006 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l46_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i64 [[TMP4]], ptr [[TMP0]]) #[[ATTR2]]
2007 // CHECK2-NEXT:    call void @__kmpc_target_deinit()
2008 // CHECK2-NEXT:    ret void
2009 // CHECK2:       worker.exit:
2010 // CHECK2-NEXT:    ret void
2011 //
2012 //
2013 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l46_omp_outlined
2014 // CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR1]] {
2015 // CHECK2-NEXT:  entry:
2016 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
2017 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
2018 // CHECK2-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
2019 // CHECK2-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
2020 // CHECK2-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2021 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2022 // CHECK2-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
2023 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
2024 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
2025 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4
2026 // CHECK2-NEXT:    [[I:%.*]] = alloca i32, align 4
2027 // CHECK2-NEXT:    [[J:%.*]] = alloca i32, align 4
2028 // CHECK2-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
2029 // CHECK2-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
2030 // CHECK2-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2031 // CHECK2-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2032 // CHECK2-NEXT:    [[I8:%.*]] = alloca i32, align 4
2033 // CHECK2-NEXT:    [[J9:%.*]] = alloca i32, align 4
2034 // CHECK2-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8
2035 // CHECK2-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [4 x ptr], align 8
2036 // CHECK2-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
2037 // CHECK2-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
2038 // CHECK2-NEXT:    store i64 [[N]], ptr [[N_ADDR]], align 8
2039 // CHECK2-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
2040 // CHECK2-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8
2041 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
2042 // CHECK2-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
2043 // CHECK2-NEXT:    [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
2044 // CHECK2-NEXT:    store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_2]], align 4
2045 // CHECK2-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
2046 // CHECK2-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
2047 // CHECK2-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1
2048 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
2049 // CHECK2-NEXT:    [[SUB4:%.*]] = sub nsw i32 [[TMP4]], 0
2050 // CHECK2-NEXT:    [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1
2051 // CHECK2-NEXT:    [[MUL:%.*]] = mul nsw i32 [[DIV]], [[DIV5]]
2052 // CHECK2-NEXT:    [[SUB6:%.*]] = sub nsw i32 [[MUL]], 1
2053 // CHECK2-NEXT:    store i32 [[SUB6]], ptr [[DOTCAPTURE_EXPR_3]], align 4
2054 // CHECK2-NEXT:    store i32 0, ptr [[I]], align 4
2055 // CHECK2-NEXT:    store i32 0, ptr [[J]], align 4
2056 // CHECK2-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
2057 // CHECK2-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP5]]
2058 // CHECK2-NEXT:    br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]]
2059 // CHECK2:       land.lhs.true:
2060 // CHECK2-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
2061 // CHECK2-NEXT:    [[CMP7:%.*]] = icmp slt i32 0, [[TMP6]]
2062 // CHECK2-NEXT:    br i1 [[CMP7]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]]
2063 // CHECK2:       omp.precond.then:
2064 // CHECK2-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
2065 // CHECK2-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4
2066 // CHECK2-NEXT:    store i32 [[TMP7]], ptr [[DOTOMP_COMB_UB]], align 4
2067 // CHECK2-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
2068 // CHECK2-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2069 // CHECK2-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
2070 // CHECK2-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
2071 // CHECK2-NEXT:    [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
2072 // CHECK2-NEXT:    call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP9]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
2073 // CHECK2-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2074 // CHECK2-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4
2075 // CHECK2-NEXT:    [[CMP10:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]]
2076 // CHECK2-NEXT:    br i1 [[CMP10]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2077 // CHECK2:       cond.true:
2078 // CHECK2-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4
2079 // CHECK2-NEXT:    br label [[COND_END:%.*]]
2080 // CHECK2:       cond.false:
2081 // CHECK2-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2082 // CHECK2-NEXT:    br label [[COND_END]]
2083 // CHECK2:       cond.end:
2084 // CHECK2-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ]
2085 // CHECK2-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
2086 // CHECK2-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
2087 // CHECK2-NEXT:    store i32 [[TMP14]], ptr [[DOTOMP_IV]], align 4
2088 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2089 // CHECK2:       omp.inner.for.cond:
2090 // CHECK2-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2091 // CHECK2-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4
2092 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP16]], 1
2093 // CHECK2-NEXT:    [[CMP11:%.*]] = icmp slt i32 [[TMP15]], [[ADD]]
2094 // CHECK2-NEXT:    br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2095 // CHECK2:       omp.inner.for.body:
2096 // CHECK2-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
2097 // CHECK2-NEXT:    [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
2098 // CHECK2-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2099 // CHECK2-NEXT:    [[TMP20:%.*]] = zext i32 [[TMP19]] to i64
2100 // CHECK2-NEXT:    [[TMP21:%.*]] = load i32, ptr [[N_ADDR]], align 4
2101 // CHECK2-NEXT:    store i32 [[TMP21]], ptr [[N_CASTED]], align 4
2102 // CHECK2-NEXT:    [[TMP22:%.*]] = load i64, ptr [[N_CASTED]], align 8
2103 // CHECK2-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
2104 // CHECK2-NEXT:    [[TMP24:%.*]] = inttoptr i64 [[TMP18]] to ptr
2105 // CHECK2-NEXT:    store ptr [[TMP24]], ptr [[TMP23]], align 8
2106 // CHECK2-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
2107 // CHECK2-NEXT:    [[TMP26:%.*]] = inttoptr i64 [[TMP20]] to ptr
2108 // CHECK2-NEXT:    store ptr [[TMP26]], ptr [[TMP25]], align 8
2109 // CHECK2-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
2110 // CHECK2-NEXT:    [[TMP28:%.*]] = inttoptr i64 [[TMP22]] to ptr
2111 // CHECK2-NEXT:    store ptr [[TMP28]], ptr [[TMP27]], align 8
2112 // CHECK2-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3
2113 // CHECK2-NEXT:    store ptr [[TMP0]], ptr [[TMP29]], align 8
2114 // CHECK2-NEXT:    [[TMP30:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
2115 // CHECK2-NEXT:    [[TMP31:%.*]] = load i32, ptr [[TMP30]], align 4
2116 // CHECK2-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP31]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l46_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 4)
2117 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2118 // CHECK2:       omp.inner.for.inc:
2119 // CHECK2-NEXT:    [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2120 // CHECK2-NEXT:    [[TMP33:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
2121 // CHECK2-NEXT:    [[ADD12:%.*]] = add nsw i32 [[TMP32]], [[TMP33]]
2122 // CHECK2-NEXT:    store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4
2123 // CHECK2-NEXT:    [[TMP34:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
2124 // CHECK2-NEXT:    [[TMP35:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
2125 // CHECK2-NEXT:    [[ADD13:%.*]] = add nsw i32 [[TMP34]], [[TMP35]]
2126 // CHECK2-NEXT:    store i32 [[ADD13]], ptr [[DOTOMP_COMB_LB]], align 4
2127 // CHECK2-NEXT:    [[TMP36:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2128 // CHECK2-NEXT:    [[TMP37:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
2129 // CHECK2-NEXT:    [[ADD14:%.*]] = add nsw i32 [[TMP36]], [[TMP37]]
2130 // CHECK2-NEXT:    store i32 [[ADD14]], ptr [[DOTOMP_COMB_UB]], align 4
2131 // CHECK2-NEXT:    [[TMP38:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2132 // CHECK2-NEXT:    [[TMP39:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4
2133 // CHECK2-NEXT:    [[CMP15:%.*]] = icmp sgt i32 [[TMP38]], [[TMP39]]
2134 // CHECK2-NEXT:    br i1 [[CMP15]], label [[COND_TRUE16:%.*]], label [[COND_FALSE17:%.*]]
2135 // CHECK2:       cond.true16:
2136 // CHECK2-NEXT:    [[TMP40:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4
2137 // CHECK2-NEXT:    br label [[COND_END18:%.*]]
2138 // CHECK2:       cond.false17:
2139 // CHECK2-NEXT:    [[TMP41:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2140 // CHECK2-NEXT:    br label [[COND_END18]]
2141 // CHECK2:       cond.end18:
2142 // CHECK2-NEXT:    [[COND19:%.*]] = phi i32 [ [[TMP40]], [[COND_TRUE16]] ], [ [[TMP41]], [[COND_FALSE17]] ]
2143 // CHECK2-NEXT:    store i32 [[COND19]], ptr [[DOTOMP_COMB_UB]], align 4
2144 // CHECK2-NEXT:    [[TMP42:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
2145 // CHECK2-NEXT:    store i32 [[TMP42]], ptr [[DOTOMP_IV]], align 4
2146 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND]]
2147 // CHECK2:       omp.inner.for.end:
2148 // CHECK2-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2149 // CHECK2:       omp.loop.exit:
2150 // CHECK2-NEXT:    [[TMP43:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
2151 // CHECK2-NEXT:    [[TMP44:%.*]] = load i32, ptr [[TMP43]], align 4
2152 // CHECK2-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP44]])
2153 // CHECK2-NEXT:    br label [[OMP_PRECOND_END]]
2154 // CHECK2:       omp.precond.end:
2155 // CHECK2-NEXT:    ret void
2156 //
2157 //
2158 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l46_omp_outlined_omp_outlined
2159 // CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR1]] {
2160 // CHECK2-NEXT:  entry:
2161 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
2162 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
2163 // CHECK2-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
2164 // CHECK2-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
2165 // CHECK2-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
2166 // CHECK2-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
2167 // CHECK2-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2168 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2169 // CHECK2-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
2170 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
2171 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
2172 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4
2173 // CHECK2-NEXT:    [[I:%.*]] = alloca i32, align 4
2174 // CHECK2-NEXT:    [[J:%.*]] = alloca i32, align 4
2175 // CHECK2-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2176 // CHECK2-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2177 // CHECK2-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2178 // CHECK2-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2179 // CHECK2-NEXT:    [[I9:%.*]] = alloca i32, align 4
2180 // CHECK2-NEXT:    [[J10:%.*]] = alloca i32, align 4
2181 // CHECK2-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
2182 // CHECK2-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
2183 // CHECK2-NEXT:    store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
2184 // CHECK2-NEXT:    store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
2185 // CHECK2-NEXT:    store i64 [[N]], ptr [[N_ADDR]], align 8
2186 // CHECK2-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
2187 // CHECK2-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 8
2188 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
2189 // CHECK2-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
2190 // CHECK2-NEXT:    [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
2191 // CHECK2-NEXT:    store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_2]], align 4
2192 // CHECK2-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
2193 // CHECK2-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
2194 // CHECK2-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1
2195 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
2196 // CHECK2-NEXT:    [[SUB4:%.*]] = sub nsw i32 [[TMP4]], 0
2197 // CHECK2-NEXT:    [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1
2198 // CHECK2-NEXT:    [[MUL:%.*]] = mul nsw i32 [[DIV]], [[DIV5]]
2199 // CHECK2-NEXT:    [[SUB6:%.*]] = sub nsw i32 [[MUL]], 1
2200 // CHECK2-NEXT:    store i32 [[SUB6]], ptr [[DOTCAPTURE_EXPR_3]], align 4
2201 // CHECK2-NEXT:    store i32 0, ptr [[I]], align 4
2202 // CHECK2-NEXT:    store i32 0, ptr [[J]], align 4
2203 // CHECK2-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
2204 // CHECK2-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP5]]
2205 // CHECK2-NEXT:    br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]]
2206 // CHECK2:       land.lhs.true:
2207 // CHECK2-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
2208 // CHECK2-NEXT:    [[CMP7:%.*]] = icmp slt i32 0, [[TMP6]]
2209 // CHECK2-NEXT:    br i1 [[CMP7]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]]
2210 // CHECK2:       omp.precond.then:
2211 // CHECK2-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
2212 // CHECK2-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4
2213 // CHECK2-NEXT:    store i32 [[TMP7]], ptr [[DOTOMP_UB]], align 4
2214 // CHECK2-NEXT:    [[TMP8:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
2215 // CHECK2-NEXT:    [[CONV:%.*]] = trunc i64 [[TMP8]] to i32
2216 // CHECK2-NEXT:    [[TMP9:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
2217 // CHECK2-NEXT:    [[CONV8:%.*]] = trunc i64 [[TMP9]] to i32
2218 // CHECK2-NEXT:    store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
2219 // CHECK2-NEXT:    store i32 [[CONV8]], ptr [[DOTOMP_UB]], align 4
2220 // CHECK2-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
2221 // CHECK2-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2222 // CHECK2-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
2223 // CHECK2-NEXT:    [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4
2224 // CHECK2-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP11]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
2225 // CHECK2-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
2226 // CHECK2-NEXT:    store i32 [[TMP12]], ptr [[DOTOMP_IV]], align 4
2227 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2228 // CHECK2:       omp.inner.for.cond:
2229 // CHECK2-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2230 // CHECK2-NEXT:    [[CONV11:%.*]] = sext i32 [[TMP13]] to i64
2231 // CHECK2-NEXT:    [[TMP14:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
2232 // CHECK2-NEXT:    [[CMP12:%.*]] = icmp ule i64 [[CONV11]], [[TMP14]]
2233 // CHECK2-NEXT:    br i1 [[CMP12]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2234 // CHECK2:       omp.inner.for.body:
2235 // CHECK2-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2236 // CHECK2-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
2237 // CHECK2-NEXT:    [[SUB13:%.*]] = sub nsw i32 [[TMP16]], 0
2238 // CHECK2-NEXT:    [[DIV14:%.*]] = sdiv i32 [[SUB13]], 1
2239 // CHECK2-NEXT:    [[MUL15:%.*]] = mul nsw i32 1, [[DIV14]]
2240 // CHECK2-NEXT:    [[DIV16:%.*]] = sdiv i32 [[TMP15]], [[MUL15]]
2241 // CHECK2-NEXT:    [[MUL17:%.*]] = mul nsw i32 [[DIV16]], 1
2242 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL17]]
2243 // CHECK2-NEXT:    store i32 [[ADD]], ptr [[I9]], align 4
2244 // CHECK2-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2245 // CHECK2-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2246 // CHECK2-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
2247 // CHECK2-NEXT:    [[SUB18:%.*]] = sub nsw i32 [[TMP19]], 0
2248 // CHECK2-NEXT:    [[DIV19:%.*]] = sdiv i32 [[SUB18]], 1
2249 // CHECK2-NEXT:    [[MUL20:%.*]] = mul nsw i32 1, [[DIV19]]
2250 // CHECK2-NEXT:    [[DIV21:%.*]] = sdiv i32 [[TMP18]], [[MUL20]]
2251 // CHECK2-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
2252 // CHECK2-NEXT:    [[SUB22:%.*]] = sub nsw i32 [[TMP20]], 0
2253 // CHECK2-NEXT:    [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1
2254 // CHECK2-NEXT:    [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]]
2255 // CHECK2-NEXT:    [[MUL25:%.*]] = mul nsw i32 [[DIV21]], [[MUL24]]
2256 // CHECK2-NEXT:    [[SUB26:%.*]] = sub nsw i32 [[TMP17]], [[MUL25]]
2257 // CHECK2-NEXT:    [[MUL27:%.*]] = mul nsw i32 [[SUB26]], 1
2258 // CHECK2-NEXT:    [[ADD28:%.*]] = add nsw i32 0, [[MUL27]]
2259 // CHECK2-NEXT:    store i32 [[ADD28]], ptr [[J10]], align 4
2260 // CHECK2-NEXT:    [[TMP21:%.*]] = load i32, ptr [[I9]], align 4
2261 // CHECK2-NEXT:    [[TMP22:%.*]] = load i32, ptr [[J10]], align 4
2262 // CHECK2-NEXT:    [[ADD29:%.*]] = add nsw i32 [[TMP21]], [[TMP22]]
2263 // CHECK2-NEXT:    [[TMP23:%.*]] = load i32, ptr [[I9]], align 4
2264 // CHECK2-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64
2265 // CHECK2-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP0]], i64 0, i64 [[IDXPROM]]
2266 // CHECK2-NEXT:    [[TMP24:%.*]] = load i32, ptr [[J10]], align 4
2267 // CHECK2-NEXT:    [[IDXPROM30:%.*]] = sext i32 [[TMP24]] to i64
2268 // CHECK2-NEXT:    [[ARRAYIDX31:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM30]]
2269 // CHECK2-NEXT:    store i32 [[ADD29]], ptr [[ARRAYIDX31]], align 4
2270 // CHECK2-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2271 // CHECK2:       omp.body.continue:
2272 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2273 // CHECK2:       omp.inner.for.inc:
2274 // CHECK2-NEXT:    [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2275 // CHECK2-NEXT:    [[TMP26:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
2276 // CHECK2-NEXT:    [[ADD32:%.*]] = add nsw i32 [[TMP25]], [[TMP26]]
2277 // CHECK2-NEXT:    store i32 [[ADD32]], ptr [[DOTOMP_IV]], align 4
2278 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND]]
2279 // CHECK2:       omp.inner.for.end:
2280 // CHECK2-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2281 // CHECK2:       omp.loop.exit:
2282 // CHECK2-NEXT:    [[TMP27:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
2283 // CHECK2-NEXT:    [[TMP28:%.*]] = load i32, ptr [[TMP27]], align 4
2284 // CHECK2-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP28]])
2285 // CHECK2-NEXT:    br label [[OMP_PRECOND_END]]
2286 // CHECK2:       omp.precond.end:
2287 // CHECK2-NEXT:    ret void
2288 //
2289 //
2290 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l53
2291 // CHECK2-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], ptr noundef [[V:%.*]]) #[[ATTR4]] {
2292 // CHECK2-NEXT:  entry:
2293 // CHECK2-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
2294 // CHECK2-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
2295 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
2296 // CHECK2-NEXT:    [[V_ADDR:%.*]] = alloca ptr, align 8
2297 // CHECK2-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8
2298 // CHECK2-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
2299 // CHECK2-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
2300 // CHECK2-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
2301 // CHECK2-NEXT:    store i64 [[N]], ptr [[N_ADDR]], align 8
2302 // CHECK2-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
2303 // CHECK2-NEXT:    store ptr [[V]], ptr [[V_ADDR]], align 8
2304 // CHECK2-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
2305 // CHECK2-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l53_kernel_environment, ptr [[DYN_PTR]])
2306 // CHECK2-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
2307 // CHECK2-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
2308 // CHECK2:       user_code.entry:
2309 // CHECK2-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
2310 // CHECK2-NEXT:    [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4
2311 // CHECK2-NEXT:    store i32 [[TMP3]], ptr [[N_CASTED]], align 4
2312 // CHECK2-NEXT:    [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8
2313 // CHECK2-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[V_ADDR]], align 8
2314 // CHECK2-NEXT:    store i32 0, ptr [[DOTZERO_ADDR]], align 4
2315 // CHECK2-NEXT:    store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4
2316 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l53_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i64 [[TMP4]], ptr [[TMP0]], ptr [[TMP5]]) #[[ATTR2]]
2317 // CHECK2-NEXT:    call void @__kmpc_target_deinit()
2318 // CHECK2-NEXT:    ret void
2319 // CHECK2:       worker.exit:
2320 // CHECK2-NEXT:    ret void
2321 //
2322 //
2323 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l53_omp_outlined
2324 // CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], ptr noundef [[V:%.*]]) #[[ATTR1]] {
2325 // CHECK2-NEXT:  entry:
2326 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
2327 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
2328 // CHECK2-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
2329 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
2330 // CHECK2-NEXT:    [[V_ADDR:%.*]] = alloca ptr, align 8
2331 // CHECK2-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2332 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2333 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
2334 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
2335 // CHECK2-NEXT:    [[I:%.*]] = alloca i32, align 4
2336 // CHECK2-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
2337 // CHECK2-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
2338 // CHECK2-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2339 // CHECK2-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2340 // CHECK2-NEXT:    [[I3:%.*]] = alloca i32, align 4
2341 // CHECK2-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8
2342 // CHECK2-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [5 x ptr], align 8
2343 // CHECK2-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
2344 // CHECK2-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
2345 // CHECK2-NEXT:    store i64 [[N]], ptr [[N_ADDR]], align 8
2346 // CHECK2-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
2347 // CHECK2-NEXT:    store ptr [[V]], ptr [[V_ADDR]], align 8
2348 // CHECK2-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
2349 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
2350 // CHECK2-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
2351 // CHECK2-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
2352 // CHECK2-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
2353 // CHECK2-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1
2354 // CHECK2-NEXT:    [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
2355 // CHECK2-NEXT:    store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
2356 // CHECK2-NEXT:    store i32 0, ptr [[I]], align 4
2357 // CHECK2-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
2358 // CHECK2-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]
2359 // CHECK2-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
2360 // CHECK2:       omp.precond.then:
2361 // CHECK2-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
2362 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
2363 // CHECK2-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_COMB_UB]], align 4
2364 // CHECK2-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
2365 // CHECK2-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2366 // CHECK2-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
2367 // CHECK2-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
2368 // CHECK2-NEXT:    [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
2369 // CHECK2-NEXT:    call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP6]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
2370 // CHECK2-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2371 // CHECK2-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
2372 // CHECK2-NEXT:    [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]]
2373 // CHECK2-NEXT:    br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2374 // CHECK2:       cond.true:
2375 // CHECK2-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
2376 // CHECK2-NEXT:    br label [[COND_END:%.*]]
2377 // CHECK2:       cond.false:
2378 // CHECK2-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2379 // CHECK2-NEXT:    br label [[COND_END]]
2380 // CHECK2:       cond.end:
2381 // CHECK2-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
2382 // CHECK2-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
2383 // CHECK2-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
2384 // CHECK2-NEXT:    store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 4
2385 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2386 // CHECK2:       omp.inner.for.cond:
2387 // CHECK2-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2388 // CHECK2-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
2389 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP13]], 1
2390 // CHECK2-NEXT:    [[CMP5:%.*]] = icmp slt i32 [[TMP12]], [[ADD]]
2391 // CHECK2-NEXT:    br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2392 // CHECK2:       omp.inner.for.body:
2393 // CHECK2-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
2394 // CHECK2-NEXT:    [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
2395 // CHECK2-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2396 // CHECK2-NEXT:    [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
2397 // CHECK2-NEXT:    [[TMP18:%.*]] = load i32, ptr [[N_ADDR]], align 4
2398 // CHECK2-NEXT:    store i32 [[TMP18]], ptr [[N_CASTED]], align 4
2399 // CHECK2-NEXT:    [[TMP19:%.*]] = load i64, ptr [[N_CASTED]], align 8
2400 // CHECK2-NEXT:    [[TMP20:%.*]] = load ptr, ptr [[V_ADDR]], align 8
2401 // CHECK2-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
2402 // CHECK2-NEXT:    [[TMP22:%.*]] = inttoptr i64 [[TMP15]] to ptr
2403 // CHECK2-NEXT:    store ptr [[TMP22]], ptr [[TMP21]], align 8
2404 // CHECK2-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
2405 // CHECK2-NEXT:    [[TMP24:%.*]] = inttoptr i64 [[TMP17]] to ptr
2406 // CHECK2-NEXT:    store ptr [[TMP24]], ptr [[TMP23]], align 8
2407 // CHECK2-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
2408 // CHECK2-NEXT:    [[TMP26:%.*]] = inttoptr i64 [[TMP19]] to ptr
2409 // CHECK2-NEXT:    store ptr [[TMP26]], ptr [[TMP25]], align 8
2410 // CHECK2-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3
2411 // CHECK2-NEXT:    store ptr [[TMP0]], ptr [[TMP27]], align 8
2412 // CHECK2-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 4
2413 // CHECK2-NEXT:    store ptr [[TMP20]], ptr [[TMP28]], align 8
2414 // CHECK2-NEXT:    [[TMP29:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
2415 // CHECK2-NEXT:    [[TMP30:%.*]] = load i32, ptr [[TMP29]], align 4
2416 // CHECK2-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP30]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l53_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 5)
2417 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2418 // CHECK2:       omp.inner.for.inc:
2419 // CHECK2-NEXT:    [[TMP31:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2420 // CHECK2-NEXT:    [[TMP32:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
2421 // CHECK2-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP31]], [[TMP32]]
2422 // CHECK2-NEXT:    store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4
2423 // CHECK2-NEXT:    [[TMP33:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
2424 // CHECK2-NEXT:    [[TMP34:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
2425 // CHECK2-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP33]], [[TMP34]]
2426 // CHECK2-NEXT:    store i32 [[ADD7]], ptr [[DOTOMP_COMB_LB]], align 4
2427 // CHECK2-NEXT:    [[TMP35:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2428 // CHECK2-NEXT:    [[TMP36:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
2429 // CHECK2-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP35]], [[TMP36]]
2430 // CHECK2-NEXT:    store i32 [[ADD8]], ptr [[DOTOMP_COMB_UB]], align 4
2431 // CHECK2-NEXT:    [[TMP37:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2432 // CHECK2-NEXT:    [[TMP38:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
2433 // CHECK2-NEXT:    [[CMP9:%.*]] = icmp sgt i32 [[TMP37]], [[TMP38]]
2434 // CHECK2-NEXT:    br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]]
2435 // CHECK2:       cond.true10:
2436 // CHECK2-NEXT:    [[TMP39:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
2437 // CHECK2-NEXT:    br label [[COND_END12:%.*]]
2438 // CHECK2:       cond.false11:
2439 // CHECK2-NEXT:    [[TMP40:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2440 // CHECK2-NEXT:    br label [[COND_END12]]
2441 // CHECK2:       cond.end12:
2442 // CHECK2-NEXT:    [[COND13:%.*]] = phi i32 [ [[TMP39]], [[COND_TRUE10]] ], [ [[TMP40]], [[COND_FALSE11]] ]
2443 // CHECK2-NEXT:    store i32 [[COND13]], ptr [[DOTOMP_COMB_UB]], align 4
2444 // CHECK2-NEXT:    [[TMP41:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
2445 // CHECK2-NEXT:    store i32 [[TMP41]], ptr [[DOTOMP_IV]], align 4
2446 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND]]
2447 // CHECK2:       omp.inner.for.end:
2448 // CHECK2-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2449 // CHECK2:       omp.loop.exit:
2450 // CHECK2-NEXT:    [[TMP42:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
2451 // CHECK2-NEXT:    [[TMP43:%.*]] = load i32, ptr [[TMP42]], align 4
2452 // CHECK2-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP43]])
2453 // CHECK2-NEXT:    br label [[OMP_PRECOND_END]]
2454 // CHECK2:       omp.precond.end:
2455 // CHECK2-NEXT:    ret void
2456 //
2457 //
2458 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l53_omp_outlined_omp_outlined
2459 // CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], ptr noundef [[V:%.*]]) #[[ATTR1]] {
2460 // CHECK2-NEXT:  entry:
2461 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
2462 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
2463 // CHECK2-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
2464 // CHECK2-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
2465 // CHECK2-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
2466 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
2467 // CHECK2-NEXT:    [[V_ADDR:%.*]] = alloca ptr, align 8
2468 // CHECK2-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2469 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2470 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
2471 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
2472 // CHECK2-NEXT:    [[I:%.*]] = alloca i32, align 4
2473 // CHECK2-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2474 // CHECK2-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2475 // CHECK2-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2476 // CHECK2-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2477 // CHECK2-NEXT:    [[I4:%.*]] = alloca i32, align 4
2478 // CHECK2-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
2479 // CHECK2-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
2480 // CHECK2-NEXT:    store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
2481 // CHECK2-NEXT:    store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
2482 // CHECK2-NEXT:    store i64 [[N]], ptr [[N_ADDR]], align 8
2483 // CHECK2-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
2484 // CHECK2-NEXT:    store ptr [[V]], ptr [[V_ADDR]], align 8
2485 // CHECK2-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
2486 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
2487 // CHECK2-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
2488 // CHECK2-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
2489 // CHECK2-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
2490 // CHECK2-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1
2491 // CHECK2-NEXT:    [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
2492 // CHECK2-NEXT:    store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
2493 // CHECK2-NEXT:    store i32 0, ptr [[I]], align 4
2494 // CHECK2-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
2495 // CHECK2-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]
2496 // CHECK2-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
2497 // CHECK2:       omp.precond.then:
2498 // CHECK2-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
2499 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
2500 // CHECK2-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4
2501 // CHECK2-NEXT:    [[TMP5:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
2502 // CHECK2-NEXT:    [[CONV:%.*]] = trunc i64 [[TMP5]] to i32
2503 // CHECK2-NEXT:    [[TMP6:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
2504 // CHECK2-NEXT:    [[CONV3:%.*]] = trunc i64 [[TMP6]] to i32
2505 // CHECK2-NEXT:    store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
2506 // CHECK2-NEXT:    store i32 [[CONV3]], ptr [[DOTOMP_UB]], align 4
2507 // CHECK2-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
2508 // CHECK2-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2509 // CHECK2-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
2510 // CHECK2-NEXT:    [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
2511 // CHECK2-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP8]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
2512 // CHECK2-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
2513 // CHECK2-NEXT:    store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4
2514 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2515 // CHECK2:       omp.inner.for.cond:
2516 // CHECK2-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2517 // CHECK2-NEXT:    [[CONV5:%.*]] = sext i32 [[TMP10]] to i64
2518 // CHECK2-NEXT:    [[TMP11:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
2519 // CHECK2-NEXT:    [[CMP6:%.*]] = icmp ule i64 [[CONV5]], [[TMP11]]
2520 // CHECK2-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2521 // CHECK2:       omp.inner.for.body:
2522 // CHECK2-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2523 // CHECK2-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
2524 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2525 // CHECK2-NEXT:    store i32 [[ADD]], ptr [[I4]], align 4
2526 // CHECK2-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[V_ADDR]], align 8
2527 // CHECK2-NEXT:    [[TMP14:%.*]] = load i32, ptr [[I4]], align 4
2528 // CHECK2-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64
2529 // CHECK2-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP13]], i64 [[IDXPROM]]
2530 // CHECK2-NEXT:    [[TMP15:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
2531 // CHECK2-NEXT:    [[TMP16:%.*]] = load i32, ptr [[I4]], align 4
2532 // CHECK2-NEXT:    [[IDXPROM7:%.*]] = sext i32 [[TMP16]] to i64
2533 // CHECK2-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM7]]
2534 // CHECK2-NEXT:    store i32 [[TMP15]], ptr [[ARRAYIDX8]], align 4
2535 // CHECK2-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2536 // CHECK2:       omp.body.continue:
2537 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2538 // CHECK2:       omp.inner.for.inc:
2539 // CHECK2-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2540 // CHECK2-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
2541 // CHECK2-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP17]], [[TMP18]]
2542 // CHECK2-NEXT:    store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4
2543 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND]]
2544 // CHECK2:       omp.inner.for.end:
2545 // CHECK2-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2546 // CHECK2:       omp.loop.exit:
2547 // CHECK2-NEXT:    [[TMP19:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
2548 // CHECK2-NEXT:    [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4
2549 // CHECK2-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP20]])
2550 // CHECK2-NEXT:    br label [[OMP_PRECOND_END]]
2551 // CHECK2:       omp.precond.end:
2552 // CHECK2-NEXT:    ret void
2553 //
2554 //
2555 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28
2556 // CHECK3-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[N:%.*]], ptr noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR0:[0-9]+]] {
2557 // CHECK3-NEXT:  entry:
2558 // CHECK3-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
2559 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
2560 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca ptr, align 4
2561 // CHECK3-NEXT:    [[N_CASTED:%.*]] = alloca i32, align 4
2562 // CHECK3-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
2563 // CHECK3-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
2564 // CHECK3-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
2565 // CHECK3-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
2566 // CHECK3-NEXT:    store ptr [[AA]], ptr [[AA_ADDR]], align 4
2567 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 4
2568 // CHECK3-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28_kernel_environment, ptr [[DYN_PTR]])
2569 // CHECK3-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
2570 // CHECK3-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
2571 // CHECK3:       user_code.entry:
2572 // CHECK3-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
2573 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4
2574 // CHECK3-NEXT:    store i32 [[TMP3]], ptr [[N_CASTED]], align 4
2575 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N_CASTED]], align 4
2576 // CHECK3-NEXT:    store i32 0, ptr [[DOTZERO_ADDR]], align 4
2577 // CHECK3-NEXT:    store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4
2578 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i32 [[TMP4]], ptr [[TMP0]]) #[[ATTR2:[0-9]+]]
2579 // CHECK3-NEXT:    call void @__kmpc_target_deinit()
2580 // CHECK3-NEXT:    ret void
2581 // CHECK3:       worker.exit:
2582 // CHECK3-NEXT:    ret void
2583 //
2584 //
2585 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28_omp_outlined
2586 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], ptr noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR1:[0-9]+]] {
2587 // CHECK3-NEXT:  entry:
2588 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
2589 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
2590 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
2591 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca ptr, align 4
2592 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2593 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2594 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
2595 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
2596 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
2597 // CHECK3-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
2598 // CHECK3-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
2599 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2600 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2601 // CHECK3-NEXT:    [[I3:%.*]] = alloca i32, align 4
2602 // CHECK3-NEXT:    [[N_CASTED:%.*]] = alloca i32, align 4
2603 // CHECK3-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [4 x ptr], align 4
2604 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
2605 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
2606 // CHECK3-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
2607 // CHECK3-NEXT:    store ptr [[AA]], ptr [[AA_ADDR]], align 4
2608 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 4
2609 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
2610 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
2611 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
2612 // CHECK3-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
2613 // CHECK3-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1
2614 // CHECK3-NEXT:    [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
2615 // CHECK3-NEXT:    store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
2616 // CHECK3-NEXT:    store i32 0, ptr [[I]], align 4
2617 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
2618 // CHECK3-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]
2619 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
2620 // CHECK3:       omp.precond.then:
2621 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
2622 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
2623 // CHECK3-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_COMB_UB]], align 4
2624 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
2625 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2626 // CHECK3-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
2627 // CHECK3-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
2628 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
2629 // CHECK3-NEXT:    call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP6]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
2630 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2631 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
2632 // CHECK3-NEXT:    [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]]
2633 // CHECK3-NEXT:    br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2634 // CHECK3:       cond.true:
2635 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
2636 // CHECK3-NEXT:    br label [[COND_END:%.*]]
2637 // CHECK3:       cond.false:
2638 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2639 // CHECK3-NEXT:    br label [[COND_END]]
2640 // CHECK3:       cond.end:
2641 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
2642 // CHECK3-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
2643 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
2644 // CHECK3-NEXT:    store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 4
2645 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2646 // CHECK3:       omp.inner.for.cond:
2647 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2648 // CHECK3-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
2649 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP13]], 1
2650 // CHECK3-NEXT:    [[CMP5:%.*]] = icmp slt i32 [[TMP12]], [[ADD]]
2651 // CHECK3-NEXT:    br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2652 // CHECK3:       omp.inner.for.body:
2653 // CHECK3-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
2654 // CHECK3-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2655 // CHECK3-NEXT:    [[TMP16:%.*]] = load i32, ptr [[N_ADDR]], align 4
2656 // CHECK3-NEXT:    store i32 [[TMP16]], ptr [[N_CASTED]], align 4
2657 // CHECK3-NEXT:    [[TMP17:%.*]] = load i32, ptr [[N_CASTED]], align 4
2658 // CHECK3-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
2659 // CHECK3-NEXT:    [[TMP19:%.*]] = inttoptr i32 [[TMP14]] to ptr
2660 // CHECK3-NEXT:    store ptr [[TMP19]], ptr [[TMP18]], align 4
2661 // CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
2662 // CHECK3-NEXT:    [[TMP21:%.*]] = inttoptr i32 [[TMP15]] to ptr
2663 // CHECK3-NEXT:    store ptr [[TMP21]], ptr [[TMP20]], align 4
2664 // CHECK3-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 2
2665 // CHECK3-NEXT:    [[TMP23:%.*]] = inttoptr i32 [[TMP17]] to ptr
2666 // CHECK3-NEXT:    store ptr [[TMP23]], ptr [[TMP22]], align 4
2667 // CHECK3-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 3
2668 // CHECK3-NEXT:    store ptr [[TMP0]], ptr [[TMP24]], align 4
2669 // CHECK3-NEXT:    [[TMP25:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
2670 // CHECK3-NEXT:    [[TMP26:%.*]] = load i32, ptr [[TMP25]], align 4
2671 // CHECK3-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP26]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 4)
2672 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2673 // CHECK3:       omp.inner.for.inc:
2674 // CHECK3-NEXT:    [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2675 // CHECK3-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
2676 // CHECK3-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP27]], [[TMP28]]
2677 // CHECK3-NEXT:    store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4
2678 // CHECK3-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
2679 // CHECK3-NEXT:    [[TMP30:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
2680 // CHECK3-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP29]], [[TMP30]]
2681 // CHECK3-NEXT:    store i32 [[ADD7]], ptr [[DOTOMP_COMB_LB]], align 4
2682 // CHECK3-NEXT:    [[TMP31:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2683 // CHECK3-NEXT:    [[TMP32:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
2684 // CHECK3-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP31]], [[TMP32]]
2685 // CHECK3-NEXT:    store i32 [[ADD8]], ptr [[DOTOMP_COMB_UB]], align 4
2686 // CHECK3-NEXT:    [[TMP33:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2687 // CHECK3-NEXT:    [[TMP34:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
2688 // CHECK3-NEXT:    [[CMP9:%.*]] = icmp sgt i32 [[TMP33]], [[TMP34]]
2689 // CHECK3-NEXT:    br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]]
2690 // CHECK3:       cond.true10:
2691 // CHECK3-NEXT:    [[TMP35:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
2692 // CHECK3-NEXT:    br label [[COND_END12:%.*]]
2693 // CHECK3:       cond.false11:
2694 // CHECK3-NEXT:    [[TMP36:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2695 // CHECK3-NEXT:    br label [[COND_END12]]
2696 // CHECK3:       cond.end12:
2697 // CHECK3-NEXT:    [[COND13:%.*]] = phi i32 [ [[TMP35]], [[COND_TRUE10]] ], [ [[TMP36]], [[COND_FALSE11]] ]
2698 // CHECK3-NEXT:    store i32 [[COND13]], ptr [[DOTOMP_COMB_UB]], align 4
2699 // CHECK3-NEXT:    [[TMP37:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
2700 // CHECK3-NEXT:    store i32 [[TMP37]], ptr [[DOTOMP_IV]], align 4
2701 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]]
2702 // CHECK3:       omp.inner.for.end:
2703 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2704 // CHECK3:       omp.loop.exit:
2705 // CHECK3-NEXT:    [[TMP38:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
2706 // CHECK3-NEXT:    [[TMP39:%.*]] = load i32, ptr [[TMP38]], align 4
2707 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB3:[0-9]+]], i32 [[TMP39]])
2708 // CHECK3-NEXT:    br label [[OMP_PRECOND_END]]
2709 // CHECK3:       omp.precond.end:
2710 // CHECK3-NEXT:    ret void
2711 //
2712 //
2713 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28_omp_outlined_omp_outlined
2714 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], ptr noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR1]] {
2715 // CHECK3-NEXT:  entry:
2716 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
2717 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
2718 // CHECK3-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
2719 // CHECK3-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
2720 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
2721 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca ptr, align 4
2722 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2723 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2724 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
2725 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
2726 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
2727 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2728 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2729 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2730 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2731 // CHECK3-NEXT:    [[I3:%.*]] = alloca i32, align 4
2732 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
2733 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
2734 // CHECK3-NEXT:    store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4
2735 // CHECK3-NEXT:    store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
2736 // CHECK3-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
2737 // CHECK3-NEXT:    store ptr [[AA]], ptr [[AA_ADDR]], align 4
2738 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 4
2739 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
2740 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
2741 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
2742 // CHECK3-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
2743 // CHECK3-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1
2744 // CHECK3-NEXT:    [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
2745 // CHECK3-NEXT:    store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
2746 // CHECK3-NEXT:    store i32 0, ptr [[I]], align 4
2747 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
2748 // CHECK3-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]
2749 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
2750 // CHECK3:       omp.precond.then:
2751 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
2752 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
2753 // CHECK3-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4
2754 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4
2755 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
2756 // CHECK3-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_LB]], align 4
2757 // CHECK3-NEXT:    store i32 [[TMP6]], ptr [[DOTOMP_UB]], align 4
2758 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
2759 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2760 // CHECK3-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
2761 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
2762 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP8]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
2763 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
2764 // CHECK3-NEXT:    store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4
2765 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2766 // CHECK3:       omp.inner.for.cond:
2767 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2768 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
2769 // CHECK3-NEXT:    [[CMP4:%.*]] = icmp ule i32 [[TMP10]], [[TMP11]]
2770 // CHECK3-NEXT:    br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2771 // CHECK3:       omp.inner.for.body:
2772 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2773 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
2774 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2775 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[I3]], align 4
2776 // CHECK3-NEXT:    [[TMP13:%.*]] = load i32, ptr [[I3]], align 4
2777 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], ptr [[TMP0]], i32 0, i32 [[TMP13]]
2778 // CHECK3-NEXT:    [[TMP14:%.*]] = load i16, ptr [[ARRAYIDX]], align 2
2779 // CHECK3-NEXT:    [[CONV:%.*]] = sext i16 [[TMP14]] to i32
2780 // CHECK3-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV]], 1
2781 // CHECK3-NEXT:    [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
2782 // CHECK3-NEXT:    store i16 [[CONV6]], ptr [[ARRAYIDX]], align 2
2783 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2784 // CHECK3:       omp.body.continue:
2785 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2786 // CHECK3:       omp.inner.for.inc:
2787 // CHECK3-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2788 // CHECK3-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
2789 // CHECK3-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
2790 // CHECK3-NEXT:    store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4
2791 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]]
2792 // CHECK3:       omp.inner.for.end:
2793 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2794 // CHECK3:       omp.loop.exit:
2795 // CHECK3-NEXT:    [[TMP17:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
2796 // CHECK3-NEXT:    [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 4
2797 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP18]])
2798 // CHECK3-NEXT:    br label [[OMP_PRECOND_END]]
2799 // CHECK3:       omp.precond.end:
2800 // CHECK3-NEXT:    ret void
2801 //
2802 //
2803 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l33
2804 // CHECK3-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR4:[0-9]+]] {
2805 // CHECK3-NEXT:  entry:
2806 // CHECK3-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
2807 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
2808 // CHECK3-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
2809 // CHECK3-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
2810 // CHECK3-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
2811 // CHECK3-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
2812 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
2813 // CHECK3-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l33_kernel_environment, ptr [[DYN_PTR]])
2814 // CHECK3-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
2815 // CHECK3-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
2816 // CHECK3:       user_code.entry:
2817 // CHECK3-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
2818 // CHECK3-NEXT:    store i32 0, ptr [[DOTZERO_ADDR]], align 4
2819 // CHECK3-NEXT:    store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4
2820 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l33_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]]) #[[ATTR2]]
2821 // CHECK3-NEXT:    call void @__kmpc_target_deinit()
2822 // CHECK3-NEXT:    ret void
2823 // CHECK3:       worker.exit:
2824 // CHECK3-NEXT:    ret void
2825 //
2826 //
2827 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l33_omp_outlined
2828 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
2829 // CHECK3-NEXT:  entry:
2830 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
2831 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
2832 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
2833 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2834 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2835 // CHECK3-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
2836 // CHECK3-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
2837 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2838 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2839 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
2840 // CHECK3-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x ptr], align 4
2841 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
2842 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
2843 // CHECK3-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
2844 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
2845 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
2846 // CHECK3-NEXT:    store i32 9, ptr [[DOTOMP_COMB_UB]], align 4
2847 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
2848 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2849 // CHECK3-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
2850 // CHECK3-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
2851 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
2852 // CHECK3-NEXT:    call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP2]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
2853 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2854 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
2855 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2856 // CHECK3:       cond.true:
2857 // CHECK3-NEXT:    br label [[COND_END:%.*]]
2858 // CHECK3:       cond.false:
2859 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2860 // CHECK3-NEXT:    br label [[COND_END]]
2861 // CHECK3:       cond.end:
2862 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
2863 // CHECK3-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
2864 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
2865 // CHECK3-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
2866 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2867 // CHECK3:       omp.inner.for.cond:
2868 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2869 // CHECK3-NEXT:    [[CMP1:%.*]] = icmp slt i32 [[TMP6]], 10
2870 // CHECK3-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2871 // CHECK3:       omp.inner.for.body:
2872 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
2873 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2874 // CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
2875 // CHECK3-NEXT:    [[TMP10:%.*]] = inttoptr i32 [[TMP7]] to ptr
2876 // CHECK3-NEXT:    store ptr [[TMP10]], ptr [[TMP9]], align 4
2877 // CHECK3-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
2878 // CHECK3-NEXT:    [[TMP12:%.*]] = inttoptr i32 [[TMP8]] to ptr
2879 // CHECK3-NEXT:    store ptr [[TMP12]], ptr [[TMP11]], align 4
2880 // CHECK3-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 2
2881 // CHECK3-NEXT:    store ptr [[TMP0]], ptr [[TMP13]], align 4
2882 // CHECK3-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l33_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 3)
2883 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2884 // CHECK3:       omp.inner.for.inc:
2885 // CHECK3-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2886 // CHECK3-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
2887 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
2888 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
2889 // CHECK3-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
2890 // CHECK3-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
2891 // CHECK3-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
2892 // CHECK3-NEXT:    store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4
2893 // CHECK3-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2894 // CHECK3-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
2895 // CHECK3-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
2896 // CHECK3-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4
2897 // CHECK3-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2898 // CHECK3-NEXT:    [[CMP4:%.*]] = icmp sgt i32 [[TMP20]], 9
2899 // CHECK3-NEXT:    br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
2900 // CHECK3:       cond.true5:
2901 // CHECK3-NEXT:    br label [[COND_END7:%.*]]
2902 // CHECK3:       cond.false6:
2903 // CHECK3-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2904 // CHECK3-NEXT:    br label [[COND_END7]]
2905 // CHECK3:       cond.end7:
2906 // CHECK3-NEXT:    [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP21]], [[COND_FALSE6]] ]
2907 // CHECK3-NEXT:    store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4
2908 // CHECK3-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
2909 // CHECK3-NEXT:    store i32 [[TMP22]], ptr [[DOTOMP_IV]], align 4
2910 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]]
2911 // CHECK3:       omp.inner.for.end:
2912 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2913 // CHECK3:       omp.loop.exit:
2914 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP2]])
2915 // CHECK3-NEXT:    ret void
2916 //
2917 //
2918 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l33_omp_outlined_omp_outlined
2919 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
2920 // CHECK3-NEXT:  entry:
2921 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
2922 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
2923 // CHECK3-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
2924 // CHECK3-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
2925 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
2926 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2927 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2928 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2929 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2930 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2931 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2932 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
2933 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
2934 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
2935 // CHECK3-NEXT:    store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4
2936 // CHECK3-NEXT:    store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
2937 // CHECK3-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
2938 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
2939 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
2940 // CHECK3-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4
2941 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4
2942 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
2943 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[DOTOMP_LB]], align 4
2944 // CHECK3-NEXT:    store i32 [[TMP2]], ptr [[DOTOMP_UB]], align 4
2945 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
2946 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2947 // CHECK3-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
2948 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
2949 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP4]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
2950 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
2951 // CHECK3-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
2952 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2953 // CHECK3:       omp.inner.for.cond:
2954 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2955 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
2956 // CHECK3-NEXT:    [[CMP:%.*]] = icmp ule i32 [[TMP6]], [[TMP7]]
2957 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2958 // CHECK3:       omp.inner.for.body:
2959 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2960 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
2961 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2962 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[I]], align 4
2963 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[I]], align 4
2964 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP9]]
2965 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
2966 // CHECK3-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP10]], 1
2967 // CHECK3-NEXT:    store i32 [[ADD1]], ptr [[ARRAYIDX]], align 4
2968 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2969 // CHECK3:       omp.body.continue:
2970 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2971 // CHECK3:       omp.inner.for.inc:
2972 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2973 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
2974 // CHECK3-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
2975 // CHECK3-NEXT:    store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4
2976 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]]
2977 // CHECK3:       omp.inner.for.end:
2978 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2979 // CHECK3:       omp.loop.exit:
2980 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP4]])
2981 // CHECK3-NEXT:    ret void
2982 //
2983 //
2984 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l38
2985 // CHECK3-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[F:%.*]]) #[[ATTR4]] {
2986 // CHECK3-NEXT:  entry:
2987 // CHECK3-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
2988 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
2989 // CHECK3-NEXT:    [[F_ADDR:%.*]] = alloca i32, align 4
2990 // CHECK3-NEXT:    [[F_CASTED:%.*]] = alloca i32, align 4
2991 // CHECK3-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
2992 // CHECK3-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
2993 // CHECK3-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
2994 // CHECK3-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
2995 // CHECK3-NEXT:    store i32 [[F]], ptr [[F_ADDR]], align 4
2996 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 4
2997 // CHECK3-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l38_kernel_environment, ptr [[DYN_PTR]])
2998 // CHECK3-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
2999 // CHECK3-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
3000 // CHECK3:       user_code.entry:
3001 // CHECK3-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
3002 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[F_ADDR]], align 4
3003 // CHECK3-NEXT:    store i32 [[TMP3]], ptr [[F_CASTED]], align 4
3004 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[F_CASTED]], align 4
3005 // CHECK3-NEXT:    store i32 0, ptr [[DOTZERO_ADDR]], align 4
3006 // CHECK3-NEXT:    store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4
3007 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l38_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]], i32 [[TMP4]]) #[[ATTR2]]
3008 // CHECK3-NEXT:    call void @__kmpc_target_deinit()
3009 // CHECK3-NEXT:    ret void
3010 // CHECK3:       worker.exit:
3011 // CHECK3-NEXT:    ret void
3012 //
3013 //
3014 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l38_omp_outlined
3015 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[F:%.*]]) #[[ATTR1]] {
3016 // CHECK3-NEXT:  entry:
3017 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
3018 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
3019 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
3020 // CHECK3-NEXT:    [[F_ADDR:%.*]] = alloca i32, align 4
3021 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
3022 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
3023 // CHECK3-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
3024 // CHECK3-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
3025 // CHECK3-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
3026 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3027 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3028 // CHECK3-NEXT:    [[K:%.*]] = alloca i32, align 4
3029 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
3030 // CHECK3-NEXT:    [[J:%.*]] = alloca i32, align 4
3031 // CHECK3-NEXT:    [[F_CASTED:%.*]] = alloca i32, align 4
3032 // CHECK3-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [4 x ptr], align 4
3033 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
3034 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
3035 // CHECK3-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
3036 // CHECK3-NEXT:    store i32 [[F]], ptr [[F_ADDR]], align 4
3037 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 4
3038 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
3039 // CHECK3-NEXT:    store i32 99, ptr [[DOTOMP_COMB_UB]], align 4
3040 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
3041 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
3042 // CHECK3-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
3043 // CHECK3-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
3044 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
3045 // CHECK3-NEXT:    call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP2]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
3046 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
3047 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 99
3048 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3049 // CHECK3:       cond.true:
3050 // CHECK3-NEXT:    br label [[COND_END:%.*]]
3051 // CHECK3:       cond.false:
3052 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
3053 // CHECK3-NEXT:    br label [[COND_END]]
3054 // CHECK3:       cond.end:
3055 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 99, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
3056 // CHECK3-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
3057 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
3058 // CHECK3-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
3059 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
3060 // CHECK3:       omp.inner.for.cond:
3061 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3062 // CHECK3-NEXT:    [[CMP2:%.*]] = icmp slt i32 [[TMP6]], 100
3063 // CHECK3-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3064 // CHECK3:       omp.inner.for.body:
3065 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
3066 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
3067 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[F_ADDR]], align 4
3068 // CHECK3-NEXT:    store i32 [[TMP9]], ptr [[F_CASTED]], align 4
3069 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[F_CASTED]], align 4
3070 // CHECK3-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
3071 // CHECK3-NEXT:    [[TMP12:%.*]] = inttoptr i32 [[TMP7]] to ptr
3072 // CHECK3-NEXT:    store ptr [[TMP12]], ptr [[TMP11]], align 4
3073 // CHECK3-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
3074 // CHECK3-NEXT:    [[TMP14:%.*]] = inttoptr i32 [[TMP8]] to ptr
3075 // CHECK3-NEXT:    store ptr [[TMP14]], ptr [[TMP13]], align 4
3076 // CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 2
3077 // CHECK3-NEXT:    store ptr [[TMP0]], ptr [[TMP15]], align 4
3078 // CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 3
3079 // CHECK3-NEXT:    [[TMP17:%.*]] = inttoptr i32 [[TMP10]] to ptr
3080 // CHECK3-NEXT:    store ptr [[TMP17]], ptr [[TMP16]], align 4
3081 // CHECK3-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l38_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 4)
3082 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
3083 // CHECK3:       omp.inner.for.inc:
3084 // CHECK3-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3085 // CHECK3-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
3086 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
3087 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
3088 // CHECK3-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
3089 // CHECK3-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
3090 // CHECK3-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]
3091 // CHECK3-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_COMB_LB]], align 4
3092 // CHECK3-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
3093 // CHECK3-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
3094 // CHECK3-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]
3095 // CHECK3-NEXT:    store i32 [[ADD4]], ptr [[DOTOMP_COMB_UB]], align 4
3096 // CHECK3-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
3097 // CHECK3-NEXT:    [[CMP5:%.*]] = icmp sgt i32 [[TMP24]], 99
3098 // CHECK3-NEXT:    br i1 [[CMP5]], label [[COND_TRUE6:%.*]], label [[COND_FALSE7:%.*]]
3099 // CHECK3:       cond.true6:
3100 // CHECK3-NEXT:    br label [[COND_END8:%.*]]
3101 // CHECK3:       cond.false7:
3102 // CHECK3-NEXT:    [[TMP25:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
3103 // CHECK3-NEXT:    br label [[COND_END8]]
3104 // CHECK3:       cond.end8:
3105 // CHECK3-NEXT:    [[COND9:%.*]] = phi i32 [ 99, [[COND_TRUE6]] ], [ [[TMP25]], [[COND_FALSE7]] ]
3106 // CHECK3-NEXT:    store i32 [[COND9]], ptr [[DOTOMP_COMB_UB]], align 4
3107 // CHECK3-NEXT:    [[TMP26:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
3108 // CHECK3-NEXT:    store i32 [[TMP26]], ptr [[DOTOMP_IV]], align 4
3109 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]]
3110 // CHECK3:       omp.inner.for.end:
3111 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
3112 // CHECK3:       omp.loop.exit:
3113 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP2]])
3114 // CHECK3-NEXT:    ret void
3115 //
3116 //
3117 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l38_omp_outlined_omp_outlined
3118 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[F:%.*]]) #[[ATTR1]] {
3119 // CHECK3-NEXT:  entry:
3120 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
3121 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
3122 // CHECK3-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
3123 // CHECK3-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
3124 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
3125 // CHECK3-NEXT:    [[F_ADDR:%.*]] = alloca i32, align 4
3126 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
3127 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
3128 // CHECK3-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
3129 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
3130 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
3131 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3132 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3133 // CHECK3-NEXT:    [[K:%.*]] = alloca i32, align 4
3134 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
3135 // CHECK3-NEXT:    [[J:%.*]] = alloca i32, align 4
3136 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
3137 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
3138 // CHECK3-NEXT:    store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4
3139 // CHECK3-NEXT:    store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
3140 // CHECK3-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
3141 // CHECK3-NEXT:    store i32 [[F]], ptr [[F_ADDR]], align 4
3142 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 4
3143 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
3144 // CHECK3-NEXT:    store i32 99, ptr [[DOTOMP_UB]], align 4
3145 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4
3146 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
3147 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[DOTOMP_LB]], align 4
3148 // CHECK3-NEXT:    store i32 [[TMP2]], ptr [[DOTOMP_UB]], align 4
3149 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
3150 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
3151 // CHECK3-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
3152 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
3153 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP4]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
3154 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
3155 // CHECK3-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
3156 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
3157 // CHECK3:       omp.inner.for.cond:
3158 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3159 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
3160 // CHECK3-NEXT:    [[CMP:%.*]] = icmp ule i32 [[TMP6]], [[TMP7]]
3161 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3162 // CHECK3:       omp.inner.for.body:
3163 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3164 // CHECK3-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP8]], 10
3165 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
3166 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
3167 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[I]], align 4
3168 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3169 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3170 // CHECK3-NEXT:    [[DIV2:%.*]] = sdiv i32 [[TMP10]], 10
3171 // CHECK3-NEXT:    [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 10
3172 // CHECK3-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL3]]
3173 // CHECK3-NEXT:    [[MUL4:%.*]] = mul nsw i32 [[SUB]], 1
3174 // CHECK3-NEXT:    [[ADD5:%.*]] = add nsw i32 0, [[MUL4]]
3175 // CHECK3-NEXT:    store i32 [[ADD5]], ptr [[J]], align 4
3176 // CHECK3-NEXT:    store i32 10, ptr [[K]], align 4
3177 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 4
3178 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, ptr [[J]], align 4
3179 // CHECK3-NEXT:    [[TMP13:%.*]] = load i32, ptr [[F_ADDR]], align 4
3180 // CHECK3-NEXT:    [[MUL6:%.*]] = mul nsw i32 [[TMP12]], [[TMP13]]
3181 // CHECK3-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP11]], [[MUL6]]
3182 // CHECK3-NEXT:    [[TMP14:%.*]] = load i32, ptr [[K]], align 4
3183 // CHECK3-NEXT:    [[ADD8:%.*]] = add nsw i32 [[ADD7]], [[TMP14]]
3184 // CHECK3-NEXT:    [[TMP15:%.*]] = load i32, ptr [[I]], align 4
3185 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP0]], i32 0, i32 [[TMP15]]
3186 // CHECK3-NEXT:    [[TMP16:%.*]] = load i32, ptr [[J]], align 4
3187 // CHECK3-NEXT:    [[ARRAYIDX9:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX]], i32 0, i32 [[TMP16]]
3188 // CHECK3-NEXT:    store i32 [[ADD8]], ptr [[ARRAYIDX9]], align 4
3189 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
3190 // CHECK3:       omp.body.continue:
3191 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
3192 // CHECK3:       omp.inner.for.inc:
3193 // CHECK3-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3194 // CHECK3-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
3195 // CHECK3-NEXT:    [[ADD10:%.*]] = add nsw i32 [[TMP17]], [[TMP18]]
3196 // CHECK3-NEXT:    store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4
3197 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]]
3198 // CHECK3:       omp.inner.for.end:
3199 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
3200 // CHECK3:       omp.loop.exit:
3201 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP4]])
3202 // CHECK3-NEXT:    ret void
3203 //
3204 //
3205 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l46
3206 // CHECK3-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR4]] {
3207 // CHECK3-NEXT:  entry:
3208 // CHECK3-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
3209 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
3210 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
3211 // CHECK3-NEXT:    [[N_CASTED:%.*]] = alloca i32, align 4
3212 // CHECK3-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
3213 // CHECK3-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
3214 // CHECK3-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
3215 // CHECK3-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
3216 // CHECK3-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
3217 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 4
3218 // CHECK3-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l46_kernel_environment, ptr [[DYN_PTR]])
3219 // CHECK3-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
3220 // CHECK3-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
3221 // CHECK3:       user_code.entry:
3222 // CHECK3-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
3223 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4
3224 // CHECK3-NEXT:    store i32 [[TMP3]], ptr [[N_CASTED]], align 4
3225 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N_CASTED]], align 4
3226 // CHECK3-NEXT:    store i32 0, ptr [[DOTZERO_ADDR]], align 4
3227 // CHECK3-NEXT:    store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4
3228 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l46_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i32 [[TMP4]], ptr [[TMP0]]) #[[ATTR2]]
3229 // CHECK3-NEXT:    call void @__kmpc_target_deinit()
3230 // CHECK3-NEXT:    ret void
3231 // CHECK3:       worker.exit:
3232 // CHECK3-NEXT:    ret void
3233 //
3234 //
3235 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l46_omp_outlined
3236 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR1]] {
3237 // CHECK3-NEXT:  entry:
3238 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
3239 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
3240 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
3241 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
3242 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
3243 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
3244 // CHECK3-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
3245 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
3246 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
3247 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8
3248 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
3249 // CHECK3-NEXT:    [[J:%.*]] = alloca i32, align 4
3250 // CHECK3-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i64, align 8
3251 // CHECK3-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i64, align 8
3252 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
3253 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3254 // CHECK3-NEXT:    [[I9:%.*]] = alloca i32, align 4
3255 // CHECK3-NEXT:    [[J10:%.*]] = alloca i32, align 4
3256 // CHECK3-NEXT:    [[N_CASTED:%.*]] = alloca i32, align 4
3257 // CHECK3-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [4 x ptr], align 4
3258 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
3259 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
3260 // CHECK3-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
3261 // CHECK3-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
3262 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 4
3263 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
3264 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
3265 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
3266 // CHECK3-NEXT:    store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_2]], align 4
3267 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
3268 // CHECK3-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
3269 // CHECK3-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1
3270 // CHECK3-NEXT:    [[CONV:%.*]] = sext i32 [[DIV]] to i64
3271 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
3272 // CHECK3-NEXT:    [[SUB4:%.*]] = sub nsw i32 [[TMP4]], 0
3273 // CHECK3-NEXT:    [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1
3274 // CHECK3-NEXT:    [[CONV6:%.*]] = sext i32 [[DIV5]] to i64
3275 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]]
3276 // CHECK3-NEXT:    [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1
3277 // CHECK3-NEXT:    store i64 [[SUB7]], ptr [[DOTCAPTURE_EXPR_3]], align 8
3278 // CHECK3-NEXT:    store i32 0, ptr [[I]], align 4
3279 // CHECK3-NEXT:    store i32 0, ptr [[J]], align 4
3280 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
3281 // CHECK3-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP5]]
3282 // CHECK3-NEXT:    br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]]
3283 // CHECK3:       land.lhs.true:
3284 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
3285 // CHECK3-NEXT:    [[CMP8:%.*]] = icmp slt i32 0, [[TMP6]]
3286 // CHECK3-NEXT:    br i1 [[CMP8]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]]
3287 // CHECK3:       omp.precond.then:
3288 // CHECK3-NEXT:    store i64 0, ptr [[DOTOMP_COMB_LB]], align 8
3289 // CHECK3-NEXT:    [[TMP7:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_3]], align 8
3290 // CHECK3-NEXT:    store i64 [[TMP7]], ptr [[DOTOMP_COMB_UB]], align 8
3291 // CHECK3-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8
3292 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
3293 // CHECK3-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
3294 // CHECK3-NEXT:    [[CONV11:%.*]] = zext i32 [[NVPTX_NUM_THREADS]] to i64
3295 // CHECK3-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
3296 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
3297 // CHECK3-NEXT:    call void @__kmpc_distribute_static_init_8(ptr @[[GLOB2]], i32 [[TMP9]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 [[CONV11]])
3298 // CHECK3-NEXT:    [[TMP10:%.*]] = load i64, ptr [[DOTOMP_COMB_UB]], align 8
3299 // CHECK3-NEXT:    [[TMP11:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_3]], align 8
3300 // CHECK3-NEXT:    [[CMP12:%.*]] = icmp sgt i64 [[TMP10]], [[TMP11]]
3301 // CHECK3-NEXT:    br i1 [[CMP12]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3302 // CHECK3:       cond.true:
3303 // CHECK3-NEXT:    [[TMP12:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_3]], align 8
3304 // CHECK3-NEXT:    br label [[COND_END:%.*]]
3305 // CHECK3:       cond.false:
3306 // CHECK3-NEXT:    [[TMP13:%.*]] = load i64, ptr [[DOTOMP_COMB_UB]], align 8
3307 // CHECK3-NEXT:    br label [[COND_END]]
3308 // CHECK3:       cond.end:
3309 // CHECK3-NEXT:    [[COND:%.*]] = phi i64 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ]
3310 // CHECK3-NEXT:    store i64 [[COND]], ptr [[DOTOMP_COMB_UB]], align 8
3311 // CHECK3-NEXT:    [[TMP14:%.*]] = load i64, ptr [[DOTOMP_COMB_LB]], align 8
3312 // CHECK3-NEXT:    store i64 [[TMP14]], ptr [[DOTOMP_IV]], align 8
3313 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
3314 // CHECK3:       omp.inner.for.cond:
3315 // CHECK3-NEXT:    [[TMP15:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
3316 // CHECK3-NEXT:    [[TMP16:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_3]], align 8
3317 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i64 [[TMP16]], 1
3318 // CHECK3-NEXT:    [[CMP13:%.*]] = icmp slt i64 [[TMP15]], [[ADD]]
3319 // CHECK3-NEXT:    br i1 [[CMP13]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3320 // CHECK3:       omp.inner.for.body:
3321 // CHECK3-NEXT:    [[TMP17:%.*]] = load i64, ptr [[DOTOMP_COMB_LB]], align 8
3322 // CHECK3-NEXT:    [[TMP18:%.*]] = trunc i64 [[TMP17]] to i32
3323 // CHECK3-NEXT:    [[TMP19:%.*]] = load i64, ptr [[DOTOMP_COMB_UB]], align 8
3324 // CHECK3-NEXT:    [[TMP20:%.*]] = trunc i64 [[TMP19]] to i32
3325 // CHECK3-NEXT:    [[TMP21:%.*]] = load i32, ptr [[N_ADDR]], align 4
3326 // CHECK3-NEXT:    store i32 [[TMP21]], ptr [[N_CASTED]], align 4
3327 // CHECK3-NEXT:    [[TMP22:%.*]] = load i32, ptr [[N_CASTED]], align 4
3328 // CHECK3-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
3329 // CHECK3-NEXT:    [[TMP24:%.*]] = inttoptr i32 [[TMP18]] to ptr
3330 // CHECK3-NEXT:    store ptr [[TMP24]], ptr [[TMP23]], align 4
3331 // CHECK3-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
3332 // CHECK3-NEXT:    [[TMP26:%.*]] = inttoptr i32 [[TMP20]] to ptr
3333 // CHECK3-NEXT:    store ptr [[TMP26]], ptr [[TMP25]], align 4
3334 // CHECK3-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 2
3335 // CHECK3-NEXT:    [[TMP28:%.*]] = inttoptr i32 [[TMP22]] to ptr
3336 // CHECK3-NEXT:    store ptr [[TMP28]], ptr [[TMP27]], align 4
3337 // CHECK3-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 3
3338 // CHECK3-NEXT:    store ptr [[TMP0]], ptr [[TMP29]], align 4
3339 // CHECK3-NEXT:    [[TMP30:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
3340 // CHECK3-NEXT:    [[TMP31:%.*]] = load i32, ptr [[TMP30]], align 4
3341 // CHECK3-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP31]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l46_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 4)
3342 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
3343 // CHECK3:       omp.inner.for.inc:
3344 // CHECK3-NEXT:    [[TMP32:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
3345 // CHECK3-NEXT:    [[TMP33:%.*]] = load i64, ptr [[DOTOMP_STRIDE]], align 8
3346 // CHECK3-NEXT:    [[ADD14:%.*]] = add nsw i64 [[TMP32]], [[TMP33]]
3347 // CHECK3-NEXT:    store i64 [[ADD14]], ptr [[DOTOMP_IV]], align 8
3348 // CHECK3-NEXT:    [[TMP34:%.*]] = load i64, ptr [[DOTOMP_COMB_LB]], align 8
3349 // CHECK3-NEXT:    [[TMP35:%.*]] = load i64, ptr [[DOTOMP_STRIDE]], align 8
3350 // CHECK3-NEXT:    [[ADD15:%.*]] = add nsw i64 [[TMP34]], [[TMP35]]
3351 // CHECK3-NEXT:    store i64 [[ADD15]], ptr [[DOTOMP_COMB_LB]], align 8
3352 // CHECK3-NEXT:    [[TMP36:%.*]] = load i64, ptr [[DOTOMP_COMB_UB]], align 8
3353 // CHECK3-NEXT:    [[TMP37:%.*]] = load i64, ptr [[DOTOMP_STRIDE]], align 8
3354 // CHECK3-NEXT:    [[ADD16:%.*]] = add nsw i64 [[TMP36]], [[TMP37]]
3355 // CHECK3-NEXT:    store i64 [[ADD16]], ptr [[DOTOMP_COMB_UB]], align 8
3356 // CHECK3-NEXT:    [[TMP38:%.*]] = load i64, ptr [[DOTOMP_COMB_UB]], align 8
3357 // CHECK3-NEXT:    [[TMP39:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_3]], align 8
3358 // CHECK3-NEXT:    [[CMP17:%.*]] = icmp sgt i64 [[TMP38]], [[TMP39]]
3359 // CHECK3-NEXT:    br i1 [[CMP17]], label [[COND_TRUE18:%.*]], label [[COND_FALSE19:%.*]]
3360 // CHECK3:       cond.true18:
3361 // CHECK3-NEXT:    [[TMP40:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_3]], align 8
3362 // CHECK3-NEXT:    br label [[COND_END20:%.*]]
3363 // CHECK3:       cond.false19:
3364 // CHECK3-NEXT:    [[TMP41:%.*]] = load i64, ptr [[DOTOMP_COMB_UB]], align 8
3365 // CHECK3-NEXT:    br label [[COND_END20]]
3366 // CHECK3:       cond.end20:
3367 // CHECK3-NEXT:    [[COND21:%.*]] = phi i64 [ [[TMP40]], [[COND_TRUE18]] ], [ [[TMP41]], [[COND_FALSE19]] ]
3368 // CHECK3-NEXT:    store i64 [[COND21]], ptr [[DOTOMP_COMB_UB]], align 8
3369 // CHECK3-NEXT:    [[TMP42:%.*]] = load i64, ptr [[DOTOMP_COMB_LB]], align 8
3370 // CHECK3-NEXT:    store i64 [[TMP42]], ptr [[DOTOMP_IV]], align 8
3371 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]]
3372 // CHECK3:       omp.inner.for.end:
3373 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
3374 // CHECK3:       omp.loop.exit:
3375 // CHECK3-NEXT:    [[TMP43:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
3376 // CHECK3-NEXT:    [[TMP44:%.*]] = load i32, ptr [[TMP43]], align 4
3377 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP44]])
3378 // CHECK3-NEXT:    br label [[OMP_PRECOND_END]]
3379 // CHECK3:       omp.precond.end:
3380 // CHECK3-NEXT:    ret void
3381 //
3382 //
3383 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l46_omp_outlined_omp_outlined
3384 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR1]] {
3385 // CHECK3-NEXT:  entry:
3386 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
3387 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
3388 // CHECK3-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
3389 // CHECK3-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
3390 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
3391 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
3392 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
3393 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
3394 // CHECK3-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
3395 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
3396 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
3397 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8
3398 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
3399 // CHECK3-NEXT:    [[J:%.*]] = alloca i32, align 4
3400 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
3401 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
3402 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
3403 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3404 // CHECK3-NEXT:    [[I11:%.*]] = alloca i32, align 4
3405 // CHECK3-NEXT:    [[J12:%.*]] = alloca i32, align 4
3406 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
3407 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
3408 // CHECK3-NEXT:    store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4
3409 // CHECK3-NEXT:    store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
3410 // CHECK3-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
3411 // CHECK3-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
3412 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[C_ADDR]], align 4
3413 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
3414 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
3415 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
3416 // CHECK3-NEXT:    store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_2]], align 4
3417 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
3418 // CHECK3-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP3]], 0
3419 // CHECK3-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1
3420 // CHECK3-NEXT:    [[CONV:%.*]] = sext i32 [[DIV]] to i64
3421 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
3422 // CHECK3-NEXT:    [[SUB4:%.*]] = sub nsw i32 [[TMP4]], 0
3423 // CHECK3-NEXT:    [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1
3424 // CHECK3-NEXT:    [[CONV6:%.*]] = sext i32 [[DIV5]] to i64
3425 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]]
3426 // CHECK3-NEXT:    [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1
3427 // CHECK3-NEXT:    store i64 [[SUB7]], ptr [[DOTCAPTURE_EXPR_3]], align 8
3428 // CHECK3-NEXT:    store i32 0, ptr [[I]], align 4
3429 // CHECK3-NEXT:    store i32 0, ptr [[J]], align 4
3430 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
3431 // CHECK3-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP5]]
3432 // CHECK3-NEXT:    br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]]
3433 // CHECK3:       land.lhs.true:
3434 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
3435 // CHECK3-NEXT:    [[CMP8:%.*]] = icmp slt i32 0, [[TMP6]]
3436 // CHECK3-NEXT:    br i1 [[CMP8]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]]
3437 // CHECK3:       omp.precond.then:
3438 // CHECK3-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8
3439 // CHECK3-NEXT:    [[TMP7:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_3]], align 8
3440 // CHECK3-NEXT:    store i64 [[TMP7]], ptr [[DOTOMP_UB]], align 8
3441 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4
3442 // CHECK3-NEXT:    [[CONV9:%.*]] = zext i32 [[TMP8]] to i64
3443 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
3444 // CHECK3-NEXT:    [[CONV10:%.*]] = zext i32 [[TMP9]] to i64
3445 // CHECK3-NEXT:    store i64 [[CONV9]], ptr [[DOTOMP_LB]], align 8
3446 // CHECK3-NEXT:    store i64 [[CONV10]], ptr [[DOTOMP_UB]], align 8
3447 // CHECK3-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8
3448 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
3449 // CHECK3-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
3450 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4
3451 // CHECK3-NEXT:    call void @__kmpc_for_static_init_8(ptr @[[GLOB3]], i32 [[TMP11]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
3452 // CHECK3-NEXT:    [[TMP12:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
3453 // CHECK3-NEXT:    store i64 [[TMP12]], ptr [[DOTOMP_IV]], align 8
3454 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
3455 // CHECK3:       omp.inner.for.cond:
3456 // CHECK3-NEXT:    [[TMP13:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
3457 // CHECK3-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
3458 // CHECK3-NEXT:    [[CONV13:%.*]] = zext i32 [[TMP14]] to i64
3459 // CHECK3-NEXT:    [[CMP14:%.*]] = icmp sle i64 [[TMP13]], [[CONV13]]
3460 // CHECK3-NEXT:    br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3461 // CHECK3:       omp.inner.for.body:
3462 // CHECK3-NEXT:    [[TMP15:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
3463 // CHECK3-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
3464 // CHECK3-NEXT:    [[SUB15:%.*]] = sub nsw i32 [[TMP16]], 0
3465 // CHECK3-NEXT:    [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1
3466 // CHECK3-NEXT:    [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]]
3467 // CHECK3-NEXT:    [[CONV18:%.*]] = sext i32 [[MUL17]] to i64
3468 // CHECK3-NEXT:    [[DIV19:%.*]] = sdiv i64 [[TMP15]], [[CONV18]]
3469 // CHECK3-NEXT:    [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1
3470 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i64 0, [[MUL20]]
3471 // CHECK3-NEXT:    [[CONV21:%.*]] = trunc i64 [[ADD]] to i32
3472 // CHECK3-NEXT:    store i32 [[CONV21]], ptr [[I11]], align 4
3473 // CHECK3-NEXT:    [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
3474 // CHECK3-NEXT:    [[TMP18:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
3475 // CHECK3-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
3476 // CHECK3-NEXT:    [[SUB22:%.*]] = sub nsw i32 [[TMP19]], 0
3477 // CHECK3-NEXT:    [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1
3478 // CHECK3-NEXT:    [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]]
3479 // CHECK3-NEXT:    [[CONV25:%.*]] = sext i32 [[MUL24]] to i64
3480 // CHECK3-NEXT:    [[DIV26:%.*]] = sdiv i64 [[TMP18]], [[CONV25]]
3481 // CHECK3-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
3482 // CHECK3-NEXT:    [[SUB27:%.*]] = sub nsw i32 [[TMP20]], 0
3483 // CHECK3-NEXT:    [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1
3484 // CHECK3-NEXT:    [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]]
3485 // CHECK3-NEXT:    [[CONV30:%.*]] = sext i32 [[MUL29]] to i64
3486 // CHECK3-NEXT:    [[MUL31:%.*]] = mul nsw i64 [[DIV26]], [[CONV30]]
3487 // CHECK3-NEXT:    [[SUB32:%.*]] = sub nsw i64 [[TMP17]], [[MUL31]]
3488 // CHECK3-NEXT:    [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 1
3489 // CHECK3-NEXT:    [[ADD34:%.*]] = add nsw i64 0, [[MUL33]]
3490 // CHECK3-NEXT:    [[CONV35:%.*]] = trunc i64 [[ADD34]] to i32
3491 // CHECK3-NEXT:    store i32 [[CONV35]], ptr [[J12]], align 4
3492 // CHECK3-NEXT:    [[TMP21:%.*]] = load i32, ptr [[I11]], align 4
3493 // CHECK3-NEXT:    [[TMP22:%.*]] = load i32, ptr [[J12]], align 4
3494 // CHECK3-NEXT:    [[ADD36:%.*]] = add nsw i32 [[TMP21]], [[TMP22]]
3495 // CHECK3-NEXT:    [[TMP23:%.*]] = load i32, ptr [[I11]], align 4
3496 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP0]], i32 0, i32 [[TMP23]]
3497 // CHECK3-NEXT:    [[TMP24:%.*]] = load i32, ptr [[J12]], align 4
3498 // CHECK3-NEXT:    [[ARRAYIDX37:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX]], i32 0, i32 [[TMP24]]
3499 // CHECK3-NEXT:    store i32 [[ADD36]], ptr [[ARRAYIDX37]], align 4
3500 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
3501 // CHECK3:       omp.body.continue:
3502 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
3503 // CHECK3:       omp.inner.for.inc:
3504 // CHECK3-NEXT:    [[TMP25:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
3505 // CHECK3-NEXT:    [[TMP26:%.*]] = load i64, ptr [[DOTOMP_STRIDE]], align 8
3506 // CHECK3-NEXT:    [[ADD38:%.*]] = add nsw i64 [[TMP25]], [[TMP26]]
3507 // CHECK3-NEXT:    store i64 [[ADD38]], ptr [[DOTOMP_IV]], align 8
3508 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]]
3509 // CHECK3:       omp.inner.for.end:
3510 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
3511 // CHECK3:       omp.loop.exit:
3512 // CHECK3-NEXT:    [[TMP27:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
3513 // CHECK3-NEXT:    [[TMP28:%.*]] = load i32, ptr [[TMP27]], align 4
3514 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP28]])
3515 // CHECK3-NEXT:    br label [[OMP_PRECOND_END]]
3516 // CHECK3:       omp.precond.end:
3517 // CHECK3-NEXT:    ret void
3518 //
3519 //
3520 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l53
3521 // CHECK3-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], ptr noundef [[V:%.*]]) #[[ATTR4]] {
3522 // CHECK3-NEXT:  entry:
3523 // CHECK3-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
3524 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
3525 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 4
3526 // CHECK3-NEXT:    [[V_ADDR:%.*]] = alloca ptr, align 4
3527 // CHECK3-NEXT:    [[N_CASTED:%.*]] = alloca i32, align 4
3528 // CHECK3-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
3529 // CHECK3-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
3530 // CHECK3-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
3531 // CHECK3-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
3532 // CHECK3-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 4
3533 // CHECK3-NEXT:    store ptr [[V]], ptr [[V_ADDR]], align 4
3534 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4
3535 // CHECK3-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l53_kernel_environment, ptr [[DYN_PTR]])
3536 // CHECK3-NEXT:    [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
3537 // CHECK3-NEXT:    br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
3538 // CHECK3:       user_code.entry:
3539 // CHECK3-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
3540 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4
3541 // CHECK3-NEXT:    store i32 [[TMP3]], ptr [[N_CASTED]], align 4
3542 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N_CASTED]], align 4
3543 // CHECK3-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[V_ADDR]], align 4
3544 // CHECK3-NEXT:    store i32 0, ptr [[DOTZERO_ADDR]], align 4
3545 // CHECK3-NEXT:    store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4
3546 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l53_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i32 [[TMP4]], ptr [[TMP0]], ptr [[TMP5]]) #[[ATTR2]]
3547 // CHECK3-NEXT:    call void @__kmpc_target_deinit()
3548 // CHECK3-NEXT:    ret void
3549 // CHECK3:       worker.exit:
3550 // CHECK3-NEXT:    ret void
3551 //
3552 //
3553 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l53_omp_outlined
3554 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], ptr noundef [[V:%.*]]) #[[ATTR1]] {
3555 // CHECK3-NEXT:  entry:
3556 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
3557 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
3558 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
3559 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 4
3560 // CHECK3-NEXT:    [[V_ADDR:%.*]] = alloca ptr, align 4
3561 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
3562 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
3563 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
3564 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
3565 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
3566 // CHECK3-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
3567 // CHECK3-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
3568 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3569 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3570 // CHECK3-NEXT:    [[I3:%.*]] = alloca i32, align 4
3571 // CHECK3-NEXT:    [[N_CASTED:%.*]] = alloca i32, align 4
3572 // CHECK3-NEXT:    [[CAPTURED_VARS_ADDRS:%.*]] = alloca [5 x ptr], align 4
3573 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
3574 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
3575 // CHECK3-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
3576 // CHECK3-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 4
3577 // CHECK3-NEXT:    store ptr [[V]], ptr [[V_ADDR]], align 4
3578 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4
3579 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
3580 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
3581 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
3582 // CHECK3-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
3583 // CHECK3-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1
3584 // CHECK3-NEXT:    [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
3585 // CHECK3-NEXT:    store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
3586 // CHECK3-NEXT:    store i32 0, ptr [[I]], align 4
3587 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
3588 // CHECK3-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]
3589 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
3590 // CHECK3:       omp.precond.then:
3591 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
3592 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
3593 // CHECK3-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_COMB_UB]], align 4
3594 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
3595 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
3596 // CHECK3-NEXT:    [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
3597 // CHECK3-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
3598 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
3599 // CHECK3-NEXT:    call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP6]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
3600 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
3601 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
3602 // CHECK3-NEXT:    [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]]
3603 // CHECK3-NEXT:    br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3604 // CHECK3:       cond.true:
3605 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
3606 // CHECK3-NEXT:    br label [[COND_END:%.*]]
3607 // CHECK3:       cond.false:
3608 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
3609 // CHECK3-NEXT:    br label [[COND_END]]
3610 // CHECK3:       cond.end:
3611 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
3612 // CHECK3-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
3613 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
3614 // CHECK3-NEXT:    store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 4
3615 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
3616 // CHECK3:       omp.inner.for.cond:
3617 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3618 // CHECK3-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
3619 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP13]], 1
3620 // CHECK3-NEXT:    [[CMP5:%.*]] = icmp slt i32 [[TMP12]], [[ADD]]
3621 // CHECK3-NEXT:    br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3622 // CHECK3:       omp.inner.for.body:
3623 // CHECK3-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
3624 // CHECK3-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
3625 // CHECK3-NEXT:    [[TMP16:%.*]] = load i32, ptr [[N_ADDR]], align 4
3626 // CHECK3-NEXT:    store i32 [[TMP16]], ptr [[N_CASTED]], align 4
3627 // CHECK3-NEXT:    [[TMP17:%.*]] = load i32, ptr [[N_CASTED]], align 4
3628 // CHECK3-NEXT:    [[TMP18:%.*]] = load ptr, ptr [[V_ADDR]], align 4
3629 // CHECK3-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
3630 // CHECK3-NEXT:    [[TMP20:%.*]] = inttoptr i32 [[TMP14]] to ptr
3631 // CHECK3-NEXT:    store ptr [[TMP20]], ptr [[TMP19]], align 4
3632 // CHECK3-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
3633 // CHECK3-NEXT:    [[TMP22:%.*]] = inttoptr i32 [[TMP15]] to ptr
3634 // CHECK3-NEXT:    store ptr [[TMP22]], ptr [[TMP21]], align 4
3635 // CHECK3-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 2
3636 // CHECK3-NEXT:    [[TMP24:%.*]] = inttoptr i32 [[TMP17]] to ptr
3637 // CHECK3-NEXT:    store ptr [[TMP24]], ptr [[TMP23]], align 4
3638 // CHECK3-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 3
3639 // CHECK3-NEXT:    store ptr [[TMP0]], ptr [[TMP25]], align 4
3640 // CHECK3-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 4
3641 // CHECK3-NEXT:    store ptr [[TMP18]], ptr [[TMP26]], align 4
3642 // CHECK3-NEXT:    [[TMP27:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
3643 // CHECK3-NEXT:    [[TMP28:%.*]] = load i32, ptr [[TMP27]], align 4
3644 // CHECK3-NEXT:    call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP28]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l53_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 5)
3645 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
3646 // CHECK3:       omp.inner.for.inc:
3647 // CHECK3-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3648 // CHECK3-NEXT:    [[TMP30:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
3649 // CHECK3-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP29]], [[TMP30]]
3650 // CHECK3-NEXT:    store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4
3651 // CHECK3-NEXT:    [[TMP31:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
3652 // CHECK3-NEXT:    [[TMP32:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
3653 // CHECK3-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP31]], [[TMP32]]
3654 // CHECK3-NEXT:    store i32 [[ADD7]], ptr [[DOTOMP_COMB_LB]], align 4
3655 // CHECK3-NEXT:    [[TMP33:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
3656 // CHECK3-NEXT:    [[TMP34:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
3657 // CHECK3-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP33]], [[TMP34]]
3658 // CHECK3-NEXT:    store i32 [[ADD8]], ptr [[DOTOMP_COMB_UB]], align 4
3659 // CHECK3-NEXT:    [[TMP35:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
3660 // CHECK3-NEXT:    [[TMP36:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
3661 // CHECK3-NEXT:    [[CMP9:%.*]] = icmp sgt i32 [[TMP35]], [[TMP36]]
3662 // CHECK3-NEXT:    br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]]
3663 // CHECK3:       cond.true10:
3664 // CHECK3-NEXT:    [[TMP37:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
3665 // CHECK3-NEXT:    br label [[COND_END12:%.*]]
3666 // CHECK3:       cond.false11:
3667 // CHECK3-NEXT:    [[TMP38:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
3668 // CHECK3-NEXT:    br label [[COND_END12]]
3669 // CHECK3:       cond.end12:
3670 // CHECK3-NEXT:    [[COND13:%.*]] = phi i32 [ [[TMP37]], [[COND_TRUE10]] ], [ [[TMP38]], [[COND_FALSE11]] ]
3671 // CHECK3-NEXT:    store i32 [[COND13]], ptr [[DOTOMP_COMB_UB]], align 4
3672 // CHECK3-NEXT:    [[TMP39:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
3673 // CHECK3-NEXT:    store i32 [[TMP39]], ptr [[DOTOMP_IV]], align 4
3674 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]]
3675 // CHECK3:       omp.inner.for.end:
3676 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
3677 // CHECK3:       omp.loop.exit:
3678 // CHECK3-NEXT:    [[TMP40:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
3679 // CHECK3-NEXT:    [[TMP41:%.*]] = load i32, ptr [[TMP40]], align 4
3680 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP41]])
3681 // CHECK3-NEXT:    br label [[OMP_PRECOND_END]]
3682 // CHECK3:       omp.precond.end:
3683 // CHECK3-NEXT:    ret void
3684 //
3685 //
3686 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l53_omp_outlined_omp_outlined
3687 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], ptr noundef [[V:%.*]]) #[[ATTR1]] {
3688 // CHECK3-NEXT:  entry:
3689 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
3690 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
3691 // CHECK3-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
3692 // CHECK3-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
3693 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
3694 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 4
3695 // CHECK3-NEXT:    [[V_ADDR:%.*]] = alloca ptr, align 4
3696 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
3697 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
3698 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
3699 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
3700 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
3701 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
3702 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
3703 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3704 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3705 // CHECK3-NEXT:    [[I3:%.*]] = alloca i32, align 4
3706 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
3707 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
3708 // CHECK3-NEXT:    store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4
3709 // CHECK3-NEXT:    store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
3710 // CHECK3-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
3711 // CHECK3-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 4
3712 // CHECK3-NEXT:    store ptr [[V]], ptr [[V_ADDR]], align 4
3713 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4
3714 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
3715 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
3716 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
3717 // CHECK3-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0
3718 // CHECK3-NEXT:    [[DIV:%.*]] = sdiv i32 [[SUB]], 1
3719 // CHECK3-NEXT:    [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
3720 // CHECK3-NEXT:    store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
3721 // CHECK3-NEXT:    store i32 0, ptr [[I]], align 4
3722 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
3723 // CHECK3-NEXT:    [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]
3724 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
3725 // CHECK3:       omp.precond.then:
3726 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
3727 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
3728 // CHECK3-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4
3729 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4
3730 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
3731 // CHECK3-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_LB]], align 4
3732 // CHECK3-NEXT:    store i32 [[TMP6]], ptr [[DOTOMP_UB]], align 4
3733 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
3734 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
3735 // CHECK3-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
3736 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
3737 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP8]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
3738 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
3739 // CHECK3-NEXT:    store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4
3740 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
3741 // CHECK3:       omp.inner.for.cond:
3742 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3743 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
3744 // CHECK3-NEXT:    [[CMP4:%.*]] = icmp ule i32 [[TMP10]], [[TMP11]]
3745 // CHECK3-NEXT:    br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3746 // CHECK3:       omp.inner.for.body:
3747 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3748 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
3749 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
3750 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[I3]], align 4
3751 // CHECK3-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[V_ADDR]], align 4
3752 // CHECK3-NEXT:    [[TMP14:%.*]] = load i32, ptr [[I3]], align 4
3753 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP13]], i32 [[TMP14]]
3754 // CHECK3-NEXT:    [[TMP15:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
3755 // CHECK3-NEXT:    [[TMP16:%.*]] = load i32, ptr [[I3]], align 4
3756 // CHECK3-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], i32 0, i32 [[TMP16]]
3757 // CHECK3-NEXT:    store i32 [[TMP15]], ptr [[ARRAYIDX5]], align 4
3758 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
3759 // CHECK3:       omp.body.continue:
3760 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
3761 // CHECK3:       omp.inner.for.inc:
3762 // CHECK3-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3763 // CHECK3-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
3764 // CHECK3-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP17]], [[TMP18]]
3765 // CHECK3-NEXT:    store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4
3766 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]]
3767 // CHECK3:       omp.inner.for.end:
3768 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
3769 // CHECK3:       omp.loop.exit:
3770 // CHECK3-NEXT:    [[TMP19:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
3771 // CHECK3-NEXT:    [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4
3772 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP20]])
3773 // CHECK3-NEXT:    br label [[OMP_PRECOND_END]]
3774 // CHECK3:       omp.precond.end:
3775 // CHECK3-NEXT:    ret void
3776 //