clang/test/OpenMP/nvptx_target_teams_ompx_bare_codegen.cpp

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
   2 // Test target codegen - host bc file has to be created first.
   3 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc
   4 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s
   5 // expected-no-diagnostics
   6 #ifndef HEADER
   7 #define HEADER
   8
   9 template<typename tx>
  10 tx ftemplate(int n) {
  11   tx a = 0;
  12
  13   #pragma omp target teams ompx_bare
  14   {
  15     a = 2;
  16   }
  17
  18   return a;
  19 }
  20
  21 int bar(int n){
  22   int a = 0;
  23
  24   a += ftemplate<char>(n);
  25
  26   return a;
  27 }
  28
  29 #endif
  30 // CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l13
  31 // CHECK-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0:[0-9]+]] {
  32 // CHECK-NEXT:  entry:
  33 // CHECK-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
  34 // CHECK-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
  35 // CHECK-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
  36 // CHECK-NEXT:    [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
  37 // CHECK-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
  38 // CHECK-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
  39 // CHECK-NEXT:    [[TMP0:%.*]] = load i8, ptr [[A_ADDR]], align 1
  40 // CHECK-NEXT:    store i8 [[TMP0]], ptr [[A_CASTED]], align 1
  41 // CHECK-NEXT:    [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8
  42 // CHECK-NEXT:    store i32 0, ptr [[DOTZERO_ADDR]], align 4
  43 // CHECK-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l13_omp_outlined(ptr null, ptr [[DOTZERO_ADDR]], i64 [[TMP1]]) #[[ATTR2:[0-9]+]]
  44 // CHECK-NEXT:    ret void
  45 //
  46 //
  47 // CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIcET_i_l13_omp_outlined
  48 // CHECK-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1:[0-9]+]] {
  49 // CHECK-NEXT:  entry:
  50 // CHECK-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
  51 // CHECK-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
  52 // CHECK-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
  53 // CHECK-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
  54 // CHECK-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
  55 // CHECK-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
  56 // CHECK-NEXT:    store i8 2, ptr [[A_ADDR]], align 1
  57 // CHECK-NEXT:    ret void
  58 //