clang/test/OpenMP/ordered_codegen.cpp

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
   2 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefixes=CHECK1
   3 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s
   4 // RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK1
   5
   6 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-enable-irbuilder -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefixes=CHECK1-IRBUILDER
   7 // RUN: %clang_cc1 -fopenmp -fopenmp-enable-irbuilder -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s
   8 // RUN: %clang_cc1 -fopenmp -fopenmp-enable-irbuilder -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK1-IRBUILDER
   9
  10 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -fopenmp-version=45 -o - | FileCheck %s --check-prefixes=CHECK3
  11 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -fopenmp-version=45 -o %t %s
  12 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK3
  13
  14 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-enable-irbuilder -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -fopenmp-version=45 -o - | FileCheck %s --check-prefixes=CHECK3-IRBUILDER
  15 // RUN: %clang_cc1 -fopenmp -fopenmp-enable-irbuilder -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -fopenmp-version=45 -o %t %s
  16 // RUN: %clang_cc1 -fopenmp -fopenmp-enable-irbuilder -fopenmp-version=45 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefixes=CHECK3-IRBUILDER
  17
  18 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK5
  19 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s
  20 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK5
  21 // expected-no-diagnostics
  22 #ifndef HEADER
  23 #define HEADER
  24
  25 void static_not_chunked(float *a, float *b, float *c, float *d) {
  26   #pragma omp for schedule(static) ordered
  27
  28 // Loop header
  29
  30   for (int i = 32000000; i > 33; i += -7) {
  31 // Start of body: calculate i from IV:
  32
  33 // ... start of ordered region ...
  34 // ... loop body ...
  35 // End of body: store into a[i]:
  36 // ... end of ordered region ...
  37     #pragma omp ordered
  38     a[i] = b[i] * c[i] * d[i];
  39   }
  40 }
  41
  42 void dynamic1(float *a, float *b, float *c, float *d) {
  43   #pragma omp for schedule(dynamic) ordered
  44
  45 // Loop header
  46
  47   for (unsigned long long i = 131071; i < 2147483647; i += 127) {
  48 // Start of body: calculate i from IV:
  49
  50 // ... start of ordered region ...
  51 // ... loop body ...
  52 // End of body: store into a[i]:
  53 // ... end of ordered region ...
  54     #pragma omp ordered threads
  55     a[i] = b[i] * c[i] * d[i];
  56
  57 // ... end iteration for ordered loop ...
  58   }
  59 }
  60
  61 void test_auto(float *a, float *b, float *c, float *d) {
  62   unsigned int x = 0;
  63   unsigned int y = 0;
  64   #pragma omp for schedule(auto) collapse(2) ordered
  65
  66 // Loop header
  67
  68 // FIXME: When the iteration count of some nested loop is not a known constant,
  69 // we should pre-calculate it, like we do for the total number of iterations!
  70   for (char i = static_cast<char>(y); i <= '9'; ++i)
  71     for (x = 11; x > 0; --x) {
  72 // Start of body: indices are calculated from IV:
  73
  74 // ... start of ordered region ...
  75 // ... loop body ...
  76 // End of body: store into a[i]:
  77 // ... end of ordered region ...
  78     #pragma omp ordered
  79     a[i] = b[i] * c[i] * d[i];
  80
  81 // ... end iteration for ordered loop ...
  82   }
  83 }
  84
  85 void runtime(float *a, float *b, float *c, float *d) {
  86   int x = 0;
  87   #pragma omp for collapse(2) schedule(runtime) ordered
  88
  89 // Loop header
  90
  91   for (unsigned char i = '0' ; i <= '9'; ++i)
  92     for (x = -10; x < 10; ++x) {
  93 // Start of body: indices are calculated from IV:
  94
  95 // ... start of ordered region ...
  96 // ... loop body ...
  97 // End of body: store into a[i]:
  98 // ... end of ordered region ...
  99     #pragma omp ordered threads
 100     a[i] = b[i] * c[i] * d[i];
 101
 102 // ... end iteration for ordered loop ...
 103   }
 104 }
 105
 106 float f[10];
 107 void foo_simd(int low, int up) {
 108 #pragma omp simd
 109   for (int i = low; i < up; ++i) {
 110     f[i] = 0.0;
 111 #pragma omp ordered simd
 112     f[i] = 1.0;
 113   }
 114 #pragma omp for simd ordered
 115   for (int i = low; i < up; ++i) {
 116     f[i] = 0.0;
 117 #pragma omp ordered simd
 118     f[i] = 1.0;
 119   }
 120 }
 121
 122
 123 #endif // HEADER
 124
 125 // CHECK1-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_
 126 // CHECK1-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] {
 127 // CHECK1-NEXT:  entry:
 128 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
 129 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
 130 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
 131 // CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
 132 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 133 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 134 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
 135 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
 136 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 137 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 138 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
 139 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
 140 // CHECK1-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
 141 // CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
 142 // CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
 143 // CHECK1-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
 144 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
 145 // CHECK1-NEXT:    store i32 4571423, ptr [[DOTOMP_UB]], align 4
 146 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 147 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 148 // CHECK1-NEXT:    call void @__kmpc_dispatch_init_4(ptr @[[GLOB1]], i32 [[TMP0]], i32 66, i32 0, i32 4571423, i32 1, i32 1)
 149 // CHECK1-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
 150 // CHECK1:       omp.dispatch.cond:
 151 // CHECK1-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
 152 // CHECK1-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0
 153 // CHECK1-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
 154 // CHECK1:       omp.dispatch.body:
 155 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
 156 // CHECK1-NEXT:    store i32 [[TMP2]], ptr [[DOTOMP_IV]], align 4
 157 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 158 // CHECK1:       omp.inner.for.cond:
 159 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 160 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 161 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP3]], [[TMP4]]
 162 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 163 // CHECK1:       omp.inner.for.body:
 164 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 165 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP5]], 7
 166 // CHECK1-NEXT:    [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
 167 // CHECK1-NEXT:    store i32 [[SUB]], ptr [[I]], align 4
 168 // CHECK1-NEXT:    call void @__kmpc_ordered(ptr @[[GLOB1]], i32 [[TMP0]])
 169 // CHECK1-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[B_ADDR]], align 8
 170 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[I]], align 4
 171 // CHECK1-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64
 172 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP6]], i64 [[IDXPROM]]
 173 // CHECK1-NEXT:    [[TMP8:%.*]] = load float, ptr [[ARRAYIDX]], align 4
 174 // CHECK1-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[C_ADDR]], align 8
 175 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[I]], align 4
 176 // CHECK1-NEXT:    [[IDXPROM1:%.*]] = sext i32 [[TMP10]] to i64
 177 // CHECK1-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[TMP9]], i64 [[IDXPROM1]]
 178 // CHECK1-NEXT:    [[TMP11:%.*]] = load float, ptr [[ARRAYIDX2]], align 4
 179 // CHECK1-NEXT:    [[MUL3:%.*]] = fmul float [[TMP8]], [[TMP11]]
 180 // CHECK1-NEXT:    [[TMP12:%.*]] = load ptr, ptr [[D_ADDR]], align 8
 181 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, ptr [[I]], align 4
 182 // CHECK1-NEXT:    [[IDXPROM4:%.*]] = sext i32 [[TMP13]] to i64
 183 // CHECK1-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds float, ptr [[TMP12]], i64 [[IDXPROM4]]
 184 // CHECK1-NEXT:    [[TMP14:%.*]] = load float, ptr [[ARRAYIDX5]], align 4
 185 // CHECK1-NEXT:    [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP14]]
 186 // CHECK1-NEXT:    [[TMP15:%.*]] = load ptr, ptr [[A_ADDR]], align 8
 187 // CHECK1-NEXT:    [[TMP16:%.*]] = load i32, ptr [[I]], align 4
 188 // CHECK1-NEXT:    [[IDXPROM7:%.*]] = sext i32 [[TMP16]] to i64
 189 // CHECK1-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds float, ptr [[TMP15]], i64 [[IDXPROM7]]
 190 // CHECK1-NEXT:    store float [[MUL6]], ptr [[ARRAYIDX8]], align 4
 191 // CHECK1-NEXT:    call void @__kmpc_end_ordered(ptr @[[GLOB1]], i32 [[TMP0]])
 192 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 193 // CHECK1:       omp.body.continue:
 194 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 195 // CHECK1:       omp.inner.for.inc:
 196 // CHECK1-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 197 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP17]], 1
 198 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
 199 // CHECK1-NEXT:    call void @__kmpc_dispatch_fini_4(ptr @[[GLOB1]], i32 [[TMP0]])
 200 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]
 201 // CHECK1:       omp.inner.for.end:
 202 // CHECK1-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
 203 // CHECK1:       omp.dispatch.inc:
 204 // CHECK1-NEXT:    br label [[OMP_DISPATCH_COND]]
 205 // CHECK1:       omp.dispatch.end:
 206 // CHECK1-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB2:[0-9]+]], i32 [[TMP0]])
 207 // CHECK1-NEXT:    ret void
 208 //
 209 //
 210 // CHECK1-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_
 211 // CHECK1-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
 212 // CHECK1-NEXT:  entry:
 213 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
 214 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
 215 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
 216 // CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
 217 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
 218 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i64, align 8
 219 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
 220 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
 221 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
 222 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 223 // CHECK1-NEXT:    [[I:%.*]] = alloca i64, align 8
 224 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
 225 // CHECK1-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
 226 // CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
 227 // CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
 228 // CHECK1-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
 229 // CHECK1-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8
 230 // CHECK1-NEXT:    store i64 16908287, ptr [[DOTOMP_UB]], align 8
 231 // CHECK1-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8
 232 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 233 // CHECK1-NEXT:    call void @__kmpc_dispatch_init_8u(ptr @[[GLOB1]], i32 [[TMP0]], i32 1073741891, i64 0, i64 16908287, i64 1, i64 1)
 234 // CHECK1-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
 235 // CHECK1:       omp.dispatch.cond:
 236 // CHECK1-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_dispatch_next_8u(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
 237 // CHECK1-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0
 238 // CHECK1-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
 239 // CHECK1:       omp.dispatch.body:
 240 // CHECK1-NEXT:    [[TMP2:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
 241 // CHECK1-NEXT:    store i64 [[TMP2]], ptr [[DOTOMP_IV]], align 8
 242 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 243 // CHECK1:       omp.inner.for.cond:
 244 // CHECK1-NEXT:    [[TMP3:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
 245 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
 246 // CHECK1-NEXT:    [[ADD:%.*]] = add i64 [[TMP4]], 1
 247 // CHECK1-NEXT:    [[CMP:%.*]] = icmp ult i64 [[TMP3]], [[ADD]]
 248 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 249 // CHECK1:       omp.inner.for.body:
 250 // CHECK1-NEXT:    [[TMP5:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
 251 // CHECK1-NEXT:    [[MUL:%.*]] = mul i64 [[TMP5]], 127
 252 // CHECK1-NEXT:    [[ADD1:%.*]] = add i64 131071, [[MUL]]
 253 // CHECK1-NEXT:    store i64 [[ADD1]], ptr [[I]], align 8
 254 // CHECK1-NEXT:    call void @__kmpc_ordered(ptr @[[GLOB1]], i32 [[TMP0]])
 255 // CHECK1-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[B_ADDR]], align 8
 256 // CHECK1-NEXT:    [[TMP7:%.*]] = load i64, ptr [[I]], align 8
 257 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP6]], i64 [[TMP7]]
 258 // CHECK1-NEXT:    [[TMP8:%.*]] = load float, ptr [[ARRAYIDX]], align 4
 259 // CHECK1-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[C_ADDR]], align 8
 260 // CHECK1-NEXT:    [[TMP10:%.*]] = load i64, ptr [[I]], align 8
 261 // CHECK1-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[TMP9]], i64 [[TMP10]]
 262 // CHECK1-NEXT:    [[TMP11:%.*]] = load float, ptr [[ARRAYIDX2]], align 4
 263 // CHECK1-NEXT:    [[MUL3:%.*]] = fmul float [[TMP8]], [[TMP11]]
 264 // CHECK1-NEXT:    [[TMP12:%.*]] = load ptr, ptr [[D_ADDR]], align 8
 265 // CHECK1-NEXT:    [[TMP13:%.*]] = load i64, ptr [[I]], align 8
 266 // CHECK1-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds float, ptr [[TMP12]], i64 [[TMP13]]
 267 // CHECK1-NEXT:    [[TMP14:%.*]] = load float, ptr [[ARRAYIDX4]], align 4
 268 // CHECK1-NEXT:    [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP14]]
 269 // CHECK1-NEXT:    [[TMP15:%.*]] = load ptr, ptr [[A_ADDR]], align 8
 270 // CHECK1-NEXT:    [[TMP16:%.*]] = load i64, ptr [[I]], align 8
 271 // CHECK1-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP15]], i64 [[TMP16]]
 272 // CHECK1-NEXT:    store float [[MUL5]], ptr [[ARRAYIDX6]], align 4
 273 // CHECK1-NEXT:    call void @__kmpc_end_ordered(ptr @[[GLOB1]], i32 [[TMP0]])
 274 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 275 // CHECK1:       omp.body.continue:
 276 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 277 // CHECK1:       omp.inner.for.inc:
 278 // CHECK1-NEXT:    [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
 279 // CHECK1-NEXT:    [[ADD7:%.*]] = add i64 [[TMP17]], 1
 280 // CHECK1-NEXT:    store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8
 281 // CHECK1-NEXT:    call void @__kmpc_dispatch_fini_8u(ptr @[[GLOB1]], i32 [[TMP0]])
 282 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]
 283 // CHECK1:       omp.inner.for.end:
 284 // CHECK1-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
 285 // CHECK1:       omp.dispatch.inc:
 286 // CHECK1-NEXT:    br label [[OMP_DISPATCH_COND]]
 287 // CHECK1:       omp.dispatch.end:
 288 // CHECK1-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB2]], i32 [[TMP0]])
 289 // CHECK1-NEXT:    ret void
 290 //
 291 //
 292 // CHECK1-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_
 293 // CHECK1-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
 294 // CHECK1-NEXT:  entry:
 295 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
 296 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
 297 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
 298 // CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
 299 // CHECK1-NEXT:    [[X:%.*]] = alloca i32, align 4
 300 // CHECK1-NEXT:    [[Y:%.*]] = alloca i32, align 4
 301 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
 302 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i8, align 1
 303 // CHECK1-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
 304 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
 305 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 8
 306 // CHECK1-NEXT:    [[I:%.*]] = alloca i8, align 1
 307 // CHECK1-NEXT:    [[X6:%.*]] = alloca i32, align 4
 308 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
 309 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
 310 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
 311 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 312 // CHECK1-NEXT:    [[I8:%.*]] = alloca i8, align 1
 313 // CHECK1-NEXT:    [[X9:%.*]] = alloca i32, align 4
 314 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
 315 // CHECK1-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
 316 // CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
 317 // CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
 318 // CHECK1-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
 319 // CHECK1-NEXT:    store i32 0, ptr [[X]], align 4
 320 // CHECK1-NEXT:    store i32 0, ptr [[Y]], align 4
 321 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[Y]], align 4
 322 // CHECK1-NEXT:    [[CONV:%.*]] = trunc i32 [[TMP1]] to i8
 323 // CHECK1-NEXT:    store i8 [[CONV]], ptr [[DOTCAPTURE_EXPR_]], align 1
 324 // CHECK1-NEXT:    [[TMP2:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
 325 // CHECK1-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP2]] to i32
 326 // CHECK1-NEXT:    [[SUB:%.*]] = sub i32 57, [[CONV3]]
 327 // CHECK1-NEXT:    [[ADD:%.*]] = add i32 [[SUB]], 1
 328 // CHECK1-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
 329 // CHECK1-NEXT:    [[CONV4:%.*]] = zext i32 [[DIV]] to i64
 330 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i64 [[CONV4]], 11
 331 // CHECK1-NEXT:    [[SUB5:%.*]] = sub nsw i64 [[MUL]], 1
 332 // CHECK1-NEXT:    store i64 [[SUB5]], ptr [[DOTCAPTURE_EXPR_2]], align 8
 333 // CHECK1-NEXT:    [[TMP3:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
 334 // CHECK1-NEXT:    store i8 [[TMP3]], ptr [[I]], align 1
 335 // CHECK1-NEXT:    store i32 11, ptr [[X6]], align 4
 336 // CHECK1-NEXT:    [[TMP4:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
 337 // CHECK1-NEXT:    [[CONV7:%.*]] = sext i8 [[TMP4]] to i32
 338 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sle i32 [[CONV7]], 57
 339 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
 340 // CHECK1:       omp.precond.then:
 341 // CHECK1-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8
 342 // CHECK1-NEXT:    [[TMP5:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_2]], align 8
 343 // CHECK1-NEXT:    store i64 [[TMP5]], ptr [[DOTOMP_UB]], align 8
 344 // CHECK1-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8
 345 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 346 // CHECK1-NEXT:    [[TMP6:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_2]], align 8
 347 // CHECK1-NEXT:    call void @__kmpc_dispatch_init_8(ptr @[[GLOB1]], i32 [[TMP0]], i32 1073741894, i64 0, i64 [[TMP6]], i64 1, i64 1)
 348 // CHECK1-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
 349 // CHECK1:       omp.dispatch.cond:
 350 // CHECK1-NEXT:    [[TMP7:%.*]] = call i32 @__kmpc_dispatch_next_8(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
 351 // CHECK1-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0
 352 // CHECK1-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
 353 // CHECK1:       omp.dispatch.body:
 354 // CHECK1-NEXT:    [[TMP8:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
 355 // CHECK1-NEXT:    store i64 [[TMP8]], ptr [[DOTOMP_IV]], align 8
 356 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 357 // CHECK1:       omp.inner.for.cond:
 358 // CHECK1-NEXT:    [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
 359 // CHECK1-NEXT:    [[TMP10:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
 360 // CHECK1-NEXT:    [[CMP10:%.*]] = icmp sle i64 [[TMP9]], [[TMP10]]
 361 // CHECK1-NEXT:    br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 362 // CHECK1:       omp.inner.for.body:
 363 // CHECK1-NEXT:    [[TMP11:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
 364 // CHECK1-NEXT:    [[CONV11:%.*]] = sext i8 [[TMP11]] to i64
 365 // CHECK1-NEXT:    [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
 366 // CHECK1-NEXT:    [[DIV12:%.*]] = sdiv i64 [[TMP12]], 11
 367 // CHECK1-NEXT:    [[MUL13:%.*]] = mul nsw i64 [[DIV12]], 1
 368 // CHECK1-NEXT:    [[ADD14:%.*]] = add nsw i64 [[CONV11]], [[MUL13]]
 369 // CHECK1-NEXT:    [[CONV15:%.*]] = trunc i64 [[ADD14]] to i8
 370 // CHECK1-NEXT:    store i8 [[CONV15]], ptr [[I8]], align 1
 371 // CHECK1-NEXT:    [[TMP13:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
 372 // CHECK1-NEXT:    [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
 373 // CHECK1-NEXT:    [[DIV16:%.*]] = sdiv i64 [[TMP14]], 11
 374 // CHECK1-NEXT:    [[MUL17:%.*]] = mul nsw i64 [[DIV16]], 11
 375 // CHECK1-NEXT:    [[SUB18:%.*]] = sub nsw i64 [[TMP13]], [[MUL17]]
 376 // CHECK1-NEXT:    [[MUL19:%.*]] = mul nsw i64 [[SUB18]], 1
 377 // CHECK1-NEXT:    [[SUB20:%.*]] = sub nsw i64 11, [[MUL19]]
 378 // CHECK1-NEXT:    [[CONV21:%.*]] = trunc i64 [[SUB20]] to i32
 379 // CHECK1-NEXT:    store i32 [[CONV21]], ptr [[X9]], align 4
 380 // CHECK1-NEXT:    call void @__kmpc_ordered(ptr @[[GLOB1]], i32 [[TMP0]])
 381 // CHECK1-NEXT:    [[TMP15:%.*]] = load ptr, ptr [[B_ADDR]], align 8
 382 // CHECK1-NEXT:    [[TMP16:%.*]] = load i8, ptr [[I8]], align 1
 383 // CHECK1-NEXT:    [[IDXPROM:%.*]] = sext i8 [[TMP16]] to i64
 384 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP15]], i64 [[IDXPROM]]
 385 // CHECK1-NEXT:    [[TMP17:%.*]] = load float, ptr [[ARRAYIDX]], align 4
 386 // CHECK1-NEXT:    [[TMP18:%.*]] = load ptr, ptr [[C_ADDR]], align 8
 387 // CHECK1-NEXT:    [[TMP19:%.*]] = load i8, ptr [[I8]], align 1
 388 // CHECK1-NEXT:    [[IDXPROM22:%.*]] = sext i8 [[TMP19]] to i64
 389 // CHECK1-NEXT:    [[ARRAYIDX23:%.*]] = getelementptr inbounds float, ptr [[TMP18]], i64 [[IDXPROM22]]
 390 // CHECK1-NEXT:    [[TMP20:%.*]] = load float, ptr [[ARRAYIDX23]], align 4
 391 // CHECK1-NEXT:    [[MUL24:%.*]] = fmul float [[TMP17]], [[TMP20]]
 392 // CHECK1-NEXT:    [[TMP21:%.*]] = load ptr, ptr [[D_ADDR]], align 8
 393 // CHECK1-NEXT:    [[TMP22:%.*]] = load i8, ptr [[I8]], align 1
 394 // CHECK1-NEXT:    [[IDXPROM25:%.*]] = sext i8 [[TMP22]] to i64
 395 // CHECK1-NEXT:    [[ARRAYIDX26:%.*]] = getelementptr inbounds float, ptr [[TMP21]], i64 [[IDXPROM25]]
 396 // CHECK1-NEXT:    [[TMP23:%.*]] = load float, ptr [[ARRAYIDX26]], align 4
 397 // CHECK1-NEXT:    [[MUL27:%.*]] = fmul float [[MUL24]], [[TMP23]]
 398 // CHECK1-NEXT:    [[TMP24:%.*]] = load ptr, ptr [[A_ADDR]], align 8
 399 // CHECK1-NEXT:    [[TMP25:%.*]] = load i8, ptr [[I8]], align 1
 400 // CHECK1-NEXT:    [[IDXPROM28:%.*]] = sext i8 [[TMP25]] to i64
 401 // CHECK1-NEXT:    [[ARRAYIDX29:%.*]] = getelementptr inbounds float, ptr [[TMP24]], i64 [[IDXPROM28]]
 402 // CHECK1-NEXT:    store float [[MUL27]], ptr [[ARRAYIDX29]], align 4
 403 // CHECK1-NEXT:    call void @__kmpc_end_ordered(ptr @[[GLOB1]], i32 [[TMP0]])
 404 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 405 // CHECK1:       omp.body.continue:
 406 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 407 // CHECK1:       omp.inner.for.inc:
 408 // CHECK1-NEXT:    [[TMP26:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
 409 // CHECK1-NEXT:    [[ADD30:%.*]] = add nsw i64 [[TMP26]], 1
 410 // CHECK1-NEXT:    store i64 [[ADD30]], ptr [[DOTOMP_IV]], align 8
 411 // CHECK1-NEXT:    call void @__kmpc_dispatch_fini_8(ptr @[[GLOB1]], i32 [[TMP0]])
 412 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]
 413 // CHECK1:       omp.inner.for.end:
 414 // CHECK1-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
 415 // CHECK1:       omp.dispatch.inc:
 416 // CHECK1-NEXT:    br label [[OMP_DISPATCH_COND]]
 417 // CHECK1:       omp.dispatch.end:
 418 // CHECK1-NEXT:    br label [[OMP_PRECOND_END]]
 419 // CHECK1:       omp.precond.end:
 420 // CHECK1-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB2]], i32 [[TMP0]])
 421 // CHECK1-NEXT:    ret void
 422 //
 423 //
 424 // CHECK1-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_
 425 // CHECK1-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
 426 // CHECK1-NEXT:  entry:
 427 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
 428 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
 429 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
 430 // CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
 431 // CHECK1-NEXT:    [[X:%.*]] = alloca i32, align 4
 432 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 433 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i8, align 1
 434 // CHECK1-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
 435 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
 436 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
 437 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 438 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 439 // CHECK1-NEXT:    [[I:%.*]] = alloca i8, align 1
 440 // CHECK1-NEXT:    [[X2:%.*]] = alloca i32, align 4
 441 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
 442 // CHECK1-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
 443 // CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
 444 // CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
 445 // CHECK1-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
 446 // CHECK1-NEXT:    store i32 0, ptr [[X]], align 4
 447 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
 448 // CHECK1-NEXT:    store i32 199, ptr [[DOTOMP_UB]], align 4
 449 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 450 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 451 // CHECK1-NEXT:    call void @__kmpc_dispatch_init_4(ptr @[[GLOB1]], i32 [[TMP0]], i32 1073741893, i32 0, i32 199, i32 1, i32 1)
 452 // CHECK1-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
 453 // CHECK1:       omp.dispatch.cond:
 454 // CHECK1-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
 455 // CHECK1-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0
 456 // CHECK1-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
 457 // CHECK1:       omp.dispatch.body:
 458 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
 459 // CHECK1-NEXT:    store i32 [[TMP2]], ptr [[DOTOMP_IV]], align 4
 460 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 461 // CHECK1:       omp.inner.for.cond:
 462 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 463 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 464 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP3]], [[TMP4]]
 465 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 466 // CHECK1:       omp.inner.for.body:
 467 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 468 // CHECK1-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP5]], 20
 469 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
 470 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 48, [[MUL]]
 471 // CHECK1-NEXT:    [[CONV:%.*]] = trunc i32 [[ADD]] to i8
 472 // CHECK1-NEXT:    store i8 [[CONV]], ptr [[I]], align 1
 473 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 474 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 475 // CHECK1-NEXT:    [[DIV3:%.*]] = sdiv i32 [[TMP7]], 20
 476 // CHECK1-NEXT:    [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 20
 477 // CHECK1-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP6]], [[MUL4]]
 478 // CHECK1-NEXT:    [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1
 479 // CHECK1-NEXT:    [[ADD6:%.*]] = add nsw i32 -10, [[MUL5]]
 480 // CHECK1-NEXT:    store i32 [[ADD6]], ptr [[X2]], align 4
 481 // CHECK1-NEXT:    call void @__kmpc_ordered(ptr @[[GLOB1]], i32 [[TMP0]])
 482 // CHECK1-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[B_ADDR]], align 8
 483 // CHECK1-NEXT:    [[TMP9:%.*]] = load i8, ptr [[I]], align 1
 484 // CHECK1-NEXT:    [[IDXPROM:%.*]] = zext i8 [[TMP9]] to i64
 485 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP8]], i64 [[IDXPROM]]
 486 // CHECK1-NEXT:    [[TMP10:%.*]] = load float, ptr [[ARRAYIDX]], align 4
 487 // CHECK1-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[C_ADDR]], align 8
 488 // CHECK1-NEXT:    [[TMP12:%.*]] = load i8, ptr [[I]], align 1
 489 // CHECK1-NEXT:    [[IDXPROM7:%.*]] = zext i8 [[TMP12]] to i64
 490 // CHECK1-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds float, ptr [[TMP11]], i64 [[IDXPROM7]]
 491 // CHECK1-NEXT:    [[TMP13:%.*]] = load float, ptr [[ARRAYIDX8]], align 4
 492 // CHECK1-NEXT:    [[MUL9:%.*]] = fmul float [[TMP10]], [[TMP13]]
 493 // CHECK1-NEXT:    [[TMP14:%.*]] = load ptr, ptr [[D_ADDR]], align 8
 494 // CHECK1-NEXT:    [[TMP15:%.*]] = load i8, ptr [[I]], align 1
 495 // CHECK1-NEXT:    [[IDXPROM10:%.*]] = zext i8 [[TMP15]] to i64
 496 // CHECK1-NEXT:    [[ARRAYIDX11:%.*]] = getelementptr inbounds float, ptr [[TMP14]], i64 [[IDXPROM10]]
 497 // CHECK1-NEXT:    [[TMP16:%.*]] = load float, ptr [[ARRAYIDX11]], align 4
 498 // CHECK1-NEXT:    [[MUL12:%.*]] = fmul float [[MUL9]], [[TMP16]]
 499 // CHECK1-NEXT:    [[TMP17:%.*]] = load ptr, ptr [[A_ADDR]], align 8
 500 // CHECK1-NEXT:    [[TMP18:%.*]] = load i8, ptr [[I]], align 1
 501 // CHECK1-NEXT:    [[IDXPROM13:%.*]] = zext i8 [[TMP18]] to i64
 502 // CHECK1-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds float, ptr [[TMP17]], i64 [[IDXPROM13]]
 503 // CHECK1-NEXT:    store float [[MUL12]], ptr [[ARRAYIDX14]], align 4
 504 // CHECK1-NEXT:    call void @__kmpc_end_ordered(ptr @[[GLOB1]], i32 [[TMP0]])
 505 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 506 // CHECK1:       omp.body.continue:
 507 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 508 // CHECK1:       omp.inner.for.inc:
 509 // CHECK1-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 510 // CHECK1-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP19]], 1
 511 // CHECK1-NEXT:    store i32 [[ADD15]], ptr [[DOTOMP_IV]], align 4
 512 // CHECK1-NEXT:    call void @__kmpc_dispatch_fini_4(ptr @[[GLOB1]], i32 [[TMP0]])
 513 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]
 514 // CHECK1:       omp.inner.for.end:
 515 // CHECK1-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
 516 // CHECK1:       omp.dispatch.inc:
 517 // CHECK1-NEXT:    br label [[OMP_DISPATCH_COND]]
 518 // CHECK1:       omp.dispatch.end:
 519 // CHECK1-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB2]], i32 [[TMP0]])
 520 // CHECK1-NEXT:    ret void
 521 //
 522 //
 523 // CHECK1-LABEL: define {{[^@]+}}@_Z8foo_simdii
 524 // CHECK1-SAME: (i32 noundef [[LOW:%.*]], i32 noundef [[UP:%.*]]) #[[ATTR3:[0-9]+]] {
 525 // CHECK1-NEXT:  entry:
 526 // CHECK1-NEXT:    [[LOW_ADDR:%.*]] = alloca i32, align 4
 527 // CHECK1-NEXT:    [[UP_ADDR:%.*]] = alloca i32, align 4
 528 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 529 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
 530 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
 531 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
 532 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
 533 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 534 // CHECK1-NEXT:    [[I5:%.*]] = alloca i32, align 4
 535 // CHECK1-NEXT:    [[DOTOMP_IV16:%.*]] = alloca i32, align 4
 536 // CHECK1-NEXT:    [[_TMP17:%.*]] = alloca i32, align 4
 537 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_18:%.*]] = alloca i32, align 4
 538 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_19:%.*]] = alloca i32, align 4
 539 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_20:%.*]] = alloca i32, align 4
 540 // CHECK1-NEXT:    [[I26:%.*]] = alloca i32, align 4
 541 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
 542 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
 543 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 544 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 545 // CHECK1-NEXT:    [[I28:%.*]] = alloca i32, align 4
 546 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
 547 // CHECK1-NEXT:    store i32 [[LOW]], ptr [[LOW_ADDR]], align 4
 548 // CHECK1-NEXT:    store i32 [[UP]], ptr [[UP_ADDR]], align 4
 549 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[LOW_ADDR]], align 4
 550 // CHECK1-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
 551 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[UP_ADDR]], align 4
 552 // CHECK1-NEXT:    store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
 553 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
 554 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
 555 // CHECK1-NEXT:    [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
 556 // CHECK1-NEXT:    [[SUB3:%.*]] = sub i32 [[SUB]], 1
 557 // CHECK1-NEXT:    [[ADD:%.*]] = add i32 [[SUB3]], 1
 558 // CHECK1-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
 559 // CHECK1-NEXT:    [[SUB4:%.*]] = sub i32 [[DIV]], 1
 560 // CHECK1-NEXT:    store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 4
 561 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
 562 // CHECK1-NEXT:    store i32 [[TMP5]], ptr [[I]], align 4
 563 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
 564 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
 565 // CHECK1-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
 566 // CHECK1-NEXT:    br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]
 567 // CHECK1:       simd.if.then:
 568 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IV]], align 4
 569 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 570 // CHECK1:       omp.inner.for.cond:
 571 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3:![0-9]+]]
 572 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group [[ACC_GRP3]]
 573 // CHECK1-NEXT:    [[ADD6:%.*]] = add i32 [[TMP9]], 1
 574 // CHECK1-NEXT:    [[CMP7:%.*]] = icmp ult i32 [[TMP8]], [[ADD6]]
 575 // CHECK1-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 576 // CHECK1:       omp.inner.for.body:
 577 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group [[ACC_GRP3]]
 578 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]
 579 // CHECK1-NEXT:    [[MUL:%.*]] = mul i32 [[TMP11]], 1
 580 // CHECK1-NEXT:    [[ADD8:%.*]] = add i32 [[TMP10]], [[MUL]]
 581 // CHECK1-NEXT:    store i32 [[ADD8]], ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP3]]
 582 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP3]]
 583 // CHECK1-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64
 584 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM]]
 585 // CHECK1-NEXT:    store float 0.000000e+00, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]]
 586 // CHECK1-NEXT:    call void @__captured_stmt(ptr [[I5]]), !llvm.access.group [[ACC_GRP3]]
 587 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 588 // CHECK1:       omp.body.continue:
 589 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 590 // CHECK1:       omp.inner.for.inc:
 591 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]
 592 // CHECK1-NEXT:    [[ADD9:%.*]] = add i32 [[TMP13]], 1
 593 // CHECK1-NEXT:    store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]
 594 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
 595 // CHECK1:       omp.inner.for.end:
 596 // CHECK1-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
 597 // CHECK1-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
 598 // CHECK1-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
 599 // CHECK1-NEXT:    [[SUB10:%.*]] = sub i32 [[TMP15]], [[TMP16]]
 600 // CHECK1-NEXT:    [[SUB11:%.*]] = sub i32 [[SUB10]], 1
 601 // CHECK1-NEXT:    [[ADD12:%.*]] = add i32 [[SUB11]], 1
 602 // CHECK1-NEXT:    [[DIV13:%.*]] = udiv i32 [[ADD12]], 1
 603 // CHECK1-NEXT:    [[MUL14:%.*]] = mul i32 [[DIV13]], 1
 604 // CHECK1-NEXT:    [[ADD15:%.*]] = add i32 [[TMP14]], [[MUL14]]
 605 // CHECK1-NEXT:    store i32 [[ADD15]], ptr [[I5]], align 4
 606 // CHECK1-NEXT:    br label [[SIMD_IF_END]]
 607 // CHECK1:       simd.if.end:
 608 // CHECK1-NEXT:    [[TMP17:%.*]] = load i32, ptr [[LOW_ADDR]], align 4
 609 // CHECK1-NEXT:    store i32 [[TMP17]], ptr [[DOTCAPTURE_EXPR_18]], align 4
 610 // CHECK1-NEXT:    [[TMP18:%.*]] = load i32, ptr [[UP_ADDR]], align 4
 611 // CHECK1-NEXT:    store i32 [[TMP18]], ptr [[DOTCAPTURE_EXPR_19]], align 4
 612 // CHECK1-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_19]], align 4
 613 // CHECK1-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 4
 614 // CHECK1-NEXT:    [[SUB21:%.*]] = sub i32 [[TMP19]], [[TMP20]]
 615 // CHECK1-NEXT:    [[SUB22:%.*]] = sub i32 [[SUB21]], 1
 616 // CHECK1-NEXT:    [[ADD23:%.*]] = add i32 [[SUB22]], 1
 617 // CHECK1-NEXT:    [[DIV24:%.*]] = udiv i32 [[ADD23]], 1
 618 // CHECK1-NEXT:    [[SUB25:%.*]] = sub i32 [[DIV24]], 1
 619 // CHECK1-NEXT:    store i32 [[SUB25]], ptr [[DOTCAPTURE_EXPR_20]], align 4
 620 // CHECK1-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 4
 621 // CHECK1-NEXT:    store i32 [[TMP21]], ptr [[I26]], align 4
 622 // CHECK1-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 4
 623 // CHECK1-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_19]], align 4
 624 // CHECK1-NEXT:    [[CMP27:%.*]] = icmp slt i32 [[TMP22]], [[TMP23]]
 625 // CHECK1-NEXT:    br i1 [[CMP27]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
 626 // CHECK1:       omp.precond.then:
 627 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
 628 // CHECK1-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_20]], align 4
 629 // CHECK1-NEXT:    store i32 [[TMP24]], ptr [[DOTOMP_UB]], align 4
 630 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 631 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 632 // CHECK1-NEXT:    [[TMP25:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_20]], align 4
 633 // CHECK1-NEXT:    call void @__kmpc_dispatch_init_4u(ptr @[[GLOB1]], i32 [[TMP0]], i32 66, i32 0, i32 [[TMP25]], i32 1, i32 1)
 634 // CHECK1-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
 635 // CHECK1:       omp.dispatch.cond:
 636 // CHECK1-NEXT:    [[TMP26:%.*]] = call i32 @__kmpc_dispatch_next_4u(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
 637 // CHECK1-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP26]], 0
 638 // CHECK1-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
 639 // CHECK1:       omp.dispatch.body:
 640 // CHECK1-NEXT:    [[TMP27:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
 641 // CHECK1-NEXT:    store i32 [[TMP27]], ptr [[DOTOMP_IV16]], align 4
 642 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND29:%.*]]
 643 // CHECK1:       omp.inner.for.cond29:
 644 // CHECK1-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTOMP_IV16]], align 4, !llvm.access.group [[ACC_GRP7:![0-9]+]]
 645 // CHECK1-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP7]]
 646 // CHECK1-NEXT:    [[ADD30:%.*]] = add i32 [[TMP29]], 1
 647 // CHECK1-NEXT:    [[CMP31:%.*]] = icmp ult i32 [[TMP28]], [[ADD30]]
 648 // CHECK1-NEXT:    br i1 [[CMP31]], label [[OMP_INNER_FOR_BODY32:%.*]], label [[OMP_INNER_FOR_END40:%.*]]
 649 // CHECK1:       omp.inner.for.body32:
 650 // CHECK1-NEXT:    [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 4, !llvm.access.group [[ACC_GRP7]]
 651 // CHECK1-NEXT:    [[TMP31:%.*]] = load i32, ptr [[DOTOMP_IV16]], align 4, !llvm.access.group [[ACC_GRP7]]
 652 // CHECK1-NEXT:    [[MUL33:%.*]] = mul i32 [[TMP31]], 1
 653 // CHECK1-NEXT:    [[ADD34:%.*]] = add i32 [[TMP30]], [[MUL33]]
 654 // CHECK1-NEXT:    store i32 [[ADD34]], ptr [[I28]], align 4, !llvm.access.group [[ACC_GRP7]]
 655 // CHECK1-NEXT:    [[TMP32:%.*]] = load i32, ptr [[I28]], align 4, !llvm.access.group [[ACC_GRP7]]
 656 // CHECK1-NEXT:    [[IDXPROM35:%.*]] = sext i32 [[TMP32]] to i64
 657 // CHECK1-NEXT:    [[ARRAYIDX36:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM35]]
 658 // CHECK1-NEXT:    store float 0.000000e+00, ptr [[ARRAYIDX36]], align 4, !llvm.access.group [[ACC_GRP7]]
 659 // CHECK1-NEXT:    call void @__captured_stmt.1(ptr [[I28]]), !llvm.access.group [[ACC_GRP7]]
 660 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE37:%.*]]
 661 // CHECK1:       omp.body.continue37:
 662 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC38:%.*]]
 663 // CHECK1:       omp.inner.for.inc38:
 664 // CHECK1-NEXT:    [[TMP33:%.*]] = load i32, ptr [[DOTOMP_IV16]], align 4, !llvm.access.group [[ACC_GRP7]]
 665 // CHECK1-NEXT:    [[ADD39:%.*]] = add i32 [[TMP33]], 1
 666 // CHECK1-NEXT:    store i32 [[ADD39]], ptr [[DOTOMP_IV16]], align 4, !llvm.access.group [[ACC_GRP7]]
 667 // CHECK1-NEXT:    call void @__kmpc_dispatch_fini_4u(ptr @[[GLOB1]], i32 [[TMP0]]), !llvm.access.group [[ACC_GRP7]]
 668 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND29]], !llvm.loop [[LOOP8:![0-9]+]]
 669 // CHECK1:       omp.inner.for.end40:
 670 // CHECK1-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
 671 // CHECK1:       omp.dispatch.inc:
 672 // CHECK1-NEXT:    br label [[OMP_DISPATCH_COND]]
 673 // CHECK1:       omp.dispatch.end:
 674 // CHECK1-NEXT:    [[TMP34:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
 675 // CHECK1-NEXT:    [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0
 676 // CHECK1-NEXT:    br i1 [[TMP35]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
 677 // CHECK1:       .omp.final.then:
 678 // CHECK1-NEXT:    [[TMP36:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 4
 679 // CHECK1-NEXT:    [[TMP37:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_19]], align 4
 680 // CHECK1-NEXT:    [[TMP38:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 4
 681 // CHECK1-NEXT:    [[SUB41:%.*]] = sub i32 [[TMP37]], [[TMP38]]
 682 // CHECK1-NEXT:    [[SUB42:%.*]] = sub i32 [[SUB41]], 1
 683 // CHECK1-NEXT:    [[ADD43:%.*]] = add i32 [[SUB42]], 1
 684 // CHECK1-NEXT:    [[DIV44:%.*]] = udiv i32 [[ADD43]], 1
 685 // CHECK1-NEXT:    [[MUL45:%.*]] = mul i32 [[DIV44]], 1
 686 // CHECK1-NEXT:    [[ADD46:%.*]] = add i32 [[TMP36]], [[MUL45]]
 687 // CHECK1-NEXT:    store i32 [[ADD46]], ptr [[I28]], align 4
 688 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
 689 // CHECK1:       .omp.final.done:
 690 // CHECK1-NEXT:    br label [[OMP_PRECOND_END]]
 691 // CHECK1:       omp.precond.end:
 692 // CHECK1-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB2]], i32 [[TMP0]])
 693 // CHECK1-NEXT:    ret void
 694 //
 695 //
 696 // CHECK1-LABEL: define {{[^@]+}}@__captured_stmt
 697 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR4:[0-9]+]] {
 698 // CHECK1-NEXT:  entry:
 699 // CHECK1-NEXT:    [[I_ADDR:%.*]] = alloca ptr, align 8
 700 // CHECK1-NEXT:    store ptr [[I]], ptr [[I_ADDR]], align 8
 701 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 8
 702 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
 703 // CHECK1-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64
 704 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM]]
 705 // CHECK1-NEXT:    store float 1.000000e+00, ptr [[ARRAYIDX]], align 4
 706 // CHECK1-NEXT:    ret void
 707 //
 708 //
 709 // CHECK1-LABEL: define {{[^@]+}}@__captured_stmt.1
 710 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR4]] {
 711 // CHECK1-NEXT:  entry:
 712 // CHECK1-NEXT:    [[I_ADDR:%.*]] = alloca ptr, align 8
 713 // CHECK1-NEXT:    store ptr [[I]], ptr [[I_ADDR]], align 8
 714 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 8
 715 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
 716 // CHECK1-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64
 717 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM]]
 718 // CHECK1-NEXT:    store float 1.000000e+00, ptr [[ARRAYIDX]], align 4
 719 // CHECK1-NEXT:    ret void
 720 //
 721 //
 722 // CHECK1-IRBUILDER-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_
 723 // CHECK1-IRBUILDER-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] {
 724 // CHECK1-IRBUILDER-NEXT:  entry:
 725 // CHECK1-IRBUILDER-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
 726 // CHECK1-IRBUILDER-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
 727 // CHECK1-IRBUILDER-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
 728 // CHECK1-IRBUILDER-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
 729 // CHECK1-IRBUILDER-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 730 // CHECK1-IRBUILDER-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 731 // CHECK1-IRBUILDER-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
 732 // CHECK1-IRBUILDER-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
 733 // CHECK1-IRBUILDER-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 734 // CHECK1-IRBUILDER-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 735 // CHECK1-IRBUILDER-NEXT:    [[I:%.*]] = alloca i32, align 4
 736 // CHECK1-IRBUILDER-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
 737 // CHECK1-IRBUILDER-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
 738 // CHECK1-IRBUILDER-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
 739 // CHECK1-IRBUILDER-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
 740 // CHECK1-IRBUILDER-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
 741 // CHECK1-IRBUILDER-NEXT:    store i32 4571423, ptr [[DOTOMP_UB]], align 4
 742 // CHECK1-IRBUILDER-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 743 // CHECK1-IRBUILDER-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 744 // CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3:[0-9]+]])
 745 // CHECK1-IRBUILDER-NEXT:    call void @__kmpc_dispatch_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 66, i32 0, i32 4571423, i32 1, i32 1)
 746 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
 747 // CHECK1-IRBUILDER:       omp.dispatch.cond:
 748 // CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3]])
 749 // CHECK1-IRBUILDER-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM1]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
 750 // CHECK1-IRBUILDER-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
 751 // CHECK1-IRBUILDER-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
 752 // CHECK1-IRBUILDER:       omp.dispatch.body:
 753 // CHECK1-IRBUILDER-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
 754 // CHECK1-IRBUILDER-NEXT:    store i32 [[TMP1]], ptr [[DOTOMP_IV]], align 4
 755 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 756 // CHECK1-IRBUILDER:       omp.inner.for.cond:
 757 // CHECK1-IRBUILDER-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 758 // CHECK1-IRBUILDER-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 759 // CHECK1-IRBUILDER-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]]
 760 // CHECK1-IRBUILDER-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 761 // CHECK1-IRBUILDER:       omp.inner.for.body:
 762 // CHECK1-IRBUILDER-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 763 // CHECK1-IRBUILDER-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP4]], 7
 764 // CHECK1-IRBUILDER-NEXT:    [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
 765 // CHECK1-IRBUILDER-NEXT:    store i32 [[SUB]], ptr [[I]], align 4
 766 // CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
 767 // CHECK1-IRBUILDER-NEXT:    call void @__kmpc_ordered(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM2]])
 768 // CHECK1-IRBUILDER-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[B_ADDR]], align 8
 769 // CHECK1-IRBUILDER-NEXT:    [[TMP6:%.*]] = load i32, ptr [[I]], align 4
 770 // CHECK1-IRBUILDER-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64
 771 // CHECK1-IRBUILDER-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP5]], i64 [[IDXPROM]]
 772 // CHECK1-IRBUILDER-NEXT:    [[TMP7:%.*]] = load float, ptr [[ARRAYIDX]], align 4
 773 // CHECK1-IRBUILDER-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[C_ADDR]], align 8
 774 // CHECK1-IRBUILDER-NEXT:    [[TMP9:%.*]] = load i32, ptr [[I]], align 4
 775 // CHECK1-IRBUILDER-NEXT:    [[IDXPROM3:%.*]] = sext i32 [[TMP9]] to i64
 776 // CHECK1-IRBUILDER-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds float, ptr [[TMP8]], i64 [[IDXPROM3]]
 777 // CHECK1-IRBUILDER-NEXT:    [[TMP10:%.*]] = load float, ptr [[ARRAYIDX4]], align 4
 778 // CHECK1-IRBUILDER-NEXT:    [[MUL5:%.*]] = fmul float [[TMP7]], [[TMP10]]
 779 // CHECK1-IRBUILDER-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[D_ADDR]], align 8
 780 // CHECK1-IRBUILDER-NEXT:    [[TMP12:%.*]] = load i32, ptr [[I]], align 4
 781 // CHECK1-IRBUILDER-NEXT:    [[IDXPROM6:%.*]] = sext i32 [[TMP12]] to i64
 782 // CHECK1-IRBUILDER-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds float, ptr [[TMP11]], i64 [[IDXPROM6]]
 783 // CHECK1-IRBUILDER-NEXT:    [[TMP13:%.*]] = load float, ptr [[ARRAYIDX7]], align 4
 784 // CHECK1-IRBUILDER-NEXT:    [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP13]]
 785 // CHECK1-IRBUILDER-NEXT:    [[TMP14:%.*]] = load ptr, ptr [[A_ADDR]], align 8
 786 // CHECK1-IRBUILDER-NEXT:    [[TMP15:%.*]] = load i32, ptr [[I]], align 4
 787 // CHECK1-IRBUILDER-NEXT:    [[IDXPROM9:%.*]] = sext i32 [[TMP15]] to i64
 788 // CHECK1-IRBUILDER-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP14]], i64 [[IDXPROM9]]
 789 // CHECK1-IRBUILDER-NEXT:    store float [[MUL8]], ptr [[ARRAYIDX10]], align 4
 790 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_BODY_ORDERED_AFTER:%.*]]
 791 // CHECK1-IRBUILDER:       omp.inner.for.body.ordered.after:
 792 // CHECK1-IRBUILDER-NEXT:    call void @__kmpc_end_ordered(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM2]])
 793 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 794 // CHECK1-IRBUILDER:       omp.body.continue:
 795 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 796 // CHECK1-IRBUILDER:       omp.inner.for.inc:
 797 // CHECK1-IRBUILDER-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 798 // CHECK1-IRBUILDER-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP16]], 1
 799 // CHECK1-IRBUILDER-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
 800 // CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM11:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3]])
 801 // CHECK1-IRBUILDER-NEXT:    call void @__kmpc_dispatch_fini_4(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM11]])
 802 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND]]
 803 // CHECK1-IRBUILDER:       omp.inner.for.end:
 804 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
 805 // CHECK1-IRBUILDER:       omp.dispatch.inc:
 806 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_COND]]
 807 // CHECK1-IRBUILDER:       omp.dispatch.end:
 808 // CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM12:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
 809 // CHECK1-IRBUILDER-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB4:[0-9]+]], i32 [[OMP_GLOBAL_THREAD_NUM12]])
 810 // CHECK1-IRBUILDER-NEXT:    ret void
 811 //
 812 //
 813 // CHECK1-IRBUILDER-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_
 814 // CHECK1-IRBUILDER-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
 815 // CHECK1-IRBUILDER-NEXT:  entry:
 816 // CHECK1-IRBUILDER-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
 817 // CHECK1-IRBUILDER-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
 818 // CHECK1-IRBUILDER-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
 819 // CHECK1-IRBUILDER-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
 820 // CHECK1-IRBUILDER-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
 821 // CHECK1-IRBUILDER-NEXT:    [[TMP:%.*]] = alloca i64, align 8
 822 // CHECK1-IRBUILDER-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
 823 // CHECK1-IRBUILDER-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
 824 // CHECK1-IRBUILDER-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
 825 // CHECK1-IRBUILDER-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 826 // CHECK1-IRBUILDER-NEXT:    [[I:%.*]] = alloca i64, align 8
 827 // CHECK1-IRBUILDER-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
 828 // CHECK1-IRBUILDER-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
 829 // CHECK1-IRBUILDER-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
 830 // CHECK1-IRBUILDER-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
 831 // CHECK1-IRBUILDER-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8
 832 // CHECK1-IRBUILDER-NEXT:    store i64 16908287, ptr [[DOTOMP_UB]], align 8
 833 // CHECK1-IRBUILDER-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8
 834 // CHECK1-IRBUILDER-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 835 // CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB6:[0-9]+]])
 836 // CHECK1-IRBUILDER-NEXT:    call void @__kmpc_dispatch_init_8u(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 1073741891, i64 0, i64 16908287, i64 1, i64 1)
 837 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
 838 // CHECK1-IRBUILDER:       omp.dispatch.cond:
 839 // CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB6]])
 840 // CHECK1-IRBUILDER-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_dispatch_next_8u(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM1]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
 841 // CHECK1-IRBUILDER-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
 842 // CHECK1-IRBUILDER-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
 843 // CHECK1-IRBUILDER:       omp.dispatch.body:
 844 // CHECK1-IRBUILDER-NEXT:    [[TMP1:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
 845 // CHECK1-IRBUILDER-NEXT:    store i64 [[TMP1]], ptr [[DOTOMP_IV]], align 8
 846 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 847 // CHECK1-IRBUILDER:       omp.inner.for.cond:
 848 // CHECK1-IRBUILDER-NEXT:    [[TMP2:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
 849 // CHECK1-IRBUILDER-NEXT:    [[TMP3:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
 850 // CHECK1-IRBUILDER-NEXT:    [[ADD:%.*]] = add i64 [[TMP3]], 1
 851 // CHECK1-IRBUILDER-NEXT:    [[CMP:%.*]] = icmp ult i64 [[TMP2]], [[ADD]]
 852 // CHECK1-IRBUILDER-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 853 // CHECK1-IRBUILDER:       omp.inner.for.body:
 854 // CHECK1-IRBUILDER-NEXT:    [[TMP4:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
 855 // CHECK1-IRBUILDER-NEXT:    [[MUL:%.*]] = mul i64 [[TMP4]], 127
 856 // CHECK1-IRBUILDER-NEXT:    [[ADD2:%.*]] = add i64 131071, [[MUL]]
 857 // CHECK1-IRBUILDER-NEXT:    store i64 [[ADD2]], ptr [[I]], align 8
 858 // CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM3:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
 859 // CHECK1-IRBUILDER-NEXT:    call void @__kmpc_ordered(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM3]])
 860 // CHECK1-IRBUILDER-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[B_ADDR]], align 8
 861 // CHECK1-IRBUILDER-NEXT:    [[TMP6:%.*]] = load i64, ptr [[I]], align 8
 862 // CHECK1-IRBUILDER-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP5]], i64 [[TMP6]]
 863 // CHECK1-IRBUILDER-NEXT:    [[TMP7:%.*]] = load float, ptr [[ARRAYIDX]], align 4
 864 // CHECK1-IRBUILDER-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[C_ADDR]], align 8
 865 // CHECK1-IRBUILDER-NEXT:    [[TMP9:%.*]] = load i64, ptr [[I]], align 8
 866 // CHECK1-IRBUILDER-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds float, ptr [[TMP8]], i64 [[TMP9]]
 867 // CHECK1-IRBUILDER-NEXT:    [[TMP10:%.*]] = load float, ptr [[ARRAYIDX4]], align 4
 868 // CHECK1-IRBUILDER-NEXT:    [[MUL5:%.*]] = fmul float [[TMP7]], [[TMP10]]
 869 // CHECK1-IRBUILDER-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[D_ADDR]], align 8
 870 // CHECK1-IRBUILDER-NEXT:    [[TMP12:%.*]] = load i64, ptr [[I]], align 8
 871 // CHECK1-IRBUILDER-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP11]], i64 [[TMP12]]
 872 // CHECK1-IRBUILDER-NEXT:    [[TMP13:%.*]] = load float, ptr [[ARRAYIDX6]], align 4
 873 // CHECK1-IRBUILDER-NEXT:    [[MUL7:%.*]] = fmul float [[MUL5]], [[TMP13]]
 874 // CHECK1-IRBUILDER-NEXT:    [[TMP14:%.*]] = load ptr, ptr [[A_ADDR]], align 8
 875 // CHECK1-IRBUILDER-NEXT:    [[TMP15:%.*]] = load i64, ptr [[I]], align 8
 876 // CHECK1-IRBUILDER-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds float, ptr [[TMP14]], i64 [[TMP15]]
 877 // CHECK1-IRBUILDER-NEXT:    store float [[MUL7]], ptr [[ARRAYIDX8]], align 4
 878 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_BODY_ORDERED_AFTER:%.*]]
 879 // CHECK1-IRBUILDER:       omp.inner.for.body.ordered.after:
 880 // CHECK1-IRBUILDER-NEXT:    call void @__kmpc_end_ordered(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM3]])
 881 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 882 // CHECK1-IRBUILDER:       omp.body.continue:
 883 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 884 // CHECK1-IRBUILDER:       omp.inner.for.inc:
 885 // CHECK1-IRBUILDER-NEXT:    [[TMP16:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
 886 // CHECK1-IRBUILDER-NEXT:    [[ADD9:%.*]] = add i64 [[TMP16]], 1
 887 // CHECK1-IRBUILDER-NEXT:    store i64 [[ADD9]], ptr [[DOTOMP_IV]], align 8
 888 // CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM10:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB6]])
 889 // CHECK1-IRBUILDER-NEXT:    call void @__kmpc_dispatch_fini_8u(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM10]])
 890 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND]]
 891 // CHECK1-IRBUILDER:       omp.inner.for.end:
 892 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
 893 // CHECK1-IRBUILDER:       omp.dispatch.inc:
 894 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_COND]]
 895 // CHECK1-IRBUILDER:       omp.dispatch.end:
 896 // CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM11:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
 897 // CHECK1-IRBUILDER-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[OMP_GLOBAL_THREAD_NUM11]])
 898 // CHECK1-IRBUILDER-NEXT:    ret void
 899 //
 900 //
 901 // CHECK1-IRBUILDER-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_
 902 // CHECK1-IRBUILDER-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
 903 // CHECK1-IRBUILDER-NEXT:  entry:
 904 // CHECK1-IRBUILDER-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
 905 // CHECK1-IRBUILDER-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
 906 // CHECK1-IRBUILDER-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
 907 // CHECK1-IRBUILDER-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
 908 // CHECK1-IRBUILDER-NEXT:    [[X:%.*]] = alloca i32, align 4
 909 // CHECK1-IRBUILDER-NEXT:    [[Y:%.*]] = alloca i32, align 4
 910 // CHECK1-IRBUILDER-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
 911 // CHECK1-IRBUILDER-NEXT:    [[TMP:%.*]] = alloca i8, align 1
 912 // CHECK1-IRBUILDER-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
 913 // CHECK1-IRBUILDER-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
 914 // CHECK1-IRBUILDER-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 8
 915 // CHECK1-IRBUILDER-NEXT:    [[I:%.*]] = alloca i8, align 1
 916 // CHECK1-IRBUILDER-NEXT:    [[X6:%.*]] = alloca i32, align 4
 917 // CHECK1-IRBUILDER-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
 918 // CHECK1-IRBUILDER-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
 919 // CHECK1-IRBUILDER-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
 920 // CHECK1-IRBUILDER-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 921 // CHECK1-IRBUILDER-NEXT:    [[I8:%.*]] = alloca i8, align 1
 922 // CHECK1-IRBUILDER-NEXT:    [[X9:%.*]] = alloca i32, align 4
 923 // CHECK1-IRBUILDER-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
 924 // CHECK1-IRBUILDER-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
 925 // CHECK1-IRBUILDER-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
 926 // CHECK1-IRBUILDER-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
 927 // CHECK1-IRBUILDER-NEXT:    store i32 0, ptr [[X]], align 4
 928 // CHECK1-IRBUILDER-NEXT:    store i32 0, ptr [[Y]], align 4
 929 // CHECK1-IRBUILDER-NEXT:    [[TMP0:%.*]] = load i32, ptr [[Y]], align 4
 930 // CHECK1-IRBUILDER-NEXT:    [[CONV:%.*]] = trunc i32 [[TMP0]] to i8
 931 // CHECK1-IRBUILDER-NEXT:    store i8 [[CONV]], ptr [[DOTCAPTURE_EXPR_]], align 1
 932 // CHECK1-IRBUILDER-NEXT:    [[TMP1:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
 933 // CHECK1-IRBUILDER-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP1]] to i32
 934 // CHECK1-IRBUILDER-NEXT:    [[SUB:%.*]] = sub i32 57, [[CONV3]]
 935 // CHECK1-IRBUILDER-NEXT:    [[ADD:%.*]] = add i32 [[SUB]], 1
 936 // CHECK1-IRBUILDER-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
 937 // CHECK1-IRBUILDER-NEXT:    [[CONV4:%.*]] = zext i32 [[DIV]] to i64
 938 // CHECK1-IRBUILDER-NEXT:    [[MUL:%.*]] = mul nsw i64 [[CONV4]], 11
 939 // CHECK1-IRBUILDER-NEXT:    [[SUB5:%.*]] = sub nsw i64 [[MUL]], 1
 940 // CHECK1-IRBUILDER-NEXT:    store i64 [[SUB5]], ptr [[DOTCAPTURE_EXPR_2]], align 8
 941 // CHECK1-IRBUILDER-NEXT:    [[TMP2:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
 942 // CHECK1-IRBUILDER-NEXT:    store i8 [[TMP2]], ptr [[I]], align 1
 943 // CHECK1-IRBUILDER-NEXT:    store i32 11, ptr [[X6]], align 4
 944 // CHECK1-IRBUILDER-NEXT:    [[TMP3:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
 945 // CHECK1-IRBUILDER-NEXT:    [[CONV7:%.*]] = sext i8 [[TMP3]] to i32
 946 // CHECK1-IRBUILDER-NEXT:    [[CMP:%.*]] = icmp sle i32 [[CONV7]], 57
 947 // CHECK1-IRBUILDER-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
 948 // CHECK1-IRBUILDER:       omp.precond.then:
 949 // CHECK1-IRBUILDER-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8
 950 // CHECK1-IRBUILDER-NEXT:    [[TMP4:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_2]], align 8
 951 // CHECK1-IRBUILDER-NEXT:    store i64 [[TMP4]], ptr [[DOTOMP_UB]], align 8
 952 // CHECK1-IRBUILDER-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8
 953 // CHECK1-IRBUILDER-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 954 // CHECK1-IRBUILDER-NEXT:    [[TMP5:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_2]], align 8
 955 // CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB8:[0-9]+]])
 956 // CHECK1-IRBUILDER-NEXT:    call void @__kmpc_dispatch_init_8(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 1073741894, i64 0, i64 [[TMP5]], i64 1, i64 1)
 957 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
 958 // CHECK1-IRBUILDER:       omp.dispatch.cond:
 959 // CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM10:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB8]])
 960 // CHECK1-IRBUILDER-NEXT:    [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_8(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM10]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
 961 // CHECK1-IRBUILDER-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0
 962 // CHECK1-IRBUILDER-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
 963 // CHECK1-IRBUILDER:       omp.dispatch.body:
 964 // CHECK1-IRBUILDER-NEXT:    [[TMP7:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
 965 // CHECK1-IRBUILDER-NEXT:    store i64 [[TMP7]], ptr [[DOTOMP_IV]], align 8
 966 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 967 // CHECK1-IRBUILDER:       omp.inner.for.cond:
 968 // CHECK1-IRBUILDER-NEXT:    [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
 969 // CHECK1-IRBUILDER-NEXT:    [[TMP9:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
 970 // CHECK1-IRBUILDER-NEXT:    [[CMP11:%.*]] = icmp sle i64 [[TMP8]], [[TMP9]]
 971 // CHECK1-IRBUILDER-NEXT:    br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 972 // CHECK1-IRBUILDER:       omp.inner.for.body:
 973 // CHECK1-IRBUILDER-NEXT:    [[TMP10:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
 974 // CHECK1-IRBUILDER-NEXT:    [[CONV12:%.*]] = sext i8 [[TMP10]] to i64
 975 // CHECK1-IRBUILDER-NEXT:    [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
 976 // CHECK1-IRBUILDER-NEXT:    [[DIV13:%.*]] = sdiv i64 [[TMP11]], 11
 977 // CHECK1-IRBUILDER-NEXT:    [[MUL14:%.*]] = mul nsw i64 [[DIV13]], 1
 978 // CHECK1-IRBUILDER-NEXT:    [[ADD15:%.*]] = add nsw i64 [[CONV12]], [[MUL14]]
 979 // CHECK1-IRBUILDER-NEXT:    [[CONV16:%.*]] = trunc i64 [[ADD15]] to i8
 980 // CHECK1-IRBUILDER-NEXT:    store i8 [[CONV16]], ptr [[I8]], align 1
 981 // CHECK1-IRBUILDER-NEXT:    [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
 982 // CHECK1-IRBUILDER-NEXT:    [[TMP13:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
 983 // CHECK1-IRBUILDER-NEXT:    [[DIV17:%.*]] = sdiv i64 [[TMP13]], 11
 984 // CHECK1-IRBUILDER-NEXT:    [[MUL18:%.*]] = mul nsw i64 [[DIV17]], 11
 985 // CHECK1-IRBUILDER-NEXT:    [[SUB19:%.*]] = sub nsw i64 [[TMP12]], [[MUL18]]
 986 // CHECK1-IRBUILDER-NEXT:    [[MUL20:%.*]] = mul nsw i64 [[SUB19]], 1
 987 // CHECK1-IRBUILDER-NEXT:    [[SUB21:%.*]] = sub nsw i64 11, [[MUL20]]
 988 // CHECK1-IRBUILDER-NEXT:    [[CONV22:%.*]] = trunc i64 [[SUB21]] to i32
 989 // CHECK1-IRBUILDER-NEXT:    store i32 [[CONV22]], ptr [[X9]], align 4
 990 // CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM23:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
 991 // CHECK1-IRBUILDER-NEXT:    call void @__kmpc_ordered(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM23]])
 992 // CHECK1-IRBUILDER-NEXT:    [[TMP14:%.*]] = load ptr, ptr [[B_ADDR]], align 8
 993 // CHECK1-IRBUILDER-NEXT:    [[TMP15:%.*]] = load i8, ptr [[I8]], align 1
 994 // CHECK1-IRBUILDER-NEXT:    [[IDXPROM:%.*]] = sext i8 [[TMP15]] to i64
 995 // CHECK1-IRBUILDER-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP14]], i64 [[IDXPROM]]
 996 // CHECK1-IRBUILDER-NEXT:    [[TMP16:%.*]] = load float, ptr [[ARRAYIDX]], align 4
 997 // CHECK1-IRBUILDER-NEXT:    [[TMP17:%.*]] = load ptr, ptr [[C_ADDR]], align 8
 998 // CHECK1-IRBUILDER-NEXT:    [[TMP18:%.*]] = load i8, ptr [[I8]], align 1
 999 // CHECK1-IRBUILDER-NEXT:    [[IDXPROM24:%.*]] = sext i8 [[TMP18]] to i64
1000 // CHECK1-IRBUILDER-NEXT:    [[ARRAYIDX25:%.*]] = getelementptr inbounds float, ptr [[TMP17]], i64 [[IDXPROM24]]
1001 // CHECK1-IRBUILDER-NEXT:    [[TMP19:%.*]] = load float, ptr [[ARRAYIDX25]], align 4
1002 // CHECK1-IRBUILDER-NEXT:    [[MUL26:%.*]] = fmul float [[TMP16]], [[TMP19]]
1003 // CHECK1-IRBUILDER-NEXT:    [[TMP20:%.*]] = load ptr, ptr [[D_ADDR]], align 8
1004 // CHECK1-IRBUILDER-NEXT:    [[TMP21:%.*]] = load i8, ptr [[I8]], align 1
1005 // CHECK1-IRBUILDER-NEXT:    [[IDXPROM27:%.*]] = sext i8 [[TMP21]] to i64
1006 // CHECK1-IRBUILDER-NEXT:    [[ARRAYIDX28:%.*]] = getelementptr inbounds float, ptr [[TMP20]], i64 [[IDXPROM27]]
1007 // CHECK1-IRBUILDER-NEXT:    [[TMP22:%.*]] = load float, ptr [[ARRAYIDX28]], align 4
1008 // CHECK1-IRBUILDER-NEXT:    [[MUL29:%.*]] = fmul float [[MUL26]], [[TMP22]]
1009 // CHECK1-IRBUILDER-NEXT:    [[TMP23:%.*]] = load ptr, ptr [[A_ADDR]], align 8
1010 // CHECK1-IRBUILDER-NEXT:    [[TMP24:%.*]] = load i8, ptr [[I8]], align 1
1011 // CHECK1-IRBUILDER-NEXT:    [[IDXPROM30:%.*]] = sext i8 [[TMP24]] to i64
1012 // CHECK1-IRBUILDER-NEXT:    [[ARRAYIDX31:%.*]] = getelementptr inbounds float, ptr [[TMP23]], i64 [[IDXPROM30]]
1013 // CHECK1-IRBUILDER-NEXT:    store float [[MUL29]], ptr [[ARRAYIDX31]], align 4
1014 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_BODY_ORDERED_AFTER:%.*]]
1015 // CHECK1-IRBUILDER:       omp.inner.for.body.ordered.after:
1016 // CHECK1-IRBUILDER-NEXT:    call void @__kmpc_end_ordered(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM23]])
1017 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1018 // CHECK1-IRBUILDER:       omp.body.continue:
1019 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1020 // CHECK1-IRBUILDER:       omp.inner.for.inc:
1021 // CHECK1-IRBUILDER-NEXT:    [[TMP25:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
1022 // CHECK1-IRBUILDER-NEXT:    [[ADD32:%.*]] = add nsw i64 [[TMP25]], 1
1023 // CHECK1-IRBUILDER-NEXT:    store i64 [[ADD32]], ptr [[DOTOMP_IV]], align 8
1024 // CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM33:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB8]])
1025 // CHECK1-IRBUILDER-NEXT:    call void @__kmpc_dispatch_fini_8(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM33]])
1026 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND]]
1027 // CHECK1-IRBUILDER:       omp.inner.for.end:
1028 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
1029 // CHECK1-IRBUILDER:       omp.dispatch.inc:
1030 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_COND]]
1031 // CHECK1-IRBUILDER:       omp.dispatch.end:
1032 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_PRECOND_END]]
1033 // CHECK1-IRBUILDER:       omp.precond.end:
1034 // CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM34:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
1035 // CHECK1-IRBUILDER-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[OMP_GLOBAL_THREAD_NUM34]])
1036 // CHECK1-IRBUILDER-NEXT:    ret void
1037 //
1038 //
1039 // CHECK1-IRBUILDER-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_
1040 // CHECK1-IRBUILDER-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
1041 // CHECK1-IRBUILDER-NEXT:  entry:
1042 // CHECK1-IRBUILDER-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
1043 // CHECK1-IRBUILDER-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
1044 // CHECK1-IRBUILDER-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
1045 // CHECK1-IRBUILDER-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
1046 // CHECK1-IRBUILDER-NEXT:    [[X:%.*]] = alloca i32, align 4
1047 // CHECK1-IRBUILDER-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1048 // CHECK1-IRBUILDER-NEXT:    [[TMP:%.*]] = alloca i8, align 1
1049 // CHECK1-IRBUILDER-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
1050 // CHECK1-IRBUILDER-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1051 // CHECK1-IRBUILDER-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1052 // CHECK1-IRBUILDER-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1053 // CHECK1-IRBUILDER-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1054 // CHECK1-IRBUILDER-NEXT:    [[I:%.*]] = alloca i8, align 1
1055 // CHECK1-IRBUILDER-NEXT:    [[X2:%.*]] = alloca i32, align 4
1056 // CHECK1-IRBUILDER-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
1057 // CHECK1-IRBUILDER-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
1058 // CHECK1-IRBUILDER-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
1059 // CHECK1-IRBUILDER-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
1060 // CHECK1-IRBUILDER-NEXT:    store i32 0, ptr [[X]], align 4
1061 // CHECK1-IRBUILDER-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
1062 // CHECK1-IRBUILDER-NEXT:    store i32 199, ptr [[DOTOMP_UB]], align 4
1063 // CHECK1-IRBUILDER-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1064 // CHECK1-IRBUILDER-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1065 // CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB10:[0-9]+]])
1066 // CHECK1-IRBUILDER-NEXT:    call void @__kmpc_dispatch_init_4(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 1073741893, i32 0, i32 199, i32 1, i32 1)
1067 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
1068 // CHECK1-IRBUILDER:       omp.dispatch.cond:
1069 // CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM3:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB10]])
1070 // CHECK1-IRBUILDER-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM3]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
1071 // CHECK1-IRBUILDER-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
1072 // CHECK1-IRBUILDER-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
1073 // CHECK1-IRBUILDER:       omp.dispatch.body:
1074 // CHECK1-IRBUILDER-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1075 // CHECK1-IRBUILDER-NEXT:    store i32 [[TMP1]], ptr [[DOTOMP_IV]], align 4
1076 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1077 // CHECK1-IRBUILDER:       omp.inner.for.cond:
1078 // CHECK1-IRBUILDER-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1079 // CHECK1-IRBUILDER-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1080 // CHECK1-IRBUILDER-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]]
1081 // CHECK1-IRBUILDER-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1082 // CHECK1-IRBUILDER:       omp.inner.for.body:
1083 // CHECK1-IRBUILDER-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1084 // CHECK1-IRBUILDER-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP4]], 20
1085 // CHECK1-IRBUILDER-NEXT:    [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
1086 // CHECK1-IRBUILDER-NEXT:    [[ADD:%.*]] = add nsw i32 48, [[MUL]]
1087 // CHECK1-IRBUILDER-NEXT:    [[CONV:%.*]] = trunc i32 [[ADD]] to i8
1088 // CHECK1-IRBUILDER-NEXT:    store i8 [[CONV]], ptr [[I]], align 1
1089 // CHECK1-IRBUILDER-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1090 // CHECK1-IRBUILDER-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1091 // CHECK1-IRBUILDER-NEXT:    [[DIV4:%.*]] = sdiv i32 [[TMP6]], 20
1092 // CHECK1-IRBUILDER-NEXT:    [[MUL5:%.*]] = mul nsw i32 [[DIV4]], 20
1093 // CHECK1-IRBUILDER-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP5]], [[MUL5]]
1094 // CHECK1-IRBUILDER-NEXT:    [[MUL6:%.*]] = mul nsw i32 [[SUB]], 1
1095 // CHECK1-IRBUILDER-NEXT:    [[ADD7:%.*]] = add nsw i32 -10, [[MUL6]]
1096 // CHECK1-IRBUILDER-NEXT:    store i32 [[ADD7]], ptr [[X2]], align 4
1097 // CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM8:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
1098 // CHECK1-IRBUILDER-NEXT:    call void @__kmpc_ordered(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM8]])
1099 // CHECK1-IRBUILDER-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[B_ADDR]], align 8
1100 // CHECK1-IRBUILDER-NEXT:    [[TMP8:%.*]] = load i8, ptr [[I]], align 1
1101 // CHECK1-IRBUILDER-NEXT:    [[IDXPROM:%.*]] = zext i8 [[TMP8]] to i64
1102 // CHECK1-IRBUILDER-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP7]], i64 [[IDXPROM]]
1103 // CHECK1-IRBUILDER-NEXT:    [[TMP9:%.*]] = load float, ptr [[ARRAYIDX]], align 4
1104 // CHECK1-IRBUILDER-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[C_ADDR]], align 8
1105 // CHECK1-IRBUILDER-NEXT:    [[TMP11:%.*]] = load i8, ptr [[I]], align 1
1106 // CHECK1-IRBUILDER-NEXT:    [[IDXPROM9:%.*]] = zext i8 [[TMP11]] to i64
1107 // CHECK1-IRBUILDER-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP10]], i64 [[IDXPROM9]]
1108 // CHECK1-IRBUILDER-NEXT:    [[TMP12:%.*]] = load float, ptr [[ARRAYIDX10]], align 4
1109 // CHECK1-IRBUILDER-NEXT:    [[MUL11:%.*]] = fmul float [[TMP9]], [[TMP12]]
1110 // CHECK1-IRBUILDER-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[D_ADDR]], align 8
1111 // CHECK1-IRBUILDER-NEXT:    [[TMP14:%.*]] = load i8, ptr [[I]], align 1
1112 // CHECK1-IRBUILDER-NEXT:    [[IDXPROM12:%.*]] = zext i8 [[TMP14]] to i64
1113 // CHECK1-IRBUILDER-NEXT:    [[ARRAYIDX13:%.*]] = getelementptr inbounds float, ptr [[TMP13]], i64 [[IDXPROM12]]
1114 // CHECK1-IRBUILDER-NEXT:    [[TMP15:%.*]] = load float, ptr [[ARRAYIDX13]], align 4
1115 // CHECK1-IRBUILDER-NEXT:    [[MUL14:%.*]] = fmul float [[MUL11]], [[TMP15]]
1116 // CHECK1-IRBUILDER-NEXT:    [[TMP16:%.*]] = load ptr, ptr [[A_ADDR]], align 8
1117 // CHECK1-IRBUILDER-NEXT:    [[TMP17:%.*]] = load i8, ptr [[I]], align 1
1118 // CHECK1-IRBUILDER-NEXT:    [[IDXPROM15:%.*]] = zext i8 [[TMP17]] to i64
1119 // CHECK1-IRBUILDER-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds float, ptr [[TMP16]], i64 [[IDXPROM15]]
1120 // CHECK1-IRBUILDER-NEXT:    store float [[MUL14]], ptr [[ARRAYIDX16]], align 4
1121 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_BODY_ORDERED_AFTER:%.*]]
1122 // CHECK1-IRBUILDER:       omp.inner.for.body.ordered.after:
1123 // CHECK1-IRBUILDER-NEXT:    call void @__kmpc_end_ordered(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM8]])
1124 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1125 // CHECK1-IRBUILDER:       omp.body.continue:
1126 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1127 // CHECK1-IRBUILDER:       omp.inner.for.inc:
1128 // CHECK1-IRBUILDER-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1129 // CHECK1-IRBUILDER-NEXT:    [[ADD17:%.*]] = add nsw i32 [[TMP18]], 1
1130 // CHECK1-IRBUILDER-NEXT:    store i32 [[ADD17]], ptr [[DOTOMP_IV]], align 4
1131 // CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM18:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB10]])
1132 // CHECK1-IRBUILDER-NEXT:    call void @__kmpc_dispatch_fini_4(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM18]])
1133 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND]]
1134 // CHECK1-IRBUILDER:       omp.inner.for.end:
1135 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
1136 // CHECK1-IRBUILDER:       omp.dispatch.inc:
1137 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_COND]]
1138 // CHECK1-IRBUILDER:       omp.dispatch.end:
1139 // CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM19:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
1140 // CHECK1-IRBUILDER-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[OMP_GLOBAL_THREAD_NUM19]])
1141 // CHECK1-IRBUILDER-NEXT:    ret void
1142 //
1143 //
1144 // CHECK1-IRBUILDER-LABEL: define {{[^@]+}}@_Z8foo_simdii
1145 // CHECK1-IRBUILDER-SAME: (i32 noundef [[LOW:%.*]], i32 noundef [[UP:%.*]]) #[[ATTR3:[0-9]+]] {
1146 // CHECK1-IRBUILDER-NEXT:  entry:
1147 // CHECK1-IRBUILDER-NEXT:    [[LOW_ADDR:%.*]] = alloca i32, align 4
1148 // CHECK1-IRBUILDER-NEXT:    [[UP_ADDR:%.*]] = alloca i32, align 4
1149 // CHECK1-IRBUILDER-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1150 // CHECK1-IRBUILDER-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
1151 // CHECK1-IRBUILDER-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
1152 // CHECK1-IRBUILDER-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
1153 // CHECK1-IRBUILDER-NEXT:    [[I:%.*]] = alloca i32, align 4
1154 // CHECK1-IRBUILDER-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1155 // CHECK1-IRBUILDER-NEXT:    [[I5:%.*]] = alloca i32, align 4
1156 // CHECK1-IRBUILDER-NEXT:    [[DOTOMP_IV16:%.*]] = alloca i32, align 4
1157 // CHECK1-IRBUILDER-NEXT:    [[_TMP17:%.*]] = alloca i32, align 4
1158 // CHECK1-IRBUILDER-NEXT:    [[DOTCAPTURE_EXPR_18:%.*]] = alloca i32, align 4
1159 // CHECK1-IRBUILDER-NEXT:    [[DOTCAPTURE_EXPR_19:%.*]] = alloca i32, align 4
1160 // CHECK1-IRBUILDER-NEXT:    [[DOTCAPTURE_EXPR_20:%.*]] = alloca i32, align 4
1161 // CHECK1-IRBUILDER-NEXT:    [[I26:%.*]] = alloca i32, align 4
1162 // CHECK1-IRBUILDER-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1163 // CHECK1-IRBUILDER-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1164 // CHECK1-IRBUILDER-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1165 // CHECK1-IRBUILDER-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1166 // CHECK1-IRBUILDER-NEXT:    [[I28:%.*]] = alloca i32, align 4
1167 // CHECK1-IRBUILDER-NEXT:    store i32 [[LOW]], ptr [[LOW_ADDR]], align 4
1168 // CHECK1-IRBUILDER-NEXT:    store i32 [[UP]], ptr [[UP_ADDR]], align 4
1169 // CHECK1-IRBUILDER-NEXT:    [[TMP0:%.*]] = load i32, ptr [[LOW_ADDR]], align 4
1170 // CHECK1-IRBUILDER-NEXT:    store i32 [[TMP0]], ptr [[DOTCAPTURE_EXPR_]], align 4
1171 // CHECK1-IRBUILDER-NEXT:    [[TMP1:%.*]] = load i32, ptr [[UP_ADDR]], align 4
1172 // CHECK1-IRBUILDER-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_1]], align 4
1173 // CHECK1-IRBUILDER-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
1174 // CHECK1-IRBUILDER-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1175 // CHECK1-IRBUILDER-NEXT:    [[SUB:%.*]] = sub i32 [[TMP2]], [[TMP3]]
1176 // CHECK1-IRBUILDER-NEXT:    [[SUB3:%.*]] = sub i32 [[SUB]], 1
1177 // CHECK1-IRBUILDER-NEXT:    [[ADD:%.*]] = add i32 [[SUB3]], 1
1178 // CHECK1-IRBUILDER-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
1179 // CHECK1-IRBUILDER-NEXT:    [[SUB4:%.*]] = sub i32 [[DIV]], 1
1180 // CHECK1-IRBUILDER-NEXT:    store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 4
1181 // CHECK1-IRBUILDER-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1182 // CHECK1-IRBUILDER-NEXT:    store i32 [[TMP4]], ptr [[I]], align 4
1183 // CHECK1-IRBUILDER-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1184 // CHECK1-IRBUILDER-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
1185 // CHECK1-IRBUILDER-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP5]], [[TMP6]]
1186 // CHECK1-IRBUILDER-NEXT:    br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]
1187 // CHECK1-IRBUILDER:       simd.if.then:
1188 // CHECK1-IRBUILDER-NEXT:    store i32 0, ptr [[DOTOMP_IV]], align 4
1189 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1190 // CHECK1-IRBUILDER:       omp.inner.for.cond:
1191 // CHECK1-IRBUILDER-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3:![0-9]+]]
1192 // CHECK1-IRBUILDER-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group [[ACC_GRP3]]
1193 // CHECK1-IRBUILDER-NEXT:    [[ADD6:%.*]] = add i32 [[TMP8]], 1
1194 // CHECK1-IRBUILDER-NEXT:    [[CMP7:%.*]] = icmp ult i32 [[TMP7]], [[ADD6]]
1195 // CHECK1-IRBUILDER-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1196 // CHECK1-IRBUILDER:       omp.inner.for.body:
1197 // CHECK1-IRBUILDER-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group [[ACC_GRP3]]
1198 // CHECK1-IRBUILDER-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]
1199 // CHECK1-IRBUILDER-NEXT:    [[MUL:%.*]] = mul i32 [[TMP10]], 1
1200 // CHECK1-IRBUILDER-NEXT:    [[ADD8:%.*]] = add i32 [[TMP9]], [[MUL]]
1201 // CHECK1-IRBUILDER-NEXT:    store i32 [[ADD8]], ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP3]]
1202 // CHECK1-IRBUILDER-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP3]]
1203 // CHECK1-IRBUILDER-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64
1204 // CHECK1-IRBUILDER-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM]]
1205 // CHECK1-IRBUILDER-NEXT:    store float 0.000000e+00, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]]
1206 // CHECK1-IRBUILDER-NEXT:    call void @__captured_stmt(ptr [[I5]]), !llvm.access.group [[ACC_GRP3]]
1207 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_BODY_ORDERED_AFTER:%.*]]
1208 // CHECK1-IRBUILDER:       omp.inner.for.body.ordered.after:
1209 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1210 // CHECK1-IRBUILDER:       omp.body.continue:
1211 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1212 // CHECK1-IRBUILDER:       omp.inner.for.inc:
1213 // CHECK1-IRBUILDER-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]
1214 // CHECK1-IRBUILDER-NEXT:    [[ADD9:%.*]] = add i32 [[TMP12]], 1
1215 // CHECK1-IRBUILDER-NEXT:    store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]
1216 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
1217 // CHECK1-IRBUILDER:       omp.inner.for.end:
1218 // CHECK1-IRBUILDER-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1219 // CHECK1-IRBUILDER-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
1220 // CHECK1-IRBUILDER-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1221 // CHECK1-IRBUILDER-NEXT:    [[SUB10:%.*]] = sub i32 [[TMP14]], [[TMP15]]
1222 // CHECK1-IRBUILDER-NEXT:    [[SUB11:%.*]] = sub i32 [[SUB10]], 1
1223 // CHECK1-IRBUILDER-NEXT:    [[ADD12:%.*]] = add i32 [[SUB11]], 1
1224 // CHECK1-IRBUILDER-NEXT:    [[DIV13:%.*]] = udiv i32 [[ADD12]], 1
1225 // CHECK1-IRBUILDER-NEXT:    [[MUL14:%.*]] = mul i32 [[DIV13]], 1
1226 // CHECK1-IRBUILDER-NEXT:    [[ADD15:%.*]] = add i32 [[TMP13]], [[MUL14]]
1227 // CHECK1-IRBUILDER-NEXT:    store i32 [[ADD15]], ptr [[I5]], align 4
1228 // CHECK1-IRBUILDER-NEXT:    br label [[SIMD_IF_END]]
1229 // CHECK1-IRBUILDER:       simd.if.end:
1230 // CHECK1-IRBUILDER-NEXT:    [[TMP16:%.*]] = load i32, ptr [[LOW_ADDR]], align 4
1231 // CHECK1-IRBUILDER-NEXT:    store i32 [[TMP16]], ptr [[DOTCAPTURE_EXPR_18]], align 4
1232 // CHECK1-IRBUILDER-NEXT:    [[TMP17:%.*]] = load i32, ptr [[UP_ADDR]], align 4
1233 // CHECK1-IRBUILDER-NEXT:    store i32 [[TMP17]], ptr [[DOTCAPTURE_EXPR_19]], align 4
1234 // CHECK1-IRBUILDER-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_19]], align 4
1235 // CHECK1-IRBUILDER-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 4
1236 // CHECK1-IRBUILDER-NEXT:    [[SUB21:%.*]] = sub i32 [[TMP18]], [[TMP19]]
1237 // CHECK1-IRBUILDER-NEXT:    [[SUB22:%.*]] = sub i32 [[SUB21]], 1
1238 // CHECK1-IRBUILDER-NEXT:    [[ADD23:%.*]] = add i32 [[SUB22]], 1
1239 // CHECK1-IRBUILDER-NEXT:    [[DIV24:%.*]] = udiv i32 [[ADD23]], 1
1240 // CHECK1-IRBUILDER-NEXT:    [[SUB25:%.*]] = sub i32 [[DIV24]], 1
1241 // CHECK1-IRBUILDER-NEXT:    store i32 [[SUB25]], ptr [[DOTCAPTURE_EXPR_20]], align 4
1242 // CHECK1-IRBUILDER-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 4
1243 // CHECK1-IRBUILDER-NEXT:    store i32 [[TMP20]], ptr [[I26]], align 4
1244 // CHECK1-IRBUILDER-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 4
1245 // CHECK1-IRBUILDER-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_19]], align 4
1246 // CHECK1-IRBUILDER-NEXT:    [[CMP27:%.*]] = icmp slt i32 [[TMP21]], [[TMP22]]
1247 // CHECK1-IRBUILDER-NEXT:    br i1 [[CMP27]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
1248 // CHECK1-IRBUILDER:       omp.precond.then:
1249 // CHECK1-IRBUILDER-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
1250 // CHECK1-IRBUILDER-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_20]], align 4
1251 // CHECK1-IRBUILDER-NEXT:    store i32 [[TMP23]], ptr [[DOTOMP_UB]], align 4
1252 // CHECK1-IRBUILDER-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1253 // CHECK1-IRBUILDER-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1254 // CHECK1-IRBUILDER-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_20]], align 4
1255 // CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB12:[0-9]+]])
1256 // CHECK1-IRBUILDER-NEXT:    call void @__kmpc_dispatch_init_4u(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 66, i32 0, i32 [[TMP24]], i32 1, i32 1)
1257 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
1258 // CHECK1-IRBUILDER:       omp.dispatch.cond:
1259 // CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM29:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB12]])
1260 // CHECK1-IRBUILDER-NEXT:    [[TMP25:%.*]] = call i32 @__kmpc_dispatch_next_4u(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM29]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
1261 // CHECK1-IRBUILDER-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP25]], 0
1262 // CHECK1-IRBUILDER-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
1263 // CHECK1-IRBUILDER:       omp.dispatch.body:
1264 // CHECK1-IRBUILDER-NEXT:    [[TMP26:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1265 // CHECK1-IRBUILDER-NEXT:    store i32 [[TMP26]], ptr [[DOTOMP_IV16]], align 4
1266 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND30:%.*]]
1267 // CHECK1-IRBUILDER:       omp.inner.for.cond30:
1268 // CHECK1-IRBUILDER-NEXT:    [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV16]], align 4, !llvm.access.group [[ACC_GRP7:![0-9]+]]
1269 // CHECK1-IRBUILDER-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP7]]
1270 // CHECK1-IRBUILDER-NEXT:    [[ADD31:%.*]] = add i32 [[TMP28]], 1
1271 // CHECK1-IRBUILDER-NEXT:    [[CMP32:%.*]] = icmp ult i32 [[TMP27]], [[ADD31]]
1272 // CHECK1-IRBUILDER-NEXT:    br i1 [[CMP32]], label [[OMP_INNER_FOR_BODY33:%.*]], label [[OMP_INNER_FOR_END42:%.*]]
1273 // CHECK1-IRBUILDER:       omp.inner.for.body33:
1274 // CHECK1-IRBUILDER-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 4, !llvm.access.group [[ACC_GRP7]]
1275 // CHECK1-IRBUILDER-NEXT:    [[TMP30:%.*]] = load i32, ptr [[DOTOMP_IV16]], align 4, !llvm.access.group [[ACC_GRP7]]
1276 // CHECK1-IRBUILDER-NEXT:    [[MUL34:%.*]] = mul i32 [[TMP30]], 1
1277 // CHECK1-IRBUILDER-NEXT:    [[ADD35:%.*]] = add i32 [[TMP29]], [[MUL34]]
1278 // CHECK1-IRBUILDER-NEXT:    store i32 [[ADD35]], ptr [[I28]], align 4, !llvm.access.group [[ACC_GRP7]]
1279 // CHECK1-IRBUILDER-NEXT:    [[TMP31:%.*]] = load i32, ptr [[I28]], align 4, !llvm.access.group [[ACC_GRP7]]
1280 // CHECK1-IRBUILDER-NEXT:    [[IDXPROM36:%.*]] = sext i32 [[TMP31]] to i64
1281 // CHECK1-IRBUILDER-NEXT:    [[ARRAYIDX37:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM36]]
1282 // CHECK1-IRBUILDER-NEXT:    store float 0.000000e+00, ptr [[ARRAYIDX37]], align 4, !llvm.access.group [[ACC_GRP7]]
1283 // CHECK1-IRBUILDER-NEXT:    call void @__captured_stmt.1(ptr [[I28]]), !llvm.access.group [[ACC_GRP7]]
1284 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_BODY33_ORDERED_AFTER:%.*]]
1285 // CHECK1-IRBUILDER:       omp.inner.for.body33.ordered.after:
1286 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_BODY_CONTINUE38:%.*]]
1287 // CHECK1-IRBUILDER:       omp.body.continue38:
1288 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_INC39:%.*]]
1289 // CHECK1-IRBUILDER:       omp.inner.for.inc39:
1290 // CHECK1-IRBUILDER-NEXT:    [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IV16]], align 4, !llvm.access.group [[ACC_GRP7]]
1291 // CHECK1-IRBUILDER-NEXT:    [[ADD40:%.*]] = add i32 [[TMP32]], 1
1292 // CHECK1-IRBUILDER-NEXT:    store i32 [[ADD40]], ptr [[DOTOMP_IV16]], align 4, !llvm.access.group [[ACC_GRP7]]
1293 // CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM41:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB12]])
1294 // CHECK1-IRBUILDER-NEXT:    call void @__kmpc_dispatch_fini_4u(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM41]]), !llvm.access.group [[ACC_GRP7]]
1295 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND30]], !llvm.loop [[LOOP8:![0-9]+]]
1296 // CHECK1-IRBUILDER:       omp.inner.for.end42:
1297 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
1298 // CHECK1-IRBUILDER:       omp.dispatch.inc:
1299 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_COND]]
1300 // CHECK1-IRBUILDER:       omp.dispatch.end:
1301 // CHECK1-IRBUILDER-NEXT:    [[TMP33:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
1302 // CHECK1-IRBUILDER-NEXT:    [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0
1303 // CHECK1-IRBUILDER-NEXT:    br i1 [[TMP34]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1304 // CHECK1-IRBUILDER:       .omp.final.then:
1305 // CHECK1-IRBUILDER-NEXT:    [[TMP35:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 4
1306 // CHECK1-IRBUILDER-NEXT:    [[TMP36:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_19]], align 4
1307 // CHECK1-IRBUILDER-NEXT:    [[TMP37:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 4
1308 // CHECK1-IRBUILDER-NEXT:    [[SUB43:%.*]] = sub i32 [[TMP36]], [[TMP37]]
1309 // CHECK1-IRBUILDER-NEXT:    [[SUB44:%.*]] = sub i32 [[SUB43]], 1
1310 // CHECK1-IRBUILDER-NEXT:    [[ADD45:%.*]] = add i32 [[SUB44]], 1
1311 // CHECK1-IRBUILDER-NEXT:    [[DIV46:%.*]] = udiv i32 [[ADD45]], 1
1312 // CHECK1-IRBUILDER-NEXT:    [[MUL47:%.*]] = mul i32 [[DIV46]], 1
1313 // CHECK1-IRBUILDER-NEXT:    [[ADD48:%.*]] = add i32 [[TMP35]], [[MUL47]]
1314 // CHECK1-IRBUILDER-NEXT:    store i32 [[ADD48]], ptr [[I28]], align 4
1315 // CHECK1-IRBUILDER-NEXT:    br label [[DOTOMP_FINAL_DONE]]
1316 // CHECK1-IRBUILDER:       .omp.final.done:
1317 // CHECK1-IRBUILDER-NEXT:    br label [[OMP_PRECOND_END]]
1318 // CHECK1-IRBUILDER:       omp.precond.end:
1319 // CHECK1-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM49:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
1320 // CHECK1-IRBUILDER-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[OMP_GLOBAL_THREAD_NUM49]])
1321 // CHECK1-IRBUILDER-NEXT:    ret void
1322 //
1323 //
1324 // CHECK1-IRBUILDER-LABEL: define {{[^@]+}}@__captured_stmt
1325 // CHECK1-IRBUILDER-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR4:[0-9]+]] {
1326 // CHECK1-IRBUILDER-NEXT:  entry:
1327 // CHECK1-IRBUILDER-NEXT:    [[I_ADDR:%.*]] = alloca ptr, align 8
1328 // CHECK1-IRBUILDER-NEXT:    store ptr [[I]], ptr [[I_ADDR]], align 8
1329 // CHECK1-IRBUILDER-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 8
1330 // CHECK1-IRBUILDER-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
1331 // CHECK1-IRBUILDER-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64
1332 // CHECK1-IRBUILDER-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM]]
1333 // CHECK1-IRBUILDER-NEXT:    store float 1.000000e+00, ptr [[ARRAYIDX]], align 4
1334 // CHECK1-IRBUILDER-NEXT:    ret void
1335 //
1336 //
1337 // CHECK1-IRBUILDER-LABEL: define {{[^@]+}}@__captured_stmt.1
1338 // CHECK1-IRBUILDER-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR4]] {
1339 // CHECK1-IRBUILDER-NEXT:  entry:
1340 // CHECK1-IRBUILDER-NEXT:    [[I_ADDR:%.*]] = alloca ptr, align 8
1341 // CHECK1-IRBUILDER-NEXT:    store ptr [[I]], ptr [[I_ADDR]], align 8
1342 // CHECK1-IRBUILDER-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 8
1343 // CHECK1-IRBUILDER-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
1344 // CHECK1-IRBUILDER-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64
1345 // CHECK1-IRBUILDER-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM]]
1346 // CHECK1-IRBUILDER-NEXT:    store float 1.000000e+00, ptr [[ARRAYIDX]], align 4
1347 // CHECK1-IRBUILDER-NEXT:    ret void
1348 //
1349 //
1350 // CHECK3-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_
1351 // CHECK3-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] {
1352 // CHECK3-NEXT:  entry:
1353 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
1354 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
1355 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
1356 // CHECK3-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
1357 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1358 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1359 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1360 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1361 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1362 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1363 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
1364 // CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
1365 // CHECK3-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
1366 // CHECK3-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
1367 // CHECK3-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
1368 // CHECK3-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
1369 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
1370 // CHECK3-NEXT:    store i32 4571423, ptr [[DOTOMP_UB]], align 4
1371 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1372 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1373 // CHECK3-NEXT:    call void @__kmpc_dispatch_init_4(ptr @[[GLOB1]], i32 [[TMP0]], i32 66, i32 0, i32 4571423, i32 1, i32 1)
1374 // CHECK3-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
1375 // CHECK3:       omp.dispatch.cond:
1376 // CHECK3-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
1377 // CHECK3-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0
1378 // CHECK3-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
1379 // CHECK3:       omp.dispatch.body:
1380 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1381 // CHECK3-NEXT:    store i32 [[TMP2]], ptr [[DOTOMP_IV]], align 4
1382 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1383 // CHECK3:       omp.inner.for.cond:
1384 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1385 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1386 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP3]], [[TMP4]]
1387 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1388 // CHECK3:       omp.inner.for.body:
1389 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1390 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP5]], 7
1391 // CHECK3-NEXT:    [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
1392 // CHECK3-NEXT:    store i32 [[SUB]], ptr [[I]], align 4
1393 // CHECK3-NEXT:    call void @__kmpc_ordered(ptr @[[GLOB1]], i32 [[TMP0]])
1394 // CHECK3-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[B_ADDR]], align 8
1395 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[I]], align 4
1396 // CHECK3-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64
1397 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP6]], i64 [[IDXPROM]]
1398 // CHECK3-NEXT:    [[TMP8:%.*]] = load float, ptr [[ARRAYIDX]], align 4
1399 // CHECK3-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[C_ADDR]], align 8
1400 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[I]], align 4
1401 // CHECK3-NEXT:    [[IDXPROM1:%.*]] = sext i32 [[TMP10]] to i64
1402 // CHECK3-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[TMP9]], i64 [[IDXPROM1]]
1403 // CHECK3-NEXT:    [[TMP11:%.*]] = load float, ptr [[ARRAYIDX2]], align 4
1404 // CHECK3-NEXT:    [[MUL3:%.*]] = fmul float [[TMP8]], [[TMP11]]
1405 // CHECK3-NEXT:    [[TMP12:%.*]] = load ptr, ptr [[D_ADDR]], align 8
1406 // CHECK3-NEXT:    [[TMP13:%.*]] = load i32, ptr [[I]], align 4
1407 // CHECK3-NEXT:    [[IDXPROM4:%.*]] = sext i32 [[TMP13]] to i64
1408 // CHECK3-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds float, ptr [[TMP12]], i64 [[IDXPROM4]]
1409 // CHECK3-NEXT:    [[TMP14:%.*]] = load float, ptr [[ARRAYIDX5]], align 4
1410 // CHECK3-NEXT:    [[MUL6:%.*]] = fmul float [[MUL3]], [[TMP14]]
1411 // CHECK3-NEXT:    [[TMP15:%.*]] = load ptr, ptr [[A_ADDR]], align 8
1412 // CHECK3-NEXT:    [[TMP16:%.*]] = load i32, ptr [[I]], align 4
1413 // CHECK3-NEXT:    [[IDXPROM7:%.*]] = sext i32 [[TMP16]] to i64
1414 // CHECK3-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds float, ptr [[TMP15]], i64 [[IDXPROM7]]
1415 // CHECK3-NEXT:    store float [[MUL6]], ptr [[ARRAYIDX8]], align 4
1416 // CHECK3-NEXT:    call void @__kmpc_end_ordered(ptr @[[GLOB1]], i32 [[TMP0]])
1417 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1418 // CHECK3:       omp.body.continue:
1419 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1420 // CHECK3:       omp.inner.for.inc:
1421 // CHECK3-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1422 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP17]], 1
1423 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
1424 // CHECK3-NEXT:    call void @__kmpc_dispatch_fini_4(ptr @[[GLOB1]], i32 [[TMP0]])
1425 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]]
1426 // CHECK3:       omp.inner.for.end:
1427 // CHECK3-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
1428 // CHECK3:       omp.dispatch.inc:
1429 // CHECK3-NEXT:    br label [[OMP_DISPATCH_COND]]
1430 // CHECK3:       omp.dispatch.end:
1431 // CHECK3-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB2:[0-9]+]], i32 [[TMP0]])
1432 // CHECK3-NEXT:    ret void
1433 //
1434 //
1435 // CHECK3-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_
1436 // CHECK3-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
1437 // CHECK3-NEXT:  entry:
1438 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
1439 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
1440 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
1441 // CHECK3-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
1442 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
1443 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i64, align 8
1444 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
1445 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
1446 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
1447 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1448 // CHECK3-NEXT:    [[I:%.*]] = alloca i64, align 8
1449 // CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
1450 // CHECK3-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
1451 // CHECK3-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
1452 // CHECK3-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
1453 // CHECK3-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
1454 // CHECK3-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8
1455 // CHECK3-NEXT:    store i64 16908287, ptr [[DOTOMP_UB]], align 8
1456 // CHECK3-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8
1457 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1458 // CHECK3-NEXT:    call void @__kmpc_dispatch_init_8u(ptr @[[GLOB1]], i32 [[TMP0]], i32 67, i64 0, i64 16908287, i64 1, i64 1)
1459 // CHECK3-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
1460 // CHECK3:       omp.dispatch.cond:
1461 // CHECK3-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_dispatch_next_8u(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
1462 // CHECK3-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0
1463 // CHECK3-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
1464 // CHECK3:       omp.dispatch.body:
1465 // CHECK3-NEXT:    [[TMP2:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
1466 // CHECK3-NEXT:    store i64 [[TMP2]], ptr [[DOTOMP_IV]], align 8
1467 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1468 // CHECK3:       omp.inner.for.cond:
1469 // CHECK3-NEXT:    [[TMP3:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
1470 // CHECK3-NEXT:    [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
1471 // CHECK3-NEXT:    [[ADD:%.*]] = add i64 [[TMP4]], 1
1472 // CHECK3-NEXT:    [[CMP:%.*]] = icmp ult i64 [[TMP3]], [[ADD]]
1473 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1474 // CHECK3:       omp.inner.for.body:
1475 // CHECK3-NEXT:    [[TMP5:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
1476 // CHECK3-NEXT:    [[MUL:%.*]] = mul i64 [[TMP5]], 127
1477 // CHECK3-NEXT:    [[ADD1:%.*]] = add i64 131071, [[MUL]]
1478 // CHECK3-NEXT:    store i64 [[ADD1]], ptr [[I]], align 8
1479 // CHECK3-NEXT:    call void @__kmpc_ordered(ptr @[[GLOB1]], i32 [[TMP0]])
1480 // CHECK3-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[B_ADDR]], align 8
1481 // CHECK3-NEXT:    [[TMP7:%.*]] = load i64, ptr [[I]], align 8
1482 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP6]], i64 [[TMP7]]
1483 // CHECK3-NEXT:    [[TMP8:%.*]] = load float, ptr [[ARRAYIDX]], align 4
1484 // CHECK3-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[C_ADDR]], align 8
1485 // CHECK3-NEXT:    [[TMP10:%.*]] = load i64, ptr [[I]], align 8
1486 // CHECK3-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[TMP9]], i64 [[TMP10]]
1487 // CHECK3-NEXT:    [[TMP11:%.*]] = load float, ptr [[ARRAYIDX2]], align 4
1488 // CHECK3-NEXT:    [[MUL3:%.*]] = fmul float [[TMP8]], [[TMP11]]
1489 // CHECK3-NEXT:    [[TMP12:%.*]] = load ptr, ptr [[D_ADDR]], align 8
1490 // CHECK3-NEXT:    [[TMP13:%.*]] = load i64, ptr [[I]], align 8
1491 // CHECK3-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds float, ptr [[TMP12]], i64 [[TMP13]]
1492 // CHECK3-NEXT:    [[TMP14:%.*]] = load float, ptr [[ARRAYIDX4]], align 4
1493 // CHECK3-NEXT:    [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP14]]
1494 // CHECK3-NEXT:    [[TMP15:%.*]] = load ptr, ptr [[A_ADDR]], align 8
1495 // CHECK3-NEXT:    [[TMP16:%.*]] = load i64, ptr [[I]], align 8
1496 // CHECK3-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP15]], i64 [[TMP16]]
1497 // CHECK3-NEXT:    store float [[MUL5]], ptr [[ARRAYIDX6]], align 4
1498 // CHECK3-NEXT:    call void @__kmpc_end_ordered(ptr @[[GLOB1]], i32 [[TMP0]])
1499 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1500 // CHECK3:       omp.body.continue:
1501 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1502 // CHECK3:       omp.inner.for.inc:
1503 // CHECK3-NEXT:    [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
1504 // CHECK3-NEXT:    [[ADD7:%.*]] = add i64 [[TMP17]], 1
1505 // CHECK3-NEXT:    store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8
1506 // CHECK3-NEXT:    call void @__kmpc_dispatch_fini_8u(ptr @[[GLOB1]], i32 [[TMP0]])
1507 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]]
1508 // CHECK3:       omp.inner.for.end:
1509 // CHECK3-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
1510 // CHECK3:       omp.dispatch.inc:
1511 // CHECK3-NEXT:    br label [[OMP_DISPATCH_COND]]
1512 // CHECK3:       omp.dispatch.end:
1513 // CHECK3-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB2]], i32 [[TMP0]])
1514 // CHECK3-NEXT:    ret void
1515 //
1516 //
1517 // CHECK3-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_
1518 // CHECK3-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
1519 // CHECK3-NEXT:  entry:
1520 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
1521 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
1522 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
1523 // CHECK3-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
1524 // CHECK3-NEXT:    [[X:%.*]] = alloca i32, align 4
1525 // CHECK3-NEXT:    [[Y:%.*]] = alloca i32, align 4
1526 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
1527 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i8, align 1
1528 // CHECK3-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
1529 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
1530 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 8
1531 // CHECK3-NEXT:    [[I:%.*]] = alloca i8, align 1
1532 // CHECK3-NEXT:    [[X6:%.*]] = alloca i32, align 4
1533 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
1534 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
1535 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
1536 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1537 // CHECK3-NEXT:    [[I8:%.*]] = alloca i8, align 1
1538 // CHECK3-NEXT:    [[X9:%.*]] = alloca i32, align 4
1539 // CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
1540 // CHECK3-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
1541 // CHECK3-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
1542 // CHECK3-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
1543 // CHECK3-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
1544 // CHECK3-NEXT:    store i32 0, ptr [[X]], align 4
1545 // CHECK3-NEXT:    store i32 0, ptr [[Y]], align 4
1546 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[Y]], align 4
1547 // CHECK3-NEXT:    [[CONV:%.*]] = trunc i32 [[TMP1]] to i8
1548 // CHECK3-NEXT:    store i8 [[CONV]], ptr [[DOTCAPTURE_EXPR_]], align 1
1549 // CHECK3-NEXT:    [[TMP2:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
1550 // CHECK3-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP2]] to i32
1551 // CHECK3-NEXT:    [[SUB:%.*]] = sub i32 57, [[CONV3]]
1552 // CHECK3-NEXT:    [[ADD:%.*]] = add i32 [[SUB]], 1
1553 // CHECK3-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
1554 // CHECK3-NEXT:    [[CONV4:%.*]] = zext i32 [[DIV]] to i64
1555 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i64 [[CONV4]], 11
1556 // CHECK3-NEXT:    [[SUB5:%.*]] = sub nsw i64 [[MUL]], 1
1557 // CHECK3-NEXT:    store i64 [[SUB5]], ptr [[DOTCAPTURE_EXPR_2]], align 8
1558 // CHECK3-NEXT:    [[TMP3:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
1559 // CHECK3-NEXT:    store i8 [[TMP3]], ptr [[I]], align 1
1560 // CHECK3-NEXT:    store i32 11, ptr [[X6]], align 4
1561 // CHECK3-NEXT:    [[TMP4:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
1562 // CHECK3-NEXT:    [[CONV7:%.*]] = sext i8 [[TMP4]] to i32
1563 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sle i32 [[CONV7]], 57
1564 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
1565 // CHECK3:       omp.precond.then:
1566 // CHECK3-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8
1567 // CHECK3-NEXT:    [[TMP5:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_2]], align 8
1568 // CHECK3-NEXT:    store i64 [[TMP5]], ptr [[DOTOMP_UB]], align 8
1569 // CHECK3-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8
1570 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1571 // CHECK3-NEXT:    [[TMP6:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_2]], align 8
1572 // CHECK3-NEXT:    call void @__kmpc_dispatch_init_8(ptr @[[GLOB1]], i32 [[TMP0]], i32 70, i64 0, i64 [[TMP6]], i64 1, i64 1)
1573 // CHECK3-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
1574 // CHECK3:       omp.dispatch.cond:
1575 // CHECK3-NEXT:    [[TMP7:%.*]] = call i32 @__kmpc_dispatch_next_8(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
1576 // CHECK3-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP7]], 0
1577 // CHECK3-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
1578 // CHECK3:       omp.dispatch.body:
1579 // CHECK3-NEXT:    [[TMP8:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
1580 // CHECK3-NEXT:    store i64 [[TMP8]], ptr [[DOTOMP_IV]], align 8
1581 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1582 // CHECK3:       omp.inner.for.cond:
1583 // CHECK3-NEXT:    [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
1584 // CHECK3-NEXT:    [[TMP10:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
1585 // CHECK3-NEXT:    [[CMP10:%.*]] = icmp sle i64 [[TMP9]], [[TMP10]]
1586 // CHECK3-NEXT:    br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1587 // CHECK3:       omp.inner.for.body:
1588 // CHECK3-NEXT:    [[TMP11:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
1589 // CHECK3-NEXT:    [[CONV11:%.*]] = sext i8 [[TMP11]] to i64
1590 // CHECK3-NEXT:    [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
1591 // CHECK3-NEXT:    [[DIV12:%.*]] = sdiv i64 [[TMP12]], 11
1592 // CHECK3-NEXT:    [[MUL13:%.*]] = mul nsw i64 [[DIV12]], 1
1593 // CHECK3-NEXT:    [[ADD14:%.*]] = add nsw i64 [[CONV11]], [[MUL13]]
1594 // CHECK3-NEXT:    [[CONV15:%.*]] = trunc i64 [[ADD14]] to i8
1595 // CHECK3-NEXT:    store i8 [[CONV15]], ptr [[I8]], align 1
1596 // CHECK3-NEXT:    [[TMP13:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
1597 // CHECK3-NEXT:    [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
1598 // CHECK3-NEXT:    [[DIV16:%.*]] = sdiv i64 [[TMP14]], 11
1599 // CHECK3-NEXT:    [[MUL17:%.*]] = mul nsw i64 [[DIV16]], 11
1600 // CHECK3-NEXT:    [[SUB18:%.*]] = sub nsw i64 [[TMP13]], [[MUL17]]
1601 // CHECK3-NEXT:    [[MUL19:%.*]] = mul nsw i64 [[SUB18]], 1
1602 // CHECK3-NEXT:    [[SUB20:%.*]] = sub nsw i64 11, [[MUL19]]
1603 // CHECK3-NEXT:    [[CONV21:%.*]] = trunc i64 [[SUB20]] to i32
1604 // CHECK3-NEXT:    store i32 [[CONV21]], ptr [[X9]], align 4
1605 // CHECK3-NEXT:    call void @__kmpc_ordered(ptr @[[GLOB1]], i32 [[TMP0]])
1606 // CHECK3-NEXT:    [[TMP15:%.*]] = load ptr, ptr [[B_ADDR]], align 8
1607 // CHECK3-NEXT:    [[TMP16:%.*]] = load i8, ptr [[I8]], align 1
1608 // CHECK3-NEXT:    [[IDXPROM:%.*]] = sext i8 [[TMP16]] to i64
1609 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP15]], i64 [[IDXPROM]]
1610 // CHECK3-NEXT:    [[TMP17:%.*]] = load float, ptr [[ARRAYIDX]], align 4
1611 // CHECK3-NEXT:    [[TMP18:%.*]] = load ptr, ptr [[C_ADDR]], align 8
1612 // CHECK3-NEXT:    [[TMP19:%.*]] = load i8, ptr [[I8]], align 1
1613 // CHECK3-NEXT:    [[IDXPROM22:%.*]] = sext i8 [[TMP19]] to i64
1614 // CHECK3-NEXT:    [[ARRAYIDX23:%.*]] = getelementptr inbounds float, ptr [[TMP18]], i64 [[IDXPROM22]]
1615 // CHECK3-NEXT:    [[TMP20:%.*]] = load float, ptr [[ARRAYIDX23]], align 4
1616 // CHECK3-NEXT:    [[MUL24:%.*]] = fmul float [[TMP17]], [[TMP20]]
1617 // CHECK3-NEXT:    [[TMP21:%.*]] = load ptr, ptr [[D_ADDR]], align 8
1618 // CHECK3-NEXT:    [[TMP22:%.*]] = load i8, ptr [[I8]], align 1
1619 // CHECK3-NEXT:    [[IDXPROM25:%.*]] = sext i8 [[TMP22]] to i64
1620 // CHECK3-NEXT:    [[ARRAYIDX26:%.*]] = getelementptr inbounds float, ptr [[TMP21]], i64 [[IDXPROM25]]
1621 // CHECK3-NEXT:    [[TMP23:%.*]] = load float, ptr [[ARRAYIDX26]], align 4
1622 // CHECK3-NEXT:    [[MUL27:%.*]] = fmul float [[MUL24]], [[TMP23]]
1623 // CHECK3-NEXT:    [[TMP24:%.*]] = load ptr, ptr [[A_ADDR]], align 8
1624 // CHECK3-NEXT:    [[TMP25:%.*]] = load i8, ptr [[I8]], align 1
1625 // CHECK3-NEXT:    [[IDXPROM28:%.*]] = sext i8 [[TMP25]] to i64
1626 // CHECK3-NEXT:    [[ARRAYIDX29:%.*]] = getelementptr inbounds float, ptr [[TMP24]], i64 [[IDXPROM28]]
1627 // CHECK3-NEXT:    store float [[MUL27]], ptr [[ARRAYIDX29]], align 4
1628 // CHECK3-NEXT:    call void @__kmpc_end_ordered(ptr @[[GLOB1]], i32 [[TMP0]])
1629 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1630 // CHECK3:       omp.body.continue:
1631 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1632 // CHECK3:       omp.inner.for.inc:
1633 // CHECK3-NEXT:    [[TMP26:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
1634 // CHECK3-NEXT:    [[ADD30:%.*]] = add nsw i64 [[TMP26]], 1
1635 // CHECK3-NEXT:    store i64 [[ADD30]], ptr [[DOTOMP_IV]], align 8
1636 // CHECK3-NEXT:    call void @__kmpc_dispatch_fini_8(ptr @[[GLOB1]], i32 [[TMP0]])
1637 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]]
1638 // CHECK3:       omp.inner.for.end:
1639 // CHECK3-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
1640 // CHECK3:       omp.dispatch.inc:
1641 // CHECK3-NEXT:    br label [[OMP_DISPATCH_COND]]
1642 // CHECK3:       omp.dispatch.end:
1643 // CHECK3-NEXT:    br label [[OMP_PRECOND_END]]
1644 // CHECK3:       omp.precond.end:
1645 // CHECK3-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB2]], i32 [[TMP0]])
1646 // CHECK3-NEXT:    ret void
1647 //
1648 //
1649 // CHECK3-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_
1650 // CHECK3-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
1651 // CHECK3-NEXT:  entry:
1652 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
1653 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
1654 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
1655 // CHECK3-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
1656 // CHECK3-NEXT:    [[X:%.*]] = alloca i32, align 4
1657 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1658 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i8, align 1
1659 // CHECK3-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
1660 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1661 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1662 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1663 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1664 // CHECK3-NEXT:    [[I:%.*]] = alloca i8, align 1
1665 // CHECK3-NEXT:    [[X2:%.*]] = alloca i32, align 4
1666 // CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
1667 // CHECK3-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
1668 // CHECK3-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
1669 // CHECK3-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
1670 // CHECK3-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
1671 // CHECK3-NEXT:    store i32 0, ptr [[X]], align 4
1672 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
1673 // CHECK3-NEXT:    store i32 199, ptr [[DOTOMP_UB]], align 4
1674 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1675 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1676 // CHECK3-NEXT:    call void @__kmpc_dispatch_init_4(ptr @[[GLOB1]], i32 [[TMP0]], i32 69, i32 0, i32 199, i32 1, i32 1)
1677 // CHECK3-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
1678 // CHECK3:       omp.dispatch.cond:
1679 // CHECK3-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
1680 // CHECK3-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0
1681 // CHECK3-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
1682 // CHECK3:       omp.dispatch.body:
1683 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1684 // CHECK3-NEXT:    store i32 [[TMP2]], ptr [[DOTOMP_IV]], align 4
1685 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1686 // CHECK3:       omp.inner.for.cond:
1687 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1688 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1689 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP3]], [[TMP4]]
1690 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1691 // CHECK3:       omp.inner.for.body:
1692 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1693 // CHECK3-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP5]], 20
1694 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
1695 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 48, [[MUL]]
1696 // CHECK3-NEXT:    [[CONV:%.*]] = trunc i32 [[ADD]] to i8
1697 // CHECK3-NEXT:    store i8 [[CONV]], ptr [[I]], align 1
1698 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1699 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1700 // CHECK3-NEXT:    [[DIV3:%.*]] = sdiv i32 [[TMP7]], 20
1701 // CHECK3-NEXT:    [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 20
1702 // CHECK3-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP6]], [[MUL4]]
1703 // CHECK3-NEXT:    [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1
1704 // CHECK3-NEXT:    [[ADD6:%.*]] = add nsw i32 -10, [[MUL5]]
1705 // CHECK3-NEXT:    store i32 [[ADD6]], ptr [[X2]], align 4
1706 // CHECK3-NEXT:    call void @__kmpc_ordered(ptr @[[GLOB1]], i32 [[TMP0]])
1707 // CHECK3-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[B_ADDR]], align 8
1708 // CHECK3-NEXT:    [[TMP9:%.*]] = load i8, ptr [[I]], align 1
1709 // CHECK3-NEXT:    [[IDXPROM:%.*]] = zext i8 [[TMP9]] to i64
1710 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP8]], i64 [[IDXPROM]]
1711 // CHECK3-NEXT:    [[TMP10:%.*]] = load float, ptr [[ARRAYIDX]], align 4
1712 // CHECK3-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[C_ADDR]], align 8
1713 // CHECK3-NEXT:    [[TMP12:%.*]] = load i8, ptr [[I]], align 1
1714 // CHECK3-NEXT:    [[IDXPROM7:%.*]] = zext i8 [[TMP12]] to i64
1715 // CHECK3-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds float, ptr [[TMP11]], i64 [[IDXPROM7]]
1716 // CHECK3-NEXT:    [[TMP13:%.*]] = load float, ptr [[ARRAYIDX8]], align 4
1717 // CHECK3-NEXT:    [[MUL9:%.*]] = fmul float [[TMP10]], [[TMP13]]
1718 // CHECK3-NEXT:    [[TMP14:%.*]] = load ptr, ptr [[D_ADDR]], align 8
1719 // CHECK3-NEXT:    [[TMP15:%.*]] = load i8, ptr [[I]], align 1
1720 // CHECK3-NEXT:    [[IDXPROM10:%.*]] = zext i8 [[TMP15]] to i64
1721 // CHECK3-NEXT:    [[ARRAYIDX11:%.*]] = getelementptr inbounds float, ptr [[TMP14]], i64 [[IDXPROM10]]
1722 // CHECK3-NEXT:    [[TMP16:%.*]] = load float, ptr [[ARRAYIDX11]], align 4
1723 // CHECK3-NEXT:    [[MUL12:%.*]] = fmul float [[MUL9]], [[TMP16]]
1724 // CHECK3-NEXT:    [[TMP17:%.*]] = load ptr, ptr [[A_ADDR]], align 8
1725 // CHECK3-NEXT:    [[TMP18:%.*]] = load i8, ptr [[I]], align 1
1726 // CHECK3-NEXT:    [[IDXPROM13:%.*]] = zext i8 [[TMP18]] to i64
1727 // CHECK3-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds float, ptr [[TMP17]], i64 [[IDXPROM13]]
1728 // CHECK3-NEXT:    store float [[MUL12]], ptr [[ARRAYIDX14]], align 4
1729 // CHECK3-NEXT:    call void @__kmpc_end_ordered(ptr @[[GLOB1]], i32 [[TMP0]])
1730 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1731 // CHECK3:       omp.body.continue:
1732 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1733 // CHECK3:       omp.inner.for.inc:
1734 // CHECK3-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1735 // CHECK3-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP19]], 1
1736 // CHECK3-NEXT:    store i32 [[ADD15]], ptr [[DOTOMP_IV]], align 4
1737 // CHECK3-NEXT:    call void @__kmpc_dispatch_fini_4(ptr @[[GLOB1]], i32 [[TMP0]])
1738 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]]
1739 // CHECK3:       omp.inner.for.end:
1740 // CHECK3-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
1741 // CHECK3:       omp.dispatch.inc:
1742 // CHECK3-NEXT:    br label [[OMP_DISPATCH_COND]]
1743 // CHECK3:       omp.dispatch.end:
1744 // CHECK3-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB2]], i32 [[TMP0]])
1745 // CHECK3-NEXT:    ret void
1746 //
1747 //
1748 // CHECK3-LABEL: define {{[^@]+}}@_Z8foo_simdii
1749 // CHECK3-SAME: (i32 noundef [[LOW:%.*]], i32 noundef [[UP:%.*]]) #[[ATTR3:[0-9]+]] {
1750 // CHECK3-NEXT:  entry:
1751 // CHECK3-NEXT:    [[LOW_ADDR:%.*]] = alloca i32, align 4
1752 // CHECK3-NEXT:    [[UP_ADDR:%.*]] = alloca i32, align 4
1753 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1754 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
1755 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
1756 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
1757 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
1758 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1759 // CHECK3-NEXT:    [[I5:%.*]] = alloca i32, align 4
1760 // CHECK3-NEXT:    [[DOTOMP_IV16:%.*]] = alloca i32, align 4
1761 // CHECK3-NEXT:    [[_TMP17:%.*]] = alloca i32, align 4
1762 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_18:%.*]] = alloca i32, align 4
1763 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_19:%.*]] = alloca i32, align 4
1764 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_20:%.*]] = alloca i32, align 4
1765 // CHECK3-NEXT:    [[I26:%.*]] = alloca i32, align 4
1766 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1767 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1768 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1769 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1770 // CHECK3-NEXT:    [[I28:%.*]] = alloca i32, align 4
1771 // CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
1772 // CHECK3-NEXT:    store i32 [[LOW]], ptr [[LOW_ADDR]], align 4
1773 // CHECK3-NEXT:    store i32 [[UP]], ptr [[UP_ADDR]], align 4
1774 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[LOW_ADDR]], align 4
1775 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
1776 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[UP_ADDR]], align 4
1777 // CHECK3-NEXT:    store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
1778 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
1779 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1780 // CHECK3-NEXT:    [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
1781 // CHECK3-NEXT:    [[SUB3:%.*]] = sub i32 [[SUB]], 1
1782 // CHECK3-NEXT:    [[ADD:%.*]] = add i32 [[SUB3]], 1
1783 // CHECK3-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
1784 // CHECK3-NEXT:    [[SUB4:%.*]] = sub i32 [[DIV]], 1
1785 // CHECK3-NEXT:    store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 4
1786 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1787 // CHECK3-NEXT:    store i32 [[TMP5]], ptr [[I]], align 4
1788 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1789 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
1790 // CHECK3-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
1791 // CHECK3-NEXT:    br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]
1792 // CHECK3:       simd.if.then:
1793 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IV]], align 4
1794 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1795 // CHECK3:       omp.inner.for.cond:
1796 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3:![0-9]+]]
1797 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group [[ACC_GRP3]]
1798 // CHECK3-NEXT:    [[ADD6:%.*]] = add i32 [[TMP9]], 1
1799 // CHECK3-NEXT:    [[CMP7:%.*]] = icmp ult i32 [[TMP8]], [[ADD6]]
1800 // CHECK3-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1801 // CHECK3:       omp.inner.for.body:
1802 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group [[ACC_GRP3]]
1803 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]
1804 // CHECK3-NEXT:    [[MUL:%.*]] = mul i32 [[TMP11]], 1
1805 // CHECK3-NEXT:    [[ADD8:%.*]] = add i32 [[TMP10]], [[MUL]]
1806 // CHECK3-NEXT:    store i32 [[ADD8]], ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP3]]
1807 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP3]]
1808 // CHECK3-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64
1809 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM]]
1810 // CHECK3-NEXT:    store float 0.000000e+00, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]]
1811 // CHECK3-NEXT:    call void @__captured_stmt(ptr [[I5]]), !llvm.access.group [[ACC_GRP3]]
1812 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1813 // CHECK3:       omp.body.continue:
1814 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1815 // CHECK3:       omp.inner.for.inc:
1816 // CHECK3-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]
1817 // CHECK3-NEXT:    [[ADD9:%.*]] = add i32 [[TMP13]], 1
1818 // CHECK3-NEXT:    store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]
1819 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
1820 // CHECK3:       omp.inner.for.end:
1821 // CHECK3-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1822 // CHECK3-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
1823 // CHECK3-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1824 // CHECK3-NEXT:    [[SUB10:%.*]] = sub i32 [[TMP15]], [[TMP16]]
1825 // CHECK3-NEXT:    [[SUB11:%.*]] = sub i32 [[SUB10]], 1
1826 // CHECK3-NEXT:    [[ADD12:%.*]] = add i32 [[SUB11]], 1
1827 // CHECK3-NEXT:    [[DIV13:%.*]] = udiv i32 [[ADD12]], 1
1828 // CHECK3-NEXT:    [[MUL14:%.*]] = mul i32 [[DIV13]], 1
1829 // CHECK3-NEXT:    [[ADD15:%.*]] = add i32 [[TMP14]], [[MUL14]]
1830 // CHECK3-NEXT:    store i32 [[ADD15]], ptr [[I5]], align 4
1831 // CHECK3-NEXT:    br label [[SIMD_IF_END]]
1832 // CHECK3:       simd.if.end:
1833 // CHECK3-NEXT:    [[TMP17:%.*]] = load i32, ptr [[LOW_ADDR]], align 4
1834 // CHECK3-NEXT:    store i32 [[TMP17]], ptr [[DOTCAPTURE_EXPR_18]], align 4
1835 // CHECK3-NEXT:    [[TMP18:%.*]] = load i32, ptr [[UP_ADDR]], align 4
1836 // CHECK3-NEXT:    store i32 [[TMP18]], ptr [[DOTCAPTURE_EXPR_19]], align 4
1837 // CHECK3-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_19]], align 4
1838 // CHECK3-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 4
1839 // CHECK3-NEXT:    [[SUB21:%.*]] = sub i32 [[TMP19]], [[TMP20]]
1840 // CHECK3-NEXT:    [[SUB22:%.*]] = sub i32 [[SUB21]], 1
1841 // CHECK3-NEXT:    [[ADD23:%.*]] = add i32 [[SUB22]], 1
1842 // CHECK3-NEXT:    [[DIV24:%.*]] = udiv i32 [[ADD23]], 1
1843 // CHECK3-NEXT:    [[SUB25:%.*]] = sub i32 [[DIV24]], 1
1844 // CHECK3-NEXT:    store i32 [[SUB25]], ptr [[DOTCAPTURE_EXPR_20]], align 4
1845 // CHECK3-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 4
1846 // CHECK3-NEXT:    store i32 [[TMP21]], ptr [[I26]], align 4
1847 // CHECK3-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 4
1848 // CHECK3-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_19]], align 4
1849 // CHECK3-NEXT:    [[CMP27:%.*]] = icmp slt i32 [[TMP22]], [[TMP23]]
1850 // CHECK3-NEXT:    br i1 [[CMP27]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
1851 // CHECK3:       omp.precond.then:
1852 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
1853 // CHECK3-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_20]], align 4
1854 // CHECK3-NEXT:    store i32 [[TMP24]], ptr [[DOTOMP_UB]], align 4
1855 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1856 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1857 // CHECK3-NEXT:    [[TMP25:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_20]], align 4
1858 // CHECK3-NEXT:    call void @__kmpc_dispatch_init_4u(ptr @[[GLOB1]], i32 [[TMP0]], i32 66, i32 0, i32 [[TMP25]], i32 1, i32 1)
1859 // CHECK3-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
1860 // CHECK3:       omp.dispatch.cond:
1861 // CHECK3-NEXT:    [[TMP26:%.*]] = call i32 @__kmpc_dispatch_next_4u(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
1862 // CHECK3-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP26]], 0
1863 // CHECK3-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
1864 // CHECK3:       omp.dispatch.body:
1865 // CHECK3-NEXT:    [[TMP27:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1866 // CHECK3-NEXT:    store i32 [[TMP27]], ptr [[DOTOMP_IV16]], align 4
1867 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND29:%.*]]
1868 // CHECK3:       omp.inner.for.cond29:
1869 // CHECK3-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTOMP_IV16]], align 4, !llvm.access.group [[ACC_GRP7:![0-9]+]]
1870 // CHECK3-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP7]]
1871 // CHECK3-NEXT:    [[ADD30:%.*]] = add i32 [[TMP29]], 1
1872 // CHECK3-NEXT:    [[CMP31:%.*]] = icmp ult i32 [[TMP28]], [[ADD30]]
1873 // CHECK3-NEXT:    br i1 [[CMP31]], label [[OMP_INNER_FOR_BODY32:%.*]], label [[OMP_INNER_FOR_END40:%.*]]
1874 // CHECK3:       omp.inner.for.body32:
1875 // CHECK3-NEXT:    [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 4, !llvm.access.group [[ACC_GRP7]]
1876 // CHECK3-NEXT:    [[TMP31:%.*]] = load i32, ptr [[DOTOMP_IV16]], align 4, !llvm.access.group [[ACC_GRP7]]
1877 // CHECK3-NEXT:    [[MUL33:%.*]] = mul i32 [[TMP31]], 1
1878 // CHECK3-NEXT:    [[ADD34:%.*]] = add i32 [[TMP30]], [[MUL33]]
1879 // CHECK3-NEXT:    store i32 [[ADD34]], ptr [[I28]], align 4, !llvm.access.group [[ACC_GRP7]]
1880 // CHECK3-NEXT:    [[TMP32:%.*]] = load i32, ptr [[I28]], align 4, !llvm.access.group [[ACC_GRP7]]
1881 // CHECK3-NEXT:    [[IDXPROM35:%.*]] = sext i32 [[TMP32]] to i64
1882 // CHECK3-NEXT:    [[ARRAYIDX36:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM35]]
1883 // CHECK3-NEXT:    store float 0.000000e+00, ptr [[ARRAYIDX36]], align 4, !llvm.access.group [[ACC_GRP7]]
1884 // CHECK3-NEXT:    call void @__captured_stmt.1(ptr [[I28]]), !llvm.access.group [[ACC_GRP7]]
1885 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE37:%.*]]
1886 // CHECK3:       omp.body.continue37:
1887 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC38:%.*]]
1888 // CHECK3:       omp.inner.for.inc38:
1889 // CHECK3-NEXT:    [[TMP33:%.*]] = load i32, ptr [[DOTOMP_IV16]], align 4, !llvm.access.group [[ACC_GRP7]]
1890 // CHECK3-NEXT:    [[ADD39:%.*]] = add i32 [[TMP33]], 1
1891 // CHECK3-NEXT:    store i32 [[ADD39]], ptr [[DOTOMP_IV16]], align 4, !llvm.access.group [[ACC_GRP7]]
1892 // CHECK3-NEXT:    call void @__kmpc_dispatch_fini_4u(ptr @[[GLOB1]], i32 [[TMP0]]), !llvm.access.group [[ACC_GRP7]]
1893 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND29]], !llvm.loop [[LOOP8:![0-9]+]]
1894 // CHECK3:       omp.inner.for.end40:
1895 // CHECK3-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
1896 // CHECK3:       omp.dispatch.inc:
1897 // CHECK3-NEXT:    br label [[OMP_DISPATCH_COND]]
1898 // CHECK3:       omp.dispatch.end:
1899 // CHECK3-NEXT:    [[TMP34:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
1900 // CHECK3-NEXT:    [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0
1901 // CHECK3-NEXT:    br i1 [[TMP35]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1902 // CHECK3:       .omp.final.then:
1903 // CHECK3-NEXT:    [[TMP36:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 4
1904 // CHECK3-NEXT:    [[TMP37:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_19]], align 4
1905 // CHECK3-NEXT:    [[TMP38:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 4
1906 // CHECK3-NEXT:    [[SUB41:%.*]] = sub i32 [[TMP37]], [[TMP38]]
1907 // CHECK3-NEXT:    [[SUB42:%.*]] = sub i32 [[SUB41]], 1
1908 // CHECK3-NEXT:    [[ADD43:%.*]] = add i32 [[SUB42]], 1
1909 // CHECK3-NEXT:    [[DIV44:%.*]] = udiv i32 [[ADD43]], 1
1910 // CHECK3-NEXT:    [[MUL45:%.*]] = mul i32 [[DIV44]], 1
1911 // CHECK3-NEXT:    [[ADD46:%.*]] = add i32 [[TMP36]], [[MUL45]]
1912 // CHECK3-NEXT:    store i32 [[ADD46]], ptr [[I28]], align 4
1913 // CHECK3-NEXT:    br label [[DOTOMP_FINAL_DONE]]
1914 // CHECK3:       .omp.final.done:
1915 // CHECK3-NEXT:    br label [[OMP_PRECOND_END]]
1916 // CHECK3:       omp.precond.end:
1917 // CHECK3-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB2]], i32 [[TMP0]])
1918 // CHECK3-NEXT:    ret void
1919 //
1920 //
1921 // CHECK3-LABEL: define {{[^@]+}}@__captured_stmt
1922 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR4:[0-9]+]] {
1923 // CHECK3-NEXT:  entry:
1924 // CHECK3-NEXT:    [[I_ADDR:%.*]] = alloca ptr, align 8
1925 // CHECK3-NEXT:    store ptr [[I]], ptr [[I_ADDR]], align 8
1926 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 8
1927 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
1928 // CHECK3-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64
1929 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM]]
1930 // CHECK3-NEXT:    store float 1.000000e+00, ptr [[ARRAYIDX]], align 4
1931 // CHECK3-NEXT:    ret void
1932 //
1933 //
1934 // CHECK3-LABEL: define {{[^@]+}}@__captured_stmt.1
1935 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR4]] {
1936 // CHECK3-NEXT:  entry:
1937 // CHECK3-NEXT:    [[I_ADDR:%.*]] = alloca ptr, align 8
1938 // CHECK3-NEXT:    store ptr [[I]], ptr [[I_ADDR]], align 8
1939 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 8
1940 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
1941 // CHECK3-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64
1942 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM]]
1943 // CHECK3-NEXT:    store float 1.000000e+00, ptr [[ARRAYIDX]], align 4
1944 // CHECK3-NEXT:    ret void
1945 //
1946 //
1947 // CHECK3-IRBUILDER-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_
1948 // CHECK3-IRBUILDER-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] {
1949 // CHECK3-IRBUILDER-NEXT:  entry:
1950 // CHECK3-IRBUILDER-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
1951 // CHECK3-IRBUILDER-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
1952 // CHECK3-IRBUILDER-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
1953 // CHECK3-IRBUILDER-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
1954 // CHECK3-IRBUILDER-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1955 // CHECK3-IRBUILDER-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1956 // CHECK3-IRBUILDER-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1957 // CHECK3-IRBUILDER-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1958 // CHECK3-IRBUILDER-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1959 // CHECK3-IRBUILDER-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1960 // CHECK3-IRBUILDER-NEXT:    [[I:%.*]] = alloca i32, align 4
1961 // CHECK3-IRBUILDER-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
1962 // CHECK3-IRBUILDER-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
1963 // CHECK3-IRBUILDER-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
1964 // CHECK3-IRBUILDER-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
1965 // CHECK3-IRBUILDER-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
1966 // CHECK3-IRBUILDER-NEXT:    store i32 4571423, ptr [[DOTOMP_UB]], align 4
1967 // CHECK3-IRBUILDER-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1968 // CHECK3-IRBUILDER-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1969 // CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3:[0-9]+]])
1970 // CHECK3-IRBUILDER-NEXT:    call void @__kmpc_dispatch_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 66, i32 0, i32 4571423, i32 1, i32 1)
1971 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
1972 // CHECK3-IRBUILDER:       omp.dispatch.cond:
1973 // CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3]])
1974 // CHECK3-IRBUILDER-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM1]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
1975 // CHECK3-IRBUILDER-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
1976 // CHECK3-IRBUILDER-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
1977 // CHECK3-IRBUILDER:       omp.dispatch.body:
1978 // CHECK3-IRBUILDER-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1979 // CHECK3-IRBUILDER-NEXT:    store i32 [[TMP1]], ptr [[DOTOMP_IV]], align 4
1980 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1981 // CHECK3-IRBUILDER:       omp.inner.for.cond:
1982 // CHECK3-IRBUILDER-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1983 // CHECK3-IRBUILDER-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1984 // CHECK3-IRBUILDER-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]]
1985 // CHECK3-IRBUILDER-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1986 // CHECK3-IRBUILDER:       omp.inner.for.body:
1987 // CHECK3-IRBUILDER-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1988 // CHECK3-IRBUILDER-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP4]], 7
1989 // CHECK3-IRBUILDER-NEXT:    [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
1990 // CHECK3-IRBUILDER-NEXT:    store i32 [[SUB]], ptr [[I]], align 4
1991 // CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
1992 // CHECK3-IRBUILDER-NEXT:    call void @__kmpc_ordered(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM2]])
1993 // CHECK3-IRBUILDER-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[B_ADDR]], align 8
1994 // CHECK3-IRBUILDER-NEXT:    [[TMP6:%.*]] = load i32, ptr [[I]], align 4
1995 // CHECK3-IRBUILDER-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64
1996 // CHECK3-IRBUILDER-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP5]], i64 [[IDXPROM]]
1997 // CHECK3-IRBUILDER-NEXT:    [[TMP7:%.*]] = load float, ptr [[ARRAYIDX]], align 4
1998 // CHECK3-IRBUILDER-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[C_ADDR]], align 8
1999 // CHECK3-IRBUILDER-NEXT:    [[TMP9:%.*]] = load i32, ptr [[I]], align 4
2000 // CHECK3-IRBUILDER-NEXT:    [[IDXPROM3:%.*]] = sext i32 [[TMP9]] to i64
2001 // CHECK3-IRBUILDER-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds float, ptr [[TMP8]], i64 [[IDXPROM3]]
2002 // CHECK3-IRBUILDER-NEXT:    [[TMP10:%.*]] = load float, ptr [[ARRAYIDX4]], align 4
2003 // CHECK3-IRBUILDER-NEXT:    [[MUL5:%.*]] = fmul float [[TMP7]], [[TMP10]]
2004 // CHECK3-IRBUILDER-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[D_ADDR]], align 8
2005 // CHECK3-IRBUILDER-NEXT:    [[TMP12:%.*]] = load i32, ptr [[I]], align 4
2006 // CHECK3-IRBUILDER-NEXT:    [[IDXPROM6:%.*]] = sext i32 [[TMP12]] to i64
2007 // CHECK3-IRBUILDER-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds float, ptr [[TMP11]], i64 [[IDXPROM6]]
2008 // CHECK3-IRBUILDER-NEXT:    [[TMP13:%.*]] = load float, ptr [[ARRAYIDX7]], align 4
2009 // CHECK3-IRBUILDER-NEXT:    [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP13]]
2010 // CHECK3-IRBUILDER-NEXT:    [[TMP14:%.*]] = load ptr, ptr [[A_ADDR]], align 8
2011 // CHECK3-IRBUILDER-NEXT:    [[TMP15:%.*]] = load i32, ptr [[I]], align 4
2012 // CHECK3-IRBUILDER-NEXT:    [[IDXPROM9:%.*]] = sext i32 [[TMP15]] to i64
2013 // CHECK3-IRBUILDER-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP14]], i64 [[IDXPROM9]]
2014 // CHECK3-IRBUILDER-NEXT:    store float [[MUL8]], ptr [[ARRAYIDX10]], align 4
2015 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_BODY_ORDERED_AFTER:%.*]]
2016 // CHECK3-IRBUILDER:       omp.inner.for.body.ordered.after:
2017 // CHECK3-IRBUILDER-NEXT:    call void @__kmpc_end_ordered(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM2]])
2018 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2019 // CHECK3-IRBUILDER:       omp.body.continue:
2020 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2021 // CHECK3-IRBUILDER:       omp.inner.for.inc:
2022 // CHECK3-IRBUILDER-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2023 // CHECK3-IRBUILDER-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP16]], 1
2024 // CHECK3-IRBUILDER-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
2025 // CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM11:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3]])
2026 // CHECK3-IRBUILDER-NEXT:    call void @__kmpc_dispatch_fini_4(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM11]])
2027 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND]]
2028 // CHECK3-IRBUILDER:       omp.inner.for.end:
2029 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
2030 // CHECK3-IRBUILDER:       omp.dispatch.inc:
2031 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_COND]]
2032 // CHECK3-IRBUILDER:       omp.dispatch.end:
2033 // CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM12:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
2034 // CHECK3-IRBUILDER-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB4:[0-9]+]], i32 [[OMP_GLOBAL_THREAD_NUM12]])
2035 // CHECK3-IRBUILDER-NEXT:    ret void
2036 //
2037 //
2038 // CHECK3-IRBUILDER-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_
2039 // CHECK3-IRBUILDER-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
2040 // CHECK3-IRBUILDER-NEXT:  entry:
2041 // CHECK3-IRBUILDER-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
2042 // CHECK3-IRBUILDER-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
2043 // CHECK3-IRBUILDER-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
2044 // CHECK3-IRBUILDER-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
2045 // CHECK3-IRBUILDER-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
2046 // CHECK3-IRBUILDER-NEXT:    [[TMP:%.*]] = alloca i64, align 8
2047 // CHECK3-IRBUILDER-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
2048 // CHECK3-IRBUILDER-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
2049 // CHECK3-IRBUILDER-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
2050 // CHECK3-IRBUILDER-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2051 // CHECK3-IRBUILDER-NEXT:    [[I:%.*]] = alloca i64, align 8
2052 // CHECK3-IRBUILDER-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
2053 // CHECK3-IRBUILDER-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
2054 // CHECK3-IRBUILDER-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
2055 // CHECK3-IRBUILDER-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
2056 // CHECK3-IRBUILDER-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8
2057 // CHECK3-IRBUILDER-NEXT:    store i64 16908287, ptr [[DOTOMP_UB]], align 8
2058 // CHECK3-IRBUILDER-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8
2059 // CHECK3-IRBUILDER-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2060 // CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB6:[0-9]+]])
2061 // CHECK3-IRBUILDER-NEXT:    call void @__kmpc_dispatch_init_8u(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 67, i64 0, i64 16908287, i64 1, i64 1)
2062 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
2063 // CHECK3-IRBUILDER:       omp.dispatch.cond:
2064 // CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB6]])
2065 // CHECK3-IRBUILDER-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_dispatch_next_8u(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM1]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
2066 // CHECK3-IRBUILDER-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
2067 // CHECK3-IRBUILDER-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
2068 // CHECK3-IRBUILDER:       omp.dispatch.body:
2069 // CHECK3-IRBUILDER-NEXT:    [[TMP1:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
2070 // CHECK3-IRBUILDER-NEXT:    store i64 [[TMP1]], ptr [[DOTOMP_IV]], align 8
2071 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2072 // CHECK3-IRBUILDER:       omp.inner.for.cond:
2073 // CHECK3-IRBUILDER-NEXT:    [[TMP2:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
2074 // CHECK3-IRBUILDER-NEXT:    [[TMP3:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
2075 // CHECK3-IRBUILDER-NEXT:    [[ADD:%.*]] = add i64 [[TMP3]], 1
2076 // CHECK3-IRBUILDER-NEXT:    [[CMP:%.*]] = icmp ult i64 [[TMP2]], [[ADD]]
2077 // CHECK3-IRBUILDER-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2078 // CHECK3-IRBUILDER:       omp.inner.for.body:
2079 // CHECK3-IRBUILDER-NEXT:    [[TMP4:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
2080 // CHECK3-IRBUILDER-NEXT:    [[MUL:%.*]] = mul i64 [[TMP4]], 127
2081 // CHECK3-IRBUILDER-NEXT:    [[ADD2:%.*]] = add i64 131071, [[MUL]]
2082 // CHECK3-IRBUILDER-NEXT:    store i64 [[ADD2]], ptr [[I]], align 8
2083 // CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM3:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
2084 // CHECK3-IRBUILDER-NEXT:    call void @__kmpc_ordered(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM3]])
2085 // CHECK3-IRBUILDER-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[B_ADDR]], align 8
2086 // CHECK3-IRBUILDER-NEXT:    [[TMP6:%.*]] = load i64, ptr [[I]], align 8
2087 // CHECK3-IRBUILDER-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP5]], i64 [[TMP6]]
2088 // CHECK3-IRBUILDER-NEXT:    [[TMP7:%.*]] = load float, ptr [[ARRAYIDX]], align 4
2089 // CHECK3-IRBUILDER-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[C_ADDR]], align 8
2090 // CHECK3-IRBUILDER-NEXT:    [[TMP9:%.*]] = load i64, ptr [[I]], align 8
2091 // CHECK3-IRBUILDER-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds float, ptr [[TMP8]], i64 [[TMP9]]
2092 // CHECK3-IRBUILDER-NEXT:    [[TMP10:%.*]] = load float, ptr [[ARRAYIDX4]], align 4
2093 // CHECK3-IRBUILDER-NEXT:    [[MUL5:%.*]] = fmul float [[TMP7]], [[TMP10]]
2094 // CHECK3-IRBUILDER-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[D_ADDR]], align 8
2095 // CHECK3-IRBUILDER-NEXT:    [[TMP12:%.*]] = load i64, ptr [[I]], align 8
2096 // CHECK3-IRBUILDER-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP11]], i64 [[TMP12]]
2097 // CHECK3-IRBUILDER-NEXT:    [[TMP13:%.*]] = load float, ptr [[ARRAYIDX6]], align 4
2098 // CHECK3-IRBUILDER-NEXT:    [[MUL7:%.*]] = fmul float [[MUL5]], [[TMP13]]
2099 // CHECK3-IRBUILDER-NEXT:    [[TMP14:%.*]] = load ptr, ptr [[A_ADDR]], align 8
2100 // CHECK3-IRBUILDER-NEXT:    [[TMP15:%.*]] = load i64, ptr [[I]], align 8
2101 // CHECK3-IRBUILDER-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds float, ptr [[TMP14]], i64 [[TMP15]]
2102 // CHECK3-IRBUILDER-NEXT:    store float [[MUL7]], ptr [[ARRAYIDX8]], align 4
2103 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_BODY_ORDERED_AFTER:%.*]]
2104 // CHECK3-IRBUILDER:       omp.inner.for.body.ordered.after:
2105 // CHECK3-IRBUILDER-NEXT:    call void @__kmpc_end_ordered(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM3]])
2106 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2107 // CHECK3-IRBUILDER:       omp.body.continue:
2108 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2109 // CHECK3-IRBUILDER:       omp.inner.for.inc:
2110 // CHECK3-IRBUILDER-NEXT:    [[TMP16:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
2111 // CHECK3-IRBUILDER-NEXT:    [[ADD9:%.*]] = add i64 [[TMP16]], 1
2112 // CHECK3-IRBUILDER-NEXT:    store i64 [[ADD9]], ptr [[DOTOMP_IV]], align 8
2113 // CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM10:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB6]])
2114 // CHECK3-IRBUILDER-NEXT:    call void @__kmpc_dispatch_fini_8u(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM10]])
2115 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND]]
2116 // CHECK3-IRBUILDER:       omp.inner.for.end:
2117 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
2118 // CHECK3-IRBUILDER:       omp.dispatch.inc:
2119 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_COND]]
2120 // CHECK3-IRBUILDER:       omp.dispatch.end:
2121 // CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM11:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
2122 // CHECK3-IRBUILDER-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[OMP_GLOBAL_THREAD_NUM11]])
2123 // CHECK3-IRBUILDER-NEXT:    ret void
2124 //
2125 //
2126 // CHECK3-IRBUILDER-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_
2127 // CHECK3-IRBUILDER-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
2128 // CHECK3-IRBUILDER-NEXT:  entry:
2129 // CHECK3-IRBUILDER-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
2130 // CHECK3-IRBUILDER-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
2131 // CHECK3-IRBUILDER-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
2132 // CHECK3-IRBUILDER-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
2133 // CHECK3-IRBUILDER-NEXT:    [[X:%.*]] = alloca i32, align 4
2134 // CHECK3-IRBUILDER-NEXT:    [[Y:%.*]] = alloca i32, align 4
2135 // CHECK3-IRBUILDER-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
2136 // CHECK3-IRBUILDER-NEXT:    [[TMP:%.*]] = alloca i8, align 1
2137 // CHECK3-IRBUILDER-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
2138 // CHECK3-IRBUILDER-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
2139 // CHECK3-IRBUILDER-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 8
2140 // CHECK3-IRBUILDER-NEXT:    [[I:%.*]] = alloca i8, align 1
2141 // CHECK3-IRBUILDER-NEXT:    [[X6:%.*]] = alloca i32, align 4
2142 // CHECK3-IRBUILDER-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
2143 // CHECK3-IRBUILDER-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
2144 // CHECK3-IRBUILDER-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
2145 // CHECK3-IRBUILDER-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2146 // CHECK3-IRBUILDER-NEXT:    [[I8:%.*]] = alloca i8, align 1
2147 // CHECK3-IRBUILDER-NEXT:    [[X9:%.*]] = alloca i32, align 4
2148 // CHECK3-IRBUILDER-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
2149 // CHECK3-IRBUILDER-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
2150 // CHECK3-IRBUILDER-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
2151 // CHECK3-IRBUILDER-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
2152 // CHECK3-IRBUILDER-NEXT:    store i32 0, ptr [[X]], align 4
2153 // CHECK3-IRBUILDER-NEXT:    store i32 0, ptr [[Y]], align 4
2154 // CHECK3-IRBUILDER-NEXT:    [[TMP0:%.*]] = load i32, ptr [[Y]], align 4
2155 // CHECK3-IRBUILDER-NEXT:    [[CONV:%.*]] = trunc i32 [[TMP0]] to i8
2156 // CHECK3-IRBUILDER-NEXT:    store i8 [[CONV]], ptr [[DOTCAPTURE_EXPR_]], align 1
2157 // CHECK3-IRBUILDER-NEXT:    [[TMP1:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
2158 // CHECK3-IRBUILDER-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP1]] to i32
2159 // CHECK3-IRBUILDER-NEXT:    [[SUB:%.*]] = sub i32 57, [[CONV3]]
2160 // CHECK3-IRBUILDER-NEXT:    [[ADD:%.*]] = add i32 [[SUB]], 1
2161 // CHECK3-IRBUILDER-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
2162 // CHECK3-IRBUILDER-NEXT:    [[CONV4:%.*]] = zext i32 [[DIV]] to i64
2163 // CHECK3-IRBUILDER-NEXT:    [[MUL:%.*]] = mul nsw i64 [[CONV4]], 11
2164 // CHECK3-IRBUILDER-NEXT:    [[SUB5:%.*]] = sub nsw i64 [[MUL]], 1
2165 // CHECK3-IRBUILDER-NEXT:    store i64 [[SUB5]], ptr [[DOTCAPTURE_EXPR_2]], align 8
2166 // CHECK3-IRBUILDER-NEXT:    [[TMP2:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
2167 // CHECK3-IRBUILDER-NEXT:    store i8 [[TMP2]], ptr [[I]], align 1
2168 // CHECK3-IRBUILDER-NEXT:    store i32 11, ptr [[X6]], align 4
2169 // CHECK3-IRBUILDER-NEXT:    [[TMP3:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
2170 // CHECK3-IRBUILDER-NEXT:    [[CONV7:%.*]] = sext i8 [[TMP3]] to i32
2171 // CHECK3-IRBUILDER-NEXT:    [[CMP:%.*]] = icmp sle i32 [[CONV7]], 57
2172 // CHECK3-IRBUILDER-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
2173 // CHECK3-IRBUILDER:       omp.precond.then:
2174 // CHECK3-IRBUILDER-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8
2175 // CHECK3-IRBUILDER-NEXT:    [[TMP4:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_2]], align 8
2176 // CHECK3-IRBUILDER-NEXT:    store i64 [[TMP4]], ptr [[DOTOMP_UB]], align 8
2177 // CHECK3-IRBUILDER-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8
2178 // CHECK3-IRBUILDER-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2179 // CHECK3-IRBUILDER-NEXT:    [[TMP5:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_2]], align 8
2180 // CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB8:[0-9]+]])
2181 // CHECK3-IRBUILDER-NEXT:    call void @__kmpc_dispatch_init_8(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 70, i64 0, i64 [[TMP5]], i64 1, i64 1)
2182 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
2183 // CHECK3-IRBUILDER:       omp.dispatch.cond:
2184 // CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM10:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB8]])
2185 // CHECK3-IRBUILDER-NEXT:    [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_8(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM10]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
2186 // CHECK3-IRBUILDER-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0
2187 // CHECK3-IRBUILDER-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
2188 // CHECK3-IRBUILDER:       omp.dispatch.body:
2189 // CHECK3-IRBUILDER-NEXT:    [[TMP7:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
2190 // CHECK3-IRBUILDER-NEXT:    store i64 [[TMP7]], ptr [[DOTOMP_IV]], align 8
2191 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2192 // CHECK3-IRBUILDER:       omp.inner.for.cond:
2193 // CHECK3-IRBUILDER-NEXT:    [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
2194 // CHECK3-IRBUILDER-NEXT:    [[TMP9:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
2195 // CHECK3-IRBUILDER-NEXT:    [[CMP11:%.*]] = icmp sle i64 [[TMP8]], [[TMP9]]
2196 // CHECK3-IRBUILDER-NEXT:    br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2197 // CHECK3-IRBUILDER:       omp.inner.for.body:
2198 // CHECK3-IRBUILDER-NEXT:    [[TMP10:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
2199 // CHECK3-IRBUILDER-NEXT:    [[CONV12:%.*]] = sext i8 [[TMP10]] to i64
2200 // CHECK3-IRBUILDER-NEXT:    [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
2201 // CHECK3-IRBUILDER-NEXT:    [[DIV13:%.*]] = sdiv i64 [[TMP11]], 11
2202 // CHECK3-IRBUILDER-NEXT:    [[MUL14:%.*]] = mul nsw i64 [[DIV13]], 1
2203 // CHECK3-IRBUILDER-NEXT:    [[ADD15:%.*]] = add nsw i64 [[CONV12]], [[MUL14]]
2204 // CHECK3-IRBUILDER-NEXT:    [[CONV16:%.*]] = trunc i64 [[ADD15]] to i8
2205 // CHECK3-IRBUILDER-NEXT:    store i8 [[CONV16]], ptr [[I8]], align 1
2206 // CHECK3-IRBUILDER-NEXT:    [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
2207 // CHECK3-IRBUILDER-NEXT:    [[TMP13:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
2208 // CHECK3-IRBUILDER-NEXT:    [[DIV17:%.*]] = sdiv i64 [[TMP13]], 11
2209 // CHECK3-IRBUILDER-NEXT:    [[MUL18:%.*]] = mul nsw i64 [[DIV17]], 11
2210 // CHECK3-IRBUILDER-NEXT:    [[SUB19:%.*]] = sub nsw i64 [[TMP12]], [[MUL18]]
2211 // CHECK3-IRBUILDER-NEXT:    [[MUL20:%.*]] = mul nsw i64 [[SUB19]], 1
2212 // CHECK3-IRBUILDER-NEXT:    [[SUB21:%.*]] = sub nsw i64 11, [[MUL20]]
2213 // CHECK3-IRBUILDER-NEXT:    [[CONV22:%.*]] = trunc i64 [[SUB21]] to i32
2214 // CHECK3-IRBUILDER-NEXT:    store i32 [[CONV22]], ptr [[X9]], align 4
2215 // CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM23:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
2216 // CHECK3-IRBUILDER-NEXT:    call void @__kmpc_ordered(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM23]])
2217 // CHECK3-IRBUILDER-NEXT:    [[TMP14:%.*]] = load ptr, ptr [[B_ADDR]], align 8
2218 // CHECK3-IRBUILDER-NEXT:    [[TMP15:%.*]] = load i8, ptr [[I8]], align 1
2219 // CHECK3-IRBUILDER-NEXT:    [[IDXPROM:%.*]] = sext i8 [[TMP15]] to i64
2220 // CHECK3-IRBUILDER-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP14]], i64 [[IDXPROM]]
2221 // CHECK3-IRBUILDER-NEXT:    [[TMP16:%.*]] = load float, ptr [[ARRAYIDX]], align 4
2222 // CHECK3-IRBUILDER-NEXT:    [[TMP17:%.*]] = load ptr, ptr [[C_ADDR]], align 8
2223 // CHECK3-IRBUILDER-NEXT:    [[TMP18:%.*]] = load i8, ptr [[I8]], align 1
2224 // CHECK3-IRBUILDER-NEXT:    [[IDXPROM24:%.*]] = sext i8 [[TMP18]] to i64
2225 // CHECK3-IRBUILDER-NEXT:    [[ARRAYIDX25:%.*]] = getelementptr inbounds float, ptr [[TMP17]], i64 [[IDXPROM24]]
2226 // CHECK3-IRBUILDER-NEXT:    [[TMP19:%.*]] = load float, ptr [[ARRAYIDX25]], align 4
2227 // CHECK3-IRBUILDER-NEXT:    [[MUL26:%.*]] = fmul float [[TMP16]], [[TMP19]]
2228 // CHECK3-IRBUILDER-NEXT:    [[TMP20:%.*]] = load ptr, ptr [[D_ADDR]], align 8
2229 // CHECK3-IRBUILDER-NEXT:    [[TMP21:%.*]] = load i8, ptr [[I8]], align 1
2230 // CHECK3-IRBUILDER-NEXT:    [[IDXPROM27:%.*]] = sext i8 [[TMP21]] to i64
2231 // CHECK3-IRBUILDER-NEXT:    [[ARRAYIDX28:%.*]] = getelementptr inbounds float, ptr [[TMP20]], i64 [[IDXPROM27]]
2232 // CHECK3-IRBUILDER-NEXT:    [[TMP22:%.*]] = load float, ptr [[ARRAYIDX28]], align 4
2233 // CHECK3-IRBUILDER-NEXT:    [[MUL29:%.*]] = fmul float [[MUL26]], [[TMP22]]
2234 // CHECK3-IRBUILDER-NEXT:    [[TMP23:%.*]] = load ptr, ptr [[A_ADDR]], align 8
2235 // CHECK3-IRBUILDER-NEXT:    [[TMP24:%.*]] = load i8, ptr [[I8]], align 1
2236 // CHECK3-IRBUILDER-NEXT:    [[IDXPROM30:%.*]] = sext i8 [[TMP24]] to i64
2237 // CHECK3-IRBUILDER-NEXT:    [[ARRAYIDX31:%.*]] = getelementptr inbounds float, ptr [[TMP23]], i64 [[IDXPROM30]]
2238 // CHECK3-IRBUILDER-NEXT:    store float [[MUL29]], ptr [[ARRAYIDX31]], align 4
2239 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_BODY_ORDERED_AFTER:%.*]]
2240 // CHECK3-IRBUILDER:       omp.inner.for.body.ordered.after:
2241 // CHECK3-IRBUILDER-NEXT:    call void @__kmpc_end_ordered(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM23]])
2242 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2243 // CHECK3-IRBUILDER:       omp.body.continue:
2244 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2245 // CHECK3-IRBUILDER:       omp.inner.for.inc:
2246 // CHECK3-IRBUILDER-NEXT:    [[TMP25:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
2247 // CHECK3-IRBUILDER-NEXT:    [[ADD32:%.*]] = add nsw i64 [[TMP25]], 1
2248 // CHECK3-IRBUILDER-NEXT:    store i64 [[ADD32]], ptr [[DOTOMP_IV]], align 8
2249 // CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM33:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB8]])
2250 // CHECK3-IRBUILDER-NEXT:    call void @__kmpc_dispatch_fini_8(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM33]])
2251 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND]]
2252 // CHECK3-IRBUILDER:       omp.inner.for.end:
2253 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
2254 // CHECK3-IRBUILDER:       omp.dispatch.inc:
2255 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_COND]]
2256 // CHECK3-IRBUILDER:       omp.dispatch.end:
2257 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_PRECOND_END]]
2258 // CHECK3-IRBUILDER:       omp.precond.end:
2259 // CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM34:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
2260 // CHECK3-IRBUILDER-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[OMP_GLOBAL_THREAD_NUM34]])
2261 // CHECK3-IRBUILDER-NEXT:    ret void
2262 //
2263 //
2264 // CHECK3-IRBUILDER-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_
2265 // CHECK3-IRBUILDER-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
2266 // CHECK3-IRBUILDER-NEXT:  entry:
2267 // CHECK3-IRBUILDER-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
2268 // CHECK3-IRBUILDER-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
2269 // CHECK3-IRBUILDER-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
2270 // CHECK3-IRBUILDER-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
2271 // CHECK3-IRBUILDER-NEXT:    [[X:%.*]] = alloca i32, align 4
2272 // CHECK3-IRBUILDER-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2273 // CHECK3-IRBUILDER-NEXT:    [[TMP:%.*]] = alloca i8, align 1
2274 // CHECK3-IRBUILDER-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
2275 // CHECK3-IRBUILDER-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2276 // CHECK3-IRBUILDER-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2277 // CHECK3-IRBUILDER-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2278 // CHECK3-IRBUILDER-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2279 // CHECK3-IRBUILDER-NEXT:    [[I:%.*]] = alloca i8, align 1
2280 // CHECK3-IRBUILDER-NEXT:    [[X2:%.*]] = alloca i32, align 4
2281 // CHECK3-IRBUILDER-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
2282 // CHECK3-IRBUILDER-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
2283 // CHECK3-IRBUILDER-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
2284 // CHECK3-IRBUILDER-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
2285 // CHECK3-IRBUILDER-NEXT:    store i32 0, ptr [[X]], align 4
2286 // CHECK3-IRBUILDER-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
2287 // CHECK3-IRBUILDER-NEXT:    store i32 199, ptr [[DOTOMP_UB]], align 4
2288 // CHECK3-IRBUILDER-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
2289 // CHECK3-IRBUILDER-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2290 // CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB10:[0-9]+]])
2291 // CHECK3-IRBUILDER-NEXT:    call void @__kmpc_dispatch_init_4(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 69, i32 0, i32 199, i32 1, i32 1)
2292 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
2293 // CHECK3-IRBUILDER:       omp.dispatch.cond:
2294 // CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM3:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB10]])
2295 // CHECK3-IRBUILDER-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM3]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
2296 // CHECK3-IRBUILDER-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP0]], 0
2297 // CHECK3-IRBUILDER-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
2298 // CHECK3-IRBUILDER:       omp.dispatch.body:
2299 // CHECK3-IRBUILDER-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
2300 // CHECK3-IRBUILDER-NEXT:    store i32 [[TMP1]], ptr [[DOTOMP_IV]], align 4
2301 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2302 // CHECK3-IRBUILDER:       omp.inner.for.cond:
2303 // CHECK3-IRBUILDER-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2304 // CHECK3-IRBUILDER-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2305 // CHECK3-IRBUILDER-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP2]], [[TMP3]]
2306 // CHECK3-IRBUILDER-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2307 // CHECK3-IRBUILDER:       omp.inner.for.body:
2308 // CHECK3-IRBUILDER-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2309 // CHECK3-IRBUILDER-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP4]], 20
2310 // CHECK3-IRBUILDER-NEXT:    [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
2311 // CHECK3-IRBUILDER-NEXT:    [[ADD:%.*]] = add nsw i32 48, [[MUL]]
2312 // CHECK3-IRBUILDER-NEXT:    [[CONV:%.*]] = trunc i32 [[ADD]] to i8
2313 // CHECK3-IRBUILDER-NEXT:    store i8 [[CONV]], ptr [[I]], align 1
2314 // CHECK3-IRBUILDER-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2315 // CHECK3-IRBUILDER-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2316 // CHECK3-IRBUILDER-NEXT:    [[DIV4:%.*]] = sdiv i32 [[TMP6]], 20
2317 // CHECK3-IRBUILDER-NEXT:    [[MUL5:%.*]] = mul nsw i32 [[DIV4]], 20
2318 // CHECK3-IRBUILDER-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP5]], [[MUL5]]
2319 // CHECK3-IRBUILDER-NEXT:    [[MUL6:%.*]] = mul nsw i32 [[SUB]], 1
2320 // CHECK3-IRBUILDER-NEXT:    [[ADD7:%.*]] = add nsw i32 -10, [[MUL6]]
2321 // CHECK3-IRBUILDER-NEXT:    store i32 [[ADD7]], ptr [[X2]], align 4
2322 // CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM8:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
2323 // CHECK3-IRBUILDER-NEXT:    call void @__kmpc_ordered(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM8]])
2324 // CHECK3-IRBUILDER-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[B_ADDR]], align 8
2325 // CHECK3-IRBUILDER-NEXT:    [[TMP8:%.*]] = load i8, ptr [[I]], align 1
2326 // CHECK3-IRBUILDER-NEXT:    [[IDXPROM:%.*]] = zext i8 [[TMP8]] to i64
2327 // CHECK3-IRBUILDER-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP7]], i64 [[IDXPROM]]
2328 // CHECK3-IRBUILDER-NEXT:    [[TMP9:%.*]] = load float, ptr [[ARRAYIDX]], align 4
2329 // CHECK3-IRBUILDER-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[C_ADDR]], align 8
2330 // CHECK3-IRBUILDER-NEXT:    [[TMP11:%.*]] = load i8, ptr [[I]], align 1
2331 // CHECK3-IRBUILDER-NEXT:    [[IDXPROM9:%.*]] = zext i8 [[TMP11]] to i64
2332 // CHECK3-IRBUILDER-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP10]], i64 [[IDXPROM9]]
2333 // CHECK3-IRBUILDER-NEXT:    [[TMP12:%.*]] = load float, ptr [[ARRAYIDX10]], align 4
2334 // CHECK3-IRBUILDER-NEXT:    [[MUL11:%.*]] = fmul float [[TMP9]], [[TMP12]]
2335 // CHECK3-IRBUILDER-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[D_ADDR]], align 8
2336 // CHECK3-IRBUILDER-NEXT:    [[TMP14:%.*]] = load i8, ptr [[I]], align 1
2337 // CHECK3-IRBUILDER-NEXT:    [[IDXPROM12:%.*]] = zext i8 [[TMP14]] to i64
2338 // CHECK3-IRBUILDER-NEXT:    [[ARRAYIDX13:%.*]] = getelementptr inbounds float, ptr [[TMP13]], i64 [[IDXPROM12]]
2339 // CHECK3-IRBUILDER-NEXT:    [[TMP15:%.*]] = load float, ptr [[ARRAYIDX13]], align 4
2340 // CHECK3-IRBUILDER-NEXT:    [[MUL14:%.*]] = fmul float [[MUL11]], [[TMP15]]
2341 // CHECK3-IRBUILDER-NEXT:    [[TMP16:%.*]] = load ptr, ptr [[A_ADDR]], align 8
2342 // CHECK3-IRBUILDER-NEXT:    [[TMP17:%.*]] = load i8, ptr [[I]], align 1
2343 // CHECK3-IRBUILDER-NEXT:    [[IDXPROM15:%.*]] = zext i8 [[TMP17]] to i64
2344 // CHECK3-IRBUILDER-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds float, ptr [[TMP16]], i64 [[IDXPROM15]]
2345 // CHECK3-IRBUILDER-NEXT:    store float [[MUL14]], ptr [[ARRAYIDX16]], align 4
2346 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_BODY_ORDERED_AFTER:%.*]]
2347 // CHECK3-IRBUILDER:       omp.inner.for.body.ordered.after:
2348 // CHECK3-IRBUILDER-NEXT:    call void @__kmpc_end_ordered(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM8]])
2349 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2350 // CHECK3-IRBUILDER:       omp.body.continue:
2351 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2352 // CHECK3-IRBUILDER:       omp.inner.for.inc:
2353 // CHECK3-IRBUILDER-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2354 // CHECK3-IRBUILDER-NEXT:    [[ADD17:%.*]] = add nsw i32 [[TMP18]], 1
2355 // CHECK3-IRBUILDER-NEXT:    store i32 [[ADD17]], ptr [[DOTOMP_IV]], align 4
2356 // CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM18:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB10]])
2357 // CHECK3-IRBUILDER-NEXT:    call void @__kmpc_dispatch_fini_4(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM18]])
2358 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND]]
2359 // CHECK3-IRBUILDER:       omp.inner.for.end:
2360 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
2361 // CHECK3-IRBUILDER:       omp.dispatch.inc:
2362 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_COND]]
2363 // CHECK3-IRBUILDER:       omp.dispatch.end:
2364 // CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM19:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
2365 // CHECK3-IRBUILDER-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[OMP_GLOBAL_THREAD_NUM19]])
2366 // CHECK3-IRBUILDER-NEXT:    ret void
2367 //
2368 //
2369 // CHECK3-IRBUILDER-LABEL: define {{[^@]+}}@_Z8foo_simdii
2370 // CHECK3-IRBUILDER-SAME: (i32 noundef [[LOW:%.*]], i32 noundef [[UP:%.*]]) #[[ATTR3:[0-9]+]] {
2371 // CHECK3-IRBUILDER-NEXT:  entry:
2372 // CHECK3-IRBUILDER-NEXT:    [[LOW_ADDR:%.*]] = alloca i32, align 4
2373 // CHECK3-IRBUILDER-NEXT:    [[UP_ADDR:%.*]] = alloca i32, align 4
2374 // CHECK3-IRBUILDER-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2375 // CHECK3-IRBUILDER-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
2376 // CHECK3-IRBUILDER-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
2377 // CHECK3-IRBUILDER-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
2378 // CHECK3-IRBUILDER-NEXT:    [[I:%.*]] = alloca i32, align 4
2379 // CHECK3-IRBUILDER-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2380 // CHECK3-IRBUILDER-NEXT:    [[I5:%.*]] = alloca i32, align 4
2381 // CHECK3-IRBUILDER-NEXT:    [[DOTOMP_IV16:%.*]] = alloca i32, align 4
2382 // CHECK3-IRBUILDER-NEXT:    [[_TMP17:%.*]] = alloca i32, align 4
2383 // CHECK3-IRBUILDER-NEXT:    [[DOTCAPTURE_EXPR_18:%.*]] = alloca i32, align 4
2384 // CHECK3-IRBUILDER-NEXT:    [[DOTCAPTURE_EXPR_19:%.*]] = alloca i32, align 4
2385 // CHECK3-IRBUILDER-NEXT:    [[DOTCAPTURE_EXPR_20:%.*]] = alloca i32, align 4
2386 // CHECK3-IRBUILDER-NEXT:    [[I26:%.*]] = alloca i32, align 4
2387 // CHECK3-IRBUILDER-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2388 // CHECK3-IRBUILDER-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2389 // CHECK3-IRBUILDER-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2390 // CHECK3-IRBUILDER-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2391 // CHECK3-IRBUILDER-NEXT:    [[I28:%.*]] = alloca i32, align 4
2392 // CHECK3-IRBUILDER-NEXT:    store i32 [[LOW]], ptr [[LOW_ADDR]], align 4
2393 // CHECK3-IRBUILDER-NEXT:    store i32 [[UP]], ptr [[UP_ADDR]], align 4
2394 // CHECK3-IRBUILDER-NEXT:    [[TMP0:%.*]] = load i32, ptr [[LOW_ADDR]], align 4
2395 // CHECK3-IRBUILDER-NEXT:    store i32 [[TMP0]], ptr [[DOTCAPTURE_EXPR_]], align 4
2396 // CHECK3-IRBUILDER-NEXT:    [[TMP1:%.*]] = load i32, ptr [[UP_ADDR]], align 4
2397 // CHECK3-IRBUILDER-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_1]], align 4
2398 // CHECK3-IRBUILDER-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
2399 // CHECK3-IRBUILDER-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
2400 // CHECK3-IRBUILDER-NEXT:    [[SUB:%.*]] = sub i32 [[TMP2]], [[TMP3]]
2401 // CHECK3-IRBUILDER-NEXT:    [[SUB3:%.*]] = sub i32 [[SUB]], 1
2402 // CHECK3-IRBUILDER-NEXT:    [[ADD:%.*]] = add i32 [[SUB3]], 1
2403 // CHECK3-IRBUILDER-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
2404 // CHECK3-IRBUILDER-NEXT:    [[SUB4:%.*]] = sub i32 [[DIV]], 1
2405 // CHECK3-IRBUILDER-NEXT:    store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 4
2406 // CHECK3-IRBUILDER-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
2407 // CHECK3-IRBUILDER-NEXT:    store i32 [[TMP4]], ptr [[I]], align 4
2408 // CHECK3-IRBUILDER-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
2409 // CHECK3-IRBUILDER-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
2410 // CHECK3-IRBUILDER-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP5]], [[TMP6]]
2411 // CHECK3-IRBUILDER-NEXT:    br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]
2412 // CHECK3-IRBUILDER:       simd.if.then:
2413 // CHECK3-IRBUILDER-NEXT:    store i32 0, ptr [[DOTOMP_IV]], align 4
2414 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2415 // CHECK3-IRBUILDER:       omp.inner.for.cond:
2416 // CHECK3-IRBUILDER-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3:![0-9]+]]
2417 // CHECK3-IRBUILDER-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group [[ACC_GRP3]]
2418 // CHECK3-IRBUILDER-NEXT:    [[ADD6:%.*]] = add i32 [[TMP8]], 1
2419 // CHECK3-IRBUILDER-NEXT:    [[CMP7:%.*]] = icmp ult i32 [[TMP7]], [[ADD6]]
2420 // CHECK3-IRBUILDER-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2421 // CHECK3-IRBUILDER:       omp.inner.for.body:
2422 // CHECK3-IRBUILDER-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group [[ACC_GRP3]]
2423 // CHECK3-IRBUILDER-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]
2424 // CHECK3-IRBUILDER-NEXT:    [[MUL:%.*]] = mul i32 [[TMP10]], 1
2425 // CHECK3-IRBUILDER-NEXT:    [[ADD8:%.*]] = add i32 [[TMP9]], [[MUL]]
2426 // CHECK3-IRBUILDER-NEXT:    store i32 [[ADD8]], ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP3]]
2427 // CHECK3-IRBUILDER-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP3]]
2428 // CHECK3-IRBUILDER-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64
2429 // CHECK3-IRBUILDER-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM]]
2430 // CHECK3-IRBUILDER-NEXT:    store float 0.000000e+00, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]]
2431 // CHECK3-IRBUILDER-NEXT:    call void @__captured_stmt(ptr [[I5]]), !llvm.access.group [[ACC_GRP3]]
2432 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_BODY_ORDERED_AFTER:%.*]]
2433 // CHECK3-IRBUILDER:       omp.inner.for.body.ordered.after:
2434 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2435 // CHECK3-IRBUILDER:       omp.body.continue:
2436 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2437 // CHECK3-IRBUILDER:       omp.inner.for.inc:
2438 // CHECK3-IRBUILDER-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]
2439 // CHECK3-IRBUILDER-NEXT:    [[ADD9:%.*]] = add i32 [[TMP12]], 1
2440 // CHECK3-IRBUILDER-NEXT:    store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]
2441 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
2442 // CHECK3-IRBUILDER:       omp.inner.for.end:
2443 // CHECK3-IRBUILDER-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
2444 // CHECK3-IRBUILDER-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
2445 // CHECK3-IRBUILDER-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
2446 // CHECK3-IRBUILDER-NEXT:    [[SUB10:%.*]] = sub i32 [[TMP14]], [[TMP15]]
2447 // CHECK3-IRBUILDER-NEXT:    [[SUB11:%.*]] = sub i32 [[SUB10]], 1
2448 // CHECK3-IRBUILDER-NEXT:    [[ADD12:%.*]] = add i32 [[SUB11]], 1
2449 // CHECK3-IRBUILDER-NEXT:    [[DIV13:%.*]] = udiv i32 [[ADD12]], 1
2450 // CHECK3-IRBUILDER-NEXT:    [[MUL14:%.*]] = mul i32 [[DIV13]], 1
2451 // CHECK3-IRBUILDER-NEXT:    [[ADD15:%.*]] = add i32 [[TMP13]], [[MUL14]]
2452 // CHECK3-IRBUILDER-NEXT:    store i32 [[ADD15]], ptr [[I5]], align 4
2453 // CHECK3-IRBUILDER-NEXT:    br label [[SIMD_IF_END]]
2454 // CHECK3-IRBUILDER:       simd.if.end:
2455 // CHECK3-IRBUILDER-NEXT:    [[TMP16:%.*]] = load i32, ptr [[LOW_ADDR]], align 4
2456 // CHECK3-IRBUILDER-NEXT:    store i32 [[TMP16]], ptr [[DOTCAPTURE_EXPR_18]], align 4
2457 // CHECK3-IRBUILDER-NEXT:    [[TMP17:%.*]] = load i32, ptr [[UP_ADDR]], align 4
2458 // CHECK3-IRBUILDER-NEXT:    store i32 [[TMP17]], ptr [[DOTCAPTURE_EXPR_19]], align 4
2459 // CHECK3-IRBUILDER-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_19]], align 4
2460 // CHECK3-IRBUILDER-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 4
2461 // CHECK3-IRBUILDER-NEXT:    [[SUB21:%.*]] = sub i32 [[TMP18]], [[TMP19]]
2462 // CHECK3-IRBUILDER-NEXT:    [[SUB22:%.*]] = sub i32 [[SUB21]], 1
2463 // CHECK3-IRBUILDER-NEXT:    [[ADD23:%.*]] = add i32 [[SUB22]], 1
2464 // CHECK3-IRBUILDER-NEXT:    [[DIV24:%.*]] = udiv i32 [[ADD23]], 1
2465 // CHECK3-IRBUILDER-NEXT:    [[SUB25:%.*]] = sub i32 [[DIV24]], 1
2466 // CHECK3-IRBUILDER-NEXT:    store i32 [[SUB25]], ptr [[DOTCAPTURE_EXPR_20]], align 4
2467 // CHECK3-IRBUILDER-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 4
2468 // CHECK3-IRBUILDER-NEXT:    store i32 [[TMP20]], ptr [[I26]], align 4
2469 // CHECK3-IRBUILDER-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 4
2470 // CHECK3-IRBUILDER-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_19]], align 4
2471 // CHECK3-IRBUILDER-NEXT:    [[CMP27:%.*]] = icmp slt i32 [[TMP21]], [[TMP22]]
2472 // CHECK3-IRBUILDER-NEXT:    br i1 [[CMP27]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
2473 // CHECK3-IRBUILDER:       omp.precond.then:
2474 // CHECK3-IRBUILDER-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
2475 // CHECK3-IRBUILDER-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_20]], align 4
2476 // CHECK3-IRBUILDER-NEXT:    store i32 [[TMP23]], ptr [[DOTOMP_UB]], align 4
2477 // CHECK3-IRBUILDER-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
2478 // CHECK3-IRBUILDER-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2479 // CHECK3-IRBUILDER-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_20]], align 4
2480 // CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB12:[0-9]+]])
2481 // CHECK3-IRBUILDER-NEXT:    call void @__kmpc_dispatch_init_4u(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM]], i32 66, i32 0, i32 [[TMP24]], i32 1, i32 1)
2482 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
2483 // CHECK3-IRBUILDER:       omp.dispatch.cond:
2484 // CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM29:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB12]])
2485 // CHECK3-IRBUILDER-NEXT:    [[TMP25:%.*]] = call i32 @__kmpc_dispatch_next_4u(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM29]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
2486 // CHECK3-IRBUILDER-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP25]], 0
2487 // CHECK3-IRBUILDER-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
2488 // CHECK3-IRBUILDER:       omp.dispatch.body:
2489 // CHECK3-IRBUILDER-NEXT:    [[TMP26:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
2490 // CHECK3-IRBUILDER-NEXT:    store i32 [[TMP26]], ptr [[DOTOMP_IV16]], align 4
2491 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND30:%.*]]
2492 // CHECK3-IRBUILDER:       omp.inner.for.cond30:
2493 // CHECK3-IRBUILDER-NEXT:    [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV16]], align 4, !llvm.access.group [[ACC_GRP7:![0-9]+]]
2494 // CHECK3-IRBUILDER-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP7]]
2495 // CHECK3-IRBUILDER-NEXT:    [[ADD31:%.*]] = add i32 [[TMP28]], 1
2496 // CHECK3-IRBUILDER-NEXT:    [[CMP32:%.*]] = icmp ult i32 [[TMP27]], [[ADD31]]
2497 // CHECK3-IRBUILDER-NEXT:    br i1 [[CMP32]], label [[OMP_INNER_FOR_BODY33:%.*]], label [[OMP_INNER_FOR_END42:%.*]]
2498 // CHECK3-IRBUILDER:       omp.inner.for.body33:
2499 // CHECK3-IRBUILDER-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 4, !llvm.access.group [[ACC_GRP7]]
2500 // CHECK3-IRBUILDER-NEXT:    [[TMP30:%.*]] = load i32, ptr [[DOTOMP_IV16]], align 4, !llvm.access.group [[ACC_GRP7]]
2501 // CHECK3-IRBUILDER-NEXT:    [[MUL34:%.*]] = mul i32 [[TMP30]], 1
2502 // CHECK3-IRBUILDER-NEXT:    [[ADD35:%.*]] = add i32 [[TMP29]], [[MUL34]]
2503 // CHECK3-IRBUILDER-NEXT:    store i32 [[ADD35]], ptr [[I28]], align 4, !llvm.access.group [[ACC_GRP7]]
2504 // CHECK3-IRBUILDER-NEXT:    [[TMP31:%.*]] = load i32, ptr [[I28]], align 4, !llvm.access.group [[ACC_GRP7]]
2505 // CHECK3-IRBUILDER-NEXT:    [[IDXPROM36:%.*]] = sext i32 [[TMP31]] to i64
2506 // CHECK3-IRBUILDER-NEXT:    [[ARRAYIDX37:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM36]]
2507 // CHECK3-IRBUILDER-NEXT:    store float 0.000000e+00, ptr [[ARRAYIDX37]], align 4, !llvm.access.group [[ACC_GRP7]]
2508 // CHECK3-IRBUILDER-NEXT:    call void @__captured_stmt.1(ptr [[I28]]), !llvm.access.group [[ACC_GRP7]]
2509 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_BODY33_ORDERED_AFTER:%.*]]
2510 // CHECK3-IRBUILDER:       omp.inner.for.body33.ordered.after:
2511 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_BODY_CONTINUE38:%.*]]
2512 // CHECK3-IRBUILDER:       omp.body.continue38:
2513 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_INC39:%.*]]
2514 // CHECK3-IRBUILDER:       omp.inner.for.inc39:
2515 // CHECK3-IRBUILDER-NEXT:    [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IV16]], align 4, !llvm.access.group [[ACC_GRP7]]
2516 // CHECK3-IRBUILDER-NEXT:    [[ADD40:%.*]] = add i32 [[TMP32]], 1
2517 // CHECK3-IRBUILDER-NEXT:    store i32 [[ADD40]], ptr [[DOTOMP_IV16]], align 4, !llvm.access.group [[ACC_GRP7]]
2518 // CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM41:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB12]])
2519 // CHECK3-IRBUILDER-NEXT:    call void @__kmpc_dispatch_fini_4u(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM41]]), !llvm.access.group [[ACC_GRP7]]
2520 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_INNER_FOR_COND30]], !llvm.loop [[LOOP8:![0-9]+]]
2521 // CHECK3-IRBUILDER:       omp.inner.for.end42:
2522 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
2523 // CHECK3-IRBUILDER:       omp.dispatch.inc:
2524 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_DISPATCH_COND]]
2525 // CHECK3-IRBUILDER:       omp.dispatch.end:
2526 // CHECK3-IRBUILDER-NEXT:    [[TMP33:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
2527 // CHECK3-IRBUILDER-NEXT:    [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0
2528 // CHECK3-IRBUILDER-NEXT:    br i1 [[TMP34]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2529 // CHECK3-IRBUILDER:       .omp.final.then:
2530 // CHECK3-IRBUILDER-NEXT:    [[TMP35:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 4
2531 // CHECK3-IRBUILDER-NEXT:    [[TMP36:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_19]], align 4
2532 // CHECK3-IRBUILDER-NEXT:    [[TMP37:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_18]], align 4
2533 // CHECK3-IRBUILDER-NEXT:    [[SUB43:%.*]] = sub i32 [[TMP36]], [[TMP37]]
2534 // CHECK3-IRBUILDER-NEXT:    [[SUB44:%.*]] = sub i32 [[SUB43]], 1
2535 // CHECK3-IRBUILDER-NEXT:    [[ADD45:%.*]] = add i32 [[SUB44]], 1
2536 // CHECK3-IRBUILDER-NEXT:    [[DIV46:%.*]] = udiv i32 [[ADD45]], 1
2537 // CHECK3-IRBUILDER-NEXT:    [[MUL47:%.*]] = mul i32 [[DIV46]], 1
2538 // CHECK3-IRBUILDER-NEXT:    [[ADD48:%.*]] = add i32 [[TMP35]], [[MUL47]]
2539 // CHECK3-IRBUILDER-NEXT:    store i32 [[ADD48]], ptr [[I28]], align 4
2540 // CHECK3-IRBUILDER-NEXT:    br label [[DOTOMP_FINAL_DONE]]
2541 // CHECK3-IRBUILDER:       .omp.final.done:
2542 // CHECK3-IRBUILDER-NEXT:    br label [[OMP_PRECOND_END]]
2543 // CHECK3-IRBUILDER:       omp.precond.end:
2544 // CHECK3-IRBUILDER-NEXT:    [[OMP_GLOBAL_THREAD_NUM49:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
2545 // CHECK3-IRBUILDER-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[OMP_GLOBAL_THREAD_NUM49]])
2546 // CHECK3-IRBUILDER-NEXT:    ret void
2547 //
2548 //
2549 // CHECK3-IRBUILDER-LABEL: define {{[^@]+}}@__captured_stmt
2550 // CHECK3-IRBUILDER-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR4:[0-9]+]] {
2551 // CHECK3-IRBUILDER-NEXT:  entry:
2552 // CHECK3-IRBUILDER-NEXT:    [[I_ADDR:%.*]] = alloca ptr, align 8
2553 // CHECK3-IRBUILDER-NEXT:    store ptr [[I]], ptr [[I_ADDR]], align 8
2554 // CHECK3-IRBUILDER-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 8
2555 // CHECK3-IRBUILDER-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
2556 // CHECK3-IRBUILDER-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64
2557 // CHECK3-IRBUILDER-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM]]
2558 // CHECK3-IRBUILDER-NEXT:    store float 1.000000e+00, ptr [[ARRAYIDX]], align 4
2559 // CHECK3-IRBUILDER-NEXT:    ret void
2560 //
2561 //
2562 // CHECK3-IRBUILDER-LABEL: define {{[^@]+}}@__captured_stmt.1
2563 // CHECK3-IRBUILDER-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[I:%.*]]) #[[ATTR4]] {
2564 // CHECK3-IRBUILDER-NEXT:  entry:
2565 // CHECK3-IRBUILDER-NEXT:    [[I_ADDR:%.*]] = alloca ptr, align 8
2566 // CHECK3-IRBUILDER-NEXT:    store ptr [[I]], ptr [[I_ADDR]], align 8
2567 // CHECK3-IRBUILDER-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 8
2568 // CHECK3-IRBUILDER-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
2569 // CHECK3-IRBUILDER-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64
2570 // CHECK3-IRBUILDER-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM]]
2571 // CHECK3-IRBUILDER-NEXT:    store float 1.000000e+00, ptr [[ARRAYIDX]], align 4
2572 // CHECK3-IRBUILDER-NEXT:    ret void
2573 //
2574 //
2575 // CHECK5-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_
2576 // CHECK5-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0:[0-9]+]] {
2577 // CHECK5-NEXT:  entry:
2578 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
2579 // CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
2580 // CHECK5-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
2581 // CHECK5-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
2582 // CHECK5-NEXT:    [[I:%.*]] = alloca i32, align 4
2583 // CHECK5-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
2584 // CHECK5-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
2585 // CHECK5-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
2586 // CHECK5-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
2587 // CHECK5-NEXT:    store i32 32000000, ptr [[I]], align 4
2588 // CHECK5-NEXT:    br label [[FOR_COND:%.*]]
2589 // CHECK5:       for.cond:
2590 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, ptr [[I]], align 4
2591 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 33
2592 // CHECK5-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
2593 // CHECK5:       for.body:
2594 // CHECK5-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
2595 // CHECK5-NEXT:    [[TMP2:%.*]] = load i32, ptr [[I]], align 4
2596 // CHECK5-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64
2597 // CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP1]], i64 [[IDXPROM]]
2598 // CHECK5-NEXT:    [[TMP3:%.*]] = load float, ptr [[ARRAYIDX]], align 4
2599 // CHECK5-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[C_ADDR]], align 8
2600 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, ptr [[I]], align 4
2601 // CHECK5-NEXT:    [[IDXPROM1:%.*]] = sext i32 [[TMP5]] to i64
2602 // CHECK5-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[TMP4]], i64 [[IDXPROM1]]
2603 // CHECK5-NEXT:    [[TMP6:%.*]] = load float, ptr [[ARRAYIDX2]], align 4
2604 // CHECK5-NEXT:    [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]]
2605 // CHECK5-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8
2606 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, ptr [[I]], align 4
2607 // CHECK5-NEXT:    [[IDXPROM3:%.*]] = sext i32 [[TMP8]] to i64
2608 // CHECK5-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds float, ptr [[TMP7]], i64 [[IDXPROM3]]
2609 // CHECK5-NEXT:    [[TMP9:%.*]] = load float, ptr [[ARRAYIDX4]], align 4
2610 // CHECK5-NEXT:    [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]]
2611 // CHECK5-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[A_ADDR]], align 8
2612 // CHECK5-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 4
2613 // CHECK5-NEXT:    [[IDXPROM6:%.*]] = sext i32 [[TMP11]] to i64
2614 // CHECK5-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds float, ptr [[TMP10]], i64 [[IDXPROM6]]
2615 // CHECK5-NEXT:    store float [[MUL5]], ptr [[ARRAYIDX7]], align 4
2616 // CHECK5-NEXT:    br label [[FOR_INC:%.*]]
2617 // CHECK5:       for.inc:
2618 // CHECK5-NEXT:    [[TMP12:%.*]] = load i32, ptr [[I]], align 4
2619 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP12]], -7
2620 // CHECK5-NEXT:    store i32 [[ADD]], ptr [[I]], align 4
2621 // CHECK5-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]]
2622 // CHECK5:       for.end:
2623 // CHECK5-NEXT:    ret void
2624 //
2625 //
2626 // CHECK5-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_
2627 // CHECK5-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
2628 // CHECK5-NEXT:  entry:
2629 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
2630 // CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
2631 // CHECK5-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
2632 // CHECK5-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
2633 // CHECK5-NEXT:    [[I:%.*]] = alloca i64, align 8
2634 // CHECK5-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
2635 // CHECK5-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
2636 // CHECK5-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
2637 // CHECK5-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
2638 // CHECK5-NEXT:    store i64 131071, ptr [[I]], align 8
2639 // CHECK5-NEXT:    br label [[FOR_COND:%.*]]
2640 // CHECK5:       for.cond:
2641 // CHECK5-NEXT:    [[TMP0:%.*]] = load i64, ptr [[I]], align 8
2642 // CHECK5-NEXT:    [[CMP:%.*]] = icmp ult i64 [[TMP0]], 2147483647
2643 // CHECK5-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
2644 // CHECK5:       for.body:
2645 // CHECK5-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
2646 // CHECK5-NEXT:    [[TMP2:%.*]] = load i64, ptr [[I]], align 8
2647 // CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP1]], i64 [[TMP2]]
2648 // CHECK5-NEXT:    [[TMP3:%.*]] = load float, ptr [[ARRAYIDX]], align 4
2649 // CHECK5-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[C_ADDR]], align 8
2650 // CHECK5-NEXT:    [[TMP5:%.*]] = load i64, ptr [[I]], align 8
2651 // CHECK5-NEXT:    [[ARRAYIDX1:%.*]] = getelementptr inbounds float, ptr [[TMP4]], i64 [[TMP5]]
2652 // CHECK5-NEXT:    [[TMP6:%.*]] = load float, ptr [[ARRAYIDX1]], align 4
2653 // CHECK5-NEXT:    [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]]
2654 // CHECK5-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8
2655 // CHECK5-NEXT:    [[TMP8:%.*]] = load i64, ptr [[I]], align 8
2656 // CHECK5-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[TMP7]], i64 [[TMP8]]
2657 // CHECK5-NEXT:    [[TMP9:%.*]] = load float, ptr [[ARRAYIDX2]], align 4
2658 // CHECK5-NEXT:    [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]]
2659 // CHECK5-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[A_ADDR]], align 8
2660 // CHECK5-NEXT:    [[TMP11:%.*]] = load i64, ptr [[I]], align 8
2661 // CHECK5-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds float, ptr [[TMP10]], i64 [[TMP11]]
2662 // CHECK5-NEXT:    store float [[MUL3]], ptr [[ARRAYIDX4]], align 4
2663 // CHECK5-NEXT:    br label [[FOR_INC:%.*]]
2664 // CHECK5:       for.inc:
2665 // CHECK5-NEXT:    [[TMP12:%.*]] = load i64, ptr [[I]], align 8
2666 // CHECK5-NEXT:    [[ADD:%.*]] = add i64 [[TMP12]], 127
2667 // CHECK5-NEXT:    store i64 [[ADD]], ptr [[I]], align 8
2668 // CHECK5-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
2669 // CHECK5:       for.end:
2670 // CHECK5-NEXT:    ret void
2671 //
2672 //
2673 // CHECK5-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_
2674 // CHECK5-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
2675 // CHECK5-NEXT:  entry:
2676 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
2677 // CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
2678 // CHECK5-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
2679 // CHECK5-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
2680 // CHECK5-NEXT:    [[X:%.*]] = alloca i32, align 4
2681 // CHECK5-NEXT:    [[Y:%.*]] = alloca i32, align 4
2682 // CHECK5-NEXT:    [[I:%.*]] = alloca i8, align 1
2683 // CHECK5-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
2684 // CHECK5-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
2685 // CHECK5-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
2686 // CHECK5-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
2687 // CHECK5-NEXT:    store i32 0, ptr [[X]], align 4
2688 // CHECK5-NEXT:    store i32 0, ptr [[Y]], align 4
2689 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, ptr [[Y]], align 4
2690 // CHECK5-NEXT:    [[CONV:%.*]] = trunc i32 [[TMP0]] to i8
2691 // CHECK5-NEXT:    store i8 [[CONV]], ptr [[I]], align 1
2692 // CHECK5-NEXT:    br label [[FOR_COND:%.*]]
2693 // CHECK5:       for.cond:
2694 // CHECK5-NEXT:    [[TMP1:%.*]] = load i8, ptr [[I]], align 1
2695 // CHECK5-NEXT:    [[CONV1:%.*]] = sext i8 [[TMP1]] to i32
2696 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sle i32 [[CONV1]], 57
2697 // CHECK5-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END13:%.*]]
2698 // CHECK5:       for.body:
2699 // CHECK5-NEXT:    store i32 11, ptr [[X]], align 4
2700 // CHECK5-NEXT:    br label [[FOR_COND2:%.*]]
2701 // CHECK5:       for.cond2:
2702 // CHECK5-NEXT:    [[TMP2:%.*]] = load i32, ptr [[X]], align 4
2703 // CHECK5-NEXT:    [[CMP3:%.*]] = icmp ugt i32 [[TMP2]], 0
2704 // CHECK5-NEXT:    br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END:%.*]]
2705 // CHECK5:       for.body4:
2706 // CHECK5-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[B_ADDR]], align 8
2707 // CHECK5-NEXT:    [[TMP4:%.*]] = load i8, ptr [[I]], align 1
2708 // CHECK5-NEXT:    [[IDXPROM:%.*]] = sext i8 [[TMP4]] to i64
2709 // CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP3]], i64 [[IDXPROM]]
2710 // CHECK5-NEXT:    [[TMP5:%.*]] = load float, ptr [[ARRAYIDX]], align 4
2711 // CHECK5-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[C_ADDR]], align 8
2712 // CHECK5-NEXT:    [[TMP7:%.*]] = load i8, ptr [[I]], align 1
2713 // CHECK5-NEXT:    [[IDXPROM5:%.*]] = sext i8 [[TMP7]] to i64
2714 // CHECK5-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP6]], i64 [[IDXPROM5]]
2715 // CHECK5-NEXT:    [[TMP8:%.*]] = load float, ptr [[ARRAYIDX6]], align 4
2716 // CHECK5-NEXT:    [[MUL:%.*]] = fmul float [[TMP5]], [[TMP8]]
2717 // CHECK5-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[D_ADDR]], align 8
2718 // CHECK5-NEXT:    [[TMP10:%.*]] = load i8, ptr [[I]], align 1
2719 // CHECK5-NEXT:    [[IDXPROM7:%.*]] = sext i8 [[TMP10]] to i64
2720 // CHECK5-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds float, ptr [[TMP9]], i64 [[IDXPROM7]]
2721 // CHECK5-NEXT:    [[TMP11:%.*]] = load float, ptr [[ARRAYIDX8]], align 4
2722 // CHECK5-NEXT:    [[MUL9:%.*]] = fmul float [[MUL]], [[TMP11]]
2723 // CHECK5-NEXT:    [[TMP12:%.*]] = load ptr, ptr [[A_ADDR]], align 8
2724 // CHECK5-NEXT:    [[TMP13:%.*]] = load i8, ptr [[I]], align 1
2725 // CHECK5-NEXT:    [[IDXPROM10:%.*]] = sext i8 [[TMP13]] to i64
2726 // CHECK5-NEXT:    [[ARRAYIDX11:%.*]] = getelementptr inbounds float, ptr [[TMP12]], i64 [[IDXPROM10]]
2727 // CHECK5-NEXT:    store float [[MUL9]], ptr [[ARRAYIDX11]], align 4
2728 // CHECK5-NEXT:    br label [[FOR_INC:%.*]]
2729 // CHECK5:       for.inc:
2730 // CHECK5-NEXT:    [[TMP14:%.*]] = load i32, ptr [[X]], align 4
2731 // CHECK5-NEXT:    [[DEC:%.*]] = add i32 [[TMP14]], -1
2732 // CHECK5-NEXT:    store i32 [[DEC]], ptr [[X]], align 4
2733 // CHECK5-NEXT:    br label [[FOR_COND2]], !llvm.loop [[LOOP5:![0-9]+]]
2734 // CHECK5:       for.end:
2735 // CHECK5-NEXT:    br label [[FOR_INC12:%.*]]
2736 // CHECK5:       for.inc12:
2737 // CHECK5-NEXT:    [[TMP15:%.*]] = load i8, ptr [[I]], align 1
2738 // CHECK5-NEXT:    [[INC:%.*]] = add i8 [[TMP15]], 1
2739 // CHECK5-NEXT:    store i8 [[INC]], ptr [[I]], align 1
2740 // CHECK5-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
2741 // CHECK5:       for.end13:
2742 // CHECK5-NEXT:    ret void
2743 //
2744 //
2745 // CHECK5-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_
2746 // CHECK5-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
2747 // CHECK5-NEXT:  entry:
2748 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
2749 // CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
2750 // CHECK5-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
2751 // CHECK5-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
2752 // CHECK5-NEXT:    [[X:%.*]] = alloca i32, align 4
2753 // CHECK5-NEXT:    [[I:%.*]] = alloca i8, align 1
2754 // CHECK5-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
2755 // CHECK5-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
2756 // CHECK5-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
2757 // CHECK5-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
2758 // CHECK5-NEXT:    store i32 0, ptr [[X]], align 4
2759 // CHECK5-NEXT:    store i8 48, ptr [[I]], align 1
2760 // CHECK5-NEXT:    br label [[FOR_COND:%.*]]
2761 // CHECK5:       for.cond:
2762 // CHECK5-NEXT:    [[TMP0:%.*]] = load i8, ptr [[I]], align 1
2763 // CHECK5-NEXT:    [[CONV:%.*]] = zext i8 [[TMP0]] to i32
2764 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sle i32 [[CONV]], 57
2765 // CHECK5-NEXT:    br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END13:%.*]]
2766 // CHECK5:       for.body:
2767 // CHECK5-NEXT:    store i32 -10, ptr [[X]], align 4
2768 // CHECK5-NEXT:    br label [[FOR_COND1:%.*]]
2769 // CHECK5:       for.cond1:
2770 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, ptr [[X]], align 4
2771 // CHECK5-NEXT:    [[CMP2:%.*]] = icmp slt i32 [[TMP1]], 10
2772 // CHECK5-NEXT:    br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]]
2773 // CHECK5:       for.body3:
2774 // CHECK5-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8
2775 // CHECK5-NEXT:    [[TMP3:%.*]] = load i8, ptr [[I]], align 1
2776 // CHECK5-NEXT:    [[IDXPROM:%.*]] = zext i8 [[TMP3]] to i64
2777 // CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 [[IDXPROM]]
2778 // CHECK5-NEXT:    [[TMP4:%.*]] = load float, ptr [[ARRAYIDX]], align 4
2779 // CHECK5-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[C_ADDR]], align 8
2780 // CHECK5-NEXT:    [[TMP6:%.*]] = load i8, ptr [[I]], align 1
2781 // CHECK5-NEXT:    [[IDXPROM4:%.*]] = zext i8 [[TMP6]] to i64
2782 // CHECK5-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds float, ptr [[TMP5]], i64 [[IDXPROM4]]
2783 // CHECK5-NEXT:    [[TMP7:%.*]] = load float, ptr [[ARRAYIDX5]], align 4
2784 // CHECK5-NEXT:    [[MUL:%.*]] = fmul float [[TMP4]], [[TMP7]]
2785 // CHECK5-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[D_ADDR]], align 8
2786 // CHECK5-NEXT:    [[TMP9:%.*]] = load i8, ptr [[I]], align 1
2787 // CHECK5-NEXT:    [[IDXPROM6:%.*]] = zext i8 [[TMP9]] to i64
2788 // CHECK5-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds float, ptr [[TMP8]], i64 [[IDXPROM6]]
2789 // CHECK5-NEXT:    [[TMP10:%.*]] = load float, ptr [[ARRAYIDX7]], align 4
2790 // CHECK5-NEXT:    [[MUL8:%.*]] = fmul float [[MUL]], [[TMP10]]
2791 // CHECK5-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[A_ADDR]], align 8
2792 // CHECK5-NEXT:    [[TMP12:%.*]] = load i8, ptr [[I]], align 1
2793 // CHECK5-NEXT:    [[IDXPROM9:%.*]] = zext i8 [[TMP12]] to i64
2794 // CHECK5-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP11]], i64 [[IDXPROM9]]
2795 // CHECK5-NEXT:    store float [[MUL8]], ptr [[ARRAYIDX10]], align 4
2796 // CHECK5-NEXT:    br label [[FOR_INC:%.*]]
2797 // CHECK5:       for.inc:
2798 // CHECK5-NEXT:    [[TMP13:%.*]] = load i32, ptr [[X]], align 4
2799 // CHECK5-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP13]], 1
2800 // CHECK5-NEXT:    store i32 [[INC]], ptr [[X]], align 4
2801 // CHECK5-NEXT:    br label [[FOR_COND1]], !llvm.loop [[LOOP7:![0-9]+]]
2802 // CHECK5:       for.end:
2803 // CHECK5-NEXT:    br label [[FOR_INC11:%.*]]
2804 // CHECK5:       for.inc11:
2805 // CHECK5-NEXT:    [[TMP14:%.*]] = load i8, ptr [[I]], align 1
2806 // CHECK5-NEXT:    [[INC12:%.*]] = add i8 [[TMP14]], 1
2807 // CHECK5-NEXT:    store i8 [[INC12]], ptr [[I]], align 1
2808 // CHECK5-NEXT:    br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
2809 // CHECK5:       for.end13:
2810 // CHECK5-NEXT:    ret void
2811 //
2812 //
2813 // CHECK5-LABEL: define {{[^@]+}}@_Z8foo_simdii
2814 // CHECK5-SAME: (i32 noundef [[LOW:%.*]], i32 noundef [[UP:%.*]]) #[[ATTR0]] {
2815 // CHECK5-NEXT:  entry:
2816 // CHECK5-NEXT:    [[LOW_ADDR:%.*]] = alloca i32, align 4
2817 // CHECK5-NEXT:    [[UP_ADDR:%.*]] = alloca i32, align 4
2818 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2819 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
2820 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
2821 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
2822 // CHECK5-NEXT:    [[I:%.*]] = alloca i32, align 4
2823 // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2824 // CHECK5-NEXT:    [[I5:%.*]] = alloca i32, align 4
2825 // CHECK5-NEXT:    [[_TMP18:%.*]] = alloca i32, align 4
2826 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR_19:%.*]] = alloca i32, align 4
2827 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR_20:%.*]] = alloca i32, align 4
2828 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR_21:%.*]] = alloca i32, align 4
2829 // CHECK5-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2830 // CHECK5-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2831 // CHECK5-NEXT:    [[I27:%.*]] = alloca i32, align 4
2832 // CHECK5-NEXT:    [[DOTOMP_IV30:%.*]] = alloca i32, align 4
2833 // CHECK5-NEXT:    [[I31:%.*]] = alloca i32, align 4
2834 // CHECK5-NEXT:    store i32 [[LOW]], ptr [[LOW_ADDR]], align 4
2835 // CHECK5-NEXT:    store i32 [[UP]], ptr [[UP_ADDR]], align 4
2836 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, ptr [[LOW_ADDR]], align 4
2837 // CHECK5-NEXT:    store i32 [[TMP0]], ptr [[DOTCAPTURE_EXPR_]], align 4
2838 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, ptr [[UP_ADDR]], align 4
2839 // CHECK5-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_1]], align 4
2840 // CHECK5-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
2841 // CHECK5-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
2842 // CHECK5-NEXT:    [[SUB:%.*]] = sub i32 [[TMP2]], [[TMP3]]
2843 // CHECK5-NEXT:    [[SUB3:%.*]] = sub i32 [[SUB]], 1
2844 // CHECK5-NEXT:    [[ADD:%.*]] = add i32 [[SUB3]], 1
2845 // CHECK5-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
2846 // CHECK5-NEXT:    [[SUB4:%.*]] = sub i32 [[DIV]], 1
2847 // CHECK5-NEXT:    store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 4
2848 // CHECK5-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
2849 // CHECK5-NEXT:    store i32 [[TMP4]], ptr [[I]], align 4
2850 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
2851 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
2852 // CHECK5-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP5]], [[TMP6]]
2853 // CHECK5-NEXT:    br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]
2854 // CHECK5:       simd.if.then:
2855 // CHECK5-NEXT:    store i32 0, ptr [[DOTOMP_IV]], align 4
2856 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2857 // CHECK5:       omp.inner.for.cond:
2858 // CHECK5-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9:![0-9]+]]
2859 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group [[ACC_GRP9]]
2860 // CHECK5-NEXT:    [[ADD6:%.*]] = add i32 [[TMP8]], 1
2861 // CHECK5-NEXT:    [[CMP7:%.*]] = icmp ult i32 [[TMP7]], [[ADD6]]
2862 // CHECK5-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2863 // CHECK5:       omp.inner.for.body:
2864 // CHECK5-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group [[ACC_GRP9]]
2865 // CHECK5-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]]
2866 // CHECK5-NEXT:    [[MUL:%.*]] = mul i32 [[TMP10]], 1
2867 // CHECK5-NEXT:    [[ADD8:%.*]] = add i32 [[TMP9]], [[MUL]]
2868 // CHECK5-NEXT:    store i32 [[ADD8]], ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP9]]
2869 // CHECK5-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP9]]
2870 // CHECK5-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64
2871 // CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM]]
2872 // CHECK5-NEXT:    store float 0.000000e+00, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP9]]
2873 // CHECK5-NEXT:    [[TMP12:%.*]] = load i32, ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP9]]
2874 // CHECK5-NEXT:    [[IDXPROM9:%.*]] = sext i32 [[TMP12]] to i64
2875 // CHECK5-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM9]]
2876 // CHECK5-NEXT:    store float 1.000000e+00, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP9]]
2877 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2878 // CHECK5:       omp.body.continue:
2879 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2880 // CHECK5:       omp.inner.for.inc:
2881 // CHECK5-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]]
2882 // CHECK5-NEXT:    [[ADD11:%.*]] = add i32 [[TMP13]], 1
2883 // CHECK5-NEXT:    store i32 [[ADD11]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]]
2884 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
2885 // CHECK5:       omp.inner.for.end:
2886 // CHECK5-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
2887 // CHECK5-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
2888 // CHECK5-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
2889 // CHECK5-NEXT:    [[SUB12:%.*]] = sub i32 [[TMP15]], [[TMP16]]
2890 // CHECK5-NEXT:    [[SUB13:%.*]] = sub i32 [[SUB12]], 1
2891 // CHECK5-NEXT:    [[ADD14:%.*]] = add i32 [[SUB13]], 1
2892 // CHECK5-NEXT:    [[DIV15:%.*]] = udiv i32 [[ADD14]], 1
2893 // CHECK5-NEXT:    [[MUL16:%.*]] = mul i32 [[DIV15]], 1
2894 // CHECK5-NEXT:    [[ADD17:%.*]] = add i32 [[TMP14]], [[MUL16]]
2895 // CHECK5-NEXT:    store i32 [[ADD17]], ptr [[I5]], align 4
2896 // CHECK5-NEXT:    br label [[SIMD_IF_END]]
2897 // CHECK5:       simd.if.end:
2898 // CHECK5-NEXT:    [[TMP17:%.*]] = load i32, ptr [[LOW_ADDR]], align 4
2899 // CHECK5-NEXT:    store i32 [[TMP17]], ptr [[DOTCAPTURE_EXPR_19]], align 4
2900 // CHECK5-NEXT:    [[TMP18:%.*]] = load i32, ptr [[UP_ADDR]], align 4
2901 // CHECK5-NEXT:    store i32 [[TMP18]], ptr [[DOTCAPTURE_EXPR_20]], align 4
2902 // CHECK5-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_20]], align 4
2903 // CHECK5-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_19]], align 4
2904 // CHECK5-NEXT:    [[SUB22:%.*]] = sub i32 [[TMP19]], [[TMP20]]
2905 // CHECK5-NEXT:    [[SUB23:%.*]] = sub i32 [[SUB22]], 1
2906 // CHECK5-NEXT:    [[ADD24:%.*]] = add i32 [[SUB23]], 1
2907 // CHECK5-NEXT:    [[DIV25:%.*]] = udiv i32 [[ADD24]], 1
2908 // CHECK5-NEXT:    [[SUB26:%.*]] = sub i32 [[DIV25]], 1
2909 // CHECK5-NEXT:    store i32 [[SUB26]], ptr [[DOTCAPTURE_EXPR_21]], align 4
2910 // CHECK5-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
2911 // CHECK5-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_21]], align 4
2912 // CHECK5-NEXT:    store i32 [[TMP21]], ptr [[DOTOMP_UB]], align 4
2913 // CHECK5-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_19]], align 4
2914 // CHECK5-NEXT:    store i32 [[TMP22]], ptr [[I27]], align 4
2915 // CHECK5-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_19]], align 4
2916 // CHECK5-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_20]], align 4
2917 // CHECK5-NEXT:    [[CMP28:%.*]] = icmp slt i32 [[TMP23]], [[TMP24]]
2918 // CHECK5-NEXT:    br i1 [[CMP28]], label [[SIMD_IF_THEN29:%.*]], label [[SIMD_IF_END52:%.*]]
2919 // CHECK5:       simd.if.then29:
2920 // CHECK5-NEXT:    [[TMP25:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
2921 // CHECK5-NEXT:    store i32 [[TMP25]], ptr [[DOTOMP_IV30]], align 4
2922 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND32:%.*]]
2923 // CHECK5:       omp.inner.for.cond32:
2924 // CHECK5-NEXT:    [[TMP26:%.*]] = load i32, ptr [[DOTOMP_IV30]], align 4, !llvm.access.group [[ACC_GRP13:![0-9]+]]
2925 // CHECK5-NEXT:    [[TMP27:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP13]]
2926 // CHECK5-NEXT:    [[ADD33:%.*]] = add i32 [[TMP27]], 1
2927 // CHECK5-NEXT:    [[CMP34:%.*]] = icmp ult i32 [[TMP26]], [[ADD33]]
2928 // CHECK5-NEXT:    br i1 [[CMP34]], label [[OMP_INNER_FOR_BODY35:%.*]], label [[OMP_INNER_FOR_END45:%.*]]
2929 // CHECK5:       omp.inner.for.body35:
2930 // CHECK5-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_19]], align 4, !llvm.access.group [[ACC_GRP13]]
2931 // CHECK5-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IV30]], align 4, !llvm.access.group [[ACC_GRP13]]
2932 // CHECK5-NEXT:    [[MUL36:%.*]] = mul i32 [[TMP29]], 1
2933 // CHECK5-NEXT:    [[ADD37:%.*]] = add i32 [[TMP28]], [[MUL36]]
2934 // CHECK5-NEXT:    store i32 [[ADD37]], ptr [[I31]], align 4, !llvm.access.group [[ACC_GRP13]]
2935 // CHECK5-NEXT:    [[TMP30:%.*]] = load i32, ptr [[I31]], align 4, !llvm.access.group [[ACC_GRP13]]
2936 // CHECK5-NEXT:    [[IDXPROM38:%.*]] = sext i32 [[TMP30]] to i64
2937 // CHECK5-NEXT:    [[ARRAYIDX39:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM38]]
2938 // CHECK5-NEXT:    store float 0.000000e+00, ptr [[ARRAYIDX39]], align 4, !llvm.access.group [[ACC_GRP13]]
2939 // CHECK5-NEXT:    [[TMP31:%.*]] = load i32, ptr [[I31]], align 4, !llvm.access.group [[ACC_GRP13]]
2940 // CHECK5-NEXT:    [[IDXPROM40:%.*]] = sext i32 [[TMP31]] to i64
2941 // CHECK5-NEXT:    [[ARRAYIDX41:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM40]]
2942 // CHECK5-NEXT:    store float 1.000000e+00, ptr [[ARRAYIDX41]], align 4, !llvm.access.group [[ACC_GRP13]]
2943 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE42:%.*]]
2944 // CHECK5:       omp.body.continue42:
2945 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC43:%.*]]
2946 // CHECK5:       omp.inner.for.inc43:
2947 // CHECK5-NEXT:    [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IV30]], align 4, !llvm.access.group [[ACC_GRP13]]
2948 // CHECK5-NEXT:    [[ADD44:%.*]] = add i32 [[TMP32]], 1
2949 // CHECK5-NEXT:    store i32 [[ADD44]], ptr [[DOTOMP_IV30]], align 4, !llvm.access.group [[ACC_GRP13]]
2950 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND32]], !llvm.loop [[LOOP14:![0-9]+]]
2951 // CHECK5:       omp.inner.for.end45:
2952 // CHECK5-NEXT:    [[TMP33:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_19]], align 4
2953 // CHECK5-NEXT:    [[TMP34:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_20]], align 4
2954 // CHECK5-NEXT:    [[TMP35:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_19]], align 4
2955 // CHECK5-NEXT:    [[SUB46:%.*]] = sub i32 [[TMP34]], [[TMP35]]
2956 // CHECK5-NEXT:    [[SUB47:%.*]] = sub i32 [[SUB46]], 1
2957 // CHECK5-NEXT:    [[ADD48:%.*]] = add i32 [[SUB47]], 1
2958 // CHECK5-NEXT:    [[DIV49:%.*]] = udiv i32 [[ADD48]], 1
2959 // CHECK5-NEXT:    [[MUL50:%.*]] = mul i32 [[DIV49]], 1
2960 // CHECK5-NEXT:    [[ADD51:%.*]] = add i32 [[TMP33]], [[MUL50]]
2961 // CHECK5-NEXT:    store i32 [[ADD51]], ptr [[I31]], align 4
2962 // CHECK5-NEXT:    br label [[SIMD_IF_END52]]
2963 // CHECK5:       simd.if.end52:
2964 // CHECK5-NEXT:    ret void
2965 //