clang/test/OpenMP/parallel_copyin_codegen.cpp

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
   2 // RUN: %clang_cc1 -verify -fopenmp -fnoopenmp-use-tls -x c++ -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1
   3 // RUN: %clang_cc1 -fopenmp -fnoopenmp-use-tls -x c++ -std=c++11 -triple x86_64-linux -emit-pch -o %t %s
   4 // RUN: %clang_cc1 -fopenmp -fnoopenmp-use-tls -x c++ -triple x86_64-linux -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1
   5 // RUN: %clang_cc1 -verify -fopenmp -fnoopenmp-use-tls -x c++ -std=c++11 -DLAMBDA -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3
   6 // RUN: %clang_cc1 -verify -fopenmp -fnoopenmp-use-tls -x c++ -fblocks -DBLOCKS -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK4
   7 // RUN: %clang_cc1 -verify -fopenmp -fnoopenmp-use-tls -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5
   8
   9 // RUN: %clang_cc1 -verify -fopenmp-simd -fnoopenmp-use-tls -x c++ -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  10 // RUN: %clang_cc1 -fopenmp-simd -fnoopenmp-use-tls -x c++ -std=c++11 -triple x86_64-linux -emit-pch -o %t %s
  11 // RUN: %clang_cc1 -fopenmp-simd -fnoopenmp-use-tls -x c++ -triple x86_64-linux -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  12 // RUN: %clang_cc1 -verify -fopenmp-simd -fnoopenmp-use-tls -x c++ -std=c++11 -DLAMBDA -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  13 // RUN: %clang_cc1 -verify -fopenmp-simd -fnoopenmp-use-tls -x c++ -fblocks -DBLOCKS -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  14 // RUN: %clang_cc1 -verify -fopenmp-simd -fnoopenmp-use-tls -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  15
  16 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11
  17 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-linux -emit-pch -o %t %s
  18 // RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-linux -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11
  19 // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13
  20 // RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK14
  21 // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DARRAY -triple x86_64-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15
  22 // RUN: %clang_cc1 -verify -fopenmp -x c++ -DNESTED -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK16
  23
  24 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  25 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-linux -emit-pch -o %t %s
  26 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-linux -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  27 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  28 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  29 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  30 // expected-no-diagnostics
  31 #if !defined(ARRAY) && !defined(NESTED)
  32 #ifndef HEADER
  33 #define HEADER
  34
  35 volatile int g __attribute__((aligned(128))) = 1212;
  36 #pragma omp threadprivate(g)
  37
  38 template <class T>
  39 struct S {
  40   T f;
  41   S(T a) : f(a + g) {}
  42   S() : f(g) {}
  43   S &operator=(const S &) { return *this; };
  44   operator T() { return T(); }
  45   ~S() {}
  46 };
  47
  48
  49
  50 template <typename T>
  51 T tmain() {
  52   S<T> test;
  53   test = S<T>();
  54   static T t_var __attribute__((aligned(128))) = 333;
  55   static T vec[] __attribute__((aligned(128))) = {3, 3};
  56   static S<T> s_arr[] __attribute__((aligned(128))) = {1, 2};
  57   static S<T> var __attribute__((aligned(128))) (3);
  58 #pragma omp threadprivate(t_var, vec, s_arr, var)
  59 #pragma omp parallel copyin(t_var, vec, s_arr, var)
  60   {
  61     vec[0] = t_var;
  62     s_arr[0] = var;
  63   }
  64 #pragma omp parallel copyin(t_var)
  65   {}
  66   return T();
  67 }
  68
  69 int main() {
  70 #ifdef LAMBDA
  71   [&]() {
  72
  73
  74 #pragma omp parallel copyin(g)
  75   {
  76
  77     // threadprivate_g = g;
  78
  79
  80     g = 1;
  81
  82     [&]() {
  83       g = 2;
  84
  85     }();
  86   }
  87   }();
  88   return 0;
  89 #elif defined(BLOCKS)
  90
  91   ^{
  92
  93
  94 #pragma omp parallel copyin(g)
  95   {
  96
  97     // threadprivate_g = g;
  98
  99
 100     g = 1;
 101
 102
 103     ^{
 104       g = 2;
 105
 106     }();
 107   }
 108   }();
 109   return 0;
 110 #else
 111   S<float> test;
 112   test = S<float>();
 113   static int t_var = 1122;
 114   static int vec[] = {1, 2};
 115   static S<float> s_arr[] = {1, 2};
 116   static S<float> var(3);
 117 #pragma omp threadprivate(t_var, vec, s_arr, var)
 118 #pragma omp parallel copyin(t_var, vec, s_arr, var)
 119   {
 120     vec[0] = t_var;
 121     s_arr[0] = var;
 122   }
 123 #pragma omp parallel copyin(t_var) default(none)
 124   ++t_var;
 125   return tmain<int>();
 126 #endif
 127 }
 128
 129
 130
 131
 132
 133 // threadprivate_t_var = t_var;
 134
 135
 136
 137 // threadprivate_vec = vec;
 138
 139
 140 // threadprivate_s_arr = s_arr;
 141
 142
 143 // threadprivate_var = var;
 144
 145
 146
 147
 148
 149
 150 // threadprivate_t_var = t_var;
 151
 152
 153
 154
 155
 156
 157
 158 // threadprivate_t_var = t_var;
 159
 160
 161
 162 // threadprivate_vec = vec;
 163
 164
 165 // threadprivate_s_arr = s_arr;
 166
 167
 168 // threadprivate_var = var;
 169
 170
 171
 172
 173
 174
 175 // threadprivate_t_var = t_var;
 176
 177
 178
 179
 180
 181 #endif
 182 #elif defined(ARRAY)
 183
 184 struct St {
 185   int a, b;
 186   St() : a(0), b(0) {}
 187   St &operator=(const St &) { return *this; };
 188   ~St() {}
 189 };
 190
 191 void array_func() {
 192   static int a[2];
 193   static St s[2];
 194
 195
 196 #pragma omp threadprivate(a, s)
 197 #pragma omp parallel copyin(a, s)
 198   ;
 199 }
 200 #elif defined(NESTED)
 201 int t_init();
 202 int t = t_init();
 203 #pragma omp threadprivate(t)
 204 void foo() {
 205 #pragma omp parallel
 206 #pragma omp parallel copyin(t)
 207   ++t;
 208 }
 209
 210 #endif // NESTED
 211
 212 // CHECK1-LABEL: define {{[^@]+}}@main
 213 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
 214 // CHECK1-NEXT:  entry:
 215 // CHECK1-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
 216 // CHECK1-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4
 217 // CHECK1-NEXT:    [[REF_TMP:%.*]] = alloca [[STRUCT_S]], align 4
 218 // CHECK1-NEXT:    store i32 0, ptr [[RETVAL]], align 4
 219 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])
 220 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]])
 221 // CHECK1-NEXT:    [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIfEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]], ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]])
 222 // CHECK1-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR3:[0-9]+]]
 223 // CHECK1-NEXT:    [[TMP0:%.*]] = load atomic i8, ptr @_ZGVZ4mainE5s_arr acquire, align 8
 224 // CHECK1-NEXT:    [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0
 225 // CHECK1-NEXT:    br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF3:![0-9]+]]
 226 // CHECK1:       init.check:
 227 // CHECK1-NEXT:    [[TMP1:%.*]] = call i32 @__cxa_guard_acquire(ptr @_ZGVZ4mainE5s_arr) #[[ATTR3]]
 228 // CHECK1-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0
 229 // CHECK1-NEXT:    br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]]
 230 // CHECK1:       init:
 231 // CHECK1-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
 232 // CHECK1-NEXT:    call void @__kmpc_threadprivate_register(ptr @[[GLOB1]], ptr @_ZZ4mainE5s_arr, ptr @.__kmpc_global_ctor_., ptr null, ptr @.__kmpc_global_dtor_.)
 233 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @_ZZ4mainE5s_arr, float noundef 1.000000e+00)
 234 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S]], ptr @_ZZ4mainE5s_arr, i64 1), float noundef 2.000000e+00)
 235 // CHECK1-NEXT:    [[TMP3:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR3]]
 236 // CHECK1-NEXT:    call void @__cxa_guard_release(ptr @_ZGVZ4mainE5s_arr) #[[ATTR3]]
 237 // CHECK1-NEXT:    br label [[INIT_END]]
 238 // CHECK1:       init.end:
 239 // CHECK1-NEXT:    [[TMP4:%.*]] = load atomic i8, ptr @_ZGVZ4mainE3var acquire, align 8
 240 // CHECK1-NEXT:    [[GUARD_UNINITIALIZED1:%.*]] = icmp eq i8 [[TMP4]], 0
 241 // CHECK1-NEXT:    br i1 [[GUARD_UNINITIALIZED1]], label [[INIT_CHECK2:%.*]], label [[INIT_END5:%.*]], !prof [[PROF3]]
 242 // CHECK1:       init.check2:
 243 // CHECK1-NEXT:    [[TMP5:%.*]] = call i32 @__cxa_guard_acquire(ptr @_ZGVZ4mainE3var) #[[ATTR3]]
 244 // CHECK1-NEXT:    [[TOBOOL3:%.*]] = icmp ne i32 [[TMP5]], 0
 245 // CHECK1-NEXT:    br i1 [[TOBOOL3]], label [[INIT4:%.*]], label [[INIT_END5]]
 246 // CHECK1:       init4:
 247 // CHECK1-NEXT:    [[TMP6:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
 248 // CHECK1-NEXT:    call void @__kmpc_threadprivate_register(ptr @[[GLOB1]], ptr @_ZZ4mainE3var, ptr @.__kmpc_global_ctor_..1, ptr null, ptr @.__kmpc_global_dtor_..2)
 249 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @_ZZ4mainE3var, float noundef 3.000000e+00)
 250 // CHECK1-NEXT:    [[TMP7:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @_ZZ4mainE3var, ptr @__dso_handle) #[[ATTR3]]
 251 // CHECK1-NEXT:    call void @__cxa_guard_release(ptr @_ZGVZ4mainE3var) #[[ATTR3]]
 252 // CHECK1-NEXT:    br label [[INIT_END5]]
 253 // CHECK1:       init.end5:
 254 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @main.omp_outlined)
 255 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @main.omp_outlined.3)
 256 // CHECK1-NEXT:    [[CALL6:%.*]] = call noundef i32 @_Z5tmainIiET_v()
 257 // CHECK1-NEXT:    store i32 [[CALL6]], ptr [[RETVAL]], align 4
 258 // CHECK1-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]]
 259 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[RETVAL]], align 4
 260 // CHECK1-NEXT:    ret i32 [[TMP8]]
 261 //
 262 //
 263 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
 264 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
 265 // CHECK1-NEXT:  entry:
 266 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 267 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 268 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 269 // CHECK1-NEXT:    call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
 270 // CHECK1-NEXT:    ret void
 271 //
 272 //
 273 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEaSERKS0_
 274 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 {
 275 // CHECK1-NEXT:  entry:
 276 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 277 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
 278 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 279 // CHECK1-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
 280 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 281 // CHECK1-NEXT:    ret ptr [[THIS1]]
 282 //
 283 //
 284 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
 285 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
 286 // CHECK1-NEXT:  entry:
 287 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 288 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 289 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 290 // CHECK1-NEXT:    call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]]
 291 // CHECK1-NEXT:    ret void
 292 //
 293 //
 294 // CHECK1-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_.
 295 // CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR4:[0-9]+]] section ".text.startup" {
 296 // CHECK1-NEXT:  entry:
 297 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
 298 // CHECK1-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
 299 // CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8
 300 // CHECK1-NEXT:    [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP1]], i64 0, i64 0
 301 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00)
 302 // CHECK1-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[ARRAYINIT_BEGIN]], i64 1
 303 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00)
 304 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8
 305 // CHECK1-NEXT:    ret ptr [[TMP2]]
 306 //
 307 //
 308 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
 309 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
 310 // CHECK1-NEXT:  entry:
 311 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 312 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
 313 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 314 // CHECK1-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
 315 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 316 // CHECK1-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
 317 // CHECK1-NEXT:    call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
 318 // CHECK1-NEXT:    ret void
 319 //
 320 //
 321 // CHECK1-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_.
 322 // CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" {
 323 // CHECK1-NEXT:  entry:
 324 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
 325 // CHECK1-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
 326 // CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8
 327 // CHECK1-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[TMP1]], i64 2
 328 // CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
 329 // CHECK1:       arraydestroy.body:
 330 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
 331 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
 332 // CHECK1-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]]
 333 // CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[TMP1]]
 334 // CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
 335 // CHECK1:       arraydestroy.done1:
 336 // CHECK1-NEXT:    ret void
 337 //
 338 //
 339 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
 340 // CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" {
 341 // CHECK1-NEXT:  entry:
 342 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
 343 // CHECK1-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
 344 // CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
 345 // CHECK1:       arraydestroy.body:
 346 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @_ZZ4mainE5s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
 347 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
 348 // CHECK1-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]]
 349 // CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @_ZZ4mainE5s_arr
 350 // CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
 351 // CHECK1:       arraydestroy.done1:
 352 // CHECK1-NEXT:    ret void
 353 //
 354 //
 355 // CHECK1-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_..1
 356 // CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" {
 357 // CHECK1-NEXT:  entry:
 358 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
 359 // CHECK1-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
 360 // CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8
 361 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[TMP1]], float noundef 3.000000e+00)
 362 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8
 363 // CHECK1-NEXT:    ret ptr [[TMP2]]
 364 //
 365 //
 366 // CHECK1-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_..2
 367 // CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" {
 368 // CHECK1-NEXT:  entry:
 369 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
 370 // CHECK1-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
 371 // CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8
 372 // CHECK1-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP1]]) #[[ATTR3]]
 373 // CHECK1-NEXT:    ret void
 374 //
 375 //
 376 // CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined
 377 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5:[0-9]+]] {
 378 // CHECK1-NEXT:  entry:
 379 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 380 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 381 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 382 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 383 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 384 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
 385 // CHECK1-NEXT:    [[TMP2:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP1]], ptr @_ZZ4mainE5t_var, i64 4, ptr @_ZZ4mainE5t_var.cache.)
 386 // CHECK1-NEXT:    [[TMP3:%.*]] = ptrtoint ptr [[TMP2]] to i64
 387 // CHECK1-NEXT:    [[TMP4:%.*]] = icmp ne i64 ptrtoint (ptr @_ZZ4mainE5t_var to i64), [[TMP3]]
 388 // CHECK1-NEXT:    br i1 [[TMP4]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]]
 389 // CHECK1:       copyin.not.master:
 390 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr @_ZZ4mainE5t_var, align 4
 391 // CHECK1-NEXT:    store i32 [[TMP5]], ptr [[TMP2]], align 4
 392 // CHECK1-NEXT:    [[TMP6:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP1]], ptr @_ZZ4mainE3vec, i64 8, ptr @_ZZ4mainE3vec.cache.)
 393 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP6]], ptr align 4 @_ZZ4mainE3vec, i64 8, i1 false)
 394 // CHECK1-NEXT:    [[TMP7:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP1]], ptr @_ZZ4mainE5s_arr, i64 8, ptr @_ZZ4mainE5s_arr.cache.)
 395 // CHECK1-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP7]], i32 0, i32 0
 396 // CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i64 2
 397 // CHECK1-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP8]]
 398 // CHECK1-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE1:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
 399 // CHECK1:       omp.arraycpy.body:
 400 // CHECK1-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ @_ZZ4mainE5s_arr, [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
 401 // CHECK1-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
 402 // CHECK1-NEXT:    [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIfEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]])
 403 // CHECK1-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
 404 // CHECK1-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
 405 // CHECK1-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]]
 406 // CHECK1-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE1]], label [[OMP_ARRAYCPY_BODY]]
 407 // CHECK1:       omp.arraycpy.done1:
 408 // CHECK1-NEXT:    [[TMP9:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP1]], ptr @_ZZ4mainE3var, i64 4, ptr @_ZZ4mainE3var.cache.)
 409 // CHECK1-NEXT:    [[CALL2:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIfEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[TMP9]], ptr noundef nonnull align 4 dereferenceable(4) @_ZZ4mainE3var)
 410 // CHECK1-NEXT:    br label [[COPYIN_NOT_MASTER_END]]
 411 // CHECK1:       copyin.not.master.end:
 412 // CHECK1-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB2:[0-9]+]], i32 [[TMP1]])
 413 // CHECK1-NEXT:    [[TMP10:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP1]], ptr @_ZZ4mainE5t_var, i64 4, ptr @_ZZ4mainE5t_var.cache.)
 414 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4
 415 // CHECK1-NEXT:    [[TMP12:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP1]], ptr @_ZZ4mainE3vec, i64 8, ptr @_ZZ4mainE3vec.cache.)
 416 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP12]], i64 0, i64 0
 417 // CHECK1-NEXT:    store i32 [[TMP11]], ptr [[ARRAYIDX]], align 4
 418 // CHECK1-NEXT:    [[TMP13:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP1]], ptr @_ZZ4mainE3var, i64 4, ptr @_ZZ4mainE3var.cache.)
 419 // CHECK1-NEXT:    [[TMP14:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP1]], ptr @_ZZ4mainE5s_arr, i64 8, ptr @_ZZ4mainE5s_arr.cache.)
 420 // CHECK1-NEXT:    [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP14]], i64 0, i64 0
 421 // CHECK1-NEXT:    [[CALL4:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIfEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYIDX3]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP13]])
 422 // CHECK1-NEXT:    ret void
 423 //
 424 //
 425 // CHECK1-LABEL: define {{[^@]+}}@main.omp_outlined.3
 426 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] {
 427 // CHECK1-NEXT:  entry:
 428 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 429 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 430 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 431 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 432 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 433 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
 434 // CHECK1-NEXT:    [[TMP2:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP1]], ptr @_ZZ4mainE5t_var, i64 4, ptr @_ZZ4mainE5t_var.cache.)
 435 // CHECK1-NEXT:    [[TMP3:%.*]] = ptrtoint ptr [[TMP2]] to i64
 436 // CHECK1-NEXT:    [[TMP4:%.*]] = icmp ne i64 ptrtoint (ptr @_ZZ4mainE5t_var to i64), [[TMP3]]
 437 // CHECK1-NEXT:    br i1 [[TMP4]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]]
 438 // CHECK1:       copyin.not.master:
 439 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr @_ZZ4mainE5t_var, align 4
 440 // CHECK1-NEXT:    store i32 [[TMP5]], ptr [[TMP2]], align 4
 441 // CHECK1-NEXT:    br label [[COPYIN_NOT_MASTER_END]]
 442 // CHECK1:       copyin.not.master.end:
 443 // CHECK1-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB2]], i32 [[TMP1]])
 444 // CHECK1-NEXT:    [[TMP6:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP1]], ptr @_ZZ4mainE5t_var, i64 4, ptr @_ZZ4mainE5t_var.cache.)
 445 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
 446 // CHECK1-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP7]], 1
 447 // CHECK1-NEXT:    store i32 [[INC]], ptr [[TMP6]], align 4
 448 // CHECK1-NEXT:    ret void
 449 //
 450 //
 451 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
 452 // CHECK1-SAME: () #[[ATTR2]] comdat {
 453 // CHECK1-NEXT:  entry:
 454 // CHECK1-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
 455 // CHECK1-NEXT:    [[REF_TMP:%.*]] = alloca [[STRUCT_S_0]], align 4
 456 // CHECK1-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])
 457 // CHECK1-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]])
 458 // CHECK1-NEXT:    [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIiEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]], ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]])
 459 // CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR3]]
 460 // CHECK1-NEXT:    [[TMP0:%.*]] = load atomic i8, ptr @_ZGVZ5tmainIiET_vE5s_arr acquire, align 8
 461 // CHECK1-NEXT:    [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0
 462 // CHECK1-NEXT:    br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF3]]
 463 // CHECK1:       init.check:
 464 // CHECK1-NEXT:    [[TMP1:%.*]] = call i32 @__cxa_guard_acquire(ptr @_ZGVZ5tmainIiET_vE5s_arr) #[[ATTR3]]
 465 // CHECK1-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0
 466 // CHECK1-NEXT:    br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]]
 467 // CHECK1:       init:
 468 // CHECK1-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
 469 // CHECK1-NEXT:    call void @__kmpc_threadprivate_register(ptr @[[GLOB1]], ptr @_ZZ5tmainIiET_vE5s_arr, ptr @.__kmpc_global_ctor_..4, ptr null, ptr @.__kmpc_global_dtor_..5)
 470 // CHECK1-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) @_ZZ5tmainIiET_vE5s_arr, i32 noundef 1)
 471 // CHECK1-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S_0]], ptr @_ZZ5tmainIiET_vE5s_arr, i64 1), i32 noundef 2)
 472 // CHECK1-NEXT:    [[TMP3:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor.6, ptr null, ptr @__dso_handle) #[[ATTR3]]
 473 // CHECK1-NEXT:    call void @__cxa_guard_release(ptr @_ZGVZ5tmainIiET_vE5s_arr) #[[ATTR3]]
 474 // CHECK1-NEXT:    br label [[INIT_END]]
 475 // CHECK1:       init.end:
 476 // CHECK1-NEXT:    [[TMP4:%.*]] = load atomic i8, ptr @_ZGVZ5tmainIiET_vE3var acquire, align 8
 477 // CHECK1-NEXT:    [[GUARD_UNINITIALIZED1:%.*]] = icmp eq i8 [[TMP4]], 0
 478 // CHECK1-NEXT:    br i1 [[GUARD_UNINITIALIZED1]], label [[INIT_CHECK2:%.*]], label [[INIT_END5:%.*]], !prof [[PROF3]]
 479 // CHECK1:       init.check2:
 480 // CHECK1-NEXT:    [[TMP5:%.*]] = call i32 @__cxa_guard_acquire(ptr @_ZGVZ5tmainIiET_vE3var) #[[ATTR3]]
 481 // CHECK1-NEXT:    [[TOBOOL3:%.*]] = icmp ne i32 [[TMP5]], 0
 482 // CHECK1-NEXT:    br i1 [[TOBOOL3]], label [[INIT4:%.*]], label [[INIT_END5]]
 483 // CHECK1:       init4:
 484 // CHECK1-NEXT:    [[TMP6:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
 485 // CHECK1-NEXT:    call void @__kmpc_threadprivate_register(ptr @[[GLOB1]], ptr @_ZZ5tmainIiET_vE3var, ptr @.__kmpc_global_ctor_..7, ptr null, ptr @.__kmpc_global_dtor_..8)
 486 // CHECK1-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) @_ZZ5tmainIiET_vE3var, i32 noundef 3)
 487 // CHECK1-NEXT:    [[TMP7:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIiED1Ev, ptr @_ZZ5tmainIiET_vE3var, ptr @__dso_handle) #[[ATTR3]]
 488 // CHECK1-NEXT:    call void @__cxa_guard_release(ptr @_ZGVZ5tmainIiET_vE3var) #[[ATTR3]]
 489 // CHECK1-NEXT:    br label [[INIT_END5]]
 490 // CHECK1:       init.end5:
 491 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @_Z5tmainIiET_v.omp_outlined)
 492 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @_Z5tmainIiET_v.omp_outlined.9)
 493 // CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]]
 494 // CHECK1-NEXT:    ret i32 0
 495 //
 496 //
 497 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
 498 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
 499 // CHECK1-NEXT:  entry:
 500 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 501 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
 502 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 503 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 504 // CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
 505 // CHECK1-NEXT:    [[TMP1:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @g, i64 4, ptr @g.cache.)
 506 // CHECK1-NEXT:    [[TMP2:%.*]] = load volatile i32, ptr [[TMP1]], align 128
 507 // CHECK1-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP2]] to float
 508 // CHECK1-NEXT:    store float [[CONV]], ptr [[F]], align 4
 509 // CHECK1-NEXT:    ret void
 510 //
 511 //
 512 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
 513 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
 514 // CHECK1-NEXT:  entry:
 515 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 516 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 517 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 518 // CHECK1-NEXT:    ret void
 519 //
 520 //
 521 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
 522 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
 523 // CHECK1-NEXT:  entry:
 524 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 525 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
 526 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
 527 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 528 // CHECK1-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
 529 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 530 // CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
 531 // CHECK1-NEXT:    [[TMP1:%.*]] = load float, ptr [[A_ADDR]], align 4
 532 // CHECK1-NEXT:    [[TMP2:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @g, i64 4, ptr @g.cache.)
 533 // CHECK1-NEXT:    [[TMP3:%.*]] = load volatile i32, ptr [[TMP2]], align 128
 534 // CHECK1-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP3]] to float
 535 // CHECK1-NEXT:    [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]]
 536 // CHECK1-NEXT:    store float [[ADD]], ptr [[F]], align 4
 537 // CHECK1-NEXT:    ret void
 538 //
 539 //
 540 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
 541 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
 542 // CHECK1-NEXT:  entry:
 543 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 544 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 545 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 546 // CHECK1-NEXT:    call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
 547 // CHECK1-NEXT:    ret void
 548 //
 549 //
 550 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEaSERKS0_
 551 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR2]] comdat align 2 {
 552 // CHECK1-NEXT:  entry:
 553 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 554 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
 555 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 556 // CHECK1-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
 557 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 558 // CHECK1-NEXT:    ret ptr [[THIS1]]
 559 //
 560 //
 561 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
 562 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
 563 // CHECK1-NEXT:  entry:
 564 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 565 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 566 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 567 // CHECK1-NEXT:    call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]]
 568 // CHECK1-NEXT:    ret void
 569 //
 570 //
 571 // CHECK1-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_..4
 572 // CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" {
 573 // CHECK1-NEXT:  entry:
 574 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
 575 // CHECK1-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
 576 // CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8
 577 // CHECK1-NEXT:    [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP1]], i64 0, i64 0
 578 // CHECK1-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef 1)
 579 // CHECK1-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[ARRAYINIT_BEGIN]], i64 1
 580 // CHECK1-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)
 581 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8
 582 // CHECK1-NEXT:    ret ptr [[TMP2]]
 583 //
 584 //
 585 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
 586 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
 587 // CHECK1-NEXT:  entry:
 588 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 589 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
 590 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 591 // CHECK1-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
 592 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 593 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
 594 // CHECK1-NEXT:    call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])
 595 // CHECK1-NEXT:    ret void
 596 //
 597 //
 598 // CHECK1-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_..5
 599 // CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" {
 600 // CHECK1-NEXT:  entry:
 601 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
 602 // CHECK1-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
 603 // CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8
 604 // CHECK1-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[TMP1]], i64 2
 605 // CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
 606 // CHECK1:       arraydestroy.body:
 607 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
 608 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
 609 // CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]]
 610 // CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[TMP1]]
 611 // CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
 612 // CHECK1:       arraydestroy.done1:
 613 // CHECK1-NEXT:    ret void
 614 //
 615 //
 616 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor.6
 617 // CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" {
 618 // CHECK1-NEXT:  entry:
 619 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
 620 // CHECK1-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
 621 // CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
 622 // CHECK1:       arraydestroy.body:
 623 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S_0:%.*]], ptr @_ZZ5tmainIiET_vE5s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
 624 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
 625 // CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]]
 626 // CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @_ZZ5tmainIiET_vE5s_arr
 627 // CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
 628 // CHECK1:       arraydestroy.done1:
 629 // CHECK1-NEXT:    ret void
 630 //
 631 //
 632 // CHECK1-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_..7
 633 // CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" {
 634 // CHECK1-NEXT:  entry:
 635 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
 636 // CHECK1-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
 637 // CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8
 638 // CHECK1-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[TMP1]], i32 noundef 3)
 639 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8
 640 // CHECK1-NEXT:    ret ptr [[TMP2]]
 641 //
 642 //
 643 // CHECK1-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_..8
 644 // CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" {
 645 // CHECK1-NEXT:  entry:
 646 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
 647 // CHECK1-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
 648 // CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8
 649 // CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP1]]) #[[ATTR3]]
 650 // CHECK1-NEXT:    ret void
 651 //
 652 //
 653 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v.omp_outlined
 654 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] {
 655 // CHECK1-NEXT:  entry:
 656 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 657 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 658 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 659 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 660 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 661 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
 662 // CHECK1-NEXT:    [[TMP2:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP1]], ptr @_ZZ5tmainIiET_vE5t_var, i64 4, ptr @_ZZ5tmainIiET_vE5t_var.cache.)
 663 // CHECK1-NEXT:    [[TMP3:%.*]] = ptrtoint ptr [[TMP2]] to i64
 664 // CHECK1-NEXT:    [[TMP4:%.*]] = icmp ne i64 ptrtoint (ptr @_ZZ5tmainIiET_vE5t_var to i64), [[TMP3]]
 665 // CHECK1-NEXT:    br i1 [[TMP4]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]]
 666 // CHECK1:       copyin.not.master:
 667 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr @_ZZ5tmainIiET_vE5t_var, align 128
 668 // CHECK1-NEXT:    store i32 [[TMP5]], ptr [[TMP2]], align 128
 669 // CHECK1-NEXT:    [[TMP6:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP1]], ptr @_ZZ5tmainIiET_vE3vec, i64 8, ptr @_ZZ5tmainIiET_vE3vec.cache.)
 670 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 128 [[TMP6]], ptr align 128 @_ZZ5tmainIiET_vE3vec, i64 8, i1 false)
 671 // CHECK1-NEXT:    [[TMP7:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP1]], ptr @_ZZ5tmainIiET_vE5s_arr, i64 8, ptr @_ZZ5tmainIiET_vE5s_arr.cache.)
 672 // CHECK1-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP7]], i32 0, i32 0
 673 // CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[ARRAY_BEGIN]], i64 2
 674 // CHECK1-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP8]]
 675 // CHECK1-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE1:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
 676 // CHECK1:       omp.arraycpy.body:
 677 // CHECK1-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ @_ZZ5tmainIiET_vE5s_arr, [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
 678 // CHECK1-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
 679 // CHECK1-NEXT:    [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIiEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]])
 680 // CHECK1-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
 681 // CHECK1-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
 682 // CHECK1-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP8]]
 683 // CHECK1-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE1]], label [[OMP_ARRAYCPY_BODY]]
 684 // CHECK1:       omp.arraycpy.done1:
 685 // CHECK1-NEXT:    [[TMP9:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP1]], ptr @_ZZ5tmainIiET_vE3var, i64 4, ptr @_ZZ5tmainIiET_vE3var.cache.)
 686 // CHECK1-NEXT:    [[CALL2:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIiEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[TMP9]], ptr noundef nonnull align 4 dereferenceable(4) @_ZZ5tmainIiET_vE3var)
 687 // CHECK1-NEXT:    br label [[COPYIN_NOT_MASTER_END]]
 688 // CHECK1:       copyin.not.master.end:
 689 // CHECK1-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB2]], i32 [[TMP1]])
 690 // CHECK1-NEXT:    [[TMP10:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP1]], ptr @_ZZ5tmainIiET_vE5t_var, i64 4, ptr @_ZZ5tmainIiET_vE5t_var.cache.)
 691 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 128
 692 // CHECK1-NEXT:    [[TMP12:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP1]], ptr @_ZZ5tmainIiET_vE3vec, i64 8, ptr @_ZZ5tmainIiET_vE3vec.cache.)
 693 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP12]], i64 0, i64 0
 694 // CHECK1-NEXT:    store i32 [[TMP11]], ptr [[ARRAYIDX]], align 128
 695 // CHECK1-NEXT:    [[TMP13:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP1]], ptr @_ZZ5tmainIiET_vE3var, i64 4, ptr @_ZZ5tmainIiET_vE3var.cache.)
 696 // CHECK1-NEXT:    [[TMP14:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP1]], ptr @_ZZ5tmainIiET_vE5s_arr, i64 8, ptr @_ZZ5tmainIiET_vE5s_arr.cache.)
 697 // CHECK1-NEXT:    [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP14]], i64 0, i64 0
 698 // CHECK1-NEXT:    [[CALL4:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIiEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYIDX3]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP13]])
 699 // CHECK1-NEXT:    ret void
 700 //
 701 //
 702 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v.omp_outlined.9
 703 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] {
 704 // CHECK1-NEXT:  entry:
 705 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 706 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 707 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 708 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 709 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 710 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
 711 // CHECK1-NEXT:    [[TMP2:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP1]], ptr @_ZZ5tmainIiET_vE5t_var, i64 4, ptr @_ZZ5tmainIiET_vE5t_var.cache.)
 712 // CHECK1-NEXT:    [[TMP3:%.*]] = ptrtoint ptr [[TMP2]] to i64
 713 // CHECK1-NEXT:    [[TMP4:%.*]] = icmp ne i64 ptrtoint (ptr @_ZZ5tmainIiET_vE5t_var to i64), [[TMP3]]
 714 // CHECK1-NEXT:    br i1 [[TMP4]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]]
 715 // CHECK1:       copyin.not.master:
 716 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr @_ZZ5tmainIiET_vE5t_var, align 128
 717 // CHECK1-NEXT:    store i32 [[TMP5]], ptr [[TMP2]], align 128
 718 // CHECK1-NEXT:    br label [[COPYIN_NOT_MASTER_END]]
 719 // CHECK1:       copyin.not.master.end:
 720 // CHECK1-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB2]], i32 [[TMP1]])
 721 // CHECK1-NEXT:    ret void
 722 //
 723 //
 724 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
 725 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
 726 // CHECK1-NEXT:  entry:
 727 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 728 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
 729 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 730 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 731 // CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
 732 // CHECK1-NEXT:    [[TMP1:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @g, i64 4, ptr @g.cache.)
 733 // CHECK1-NEXT:    [[TMP2:%.*]] = load volatile i32, ptr [[TMP1]], align 128
 734 // CHECK1-NEXT:    store i32 [[TMP2]], ptr [[F]], align 4
 735 // CHECK1-NEXT:    ret void
 736 //
 737 //
 738 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
 739 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
 740 // CHECK1-NEXT:  entry:
 741 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 742 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 743 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 744 // CHECK1-NEXT:    ret void
 745 //
 746 //
 747 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
 748 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
 749 // CHECK1-NEXT:  entry:
 750 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 751 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
 752 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
 753 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 754 // CHECK1-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
 755 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 756 // CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
 757 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
 758 // CHECK1-NEXT:    [[TMP2:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @g, i64 4, ptr @g.cache.)
 759 // CHECK1-NEXT:    [[TMP3:%.*]] = load volatile i32, ptr [[TMP2]], align 128
 760 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP3]]
 761 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[F]], align 4
 762 // CHECK1-NEXT:    ret void
 763 //
 764 //
 765 // CHECK3-LABEL: define {{[^@]+}}@main
 766 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] {
 767 // CHECK3-NEXT:  entry:
 768 // CHECK3-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
 769 // CHECK3-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
 770 // CHECK3-NEXT:    store i32 0, ptr [[RETVAL]], align 4
 771 // CHECK3-NEXT:    call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])
 772 // CHECK3-NEXT:    ret i32 0
 773 //
 774 //
 775 // CHECK4-LABEL: define {{[^@]+}}@main
 776 // CHECK4-SAME: () #[[ATTR1:[0-9]+]] {
 777 // CHECK4-NEXT:  entry:
 778 // CHECK4-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
 779 // CHECK4-NEXT:    store i32 0, ptr [[RETVAL]], align 4
 780 // CHECK4-NEXT:    [[TMP0:%.*]] = load ptr, ptr getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr @__block_literal_global, i32 0, i32 3), align 8
 781 // CHECK4-NEXT:    call void [[TMP0]](ptr noundef @__block_literal_global)
 782 // CHECK4-NEXT:    ret i32 0
 783 //
 784 //
 785 // CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke
 786 // CHECK4-SAME: (ptr noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] {
 787 // CHECK4-NEXT:  entry:
 788 // CHECK4-NEXT:    [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 8
 789 // CHECK4-NEXT:    [[BLOCK_ADDR:%.*]] = alloca ptr, align 8
 790 // CHECK4-NEXT:    store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8
 791 // CHECK4-NEXT:    store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 8
 792 // CHECK4-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 0, ptr @__main_block_invoke.omp_outlined)
 793 // CHECK4-NEXT:    ret void
 794 //
 795 //
 796 // CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke.omp_outlined
 797 // CHECK4-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] {
 798 // CHECK4-NEXT:  entry:
 799 // CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 800 // CHECK4-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 801 // CHECK4-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 802 // CHECK4-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 803 // CHECK4-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 804 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
 805 // CHECK4-NEXT:    [[TMP2:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP1]], ptr @g, i64 4, ptr @g.cache.)
 806 // CHECK4-NEXT:    [[TMP3:%.*]] = ptrtoint ptr [[TMP2]] to i64
 807 // CHECK4-NEXT:    [[TMP4:%.*]] = icmp ne i64 ptrtoint (ptr @g to i64), [[TMP3]]
 808 // CHECK4-NEXT:    br i1 [[TMP4]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]]
 809 // CHECK4:       copyin.not.master:
 810 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, ptr @g, align 128
 811 // CHECK4-NEXT:    store volatile i32 [[TMP5]], ptr [[TMP2]], align 128
 812 // CHECK4-NEXT:    br label [[COPYIN_NOT_MASTER_END]]
 813 // CHECK4:       copyin.not.master.end:
 814 // CHECK4-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB2:[0-9]+]], i32 [[TMP1]])
 815 // CHECK4-NEXT:    [[TMP6:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP1]], ptr @g, i64 4, ptr @g.cache.)
 816 // CHECK4-NEXT:    store volatile i32 1, ptr [[TMP6]], align 128
 817 // CHECK4-NEXT:    [[TMP7:%.*]] = load ptr, ptr getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr @__block_literal_global.2, i32 0, i32 3), align 8
 818 // CHECK4-NEXT:    call void [[TMP7]](ptr noundef @__block_literal_global.2)
 819 // CHECK4-NEXT:    ret void
 820 //
 821 //
 822 // CHECK4-LABEL: define {{[^@]+}}@g_block_invoke
 823 // CHECK4-SAME: (ptr noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] {
 824 // CHECK4-NEXT:  entry:
 825 // CHECK4-NEXT:    [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 8
 826 // CHECK4-NEXT:    [[BLOCK_ADDR:%.*]] = alloca ptr, align 8
 827 // CHECK4-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
 828 // CHECK4-NEXT:    store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8
 829 // CHECK4-NEXT:    store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 8
 830 // CHECK4-NEXT:    [[TMP1:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @g, i64 4, ptr @g.cache.)
 831 // CHECK4-NEXT:    store volatile i32 2, ptr [[TMP1]], align 128
 832 // CHECK4-NEXT:    ret void
 833 //
 834 //
 835 // CHECK5-LABEL: define {{[^@]+}}@_Z10array_funcv
 836 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] {
 837 // CHECK5-NEXT:  entry:
 838 // CHECK5-NEXT:    [[TMP0:%.*]] = load atomic i8, ptr @_ZGVZ10array_funcvE1s acquire, align 8
 839 // CHECK5-NEXT:    [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0
 840 // CHECK5-NEXT:    br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF3:![0-9]+]]
 841 // CHECK5:       init.check:
 842 // CHECK5-NEXT:    [[TMP1:%.*]] = call i32 @__cxa_guard_acquire(ptr @_ZGVZ10array_funcvE1s) #[[ATTR1:[0-9]+]]
 843 // CHECK5-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0
 844 // CHECK5-NEXT:    br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]]
 845 // CHECK5:       init:
 846 // CHECK5-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
 847 // CHECK5-NEXT:    call void @__kmpc_threadprivate_register(ptr @[[GLOB1]], ptr @_ZZ10array_funcvE1s, ptr @.__kmpc_global_ctor_., ptr null, ptr @.__kmpc_global_dtor_.)
 848 // CHECK5-NEXT:    br label [[ARRAYCTOR_LOOP:%.*]]
 849 // CHECK5:       arrayctor.loop:
 850 // CHECK5-NEXT:    [[ARRAYCTOR_CUR:%.*]] = phi ptr [ @_ZZ10array_funcvE1s, [[INIT]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
 851 // CHECK5-NEXT:    call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[ARRAYCTOR_CUR]])
 852 // CHECK5-NEXT:    [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[ARRAYCTOR_CUR]], i64 1
 853 // CHECK5-NEXT:    [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], getelementptr inbounds ([[STRUCT_ST]], ptr @_ZZ10array_funcvE1s, i64 2)
 854 // CHECK5-NEXT:    br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
 855 // CHECK5:       arrayctor.cont:
 856 // CHECK5-NEXT:    [[TMP3:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR1]]
 857 // CHECK5-NEXT:    call void @__cxa_guard_release(ptr @_ZGVZ10array_funcvE1s) #[[ATTR1]]
 858 // CHECK5-NEXT:    br label [[INIT_END]]
 859 // CHECK5:       init.end:
 860 // CHECK5-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @_Z10array_funcv.omp_outlined)
 861 // CHECK5-NEXT:    ret void
 862 //
 863 //
 864 // CHECK5-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_.
 865 // CHECK5-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR2:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" {
 866 // CHECK5-NEXT:  entry:
 867 // CHECK5-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
 868 // CHECK5-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
 869 // CHECK5-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8
 870 // CHECK5-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.St], ptr [[TMP1]], i32 0, i32 0
 871 // CHECK5-NEXT:    [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[ARRAY_BEGIN]], i64 2
 872 // CHECK5-NEXT:    br label [[ARRAYCTOR_LOOP:%.*]]
 873 // CHECK5:       arrayctor.loop:
 874 // CHECK5-NEXT:    [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
 875 // CHECK5-NEXT:    call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[ARRAYCTOR_CUR]])
 876 // CHECK5-NEXT:    [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_ST]], ptr [[ARRAYCTOR_CUR]], i64 1
 877 // CHECK5-NEXT:    [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
 878 // CHECK5-NEXT:    br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
 879 // CHECK5:       arrayctor.cont:
 880 // CHECK5-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8
 881 // CHECK5-NEXT:    ret ptr [[TMP2]]
 882 //
 883 //
 884 // CHECK5-LABEL: define {{[^@]+}}@_ZN2StC1Ev
 885 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR3:[0-9]+]] align 2 {
 886 // CHECK5-NEXT:  entry:
 887 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 888 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 889 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 890 // CHECK5-NEXT:    call void @_ZN2StC2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]])
 891 // CHECK5-NEXT:    ret void
 892 //
 893 //
 894 // CHECK5-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_.
 895 // CHECK5-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR2]] section "__TEXT,__StaticInit,regular,pure_instructions" {
 896 // CHECK5-NEXT:  entry:
 897 // CHECK5-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
 898 // CHECK5-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
 899 // CHECK5-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8
 900 // CHECK5-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[TMP1]], i64 2
 901 // CHECK5-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
 902 // CHECK5:       arraydestroy.body:
 903 // CHECK5-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
 904 // CHECK5-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_ST]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
 905 // CHECK5-NEXT:    call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR1]]
 906 // CHECK5-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[TMP1]]
 907 // CHECK5-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
 908 // CHECK5:       arraydestroy.done1:
 909 // CHECK5-NEXT:    ret void
 910 //
 911 //
 912 // CHECK5-LABEL: define {{[^@]+}}@_ZN2StD1Ev
 913 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] align 2 {
 914 // CHECK5-NEXT:  entry:
 915 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 916 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 917 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 918 // CHECK5-NEXT:    call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR1]]
 919 // CHECK5-NEXT:    ret void
 920 //
 921 //
 922 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
 923 // CHECK5-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR2]] section "__TEXT,__StaticInit,regular,pure_instructions" {
 924 // CHECK5-NEXT:  entry:
 925 // CHECK5-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
 926 // CHECK5-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
 927 // CHECK5-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
 928 // CHECK5:       arraydestroy.body:
 929 // CHECK5-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_ST:%.*]], ptr @_ZZ10array_funcvE1s, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
 930 // CHECK5-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_ST]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
 931 // CHECK5-NEXT:    call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR1]]
 932 // CHECK5-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @_ZZ10array_funcvE1s
 933 // CHECK5-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
 934 // CHECK5:       arraydestroy.done1:
 935 // CHECK5-NEXT:    ret void
 936 //
 937 //
 938 // CHECK5-LABEL: define {{[^@]+}}@_Z10array_funcv.omp_outlined
 939 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4:[0-9]+]] {
 940 // CHECK5-NEXT:  entry:
 941 // CHECK5-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 942 // CHECK5-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 943 // CHECK5-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 944 // CHECK5-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 945 // CHECK5-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 946 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
 947 // CHECK5-NEXT:    [[TMP2:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP1]], ptr @_ZZ10array_funcvE1a, i64 8, ptr @_ZZ10array_funcvE1a.cache.)
 948 // CHECK5-NEXT:    [[TMP3:%.*]] = ptrtoint ptr [[TMP2]] to i64
 949 // CHECK5-NEXT:    [[TMP4:%.*]] = icmp ne i64 ptrtoint (ptr @_ZZ10array_funcvE1a to i64), [[TMP3]]
 950 // CHECK5-NEXT:    br i1 [[TMP4]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]]
 951 // CHECK5:       copyin.not.master:
 952 // CHECK5-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP2]], ptr align 4 @_ZZ10array_funcvE1a, i64 8, i1 false)
 953 // CHECK5-NEXT:    [[TMP5:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP1]], ptr @_ZZ10array_funcvE1s, i64 16, ptr @_ZZ10array_funcvE1s.cache.)
 954 // CHECK5-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.St], ptr [[TMP5]], i32 0, i32 0
 955 // CHECK5-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[ARRAY_BEGIN]], i64 2
 956 // CHECK5-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP6]]
 957 // CHECK5-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE1:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
 958 // CHECK5:       omp.arraycpy.body:
 959 // CHECK5-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ @_ZZ10array_funcvE1s, [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
 960 // CHECK5-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
 961 // CHECK5-NEXT:    [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(8) ptr @_ZN2StaSERKS_(ptr noundef nonnull align 4 dereferenceable(8) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(8) [[OMP_ARRAYCPY_SRCELEMENTPAST]])
 962 // CHECK5-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_ST]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
 963 // CHECK5-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_ST]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
 964 // CHECK5-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP6]]
 965 // CHECK5-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE1]], label [[OMP_ARRAYCPY_BODY]]
 966 // CHECK5:       omp.arraycpy.done1:
 967 // CHECK5-NEXT:    br label [[COPYIN_NOT_MASTER_END]]
 968 // CHECK5:       copyin.not.master.end:
 969 // CHECK5-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB2:[0-9]+]], i32 [[TMP1]])
 970 // CHECK5-NEXT:    ret void
 971 //
 972 //
 973 // CHECK5-LABEL: define {{[^@]+}}@_ZN2StaSERKS_
 974 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[TMP0:%.*]]) #[[ATTR0]] align 2 {
 975 // CHECK5-NEXT:  entry:
 976 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 977 // CHECK5-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
 978 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 979 // CHECK5-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
 980 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 981 // CHECK5-NEXT:    ret ptr [[THIS1]]
 982 //
 983 //
 984 // CHECK5-LABEL: define {{[^@]+}}@_ZN2StC2Ev
 985 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] align 2 {
 986 // CHECK5-NEXT:  entry:
 987 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 988 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 989 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 990 // CHECK5-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0
 991 // CHECK5-NEXT:    store i32 0, ptr [[A]], align 4
 992 // CHECK5-NEXT:    [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1
 993 // CHECK5-NEXT:    store i32 0, ptr [[B]], align 4
 994 // CHECK5-NEXT:    ret void
 995 //
 996 //
 997 // CHECK5-LABEL: define {{[^@]+}}@_ZN2StD2Ev
 998 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] align 2 {
 999 // CHECK5-NEXT:  entry:
1000 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1001 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1002 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1003 // CHECK5-NEXT:    ret void
1004 //
1005 //
1006 // CHECK11-LABEL: define {{[^@]+}}@main
1007 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] {
1008 // CHECK11-NEXT:  entry:
1009 // CHECK11-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
1010 // CHECK11-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4
1011 // CHECK11-NEXT:    [[REF_TMP:%.*]] = alloca [[STRUCT_S]], align 4
1012 // CHECK11-NEXT:    store i32 0, ptr [[RETVAL]], align 4
1013 // CHECK11-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])
1014 // CHECK11-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]])
1015 // CHECK11-NEXT:    [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIfEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]], ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]])
1016 // CHECK11-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR4:[0-9]+]]
1017 // CHECK11-NEXT:    [[TMP0:%.*]] = load i8, ptr @_ZGVZ4mainE5s_arr, align 1
1018 // CHECK11-NEXT:    [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0
1019 // CHECK11-NEXT:    br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF3:![0-9]+]]
1020 // CHECK11:       init.check:
1021 // CHECK11-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @_ZZ4mainE5s_arr, float noundef 1.000000e+00)
1022 // CHECK11-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S]], ptr @_ZZ4mainE5s_arr, i64 1), float noundef 2.000000e+00)
1023 // CHECK11-NEXT:    [[TMP1:%.*]] = call i32 @__cxa_thread_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR4]]
1024 // CHECK11-NEXT:    store i8 1, ptr @_ZGVZ4mainE5s_arr, align 1
1025 // CHECK11-NEXT:    br label [[INIT_END]]
1026 // CHECK11:       init.end:
1027 // CHECK11-NEXT:    [[TMP2:%.*]] = load i8, ptr @_ZGVZ4mainE3var, align 1
1028 // CHECK11-NEXT:    [[GUARD_UNINITIALIZED1:%.*]] = icmp eq i8 [[TMP2]], 0
1029 // CHECK11-NEXT:    br i1 [[GUARD_UNINITIALIZED1]], label [[INIT_CHECK2:%.*]], label [[INIT_END3:%.*]], !prof [[PROF3]]
1030 // CHECK11:       init.check2:
1031 // CHECK11-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @_ZZ4mainE3var, float noundef 3.000000e+00)
1032 // CHECK11-NEXT:    [[TMP3:%.*]] = call i32 @__cxa_thread_atexit(ptr @_ZN1SIfED1Ev, ptr @_ZZ4mainE3var, ptr @__dso_handle) #[[ATTR4]]
1033 // CHECK11-NEXT:    store i8 1, ptr @_ZGVZ4mainE3var, align 1
1034 // CHECK11-NEXT:    br label [[INIT_END3]]
1035 // CHECK11:       init.end3:
1036 // CHECK11-NEXT:    [[TMP4:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZZ4mainE5t_var)
1037 // CHECK11-NEXT:    [[TMP5:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZZ4mainE3vec)
1038 // CHECK11-NEXT:    [[TMP6:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZZ4mainE5s_arr)
1039 // CHECK11-NEXT:    [[TMP7:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZZ4mainE3var)
1040 // CHECK11-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2:[0-9]+]], i32 4, ptr @main.omp_outlined, ptr [[TMP4]], ptr [[TMP5]], ptr [[TMP6]], ptr [[TMP7]])
1041 // CHECK11-NEXT:    [[TMP8:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZZ4mainE5t_var)
1042 // CHECK11-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @main.omp_outlined.1, ptr [[TMP8]])
1043 // CHECK11-NEXT:    [[CALL4:%.*]] = call noundef i32 @_Z5tmainIiET_v()
1044 // CHECK11-NEXT:    store i32 [[CALL4]], ptr [[RETVAL]], align 4
1045 // CHECK11-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
1046 // CHECK11-NEXT:    [[TMP9:%.*]] = load i32, ptr [[RETVAL]], align 4
1047 // CHECK11-NEXT:    ret i32 [[TMP9]]
1048 //
1049 //
1050 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
1051 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
1052 // CHECK11-NEXT:  entry:
1053 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1054 // CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1055 // CHECK11-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1056 // CHECK11-NEXT:    call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
1057 // CHECK11-NEXT:    ret void
1058 //
1059 //
1060 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEaSERKS0_
1061 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 {
1062 // CHECK11-NEXT:  entry:
1063 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1064 // CHECK11-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
1065 // CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1066 // CHECK11-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
1067 // CHECK11-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1068 // CHECK11-NEXT:    ret ptr [[THIS1]]
1069 //
1070 //
1071 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
1072 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1073 // CHECK11-NEXT:  entry:
1074 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1075 // CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1076 // CHECK11-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1077 // CHECK11-NEXT:    call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
1078 // CHECK11-NEXT:    ret void
1079 //
1080 //
1081 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
1082 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1083 // CHECK11-NEXT:  entry:
1084 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1085 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
1086 // CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1087 // CHECK11-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
1088 // CHECK11-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1089 // CHECK11-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
1090 // CHECK11-NEXT:    call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
1091 // CHECK11-NEXT:    ret void
1092 //
1093 //
1094 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
1095 // CHECK11-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR3:[0-9]+]] section ".text.startup" {
1096 // CHECK11-NEXT:  entry:
1097 // CHECK11-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
1098 // CHECK11-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
1099 // CHECK11-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1100 // CHECK11:       arraydestroy.body:
1101 // CHECK11-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @_ZZ4mainE5s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1102 // CHECK11-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1103 // CHECK11-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
1104 // CHECK11-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @_ZZ4mainE5s_arr
1105 // CHECK11-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
1106 // CHECK11:       arraydestroy.done1:
1107 // CHECK11-NEXT:    ret void
1108 //
1109 //
1110 // CHECK11-LABEL: define {{[^@]+}}@main.omp_outlined
1111 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR5:[0-9]+]] {
1112 // CHECK11-NEXT:  entry:
1113 // CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1114 // CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1115 // CHECK11-NEXT:    [[T_VAR_ADDR:%.*]] = alloca ptr, align 8
1116 // CHECK11-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 8
1117 // CHECK11-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 8
1118 // CHECK11-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 8
1119 // CHECK11-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1120 // CHECK11-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1121 // CHECK11-NEXT:    store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
1122 // CHECK11-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 8
1123 // CHECK11-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8
1124 // CHECK11-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 8
1125 // CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8
1126 // CHECK11-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8
1127 // CHECK11-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8
1128 // CHECK11-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8
1129 // CHECK11-NEXT:    [[TMP4:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZZ4mainE5t_var)
1130 // CHECK11-NEXT:    [[TMP5:%.*]] = ptrtoint ptr [[TMP0]] to i64
1131 // CHECK11-NEXT:    [[TMP6:%.*]] = ptrtoint ptr [[TMP4]] to i64
1132 // CHECK11-NEXT:    [[TMP7:%.*]] = icmp ne i64 [[TMP5]], [[TMP6]]
1133 // CHECK11-NEXT:    br i1 [[TMP7]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]]
1134 // CHECK11:       copyin.not.master:
1135 // CHECK11-NEXT:    [[TMP8:%.*]] = load i32, ptr [[TMP0]], align 4
1136 // CHECK11-NEXT:    store i32 [[TMP8]], ptr [[TMP4]], align 4
1137 // CHECK11-NEXT:    [[TMP9:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZZ4mainE3vec)
1138 // CHECK11-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP9]], ptr align 4 [[TMP1]], i64 8, i1 false)
1139 // CHECK11-NEXT:    [[TMP10:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZZ4mainE5s_arr)
1140 // CHECK11-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP10]], i32 0, i32 0
1141 // CHECK11-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i64 2
1142 // CHECK11-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP11]]
1143 // CHECK11-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE1:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
1144 // CHECK11:       omp.arraycpy.body:
1145 // CHECK11-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1146 // CHECK11-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1147 // CHECK11-NEXT:    [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIfEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]])
1148 // CHECK11-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
1149 // CHECK11-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
1150 // CHECK11-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP11]]
1151 // CHECK11-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE1]], label [[OMP_ARRAYCPY_BODY]]
1152 // CHECK11:       omp.arraycpy.done1:
1153 // CHECK11-NEXT:    [[TMP12:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZZ4mainE3var)
1154 // CHECK11-NEXT:    [[CALL2:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIfEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[TMP12]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP3]])
1155 // CHECK11-NEXT:    br label [[COPYIN_NOT_MASTER_END]]
1156 // CHECK11:       copyin.not.master.end:
1157 // CHECK11-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1158 // CHECK11-NEXT:    [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4
1159 // CHECK11-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB1:[0-9]+]], i32 [[TMP14]])
1160 // CHECK11-NEXT:    [[TMP15:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZZ4mainE5t_var)
1161 // CHECK11-NEXT:    [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 4
1162 // CHECK11-NEXT:    [[TMP17:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZZ4mainE3vec)
1163 // CHECK11-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP17]], i64 0, i64 0
1164 // CHECK11-NEXT:    store i32 [[TMP16]], ptr [[ARRAYIDX]], align 4
1165 // CHECK11-NEXT:    [[TMP18:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZZ4mainE3var)
1166 // CHECK11-NEXT:    [[TMP19:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZZ4mainE5s_arr)
1167 // CHECK11-NEXT:    [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP19]], i64 0, i64 0
1168 // CHECK11-NEXT:    [[CALL4:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIfEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYIDX3]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP18]])
1169 // CHECK11-NEXT:    ret void
1170 //
1171 //
1172 // CHECK11-LABEL: define {{[^@]+}}@main.omp_outlined.1
1173 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR5]] {
1174 // CHECK11-NEXT:  entry:
1175 // CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1176 // CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1177 // CHECK11-NEXT:    [[T_VAR_ADDR:%.*]] = alloca ptr, align 8
1178 // CHECK11-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1179 // CHECK11-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1180 // CHECK11-NEXT:    store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
1181 // CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8
1182 // CHECK11-NEXT:    [[TMP1:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZZ4mainE5t_var)
1183 // CHECK11-NEXT:    [[TMP2:%.*]] = ptrtoint ptr [[TMP0]] to i64
1184 // CHECK11-NEXT:    [[TMP3:%.*]] = ptrtoint ptr [[TMP1]] to i64
1185 // CHECK11-NEXT:    [[TMP4:%.*]] = icmp ne i64 [[TMP2]], [[TMP3]]
1186 // CHECK11-NEXT:    br i1 [[TMP4]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]]
1187 // CHECK11:       copyin.not.master:
1188 // CHECK11-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 4
1189 // CHECK11-NEXT:    store i32 [[TMP5]], ptr [[TMP1]], align 4
1190 // CHECK11-NEXT:    br label [[COPYIN_NOT_MASTER_END]]
1191 // CHECK11:       copyin.not.master.end:
1192 // CHECK11-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1193 // CHECK11-NEXT:    [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
1194 // CHECK11-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB1]], i32 [[TMP7]])
1195 // CHECK11-NEXT:    [[TMP8:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZZ4mainE5t_var)
1196 // CHECK11-NEXT:    [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
1197 // CHECK11-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP9]], 1
1198 // CHECK11-NEXT:    store i32 [[INC]], ptr [[TMP8]], align 4
1199 // CHECK11-NEXT:    ret void
1200 //
1201 //
1202 // CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
1203 // CHECK11-SAME: () #[[ATTR2]] comdat {
1204 // CHECK11-NEXT:  entry:
1205 // CHECK11-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1206 // CHECK11-NEXT:    [[REF_TMP:%.*]] = alloca [[STRUCT_S_0]], align 4
1207 // CHECK11-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])
1208 // CHECK11-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]])
1209 // CHECK11-NEXT:    [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIiEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]], ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]])
1210 // CHECK11-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR4]]
1211 // CHECK11-NEXT:    [[TMP0:%.*]] = load i8, ptr @_ZGVZ5tmainIiET_vE5s_arr, align 8
1212 // CHECK11-NEXT:    [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0
1213 // CHECK11-NEXT:    br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF3]]
1214 // CHECK11:       init.check:
1215 // CHECK11-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) @_ZZ5tmainIiET_vE5s_arr, i32 noundef 1)
1216 // CHECK11-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S_0]], ptr @_ZZ5tmainIiET_vE5s_arr, i64 1), i32 noundef 2)
1217 // CHECK11-NEXT:    [[TMP1:%.*]] = call i32 @__cxa_thread_atexit(ptr @__cxx_global_array_dtor.2, ptr null, ptr @__dso_handle) #[[ATTR4]]
1218 // CHECK11-NEXT:    store i8 1, ptr @_ZGVZ5tmainIiET_vE5s_arr, align 8
1219 // CHECK11-NEXT:    br label [[INIT_END]]
1220 // CHECK11:       init.end:
1221 // CHECK11-NEXT:    [[TMP2:%.*]] = load i8, ptr @_ZGVZ5tmainIiET_vE3var, align 8
1222 // CHECK11-NEXT:    [[GUARD_UNINITIALIZED1:%.*]] = icmp eq i8 [[TMP2]], 0
1223 // CHECK11-NEXT:    br i1 [[GUARD_UNINITIALIZED1]], label [[INIT_CHECK2:%.*]], label [[INIT_END3:%.*]], !prof [[PROF3]]
1224 // CHECK11:       init.check2:
1225 // CHECK11-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) @_ZZ5tmainIiET_vE3var, i32 noundef 3)
1226 // CHECK11-NEXT:    [[TMP3:%.*]] = call i32 @__cxa_thread_atexit(ptr @_ZN1SIiED1Ev, ptr @_ZZ5tmainIiET_vE3var, ptr @__dso_handle) #[[ATTR4]]
1227 // CHECK11-NEXT:    store i8 1, ptr @_ZGVZ5tmainIiET_vE3var, align 8
1228 // CHECK11-NEXT:    br label [[INIT_END3]]
1229 // CHECK11:       init.end3:
1230 // CHECK11-NEXT:    [[TMP4:%.*]] = call align 128 ptr @llvm.threadlocal.address.p0(ptr align 128 @_ZZ5tmainIiET_vE5t_var)
1231 // CHECK11-NEXT:    [[TMP5:%.*]] = call align 128 ptr @llvm.threadlocal.address.p0(ptr align 128 @_ZZ5tmainIiET_vE3vec)
1232 // CHECK11-NEXT:    [[TMP6:%.*]] = call align 128 ptr @llvm.threadlocal.address.p0(ptr align 128 @_ZZ5tmainIiET_vE5s_arr)
1233 // CHECK11-NEXT:    [[TMP7:%.*]] = call align 128 ptr @llvm.threadlocal.address.p0(ptr align 128 @_ZZ5tmainIiET_vE3var)
1234 // CHECK11-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @_Z5tmainIiET_v.omp_outlined, ptr [[TMP4]], ptr [[TMP5]], ptr [[TMP6]], ptr [[TMP7]])
1235 // CHECK11-NEXT:    [[TMP8:%.*]] = call align 128 ptr @llvm.threadlocal.address.p0(ptr align 128 @_ZZ5tmainIiET_vE5t_var)
1236 // CHECK11-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @_Z5tmainIiET_v.omp_outlined.3, ptr [[TMP8]])
1237 // CHECK11-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
1238 // CHECK11-NEXT:    ret i32 0
1239 //
1240 //
1241 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
1242 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1243 // CHECK11-NEXT:  entry:
1244 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1245 // CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1246 // CHECK11-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1247 // CHECK11-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
1248 // CHECK11-NEXT:    [[TMP0:%.*]] = call align 128 ptr @llvm.threadlocal.address.p0(ptr align 128 @g)
1249 // CHECK11-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr [[TMP0]], align 128
1250 // CHECK11-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
1251 // CHECK11-NEXT:    store float [[CONV]], ptr [[F]], align 4
1252 // CHECK11-NEXT:    ret void
1253 //
1254 //
1255 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
1256 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1257 // CHECK11-NEXT:  entry:
1258 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1259 // CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1260 // CHECK11-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1261 // CHECK11-NEXT:    ret void
1262 //
1263 //
1264 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
1265 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1266 // CHECK11-NEXT:  entry:
1267 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1268 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
1269 // CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1270 // CHECK11-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
1271 // CHECK11-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1272 // CHECK11-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
1273 // CHECK11-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
1274 // CHECK11-NEXT:    [[TMP1:%.*]] = call align 128 ptr @llvm.threadlocal.address.p0(ptr align 128 @g)
1275 // CHECK11-NEXT:    [[TMP2:%.*]] = load volatile i32, ptr [[TMP1]], align 128
1276 // CHECK11-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP2]] to float
1277 // CHECK11-NEXT:    [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
1278 // CHECK11-NEXT:    store float [[ADD]], ptr [[F]], align 4
1279 // CHECK11-NEXT:    ret void
1280 //
1281 //
1282 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
1283 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1284 // CHECK11-NEXT:  entry:
1285 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1286 // CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1287 // CHECK11-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1288 // CHECK11-NEXT:    call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
1289 // CHECK11-NEXT:    ret void
1290 //
1291 //
1292 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEaSERKS0_
1293 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR2]] comdat align 2 {
1294 // CHECK11-NEXT:  entry:
1295 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1296 // CHECK11-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
1297 // CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1298 // CHECK11-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
1299 // CHECK11-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1300 // CHECK11-NEXT:    ret ptr [[THIS1]]
1301 //
1302 //
1303 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
1304 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1305 // CHECK11-NEXT:  entry:
1306 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1307 // CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1308 // CHECK11-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1309 // CHECK11-NEXT:    call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
1310 // CHECK11-NEXT:    ret void
1311 //
1312 //
1313 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
1314 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1315 // CHECK11-NEXT:  entry:
1316 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1317 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
1318 // CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1319 // CHECK11-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
1320 // CHECK11-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1321 // CHECK11-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
1322 // CHECK11-NEXT:    call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])
1323 // CHECK11-NEXT:    ret void
1324 //
1325 //
1326 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_array_dtor.2
1327 // CHECK11-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR3]] section ".text.startup" {
1328 // CHECK11-NEXT:  entry:
1329 // CHECK11-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
1330 // CHECK11-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
1331 // CHECK11-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1332 // CHECK11:       arraydestroy.body:
1333 // CHECK11-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S_0:%.*]], ptr @_ZZ5tmainIiET_vE5s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1334 // CHECK11-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1335 // CHECK11-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
1336 // CHECK11-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @_ZZ5tmainIiET_vE5s_arr
1337 // CHECK11-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
1338 // CHECK11:       arraydestroy.done1:
1339 // CHECK11-NEXT:    ret void
1340 //
1341 //
1342 // CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiET_v.omp_outlined
1343 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR5]] {
1344 // CHECK11-NEXT:  entry:
1345 // CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1346 // CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1347 // CHECK11-NEXT:    [[T_VAR_ADDR:%.*]] = alloca ptr, align 8
1348 // CHECK11-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 8
1349 // CHECK11-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 8
1350 // CHECK11-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 8
1351 // CHECK11-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1352 // CHECK11-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1353 // CHECK11-NEXT:    store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
1354 // CHECK11-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 8
1355 // CHECK11-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8
1356 // CHECK11-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 8
1357 // CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8
1358 // CHECK11-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8
1359 // CHECK11-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8
1360 // CHECK11-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8
1361 // CHECK11-NEXT:    [[TMP4:%.*]] = call align 128 ptr @llvm.threadlocal.address.p0(ptr align 128 @_ZZ5tmainIiET_vE5t_var)
1362 // CHECK11-NEXT:    [[TMP5:%.*]] = ptrtoint ptr [[TMP0]] to i64
1363 // CHECK11-NEXT:    [[TMP6:%.*]] = ptrtoint ptr [[TMP4]] to i64
1364 // CHECK11-NEXT:    [[TMP7:%.*]] = icmp ne i64 [[TMP5]], [[TMP6]]
1365 // CHECK11-NEXT:    br i1 [[TMP7]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]]
1366 // CHECK11:       copyin.not.master:
1367 // CHECK11-NEXT:    [[TMP8:%.*]] = load i32, ptr [[TMP0]], align 128
1368 // CHECK11-NEXT:    store i32 [[TMP8]], ptr [[TMP4]], align 128
1369 // CHECK11-NEXT:    [[TMP9:%.*]] = call align 128 ptr @llvm.threadlocal.address.p0(ptr align 128 @_ZZ5tmainIiET_vE3vec)
1370 // CHECK11-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 128 [[TMP9]], ptr align 128 [[TMP1]], i64 8, i1 false)
1371 // CHECK11-NEXT:    [[TMP10:%.*]] = call align 128 ptr @llvm.threadlocal.address.p0(ptr align 128 @_ZZ5tmainIiET_vE5s_arr)
1372 // CHECK11-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP10]], i32 0, i32 0
1373 // CHECK11-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[ARRAY_BEGIN]], i64 2
1374 // CHECK11-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP11]]
1375 // CHECK11-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE1:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
1376 // CHECK11:       omp.arraycpy.body:
1377 // CHECK11-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1378 // CHECK11-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1379 // CHECK11-NEXT:    [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIiEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]])
1380 // CHECK11-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
1381 // CHECK11-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
1382 // CHECK11-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP11]]
1383 // CHECK11-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE1]], label [[OMP_ARRAYCPY_BODY]]
1384 // CHECK11:       omp.arraycpy.done1:
1385 // CHECK11-NEXT:    [[TMP12:%.*]] = call align 128 ptr @llvm.threadlocal.address.p0(ptr align 128 @_ZZ5tmainIiET_vE3var)
1386 // CHECK11-NEXT:    [[CALL2:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIiEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[TMP12]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP3]])
1387 // CHECK11-NEXT:    br label [[COPYIN_NOT_MASTER_END]]
1388 // CHECK11:       copyin.not.master.end:
1389 // CHECK11-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1390 // CHECK11-NEXT:    [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4
1391 // CHECK11-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB1]], i32 [[TMP14]])
1392 // CHECK11-NEXT:    [[TMP15:%.*]] = call align 128 ptr @llvm.threadlocal.address.p0(ptr align 128 @_ZZ5tmainIiET_vE5t_var)
1393 // CHECK11-NEXT:    [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 128
1394 // CHECK11-NEXT:    [[TMP17:%.*]] = call align 128 ptr @llvm.threadlocal.address.p0(ptr align 128 @_ZZ5tmainIiET_vE3vec)
1395 // CHECK11-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP17]], i64 0, i64 0
1396 // CHECK11-NEXT:    store i32 [[TMP16]], ptr [[ARRAYIDX]], align 128
1397 // CHECK11-NEXT:    [[TMP18:%.*]] = call align 128 ptr @llvm.threadlocal.address.p0(ptr align 128 @_ZZ5tmainIiET_vE3var)
1398 // CHECK11-NEXT:    [[TMP19:%.*]] = call align 128 ptr @llvm.threadlocal.address.p0(ptr align 128 @_ZZ5tmainIiET_vE5s_arr)
1399 // CHECK11-NEXT:    [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP19]], i64 0, i64 0
1400 // CHECK11-NEXT:    [[CALL4:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIiEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYIDX3]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP18]])
1401 // CHECK11-NEXT:    ret void
1402 //
1403 //
1404 // CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiET_v.omp_outlined.3
1405 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR5]] {
1406 // CHECK11-NEXT:  entry:
1407 // CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1408 // CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1409 // CHECK11-NEXT:    [[T_VAR_ADDR:%.*]] = alloca ptr, align 8
1410 // CHECK11-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1411 // CHECK11-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1412 // CHECK11-NEXT:    store ptr [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
1413 // CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[T_VAR_ADDR]], align 8
1414 // CHECK11-NEXT:    [[TMP1:%.*]] = call align 128 ptr @llvm.threadlocal.address.p0(ptr align 128 @_ZZ5tmainIiET_vE5t_var)
1415 // CHECK11-NEXT:    [[TMP2:%.*]] = ptrtoint ptr [[TMP0]] to i64
1416 // CHECK11-NEXT:    [[TMP3:%.*]] = ptrtoint ptr [[TMP1]] to i64
1417 // CHECK11-NEXT:    [[TMP4:%.*]] = icmp ne i64 [[TMP2]], [[TMP3]]
1418 // CHECK11-NEXT:    br i1 [[TMP4]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]]
1419 // CHECK11:       copyin.not.master:
1420 // CHECK11-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 128
1421 // CHECK11-NEXT:    store i32 [[TMP5]], ptr [[TMP1]], align 128
1422 // CHECK11-NEXT:    br label [[COPYIN_NOT_MASTER_END]]
1423 // CHECK11:       copyin.not.master.end:
1424 // CHECK11-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1425 // CHECK11-NEXT:    [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
1426 // CHECK11-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB1]], i32 [[TMP7]])
1427 // CHECK11-NEXT:    ret void
1428 //
1429 //
1430 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
1431 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1432 // CHECK11-NEXT:  entry:
1433 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1434 // CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1435 // CHECK11-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1436 // CHECK11-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
1437 // CHECK11-NEXT:    [[TMP0:%.*]] = call align 128 ptr @llvm.threadlocal.address.p0(ptr align 128 @g)
1438 // CHECK11-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr [[TMP0]], align 128
1439 // CHECK11-NEXT:    store i32 [[TMP1]], ptr [[F]], align 4
1440 // CHECK11-NEXT:    ret void
1441 //
1442 //
1443 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
1444 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1445 // CHECK11-NEXT:  entry:
1446 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1447 // CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1448 // CHECK11-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1449 // CHECK11-NEXT:    ret void
1450 //
1451 //
1452 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
1453 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1454 // CHECK11-NEXT:  entry:
1455 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1456 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
1457 // CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1458 // CHECK11-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
1459 // CHECK11-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1460 // CHECK11-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
1461 // CHECK11-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
1462 // CHECK11-NEXT:    [[TMP1:%.*]] = call align 128 ptr @llvm.threadlocal.address.p0(ptr align 128 @g)
1463 // CHECK11-NEXT:    [[TMP2:%.*]] = load volatile i32, ptr [[TMP1]], align 128
1464 // CHECK11-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP2]]
1465 // CHECK11-NEXT:    store i32 [[ADD]], ptr [[F]], align 4
1466 // CHECK11-NEXT:    ret void
1467 //
1468 //
1469 // CHECK11-LABEL: define {{[^@]+}}@_ZTW1g
1470 // CHECK11-SAME: () #[[ATTR9:[0-9]+]] comdat {
1471 // CHECK11-NEXT:    [[TMP1:%.*]] = call align 128 ptr @llvm.threadlocal.address.p0(ptr align 128 @g)
1472 // CHECK11-NEXT:    ret ptr [[TMP1]]
1473 //
1474 //
1475 // CHECK13-LABEL: define {{[^@]+}}@main
1476 // CHECK13-SAME: () #[[ATTR0:[0-9]+]] {
1477 // CHECK13-NEXT:  entry:
1478 // CHECK13-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
1479 // CHECK13-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
1480 // CHECK13-NEXT:    store i32 0, ptr [[RETVAL]], align 4
1481 // CHECK13-NEXT:    call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])
1482 // CHECK13-NEXT:    ret i32 0
1483 //
1484 //
1485 // CHECK13-LABEL: define {{[^@]+}}@_ZTW1g
1486 // CHECK13-SAME: () #[[ATTR6:[0-9]+]] comdat {
1487 // CHECK13-NEXT:    [[TMP1:%.*]] = call align 128 ptr @llvm.threadlocal.address.p0(ptr align 128 @g)
1488 // CHECK13-NEXT:    ret ptr [[TMP1]]
1489 //
1490 //
1491 // CHECK14-LABEL: define {{[^@]+}}@main
1492 // CHECK14-SAME: () #[[ATTR1:[0-9]+]] {
1493 // CHECK14-NEXT:  entry:
1494 // CHECK14-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
1495 // CHECK14-NEXT:    store i32 0, ptr [[RETVAL]], align 4
1496 // CHECK14-NEXT:    [[TMP0:%.*]] = load ptr, ptr getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr @__block_literal_global, i32 0, i32 3), align 8
1497 // CHECK14-NEXT:    call void [[TMP0]](ptr noundef @__block_literal_global)
1498 // CHECK14-NEXT:    ret i32 0
1499 //
1500 //
1501 // CHECK14-LABEL: define {{[^@]+}}@__main_block_invoke
1502 // CHECK14-SAME: (ptr noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] {
1503 // CHECK14-NEXT:  entry:
1504 // CHECK14-NEXT:    [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 8
1505 // CHECK14-NEXT:    [[BLOCK_ADDR:%.*]] = alloca ptr, align 8
1506 // CHECK14-NEXT:    store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8
1507 // CHECK14-NEXT:    store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 8
1508 // CHECK14-NEXT:    [[TMP0:%.*]] = call align 128 ptr @llvm.threadlocal.address.p0(ptr align 128 @g)
1509 // CHECK14-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2:[0-9]+]], i32 1, ptr @__main_block_invoke.omp_outlined, ptr [[TMP0]])
1510 // CHECK14-NEXT:    ret void
1511 //
1512 //
1513 // CHECK14-LABEL: define {{[^@]+}}@__main_block_invoke.omp_outlined
1514 // CHECK14-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[G:%.*]]) #[[ATTR3:[0-9]+]] {
1515 // CHECK14-NEXT:  entry:
1516 // CHECK14-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1517 // CHECK14-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1518 // CHECK14-NEXT:    [[G_ADDR:%.*]] = alloca ptr, align 8
1519 // CHECK14-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1520 // CHECK14-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1521 // CHECK14-NEXT:    store ptr [[G]], ptr [[G_ADDR]], align 8
1522 // CHECK14-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[G_ADDR]], align 8
1523 // CHECK14-NEXT:    [[TMP1:%.*]] = call align 128 ptr @llvm.threadlocal.address.p0(ptr align 128 @g)
1524 // CHECK14-NEXT:    [[TMP2:%.*]] = ptrtoint ptr [[TMP0]] to i64
1525 // CHECK14-NEXT:    [[TMP3:%.*]] = ptrtoint ptr [[TMP1]] to i64
1526 // CHECK14-NEXT:    [[TMP4:%.*]] = icmp ne i64 [[TMP2]], [[TMP3]]
1527 // CHECK14-NEXT:    br i1 [[TMP4]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]]
1528 // CHECK14:       copyin.not.master:
1529 // CHECK14-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 128
1530 // CHECK14-NEXT:    store volatile i32 [[TMP5]], ptr [[TMP1]], align 128
1531 // CHECK14-NEXT:    br label [[COPYIN_NOT_MASTER_END]]
1532 // CHECK14:       copyin.not.master.end:
1533 // CHECK14-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1534 // CHECK14-NEXT:    [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
1535 // CHECK14-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB1:[0-9]+]], i32 [[TMP7]])
1536 // CHECK14-NEXT:    [[TMP8:%.*]] = call align 128 ptr @llvm.threadlocal.address.p0(ptr align 128 @g)
1537 // CHECK14-NEXT:    store volatile i32 1, ptr [[TMP8]], align 128
1538 // CHECK14-NEXT:    [[TMP9:%.*]] = load ptr, ptr getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], ptr @__block_literal_global.2, i32 0, i32 3), align 8
1539 // CHECK14-NEXT:    call void [[TMP9]](ptr noundef @__block_literal_global.2)
1540 // CHECK14-NEXT:    ret void
1541 //
1542 //
1543 // CHECK14-LABEL: define {{[^@]+}}@g_block_invoke
1544 // CHECK14-SAME: (ptr noundef [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] {
1545 // CHECK14-NEXT:  entry:
1546 // CHECK14-NEXT:    [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca ptr, align 8
1547 // CHECK14-NEXT:    [[BLOCK_ADDR:%.*]] = alloca ptr, align 8
1548 // CHECK14-NEXT:    store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8
1549 // CHECK14-NEXT:    store ptr [[DOTBLOCK_DESCRIPTOR]], ptr [[BLOCK_ADDR]], align 8
1550 // CHECK14-NEXT:    [[TMP0:%.*]] = call align 128 ptr @llvm.threadlocal.address.p0(ptr align 128 @g)
1551 // CHECK14-NEXT:    store volatile i32 2, ptr [[TMP0]], align 128
1552 // CHECK14-NEXT:    ret void
1553 //
1554 //
1555 // CHECK14-LABEL: define {{[^@]+}}@_ZTW1g
1556 // CHECK14-SAME: () #[[ATTR7:[0-9]+]] comdat {
1557 // CHECK14-NEXT:    [[TMP1:%.*]] = call align 128 ptr @llvm.threadlocal.address.p0(ptr align 128 @g)
1558 // CHECK14-NEXT:    ret ptr [[TMP1]]
1559 //
1560 //
1561 // CHECK15-LABEL: define {{[^@]+}}@_Z10array_funcv
1562 // CHECK15-SAME: () #[[ATTR0:[0-9]+]] {
1563 // CHECK15-NEXT:  entry:
1564 // CHECK15-NEXT:    [[TMP0:%.*]] = load i8, ptr @_ZGVZ10array_funcvE1s, align 1
1565 // CHECK15-NEXT:    [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0
1566 // CHECK15-NEXT:    br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF3:![0-9]+]]
1567 // CHECK15:       init.check:
1568 // CHECK15-NEXT:    br label [[ARRAYCTOR_LOOP:%.*]]
1569 // CHECK15:       arrayctor.loop:
1570 // CHECK15-NEXT:    [[ARRAYCTOR_CUR:%.*]] = phi ptr [ @_ZZ10array_funcvE1s, [[INIT_CHECK]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1571 // CHECK15-NEXT:    call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[ARRAYCTOR_CUR]])
1572 // CHECK15-NEXT:    [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[ARRAYCTOR_CUR]], i64 1
1573 // CHECK15-NEXT:    [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], getelementptr inbounds ([[STRUCT_ST]], ptr @_ZZ10array_funcvE1s, i64 2)
1574 // CHECK15-NEXT:    br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1575 // CHECK15:       arrayctor.cont:
1576 // CHECK15-NEXT:    [[TMP1:%.*]] = call i32 @__cxa_thread_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR3:[0-9]+]]
1577 // CHECK15-NEXT:    store i8 1, ptr @_ZGVZ10array_funcvE1s, align 1
1578 // CHECK15-NEXT:    br label [[INIT_END]]
1579 // CHECK15:       init.end:
1580 // CHECK15-NEXT:    [[TMP2:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZZ10array_funcvE1a)
1581 // CHECK15-NEXT:    [[TMP3:%.*]] = call align 16 ptr @llvm.threadlocal.address.p0(ptr align 16 @_ZZ10array_funcvE1s)
1582 // CHECK15-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2:[0-9]+]], i32 2, ptr @_Z10array_funcv.omp_outlined, ptr [[TMP2]], ptr [[TMP3]])
1583 // CHECK15-NEXT:    ret void
1584 //
1585 //
1586 // CHECK15-LABEL: define {{[^@]+}}@_ZN2StC1Ev
1587 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
1588 // CHECK15-NEXT:  entry:
1589 // CHECK15-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1590 // CHECK15-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1591 // CHECK15-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1592 // CHECK15-NEXT:    call void @_ZN2StC2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]])
1593 // CHECK15-NEXT:    ret void
1594 //
1595 //
1596 // CHECK15-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
1597 // CHECK15-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR2:[0-9]+]] section ".text.startup" {
1598 // CHECK15-NEXT:  entry:
1599 // CHECK15-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
1600 // CHECK15-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
1601 // CHECK15-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1602 // CHECK15:       arraydestroy.body:
1603 // CHECK15-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_ST:%.*]], ptr @_ZZ10array_funcvE1s, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1604 // CHECK15-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_ST]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1605 // CHECK15-NEXT:    call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]]
1606 // CHECK15-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @_ZZ10array_funcvE1s
1607 // CHECK15-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
1608 // CHECK15:       arraydestroy.done1:
1609 // CHECK15-NEXT:    ret void
1610 //
1611 //
1612 // CHECK15-LABEL: define {{[^@]+}}@_ZN2StD1Ev
1613 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1614 // CHECK15-NEXT:  entry:
1615 // CHECK15-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1616 // CHECK15-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1617 // CHECK15-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1618 // CHECK15-NEXT:    call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR3]]
1619 // CHECK15-NEXT:    ret void
1620 //
1621 //
1622 // CHECK15-LABEL: define {{[^@]+}}@_Z10array_funcv.omp_outlined
1623 // CHECK15-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(16) [[S:%.*]]) #[[ATTR4:[0-9]+]] {
1624 // CHECK15-NEXT:  entry:
1625 // CHECK15-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1626 // CHECK15-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1627 // CHECK15-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
1628 // CHECK15-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8
1629 // CHECK15-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1630 // CHECK15-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1631 // CHECK15-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
1632 // CHECK15-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8
1633 // CHECK15-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
1634 // CHECK15-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ADDR]], align 8
1635 // CHECK15-NEXT:    [[TMP2:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZZ10array_funcvE1a)
1636 // CHECK15-NEXT:    [[TMP3:%.*]] = ptrtoint ptr [[TMP0]] to i64
1637 // CHECK15-NEXT:    [[TMP4:%.*]] = ptrtoint ptr [[TMP2]] to i64
1638 // CHECK15-NEXT:    [[TMP5:%.*]] = icmp ne i64 [[TMP3]], [[TMP4]]
1639 // CHECK15-NEXT:    br i1 [[TMP5]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]]
1640 // CHECK15:       copyin.not.master:
1641 // CHECK15-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP2]], ptr align 4 [[TMP0]], i64 8, i1 false)
1642 // CHECK15-NEXT:    [[TMP6:%.*]] = call align 16 ptr @llvm.threadlocal.address.p0(ptr align 16 @_ZZ10array_funcvE1s)
1643 // CHECK15-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.St], ptr [[TMP6]], i32 0, i32 0
1644 // CHECK15-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[ARRAY_BEGIN]], i64 2
1645 // CHECK15-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP7]]
1646 // CHECK15-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE1:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
1647 // CHECK15:       omp.arraycpy.body:
1648 // CHECK15-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1649 // CHECK15-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1650 // CHECK15-NEXT:    [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(8) ptr @_ZN2StaSERKS_(ptr noundef nonnull align 4 dereferenceable(8) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(8) [[OMP_ARRAYCPY_SRCELEMENTPAST]])
1651 // CHECK15-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_ST]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
1652 // CHECK15-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_ST]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
1653 // CHECK15-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP7]]
1654 // CHECK15-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE1]], label [[OMP_ARRAYCPY_BODY]]
1655 // CHECK15:       omp.arraycpy.done1:
1656 // CHECK15-NEXT:    br label [[COPYIN_NOT_MASTER_END]]
1657 // CHECK15:       copyin.not.master.end:
1658 // CHECK15-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1659 // CHECK15-NEXT:    [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
1660 // CHECK15-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB1:[0-9]+]], i32 [[TMP9]])
1661 // CHECK15-NEXT:    ret void
1662 //
1663 //
1664 // CHECK15-LABEL: define {{[^@]+}}@_ZN2StaSERKS_
1665 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[TMP0:%.*]]) #[[ATTR0]] comdat align 2 {
1666 // CHECK15-NEXT:  entry:
1667 // CHECK15-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1668 // CHECK15-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
1669 // CHECK15-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1670 // CHECK15-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
1671 // CHECK15-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1672 // CHECK15-NEXT:    ret ptr [[THIS1]]
1673 //
1674 //
1675 // CHECK15-LABEL: define {{[^@]+}}@_ZN2StC2Ev
1676 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1677 // CHECK15-NEXT:  entry:
1678 // CHECK15-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1679 // CHECK15-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1680 // CHECK15-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1681 // CHECK15-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0
1682 // CHECK15-NEXT:    store i32 0, ptr [[A]], align 4
1683 // CHECK15-NEXT:    [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1
1684 // CHECK15-NEXT:    store i32 0, ptr [[B]], align 4
1685 // CHECK15-NEXT:    ret void
1686 //
1687 //
1688 // CHECK15-LABEL: define {{[^@]+}}@_ZN2StD2Ev
1689 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1690 // CHECK15-NEXT:  entry:
1691 // CHECK15-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1692 // CHECK15-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1693 // CHECK15-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1694 // CHECK15-NEXT:    ret void
1695 //
1696 //
1697 // CHECK16-LABEL: define {{[^@]+}}@__cxx_global_var_init
1698 // CHECK16-SAME: () #[[ATTR0:[0-9]+]] section ".text.startup" {
1699 // CHECK16-NEXT:  entry:
1700 // CHECK16-NEXT:    [[CALL:%.*]] = call noundef i32 @_Z6t_initv()
1701 // CHECK16-NEXT:    [[TMP0:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @t)
1702 // CHECK16-NEXT:    store i32 [[CALL]], ptr [[TMP0]], align 4
1703 // CHECK16-NEXT:    ret void
1704 //
1705 //
1706 // CHECK16-LABEL: define {{[^@]+}}@_Z3foov
1707 // CHECK16-SAME: () #[[ATTR3:[0-9]+]] {
1708 // CHECK16-NEXT:  entry:
1709 // CHECK16-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @_Z3foov.omp_outlined)
1710 // CHECK16-NEXT:    ret void
1711 //
1712 //
1713 // CHECK16-LABEL: define {{[^@]+}}@_Z3foov.omp_outlined
1714 // CHECK16-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4:[0-9]+]] {
1715 // CHECK16-NEXT:  entry:
1716 // CHECK16-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1717 // CHECK16-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1718 // CHECK16-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1719 // CHECK16-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1720 // CHECK16-NEXT:    [[TMP0:%.*]] = call ptr @_ZTW1t()
1721 // CHECK16-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @_Z3foov.omp_outlined.omp_outlined, ptr [[TMP0]])
1722 // CHECK16-NEXT:    ret void
1723 //
1724 //
1725 // CHECK16-LABEL: define {{[^@]+}}@_Z3foov.omp_outlined.omp_outlined
1726 // CHECK16-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[T:%.*]]) #[[ATTR4]] {
1727 // CHECK16-NEXT:  entry:
1728 // CHECK16-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1729 // CHECK16-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1730 // CHECK16-NEXT:    [[T_ADDR:%.*]] = alloca ptr, align 8
1731 // CHECK16-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1732 // CHECK16-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1733 // CHECK16-NEXT:    store ptr [[T]], ptr [[T_ADDR]], align 8
1734 // CHECK16-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[T_ADDR]], align 8
1735 // CHECK16-NEXT:    [[TMP1:%.*]] = call ptr @_ZTW1t()
1736 // CHECK16-NEXT:    [[TMP2:%.*]] = ptrtoint ptr [[TMP0]] to i64
1737 // CHECK16-NEXT:    [[TMP3:%.*]] = ptrtoint ptr [[TMP1]] to i64
1738 // CHECK16-NEXT:    [[TMP4:%.*]] = icmp ne i64 [[TMP2]], [[TMP3]]
1739 // CHECK16-NEXT:    br i1 [[TMP4]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]]
1740 // CHECK16:       copyin.not.master:
1741 // CHECK16-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 4
1742 // CHECK16-NEXT:    store i32 [[TMP5]], ptr [[TMP1]], align 4
1743 // CHECK16-NEXT:    br label [[COPYIN_NOT_MASTER_END]]
1744 // CHECK16:       copyin.not.master.end:
1745 // CHECK16-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1746 // CHECK16-NEXT:    [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
1747 // CHECK16-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB1:[0-9]+]], i32 [[TMP7]])
1748 // CHECK16-NEXT:    [[TMP8:%.*]] = call ptr @_ZTW1t()
1749 // CHECK16-NEXT:    [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
1750 // CHECK16-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP9]], 1
1751 // CHECK16-NEXT:    store i32 [[INC]], ptr [[TMP8]], align 4
1752 // CHECK16-NEXT:    ret void
1753 //
1754 //
1755 // CHECK16-LABEL: define {{[^@]+}}@_ZTW1t
1756 // CHECK16-SAME: () #[[ATTR5:[0-9]+]] comdat {
1757 // CHECK16-NEXT:    call void @_ZTH1t()
1758 // CHECK16-NEXT:    [[TMP1:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @t)
1759 // CHECK16-NEXT:    ret ptr [[TMP1]]
1760 //
1761 //
1762 // CHECK16-LABEL: define {{[^@]+}}@__tls_init
1763 // CHECK16-SAME: () #[[ATTR0]] {
1764 // CHECK16-NEXT:  entry:
1765 // CHECK16-NEXT:    [[TMP0:%.*]] = load i8, ptr @__tls_guard, align 1
1766 // CHECK16-NEXT:    [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0
1767 // CHECK16-NEXT:    br i1 [[GUARD_UNINITIALIZED]], label [[INIT:%.*]], label [[EXIT:%.*]], !prof [[PROF5:![0-9]+]]
1768 // CHECK16:       init:
1769 // CHECK16-NEXT:    store i8 1, ptr @__tls_guard, align 1
1770 // CHECK16-NEXT:    call void @__cxx_global_var_init()
1771 // CHECK16-NEXT:    br label [[EXIT]]
1772 // CHECK16:       exit:
1773 // CHECK16-NEXT:    ret void
1774 //