clang/test/OpenMP/parallel_for_codegen.cpp

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
   2 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK1
   3 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK2
   4
   5 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s
   6 // RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1
   7
   8 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s
   9 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2
  10
  11 // RUN: %clang_cc1 -verify -Wno-vla -triple x86_64-apple-darwin10 -fopenmp -fexceptions -fcxx-exceptions -debug-info-kind=line-tables-only -gno-column-info -x c++ -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5
  12 // RUN: %clang_cc1 -verify -Wno-vla -triple x86_64-apple-darwin10 -fopenmp -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK6
  13
  14 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  15 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s
  16 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  17 // RUN: %clang_cc1 -verify -Wno-vla -triple x86_64-apple-darwin10 -fopenmp-simd -fexceptions -fcxx-exceptions -debug-info-kind=line-tables-only -x c++ -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  18 // RUN: %clang_cc1 -verify -Wno-vla -triple x86_64-apple-darwin10 -fopenmp-simd -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  19 // expected-no-diagnostics
  20
  21 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -DOMP5 -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK11
  22 // RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s
  23 // RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11
  24 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -DOMP5 -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  25 // RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s
  26 // RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  27 #ifndef HEADER
  28 #define HEADER
  29
  30 #ifndef OMP5
  31
  32 void with_var_schedule() {
  33   double a = 5;
  34
  35 #pragma omp parallel for schedule(static, char(a)) private(a)
  36   for (unsigned long long i = 1; i < 2 + a; ++i) {
  37   }
  38 }
  39
  40 void without_schedule_clause(float *a, float *b, float *c, float *d) {
  41   #pragma omp parallel for
  42 // UB = min(UB, GlobalUB)
  43 // Loop header
  44   for (int i = 33; i < 32000000; i += 7) {
  45 // Start of body: calculate i from IV:
  46 // ... loop body ...
  47 // End of body: store into a[i]:
  48     a[i] = b[i] * c[i] * d[i];
  49   }
  50 }
  51
  52 void static_not_chunked(float *a, float *b, float *c, float *d) {
  53   #pragma omp parallel for schedule(static)
  54 // UB = min(UB, GlobalUB)
  55 // Loop header
  56   for (int i = 32000000; i > 33; i += -7) {
  57 // Start of body: calculate i from IV:
  58 // ... loop body ...
  59 // End of body: store into a[i]:
  60     a[i] = b[i] * c[i] * d[i];
  61   }
  62 }
  63
  64 void static_chunked(float *a, float *b, float *c, float *d) {
  65   #pragma omp parallel for schedule(static, 5)
  66 // UB = min(UB, GlobalUB)
  67
  68 // Outer loop header
  69
  70 // Loop header
  71   for (unsigned i = 131071; i <= 2147483647; i += 127) {
  72 // Start of body: calculate i from IV:
  73 // ... loop body ...
  74 // End of body: store into a[i]:
  75     a[i] = b[i] * c[i] * d[i];
  76   }
  77 // Update the counters, adding stride
  78
  79 }
  80
  81 void dynamic1(float *a, float *b, float *c, float *d) {
  82   #pragma omp parallel for schedule(dynamic)
  83
  84 // Loop header
  85
  86   for (unsigned long long i = 131071; i < 2147483647; i += 127) {
  87 // Start of body: calculate i from IV:
  88 // ... loop body ...
  89 // End of body: store into a[i]:
  90     a[i] = b[i] * c[i] * d[i];
  91   }
  92 }
  93
  94 void guided7(float *a, float *b, float *c, float *d) {
  95   #pragma omp parallel for schedule(guided, 7)
  96
  97 // Loop header
  98
  99   for (unsigned long long i = 131071; i < 2147483647; i += 127) {
 100 // Start of body: calculate i from IV:
 101 // ... loop body ...
 102 // End of body: store into a[i]:
 103     a[i] = b[i] * c[i] * d[i];
 104   }
 105 }
 106
 107 void test_auto(float *a, float *b, float *c, float *d) {
 108   unsigned int x = 0;
 109   unsigned int y = 0;
 110   #pragma omp parallel for schedule(auto) collapse(2)
 111
 112 // Loop header
 113
 114 // FIXME: When the iteration count of some nested loop is not a known constant,
 115 // we should pre-calculate it, like we do for the total number of iterations!
 116   for (char i = static_cast<char>(y); i <= '9'; ++i)
 117     for (x = 11; x > 0; --x) {
 118 // Start of body: indices are calculated from IV:
 119 // ... loop body ...
 120 // End of body: store into a[i]:
 121     a[i] = b[i] * c[i] * d[i];
 122   }
 123 }
 124
 125 void runtime(float *a, float *b, float *c, float *d) {
 126   int x = 0;
 127   #pragma omp parallel for collapse(2) schedule(runtime)
 128
 129 // Loop header
 130
 131   for (unsigned char i = '0' ; i <= '9'; ++i)
 132     for (x = -10; x < 10; ++x) {
 133 // Start of body: indices are calculated from IV:
 134 // ... loop body ...
 135 // End of body: store into a[i]:
 136     a[i] = b[i] * c[i] * d[i];
 137   }
 138 }
 139
 140 int foo() { extern void mayThrow(); mayThrow(); return 0; };
 141
 142 void parallel_for(float *a, const int n) {
 143   float arr[n];
 144 #pragma omp parallel for schedule(static, 5) private(arr) default(none) firstprivate(n) shared(a)
 145   for (unsigned i = 131071; i <= 2147483647; i += 127)
 146     a[i] += foo() + arr[i] + n;
 147 }
 148 // Check source line corresponds to "#pragma omp parallel for schedule(static, 5)" above:
 149
 150 #else // OMP5
 151 int increment () {
 152   #pragma omp for
 153 // Determine UB = min(UB, GlobalUB)
 154
 155 // Loop header
 156
 157   for (int i = 0 ; i != 5; ++i)
 158 // Start of body: calculate i from IV:
 159     ;
 160   return 0;
 161 }
 162
 163 int decrement_nowait () {
 164   #pragma omp for nowait
 165 // Determine UB = min(UB, GlobalUB)
 166
 167 // Loop header
 168   for (int j = 5 ; j != 0; --j)
 169 // Start of body: calculate i from IV:
 170     ;
 171   return 0;
 172 }
 173
 174 void range_for_single() {
 175   int arr[10] = {0};
 176 #pragma omp parallel for
 177   for (auto &a : arr)
 178     (void)a;
 179 }
 180
 181
 182 // __range = arr;
 183
 184 // __end = end(_range);
 185
 186
 187 // calculate number of elements.
 188
 189 // __begin = begin(range);
 190
 191 // __begin >= __end ? goto then : goto exit;
 192
 193
 194 // lb = 0;
 195
 196 // ub = number of elements
 197
 198 // stride = 1;
 199
 200 // is_last = 0;
 201
 202 // loop.
 203
 204 // ub = (ub > number_of_elems ? number_of_elems : ub);
 205
 206
 207
 208 // OMP%: store i64 [[MIN]], ptr [[UB]],
 209
 210 // iv = lb;
 211
 212 // goto loop;
 213 // loop:
 214
 215
 216 // iv <= ub ? goto body : goto end;
 217
 218 // body:
 219 // __begin = begin(arr) + iv * 1;
 220
 221 // a = *__begin;
 222
 223 // (void)a;
 224
 225 // iv += 1;
 226
 227 // goto loop;
 228
 229 // end:
 230 // exit:
 231
 232 void range_for_collapsed() {
 233   int arr[10] = {0};
 234 #pragma omp parallel for collapse(2)
 235   for (auto &a : arr)
 236     for (auto b : arr)
 237       a = b;
 238 }
 239 #endif // OMP5
 240
 241 #endif // HEADER
 242
 243 // CHECK1-LABEL: define {{[^@]+}}@_Z17with_var_schedulev
 244 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
 245 // CHECK1-NEXT:  entry:
 246 // CHECK1-NEXT:    [[A:%.*]] = alloca double, align 8
 247 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
 248 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
 249 // CHECK1-NEXT:    store double 5.000000e+00, ptr [[A]], align 8
 250 // CHECK1-NEXT:    [[TMP0:%.*]] = load double, ptr [[A]], align 8
 251 // CHECK1-NEXT:    [[CONV:%.*]] = fptosi double [[TMP0]] to i8
 252 // CHECK1-NEXT:    store i8 [[CONV]], ptr [[DOTCAPTURE_EXPR_]], align 1
 253 // CHECK1-NEXT:    [[TMP1:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
 254 // CHECK1-NEXT:    store i8 [[TMP1]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1
 255 // CHECK1-NEXT:    [[TMP2:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8
 256 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2:[0-9]+]], i32 1, ptr @_Z17with_var_schedulev.omp_outlined, i64 [[TMP2]])
 257 // CHECK1-NEXT:    ret void
 258 //
 259 //
 260 // CHECK1-LABEL: define {{[^@]+}}@_Z17with_var_schedulev.omp_outlined
 261 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] {
 262 // CHECK1-NEXT:  entry:
 263 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 264 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 265 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
 266 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
 267 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i64, align 8
 268 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca double, align 8
 269 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 8
 270 // CHECK1-NEXT:    [[I:%.*]] = alloca i64, align 8
 271 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
 272 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
 273 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
 274 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 275 // CHECK1-NEXT:    [[A:%.*]] = alloca double, align 8
 276 // CHECK1-NEXT:    [[I4:%.*]] = alloca i64, align 8
 277 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 278 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 279 // CHECK1-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
 280 // CHECK1-NEXT:    [[TMP0:%.*]] = load double, ptr undef, align 8
 281 // CHECK1-NEXT:    [[ADD:%.*]] = fadd double 2.000000e+00, [[TMP0]]
 282 // CHECK1-NEXT:    store double [[ADD]], ptr [[DOTCAPTURE_EXPR_1]], align 8
 283 // CHECK1-NEXT:    [[TMP1:%.*]] = load double, ptr [[DOTCAPTURE_EXPR_1]], align 8
 284 // CHECK1-NEXT:    [[SUB:%.*]] = fsub double [[TMP1]], 1.000000e+00
 285 // CHECK1-NEXT:    [[DIV:%.*]] = fdiv double [[SUB]], 1.000000e+00
 286 // CHECK1-NEXT:    [[CONV:%.*]] = fptoui double [[DIV]] to i64
 287 // CHECK1-NEXT:    [[SUB3:%.*]] = sub i64 [[CONV]], 1
 288 // CHECK1-NEXT:    store i64 [[SUB3]], ptr [[DOTCAPTURE_EXPR_2]], align 8
 289 // CHECK1-NEXT:    store i64 1, ptr [[I]], align 8
 290 // CHECK1-NEXT:    [[TMP2:%.*]] = load double, ptr [[DOTCAPTURE_EXPR_1]], align 8
 291 // CHECK1-NEXT:    [[CMP:%.*]] = fcmp olt double 1.000000e+00, [[TMP2]]
 292 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
 293 // CHECK1:       omp.precond.then:
 294 // CHECK1-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8
 295 // CHECK1-NEXT:    [[TMP3:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_2]], align 8
 296 // CHECK1-NEXT:    store i64 [[TMP3]], ptr [[DOTOMP_UB]], align 8
 297 // CHECK1-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8
 298 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 299 // CHECK1-NEXT:    [[TMP4:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1
 300 // CHECK1-NEXT:    [[CONV5:%.*]] = sext i8 [[TMP4]] to i64
 301 // CHECK1-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 302 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
 303 // CHECK1-NEXT:    call void @__kmpc_for_static_init_8u(ptr @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 [[CONV5]])
 304 // CHECK1-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
 305 // CHECK1:       omp.dispatch.cond:
 306 // CHECK1-NEXT:    [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
 307 // CHECK1-NEXT:    [[TMP8:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_2]], align 8
 308 // CHECK1-NEXT:    [[CMP6:%.*]] = icmp ugt i64 [[TMP7]], [[TMP8]]
 309 // CHECK1-NEXT:    br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 310 // CHECK1:       cond.true:
 311 // CHECK1-NEXT:    [[TMP9:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_2]], align 8
 312 // CHECK1-NEXT:    br label [[COND_END:%.*]]
 313 // CHECK1:       cond.false:
 314 // CHECK1-NEXT:    [[TMP10:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
 315 // CHECK1-NEXT:    br label [[COND_END]]
 316 // CHECK1:       cond.end:
 317 // CHECK1-NEXT:    [[COND:%.*]] = phi i64 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
 318 // CHECK1-NEXT:    store i64 [[COND]], ptr [[DOTOMP_UB]], align 8
 319 // CHECK1-NEXT:    [[TMP11:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
 320 // CHECK1-NEXT:    store i64 [[TMP11]], ptr [[DOTOMP_IV]], align 8
 321 // CHECK1-NEXT:    [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
 322 // CHECK1-NEXT:    [[TMP13:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
 323 // CHECK1-NEXT:    [[ADD7:%.*]] = add i64 [[TMP13]], 1
 324 // CHECK1-NEXT:    [[CMP8:%.*]] = icmp ult i64 [[TMP12]], [[ADD7]]
 325 // CHECK1-NEXT:    br i1 [[CMP8]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
 326 // CHECK1:       omp.dispatch.body:
 327 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 328 // CHECK1:       omp.inner.for.cond:
 329 // CHECK1-NEXT:    [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
 330 // CHECK1-NEXT:    [[TMP15:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
 331 // CHECK1-NEXT:    [[ADD9:%.*]] = add i64 [[TMP15]], 1
 332 // CHECK1-NEXT:    [[CMP10:%.*]] = icmp ult i64 [[TMP14]], [[ADD9]]
 333 // CHECK1-NEXT:    br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 334 // CHECK1:       omp.inner.for.body:
 335 // CHECK1-NEXT:    [[TMP16:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
 336 // CHECK1-NEXT:    [[MUL:%.*]] = mul i64 [[TMP16]], 1
 337 // CHECK1-NEXT:    [[ADD11:%.*]] = add i64 1, [[MUL]]
 338 // CHECK1-NEXT:    store i64 [[ADD11]], ptr [[I4]], align 8
 339 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 340 // CHECK1:       omp.body.continue:
 341 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 342 // CHECK1:       omp.inner.for.inc:
 343 // CHECK1-NEXT:    [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
 344 // CHECK1-NEXT:    [[ADD12:%.*]] = add i64 [[TMP17]], 1
 345 // CHECK1-NEXT:    store i64 [[ADD12]], ptr [[DOTOMP_IV]], align 8
 346 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]
 347 // CHECK1:       omp.inner.for.end:
 348 // CHECK1-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
 349 // CHECK1:       omp.dispatch.inc:
 350 // CHECK1-NEXT:    [[TMP18:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
 351 // CHECK1-NEXT:    [[TMP19:%.*]] = load i64, ptr [[DOTOMP_STRIDE]], align 8
 352 // CHECK1-NEXT:    [[ADD13:%.*]] = add i64 [[TMP18]], [[TMP19]]
 353 // CHECK1-NEXT:    store i64 [[ADD13]], ptr [[DOTOMP_LB]], align 8
 354 // CHECK1-NEXT:    [[TMP20:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
 355 // CHECK1-NEXT:    [[TMP21:%.*]] = load i64, ptr [[DOTOMP_STRIDE]], align 8
 356 // CHECK1-NEXT:    [[ADD14:%.*]] = add i64 [[TMP20]], [[TMP21]]
 357 // CHECK1-NEXT:    store i64 [[ADD14]], ptr [[DOTOMP_UB]], align 8
 358 // CHECK1-NEXT:    br label [[OMP_DISPATCH_COND]]
 359 // CHECK1:       omp.dispatch.end:
 360 // CHECK1-NEXT:    [[TMP22:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 361 // CHECK1-NEXT:    [[TMP23:%.*]] = load i32, ptr [[TMP22]], align 4
 362 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP23]])
 363 // CHECK1-NEXT:    br label [[OMP_PRECOND_END]]
 364 // CHECK1:       omp.precond.end:
 365 // CHECK1-NEXT:    ret void
 366 //
 367 //
 368 // CHECK1-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_
 369 // CHECK1-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
 370 // CHECK1-NEXT:  entry:
 371 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
 372 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
 373 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
 374 // CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
 375 // CHECK1-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
 376 // CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
 377 // CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
 378 // CHECK1-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
 379 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @_Z23without_schedule_clausePfS_S_S_.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])
 380 // CHECK1-NEXT:    ret void
 381 //
 382 //
 383 // CHECK1-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_.omp_outlined
 384 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] {
 385 // CHECK1-NEXT:  entry:
 386 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 387 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 388 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
 389 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
 390 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
 391 // CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
 392 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 393 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 394 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
 395 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
 396 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 397 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 398 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
 399 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 400 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 401 // CHECK1-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
 402 // CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
 403 // CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
 404 // CHECK1-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
 405 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
 406 // CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
 407 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8
 408 // CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8
 409 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
 410 // CHECK1-NEXT:    store i32 4571423, ptr [[DOTOMP_UB]], align 4
 411 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 412 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 413 // CHECK1-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 414 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
 415 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
 416 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 417 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423
 418 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 419 // CHECK1:       cond.true:
 420 // CHECK1-NEXT:    br label [[COND_END:%.*]]
 421 // CHECK1:       cond.false:
 422 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 423 // CHECK1-NEXT:    br label [[COND_END]]
 424 // CHECK1:       cond.end:
 425 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
 426 // CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
 427 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
 428 // CHECK1-NEXT:    store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4
 429 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 430 // CHECK1:       omp.inner.for.cond:
 431 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 432 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 433 // CHECK1-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
 434 // CHECK1-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 435 // CHECK1:       omp.inner.for.body:
 436 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 437 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7
 438 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 33, [[MUL]]
 439 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[I]], align 4
 440 // CHECK1-NEXT:    [[TMP12:%.*]] = load ptr, ptr [[TMP1]], align 8
 441 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, ptr [[I]], align 4
 442 // CHECK1-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64
 443 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP12]], i64 [[IDXPROM]]
 444 // CHECK1-NEXT:    [[TMP14:%.*]] = load float, ptr [[ARRAYIDX]], align 4
 445 // CHECK1-NEXT:    [[TMP15:%.*]] = load ptr, ptr [[TMP2]], align 8
 446 // CHECK1-NEXT:    [[TMP16:%.*]] = load i32, ptr [[I]], align 4
 447 // CHECK1-NEXT:    [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64
 448 // CHECK1-NEXT:    [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP15]], i64 [[IDXPROM2]]
 449 // CHECK1-NEXT:    [[TMP17:%.*]] = load float, ptr [[ARRAYIDX3]], align 4
 450 // CHECK1-NEXT:    [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]]
 451 // CHECK1-NEXT:    [[TMP18:%.*]] = load ptr, ptr [[TMP3]], align 8
 452 // CHECK1-NEXT:    [[TMP19:%.*]] = load i32, ptr [[I]], align 4
 453 // CHECK1-NEXT:    [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64
 454 // CHECK1-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP18]], i64 [[IDXPROM5]]
 455 // CHECK1-NEXT:    [[TMP20:%.*]] = load float, ptr [[ARRAYIDX6]], align 4
 456 // CHECK1-NEXT:    [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]]
 457 // CHECK1-NEXT:    [[TMP21:%.*]] = load ptr, ptr [[TMP0]], align 8
 458 // CHECK1-NEXT:    [[TMP22:%.*]] = load i32, ptr [[I]], align 4
 459 // CHECK1-NEXT:    [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64
 460 // CHECK1-NEXT:    [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP21]], i64 [[IDXPROM8]]
 461 // CHECK1-NEXT:    store float [[MUL7]], ptr [[ARRAYIDX9]], align 4
 462 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 463 // CHECK1:       omp.body.continue:
 464 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 465 // CHECK1:       omp.inner.for.inc:
 466 // CHECK1-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 467 // CHECK1-NEXT:    [[ADD10:%.*]] = add nsw i32 [[TMP23]], 1
 468 // CHECK1-NEXT:    store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4
 469 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]
 470 // CHECK1:       omp.inner.for.end:
 471 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
 472 // CHECK1:       omp.loop.exit:
 473 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])
 474 // CHECK1-NEXT:    ret void
 475 //
 476 //
 477 // CHECK1-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_
 478 // CHECK1-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
 479 // CHECK1-NEXT:  entry:
 480 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
 481 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
 482 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
 483 // CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
 484 // CHECK1-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
 485 // CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
 486 // CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
 487 // CHECK1-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
 488 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @_Z18static_not_chunkedPfS_S_S_.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])
 489 // CHECK1-NEXT:    ret void
 490 //
 491 //
 492 // CHECK1-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_.omp_outlined
 493 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] {
 494 // CHECK1-NEXT:  entry:
 495 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 496 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 497 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
 498 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
 499 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
 500 // CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
 501 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 502 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 503 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
 504 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
 505 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 506 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 507 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
 508 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 509 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 510 // CHECK1-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
 511 // CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
 512 // CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
 513 // CHECK1-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
 514 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
 515 // CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
 516 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8
 517 // CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8
 518 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
 519 // CHECK1-NEXT:    store i32 4571423, ptr [[DOTOMP_UB]], align 4
 520 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 521 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 522 // CHECK1-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 523 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
 524 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
 525 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 526 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423
 527 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 528 // CHECK1:       cond.true:
 529 // CHECK1-NEXT:    br label [[COND_END:%.*]]
 530 // CHECK1:       cond.false:
 531 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 532 // CHECK1-NEXT:    br label [[COND_END]]
 533 // CHECK1:       cond.end:
 534 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
 535 // CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
 536 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
 537 // CHECK1-NEXT:    store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4
 538 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 539 // CHECK1:       omp.inner.for.cond:
 540 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 541 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 542 // CHECK1-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
 543 // CHECK1-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 544 // CHECK1:       omp.inner.for.body:
 545 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 546 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7
 547 // CHECK1-NEXT:    [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
 548 // CHECK1-NEXT:    store i32 [[SUB]], ptr [[I]], align 4
 549 // CHECK1-NEXT:    [[TMP12:%.*]] = load ptr, ptr [[TMP1]], align 8
 550 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, ptr [[I]], align 4
 551 // CHECK1-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64
 552 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP12]], i64 [[IDXPROM]]
 553 // CHECK1-NEXT:    [[TMP14:%.*]] = load float, ptr [[ARRAYIDX]], align 4
 554 // CHECK1-NEXT:    [[TMP15:%.*]] = load ptr, ptr [[TMP2]], align 8
 555 // CHECK1-NEXT:    [[TMP16:%.*]] = load i32, ptr [[I]], align 4
 556 // CHECK1-NEXT:    [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64
 557 // CHECK1-NEXT:    [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP15]], i64 [[IDXPROM2]]
 558 // CHECK1-NEXT:    [[TMP17:%.*]] = load float, ptr [[ARRAYIDX3]], align 4
 559 // CHECK1-NEXT:    [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]]
 560 // CHECK1-NEXT:    [[TMP18:%.*]] = load ptr, ptr [[TMP3]], align 8
 561 // CHECK1-NEXT:    [[TMP19:%.*]] = load i32, ptr [[I]], align 4
 562 // CHECK1-NEXT:    [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64
 563 // CHECK1-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP18]], i64 [[IDXPROM5]]
 564 // CHECK1-NEXT:    [[TMP20:%.*]] = load float, ptr [[ARRAYIDX6]], align 4
 565 // CHECK1-NEXT:    [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]]
 566 // CHECK1-NEXT:    [[TMP21:%.*]] = load ptr, ptr [[TMP0]], align 8
 567 // CHECK1-NEXT:    [[TMP22:%.*]] = load i32, ptr [[I]], align 4
 568 // CHECK1-NEXT:    [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64
 569 // CHECK1-NEXT:    [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP21]], i64 [[IDXPROM8]]
 570 // CHECK1-NEXT:    store float [[MUL7]], ptr [[ARRAYIDX9]], align 4
 571 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 572 // CHECK1:       omp.body.continue:
 573 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 574 // CHECK1:       omp.inner.for.inc:
 575 // CHECK1-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 576 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP23]], 1
 577 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
 578 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]
 579 // CHECK1:       omp.inner.for.end:
 580 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
 581 // CHECK1:       omp.loop.exit:
 582 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])
 583 // CHECK1-NEXT:    ret void
 584 //
 585 //
 586 // CHECK1-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_
 587 // CHECK1-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
 588 // CHECK1-NEXT:  entry:
 589 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
 590 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
 591 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
 592 // CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
 593 // CHECK1-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
 594 // CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
 595 // CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
 596 // CHECK1-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
 597 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @_Z14static_chunkedPfS_S_S_.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])
 598 // CHECK1-NEXT:    ret void
 599 //
 600 //
 601 // CHECK1-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_.omp_outlined
 602 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] {
 603 // CHECK1-NEXT:  entry:
 604 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 605 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 606 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
 607 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
 608 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
 609 // CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
 610 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 611 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 612 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
 613 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
 614 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 615 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 616 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
 617 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 618 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 619 // CHECK1-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
 620 // CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
 621 // CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
 622 // CHECK1-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
 623 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
 624 // CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
 625 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8
 626 // CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8
 627 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
 628 // CHECK1-NEXT:    store i32 16908288, ptr [[DOTOMP_UB]], align 4
 629 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 630 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 631 // CHECK1-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 632 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
 633 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4u(ptr @[[GLOB1]], i32 [[TMP5]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 5)
 634 // CHECK1-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
 635 // CHECK1:       omp.dispatch.cond:
 636 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 637 // CHECK1-NEXT:    [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288
 638 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 639 // CHECK1:       cond.true:
 640 // CHECK1-NEXT:    br label [[COND_END:%.*]]
 641 // CHECK1:       cond.false:
 642 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 643 // CHECK1-NEXT:    br label [[COND_END]]
 644 // CHECK1:       cond.end:
 645 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
 646 // CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
 647 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
 648 // CHECK1-NEXT:    store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4
 649 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 650 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 651 // CHECK1-NEXT:    [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]
 652 // CHECK1-NEXT:    br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
 653 // CHECK1:       omp.dispatch.body:
 654 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 655 // CHECK1:       omp.inner.for.cond:
 656 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 657 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 658 // CHECK1-NEXT:    [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]
 659 // CHECK1-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 660 // CHECK1:       omp.inner.for.body:
 661 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 662 // CHECK1-NEXT:    [[MUL:%.*]] = mul i32 [[TMP13]], 127
 663 // CHECK1-NEXT:    [[ADD:%.*]] = add i32 131071, [[MUL]]
 664 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[I]], align 4
 665 // CHECK1-NEXT:    [[TMP14:%.*]] = load ptr, ptr [[TMP1]], align 8
 666 // CHECK1-NEXT:    [[TMP15:%.*]] = load i32, ptr [[I]], align 4
 667 // CHECK1-NEXT:    [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64
 668 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP14]], i64 [[IDXPROM]]
 669 // CHECK1-NEXT:    [[TMP16:%.*]] = load float, ptr [[ARRAYIDX]], align 4
 670 // CHECK1-NEXT:    [[TMP17:%.*]] = load ptr, ptr [[TMP2]], align 8
 671 // CHECK1-NEXT:    [[TMP18:%.*]] = load i32, ptr [[I]], align 4
 672 // CHECK1-NEXT:    [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64
 673 // CHECK1-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds float, ptr [[TMP17]], i64 [[IDXPROM3]]
 674 // CHECK1-NEXT:    [[TMP19:%.*]] = load float, ptr [[ARRAYIDX4]], align 4
 675 // CHECK1-NEXT:    [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]]
 676 // CHECK1-NEXT:    [[TMP20:%.*]] = load ptr, ptr [[TMP3]], align 8
 677 // CHECK1-NEXT:    [[TMP21:%.*]] = load i32, ptr [[I]], align 4
 678 // CHECK1-NEXT:    [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64
 679 // CHECK1-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds float, ptr [[TMP20]], i64 [[IDXPROM6]]
 680 // CHECK1-NEXT:    [[TMP22:%.*]] = load float, ptr [[ARRAYIDX7]], align 4
 681 // CHECK1-NEXT:    [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]]
 682 // CHECK1-NEXT:    [[TMP23:%.*]] = load ptr, ptr [[TMP0]], align 8
 683 // CHECK1-NEXT:    [[TMP24:%.*]] = load i32, ptr [[I]], align 4
 684 // CHECK1-NEXT:    [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64
 685 // CHECK1-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP23]], i64 [[IDXPROM9]]
 686 // CHECK1-NEXT:    store float [[MUL8]], ptr [[ARRAYIDX10]], align 4
 687 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 688 // CHECK1:       omp.body.continue:
 689 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 690 // CHECK1:       omp.inner.for.inc:
 691 // CHECK1-NEXT:    [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 692 // CHECK1-NEXT:    [[ADD11:%.*]] = add i32 [[TMP25]], 1
 693 // CHECK1-NEXT:    store i32 [[ADD11]], ptr [[DOTOMP_IV]], align 4
 694 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]
 695 // CHECK1:       omp.inner.for.end:
 696 // CHECK1-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
 697 // CHECK1:       omp.dispatch.inc:
 698 // CHECK1-NEXT:    [[TMP26:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
 699 // CHECK1-NEXT:    [[TMP27:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
 700 // CHECK1-NEXT:    [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]]
 701 // CHECK1-NEXT:    store i32 [[ADD12]], ptr [[DOTOMP_LB]], align 4
 702 // CHECK1-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 703 // CHECK1-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
 704 // CHECK1-NEXT:    [[ADD13:%.*]] = add i32 [[TMP28]], [[TMP29]]
 705 // CHECK1-NEXT:    store i32 [[ADD13]], ptr [[DOTOMP_UB]], align 4
 706 // CHECK1-NEXT:    br label [[OMP_DISPATCH_COND]]
 707 // CHECK1:       omp.dispatch.end:
 708 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])
 709 // CHECK1-NEXT:    ret void
 710 //
 711 //
 712 // CHECK1-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_
 713 // CHECK1-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
 714 // CHECK1-NEXT:  entry:
 715 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
 716 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
 717 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
 718 // CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
 719 // CHECK1-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
 720 // CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
 721 // CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
 722 // CHECK1-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
 723 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @_Z8dynamic1PfS_S_S_.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])
 724 // CHECK1-NEXT:    ret void
 725 //
 726 //
 727 // CHECK1-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_.omp_outlined
 728 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] {
 729 // CHECK1-NEXT:  entry:
 730 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 731 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 732 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
 733 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
 734 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
 735 // CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
 736 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
 737 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i64, align 8
 738 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
 739 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
 740 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
 741 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 742 // CHECK1-NEXT:    [[I:%.*]] = alloca i64, align 8
 743 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 744 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 745 // CHECK1-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
 746 // CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
 747 // CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
 748 // CHECK1-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
 749 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
 750 // CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
 751 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8
 752 // CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8
 753 // CHECK1-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8
 754 // CHECK1-NEXT:    store i64 16908287, ptr [[DOTOMP_UB]], align 8
 755 // CHECK1-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8
 756 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 757 // CHECK1-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 758 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
 759 // CHECK1-NEXT:    call void @__kmpc_dispatch_init_8u(ptr @[[GLOB2]], i32 [[TMP5]], i32 1073741859, i64 0, i64 16908287, i64 1, i64 1)
 760 // CHECK1-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
 761 // CHECK1:       omp.dispatch.cond:
 762 // CHECK1-NEXT:    [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_8u(ptr @[[GLOB2]], i32 [[TMP5]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
 763 // CHECK1-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0
 764 // CHECK1-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
 765 // CHECK1:       omp.dispatch.body:
 766 // CHECK1-NEXT:    [[TMP7:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
 767 // CHECK1-NEXT:    store i64 [[TMP7]], ptr [[DOTOMP_IV]], align 8
 768 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 769 // CHECK1:       omp.inner.for.cond:
 770 // CHECK1-NEXT:    [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP5:![0-9]+]]
 771 // CHECK1-NEXT:    [[TMP9:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP5]]
 772 // CHECK1-NEXT:    [[ADD:%.*]] = add i64 [[TMP9]], 1
 773 // CHECK1-NEXT:    [[CMP:%.*]] = icmp ult i64 [[TMP8]], [[ADD]]
 774 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 775 // CHECK1:       omp.inner.for.body:
 776 // CHECK1-NEXT:    [[TMP10:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP5]]
 777 // CHECK1-NEXT:    [[MUL:%.*]] = mul i64 [[TMP10]], 127
 778 // CHECK1-NEXT:    [[ADD1:%.*]] = add i64 131071, [[MUL]]
 779 // CHECK1-NEXT:    store i64 [[ADD1]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP5]]
 780 // CHECK1-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP5]]
 781 // CHECK1-NEXT:    [[TMP12:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP5]]
 782 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP11]], i64 [[TMP12]]
 783 // CHECK1-NEXT:    [[TMP13:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP5]]
 784 // CHECK1-NEXT:    [[TMP14:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP5]]
 785 // CHECK1-NEXT:    [[TMP15:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP5]]
 786 // CHECK1-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[TMP14]], i64 [[TMP15]]
 787 // CHECK1-NEXT:    [[TMP16:%.*]] = load float, ptr [[ARRAYIDX2]], align 4, !llvm.access.group [[ACC_GRP5]]
 788 // CHECK1-NEXT:    [[MUL3:%.*]] = fmul float [[TMP13]], [[TMP16]]
 789 // CHECK1-NEXT:    [[TMP17:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP5]]
 790 // CHECK1-NEXT:    [[TMP18:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP5]]
 791 // CHECK1-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds float, ptr [[TMP17]], i64 [[TMP18]]
 792 // CHECK1-NEXT:    [[TMP19:%.*]] = load float, ptr [[ARRAYIDX4]], align 4, !llvm.access.group [[ACC_GRP5]]
 793 // CHECK1-NEXT:    [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP19]]
 794 // CHECK1-NEXT:    [[TMP20:%.*]] = load ptr, ptr [[TMP0]], align 8, !llvm.access.group [[ACC_GRP5]]
 795 // CHECK1-NEXT:    [[TMP21:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP5]]
 796 // CHECK1-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP20]], i64 [[TMP21]]
 797 // CHECK1-NEXT:    store float [[MUL5]], ptr [[ARRAYIDX6]], align 4, !llvm.access.group [[ACC_GRP5]]
 798 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 799 // CHECK1:       omp.body.continue:
 800 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 801 // CHECK1:       omp.inner.for.inc:
 802 // CHECK1-NEXT:    [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP5]]
 803 // CHECK1-NEXT:    [[ADD7:%.*]] = add i64 [[TMP22]], 1
 804 // CHECK1-NEXT:    store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP5]]
 805 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
 806 // CHECK1:       omp.inner.for.end:
 807 // CHECK1-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
 808 // CHECK1:       omp.dispatch.inc:
 809 // CHECK1-NEXT:    br label [[OMP_DISPATCH_COND]]
 810 // CHECK1:       omp.dispatch.end:
 811 // CHECK1-NEXT:    ret void
 812 //
 813 //
 814 // CHECK1-LABEL: define {{[^@]+}}@_Z7guided7PfS_S_S_
 815 // CHECK1-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
 816 // CHECK1-NEXT:  entry:
 817 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
 818 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
 819 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
 820 // CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
 821 // CHECK1-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
 822 // CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
 823 // CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
 824 // CHECK1-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
 825 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @_Z7guided7PfS_S_S_.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])
 826 // CHECK1-NEXT:    ret void
 827 //
 828 //
 829 // CHECK1-LABEL: define {{[^@]+}}@_Z7guided7PfS_S_S_.omp_outlined
 830 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] {
 831 // CHECK1-NEXT:  entry:
 832 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 833 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 834 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
 835 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
 836 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
 837 // CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
 838 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
 839 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i64, align 8
 840 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
 841 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
 842 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
 843 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 844 // CHECK1-NEXT:    [[I:%.*]] = alloca i64, align 8
 845 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 846 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 847 // CHECK1-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
 848 // CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
 849 // CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
 850 // CHECK1-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
 851 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
 852 // CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
 853 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8
 854 // CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8
 855 // CHECK1-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8
 856 // CHECK1-NEXT:    store i64 16908287, ptr [[DOTOMP_UB]], align 8
 857 // CHECK1-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8
 858 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 859 // CHECK1-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 860 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
 861 // CHECK1-NEXT:    call void @__kmpc_dispatch_init_8u(ptr @[[GLOB2]], i32 [[TMP5]], i32 1073741860, i64 0, i64 16908287, i64 1, i64 7)
 862 // CHECK1-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
 863 // CHECK1:       omp.dispatch.cond:
 864 // CHECK1-NEXT:    [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_8u(ptr @[[GLOB2]], i32 [[TMP5]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
 865 // CHECK1-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0
 866 // CHECK1-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
 867 // CHECK1:       omp.dispatch.body:
 868 // CHECK1-NEXT:    [[TMP7:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
 869 // CHECK1-NEXT:    store i64 [[TMP7]], ptr [[DOTOMP_IV]], align 8
 870 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 871 // CHECK1:       omp.inner.for.cond:
 872 // CHECK1-NEXT:    [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP8:![0-9]+]]
 873 // CHECK1-NEXT:    [[TMP9:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP8]]
 874 // CHECK1-NEXT:    [[ADD:%.*]] = add i64 [[TMP9]], 1
 875 // CHECK1-NEXT:    [[CMP:%.*]] = icmp ult i64 [[TMP8]], [[ADD]]
 876 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 877 // CHECK1:       omp.inner.for.body:
 878 // CHECK1-NEXT:    [[TMP10:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP8]]
 879 // CHECK1-NEXT:    [[MUL:%.*]] = mul i64 [[TMP10]], 127
 880 // CHECK1-NEXT:    [[ADD1:%.*]] = add i64 131071, [[MUL]]
 881 // CHECK1-NEXT:    store i64 [[ADD1]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP8]]
 882 // CHECK1-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP8]]
 883 // CHECK1-NEXT:    [[TMP12:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP8]]
 884 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP11]], i64 [[TMP12]]
 885 // CHECK1-NEXT:    [[TMP13:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP8]]
 886 // CHECK1-NEXT:    [[TMP14:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP8]]
 887 // CHECK1-NEXT:    [[TMP15:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP8]]
 888 // CHECK1-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[TMP14]], i64 [[TMP15]]
 889 // CHECK1-NEXT:    [[TMP16:%.*]] = load float, ptr [[ARRAYIDX2]], align 4, !llvm.access.group [[ACC_GRP8]]
 890 // CHECK1-NEXT:    [[MUL3:%.*]] = fmul float [[TMP13]], [[TMP16]]
 891 // CHECK1-NEXT:    [[TMP17:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP8]]
 892 // CHECK1-NEXT:    [[TMP18:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP8]]
 893 // CHECK1-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds float, ptr [[TMP17]], i64 [[TMP18]]
 894 // CHECK1-NEXT:    [[TMP19:%.*]] = load float, ptr [[ARRAYIDX4]], align 4, !llvm.access.group [[ACC_GRP8]]
 895 // CHECK1-NEXT:    [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP19]]
 896 // CHECK1-NEXT:    [[TMP20:%.*]] = load ptr, ptr [[TMP0]], align 8, !llvm.access.group [[ACC_GRP8]]
 897 // CHECK1-NEXT:    [[TMP21:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP8]]
 898 // CHECK1-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP20]], i64 [[TMP21]]
 899 // CHECK1-NEXT:    store float [[MUL5]], ptr [[ARRAYIDX6]], align 4, !llvm.access.group [[ACC_GRP8]]
 900 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 901 // CHECK1:       omp.body.continue:
 902 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 903 // CHECK1:       omp.inner.for.inc:
 904 // CHECK1-NEXT:    [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP8]]
 905 // CHECK1-NEXT:    [[ADD7:%.*]] = add i64 [[TMP22]], 1
 906 // CHECK1-NEXT:    store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP8]]
 907 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
 908 // CHECK1:       omp.inner.for.end:
 909 // CHECK1-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
 910 // CHECK1:       omp.dispatch.inc:
 911 // CHECK1-NEXT:    br label [[OMP_DISPATCH_COND]]
 912 // CHECK1:       omp.dispatch.end:
 913 // CHECK1-NEXT:    ret void
 914 //
 915 //
 916 // CHECK1-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_
 917 // CHECK1-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
 918 // CHECK1-NEXT:  entry:
 919 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
 920 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
 921 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
 922 // CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
 923 // CHECK1-NEXT:    [[X:%.*]] = alloca i32, align 4
 924 // CHECK1-NEXT:    [[Y:%.*]] = alloca i32, align 4
 925 // CHECK1-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
 926 // CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
 927 // CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
 928 // CHECK1-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
 929 // CHECK1-NEXT:    store i32 0, ptr [[X]], align 4
 930 // CHECK1-NEXT:    store i32 0, ptr [[Y]], align 4
 931 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 5, ptr @_Z9test_autoPfS_S_S_.omp_outlined, ptr [[Y]], ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])
 932 // CHECK1-NEXT:    ret void
 933 //
 934 //
 935 // CHECK1-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_.omp_outlined
 936 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[Y:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] {
 937 // CHECK1-NEXT:  entry:
 938 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 939 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 940 // CHECK1-NEXT:    [[Y_ADDR:%.*]] = alloca ptr, align 8
 941 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
 942 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
 943 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
 944 // CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
 945 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
 946 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i8, align 1
 947 // CHECK1-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
 948 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
 949 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 8
 950 // CHECK1-NEXT:    [[I:%.*]] = alloca i8, align 1
 951 // CHECK1-NEXT:    [[X:%.*]] = alloca i32, align 4
 952 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
 953 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
 954 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
 955 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 956 // CHECK1-NEXT:    [[I7:%.*]] = alloca i8, align 1
 957 // CHECK1-NEXT:    [[X8:%.*]] = alloca i32, align 4
 958 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 959 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 960 // CHECK1-NEXT:    store ptr [[Y]], ptr [[Y_ADDR]], align 8
 961 // CHECK1-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
 962 // CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
 963 // CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
 964 // CHECK1-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
 965 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[Y_ADDR]], align 8
 966 // CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8
 967 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8
 968 // CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
 969 // CHECK1-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[D_ADDR]], align 8
 970 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 4
 971 // CHECK1-NEXT:    [[CONV:%.*]] = trunc i32 [[TMP5]] to i8
 972 // CHECK1-NEXT:    store i8 [[CONV]], ptr [[DOTCAPTURE_EXPR_]], align 1
 973 // CHECK1-NEXT:    [[TMP6:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
 974 // CHECK1-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP6]] to i32
 975 // CHECK1-NEXT:    [[SUB:%.*]] = sub i32 57, [[CONV3]]
 976 // CHECK1-NEXT:    [[ADD:%.*]] = add i32 [[SUB]], 1
 977 // CHECK1-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
 978 // CHECK1-NEXT:    [[CONV4:%.*]] = zext i32 [[DIV]] to i64
 979 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i64 [[CONV4]], 11
 980 // CHECK1-NEXT:    [[SUB5:%.*]] = sub nsw i64 [[MUL]], 1
 981 // CHECK1-NEXT:    store i64 [[SUB5]], ptr [[DOTCAPTURE_EXPR_2]], align 8
 982 // CHECK1-NEXT:    [[TMP7:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
 983 // CHECK1-NEXT:    store i8 [[TMP7]], ptr [[I]], align 1
 984 // CHECK1-NEXT:    store i32 11, ptr [[X]], align 4
 985 // CHECK1-NEXT:    [[TMP8:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
 986 // CHECK1-NEXT:    [[CONV6:%.*]] = sext i8 [[TMP8]] to i32
 987 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sle i32 [[CONV6]], 57
 988 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
 989 // CHECK1:       omp.precond.then:
 990 // CHECK1-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8
 991 // CHECK1-NEXT:    [[TMP9:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_2]], align 8
 992 // CHECK1-NEXT:    store i64 [[TMP9]], ptr [[DOTOMP_UB]], align 8
 993 // CHECK1-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8
 994 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 995 // CHECK1-NEXT:    [[TMP10:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_2]], align 8
 996 // CHECK1-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 997 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4
 998 // CHECK1-NEXT:    call void @__kmpc_dispatch_init_8(ptr @[[GLOB2]], i32 [[TMP12]], i32 1073741862, i64 0, i64 [[TMP10]], i64 1, i64 1)
 999 // CHECK1-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
1000 // CHECK1:       omp.dispatch.cond:
1001 // CHECK1-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1002 // CHECK1-NEXT:    [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4
1003 // CHECK1-NEXT:    [[TMP15:%.*]] = call i32 @__kmpc_dispatch_next_8(ptr @[[GLOB2]], i32 [[TMP14]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
1004 // CHECK1-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0
1005 // CHECK1-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
1006 // CHECK1:       omp.dispatch.body:
1007 // CHECK1-NEXT:    [[TMP16:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
1008 // CHECK1-NEXT:    store i64 [[TMP16]], ptr [[DOTOMP_IV]], align 8
1009 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1010 // CHECK1:       omp.inner.for.cond:
1011 // CHECK1-NEXT:    [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP11:![0-9]+]]
1012 // CHECK1-NEXT:    [[TMP18:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP11]]
1013 // CHECK1-NEXT:    [[CMP9:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]]
1014 // CHECK1-NEXT:    br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1015 // CHECK1:       omp.inner.for.body:
1016 // CHECK1-NEXT:    [[TMP19:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group [[ACC_GRP11]]
1017 // CHECK1-NEXT:    [[CONV10:%.*]] = sext i8 [[TMP19]] to i64
1018 // CHECK1-NEXT:    [[TMP20:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP11]]
1019 // CHECK1-NEXT:    [[DIV11:%.*]] = sdiv i64 [[TMP20]], 11
1020 // CHECK1-NEXT:    [[MUL12:%.*]] = mul nsw i64 [[DIV11]], 1
1021 // CHECK1-NEXT:    [[ADD13:%.*]] = add nsw i64 [[CONV10]], [[MUL12]]
1022 // CHECK1-NEXT:    [[CONV14:%.*]] = trunc i64 [[ADD13]] to i8
1023 // CHECK1-NEXT:    store i8 [[CONV14]], ptr [[I7]], align 1, !llvm.access.group [[ACC_GRP11]]
1024 // CHECK1-NEXT:    [[TMP21:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP11]]
1025 // CHECK1-NEXT:    [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP11]]
1026 // CHECK1-NEXT:    [[DIV15:%.*]] = sdiv i64 [[TMP22]], 11
1027 // CHECK1-NEXT:    [[MUL16:%.*]] = mul nsw i64 [[DIV15]], 11
1028 // CHECK1-NEXT:    [[SUB17:%.*]] = sub nsw i64 [[TMP21]], [[MUL16]]
1029 // CHECK1-NEXT:    [[MUL18:%.*]] = mul nsw i64 [[SUB17]], 1
1030 // CHECK1-NEXT:    [[SUB19:%.*]] = sub nsw i64 11, [[MUL18]]
1031 // CHECK1-NEXT:    [[CONV20:%.*]] = trunc i64 [[SUB19]] to i32
1032 // CHECK1-NEXT:    store i32 [[CONV20]], ptr [[X8]], align 4, !llvm.access.group [[ACC_GRP11]]
1033 // CHECK1-NEXT:    [[TMP23:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP11]]
1034 // CHECK1-NEXT:    [[TMP24:%.*]] = load i8, ptr [[I7]], align 1, !llvm.access.group [[ACC_GRP11]]
1035 // CHECK1-NEXT:    [[IDXPROM:%.*]] = sext i8 [[TMP24]] to i64
1036 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP23]], i64 [[IDXPROM]]
1037 // CHECK1-NEXT:    [[TMP25:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP11]]
1038 // CHECK1-NEXT:    [[TMP26:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP11]]
1039 // CHECK1-NEXT:    [[TMP27:%.*]] = load i8, ptr [[I7]], align 1, !llvm.access.group [[ACC_GRP11]]
1040 // CHECK1-NEXT:    [[IDXPROM21:%.*]] = sext i8 [[TMP27]] to i64
1041 // CHECK1-NEXT:    [[ARRAYIDX22:%.*]] = getelementptr inbounds float, ptr [[TMP26]], i64 [[IDXPROM21]]
1042 // CHECK1-NEXT:    [[TMP28:%.*]] = load float, ptr [[ARRAYIDX22]], align 4, !llvm.access.group [[ACC_GRP11]]
1043 // CHECK1-NEXT:    [[MUL23:%.*]] = fmul float [[TMP25]], [[TMP28]]
1044 // CHECK1-NEXT:    [[TMP29:%.*]] = load ptr, ptr [[TMP4]], align 8, !llvm.access.group [[ACC_GRP11]]
1045 // CHECK1-NEXT:    [[TMP30:%.*]] = load i8, ptr [[I7]], align 1, !llvm.access.group [[ACC_GRP11]]
1046 // CHECK1-NEXT:    [[IDXPROM24:%.*]] = sext i8 [[TMP30]] to i64
1047 // CHECK1-NEXT:    [[ARRAYIDX25:%.*]] = getelementptr inbounds float, ptr [[TMP29]], i64 [[IDXPROM24]]
1048 // CHECK1-NEXT:    [[TMP31:%.*]] = load float, ptr [[ARRAYIDX25]], align 4, !llvm.access.group [[ACC_GRP11]]
1049 // CHECK1-NEXT:    [[MUL26:%.*]] = fmul float [[MUL23]], [[TMP31]]
1050 // CHECK1-NEXT:    [[TMP32:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP11]]
1051 // CHECK1-NEXT:    [[TMP33:%.*]] = load i8, ptr [[I7]], align 1, !llvm.access.group [[ACC_GRP11]]
1052 // CHECK1-NEXT:    [[IDXPROM27:%.*]] = sext i8 [[TMP33]] to i64
1053 // CHECK1-NEXT:    [[ARRAYIDX28:%.*]] = getelementptr inbounds float, ptr [[TMP32]], i64 [[IDXPROM27]]
1054 // CHECK1-NEXT:    store float [[MUL26]], ptr [[ARRAYIDX28]], align 4, !llvm.access.group [[ACC_GRP11]]
1055 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1056 // CHECK1:       omp.body.continue:
1057 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1058 // CHECK1:       omp.inner.for.inc:
1059 // CHECK1-NEXT:    [[TMP34:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP11]]
1060 // CHECK1-NEXT:    [[ADD29:%.*]] = add nsw i64 [[TMP34]], 1
1061 // CHECK1-NEXT:    store i64 [[ADD29]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP11]]
1062 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
1063 // CHECK1:       omp.inner.for.end:
1064 // CHECK1-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
1065 // CHECK1:       omp.dispatch.inc:
1066 // CHECK1-NEXT:    br label [[OMP_DISPATCH_COND]]
1067 // CHECK1:       omp.dispatch.end:
1068 // CHECK1-NEXT:    br label [[OMP_PRECOND_END]]
1069 // CHECK1:       omp.precond.end:
1070 // CHECK1-NEXT:    ret void
1071 //
1072 //
1073 // CHECK1-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_
1074 // CHECK1-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
1075 // CHECK1-NEXT:  entry:
1076 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
1077 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
1078 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
1079 // CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
1080 // CHECK1-NEXT:    [[X:%.*]] = alloca i32, align 4
1081 // CHECK1-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
1082 // CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
1083 // CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
1084 // CHECK1-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
1085 // CHECK1-NEXT:    store i32 0, ptr [[X]], align 4
1086 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @_Z7runtimePfS_S_S_.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])
1087 // CHECK1-NEXT:    ret void
1088 //
1089 //
1090 // CHECK1-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_.omp_outlined
1091 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] {
1092 // CHECK1-NEXT:  entry:
1093 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1094 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1095 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
1096 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
1097 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
1098 // CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
1099 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1100 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i8, align 1
1101 // CHECK1-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
1102 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1103 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1104 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1105 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1106 // CHECK1-NEXT:    [[I:%.*]] = alloca i8, align 1
1107 // CHECK1-NEXT:    [[X:%.*]] = alloca i32, align 4
1108 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1109 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1110 // CHECK1-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
1111 // CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
1112 // CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
1113 // CHECK1-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
1114 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
1115 // CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
1116 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8
1117 // CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8
1118 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
1119 // CHECK1-NEXT:    store i32 199, ptr [[DOTOMP_UB]], align 4
1120 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1121 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1122 // CHECK1-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1123 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
1124 // CHECK1-NEXT:    call void @__kmpc_dispatch_init_4(ptr @[[GLOB2]], i32 [[TMP5]], i32 1073741861, i32 0, i32 199, i32 1, i32 1)
1125 // CHECK1-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
1126 // CHECK1:       omp.dispatch.cond:
1127 // CHECK1-NEXT:    [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB2]], i32 [[TMP5]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
1128 // CHECK1-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0
1129 // CHECK1-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
1130 // CHECK1:       omp.dispatch.body:
1131 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1132 // CHECK1-NEXT:    store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
1133 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1134 // CHECK1:       omp.inner.for.cond:
1135 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14:![0-9]+]]
1136 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP14]]
1137 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
1138 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1139 // CHECK1:       omp.inner.for.body:
1140 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]
1141 // CHECK1-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP10]], 20
1142 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
1143 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 48, [[MUL]]
1144 // CHECK1-NEXT:    [[CONV:%.*]] = trunc i32 [[ADD]] to i8
1145 // CHECK1-NEXT:    store i8 [[CONV]], ptr [[I]], align 1, !llvm.access.group [[ACC_GRP14]]
1146 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]
1147 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]
1148 // CHECK1-NEXT:    [[DIV2:%.*]] = sdiv i32 [[TMP12]], 20
1149 // CHECK1-NEXT:    [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 20
1150 // CHECK1-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL3]]
1151 // CHECK1-NEXT:    [[MUL4:%.*]] = mul nsw i32 [[SUB]], 1
1152 // CHECK1-NEXT:    [[ADD5:%.*]] = add nsw i32 -10, [[MUL4]]
1153 // CHECK1-NEXT:    store i32 [[ADD5]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP14]]
1154 // CHECK1-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP14]]
1155 // CHECK1-NEXT:    [[TMP14:%.*]] = load i8, ptr [[I]], align 1, !llvm.access.group [[ACC_GRP14]]
1156 // CHECK1-NEXT:    [[IDXPROM:%.*]] = zext i8 [[TMP14]] to i64
1157 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP13]], i64 [[IDXPROM]]
1158 // CHECK1-NEXT:    [[TMP15:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP14]]
1159 // CHECK1-NEXT:    [[TMP16:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP14]]
1160 // CHECK1-NEXT:    [[TMP17:%.*]] = load i8, ptr [[I]], align 1, !llvm.access.group [[ACC_GRP14]]
1161 // CHECK1-NEXT:    [[IDXPROM6:%.*]] = zext i8 [[TMP17]] to i64
1162 // CHECK1-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds float, ptr [[TMP16]], i64 [[IDXPROM6]]
1163 // CHECK1-NEXT:    [[TMP18:%.*]] = load float, ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP14]]
1164 // CHECK1-NEXT:    [[MUL8:%.*]] = fmul float [[TMP15]], [[TMP18]]
1165 // CHECK1-NEXT:    [[TMP19:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP14]]
1166 // CHECK1-NEXT:    [[TMP20:%.*]] = load i8, ptr [[I]], align 1, !llvm.access.group [[ACC_GRP14]]
1167 // CHECK1-NEXT:    [[IDXPROM9:%.*]] = zext i8 [[TMP20]] to i64
1168 // CHECK1-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP19]], i64 [[IDXPROM9]]
1169 // CHECK1-NEXT:    [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP14]]
1170 // CHECK1-NEXT:    [[MUL11:%.*]] = fmul float [[MUL8]], [[TMP21]]
1171 // CHECK1-NEXT:    [[TMP22:%.*]] = load ptr, ptr [[TMP0]], align 8, !llvm.access.group [[ACC_GRP14]]
1172 // CHECK1-NEXT:    [[TMP23:%.*]] = load i8, ptr [[I]], align 1, !llvm.access.group [[ACC_GRP14]]
1173 // CHECK1-NEXT:    [[IDXPROM12:%.*]] = zext i8 [[TMP23]] to i64
1174 // CHECK1-NEXT:    [[ARRAYIDX13:%.*]] = getelementptr inbounds float, ptr [[TMP22]], i64 [[IDXPROM12]]
1175 // CHECK1-NEXT:    store float [[MUL11]], ptr [[ARRAYIDX13]], align 4, !llvm.access.group [[ACC_GRP14]]
1176 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1177 // CHECK1:       omp.body.continue:
1178 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1179 // CHECK1:       omp.inner.for.inc:
1180 // CHECK1-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]
1181 // CHECK1-NEXT:    [[ADD14:%.*]] = add nsw i32 [[TMP24]], 1
1182 // CHECK1-NEXT:    store i32 [[ADD14]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]
1183 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
1184 // CHECK1:       omp.inner.for.end:
1185 // CHECK1-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
1186 // CHECK1:       omp.dispatch.inc:
1187 // CHECK1-NEXT:    br label [[OMP_DISPATCH_COND]]
1188 // CHECK1:       omp.dispatch.end:
1189 // CHECK1-NEXT:    ret void
1190 //
1191 //
1192 // CHECK1-LABEL: define {{[^@]+}}@_Z3foov
1193 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] {
1194 // CHECK1-NEXT:  entry:
1195 // CHECK1-NEXT:    call void @_Z8mayThrowv()
1196 // CHECK1-NEXT:    ret i32 0
1197 //
1198 //
1199 // CHECK1-LABEL: define {{[^@]+}}@_Z12parallel_forPfi
1200 // CHECK1-SAME: (ptr noundef [[A:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] {
1201 // CHECK1-NEXT:  entry:
1202 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
1203 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
1204 // CHECK1-NEXT:    [[SAVED_STACK:%.*]] = alloca ptr, align 8
1205 // CHECK1-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
1206 // CHECK1-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8
1207 // CHECK1-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
1208 // CHECK1-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
1209 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
1210 // CHECK1-NEXT:    [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
1211 // CHECK1-NEXT:    [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
1212 // CHECK1-NEXT:    store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
1213 // CHECK1-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 16
1214 // CHECK1-NEXT:    store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
1215 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4
1216 // CHECK1-NEXT:    store i32 [[TMP3]], ptr [[N_CASTED]], align 4
1217 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8
1218 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @_Z12parallel_forPfi.omp_outlined, ptr [[A_ADDR]], i64 [[TMP1]], i64 [[TMP4]])
1219 // CHECK1-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
1220 // CHECK1-NEXT:    call void @llvm.stackrestore.p0(ptr [[TMP5]])
1221 // CHECK1-NEXT:    ret void
1222 //
1223 //
1224 // CHECK1-LABEL: define {{[^@]+}}@_Z12parallel_forPfi.omp_outlined
1225 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[N:%.*]]) #[[ATTR1]] personality ptr @__gxx_personality_v0 {
1226 // CHECK1-NEXT:  entry:
1227 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1228 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1229 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
1230 // CHECK1-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
1231 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
1232 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1233 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1234 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1235 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1236 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1237 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1238 // CHECK1-NEXT:    [[SAVED_STACK:%.*]] = alloca ptr, align 8
1239 // CHECK1-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
1240 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
1241 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1242 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1243 // CHECK1-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
1244 // CHECK1-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
1245 // CHECK1-NEXT:    store i64 [[N]], ptr [[N_ADDR]], align 8
1246 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
1247 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
1248 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
1249 // CHECK1-NEXT:    store i32 16908288, ptr [[DOTOMP_UB]], align 4
1250 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1251 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1252 // CHECK1-NEXT:    [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
1253 // CHECK1-NEXT:    store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
1254 // CHECK1-NEXT:    [[VLA1:%.*]] = alloca float, i64 [[TMP1]], align 16
1255 // CHECK1-NEXT:    store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
1256 // CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1257 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
1258 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4u(ptr @[[GLOB1]], i32 [[TMP4]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 5)
1259 // CHECK1-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
1260 // CHECK1:       omp.dispatch.cond:
1261 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1262 // CHECK1-NEXT:    [[CMP:%.*]] = icmp ugt i32 [[TMP5]], 16908288
1263 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1264 // CHECK1:       cond.true:
1265 // CHECK1-NEXT:    br label [[COND_END:%.*]]
1266 // CHECK1:       cond.false:
1267 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1268 // CHECK1-NEXT:    br label [[COND_END]]
1269 // CHECK1:       cond.end:
1270 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]
1271 // CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
1272 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1273 // CHECK1-NEXT:    store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
1274 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1275 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1276 // CHECK1-NEXT:    [[CMP2:%.*]] = icmp ule i32 [[TMP8]], [[TMP9]]
1277 // CHECK1-NEXT:    br i1 [[CMP2]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_CLEANUP:%.*]]
1278 // CHECK1:       omp.dispatch.cleanup:
1279 // CHECK1-NEXT:    br label [[OMP_DISPATCH_END:%.*]]
1280 // CHECK1:       omp.dispatch.body:
1281 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1282 // CHECK1:       omp.inner.for.cond:
1283 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1284 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1285 // CHECK1-NEXT:    [[CMP3:%.*]] = icmp ule i32 [[TMP10]], [[TMP11]]
1286 // CHECK1-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1287 // CHECK1:       omp.inner.for.cond.cleanup:
1288 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
1289 // CHECK1:       omp.inner.for.body:
1290 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1291 // CHECK1-NEXT:    [[MUL:%.*]] = mul i32 [[TMP12]], 127
1292 // CHECK1-NEXT:    [[ADD:%.*]] = add i32 131071, [[MUL]]
1293 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[I]], align 4
1294 // CHECK1-NEXT:    [[CALL:%.*]] = invoke noundef i32 @_Z3foov()
1295 // CHECK1-NEXT:    to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]]
1296 // CHECK1:       invoke.cont:
1297 // CHECK1-NEXT:    [[CONV:%.*]] = sitofp i32 [[CALL]] to float
1298 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, ptr [[I]], align 4
1299 // CHECK1-NEXT:    [[IDXPROM:%.*]] = zext i32 [[TMP13]] to i64
1300 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[VLA1]], i64 [[IDXPROM]]
1301 // CHECK1-NEXT:    [[TMP14:%.*]] = load float, ptr [[ARRAYIDX]], align 4
1302 // CHECK1-NEXT:    [[ADD4:%.*]] = fadd float [[CONV]], [[TMP14]]
1303 // CHECK1-NEXT:    [[TMP15:%.*]] = load i32, ptr [[N_ADDR]], align 4
1304 // CHECK1-NEXT:    [[CONV5:%.*]] = sitofp i32 [[TMP15]] to float
1305 // CHECK1-NEXT:    [[ADD6:%.*]] = fadd float [[ADD4]], [[CONV5]]
1306 // CHECK1-NEXT:    [[TMP16:%.*]] = load ptr, ptr [[TMP0]], align 8
1307 // CHECK1-NEXT:    [[TMP17:%.*]] = load i32, ptr [[I]], align 4
1308 // CHECK1-NEXT:    [[IDXPROM7:%.*]] = zext i32 [[TMP17]] to i64
1309 // CHECK1-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds float, ptr [[TMP16]], i64 [[IDXPROM7]]
1310 // CHECK1-NEXT:    [[TMP18:%.*]] = load float, ptr [[ARRAYIDX8]], align 4
1311 // CHECK1-NEXT:    [[ADD9:%.*]] = fadd float [[TMP18]], [[ADD6]]
1312 // CHECK1-NEXT:    store float [[ADD9]], ptr [[ARRAYIDX8]], align 4
1313 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1314 // CHECK1:       omp.body.continue:
1315 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1316 // CHECK1:       omp.inner.for.inc:
1317 // CHECK1-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1318 // CHECK1-NEXT:    [[ADD10:%.*]] = add i32 [[TMP19]], 1
1319 // CHECK1-NEXT:    store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4
1320 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]
1321 // CHECK1:       omp.inner.for.end:
1322 // CHECK1-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
1323 // CHECK1:       omp.dispatch.inc:
1324 // CHECK1-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1325 // CHECK1-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
1326 // CHECK1-NEXT:    [[ADD11:%.*]] = add i32 [[TMP20]], [[TMP21]]
1327 // CHECK1-NEXT:    store i32 [[ADD11]], ptr [[DOTOMP_LB]], align 4
1328 // CHECK1-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1329 // CHECK1-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
1330 // CHECK1-NEXT:    [[ADD12:%.*]] = add i32 [[TMP22]], [[TMP23]]
1331 // CHECK1-NEXT:    store i32 [[ADD12]], ptr [[DOTOMP_UB]], align 4
1332 // CHECK1-NEXT:    br label [[OMP_DISPATCH_COND]]
1333 // CHECK1:       omp.dispatch.end:
1334 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP4]])
1335 // CHECK1-NEXT:    [[TMP24:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
1336 // CHECK1-NEXT:    call void @llvm.stackrestore.p0(ptr [[TMP24]])
1337 // CHECK1-NEXT:    ret void
1338 // CHECK1:       terminate.lpad:
1339 // CHECK1-NEXT:    [[TMP25:%.*]] = landingpad { ptr, i32 }
1340 // CHECK1-NEXT:    catch ptr null
1341 // CHECK1-NEXT:    [[TMP26:%.*]] = extractvalue { ptr, i32 } [[TMP25]], 0
1342 // CHECK1-NEXT:    call void @__clang_call_terminate(ptr [[TMP26]]) #[[ATTR7:[0-9]+]]
1343 // CHECK1-NEXT:    unreachable
1344 //
1345 //
1346 // CHECK1-LABEL: define {{[^@]+}}@__clang_call_terminate
1347 // CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR6:[0-9]+]] comdat {
1348 // CHECK1-NEXT:    [[TMP2:%.*]] = call ptr @__cxa_begin_catch(ptr [[TMP0]]) #[[ATTR2:[0-9]+]]
1349 // CHECK1-NEXT:    call void @_ZSt9terminatev() #[[ATTR7]]
1350 // CHECK1-NEXT:    unreachable
1351 //
1352 //
1353 // CHECK2-LABEL: define {{[^@]+}}@_Z17with_var_schedulev
1354 // CHECK2-SAME: () #[[ATTR0:[0-9]+]] {
1355 // CHECK2-NEXT:  entry:
1356 // CHECK2-NEXT:    [[A:%.*]] = alloca double, align 8
1357 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
1358 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
1359 // CHECK2-NEXT:    store double 5.000000e+00, ptr [[A]], align 8
1360 // CHECK2-NEXT:    [[TMP0:%.*]] = load double, ptr [[A]], align 8
1361 // CHECK2-NEXT:    [[CONV:%.*]] = fptosi double [[TMP0]] to i8
1362 // CHECK2-NEXT:    store i8 [[CONV]], ptr [[DOTCAPTURE_EXPR_]], align 1
1363 // CHECK2-NEXT:    [[TMP1:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
1364 // CHECK2-NEXT:    store i8 [[TMP1]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1
1365 // CHECK2-NEXT:    [[TMP2:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8
1366 // CHECK2-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2:[0-9]+]], i32 1, ptr @_Z17with_var_schedulev.omp_outlined, i64 [[TMP2]])
1367 // CHECK2-NEXT:    ret void
1368 //
1369 //
1370 // CHECK2-LABEL: define {{[^@]+}}@_Z17with_var_schedulev.omp_outlined
1371 // CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] {
1372 // CHECK2-NEXT:  entry:
1373 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1374 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1375 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
1376 // CHECK2-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
1377 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i64, align 8
1378 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca double, align 8
1379 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 8
1380 // CHECK2-NEXT:    [[I:%.*]] = alloca i64, align 8
1381 // CHECK2-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
1382 // CHECK2-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
1383 // CHECK2-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
1384 // CHECK2-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1385 // CHECK2-NEXT:    [[A:%.*]] = alloca double, align 8
1386 // CHECK2-NEXT:    [[I4:%.*]] = alloca i64, align 8
1387 // CHECK2-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1388 // CHECK2-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1389 // CHECK2-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
1390 // CHECK2-NEXT:    [[TMP0:%.*]] = load double, ptr undef, align 8
1391 // CHECK2-NEXT:    [[ADD:%.*]] = fadd double 2.000000e+00, [[TMP0]]
1392 // CHECK2-NEXT:    store double [[ADD]], ptr [[DOTCAPTURE_EXPR_1]], align 8
1393 // CHECK2-NEXT:    [[TMP1:%.*]] = load double, ptr [[DOTCAPTURE_EXPR_1]], align 8
1394 // CHECK2-NEXT:    [[SUB:%.*]] = fsub double [[TMP1]], 1.000000e+00
1395 // CHECK2-NEXT:    [[DIV:%.*]] = fdiv double [[SUB]], 1.000000e+00
1396 // CHECK2-NEXT:    [[CONV:%.*]] = fptoui double [[DIV]] to i64
1397 // CHECK2-NEXT:    [[SUB3:%.*]] = sub i64 [[CONV]], 1
1398 // CHECK2-NEXT:    store i64 [[SUB3]], ptr [[DOTCAPTURE_EXPR_2]], align 8
1399 // CHECK2-NEXT:    store i64 1, ptr [[I]], align 8
1400 // CHECK2-NEXT:    [[TMP2:%.*]] = load double, ptr [[DOTCAPTURE_EXPR_1]], align 8
1401 // CHECK2-NEXT:    [[CMP:%.*]] = fcmp olt double 1.000000e+00, [[TMP2]]
1402 // CHECK2-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
1403 // CHECK2:       omp.precond.then:
1404 // CHECK2-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8
1405 // CHECK2-NEXT:    [[TMP3:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_2]], align 8
1406 // CHECK2-NEXT:    store i64 [[TMP3]], ptr [[DOTOMP_UB]], align 8
1407 // CHECK2-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8
1408 // CHECK2-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1409 // CHECK2-NEXT:    [[TMP4:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1
1410 // CHECK2-NEXT:    [[CONV5:%.*]] = sext i8 [[TMP4]] to i64
1411 // CHECK2-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1412 // CHECK2-NEXT:    [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
1413 // CHECK2-NEXT:    call void @__kmpc_for_static_init_8u(ptr @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 [[CONV5]])
1414 // CHECK2-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
1415 // CHECK2:       omp.dispatch.cond:
1416 // CHECK2-NEXT:    [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
1417 // CHECK2-NEXT:    [[TMP8:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_2]], align 8
1418 // CHECK2-NEXT:    [[CMP6:%.*]] = icmp ugt i64 [[TMP7]], [[TMP8]]
1419 // CHECK2-NEXT:    br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1420 // CHECK2:       cond.true:
1421 // CHECK2-NEXT:    [[TMP9:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_2]], align 8
1422 // CHECK2-NEXT:    br label [[COND_END:%.*]]
1423 // CHECK2:       cond.false:
1424 // CHECK2-NEXT:    [[TMP10:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
1425 // CHECK2-NEXT:    br label [[COND_END]]
1426 // CHECK2:       cond.end:
1427 // CHECK2-NEXT:    [[COND:%.*]] = phi i64 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
1428 // CHECK2-NEXT:    store i64 [[COND]], ptr [[DOTOMP_UB]], align 8
1429 // CHECK2-NEXT:    [[TMP11:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
1430 // CHECK2-NEXT:    store i64 [[TMP11]], ptr [[DOTOMP_IV]], align 8
1431 // CHECK2-NEXT:    [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
1432 // CHECK2-NEXT:    [[TMP13:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
1433 // CHECK2-NEXT:    [[ADD7:%.*]] = add i64 [[TMP13]], 1
1434 // CHECK2-NEXT:    [[CMP8:%.*]] = icmp ult i64 [[TMP12]], [[ADD7]]
1435 // CHECK2-NEXT:    br i1 [[CMP8]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
1436 // CHECK2:       omp.dispatch.body:
1437 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1438 // CHECK2:       omp.inner.for.cond:
1439 // CHECK2-NEXT:    [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
1440 // CHECK2-NEXT:    [[TMP15:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
1441 // CHECK2-NEXT:    [[ADD9:%.*]] = add i64 [[TMP15]], 1
1442 // CHECK2-NEXT:    [[CMP10:%.*]] = icmp ult i64 [[TMP14]], [[ADD9]]
1443 // CHECK2-NEXT:    br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1444 // CHECK2:       omp.inner.for.body:
1445 // CHECK2-NEXT:    [[TMP16:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
1446 // CHECK2-NEXT:    [[MUL:%.*]] = mul i64 [[TMP16]], 1
1447 // CHECK2-NEXT:    [[ADD11:%.*]] = add i64 1, [[MUL]]
1448 // CHECK2-NEXT:    store i64 [[ADD11]], ptr [[I4]], align 8
1449 // CHECK2-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1450 // CHECK2:       omp.body.continue:
1451 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1452 // CHECK2:       omp.inner.for.inc:
1453 // CHECK2-NEXT:    [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
1454 // CHECK2-NEXT:    [[ADD12:%.*]] = add i64 [[TMP17]], 1
1455 // CHECK2-NEXT:    store i64 [[ADD12]], ptr [[DOTOMP_IV]], align 8
1456 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND]]
1457 // CHECK2:       omp.inner.for.end:
1458 // CHECK2-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
1459 // CHECK2:       omp.dispatch.inc:
1460 // CHECK2-NEXT:    [[TMP18:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
1461 // CHECK2-NEXT:    [[TMP19:%.*]] = load i64, ptr [[DOTOMP_STRIDE]], align 8
1462 // CHECK2-NEXT:    [[ADD13:%.*]] = add i64 [[TMP18]], [[TMP19]]
1463 // CHECK2-NEXT:    store i64 [[ADD13]], ptr [[DOTOMP_LB]], align 8
1464 // CHECK2-NEXT:    [[TMP20:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
1465 // CHECK2-NEXT:    [[TMP21:%.*]] = load i64, ptr [[DOTOMP_STRIDE]], align 8
1466 // CHECK2-NEXT:    [[ADD14:%.*]] = add i64 [[TMP20]], [[TMP21]]
1467 // CHECK2-NEXT:    store i64 [[ADD14]], ptr [[DOTOMP_UB]], align 8
1468 // CHECK2-NEXT:    br label [[OMP_DISPATCH_COND]]
1469 // CHECK2:       omp.dispatch.end:
1470 // CHECK2-NEXT:    [[TMP22:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1471 // CHECK2-NEXT:    [[TMP23:%.*]] = load i32, ptr [[TMP22]], align 4
1472 // CHECK2-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP23]])
1473 // CHECK2-NEXT:    br label [[OMP_PRECOND_END]]
1474 // CHECK2:       omp.precond.end:
1475 // CHECK2-NEXT:    ret void
1476 //
1477 //
1478 // CHECK2-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_
1479 // CHECK2-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
1480 // CHECK2-NEXT:  entry:
1481 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
1482 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
1483 // CHECK2-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
1484 // CHECK2-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
1485 // CHECK2-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
1486 // CHECK2-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
1487 // CHECK2-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
1488 // CHECK2-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
1489 // CHECK2-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @_Z23without_schedule_clausePfS_S_S_.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])
1490 // CHECK2-NEXT:    ret void
1491 //
1492 //
1493 // CHECK2-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_.omp_outlined
1494 // CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] {
1495 // CHECK2-NEXT:  entry:
1496 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1497 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1498 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
1499 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
1500 // CHECK2-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
1501 // CHECK2-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
1502 // CHECK2-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1503 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1504 // CHECK2-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1505 // CHECK2-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1506 // CHECK2-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1507 // CHECK2-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1508 // CHECK2-NEXT:    [[I:%.*]] = alloca i32, align 4
1509 // CHECK2-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1510 // CHECK2-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1511 // CHECK2-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
1512 // CHECK2-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
1513 // CHECK2-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
1514 // CHECK2-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
1515 // CHECK2-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
1516 // CHECK2-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
1517 // CHECK2-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8
1518 // CHECK2-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8
1519 // CHECK2-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
1520 // CHECK2-NEXT:    store i32 4571423, ptr [[DOTOMP_UB]], align 4
1521 // CHECK2-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1522 // CHECK2-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1523 // CHECK2-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1524 // CHECK2-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
1525 // CHECK2-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
1526 // CHECK2-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1527 // CHECK2-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423
1528 // CHECK2-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1529 // CHECK2:       cond.true:
1530 // CHECK2-NEXT:    br label [[COND_END:%.*]]
1531 // CHECK2:       cond.false:
1532 // CHECK2-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1533 // CHECK2-NEXT:    br label [[COND_END]]
1534 // CHECK2:       cond.end:
1535 // CHECK2-NEXT:    [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
1536 // CHECK2-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
1537 // CHECK2-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1538 // CHECK2-NEXT:    store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4
1539 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1540 // CHECK2:       omp.inner.for.cond:
1541 // CHECK2-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1542 // CHECK2-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1543 // CHECK2-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
1544 // CHECK2-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1545 // CHECK2:       omp.inner.for.body:
1546 // CHECK2-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1547 // CHECK2-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7
1548 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 33, [[MUL]]
1549 // CHECK2-NEXT:    store i32 [[ADD]], ptr [[I]], align 4
1550 // CHECK2-NEXT:    [[TMP12:%.*]] = load ptr, ptr [[TMP1]], align 8
1551 // CHECK2-NEXT:    [[TMP13:%.*]] = load i32, ptr [[I]], align 4
1552 // CHECK2-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64
1553 // CHECK2-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP12]], i64 [[IDXPROM]]
1554 // CHECK2-NEXT:    [[TMP14:%.*]] = load float, ptr [[ARRAYIDX]], align 4
1555 // CHECK2-NEXT:    [[TMP15:%.*]] = load ptr, ptr [[TMP2]], align 8
1556 // CHECK2-NEXT:    [[TMP16:%.*]] = load i32, ptr [[I]], align 4
1557 // CHECK2-NEXT:    [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64
1558 // CHECK2-NEXT:    [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP15]], i64 [[IDXPROM2]]
1559 // CHECK2-NEXT:    [[TMP17:%.*]] = load float, ptr [[ARRAYIDX3]], align 4
1560 // CHECK2-NEXT:    [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]]
1561 // CHECK2-NEXT:    [[TMP18:%.*]] = load ptr, ptr [[TMP3]], align 8
1562 // CHECK2-NEXT:    [[TMP19:%.*]] = load i32, ptr [[I]], align 4
1563 // CHECK2-NEXT:    [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64
1564 // CHECK2-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP18]], i64 [[IDXPROM5]]
1565 // CHECK2-NEXT:    [[TMP20:%.*]] = load float, ptr [[ARRAYIDX6]], align 4
1566 // CHECK2-NEXT:    [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]]
1567 // CHECK2-NEXT:    [[TMP21:%.*]] = load ptr, ptr [[TMP0]], align 8
1568 // CHECK2-NEXT:    [[TMP22:%.*]] = load i32, ptr [[I]], align 4
1569 // CHECK2-NEXT:    [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64
1570 // CHECK2-NEXT:    [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP21]], i64 [[IDXPROM8]]
1571 // CHECK2-NEXT:    store float [[MUL7]], ptr [[ARRAYIDX9]], align 4
1572 // CHECK2-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1573 // CHECK2:       omp.body.continue:
1574 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1575 // CHECK2:       omp.inner.for.inc:
1576 // CHECK2-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1577 // CHECK2-NEXT:    [[ADD10:%.*]] = add nsw i32 [[TMP23]], 1
1578 // CHECK2-NEXT:    store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4
1579 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND]]
1580 // CHECK2:       omp.inner.for.end:
1581 // CHECK2-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1582 // CHECK2:       omp.loop.exit:
1583 // CHECK2-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])
1584 // CHECK2-NEXT:    ret void
1585 //
1586 //
1587 // CHECK2-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_
1588 // CHECK2-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
1589 // CHECK2-NEXT:  entry:
1590 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
1591 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
1592 // CHECK2-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
1593 // CHECK2-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
1594 // CHECK2-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
1595 // CHECK2-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
1596 // CHECK2-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
1597 // CHECK2-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
1598 // CHECK2-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @_Z18static_not_chunkedPfS_S_S_.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])
1599 // CHECK2-NEXT:    ret void
1600 //
1601 //
1602 // CHECK2-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_.omp_outlined
1603 // CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] {
1604 // CHECK2-NEXT:  entry:
1605 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1606 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1607 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
1608 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
1609 // CHECK2-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
1610 // CHECK2-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
1611 // CHECK2-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1612 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1613 // CHECK2-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1614 // CHECK2-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1615 // CHECK2-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1616 // CHECK2-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1617 // CHECK2-NEXT:    [[I:%.*]] = alloca i32, align 4
1618 // CHECK2-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1619 // CHECK2-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1620 // CHECK2-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
1621 // CHECK2-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
1622 // CHECK2-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
1623 // CHECK2-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
1624 // CHECK2-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
1625 // CHECK2-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
1626 // CHECK2-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8
1627 // CHECK2-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8
1628 // CHECK2-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
1629 // CHECK2-NEXT:    store i32 4571423, ptr [[DOTOMP_UB]], align 4
1630 // CHECK2-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1631 // CHECK2-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1632 // CHECK2-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1633 // CHECK2-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
1634 // CHECK2-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
1635 // CHECK2-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1636 // CHECK2-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423
1637 // CHECK2-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1638 // CHECK2:       cond.true:
1639 // CHECK2-NEXT:    br label [[COND_END:%.*]]
1640 // CHECK2:       cond.false:
1641 // CHECK2-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1642 // CHECK2-NEXT:    br label [[COND_END]]
1643 // CHECK2:       cond.end:
1644 // CHECK2-NEXT:    [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
1645 // CHECK2-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
1646 // CHECK2-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1647 // CHECK2-NEXT:    store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4
1648 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1649 // CHECK2:       omp.inner.for.cond:
1650 // CHECK2-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1651 // CHECK2-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1652 // CHECK2-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
1653 // CHECK2-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1654 // CHECK2:       omp.inner.for.body:
1655 // CHECK2-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1656 // CHECK2-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7
1657 // CHECK2-NEXT:    [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
1658 // CHECK2-NEXT:    store i32 [[SUB]], ptr [[I]], align 4
1659 // CHECK2-NEXT:    [[TMP12:%.*]] = load ptr, ptr [[TMP1]], align 8
1660 // CHECK2-NEXT:    [[TMP13:%.*]] = load i32, ptr [[I]], align 4
1661 // CHECK2-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64
1662 // CHECK2-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP12]], i64 [[IDXPROM]]
1663 // CHECK2-NEXT:    [[TMP14:%.*]] = load float, ptr [[ARRAYIDX]], align 4
1664 // CHECK2-NEXT:    [[TMP15:%.*]] = load ptr, ptr [[TMP2]], align 8
1665 // CHECK2-NEXT:    [[TMP16:%.*]] = load i32, ptr [[I]], align 4
1666 // CHECK2-NEXT:    [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64
1667 // CHECK2-NEXT:    [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP15]], i64 [[IDXPROM2]]
1668 // CHECK2-NEXT:    [[TMP17:%.*]] = load float, ptr [[ARRAYIDX3]], align 4
1669 // CHECK2-NEXT:    [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]]
1670 // CHECK2-NEXT:    [[TMP18:%.*]] = load ptr, ptr [[TMP3]], align 8
1671 // CHECK2-NEXT:    [[TMP19:%.*]] = load i32, ptr [[I]], align 4
1672 // CHECK2-NEXT:    [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64
1673 // CHECK2-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP18]], i64 [[IDXPROM5]]
1674 // CHECK2-NEXT:    [[TMP20:%.*]] = load float, ptr [[ARRAYIDX6]], align 4
1675 // CHECK2-NEXT:    [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]]
1676 // CHECK2-NEXT:    [[TMP21:%.*]] = load ptr, ptr [[TMP0]], align 8
1677 // CHECK2-NEXT:    [[TMP22:%.*]] = load i32, ptr [[I]], align 4
1678 // CHECK2-NEXT:    [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64
1679 // CHECK2-NEXT:    [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP21]], i64 [[IDXPROM8]]
1680 // CHECK2-NEXT:    store float [[MUL7]], ptr [[ARRAYIDX9]], align 4
1681 // CHECK2-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1682 // CHECK2:       omp.body.continue:
1683 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1684 // CHECK2:       omp.inner.for.inc:
1685 // CHECK2-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1686 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP23]], 1
1687 // CHECK2-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
1688 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND]]
1689 // CHECK2:       omp.inner.for.end:
1690 // CHECK2-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1691 // CHECK2:       omp.loop.exit:
1692 // CHECK2-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])
1693 // CHECK2-NEXT:    ret void
1694 //
1695 //
1696 // CHECK2-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_
1697 // CHECK2-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
1698 // CHECK2-NEXT:  entry:
1699 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
1700 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
1701 // CHECK2-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
1702 // CHECK2-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
1703 // CHECK2-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
1704 // CHECK2-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
1705 // CHECK2-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
1706 // CHECK2-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
1707 // CHECK2-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @_Z14static_chunkedPfS_S_S_.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])
1708 // CHECK2-NEXT:    ret void
1709 //
1710 //
1711 // CHECK2-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_.omp_outlined
1712 // CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] {
1713 // CHECK2-NEXT:  entry:
1714 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1715 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1716 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
1717 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
1718 // CHECK2-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
1719 // CHECK2-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
1720 // CHECK2-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1721 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1722 // CHECK2-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1723 // CHECK2-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1724 // CHECK2-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1725 // CHECK2-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1726 // CHECK2-NEXT:    [[I:%.*]] = alloca i32, align 4
1727 // CHECK2-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1728 // CHECK2-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1729 // CHECK2-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
1730 // CHECK2-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
1731 // CHECK2-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
1732 // CHECK2-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
1733 // CHECK2-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
1734 // CHECK2-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
1735 // CHECK2-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8
1736 // CHECK2-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8
1737 // CHECK2-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
1738 // CHECK2-NEXT:    store i32 16908288, ptr [[DOTOMP_UB]], align 4
1739 // CHECK2-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1740 // CHECK2-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1741 // CHECK2-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1742 // CHECK2-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
1743 // CHECK2-NEXT:    call void @__kmpc_for_static_init_4u(ptr @[[GLOB1]], i32 [[TMP5]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 5)
1744 // CHECK2-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
1745 // CHECK2:       omp.dispatch.cond:
1746 // CHECK2-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1747 // CHECK2-NEXT:    [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288
1748 // CHECK2-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1749 // CHECK2:       cond.true:
1750 // CHECK2-NEXT:    br label [[COND_END:%.*]]
1751 // CHECK2:       cond.false:
1752 // CHECK2-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1753 // CHECK2-NEXT:    br label [[COND_END]]
1754 // CHECK2:       cond.end:
1755 // CHECK2-NEXT:    [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
1756 // CHECK2-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
1757 // CHECK2-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1758 // CHECK2-NEXT:    store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4
1759 // CHECK2-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1760 // CHECK2-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1761 // CHECK2-NEXT:    [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]
1762 // CHECK2-NEXT:    br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
1763 // CHECK2:       omp.dispatch.body:
1764 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1765 // CHECK2:       omp.inner.for.cond:
1766 // CHECK2-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1767 // CHECK2-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1768 // CHECK2-NEXT:    [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]
1769 // CHECK2-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1770 // CHECK2:       omp.inner.for.body:
1771 // CHECK2-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1772 // CHECK2-NEXT:    [[MUL:%.*]] = mul i32 [[TMP13]], 127
1773 // CHECK2-NEXT:    [[ADD:%.*]] = add i32 131071, [[MUL]]
1774 // CHECK2-NEXT:    store i32 [[ADD]], ptr [[I]], align 4
1775 // CHECK2-NEXT:    [[TMP14:%.*]] = load ptr, ptr [[TMP1]], align 8
1776 // CHECK2-NEXT:    [[TMP15:%.*]] = load i32, ptr [[I]], align 4
1777 // CHECK2-NEXT:    [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64
1778 // CHECK2-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP14]], i64 [[IDXPROM]]
1779 // CHECK2-NEXT:    [[TMP16:%.*]] = load float, ptr [[ARRAYIDX]], align 4
1780 // CHECK2-NEXT:    [[TMP17:%.*]] = load ptr, ptr [[TMP2]], align 8
1781 // CHECK2-NEXT:    [[TMP18:%.*]] = load i32, ptr [[I]], align 4
1782 // CHECK2-NEXT:    [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64
1783 // CHECK2-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds float, ptr [[TMP17]], i64 [[IDXPROM3]]
1784 // CHECK2-NEXT:    [[TMP19:%.*]] = load float, ptr [[ARRAYIDX4]], align 4
1785 // CHECK2-NEXT:    [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]]
1786 // CHECK2-NEXT:    [[TMP20:%.*]] = load ptr, ptr [[TMP3]], align 8
1787 // CHECK2-NEXT:    [[TMP21:%.*]] = load i32, ptr [[I]], align 4
1788 // CHECK2-NEXT:    [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64
1789 // CHECK2-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds float, ptr [[TMP20]], i64 [[IDXPROM6]]
1790 // CHECK2-NEXT:    [[TMP22:%.*]] = load float, ptr [[ARRAYIDX7]], align 4
1791 // CHECK2-NEXT:    [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]]
1792 // CHECK2-NEXT:    [[TMP23:%.*]] = load ptr, ptr [[TMP0]], align 8
1793 // CHECK2-NEXT:    [[TMP24:%.*]] = load i32, ptr [[I]], align 4
1794 // CHECK2-NEXT:    [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64
1795 // CHECK2-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP23]], i64 [[IDXPROM9]]
1796 // CHECK2-NEXT:    store float [[MUL8]], ptr [[ARRAYIDX10]], align 4
1797 // CHECK2-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1798 // CHECK2:       omp.body.continue:
1799 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1800 // CHECK2:       omp.inner.for.inc:
1801 // CHECK2-NEXT:    [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1802 // CHECK2-NEXT:    [[ADD11:%.*]] = add i32 [[TMP25]], 1
1803 // CHECK2-NEXT:    store i32 [[ADD11]], ptr [[DOTOMP_IV]], align 4
1804 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND]]
1805 // CHECK2:       omp.inner.for.end:
1806 // CHECK2-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
1807 // CHECK2:       omp.dispatch.inc:
1808 // CHECK2-NEXT:    [[TMP26:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1809 // CHECK2-NEXT:    [[TMP27:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
1810 // CHECK2-NEXT:    [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]]
1811 // CHECK2-NEXT:    store i32 [[ADD12]], ptr [[DOTOMP_LB]], align 4
1812 // CHECK2-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1813 // CHECK2-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
1814 // CHECK2-NEXT:    [[ADD13:%.*]] = add i32 [[TMP28]], [[TMP29]]
1815 // CHECK2-NEXT:    store i32 [[ADD13]], ptr [[DOTOMP_UB]], align 4
1816 // CHECK2-NEXT:    br label [[OMP_DISPATCH_COND]]
1817 // CHECK2:       omp.dispatch.end:
1818 // CHECK2-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])
1819 // CHECK2-NEXT:    ret void
1820 //
1821 //
1822 // CHECK2-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_
1823 // CHECK2-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
1824 // CHECK2-NEXT:  entry:
1825 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
1826 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
1827 // CHECK2-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
1828 // CHECK2-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
1829 // CHECK2-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
1830 // CHECK2-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
1831 // CHECK2-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
1832 // CHECK2-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
1833 // CHECK2-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @_Z8dynamic1PfS_S_S_.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])
1834 // CHECK2-NEXT:    ret void
1835 //
1836 //
1837 // CHECK2-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_.omp_outlined
1838 // CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] {
1839 // CHECK2-NEXT:  entry:
1840 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1841 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1842 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
1843 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
1844 // CHECK2-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
1845 // CHECK2-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
1846 // CHECK2-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
1847 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i64, align 8
1848 // CHECK2-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
1849 // CHECK2-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
1850 // CHECK2-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
1851 // CHECK2-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1852 // CHECK2-NEXT:    [[I:%.*]] = alloca i64, align 8
1853 // CHECK2-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1854 // CHECK2-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1855 // CHECK2-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
1856 // CHECK2-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
1857 // CHECK2-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
1858 // CHECK2-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
1859 // CHECK2-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
1860 // CHECK2-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
1861 // CHECK2-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8
1862 // CHECK2-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8
1863 // CHECK2-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8
1864 // CHECK2-NEXT:    store i64 16908287, ptr [[DOTOMP_UB]], align 8
1865 // CHECK2-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8
1866 // CHECK2-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1867 // CHECK2-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1868 // CHECK2-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
1869 // CHECK2-NEXT:    call void @__kmpc_dispatch_init_8u(ptr @[[GLOB2]], i32 [[TMP5]], i32 35, i64 0, i64 16908287, i64 1, i64 1)
1870 // CHECK2-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
1871 // CHECK2:       omp.dispatch.cond:
1872 // CHECK2-NEXT:    [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_8u(ptr @[[GLOB2]], i32 [[TMP5]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
1873 // CHECK2-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0
1874 // CHECK2-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
1875 // CHECK2:       omp.dispatch.body:
1876 // CHECK2-NEXT:    [[TMP7:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
1877 // CHECK2-NEXT:    store i64 [[TMP7]], ptr [[DOTOMP_IV]], align 8
1878 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1879 // CHECK2:       omp.inner.for.cond:
1880 // CHECK2-NEXT:    [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP5:![0-9]+]]
1881 // CHECK2-NEXT:    [[TMP9:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP5]]
1882 // CHECK2-NEXT:    [[ADD:%.*]] = add i64 [[TMP9]], 1
1883 // CHECK2-NEXT:    [[CMP:%.*]] = icmp ult i64 [[TMP8]], [[ADD]]
1884 // CHECK2-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1885 // CHECK2:       omp.inner.for.body:
1886 // CHECK2-NEXT:    [[TMP10:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP5]]
1887 // CHECK2-NEXT:    [[MUL:%.*]] = mul i64 [[TMP10]], 127
1888 // CHECK2-NEXT:    [[ADD1:%.*]] = add i64 131071, [[MUL]]
1889 // CHECK2-NEXT:    store i64 [[ADD1]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP5]]
1890 // CHECK2-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP5]]
1891 // CHECK2-NEXT:    [[TMP12:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP5]]
1892 // CHECK2-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP11]], i64 [[TMP12]]
1893 // CHECK2-NEXT:    [[TMP13:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP5]]
1894 // CHECK2-NEXT:    [[TMP14:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP5]]
1895 // CHECK2-NEXT:    [[TMP15:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP5]]
1896 // CHECK2-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[TMP14]], i64 [[TMP15]]
1897 // CHECK2-NEXT:    [[TMP16:%.*]] = load float, ptr [[ARRAYIDX2]], align 4, !llvm.access.group [[ACC_GRP5]]
1898 // CHECK2-NEXT:    [[MUL3:%.*]] = fmul float [[TMP13]], [[TMP16]]
1899 // CHECK2-NEXT:    [[TMP17:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP5]]
1900 // CHECK2-NEXT:    [[TMP18:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP5]]
1901 // CHECK2-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds float, ptr [[TMP17]], i64 [[TMP18]]
1902 // CHECK2-NEXT:    [[TMP19:%.*]] = load float, ptr [[ARRAYIDX4]], align 4, !llvm.access.group [[ACC_GRP5]]
1903 // CHECK2-NEXT:    [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP19]]
1904 // CHECK2-NEXT:    [[TMP20:%.*]] = load ptr, ptr [[TMP0]], align 8, !llvm.access.group [[ACC_GRP5]]
1905 // CHECK2-NEXT:    [[TMP21:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP5]]
1906 // CHECK2-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP20]], i64 [[TMP21]]
1907 // CHECK2-NEXT:    store float [[MUL5]], ptr [[ARRAYIDX6]], align 4, !llvm.access.group [[ACC_GRP5]]
1908 // CHECK2-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1909 // CHECK2:       omp.body.continue:
1910 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1911 // CHECK2:       omp.inner.for.inc:
1912 // CHECK2-NEXT:    [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP5]]
1913 // CHECK2-NEXT:    [[ADD7:%.*]] = add i64 [[TMP22]], 1
1914 // CHECK2-NEXT:    store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP5]]
1915 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
1916 // CHECK2:       omp.inner.for.end:
1917 // CHECK2-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
1918 // CHECK2:       omp.dispatch.inc:
1919 // CHECK2-NEXT:    br label [[OMP_DISPATCH_COND]]
1920 // CHECK2:       omp.dispatch.end:
1921 // CHECK2-NEXT:    ret void
1922 //
1923 //
1924 // CHECK2-LABEL: define {{[^@]+}}@_Z7guided7PfS_S_S_
1925 // CHECK2-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
1926 // CHECK2-NEXT:  entry:
1927 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
1928 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
1929 // CHECK2-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
1930 // CHECK2-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
1931 // CHECK2-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
1932 // CHECK2-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
1933 // CHECK2-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
1934 // CHECK2-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
1935 // CHECK2-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @_Z7guided7PfS_S_S_.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])
1936 // CHECK2-NEXT:    ret void
1937 //
1938 //
1939 // CHECK2-LABEL: define {{[^@]+}}@_Z7guided7PfS_S_S_.omp_outlined
1940 // CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] {
1941 // CHECK2-NEXT:  entry:
1942 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1943 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1944 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
1945 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
1946 // CHECK2-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
1947 // CHECK2-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
1948 // CHECK2-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
1949 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i64, align 8
1950 // CHECK2-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
1951 // CHECK2-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
1952 // CHECK2-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
1953 // CHECK2-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1954 // CHECK2-NEXT:    [[I:%.*]] = alloca i64, align 8
1955 // CHECK2-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1956 // CHECK2-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1957 // CHECK2-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
1958 // CHECK2-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
1959 // CHECK2-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
1960 // CHECK2-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
1961 // CHECK2-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
1962 // CHECK2-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
1963 // CHECK2-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8
1964 // CHECK2-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8
1965 // CHECK2-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8
1966 // CHECK2-NEXT:    store i64 16908287, ptr [[DOTOMP_UB]], align 8
1967 // CHECK2-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8
1968 // CHECK2-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1969 // CHECK2-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1970 // CHECK2-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
1971 // CHECK2-NEXT:    call void @__kmpc_dispatch_init_8u(ptr @[[GLOB2]], i32 [[TMP5]], i32 36, i64 0, i64 16908287, i64 1, i64 7)
1972 // CHECK2-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
1973 // CHECK2:       omp.dispatch.cond:
1974 // CHECK2-NEXT:    [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_8u(ptr @[[GLOB2]], i32 [[TMP5]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
1975 // CHECK2-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0
1976 // CHECK2-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
1977 // CHECK2:       omp.dispatch.body:
1978 // CHECK2-NEXT:    [[TMP7:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
1979 // CHECK2-NEXT:    store i64 [[TMP7]], ptr [[DOTOMP_IV]], align 8
1980 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1981 // CHECK2:       omp.inner.for.cond:
1982 // CHECK2-NEXT:    [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP8:![0-9]+]]
1983 // CHECK2-NEXT:    [[TMP9:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP8]]
1984 // CHECK2-NEXT:    [[ADD:%.*]] = add i64 [[TMP9]], 1
1985 // CHECK2-NEXT:    [[CMP:%.*]] = icmp ult i64 [[TMP8]], [[ADD]]
1986 // CHECK2-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1987 // CHECK2:       omp.inner.for.body:
1988 // CHECK2-NEXT:    [[TMP10:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP8]]
1989 // CHECK2-NEXT:    [[MUL:%.*]] = mul i64 [[TMP10]], 127
1990 // CHECK2-NEXT:    [[ADD1:%.*]] = add i64 131071, [[MUL]]
1991 // CHECK2-NEXT:    store i64 [[ADD1]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP8]]
1992 // CHECK2-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP8]]
1993 // CHECK2-NEXT:    [[TMP12:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP8]]
1994 // CHECK2-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP11]], i64 [[TMP12]]
1995 // CHECK2-NEXT:    [[TMP13:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP8]]
1996 // CHECK2-NEXT:    [[TMP14:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP8]]
1997 // CHECK2-NEXT:    [[TMP15:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP8]]
1998 // CHECK2-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[TMP14]], i64 [[TMP15]]
1999 // CHECK2-NEXT:    [[TMP16:%.*]] = load float, ptr [[ARRAYIDX2]], align 4, !llvm.access.group [[ACC_GRP8]]
2000 // CHECK2-NEXT:    [[MUL3:%.*]] = fmul float [[TMP13]], [[TMP16]]
2001 // CHECK2-NEXT:    [[TMP17:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP8]]
2002 // CHECK2-NEXT:    [[TMP18:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP8]]
2003 // CHECK2-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds float, ptr [[TMP17]], i64 [[TMP18]]
2004 // CHECK2-NEXT:    [[TMP19:%.*]] = load float, ptr [[ARRAYIDX4]], align 4, !llvm.access.group [[ACC_GRP8]]
2005 // CHECK2-NEXT:    [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP19]]
2006 // CHECK2-NEXT:    [[TMP20:%.*]] = load ptr, ptr [[TMP0]], align 8, !llvm.access.group [[ACC_GRP8]]
2007 // CHECK2-NEXT:    [[TMP21:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP8]]
2008 // CHECK2-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP20]], i64 [[TMP21]]
2009 // CHECK2-NEXT:    store float [[MUL5]], ptr [[ARRAYIDX6]], align 4, !llvm.access.group [[ACC_GRP8]]
2010 // CHECK2-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2011 // CHECK2:       omp.body.continue:
2012 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2013 // CHECK2:       omp.inner.for.inc:
2014 // CHECK2-NEXT:    [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP8]]
2015 // CHECK2-NEXT:    [[ADD7:%.*]] = add i64 [[TMP22]], 1
2016 // CHECK2-NEXT:    store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP8]]
2017 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
2018 // CHECK2:       omp.inner.for.end:
2019 // CHECK2-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
2020 // CHECK2:       omp.dispatch.inc:
2021 // CHECK2-NEXT:    br label [[OMP_DISPATCH_COND]]
2022 // CHECK2:       omp.dispatch.end:
2023 // CHECK2-NEXT:    ret void
2024 //
2025 //
2026 // CHECK2-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_
2027 // CHECK2-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
2028 // CHECK2-NEXT:  entry:
2029 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
2030 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
2031 // CHECK2-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
2032 // CHECK2-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
2033 // CHECK2-NEXT:    [[X:%.*]] = alloca i32, align 4
2034 // CHECK2-NEXT:    [[Y:%.*]] = alloca i32, align 4
2035 // CHECK2-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
2036 // CHECK2-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
2037 // CHECK2-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
2038 // CHECK2-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
2039 // CHECK2-NEXT:    store i32 0, ptr [[X]], align 4
2040 // CHECK2-NEXT:    store i32 0, ptr [[Y]], align 4
2041 // CHECK2-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 5, ptr @_Z9test_autoPfS_S_S_.omp_outlined, ptr [[Y]], ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])
2042 // CHECK2-NEXT:    ret void
2043 //
2044 //
2045 // CHECK2-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_.omp_outlined
2046 // CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[Y:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] {
2047 // CHECK2-NEXT:  entry:
2048 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
2049 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
2050 // CHECK2-NEXT:    [[Y_ADDR:%.*]] = alloca ptr, align 8
2051 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
2052 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
2053 // CHECK2-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
2054 // CHECK2-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
2055 // CHECK2-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
2056 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i8, align 1
2057 // CHECK2-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
2058 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
2059 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 8
2060 // CHECK2-NEXT:    [[I:%.*]] = alloca i8, align 1
2061 // CHECK2-NEXT:    [[X:%.*]] = alloca i32, align 4
2062 // CHECK2-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
2063 // CHECK2-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
2064 // CHECK2-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
2065 // CHECK2-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2066 // CHECK2-NEXT:    [[I7:%.*]] = alloca i8, align 1
2067 // CHECK2-NEXT:    [[X8:%.*]] = alloca i32, align 4
2068 // CHECK2-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
2069 // CHECK2-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
2070 // CHECK2-NEXT:    store ptr [[Y]], ptr [[Y_ADDR]], align 8
2071 // CHECK2-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
2072 // CHECK2-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
2073 // CHECK2-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
2074 // CHECK2-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
2075 // CHECK2-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[Y_ADDR]], align 8
2076 // CHECK2-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8
2077 // CHECK2-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8
2078 // CHECK2-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
2079 // CHECK2-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[D_ADDR]], align 8
2080 // CHECK2-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 4
2081 // CHECK2-NEXT:    [[CONV:%.*]] = trunc i32 [[TMP5]] to i8
2082 // CHECK2-NEXT:    store i8 [[CONV]], ptr [[DOTCAPTURE_EXPR_]], align 1
2083 // CHECK2-NEXT:    [[TMP6:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
2084 // CHECK2-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP6]] to i32
2085 // CHECK2-NEXT:    [[SUB:%.*]] = sub i32 57, [[CONV3]]
2086 // CHECK2-NEXT:    [[ADD:%.*]] = add i32 [[SUB]], 1
2087 // CHECK2-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
2088 // CHECK2-NEXT:    [[CONV4:%.*]] = zext i32 [[DIV]] to i64
2089 // CHECK2-NEXT:    [[MUL:%.*]] = mul nsw i64 [[CONV4]], 11
2090 // CHECK2-NEXT:    [[SUB5:%.*]] = sub nsw i64 [[MUL]], 1
2091 // CHECK2-NEXT:    store i64 [[SUB5]], ptr [[DOTCAPTURE_EXPR_2]], align 8
2092 // CHECK2-NEXT:    [[TMP7:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
2093 // CHECK2-NEXT:    store i8 [[TMP7]], ptr [[I]], align 1
2094 // CHECK2-NEXT:    store i32 11, ptr [[X]], align 4
2095 // CHECK2-NEXT:    [[TMP8:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
2096 // CHECK2-NEXT:    [[CONV6:%.*]] = sext i8 [[TMP8]] to i32
2097 // CHECK2-NEXT:    [[CMP:%.*]] = icmp sle i32 [[CONV6]], 57
2098 // CHECK2-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
2099 // CHECK2:       omp.precond.then:
2100 // CHECK2-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8
2101 // CHECK2-NEXT:    [[TMP9:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_2]], align 8
2102 // CHECK2-NEXT:    store i64 [[TMP9]], ptr [[DOTOMP_UB]], align 8
2103 // CHECK2-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8
2104 // CHECK2-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2105 // CHECK2-NEXT:    [[TMP10:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_2]], align 8
2106 // CHECK2-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
2107 // CHECK2-NEXT:    [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4
2108 // CHECK2-NEXT:    call void @__kmpc_dispatch_init_8(ptr @[[GLOB2]], i32 [[TMP12]], i32 38, i64 0, i64 [[TMP10]], i64 1, i64 1)
2109 // CHECK2-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
2110 // CHECK2:       omp.dispatch.cond:
2111 // CHECK2-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
2112 // CHECK2-NEXT:    [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4
2113 // CHECK2-NEXT:    [[TMP15:%.*]] = call i32 @__kmpc_dispatch_next_8(ptr @[[GLOB2]], i32 [[TMP14]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
2114 // CHECK2-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0
2115 // CHECK2-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
2116 // CHECK2:       omp.dispatch.body:
2117 // CHECK2-NEXT:    [[TMP16:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
2118 // CHECK2-NEXT:    store i64 [[TMP16]], ptr [[DOTOMP_IV]], align 8
2119 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2120 // CHECK2:       omp.inner.for.cond:
2121 // CHECK2-NEXT:    [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP11:![0-9]+]]
2122 // CHECK2-NEXT:    [[TMP18:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP11]]
2123 // CHECK2-NEXT:    [[CMP9:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]]
2124 // CHECK2-NEXT:    br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2125 // CHECK2:       omp.inner.for.body:
2126 // CHECK2-NEXT:    [[TMP19:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group [[ACC_GRP11]]
2127 // CHECK2-NEXT:    [[CONV10:%.*]] = sext i8 [[TMP19]] to i64
2128 // CHECK2-NEXT:    [[TMP20:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP11]]
2129 // CHECK2-NEXT:    [[DIV11:%.*]] = sdiv i64 [[TMP20]], 11
2130 // CHECK2-NEXT:    [[MUL12:%.*]] = mul nsw i64 [[DIV11]], 1
2131 // CHECK2-NEXT:    [[ADD13:%.*]] = add nsw i64 [[CONV10]], [[MUL12]]
2132 // CHECK2-NEXT:    [[CONV14:%.*]] = trunc i64 [[ADD13]] to i8
2133 // CHECK2-NEXT:    store i8 [[CONV14]], ptr [[I7]], align 1, !llvm.access.group [[ACC_GRP11]]
2134 // CHECK2-NEXT:    [[TMP21:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP11]]
2135 // CHECK2-NEXT:    [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP11]]
2136 // CHECK2-NEXT:    [[DIV15:%.*]] = sdiv i64 [[TMP22]], 11
2137 // CHECK2-NEXT:    [[MUL16:%.*]] = mul nsw i64 [[DIV15]], 11
2138 // CHECK2-NEXT:    [[SUB17:%.*]] = sub nsw i64 [[TMP21]], [[MUL16]]
2139 // CHECK2-NEXT:    [[MUL18:%.*]] = mul nsw i64 [[SUB17]], 1
2140 // CHECK2-NEXT:    [[SUB19:%.*]] = sub nsw i64 11, [[MUL18]]
2141 // CHECK2-NEXT:    [[CONV20:%.*]] = trunc i64 [[SUB19]] to i32
2142 // CHECK2-NEXT:    store i32 [[CONV20]], ptr [[X8]], align 4, !llvm.access.group [[ACC_GRP11]]
2143 // CHECK2-NEXT:    [[TMP23:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP11]]
2144 // CHECK2-NEXT:    [[TMP24:%.*]] = load i8, ptr [[I7]], align 1, !llvm.access.group [[ACC_GRP11]]
2145 // CHECK2-NEXT:    [[IDXPROM:%.*]] = sext i8 [[TMP24]] to i64
2146 // CHECK2-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP23]], i64 [[IDXPROM]]
2147 // CHECK2-NEXT:    [[TMP25:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP11]]
2148 // CHECK2-NEXT:    [[TMP26:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP11]]
2149 // CHECK2-NEXT:    [[TMP27:%.*]] = load i8, ptr [[I7]], align 1, !llvm.access.group [[ACC_GRP11]]
2150 // CHECK2-NEXT:    [[IDXPROM21:%.*]] = sext i8 [[TMP27]] to i64
2151 // CHECK2-NEXT:    [[ARRAYIDX22:%.*]] = getelementptr inbounds float, ptr [[TMP26]], i64 [[IDXPROM21]]
2152 // CHECK2-NEXT:    [[TMP28:%.*]] = load float, ptr [[ARRAYIDX22]], align 4, !llvm.access.group [[ACC_GRP11]]
2153 // CHECK2-NEXT:    [[MUL23:%.*]] = fmul float [[TMP25]], [[TMP28]]
2154 // CHECK2-NEXT:    [[TMP29:%.*]] = load ptr, ptr [[TMP4]], align 8, !llvm.access.group [[ACC_GRP11]]
2155 // CHECK2-NEXT:    [[TMP30:%.*]] = load i8, ptr [[I7]], align 1, !llvm.access.group [[ACC_GRP11]]
2156 // CHECK2-NEXT:    [[IDXPROM24:%.*]] = sext i8 [[TMP30]] to i64
2157 // CHECK2-NEXT:    [[ARRAYIDX25:%.*]] = getelementptr inbounds float, ptr [[TMP29]], i64 [[IDXPROM24]]
2158 // CHECK2-NEXT:    [[TMP31:%.*]] = load float, ptr [[ARRAYIDX25]], align 4, !llvm.access.group [[ACC_GRP11]]
2159 // CHECK2-NEXT:    [[MUL26:%.*]] = fmul float [[MUL23]], [[TMP31]]
2160 // CHECK2-NEXT:    [[TMP32:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP11]]
2161 // CHECK2-NEXT:    [[TMP33:%.*]] = load i8, ptr [[I7]], align 1, !llvm.access.group [[ACC_GRP11]]
2162 // CHECK2-NEXT:    [[IDXPROM27:%.*]] = sext i8 [[TMP33]] to i64
2163 // CHECK2-NEXT:    [[ARRAYIDX28:%.*]] = getelementptr inbounds float, ptr [[TMP32]], i64 [[IDXPROM27]]
2164 // CHECK2-NEXT:    store float [[MUL26]], ptr [[ARRAYIDX28]], align 4, !llvm.access.group [[ACC_GRP11]]
2165 // CHECK2-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2166 // CHECK2:       omp.body.continue:
2167 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2168 // CHECK2:       omp.inner.for.inc:
2169 // CHECK2-NEXT:    [[TMP34:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP11]]
2170 // CHECK2-NEXT:    [[ADD29:%.*]] = add nsw i64 [[TMP34]], 1
2171 // CHECK2-NEXT:    store i64 [[ADD29]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP11]]
2172 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
2173 // CHECK2:       omp.inner.for.end:
2174 // CHECK2-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
2175 // CHECK2:       omp.dispatch.inc:
2176 // CHECK2-NEXT:    br label [[OMP_DISPATCH_COND]]
2177 // CHECK2:       omp.dispatch.end:
2178 // CHECK2-NEXT:    br label [[OMP_PRECOND_END]]
2179 // CHECK2:       omp.precond.end:
2180 // CHECK2-NEXT:    ret void
2181 //
2182 //
2183 // CHECK2-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_
2184 // CHECK2-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
2185 // CHECK2-NEXT:  entry:
2186 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
2187 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
2188 // CHECK2-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
2189 // CHECK2-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
2190 // CHECK2-NEXT:    [[X:%.*]] = alloca i32, align 4
2191 // CHECK2-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
2192 // CHECK2-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
2193 // CHECK2-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
2194 // CHECK2-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
2195 // CHECK2-NEXT:    store i32 0, ptr [[X]], align 4
2196 // CHECK2-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @_Z7runtimePfS_S_S_.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])
2197 // CHECK2-NEXT:    ret void
2198 //
2199 //
2200 // CHECK2-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_.omp_outlined
2201 // CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] {
2202 // CHECK2-NEXT:  entry:
2203 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
2204 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
2205 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
2206 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
2207 // CHECK2-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
2208 // CHECK2-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
2209 // CHECK2-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2210 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i8, align 1
2211 // CHECK2-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
2212 // CHECK2-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2213 // CHECK2-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2214 // CHECK2-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2215 // CHECK2-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2216 // CHECK2-NEXT:    [[I:%.*]] = alloca i8, align 1
2217 // CHECK2-NEXT:    [[X:%.*]] = alloca i32, align 4
2218 // CHECK2-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
2219 // CHECK2-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
2220 // CHECK2-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
2221 // CHECK2-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
2222 // CHECK2-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
2223 // CHECK2-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
2224 // CHECK2-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
2225 // CHECK2-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
2226 // CHECK2-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8
2227 // CHECK2-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8
2228 // CHECK2-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
2229 // CHECK2-NEXT:    store i32 199, ptr [[DOTOMP_UB]], align 4
2230 // CHECK2-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
2231 // CHECK2-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2232 // CHECK2-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
2233 // CHECK2-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
2234 // CHECK2-NEXT:    call void @__kmpc_dispatch_init_4(ptr @[[GLOB2]], i32 [[TMP5]], i32 37, i32 0, i32 199, i32 1, i32 1)
2235 // CHECK2-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
2236 // CHECK2:       omp.dispatch.cond:
2237 // CHECK2-NEXT:    [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB2]], i32 [[TMP5]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
2238 // CHECK2-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0
2239 // CHECK2-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
2240 // CHECK2:       omp.dispatch.body:
2241 // CHECK2-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
2242 // CHECK2-NEXT:    store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
2243 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2244 // CHECK2:       omp.inner.for.cond:
2245 // CHECK2-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14:![0-9]+]]
2246 // CHECK2-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP14]]
2247 // CHECK2-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
2248 // CHECK2-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2249 // CHECK2:       omp.inner.for.body:
2250 // CHECK2-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]
2251 // CHECK2-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP10]], 20
2252 // CHECK2-NEXT:    [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
2253 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 48, [[MUL]]
2254 // CHECK2-NEXT:    [[CONV:%.*]] = trunc i32 [[ADD]] to i8
2255 // CHECK2-NEXT:    store i8 [[CONV]], ptr [[I]], align 1, !llvm.access.group [[ACC_GRP14]]
2256 // CHECK2-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]
2257 // CHECK2-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]
2258 // CHECK2-NEXT:    [[DIV2:%.*]] = sdiv i32 [[TMP12]], 20
2259 // CHECK2-NEXT:    [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 20
2260 // CHECK2-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL3]]
2261 // CHECK2-NEXT:    [[MUL4:%.*]] = mul nsw i32 [[SUB]], 1
2262 // CHECK2-NEXT:    [[ADD5:%.*]] = add nsw i32 -10, [[MUL4]]
2263 // CHECK2-NEXT:    store i32 [[ADD5]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP14]]
2264 // CHECK2-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP14]]
2265 // CHECK2-NEXT:    [[TMP14:%.*]] = load i8, ptr [[I]], align 1, !llvm.access.group [[ACC_GRP14]]
2266 // CHECK2-NEXT:    [[IDXPROM:%.*]] = zext i8 [[TMP14]] to i64
2267 // CHECK2-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP13]], i64 [[IDXPROM]]
2268 // CHECK2-NEXT:    [[TMP15:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP14]]
2269 // CHECK2-NEXT:    [[TMP16:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP14]]
2270 // CHECK2-NEXT:    [[TMP17:%.*]] = load i8, ptr [[I]], align 1, !llvm.access.group [[ACC_GRP14]]
2271 // CHECK2-NEXT:    [[IDXPROM6:%.*]] = zext i8 [[TMP17]] to i64
2272 // CHECK2-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds float, ptr [[TMP16]], i64 [[IDXPROM6]]
2273 // CHECK2-NEXT:    [[TMP18:%.*]] = load float, ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP14]]
2274 // CHECK2-NEXT:    [[MUL8:%.*]] = fmul float [[TMP15]], [[TMP18]]
2275 // CHECK2-NEXT:    [[TMP19:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP14]]
2276 // CHECK2-NEXT:    [[TMP20:%.*]] = load i8, ptr [[I]], align 1, !llvm.access.group [[ACC_GRP14]]
2277 // CHECK2-NEXT:    [[IDXPROM9:%.*]] = zext i8 [[TMP20]] to i64
2278 // CHECK2-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP19]], i64 [[IDXPROM9]]
2279 // CHECK2-NEXT:    [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP14]]
2280 // CHECK2-NEXT:    [[MUL11:%.*]] = fmul float [[MUL8]], [[TMP21]]
2281 // CHECK2-NEXT:    [[TMP22:%.*]] = load ptr, ptr [[TMP0]], align 8, !llvm.access.group [[ACC_GRP14]]
2282 // CHECK2-NEXT:    [[TMP23:%.*]] = load i8, ptr [[I]], align 1, !llvm.access.group [[ACC_GRP14]]
2283 // CHECK2-NEXT:    [[IDXPROM12:%.*]] = zext i8 [[TMP23]] to i64
2284 // CHECK2-NEXT:    [[ARRAYIDX13:%.*]] = getelementptr inbounds float, ptr [[TMP22]], i64 [[IDXPROM12]]
2285 // CHECK2-NEXT:    store float [[MUL11]], ptr [[ARRAYIDX13]], align 4, !llvm.access.group [[ACC_GRP14]]
2286 // CHECK2-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2287 // CHECK2:       omp.body.continue:
2288 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2289 // CHECK2:       omp.inner.for.inc:
2290 // CHECK2-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]
2291 // CHECK2-NEXT:    [[ADD14:%.*]] = add nsw i32 [[TMP24]], 1
2292 // CHECK2-NEXT:    store i32 [[ADD14]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]
2293 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
2294 // CHECK2:       omp.inner.for.end:
2295 // CHECK2-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
2296 // CHECK2:       omp.dispatch.inc:
2297 // CHECK2-NEXT:    br label [[OMP_DISPATCH_COND]]
2298 // CHECK2:       omp.dispatch.end:
2299 // CHECK2-NEXT:    ret void
2300 //
2301 //
2302 // CHECK2-LABEL: define {{[^@]+}}@_Z3foov
2303 // CHECK2-SAME: () #[[ATTR3:[0-9]+]] {
2304 // CHECK2-NEXT:  entry:
2305 // CHECK2-NEXT:    call void @_Z8mayThrowv()
2306 // CHECK2-NEXT:    ret i32 0
2307 //
2308 //
2309 // CHECK2-LABEL: define {{[^@]+}}@_Z12parallel_forPfi
2310 // CHECK2-SAME: (ptr noundef [[A:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] {
2311 // CHECK2-NEXT:  entry:
2312 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
2313 // CHECK2-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
2314 // CHECK2-NEXT:    [[SAVED_STACK:%.*]] = alloca ptr, align 8
2315 // CHECK2-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
2316 // CHECK2-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8
2317 // CHECK2-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
2318 // CHECK2-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
2319 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
2320 // CHECK2-NEXT:    [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
2321 // CHECK2-NEXT:    [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
2322 // CHECK2-NEXT:    store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
2323 // CHECK2-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 16
2324 // CHECK2-NEXT:    store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
2325 // CHECK2-NEXT:    [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4
2326 // CHECK2-NEXT:    store i32 [[TMP3]], ptr [[N_CASTED]], align 4
2327 // CHECK2-NEXT:    [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8
2328 // CHECK2-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @_Z12parallel_forPfi.omp_outlined, ptr [[A_ADDR]], i64 [[TMP1]], i64 [[TMP4]])
2329 // CHECK2-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
2330 // CHECK2-NEXT:    call void @llvm.stackrestore.p0(ptr [[TMP5]])
2331 // CHECK2-NEXT:    ret void
2332 //
2333 //
2334 // CHECK2-LABEL: define {{[^@]+}}@_Z12parallel_forPfi.omp_outlined
2335 // CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[N:%.*]]) #[[ATTR1]] personality ptr @__gxx_personality_v0 {
2336 // CHECK2-NEXT:  entry:
2337 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
2338 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
2339 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
2340 // CHECK2-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
2341 // CHECK2-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
2342 // CHECK2-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2343 // CHECK2-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2344 // CHECK2-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2345 // CHECK2-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2346 // CHECK2-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2347 // CHECK2-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2348 // CHECK2-NEXT:    [[SAVED_STACK:%.*]] = alloca ptr, align 8
2349 // CHECK2-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
2350 // CHECK2-NEXT:    [[I:%.*]] = alloca i32, align 4
2351 // CHECK2-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
2352 // CHECK2-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
2353 // CHECK2-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
2354 // CHECK2-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
2355 // CHECK2-NEXT:    store i64 [[N]], ptr [[N_ADDR]], align 8
2356 // CHECK2-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
2357 // CHECK2-NEXT:    [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
2358 // CHECK2-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
2359 // CHECK2-NEXT:    store i32 16908288, ptr [[DOTOMP_UB]], align 4
2360 // CHECK2-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
2361 // CHECK2-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2362 // CHECK2-NEXT:    [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
2363 // CHECK2-NEXT:    store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
2364 // CHECK2-NEXT:    [[VLA1:%.*]] = alloca float, i64 [[TMP1]], align 16
2365 // CHECK2-NEXT:    store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
2366 // CHECK2-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
2367 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
2368 // CHECK2-NEXT:    call void @__kmpc_for_static_init_4u(ptr @[[GLOB1]], i32 [[TMP4]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 5)
2369 // CHECK2-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
2370 // CHECK2:       omp.dispatch.cond:
2371 // CHECK2-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2372 // CHECK2-NEXT:    [[CMP:%.*]] = icmp ugt i32 [[TMP5]], 16908288
2373 // CHECK2-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2374 // CHECK2:       cond.true:
2375 // CHECK2-NEXT:    br label [[COND_END:%.*]]
2376 // CHECK2:       cond.false:
2377 // CHECK2-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2378 // CHECK2-NEXT:    br label [[COND_END]]
2379 // CHECK2:       cond.end:
2380 // CHECK2-NEXT:    [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]
2381 // CHECK2-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
2382 // CHECK2-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
2383 // CHECK2-NEXT:    store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
2384 // CHECK2-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2385 // CHECK2-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2386 // CHECK2-NEXT:    [[CMP2:%.*]] = icmp ule i32 [[TMP8]], [[TMP9]]
2387 // CHECK2-NEXT:    br i1 [[CMP2]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_CLEANUP:%.*]]
2388 // CHECK2:       omp.dispatch.cleanup:
2389 // CHECK2-NEXT:    br label [[OMP_DISPATCH_END:%.*]]
2390 // CHECK2:       omp.dispatch.body:
2391 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2392 // CHECK2:       omp.inner.for.cond:
2393 // CHECK2-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2394 // CHECK2-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2395 // CHECK2-NEXT:    [[CMP3:%.*]] = icmp ule i32 [[TMP10]], [[TMP11]]
2396 // CHECK2-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2397 // CHECK2:       omp.inner.for.cond.cleanup:
2398 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
2399 // CHECK2:       omp.inner.for.body:
2400 // CHECK2-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2401 // CHECK2-NEXT:    [[MUL:%.*]] = mul i32 [[TMP12]], 127
2402 // CHECK2-NEXT:    [[ADD:%.*]] = add i32 131071, [[MUL]]
2403 // CHECK2-NEXT:    store i32 [[ADD]], ptr [[I]], align 4
2404 // CHECK2-NEXT:    [[CALL:%.*]] = invoke noundef i32 @_Z3foov()
2405 // CHECK2-NEXT:    to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]]
2406 // CHECK2:       invoke.cont:
2407 // CHECK2-NEXT:    [[CONV:%.*]] = sitofp i32 [[CALL]] to float
2408 // CHECK2-NEXT:    [[TMP13:%.*]] = load i32, ptr [[I]], align 4
2409 // CHECK2-NEXT:    [[IDXPROM:%.*]] = zext i32 [[TMP13]] to i64
2410 // CHECK2-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[VLA1]], i64 [[IDXPROM]]
2411 // CHECK2-NEXT:    [[TMP14:%.*]] = load float, ptr [[ARRAYIDX]], align 4
2412 // CHECK2-NEXT:    [[ADD4:%.*]] = fadd float [[CONV]], [[TMP14]]
2413 // CHECK2-NEXT:    [[TMP15:%.*]] = load i32, ptr [[N_ADDR]], align 4
2414 // CHECK2-NEXT:    [[CONV5:%.*]] = sitofp i32 [[TMP15]] to float
2415 // CHECK2-NEXT:    [[ADD6:%.*]] = fadd float [[ADD4]], [[CONV5]]
2416 // CHECK2-NEXT:    [[TMP16:%.*]] = load ptr, ptr [[TMP0]], align 8
2417 // CHECK2-NEXT:    [[TMP17:%.*]] = load i32, ptr [[I]], align 4
2418 // CHECK2-NEXT:    [[IDXPROM7:%.*]] = zext i32 [[TMP17]] to i64
2419 // CHECK2-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds float, ptr [[TMP16]], i64 [[IDXPROM7]]
2420 // CHECK2-NEXT:    [[TMP18:%.*]] = load float, ptr [[ARRAYIDX8]], align 4
2421 // CHECK2-NEXT:    [[ADD9:%.*]] = fadd float [[TMP18]], [[ADD6]]
2422 // CHECK2-NEXT:    store float [[ADD9]], ptr [[ARRAYIDX8]], align 4
2423 // CHECK2-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2424 // CHECK2:       omp.body.continue:
2425 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2426 // CHECK2:       omp.inner.for.inc:
2427 // CHECK2-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2428 // CHECK2-NEXT:    [[ADD10:%.*]] = add i32 [[TMP19]], 1
2429 // CHECK2-NEXT:    store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4
2430 // CHECK2-NEXT:    br label [[OMP_INNER_FOR_COND]]
2431 // CHECK2:       omp.inner.for.end:
2432 // CHECK2-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
2433 // CHECK2:       omp.dispatch.inc:
2434 // CHECK2-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
2435 // CHECK2-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
2436 // CHECK2-NEXT:    [[ADD11:%.*]] = add i32 [[TMP20]], [[TMP21]]
2437 // CHECK2-NEXT:    store i32 [[ADD11]], ptr [[DOTOMP_LB]], align 4
2438 // CHECK2-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2439 // CHECK2-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
2440 // CHECK2-NEXT:    [[ADD12:%.*]] = add i32 [[TMP22]], [[TMP23]]
2441 // CHECK2-NEXT:    store i32 [[ADD12]], ptr [[DOTOMP_UB]], align 4
2442 // CHECK2-NEXT:    br label [[OMP_DISPATCH_COND]]
2443 // CHECK2:       omp.dispatch.end:
2444 // CHECK2-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP4]])
2445 // CHECK2-NEXT:    [[TMP24:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
2446 // CHECK2-NEXT:    call void @llvm.stackrestore.p0(ptr [[TMP24]])
2447 // CHECK2-NEXT:    ret void
2448 // CHECK2:       terminate.lpad:
2449 // CHECK2-NEXT:    [[TMP25:%.*]] = landingpad { ptr, i32 }
2450 // CHECK2-NEXT:    catch ptr null
2451 // CHECK2-NEXT:    [[TMP26:%.*]] = extractvalue { ptr, i32 } [[TMP25]], 0
2452 // CHECK2-NEXT:    call void @__clang_call_terminate(ptr [[TMP26]]) #[[ATTR7:[0-9]+]]
2453 // CHECK2-NEXT:    unreachable
2454 //
2455 //
2456 // CHECK2-LABEL: define {{[^@]+}}@__clang_call_terminate
2457 // CHECK2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR6:[0-9]+]] comdat {
2458 // CHECK2-NEXT:    [[TMP2:%.*]] = call ptr @__cxa_begin_catch(ptr [[TMP0]]) #[[ATTR2:[0-9]+]]
2459 // CHECK2-NEXT:    call void @_ZSt9terminatev() #[[ATTR7]]
2460 // CHECK2-NEXT:    unreachable
2461 //
2462 //
2463 // CHECK5-LABEL: define {{[^@]+}}@_Z17with_var_schedulev
2464 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] !dbg [[DBG6:![0-9]+]] {
2465 // CHECK5-NEXT:  entry:
2466 // CHECK5-NEXT:    [[A:%.*]] = alloca double, align 8
2467 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
2468 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
2469 // CHECK5-NEXT:    store double 5.000000e+00, ptr [[A]], align 8, !dbg [[DBG10:![0-9]+]]
2470 // CHECK5-NEXT:    [[TMP0:%.*]] = load double, ptr [[A]], align 8, !dbg [[DBG11:![0-9]+]]
2471 // CHECK5-NEXT:    [[CONV:%.*]] = fptosi double [[TMP0]] to i8, !dbg [[DBG11]]
2472 // CHECK5-NEXT:    store i8 [[CONV]], ptr [[DOTCAPTURE_EXPR_]], align 1, !dbg [[DBG11]]
2473 // CHECK5-NEXT:    [[TMP1:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1, !dbg [[DBG11]]
2474 // CHECK5-NEXT:    store i8 [[TMP1]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1, !dbg [[DBG11]]
2475 // CHECK5-NEXT:    [[TMP2:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8, !dbg [[DBG11]]
2476 // CHECK5-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB4:[0-9]+]], i32 1, ptr @_Z17with_var_schedulev.omp_outlined, i64 [[TMP2]]), !dbg [[DBG11]]
2477 // CHECK5-NEXT:    ret void, !dbg [[DBG12:![0-9]+]]
2478 //
2479 //
2480 // CHECK5-LABEL: define {{[^@]+}}@_Z17with_var_schedulev.omp_outlined
2481 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] !dbg [[DBG13:![0-9]+]] {
2482 // CHECK5-NEXT:  entry:
2483 // CHECK5-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
2484 // CHECK5-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
2485 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
2486 // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
2487 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i64, align 8
2488 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca double, align 8
2489 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 8
2490 // CHECK5-NEXT:    [[I:%.*]] = alloca i64, align 8
2491 // CHECK5-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
2492 // CHECK5-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
2493 // CHECK5-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
2494 // CHECK5-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2495 // CHECK5-NEXT:    [[A:%.*]] = alloca double, align 8
2496 // CHECK5-NEXT:    [[I4:%.*]] = alloca i64, align 8
2497 // CHECK5-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
2498 // CHECK5-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
2499 // CHECK5-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
2500 // CHECK5-NEXT:    [[TMP0:%.*]] = load double, ptr undef, align 8, !dbg [[DBG14:![0-9]+]]
2501 // CHECK5-NEXT:    [[ADD:%.*]] = fadd double 2.000000e+00, [[TMP0]], !dbg [[DBG14]]
2502 // CHECK5-NEXT:    store double [[ADD]], ptr [[DOTCAPTURE_EXPR_1]], align 8, !dbg [[DBG14]]
2503 // CHECK5-NEXT:    [[TMP1:%.*]] = load double, ptr [[DOTCAPTURE_EXPR_1]], align 8, !dbg [[DBG14]]
2504 // CHECK5-NEXT:    [[SUB:%.*]] = fsub double [[TMP1]], 1.000000e+00, !dbg [[DBG14]]
2505 // CHECK5-NEXT:    [[DIV:%.*]] = fdiv double [[SUB]], 1.000000e+00, !dbg [[DBG14]]
2506 // CHECK5-NEXT:    [[CONV:%.*]] = fptoui double [[DIV]] to i64, !dbg [[DBG14]]
2507 // CHECK5-NEXT:    [[SUB3:%.*]] = sub i64 [[CONV]], 1, !dbg [[DBG14]]
2508 // CHECK5-NEXT:    store i64 [[SUB3]], ptr [[DOTCAPTURE_EXPR_2]], align 8, !dbg [[DBG14]]
2509 // CHECK5-NEXT:    store i64 1, ptr [[I]], align 8, !dbg [[DBG14]]
2510 // CHECK5-NEXT:    [[TMP2:%.*]] = load double, ptr [[DOTCAPTURE_EXPR_1]], align 8, !dbg [[DBG14]]
2511 // CHECK5-NEXT:    [[CMP:%.*]] = fcmp olt double 1.000000e+00, [[TMP2]], !dbg [[DBG14]]
2512 // CHECK5-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]], !dbg [[DBG15:![0-9]+]]
2513 // CHECK5:       omp.precond.then:
2514 // CHECK5-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8, !dbg [[DBG14]]
2515 // CHECK5-NEXT:    [[TMP3:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_2]], align 8, !dbg [[DBG14]]
2516 // CHECK5-NEXT:    store i64 [[TMP3]], ptr [[DOTOMP_UB]], align 8, !dbg [[DBG14]]
2517 // CHECK5-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8, !dbg [[DBG14]]
2518 // CHECK5-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG14]]
2519 // CHECK5-NEXT:    [[TMP4:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1, !dbg [[DBG15]]
2520 // CHECK5-NEXT:    [[CONV5:%.*]] = sext i8 [[TMP4]] to i64, !dbg [[DBG15]]
2521 // CHECK5-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG15]]
2522 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG15]]
2523 // CHECK5-NEXT:    call void @__kmpc_for_static_init_8u(ptr @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 [[CONV5]]), !dbg [[DBG15]]
2524 // CHECK5-NEXT:    br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG15]]
2525 // CHECK5:       omp.dispatch.cond:
2526 // CHECK5-NEXT:    [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !dbg [[DBG14]]
2527 // CHECK5-NEXT:    [[TMP8:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_2]], align 8, !dbg [[DBG14]]
2528 // CHECK5-NEXT:    [[CMP6:%.*]] = icmp ugt i64 [[TMP7]], [[TMP8]], !dbg [[DBG14]]
2529 // CHECK5-NEXT:    br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]], !dbg [[DBG14]]
2530 // CHECK5:       cond.true:
2531 // CHECK5-NEXT:    [[TMP9:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_2]], align 8, !dbg [[DBG14]]
2532 // CHECK5-NEXT:    br label [[COND_END:%.*]], !dbg [[DBG14]]
2533 // CHECK5:       cond.false:
2534 // CHECK5-NEXT:    [[TMP10:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !dbg [[DBG14]]
2535 // CHECK5-NEXT:    br label [[COND_END]], !dbg [[DBG14]]
2536 // CHECK5:       cond.end:
2537 // CHECK5-NEXT:    [[COND:%.*]] = phi i64 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ], !dbg [[DBG14]]
2538 // CHECK5-NEXT:    store i64 [[COND]], ptr [[DOTOMP_UB]], align 8, !dbg [[DBG14]]
2539 // CHECK5-NEXT:    [[TMP11:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8, !dbg [[DBG14]]
2540 // CHECK5-NEXT:    store i64 [[TMP11]], ptr [[DOTOMP_IV]], align 8, !dbg [[DBG14]]
2541 // CHECK5-NEXT:    [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !dbg [[DBG14]]
2542 // CHECK5-NEXT:    [[TMP13:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !dbg [[DBG14]]
2543 // CHECK5-NEXT:    [[ADD7:%.*]] = add i64 [[TMP13]], 1, !dbg [[DBG14]]
2544 // CHECK5-NEXT:    [[CMP8:%.*]] = icmp ult i64 [[TMP12]], [[ADD7]], !dbg [[DBG14]]
2545 // CHECK5-NEXT:    br i1 [[CMP8]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG15]]
2546 // CHECK5:       omp.dispatch.body:
2547 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG15]]
2548 // CHECK5:       omp.inner.for.cond:
2549 // CHECK5-NEXT:    [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !dbg [[DBG14]]
2550 // CHECK5-NEXT:    [[TMP15:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !dbg [[DBG14]]
2551 // CHECK5-NEXT:    [[ADD9:%.*]] = add i64 [[TMP15]], 1, !dbg [[DBG14]]
2552 // CHECK5-NEXT:    [[CMP10:%.*]] = icmp ult i64 [[TMP14]], [[ADD9]], !dbg [[DBG14]]
2553 // CHECK5-NEXT:    br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG15]]
2554 // CHECK5:       omp.inner.for.body:
2555 // CHECK5-NEXT:    [[TMP16:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !dbg [[DBG14]]
2556 // CHECK5-NEXT:    [[MUL:%.*]] = mul i64 [[TMP16]], 1, !dbg [[DBG14]]
2557 // CHECK5-NEXT:    [[ADD11:%.*]] = add i64 1, [[MUL]], !dbg [[DBG14]]
2558 // CHECK5-NEXT:    store i64 [[ADD11]], ptr [[I4]], align 8, !dbg [[DBG14]]
2559 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG16:![0-9]+]]
2560 // CHECK5:       omp.body.continue:
2561 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG15]]
2562 // CHECK5:       omp.inner.for.inc:
2563 // CHECK5-NEXT:    [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !dbg [[DBG14]]
2564 // CHECK5-NEXT:    [[ADD12:%.*]] = add i64 [[TMP17]], 1, !dbg [[DBG14]]
2565 // CHECK5-NEXT:    store i64 [[ADD12]], ptr [[DOTOMP_IV]], align 8, !dbg [[DBG14]]
2566 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]], !dbg [[DBG15]], !llvm.loop [[LOOP17:![0-9]+]]
2567 // CHECK5:       omp.inner.for.end:
2568 // CHECK5-NEXT:    br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG15]]
2569 // CHECK5:       omp.dispatch.inc:
2570 // CHECK5-NEXT:    [[TMP18:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8, !dbg [[DBG14]]
2571 // CHECK5-NEXT:    [[TMP19:%.*]] = load i64, ptr [[DOTOMP_STRIDE]], align 8, !dbg [[DBG14]]
2572 // CHECK5-NEXT:    [[ADD13:%.*]] = add i64 [[TMP18]], [[TMP19]], !dbg [[DBG14]]
2573 // CHECK5-NEXT:    store i64 [[ADD13]], ptr [[DOTOMP_LB]], align 8, !dbg [[DBG14]]
2574 // CHECK5-NEXT:    [[TMP20:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !dbg [[DBG14]]
2575 // CHECK5-NEXT:    [[TMP21:%.*]] = load i64, ptr [[DOTOMP_STRIDE]], align 8, !dbg [[DBG14]]
2576 // CHECK5-NEXT:    [[ADD14:%.*]] = add i64 [[TMP20]], [[TMP21]], !dbg [[DBG14]]
2577 // CHECK5-NEXT:    store i64 [[ADD14]], ptr [[DOTOMP_UB]], align 8, !dbg [[DBG14]]
2578 // CHECK5-NEXT:    br label [[OMP_DISPATCH_COND]], !dbg [[DBG15]], !llvm.loop [[LOOP18:![0-9]+]]
2579 // CHECK5:       omp.dispatch.end:
2580 // CHECK5-NEXT:    [[TMP22:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG15]]
2581 // CHECK5-NEXT:    [[TMP23:%.*]] = load i32, ptr [[TMP22]], align 4, !dbg [[DBG15]]
2582 // CHECK5-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB3:[0-9]+]], i32 [[TMP23]]), !dbg [[DBG15]]
2583 // CHECK5-NEXT:    br label [[OMP_PRECOND_END]], !dbg [[DBG15]]
2584 // CHECK5:       omp.precond.end:
2585 // CHECK5-NEXT:    ret void, !dbg [[DBG16]]
2586 //
2587 //
2588 // CHECK5-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_
2589 // CHECK5-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] !dbg [[DBG21:![0-9]+]] {
2590 // CHECK5-NEXT:  entry:
2591 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
2592 // CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
2593 // CHECK5-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
2594 // CHECK5-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
2595 // CHECK5-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
2596 // CHECK5-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
2597 // CHECK5-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
2598 // CHECK5-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
2599 // CHECK5-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB9:[0-9]+]], i32 4, ptr @_Z23without_schedule_clausePfS_S_S_.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]), !dbg [[DBG22:![0-9]+]]
2600 // CHECK5-NEXT:    ret void, !dbg [[DBG23:![0-9]+]]
2601 //
2602 //
2603 // CHECK5-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_.omp_outlined
2604 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] !dbg [[DBG24:![0-9]+]] {
2605 // CHECK5-NEXT:  entry:
2606 // CHECK5-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
2607 // CHECK5-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
2608 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
2609 // CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
2610 // CHECK5-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
2611 // CHECK5-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
2612 // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2613 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2614 // CHECK5-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2615 // CHECK5-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2616 // CHECK5-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2617 // CHECK5-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2618 // CHECK5-NEXT:    [[I:%.*]] = alloca i32, align 4
2619 // CHECK5-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
2620 // CHECK5-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
2621 // CHECK5-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
2622 // CHECK5-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
2623 // CHECK5-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
2624 // CHECK5-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
2625 // CHECK5-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG25:![0-9]+]]
2626 // CHECK5-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG25]]
2627 // CHECK5-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG25]]
2628 // CHECK5-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !dbg [[DBG25]]
2629 // CHECK5-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG26:![0-9]+]]
2630 // CHECK5-NEXT:    store i32 4571423, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG26]]
2631 // CHECK5-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG26]]
2632 // CHECK5-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG26]]
2633 // CHECK5-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG25]]
2634 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4, !dbg [[DBG25]]
2635 // CHECK5-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB6:[0-9]+]], i32 [[TMP5]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1), !dbg [[DBG25]]
2636 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG26]]
2637 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423, !dbg [[DBG26]]
2638 // CHECK5-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]], !dbg [[DBG26]]
2639 // CHECK5:       cond.true:
2640 // CHECK5-NEXT:    br label [[COND_END:%.*]], !dbg [[DBG26]]
2641 // CHECK5:       cond.false:
2642 // CHECK5-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG26]]
2643 // CHECK5-NEXT:    br label [[COND_END]], !dbg [[DBG26]]
2644 // CHECK5:       cond.end:
2645 // CHECK5-NEXT:    [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ], !dbg [[DBG26]]
2646 // CHECK5-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4, !dbg [[DBG26]]
2647 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG26]]
2648 // CHECK5-NEXT:    store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG26]]
2649 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG25]]
2650 // CHECK5:       omp.inner.for.cond:
2651 // CHECK5-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG26]]
2652 // CHECK5-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG26]]
2653 // CHECK5-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]], !dbg [[DBG26]]
2654 // CHECK5-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG25]]
2655 // CHECK5:       omp.inner.for.body:
2656 // CHECK5-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG26]]
2657 // CHECK5-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7, !dbg [[DBG26]]
2658 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 33, [[MUL]], !dbg [[DBG26]]
2659 // CHECK5-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !dbg [[DBG26]]
2660 // CHECK5-NEXT:    [[TMP12:%.*]] = load ptr, ptr [[TMP1]], align 8, !dbg [[DBG27:![0-9]+]]
2661 // CHECK5-NEXT:    [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !dbg [[DBG27]]
2662 // CHECK5-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64, !dbg [[DBG27]]
2663 // CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP12]], i64 [[IDXPROM]], !dbg [[DBG27]]
2664 // CHECK5-NEXT:    [[TMP14:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !dbg [[DBG27]]
2665 // CHECK5-NEXT:    [[TMP15:%.*]] = load ptr, ptr [[TMP2]], align 8, !dbg [[DBG27]]
2666 // CHECK5-NEXT:    [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !dbg [[DBG27]]
2667 // CHECK5-NEXT:    [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64, !dbg [[DBG27]]
2668 // CHECK5-NEXT:    [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP15]], i64 [[IDXPROM2]], !dbg [[DBG27]]
2669 // CHECK5-NEXT:    [[TMP17:%.*]] = load float, ptr [[ARRAYIDX3]], align 4, !dbg [[DBG27]]
2670 // CHECK5-NEXT:    [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]], !dbg [[DBG27]]
2671 // CHECK5-NEXT:    [[TMP18:%.*]] = load ptr, ptr [[TMP3]], align 8, !dbg [[DBG27]]
2672 // CHECK5-NEXT:    [[TMP19:%.*]] = load i32, ptr [[I]], align 4, !dbg [[DBG27]]
2673 // CHECK5-NEXT:    [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64, !dbg [[DBG27]]
2674 // CHECK5-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP18]], i64 [[IDXPROM5]], !dbg [[DBG27]]
2675 // CHECK5-NEXT:    [[TMP20:%.*]] = load float, ptr [[ARRAYIDX6]], align 4, !dbg [[DBG27]]
2676 // CHECK5-NEXT:    [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]], !dbg [[DBG27]]
2677 // CHECK5-NEXT:    [[TMP21:%.*]] = load ptr, ptr [[TMP0]], align 8, !dbg [[DBG27]]
2678 // CHECK5-NEXT:    [[TMP22:%.*]] = load i32, ptr [[I]], align 4, !dbg [[DBG27]]
2679 // CHECK5-NEXT:    [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64, !dbg [[DBG27]]
2680 // CHECK5-NEXT:    [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP21]], i64 [[IDXPROM8]], !dbg [[DBG27]]
2681 // CHECK5-NEXT:    store float [[MUL7]], ptr [[ARRAYIDX9]], align 4, !dbg [[DBG27]]
2682 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG28:![0-9]+]]
2683 // CHECK5:       omp.body.continue:
2684 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG25]]
2685 // CHECK5:       omp.inner.for.inc:
2686 // CHECK5-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG26]]
2687 // CHECK5-NEXT:    [[ADD10:%.*]] = add nsw i32 [[TMP23]], 1, !dbg [[DBG26]]
2688 // CHECK5-NEXT:    store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG26]]
2689 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]], !dbg [[DBG25]], !llvm.loop [[LOOP29:![0-9]+]]
2690 // CHECK5:       omp.inner.for.end:
2691 // CHECK5-NEXT:    br label [[OMP_LOOP_EXIT:%.*]], !dbg [[DBG25]]
2692 // CHECK5:       omp.loop.exit:
2693 // CHECK5-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB8:[0-9]+]], i32 [[TMP5]]), !dbg [[DBG25]]
2694 // CHECK5-NEXT:    ret void, !dbg [[DBG28]]
2695 //
2696 //
2697 // CHECK5-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_
2698 // CHECK5-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] !dbg [[DBG30:![0-9]+]] {
2699 // CHECK5-NEXT:  entry:
2700 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
2701 // CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
2702 // CHECK5-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
2703 // CHECK5-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
2704 // CHECK5-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
2705 // CHECK5-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
2706 // CHECK5-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
2707 // CHECK5-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
2708 // CHECK5-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB14:[0-9]+]], i32 4, ptr @_Z18static_not_chunkedPfS_S_S_.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]), !dbg [[DBG31:![0-9]+]]
2709 // CHECK5-NEXT:    ret void, !dbg [[DBG32:![0-9]+]]
2710 //
2711 //
2712 // CHECK5-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_.omp_outlined
2713 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] !dbg [[DBG33:![0-9]+]] {
2714 // CHECK5-NEXT:  entry:
2715 // CHECK5-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
2716 // CHECK5-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
2717 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
2718 // CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
2719 // CHECK5-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
2720 // CHECK5-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
2721 // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2722 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2723 // CHECK5-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2724 // CHECK5-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2725 // CHECK5-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2726 // CHECK5-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2727 // CHECK5-NEXT:    [[I:%.*]] = alloca i32, align 4
2728 // CHECK5-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
2729 // CHECK5-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
2730 // CHECK5-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
2731 // CHECK5-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
2732 // CHECK5-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
2733 // CHECK5-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
2734 // CHECK5-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG34:![0-9]+]]
2735 // CHECK5-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG34]]
2736 // CHECK5-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG34]]
2737 // CHECK5-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !dbg [[DBG34]]
2738 // CHECK5-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG35:![0-9]+]]
2739 // CHECK5-NEXT:    store i32 4571423, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG35]]
2740 // CHECK5-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG35]]
2741 // CHECK5-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG35]]
2742 // CHECK5-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG34]]
2743 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4, !dbg [[DBG34]]
2744 // CHECK5-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB11:[0-9]+]], i32 [[TMP5]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1), !dbg [[DBG34]]
2745 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG35]]
2746 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423, !dbg [[DBG35]]
2747 // CHECK5-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]], !dbg [[DBG35]]
2748 // CHECK5:       cond.true:
2749 // CHECK5-NEXT:    br label [[COND_END:%.*]], !dbg [[DBG35]]
2750 // CHECK5:       cond.false:
2751 // CHECK5-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG35]]
2752 // CHECK5-NEXT:    br label [[COND_END]], !dbg [[DBG35]]
2753 // CHECK5:       cond.end:
2754 // CHECK5-NEXT:    [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ], !dbg [[DBG35]]
2755 // CHECK5-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4, !dbg [[DBG35]]
2756 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG35]]
2757 // CHECK5-NEXT:    store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG35]]
2758 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG34]]
2759 // CHECK5:       omp.inner.for.cond:
2760 // CHECK5-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG35]]
2761 // CHECK5-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG35]]
2762 // CHECK5-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]], !dbg [[DBG35]]
2763 // CHECK5-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG34]]
2764 // CHECK5:       omp.inner.for.body:
2765 // CHECK5-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG35]]
2766 // CHECK5-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7, !dbg [[DBG35]]
2767 // CHECK5-NEXT:    [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]], !dbg [[DBG35]]
2768 // CHECK5-NEXT:    store i32 [[SUB]], ptr [[I]], align 4, !dbg [[DBG35]]
2769 // CHECK5-NEXT:    [[TMP12:%.*]] = load ptr, ptr [[TMP1]], align 8, !dbg [[DBG36:![0-9]+]]
2770 // CHECK5-NEXT:    [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !dbg [[DBG36]]
2771 // CHECK5-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64, !dbg [[DBG36]]
2772 // CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP12]], i64 [[IDXPROM]], !dbg [[DBG36]]
2773 // CHECK5-NEXT:    [[TMP14:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !dbg [[DBG36]]
2774 // CHECK5-NEXT:    [[TMP15:%.*]] = load ptr, ptr [[TMP2]], align 8, !dbg [[DBG36]]
2775 // CHECK5-NEXT:    [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !dbg [[DBG36]]
2776 // CHECK5-NEXT:    [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64, !dbg [[DBG36]]
2777 // CHECK5-NEXT:    [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP15]], i64 [[IDXPROM2]], !dbg [[DBG36]]
2778 // CHECK5-NEXT:    [[TMP17:%.*]] = load float, ptr [[ARRAYIDX3]], align 4, !dbg [[DBG36]]
2779 // CHECK5-NEXT:    [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]], !dbg [[DBG36]]
2780 // CHECK5-NEXT:    [[TMP18:%.*]] = load ptr, ptr [[TMP3]], align 8, !dbg [[DBG36]]
2781 // CHECK5-NEXT:    [[TMP19:%.*]] = load i32, ptr [[I]], align 4, !dbg [[DBG36]]
2782 // CHECK5-NEXT:    [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64, !dbg [[DBG36]]
2783 // CHECK5-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP18]], i64 [[IDXPROM5]], !dbg [[DBG36]]
2784 // CHECK5-NEXT:    [[TMP20:%.*]] = load float, ptr [[ARRAYIDX6]], align 4, !dbg [[DBG36]]
2785 // CHECK5-NEXT:    [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]], !dbg [[DBG36]]
2786 // CHECK5-NEXT:    [[TMP21:%.*]] = load ptr, ptr [[TMP0]], align 8, !dbg [[DBG36]]
2787 // CHECK5-NEXT:    [[TMP22:%.*]] = load i32, ptr [[I]], align 4, !dbg [[DBG36]]
2788 // CHECK5-NEXT:    [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64, !dbg [[DBG36]]
2789 // CHECK5-NEXT:    [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP21]], i64 [[IDXPROM8]], !dbg [[DBG36]]
2790 // CHECK5-NEXT:    store float [[MUL7]], ptr [[ARRAYIDX9]], align 4, !dbg [[DBG36]]
2791 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG37:![0-9]+]]
2792 // CHECK5:       omp.body.continue:
2793 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG34]]
2794 // CHECK5:       omp.inner.for.inc:
2795 // CHECK5-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG35]]
2796 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP23]], 1, !dbg [[DBG35]]
2797 // CHECK5-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG35]]
2798 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]], !dbg [[DBG34]], !llvm.loop [[LOOP38:![0-9]+]]
2799 // CHECK5:       omp.inner.for.end:
2800 // CHECK5-NEXT:    br label [[OMP_LOOP_EXIT:%.*]], !dbg [[DBG34]]
2801 // CHECK5:       omp.loop.exit:
2802 // CHECK5-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB13:[0-9]+]], i32 [[TMP5]]), !dbg [[DBG34]]
2803 // CHECK5-NEXT:    ret void, !dbg [[DBG37]]
2804 //
2805 //
2806 // CHECK5-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_
2807 // CHECK5-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] !dbg [[DBG39:![0-9]+]] {
2808 // CHECK5-NEXT:  entry:
2809 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
2810 // CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
2811 // CHECK5-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
2812 // CHECK5-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
2813 // CHECK5-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
2814 // CHECK5-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
2815 // CHECK5-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
2816 // CHECK5-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
2817 // CHECK5-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB19:[0-9]+]], i32 4, ptr @_Z14static_chunkedPfS_S_S_.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]), !dbg [[DBG40:![0-9]+]]
2818 // CHECK5-NEXT:    ret void, !dbg [[DBG41:![0-9]+]]
2819 //
2820 //
2821 // CHECK5-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_.omp_outlined
2822 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] !dbg [[DBG42:![0-9]+]] {
2823 // CHECK5-NEXT:  entry:
2824 // CHECK5-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
2825 // CHECK5-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
2826 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
2827 // CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
2828 // CHECK5-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
2829 // CHECK5-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
2830 // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2831 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2832 // CHECK5-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2833 // CHECK5-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2834 // CHECK5-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2835 // CHECK5-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2836 // CHECK5-NEXT:    [[I:%.*]] = alloca i32, align 4
2837 // CHECK5-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
2838 // CHECK5-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
2839 // CHECK5-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
2840 // CHECK5-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
2841 // CHECK5-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
2842 // CHECK5-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
2843 // CHECK5-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG43:![0-9]+]]
2844 // CHECK5-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG43]]
2845 // CHECK5-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG43]]
2846 // CHECK5-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !dbg [[DBG43]]
2847 // CHECK5-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG44:![0-9]+]]
2848 // CHECK5-NEXT:    store i32 16908288, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG44]]
2849 // CHECK5-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG44]]
2850 // CHECK5-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG44]]
2851 // CHECK5-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG43]]
2852 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4, !dbg [[DBG43]]
2853 // CHECK5-NEXT:    call void @__kmpc_for_static_init_4u(ptr @[[GLOB16:[0-9]+]], i32 [[TMP5]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 5), !dbg [[DBG43]]
2854 // CHECK5-NEXT:    br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG43]]
2855 // CHECK5:       omp.dispatch.cond:
2856 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG44]]
2857 // CHECK5-NEXT:    [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288, !dbg [[DBG44]]
2858 // CHECK5-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]], !dbg [[DBG44]]
2859 // CHECK5:       cond.true:
2860 // CHECK5-NEXT:    br label [[COND_END:%.*]], !dbg [[DBG44]]
2861 // CHECK5:       cond.false:
2862 // CHECK5-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG44]]
2863 // CHECK5-NEXT:    br label [[COND_END]], !dbg [[DBG44]]
2864 // CHECK5:       cond.end:
2865 // CHECK5-NEXT:    [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ], !dbg [[DBG44]]
2866 // CHECK5-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4, !dbg [[DBG44]]
2867 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG44]]
2868 // CHECK5-NEXT:    store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG44]]
2869 // CHECK5-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG44]]
2870 // CHECK5-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG44]]
2871 // CHECK5-NEXT:    [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]], !dbg [[DBG44]]
2872 // CHECK5-NEXT:    br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG43]]
2873 // CHECK5:       omp.dispatch.body:
2874 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG43]]
2875 // CHECK5:       omp.inner.for.cond:
2876 // CHECK5-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG44]]
2877 // CHECK5-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG44]]
2878 // CHECK5-NEXT:    [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]], !dbg [[DBG44]]
2879 // CHECK5-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG43]]
2880 // CHECK5:       omp.inner.for.body:
2881 // CHECK5-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG44]]
2882 // CHECK5-NEXT:    [[MUL:%.*]] = mul i32 [[TMP13]], 127, !dbg [[DBG44]]
2883 // CHECK5-NEXT:    [[ADD:%.*]] = add i32 131071, [[MUL]], !dbg [[DBG44]]
2884 // CHECK5-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !dbg [[DBG44]]
2885 // CHECK5-NEXT:    [[TMP14:%.*]] = load ptr, ptr [[TMP1]], align 8, !dbg [[DBG45:![0-9]+]]
2886 // CHECK5-NEXT:    [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !dbg [[DBG45]]
2887 // CHECK5-NEXT:    [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64, !dbg [[DBG45]]
2888 // CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP14]], i64 [[IDXPROM]], !dbg [[DBG45]]
2889 // CHECK5-NEXT:    [[TMP16:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !dbg [[DBG45]]
2890 // CHECK5-NEXT:    [[TMP17:%.*]] = load ptr, ptr [[TMP2]], align 8, !dbg [[DBG45]]
2891 // CHECK5-NEXT:    [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !dbg [[DBG45]]
2892 // CHECK5-NEXT:    [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64, !dbg [[DBG45]]
2893 // CHECK5-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds float, ptr [[TMP17]], i64 [[IDXPROM3]], !dbg [[DBG45]]
2894 // CHECK5-NEXT:    [[TMP19:%.*]] = load float, ptr [[ARRAYIDX4]], align 4, !dbg [[DBG45]]
2895 // CHECK5-NEXT:    [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]], !dbg [[DBG45]]
2896 // CHECK5-NEXT:    [[TMP20:%.*]] = load ptr, ptr [[TMP3]], align 8, !dbg [[DBG45]]
2897 // CHECK5-NEXT:    [[TMP21:%.*]] = load i32, ptr [[I]], align 4, !dbg [[DBG45]]
2898 // CHECK5-NEXT:    [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64, !dbg [[DBG45]]
2899 // CHECK5-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds float, ptr [[TMP20]], i64 [[IDXPROM6]], !dbg [[DBG45]]
2900 // CHECK5-NEXT:    [[TMP22:%.*]] = load float, ptr [[ARRAYIDX7]], align 4, !dbg [[DBG45]]
2901 // CHECK5-NEXT:    [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]], !dbg [[DBG45]]
2902 // CHECK5-NEXT:    [[TMP23:%.*]] = load ptr, ptr [[TMP0]], align 8, !dbg [[DBG45]]
2903 // CHECK5-NEXT:    [[TMP24:%.*]] = load i32, ptr [[I]], align 4, !dbg [[DBG45]]
2904 // CHECK5-NEXT:    [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64, !dbg [[DBG45]]
2905 // CHECK5-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP23]], i64 [[IDXPROM9]], !dbg [[DBG45]]
2906 // CHECK5-NEXT:    store float [[MUL8]], ptr [[ARRAYIDX10]], align 4, !dbg [[DBG45]]
2907 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG46:![0-9]+]]
2908 // CHECK5:       omp.body.continue:
2909 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG43]]
2910 // CHECK5:       omp.inner.for.inc:
2911 // CHECK5-NEXT:    [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG44]]
2912 // CHECK5-NEXT:    [[ADD11:%.*]] = add i32 [[TMP25]], 1, !dbg [[DBG44]]
2913 // CHECK5-NEXT:    store i32 [[ADD11]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG44]]
2914 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]], !dbg [[DBG43]], !llvm.loop [[LOOP47:![0-9]+]]
2915 // CHECK5:       omp.inner.for.end:
2916 // CHECK5-NEXT:    br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG43]]
2917 // CHECK5:       omp.dispatch.inc:
2918 // CHECK5-NEXT:    [[TMP26:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG44]]
2919 // CHECK5-NEXT:    [[TMP27:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG44]]
2920 // CHECK5-NEXT:    [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]], !dbg [[DBG44]]
2921 // CHECK5-NEXT:    store i32 [[ADD12]], ptr [[DOTOMP_LB]], align 4, !dbg [[DBG44]]
2922 // CHECK5-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG44]]
2923 // CHECK5-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG44]]
2924 // CHECK5-NEXT:    [[ADD13:%.*]] = add i32 [[TMP28]], [[TMP29]], !dbg [[DBG44]]
2925 // CHECK5-NEXT:    store i32 [[ADD13]], ptr [[DOTOMP_UB]], align 4, !dbg [[DBG44]]
2926 // CHECK5-NEXT:    br label [[OMP_DISPATCH_COND]], !dbg [[DBG43]], !llvm.loop [[LOOP48:![0-9]+]]
2927 // CHECK5:       omp.dispatch.end:
2928 // CHECK5-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB18:[0-9]+]], i32 [[TMP5]]), !dbg [[DBG43]]
2929 // CHECK5-NEXT:    ret void, !dbg [[DBG46]]
2930 //
2931 //
2932 // CHECK5-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_
2933 // CHECK5-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] !dbg [[DBG49:![0-9]+]] {
2934 // CHECK5-NEXT:  entry:
2935 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
2936 // CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
2937 // CHECK5-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
2938 // CHECK5-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
2939 // CHECK5-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
2940 // CHECK5-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
2941 // CHECK5-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
2942 // CHECK5-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
2943 // CHECK5-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB21:[0-9]+]], i32 4, ptr @_Z8dynamic1PfS_S_S_.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]), !dbg [[DBG50:![0-9]+]]
2944 // CHECK5-NEXT:    ret void, !dbg [[DBG51:![0-9]+]]
2945 //
2946 //
2947 // CHECK5-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_.omp_outlined
2948 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] !dbg [[DBG52:![0-9]+]] {
2949 // CHECK5-NEXT:  entry:
2950 // CHECK5-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
2951 // CHECK5-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
2952 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
2953 // CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
2954 // CHECK5-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
2955 // CHECK5-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
2956 // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
2957 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i64, align 8
2958 // CHECK5-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
2959 // CHECK5-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
2960 // CHECK5-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
2961 // CHECK5-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2962 // CHECK5-NEXT:    [[I:%.*]] = alloca i64, align 8
2963 // CHECK5-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
2964 // CHECK5-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
2965 // CHECK5-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
2966 // CHECK5-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
2967 // CHECK5-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
2968 // CHECK5-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
2969 // CHECK5-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG53:![0-9]+]]
2970 // CHECK5-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG53]]
2971 // CHECK5-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG53]]
2972 // CHECK5-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !dbg [[DBG53]]
2973 // CHECK5-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8, !dbg [[DBG54:![0-9]+]]
2974 // CHECK5-NEXT:    store i64 16908287, ptr [[DOTOMP_UB]], align 8, !dbg [[DBG54]]
2975 // CHECK5-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8, !dbg [[DBG54]]
2976 // CHECK5-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG54]]
2977 // CHECK5-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG53]]
2978 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4, !dbg [[DBG53]]
2979 // CHECK5-NEXT:    call void @__kmpc_dispatch_init_8u(ptr @[[GLOB21]], i32 [[TMP5]], i32 1073741859, i64 0, i64 16908287, i64 1, i64 1), !dbg [[DBG53]]
2980 // CHECK5-NEXT:    br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG53]]
2981 // CHECK5:       omp.dispatch.cond:
2982 // CHECK5-NEXT:    [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_8u(ptr @[[GLOB21]], i32 [[TMP5]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]]), !dbg [[DBG53]]
2983 // CHECK5-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0, !dbg [[DBG53]]
2984 // CHECK5-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG53]]
2985 // CHECK5:       omp.dispatch.body:
2986 // CHECK5-NEXT:    [[TMP7:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8, !dbg [[DBG54]]
2987 // CHECK5-NEXT:    store i64 [[TMP7]], ptr [[DOTOMP_IV]], align 8, !dbg [[DBG54]]
2988 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG53]]
2989 // CHECK5:       omp.inner.for.cond:
2990 // CHECK5-NEXT:    [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !dbg [[DBG54]], !llvm.access.group [[ACC_GRP55:![0-9]+]]
2991 // CHECK5-NEXT:    [[TMP9:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !dbg [[DBG54]], !llvm.access.group [[ACC_GRP55]]
2992 // CHECK5-NEXT:    [[ADD:%.*]] = add i64 [[TMP9]], 1, !dbg [[DBG54]]
2993 // CHECK5-NEXT:    [[CMP:%.*]] = icmp ult i64 [[TMP8]], [[ADD]], !dbg [[DBG54]]
2994 // CHECK5-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG53]]
2995 // CHECK5:       omp.inner.for.body:
2996 // CHECK5-NEXT:    [[TMP10:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !dbg [[DBG54]], !llvm.access.group [[ACC_GRP55]]
2997 // CHECK5-NEXT:    [[MUL:%.*]] = mul i64 [[TMP10]], 127, !dbg [[DBG54]]
2998 // CHECK5-NEXT:    [[ADD1:%.*]] = add i64 131071, [[MUL]], !dbg [[DBG54]]
2999 // CHECK5-NEXT:    store i64 [[ADD1]], ptr [[I]], align 8, !dbg [[DBG54]], !llvm.access.group [[ACC_GRP55]]
3000 // CHECK5-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[TMP1]], align 8, !dbg [[DBG56:![0-9]+]], !llvm.access.group [[ACC_GRP55]]
3001 // CHECK5-NEXT:    [[TMP12:%.*]] = load i64, ptr [[I]], align 8, !dbg [[DBG56]], !llvm.access.group [[ACC_GRP55]]
3002 // CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP11]], i64 [[TMP12]], !dbg [[DBG56]]
3003 // CHECK5-NEXT:    [[TMP13:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !dbg [[DBG56]], !llvm.access.group [[ACC_GRP55]]
3004 // CHECK5-NEXT:    [[TMP14:%.*]] = load ptr, ptr [[TMP2]], align 8, !dbg [[DBG56]], !llvm.access.group [[ACC_GRP55]]
3005 // CHECK5-NEXT:    [[TMP15:%.*]] = load i64, ptr [[I]], align 8, !dbg [[DBG56]], !llvm.access.group [[ACC_GRP55]]
3006 // CHECK5-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[TMP14]], i64 [[TMP15]], !dbg [[DBG56]]
3007 // CHECK5-NEXT:    [[TMP16:%.*]] = load float, ptr [[ARRAYIDX2]], align 4, !dbg [[DBG56]], !llvm.access.group [[ACC_GRP55]]
3008 // CHECK5-NEXT:    [[MUL3:%.*]] = fmul float [[TMP13]], [[TMP16]], !dbg [[DBG56]]
3009 // CHECK5-NEXT:    [[TMP17:%.*]] = load ptr, ptr [[TMP3]], align 8, !dbg [[DBG56]], !llvm.access.group [[ACC_GRP55]]
3010 // CHECK5-NEXT:    [[TMP18:%.*]] = load i64, ptr [[I]], align 8, !dbg [[DBG56]], !llvm.access.group [[ACC_GRP55]]
3011 // CHECK5-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds float, ptr [[TMP17]], i64 [[TMP18]], !dbg [[DBG56]]
3012 // CHECK5-NEXT:    [[TMP19:%.*]] = load float, ptr [[ARRAYIDX4]], align 4, !dbg [[DBG56]], !llvm.access.group [[ACC_GRP55]]
3013 // CHECK5-NEXT:    [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP19]], !dbg [[DBG56]]
3014 // CHECK5-NEXT:    [[TMP20:%.*]] = load ptr, ptr [[TMP0]], align 8, !dbg [[DBG56]], !llvm.access.group [[ACC_GRP55]]
3015 // CHECK5-NEXT:    [[TMP21:%.*]] = load i64, ptr [[I]], align 8, !dbg [[DBG56]], !llvm.access.group [[ACC_GRP55]]
3016 // CHECK5-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP20]], i64 [[TMP21]], !dbg [[DBG56]]
3017 // CHECK5-NEXT:    store float [[MUL5]], ptr [[ARRAYIDX6]], align 4, !dbg [[DBG56]], !llvm.access.group [[ACC_GRP55]]
3018 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG57:![0-9]+]]
3019 // CHECK5:       omp.body.continue:
3020 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG53]]
3021 // CHECK5:       omp.inner.for.inc:
3022 // CHECK5-NEXT:    [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !dbg [[DBG54]], !llvm.access.group [[ACC_GRP55]]
3023 // CHECK5-NEXT:    [[ADD7:%.*]] = add i64 [[TMP22]], 1, !dbg [[DBG54]]
3024 // CHECK5-NEXT:    store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !dbg [[DBG54]], !llvm.access.group [[ACC_GRP55]]
3025 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]], !dbg [[DBG53]], !llvm.loop [[LOOP58:![0-9]+]]
3026 // CHECK5:       omp.inner.for.end:
3027 // CHECK5-NEXT:    br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG53]]
3028 // CHECK5:       omp.dispatch.inc:
3029 // CHECK5-NEXT:    br label [[OMP_DISPATCH_COND]], !dbg [[DBG53]], !llvm.loop [[LOOP60:![0-9]+]]
3030 // CHECK5:       omp.dispatch.end:
3031 // CHECK5-NEXT:    ret void, !dbg [[DBG57]]
3032 //
3033 //
3034 // CHECK5-LABEL: define {{[^@]+}}@_Z7guided7PfS_S_S_
3035 // CHECK5-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] !dbg [[DBG61:![0-9]+]] {
3036 // CHECK5-NEXT:  entry:
3037 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
3038 // CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
3039 // CHECK5-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
3040 // CHECK5-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
3041 // CHECK5-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
3042 // CHECK5-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
3043 // CHECK5-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
3044 // CHECK5-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
3045 // CHECK5-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB23:[0-9]+]], i32 4, ptr @_Z7guided7PfS_S_S_.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]), !dbg [[DBG62:![0-9]+]]
3046 // CHECK5-NEXT:    ret void, !dbg [[DBG63:![0-9]+]]
3047 //
3048 //
3049 // CHECK5-LABEL: define {{[^@]+}}@_Z7guided7PfS_S_S_.omp_outlined
3050 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] !dbg [[DBG64:![0-9]+]] {
3051 // CHECK5-NEXT:  entry:
3052 // CHECK5-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
3053 // CHECK5-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
3054 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
3055 // CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
3056 // CHECK5-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
3057 // CHECK5-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
3058 // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
3059 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i64, align 8
3060 // CHECK5-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
3061 // CHECK5-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
3062 // CHECK5-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
3063 // CHECK5-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3064 // CHECK5-NEXT:    [[I:%.*]] = alloca i64, align 8
3065 // CHECK5-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
3066 // CHECK5-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
3067 // CHECK5-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
3068 // CHECK5-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
3069 // CHECK5-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
3070 // CHECK5-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
3071 // CHECK5-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG65:![0-9]+]]
3072 // CHECK5-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG65]]
3073 // CHECK5-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG65]]
3074 // CHECK5-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !dbg [[DBG65]]
3075 // CHECK5-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8, !dbg [[DBG66:![0-9]+]]
3076 // CHECK5-NEXT:    store i64 16908287, ptr [[DOTOMP_UB]], align 8, !dbg [[DBG66]]
3077 // CHECK5-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8, !dbg [[DBG66]]
3078 // CHECK5-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG66]]
3079 // CHECK5-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG65]]
3080 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4, !dbg [[DBG65]]
3081 // CHECK5-NEXT:    call void @__kmpc_dispatch_init_8u(ptr @[[GLOB23]], i32 [[TMP5]], i32 1073741860, i64 0, i64 16908287, i64 1, i64 7), !dbg [[DBG65]]
3082 // CHECK5-NEXT:    br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG65]]
3083 // CHECK5:       omp.dispatch.cond:
3084 // CHECK5-NEXT:    [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_8u(ptr @[[GLOB23]], i32 [[TMP5]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]]), !dbg [[DBG65]]
3085 // CHECK5-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0, !dbg [[DBG65]]
3086 // CHECK5-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG65]]
3087 // CHECK5:       omp.dispatch.body:
3088 // CHECK5-NEXT:    [[TMP7:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8, !dbg [[DBG66]]
3089 // CHECK5-NEXT:    store i64 [[TMP7]], ptr [[DOTOMP_IV]], align 8, !dbg [[DBG66]]
3090 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG65]]
3091 // CHECK5:       omp.inner.for.cond:
3092 // CHECK5-NEXT:    [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !dbg [[DBG66]], !llvm.access.group [[ACC_GRP67:![0-9]+]]
3093 // CHECK5-NEXT:    [[TMP9:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !dbg [[DBG66]], !llvm.access.group [[ACC_GRP67]]
3094 // CHECK5-NEXT:    [[ADD:%.*]] = add i64 [[TMP9]], 1, !dbg [[DBG66]]
3095 // CHECK5-NEXT:    [[CMP:%.*]] = icmp ult i64 [[TMP8]], [[ADD]], !dbg [[DBG66]]
3096 // CHECK5-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG65]]
3097 // CHECK5:       omp.inner.for.body:
3098 // CHECK5-NEXT:    [[TMP10:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !dbg [[DBG66]], !llvm.access.group [[ACC_GRP67]]
3099 // CHECK5-NEXT:    [[MUL:%.*]] = mul i64 [[TMP10]], 127, !dbg [[DBG66]]
3100 // CHECK5-NEXT:    [[ADD1:%.*]] = add i64 131071, [[MUL]], !dbg [[DBG66]]
3101 // CHECK5-NEXT:    store i64 [[ADD1]], ptr [[I]], align 8, !dbg [[DBG66]], !llvm.access.group [[ACC_GRP67]]
3102 // CHECK5-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[TMP1]], align 8, !dbg [[DBG68:![0-9]+]], !llvm.access.group [[ACC_GRP67]]
3103 // CHECK5-NEXT:    [[TMP12:%.*]] = load i64, ptr [[I]], align 8, !dbg [[DBG68]], !llvm.access.group [[ACC_GRP67]]
3104 // CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP11]], i64 [[TMP12]], !dbg [[DBG68]]
3105 // CHECK5-NEXT:    [[TMP13:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !dbg [[DBG68]], !llvm.access.group [[ACC_GRP67]]
3106 // CHECK5-NEXT:    [[TMP14:%.*]] = load ptr, ptr [[TMP2]], align 8, !dbg [[DBG68]], !llvm.access.group [[ACC_GRP67]]
3107 // CHECK5-NEXT:    [[TMP15:%.*]] = load i64, ptr [[I]], align 8, !dbg [[DBG68]], !llvm.access.group [[ACC_GRP67]]
3108 // CHECK5-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[TMP14]], i64 [[TMP15]], !dbg [[DBG68]]
3109 // CHECK5-NEXT:    [[TMP16:%.*]] = load float, ptr [[ARRAYIDX2]], align 4, !dbg [[DBG68]], !llvm.access.group [[ACC_GRP67]]
3110 // CHECK5-NEXT:    [[MUL3:%.*]] = fmul float [[TMP13]], [[TMP16]], !dbg [[DBG68]]
3111 // CHECK5-NEXT:    [[TMP17:%.*]] = load ptr, ptr [[TMP3]], align 8, !dbg [[DBG68]], !llvm.access.group [[ACC_GRP67]]
3112 // CHECK5-NEXT:    [[TMP18:%.*]] = load i64, ptr [[I]], align 8, !dbg [[DBG68]], !llvm.access.group [[ACC_GRP67]]
3113 // CHECK5-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds float, ptr [[TMP17]], i64 [[TMP18]], !dbg [[DBG68]]
3114 // CHECK5-NEXT:    [[TMP19:%.*]] = load float, ptr [[ARRAYIDX4]], align 4, !dbg [[DBG68]], !llvm.access.group [[ACC_GRP67]]
3115 // CHECK5-NEXT:    [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP19]], !dbg [[DBG68]]
3116 // CHECK5-NEXT:    [[TMP20:%.*]] = load ptr, ptr [[TMP0]], align 8, !dbg [[DBG68]], !llvm.access.group [[ACC_GRP67]]
3117 // CHECK5-NEXT:    [[TMP21:%.*]] = load i64, ptr [[I]], align 8, !dbg [[DBG68]], !llvm.access.group [[ACC_GRP67]]
3118 // CHECK5-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP20]], i64 [[TMP21]], !dbg [[DBG68]]
3119 // CHECK5-NEXT:    store float [[MUL5]], ptr [[ARRAYIDX6]], align 4, !dbg [[DBG68]], !llvm.access.group [[ACC_GRP67]]
3120 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG69:![0-9]+]]
3121 // CHECK5:       omp.body.continue:
3122 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG65]]
3123 // CHECK5:       omp.inner.for.inc:
3124 // CHECK5-NEXT:    [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !dbg [[DBG66]], !llvm.access.group [[ACC_GRP67]]
3125 // CHECK5-NEXT:    [[ADD7:%.*]] = add i64 [[TMP22]], 1, !dbg [[DBG66]]
3126 // CHECK5-NEXT:    store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !dbg [[DBG66]], !llvm.access.group [[ACC_GRP67]]
3127 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]], !dbg [[DBG65]], !llvm.loop [[LOOP70:![0-9]+]]
3128 // CHECK5:       omp.inner.for.end:
3129 // CHECK5-NEXT:    br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG65]]
3130 // CHECK5:       omp.dispatch.inc:
3131 // CHECK5-NEXT:    br label [[OMP_DISPATCH_COND]], !dbg [[DBG65]], !llvm.loop [[LOOP72:![0-9]+]]
3132 // CHECK5:       omp.dispatch.end:
3133 // CHECK5-NEXT:    ret void, !dbg [[DBG69]]
3134 //
3135 //
3136 // CHECK5-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_
3137 // CHECK5-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] !dbg [[DBG73:![0-9]+]] {
3138 // CHECK5-NEXT:  entry:
3139 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
3140 // CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
3141 // CHECK5-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
3142 // CHECK5-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
3143 // CHECK5-NEXT:    [[X:%.*]] = alloca i32, align 4
3144 // CHECK5-NEXT:    [[Y:%.*]] = alloca i32, align 4
3145 // CHECK5-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
3146 // CHECK5-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
3147 // CHECK5-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
3148 // CHECK5-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
3149 // CHECK5-NEXT:    store i32 0, ptr [[X]], align 4, !dbg [[DBG74:![0-9]+]]
3150 // CHECK5-NEXT:    store i32 0, ptr [[Y]], align 4, !dbg [[DBG75:![0-9]+]]
3151 // CHECK5-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB25:[0-9]+]], i32 5, ptr @_Z9test_autoPfS_S_S_.omp_outlined, ptr [[Y]], ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]), !dbg [[DBG76:![0-9]+]]
3152 // CHECK5-NEXT:    ret void, !dbg [[DBG77:![0-9]+]]
3153 //
3154 //
3155 // CHECK5-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_.omp_outlined
3156 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[Y:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] !dbg [[DBG78:![0-9]+]] {
3157 // CHECK5-NEXT:  entry:
3158 // CHECK5-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
3159 // CHECK5-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
3160 // CHECK5-NEXT:    [[Y_ADDR:%.*]] = alloca ptr, align 8
3161 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
3162 // CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
3163 // CHECK5-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
3164 // CHECK5-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
3165 // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
3166 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i8, align 1
3167 // CHECK5-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
3168 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
3169 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 8
3170 // CHECK5-NEXT:    [[I:%.*]] = alloca i8, align 1
3171 // CHECK5-NEXT:    [[X:%.*]] = alloca i32, align 4
3172 // CHECK5-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
3173 // CHECK5-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
3174 // CHECK5-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
3175 // CHECK5-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3176 // CHECK5-NEXT:    [[I7:%.*]] = alloca i8, align 1
3177 // CHECK5-NEXT:    [[X8:%.*]] = alloca i32, align 4
3178 // CHECK5-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
3179 // CHECK5-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
3180 // CHECK5-NEXT:    store ptr [[Y]], ptr [[Y_ADDR]], align 8
3181 // CHECK5-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
3182 // CHECK5-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
3183 // CHECK5-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
3184 // CHECK5-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
3185 // CHECK5-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[Y_ADDR]], align 8, !dbg [[DBG79:![0-9]+]]
3186 // CHECK5-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG79]]
3187 // CHECK5-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG79]]
3188 // CHECK5-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG79]]
3189 // CHECK5-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !dbg [[DBG79]]
3190 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 4, !dbg [[DBG80:![0-9]+]]
3191 // CHECK5-NEXT:    [[CONV:%.*]] = trunc i32 [[TMP5]] to i8, !dbg [[DBG80]]
3192 // CHECK5-NEXT:    store i8 [[CONV]], ptr [[DOTCAPTURE_EXPR_]], align 1, !dbg [[DBG80]]
3193 // CHECK5-NEXT:    [[TMP6:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1, !dbg [[DBG80]]
3194 // CHECK5-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP6]] to i32, !dbg [[DBG80]]
3195 // CHECK5-NEXT:    [[SUB:%.*]] = sub i32 57, [[CONV3]], !dbg [[DBG80]]
3196 // CHECK5-NEXT:    [[ADD:%.*]] = add i32 [[SUB]], 1, !dbg [[DBG80]]
3197 // CHECK5-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1, !dbg [[DBG80]]
3198 // CHECK5-NEXT:    [[CONV4:%.*]] = zext i32 [[DIV]] to i64, !dbg [[DBG80]]
3199 // CHECK5-NEXT:    [[MUL:%.*]] = mul nsw i64 [[CONV4]], 11, !dbg [[DBG81:![0-9]+]]
3200 // CHECK5-NEXT:    [[SUB5:%.*]] = sub nsw i64 [[MUL]], 1, !dbg [[DBG81]]
3201 // CHECK5-NEXT:    store i64 [[SUB5]], ptr [[DOTCAPTURE_EXPR_2]], align 8, !dbg [[DBG80]]
3202 // CHECK5-NEXT:    [[TMP7:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1, !dbg [[DBG80]]
3203 // CHECK5-NEXT:    store i8 [[TMP7]], ptr [[I]], align 1, !dbg [[DBG80]]
3204 // CHECK5-NEXT:    store i32 11, ptr [[X]], align 4, !dbg [[DBG81]]
3205 // CHECK5-NEXT:    [[TMP8:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1, !dbg [[DBG80]]
3206 // CHECK5-NEXT:    [[CONV6:%.*]] = sext i8 [[TMP8]] to i32, !dbg [[DBG80]]
3207 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sle i32 [[CONV6]], 57, !dbg [[DBG80]]
3208 // CHECK5-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]], !dbg [[DBG79]]
3209 // CHECK5:       omp.precond.then:
3210 // CHECK5-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8, !dbg [[DBG80]]
3211 // CHECK5-NEXT:    [[TMP9:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_2]], align 8, !dbg [[DBG81]]
3212 // CHECK5-NEXT:    store i64 [[TMP9]], ptr [[DOTOMP_UB]], align 8, !dbg [[DBG80]]
3213 // CHECK5-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8, !dbg [[DBG80]]
3214 // CHECK5-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG80]]
3215 // CHECK5-NEXT:    [[TMP10:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_2]], align 8, !dbg [[DBG81]]
3216 // CHECK5-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG79]]
3217 // CHECK5-NEXT:    [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4, !dbg [[DBG79]]
3218 // CHECK5-NEXT:    call void @__kmpc_dispatch_init_8(ptr @[[GLOB25]], i32 [[TMP12]], i32 1073741862, i64 0, i64 [[TMP10]], i64 1, i64 1), !dbg [[DBG79]]
3219 // CHECK5-NEXT:    br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG79]]
3220 // CHECK5:       omp.dispatch.cond:
3221 // CHECK5-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG79]]
3222 // CHECK5-NEXT:    [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4, !dbg [[DBG79]]
3223 // CHECK5-NEXT:    [[TMP15:%.*]] = call i32 @__kmpc_dispatch_next_8(ptr @[[GLOB25]], i32 [[TMP14]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]]), !dbg [[DBG79]]
3224 // CHECK5-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0, !dbg [[DBG79]]
3225 // CHECK5-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG79]]
3226 // CHECK5:       omp.dispatch.body:
3227 // CHECK5-NEXT:    [[TMP16:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8, !dbg [[DBG80]]
3228 // CHECK5-NEXT:    store i64 [[TMP16]], ptr [[DOTOMP_IV]], align 8, !dbg [[DBG80]]
3229 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG79]]
3230 // CHECK5:       omp.inner.for.cond:
3231 // CHECK5-NEXT:    [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !dbg [[DBG80]], !llvm.access.group [[ACC_GRP82:![0-9]+]]
3232 // CHECK5-NEXT:    [[TMP18:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !dbg [[DBG80]], !llvm.access.group [[ACC_GRP82]]
3233 // CHECK5-NEXT:    [[CMP9:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]], !dbg [[DBG80]]
3234 // CHECK5-NEXT:    br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG79]]
3235 // CHECK5:       omp.inner.for.body:
3236 // CHECK5-NEXT:    [[TMP19:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1, !dbg [[DBG80]], !llvm.access.group [[ACC_GRP82]]
3237 // CHECK5-NEXT:    [[CONV10:%.*]] = sext i8 [[TMP19]] to i64, !dbg [[DBG80]]
3238 // CHECK5-NEXT:    [[TMP20:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !dbg [[DBG80]], !llvm.access.group [[ACC_GRP82]]
3239 // CHECK5-NEXT:    [[DIV11:%.*]] = sdiv i64 [[TMP20]], 11, !dbg [[DBG80]]
3240 // CHECK5-NEXT:    [[MUL12:%.*]] = mul nsw i64 [[DIV11]], 1, !dbg [[DBG80]]
3241 // CHECK5-NEXT:    [[ADD13:%.*]] = add nsw i64 [[CONV10]], [[MUL12]], !dbg [[DBG80]]
3242 // CHECK5-NEXT:    [[CONV14:%.*]] = trunc i64 [[ADD13]] to i8, !dbg [[DBG80]]
3243 // CHECK5-NEXT:    store i8 [[CONV14]], ptr [[I7]], align 1, !dbg [[DBG80]], !llvm.access.group [[ACC_GRP82]]
3244 // CHECK5-NEXT:    [[TMP21:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !dbg [[DBG80]], !llvm.access.group [[ACC_GRP82]]
3245 // CHECK5-NEXT:    [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !dbg [[DBG80]], !llvm.access.group [[ACC_GRP82]]
3246 // CHECK5-NEXT:    [[DIV15:%.*]] = sdiv i64 [[TMP22]], 11, !dbg [[DBG80]]
3247 // CHECK5-NEXT:    [[MUL16:%.*]] = mul nsw i64 [[DIV15]], 11, !dbg [[DBG80]]
3248 // CHECK5-NEXT:    [[SUB17:%.*]] = sub nsw i64 [[TMP21]], [[MUL16]], !dbg [[DBG80]]
3249 // CHECK5-NEXT:    [[MUL18:%.*]] = mul nsw i64 [[SUB17]], 1, !dbg [[DBG81]]
3250 // CHECK5-NEXT:    [[SUB19:%.*]] = sub nsw i64 11, [[MUL18]], !dbg [[DBG81]]
3251 // CHECK5-NEXT:    [[CONV20:%.*]] = trunc i64 [[SUB19]] to i32, !dbg [[DBG81]]
3252 // CHECK5-NEXT:    store i32 [[CONV20]], ptr [[X8]], align 4, !dbg [[DBG81]], !llvm.access.group [[ACC_GRP82]]
3253 // CHECK5-NEXT:    [[TMP23:%.*]] = load ptr, ptr [[TMP2]], align 8, !dbg [[DBG83:![0-9]+]], !llvm.access.group [[ACC_GRP82]]
3254 // CHECK5-NEXT:    [[TMP24:%.*]] = load i8, ptr [[I7]], align 1, !dbg [[DBG83]], !llvm.access.group [[ACC_GRP82]]
3255 // CHECK5-NEXT:    [[IDXPROM:%.*]] = sext i8 [[TMP24]] to i64, !dbg [[DBG83]]
3256 // CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP23]], i64 [[IDXPROM]], !dbg [[DBG83]]
3257 // CHECK5-NEXT:    [[TMP25:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !dbg [[DBG83]], !llvm.access.group [[ACC_GRP82]]
3258 // CHECK5-NEXT:    [[TMP26:%.*]] = load ptr, ptr [[TMP3]], align 8, !dbg [[DBG83]], !llvm.access.group [[ACC_GRP82]]
3259 // CHECK5-NEXT:    [[TMP27:%.*]] = load i8, ptr [[I7]], align 1, !dbg [[DBG83]], !llvm.access.group [[ACC_GRP82]]
3260 // CHECK5-NEXT:    [[IDXPROM21:%.*]] = sext i8 [[TMP27]] to i64, !dbg [[DBG83]]
3261 // CHECK5-NEXT:    [[ARRAYIDX22:%.*]] = getelementptr inbounds float, ptr [[TMP26]], i64 [[IDXPROM21]], !dbg [[DBG83]]
3262 // CHECK5-NEXT:    [[TMP28:%.*]] = load float, ptr [[ARRAYIDX22]], align 4, !dbg [[DBG83]], !llvm.access.group [[ACC_GRP82]]
3263 // CHECK5-NEXT:    [[MUL23:%.*]] = fmul float [[TMP25]], [[TMP28]], !dbg [[DBG83]]
3264 // CHECK5-NEXT:    [[TMP29:%.*]] = load ptr, ptr [[TMP4]], align 8, !dbg [[DBG83]], !llvm.access.group [[ACC_GRP82]]
3265 // CHECK5-NEXT:    [[TMP30:%.*]] = load i8, ptr [[I7]], align 1, !dbg [[DBG83]], !llvm.access.group [[ACC_GRP82]]
3266 // CHECK5-NEXT:    [[IDXPROM24:%.*]] = sext i8 [[TMP30]] to i64, !dbg [[DBG83]]
3267 // CHECK5-NEXT:    [[ARRAYIDX25:%.*]] = getelementptr inbounds float, ptr [[TMP29]], i64 [[IDXPROM24]], !dbg [[DBG83]]
3268 // CHECK5-NEXT:    [[TMP31:%.*]] = load float, ptr [[ARRAYIDX25]], align 4, !dbg [[DBG83]], !llvm.access.group [[ACC_GRP82]]
3269 // CHECK5-NEXT:    [[MUL26:%.*]] = fmul float [[MUL23]], [[TMP31]], !dbg [[DBG83]]
3270 // CHECK5-NEXT:    [[TMP32:%.*]] = load ptr, ptr [[TMP1]], align 8, !dbg [[DBG83]], !llvm.access.group [[ACC_GRP82]]
3271 // CHECK5-NEXT:    [[TMP33:%.*]] = load i8, ptr [[I7]], align 1, !dbg [[DBG83]], !llvm.access.group [[ACC_GRP82]]
3272 // CHECK5-NEXT:    [[IDXPROM27:%.*]] = sext i8 [[TMP33]] to i64, !dbg [[DBG83]]
3273 // CHECK5-NEXT:    [[ARRAYIDX28:%.*]] = getelementptr inbounds float, ptr [[TMP32]], i64 [[IDXPROM27]], !dbg [[DBG83]]
3274 // CHECK5-NEXT:    store float [[MUL26]], ptr [[ARRAYIDX28]], align 4, !dbg [[DBG83]], !llvm.access.group [[ACC_GRP82]]
3275 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG84:![0-9]+]]
3276 // CHECK5:       omp.body.continue:
3277 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG79]]
3278 // CHECK5:       omp.inner.for.inc:
3279 // CHECK5-NEXT:    [[TMP34:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !dbg [[DBG80]], !llvm.access.group [[ACC_GRP82]]
3280 // CHECK5-NEXT:    [[ADD29:%.*]] = add nsw i64 [[TMP34]], 1, !dbg [[DBG80]]
3281 // CHECK5-NEXT:    store i64 [[ADD29]], ptr [[DOTOMP_IV]], align 8, !dbg [[DBG80]], !llvm.access.group [[ACC_GRP82]]
3282 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]], !dbg [[DBG79]], !llvm.loop [[LOOP85:![0-9]+]]
3283 // CHECK5:       omp.inner.for.end:
3284 // CHECK5-NEXT:    br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG79]]
3285 // CHECK5:       omp.dispatch.inc:
3286 // CHECK5-NEXT:    br label [[OMP_DISPATCH_COND]], !dbg [[DBG79]], !llvm.loop [[LOOP87:![0-9]+]]
3287 // CHECK5:       omp.dispatch.end:
3288 // CHECK5-NEXT:    br label [[OMP_PRECOND_END]], !dbg [[DBG79]]
3289 // CHECK5:       omp.precond.end:
3290 // CHECK5-NEXT:    ret void, !dbg [[DBG84]]
3291 //
3292 //
3293 // CHECK5-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_
3294 // CHECK5-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] !dbg [[DBG88:![0-9]+]] {
3295 // CHECK5-NEXT:  entry:
3296 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
3297 // CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
3298 // CHECK5-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
3299 // CHECK5-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
3300 // CHECK5-NEXT:    [[X:%.*]] = alloca i32, align 4
3301 // CHECK5-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
3302 // CHECK5-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
3303 // CHECK5-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
3304 // CHECK5-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
3305 // CHECK5-NEXT:    store i32 0, ptr [[X]], align 4, !dbg [[DBG89:![0-9]+]]
3306 // CHECK5-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB27:[0-9]+]], i32 4, ptr @_Z7runtimePfS_S_S_.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]]), !dbg [[DBG90:![0-9]+]]
3307 // CHECK5-NEXT:    ret void, !dbg [[DBG91:![0-9]+]]
3308 //
3309 //
3310 // CHECK5-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_.omp_outlined
3311 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] !dbg [[DBG92:![0-9]+]] {
3312 // CHECK5-NEXT:  entry:
3313 // CHECK5-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
3314 // CHECK5-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
3315 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
3316 // CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
3317 // CHECK5-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
3318 // CHECK5-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
3319 // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
3320 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i8, align 1
3321 // CHECK5-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
3322 // CHECK5-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
3323 // CHECK5-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
3324 // CHECK5-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3325 // CHECK5-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3326 // CHECK5-NEXT:    [[I:%.*]] = alloca i8, align 1
3327 // CHECK5-NEXT:    [[X:%.*]] = alloca i32, align 4
3328 // CHECK5-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
3329 // CHECK5-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
3330 // CHECK5-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
3331 // CHECK5-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
3332 // CHECK5-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
3333 // CHECK5-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
3334 // CHECK5-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG93:![0-9]+]]
3335 // CHECK5-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !dbg [[DBG93]]
3336 // CHECK5-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8, !dbg [[DBG93]]
3337 // CHECK5-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8, !dbg [[DBG93]]
3338 // CHECK5-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG94:![0-9]+]]
3339 // CHECK5-NEXT:    store i32 199, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG94]]
3340 // CHECK5-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG94]]
3341 // CHECK5-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG94]]
3342 // CHECK5-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG93]]
3343 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4, !dbg [[DBG93]]
3344 // CHECK5-NEXT:    call void @__kmpc_dispatch_init_4(ptr @[[GLOB27]], i32 [[TMP5]], i32 1073741861, i32 0, i32 199, i32 1, i32 1), !dbg [[DBG93]]
3345 // CHECK5-NEXT:    br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG93]]
3346 // CHECK5:       omp.dispatch.cond:
3347 // CHECK5-NEXT:    [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB27]], i32 [[TMP5]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]]), !dbg [[DBG93]]
3348 // CHECK5-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0, !dbg [[DBG93]]
3349 // CHECK5-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG93]]
3350 // CHECK5:       omp.dispatch.body:
3351 // CHECK5-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG94]]
3352 // CHECK5-NEXT:    store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG94]]
3353 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG93]]
3354 // CHECK5:       omp.inner.for.cond:
3355 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG94]], !llvm.access.group [[ACC_GRP95:![0-9]+]]
3356 // CHECK5-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG94]], !llvm.access.group [[ACC_GRP95]]
3357 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]], !dbg [[DBG94]]
3358 // CHECK5-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG93]]
3359 // CHECK5:       omp.inner.for.body:
3360 // CHECK5-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG94]], !llvm.access.group [[ACC_GRP95]]
3361 // CHECK5-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP10]], 20, !dbg [[DBG94]]
3362 // CHECK5-NEXT:    [[MUL:%.*]] = mul nsw i32 [[DIV]], 1, !dbg [[DBG94]]
3363 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 48, [[MUL]], !dbg [[DBG94]]
3364 // CHECK5-NEXT:    [[CONV:%.*]] = trunc i32 [[ADD]] to i8, !dbg [[DBG94]]
3365 // CHECK5-NEXT:    store i8 [[CONV]], ptr [[I]], align 1, !dbg [[DBG94]], !llvm.access.group [[ACC_GRP95]]
3366 // CHECK5-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG94]], !llvm.access.group [[ACC_GRP95]]
3367 // CHECK5-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG94]], !llvm.access.group [[ACC_GRP95]]
3368 // CHECK5-NEXT:    [[DIV2:%.*]] = sdiv i32 [[TMP12]], 20, !dbg [[DBG94]]
3369 // CHECK5-NEXT:    [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 20, !dbg [[DBG94]]
3370 // CHECK5-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL3]], !dbg [[DBG94]]
3371 // CHECK5-NEXT:    [[MUL4:%.*]] = mul nsw i32 [[SUB]], 1, !dbg [[DBG96:![0-9]+]]
3372 // CHECK5-NEXT:    [[ADD5:%.*]] = add nsw i32 -10, [[MUL4]], !dbg [[DBG96]]
3373 // CHECK5-NEXT:    store i32 [[ADD5]], ptr [[X]], align 4, !dbg [[DBG96]], !llvm.access.group [[ACC_GRP95]]
3374 // CHECK5-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[TMP1]], align 8, !dbg [[DBG97:![0-9]+]], !llvm.access.group [[ACC_GRP95]]
3375 // CHECK5-NEXT:    [[TMP14:%.*]] = load i8, ptr [[I]], align 1, !dbg [[DBG97]], !llvm.access.group [[ACC_GRP95]]
3376 // CHECK5-NEXT:    [[IDXPROM:%.*]] = zext i8 [[TMP14]] to i64, !dbg [[DBG97]]
3377 // CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP13]], i64 [[IDXPROM]], !dbg [[DBG97]]
3378 // CHECK5-NEXT:    [[TMP15:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !dbg [[DBG97]], !llvm.access.group [[ACC_GRP95]]
3379 // CHECK5-NEXT:    [[TMP16:%.*]] = load ptr, ptr [[TMP2]], align 8, !dbg [[DBG97]], !llvm.access.group [[ACC_GRP95]]
3380 // CHECK5-NEXT:    [[TMP17:%.*]] = load i8, ptr [[I]], align 1, !dbg [[DBG97]], !llvm.access.group [[ACC_GRP95]]
3381 // CHECK5-NEXT:    [[IDXPROM6:%.*]] = zext i8 [[TMP17]] to i64, !dbg [[DBG97]]
3382 // CHECK5-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds float, ptr [[TMP16]], i64 [[IDXPROM6]], !dbg [[DBG97]]
3383 // CHECK5-NEXT:    [[TMP18:%.*]] = load float, ptr [[ARRAYIDX7]], align 4, !dbg [[DBG97]], !llvm.access.group [[ACC_GRP95]]
3384 // CHECK5-NEXT:    [[MUL8:%.*]] = fmul float [[TMP15]], [[TMP18]], !dbg [[DBG97]]
3385 // CHECK5-NEXT:    [[TMP19:%.*]] = load ptr, ptr [[TMP3]], align 8, !dbg [[DBG97]], !llvm.access.group [[ACC_GRP95]]
3386 // CHECK5-NEXT:    [[TMP20:%.*]] = load i8, ptr [[I]], align 1, !dbg [[DBG97]], !llvm.access.group [[ACC_GRP95]]
3387 // CHECK5-NEXT:    [[IDXPROM9:%.*]] = zext i8 [[TMP20]] to i64, !dbg [[DBG97]]
3388 // CHECK5-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP19]], i64 [[IDXPROM9]], !dbg [[DBG97]]
3389 // CHECK5-NEXT:    [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !dbg [[DBG97]], !llvm.access.group [[ACC_GRP95]]
3390 // CHECK5-NEXT:    [[MUL11:%.*]] = fmul float [[MUL8]], [[TMP21]], !dbg [[DBG97]]
3391 // CHECK5-NEXT:    [[TMP22:%.*]] = load ptr, ptr [[TMP0]], align 8, !dbg [[DBG97]], !llvm.access.group [[ACC_GRP95]]
3392 // CHECK5-NEXT:    [[TMP23:%.*]] = load i8, ptr [[I]], align 1, !dbg [[DBG97]], !llvm.access.group [[ACC_GRP95]]
3393 // CHECK5-NEXT:    [[IDXPROM12:%.*]] = zext i8 [[TMP23]] to i64, !dbg [[DBG97]]
3394 // CHECK5-NEXT:    [[ARRAYIDX13:%.*]] = getelementptr inbounds float, ptr [[TMP22]], i64 [[IDXPROM12]], !dbg [[DBG97]]
3395 // CHECK5-NEXT:    store float [[MUL11]], ptr [[ARRAYIDX13]], align 4, !dbg [[DBG97]], !llvm.access.group [[ACC_GRP95]]
3396 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG98:![0-9]+]]
3397 // CHECK5:       omp.body.continue:
3398 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG93]]
3399 // CHECK5:       omp.inner.for.inc:
3400 // CHECK5-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG94]], !llvm.access.group [[ACC_GRP95]]
3401 // CHECK5-NEXT:    [[ADD14:%.*]] = add nsw i32 [[TMP24]], 1, !dbg [[DBG94]]
3402 // CHECK5-NEXT:    store i32 [[ADD14]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG94]], !llvm.access.group [[ACC_GRP95]]
3403 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]], !dbg [[DBG93]], !llvm.loop [[LOOP99:![0-9]+]]
3404 // CHECK5:       omp.inner.for.end:
3405 // CHECK5-NEXT:    br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG93]]
3406 // CHECK5:       omp.dispatch.inc:
3407 // CHECK5-NEXT:    br label [[OMP_DISPATCH_COND]], !dbg [[DBG93]], !llvm.loop [[LOOP101:![0-9]+]]
3408 // CHECK5:       omp.dispatch.end:
3409 // CHECK5-NEXT:    ret void, !dbg [[DBG98]]
3410 //
3411 //
3412 // CHECK5-LABEL: define {{[^@]+}}@_Z3foov
3413 // CHECK5-SAME: () #[[ATTR3:[0-9]+]] !dbg [[DBG102:![0-9]+]] {
3414 // CHECK5-NEXT:  entry:
3415 // CHECK5-NEXT:    call void @_Z8mayThrowv(), !dbg [[DBG103:![0-9]+]]
3416 // CHECK5-NEXT:    ret i32 0, !dbg [[DBG103]]
3417 //
3418 //
3419 // CHECK5-LABEL: define {{[^@]+}}@_Z12parallel_forPfi
3420 // CHECK5-SAME: (ptr noundef [[A:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] !dbg [[DBG104:![0-9]+]] {
3421 // CHECK5-NEXT:  entry:
3422 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
3423 // CHECK5-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
3424 // CHECK5-NEXT:    [[SAVED_STACK:%.*]] = alloca ptr, align 8
3425 // CHECK5-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
3426 // CHECK5-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8
3427 // CHECK5-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
3428 // CHECK5-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
3429 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4, !dbg [[DBG105:![0-9]+]]
3430 // CHECK5-NEXT:    [[TMP1:%.*]] = zext i32 [[TMP0]] to i64, !dbg [[DBG105]]
3431 // CHECK5-NEXT:    [[TMP2:%.*]] = call ptr @llvm.stacksave.p0(), !dbg [[DBG105]]
3432 // CHECK5-NEXT:    store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8, !dbg [[DBG105]]
3433 // CHECK5-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 16, !dbg [[DBG105]]
3434 // CHECK5-NEXT:    store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8, !dbg [[DBG105]]
3435 // CHECK5-NEXT:    [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4, !dbg [[DBG106:![0-9]+]]
3436 // CHECK5-NEXT:    store i32 [[TMP3]], ptr [[N_CASTED]], align 4, !dbg [[DBG106]]
3437 // CHECK5-NEXT:    [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8, !dbg [[DBG106]]
3438 // CHECK5-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB32:[0-9]+]], i32 3, ptr @_Z12parallel_forPfi.omp_outlined, ptr [[A_ADDR]], i64 [[TMP1]], i64 [[TMP4]]), !dbg [[DBG106]]
3439 // CHECK5-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8, !dbg [[DBG107:![0-9]+]]
3440 // CHECK5-NEXT:    call void @llvm.stackrestore.p0(ptr [[TMP5]]), !dbg [[DBG107]]
3441 // CHECK5-NEXT:    ret void, !dbg [[DBG107]]
3442 //
3443 //
3444 // CHECK5-LABEL: define {{[^@]+}}@_Z12parallel_forPfi.omp_outlined
3445 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[N:%.*]]) #[[ATTR1]] personality ptr @__gxx_personality_v0 !dbg [[DBG108:![0-9]+]] {
3446 // CHECK5-NEXT:  entry:
3447 // CHECK5-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
3448 // CHECK5-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
3449 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
3450 // CHECK5-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
3451 // CHECK5-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
3452 // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
3453 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4
3454 // CHECK5-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
3455 // CHECK5-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
3456 // CHECK5-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3457 // CHECK5-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3458 // CHECK5-NEXT:    [[SAVED_STACK:%.*]] = alloca ptr, align 8
3459 // CHECK5-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
3460 // CHECK5-NEXT:    [[I:%.*]] = alloca i32, align 4
3461 // CHECK5-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
3462 // CHECK5-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
3463 // CHECK5-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
3464 // CHECK5-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
3465 // CHECK5-NEXT:    store i64 [[N]], ptr [[N_ADDR]], align 8
3466 // CHECK5-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8, !dbg [[DBG109:![0-9]+]]
3467 // CHECK5-NEXT:    [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8, !dbg [[DBG109]]
3468 // CHECK5-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG110:![0-9]+]]
3469 // CHECK5-NEXT:    store i32 16908288, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG110]]
3470 // CHECK5-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG110]]
3471 // CHECK5-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG110]]
3472 // CHECK5-NEXT:    [[TMP2:%.*]] = call ptr @llvm.stacksave.p0(), !dbg [[DBG109]]
3473 // CHECK5-NEXT:    store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8, !dbg [[DBG109]]
3474 // CHECK5-NEXT:    [[VLA1:%.*]] = alloca float, i64 [[TMP1]], align 16, !dbg [[DBG109]]
3475 // CHECK5-NEXT:    store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8, !dbg [[DBG109]]
3476 // CHECK5-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG109]]
3477 // CHECK5-NEXT:    [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4, !dbg [[DBG109]]
3478 // CHECK5-NEXT:    call void @__kmpc_for_static_init_4u(ptr @[[GLOB29:[0-9]+]], i32 [[TMP4]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 5), !dbg [[DBG109]]
3479 // CHECK5-NEXT:    br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG109]]
3480 // CHECK5:       omp.dispatch.cond:
3481 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG110]]
3482 // CHECK5-NEXT:    [[CMP:%.*]] = icmp ugt i32 [[TMP5]], 16908288, !dbg [[DBG110]]
3483 // CHECK5-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]], !dbg [[DBG110]]
3484 // CHECK5:       cond.true:
3485 // CHECK5-NEXT:    br label [[COND_END:%.*]], !dbg [[DBG110]]
3486 // CHECK5:       cond.false:
3487 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG110]]
3488 // CHECK5-NEXT:    br label [[COND_END]], !dbg [[DBG110]]
3489 // CHECK5:       cond.end:
3490 // CHECK5-NEXT:    [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ], !dbg [[DBG110]]
3491 // CHECK5-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4, !dbg [[DBG110]]
3492 // CHECK5-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG110]]
3493 // CHECK5-NEXT:    store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG110]]
3494 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG110]]
3495 // CHECK5-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG110]]
3496 // CHECK5-NEXT:    [[CMP2:%.*]] = icmp ule i32 [[TMP8]], [[TMP9]], !dbg [[DBG110]]
3497 // CHECK5-NEXT:    br i1 [[CMP2]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_CLEANUP:%.*]], !dbg [[DBG109]]
3498 // CHECK5:       omp.dispatch.cleanup:
3499 // CHECK5-NEXT:    br label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG109]]
3500 // CHECK5:       omp.dispatch.body:
3501 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG109]]
3502 // CHECK5:       omp.inner.for.cond:
3503 // CHECK5-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG110]]
3504 // CHECK5-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG110]]
3505 // CHECK5-NEXT:    [[CMP3:%.*]] = icmp ule i32 [[TMP10]], [[TMP11]], !dbg [[DBG110]]
3506 // CHECK5-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]], !dbg [[DBG109]]
3507 // CHECK5:       omp.inner.for.cond.cleanup:
3508 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG109]]
3509 // CHECK5:       omp.inner.for.body:
3510 // CHECK5-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG110]]
3511 // CHECK5-NEXT:    [[MUL:%.*]] = mul i32 [[TMP12]], 127, !dbg [[DBG110]]
3512 // CHECK5-NEXT:    [[ADD:%.*]] = add i32 131071, [[MUL]], !dbg [[DBG110]]
3513 // CHECK5-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !dbg [[DBG110]]
3514 // CHECK5-NEXT:    [[CALL:%.*]] = invoke noundef i32 @_Z3foov()
3515 // CHECK5-NEXT:    to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !dbg [[DBG111:![0-9]+]]
3516 // CHECK5:       invoke.cont:
3517 // CHECK5-NEXT:    [[CONV:%.*]] = sitofp i32 [[CALL]] to float, !dbg [[DBG111]]
3518 // CHECK5-NEXT:    [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !dbg [[DBG111]]
3519 // CHECK5-NEXT:    [[IDXPROM:%.*]] = zext i32 [[TMP13]] to i64, !dbg [[DBG111]]
3520 // CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[VLA1]], i64 [[IDXPROM]], !dbg [[DBG111]]
3521 // CHECK5-NEXT:    [[TMP14:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !dbg [[DBG111]]
3522 // CHECK5-NEXT:    [[ADD4:%.*]] = fadd float [[CONV]], [[TMP14]], !dbg [[DBG111]]
3523 // CHECK5-NEXT:    [[TMP15:%.*]] = load i32, ptr [[N_ADDR]], align 4, !dbg [[DBG111]]
3524 // CHECK5-NEXT:    [[CONV5:%.*]] = sitofp i32 [[TMP15]] to float, !dbg [[DBG111]]
3525 // CHECK5-NEXT:    [[ADD6:%.*]] = fadd float [[ADD4]], [[CONV5]], !dbg [[DBG111]]
3526 // CHECK5-NEXT:    [[TMP16:%.*]] = load ptr, ptr [[TMP0]], align 8, !dbg [[DBG111]]
3527 // CHECK5-NEXT:    [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !dbg [[DBG111]]
3528 // CHECK5-NEXT:    [[IDXPROM7:%.*]] = zext i32 [[TMP17]] to i64, !dbg [[DBG111]]
3529 // CHECK5-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds float, ptr [[TMP16]], i64 [[IDXPROM7]], !dbg [[DBG111]]
3530 // CHECK5-NEXT:    [[TMP18:%.*]] = load float, ptr [[ARRAYIDX8]], align 4, !dbg [[DBG111]]
3531 // CHECK5-NEXT:    [[ADD9:%.*]] = fadd float [[TMP18]], [[ADD6]], !dbg [[DBG111]]
3532 // CHECK5-NEXT:    store float [[ADD9]], ptr [[ARRAYIDX8]], align 4, !dbg [[DBG111]]
3533 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG111]]
3534 // CHECK5:       omp.body.continue:
3535 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG109]]
3536 // CHECK5:       omp.inner.for.inc:
3537 // CHECK5-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !dbg [[DBG110]]
3538 // CHECK5-NEXT:    [[ADD10:%.*]] = add i32 [[TMP19]], 1, !dbg [[DBG110]]
3539 // CHECK5-NEXT:    store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4, !dbg [[DBG110]]
3540 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]], !dbg [[DBG109]], !llvm.loop [[LOOP112:![0-9]+]]
3541 // CHECK5:       omp.inner.for.end:
3542 // CHECK5-NEXT:    br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG109]]
3543 // CHECK5:       omp.dispatch.inc:
3544 // CHECK5-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4, !dbg [[DBG110]]
3545 // CHECK5-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG110]]
3546 // CHECK5-NEXT:    [[ADD11:%.*]] = add i32 [[TMP20]], [[TMP21]], !dbg [[DBG110]]
3547 // CHECK5-NEXT:    store i32 [[ADD11]], ptr [[DOTOMP_LB]], align 4, !dbg [[DBG110]]
3548 // CHECK5-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !dbg [[DBG110]]
3549 // CHECK5-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !dbg [[DBG110]]
3550 // CHECK5-NEXT:    [[ADD12:%.*]] = add i32 [[TMP22]], [[TMP23]], !dbg [[DBG110]]
3551 // CHECK5-NEXT:    store i32 [[ADD12]], ptr [[DOTOMP_UB]], align 4, !dbg [[DBG110]]
3552 // CHECK5-NEXT:    br label [[OMP_DISPATCH_COND]], !dbg [[DBG109]], !llvm.loop [[LOOP113:![0-9]+]]
3553 // CHECK5:       omp.dispatch.end:
3554 // CHECK5-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB31:[0-9]+]], i32 [[TMP4]]), !dbg [[DBG109]]
3555 // CHECK5-NEXT:    [[TMP24:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8, !dbg [[DBG109]]
3556 // CHECK5-NEXT:    call void @llvm.stackrestore.p0(ptr [[TMP24]]), !dbg [[DBG109]]
3557 // CHECK5-NEXT:    ret void, !dbg [[DBG111]]
3558 // CHECK5:       terminate.lpad:
3559 // CHECK5-NEXT:    [[TMP25:%.*]] = landingpad { ptr, i32 }
3560 // CHECK5-NEXT:    catch ptr null, !dbg [[DBG111]]
3561 // CHECK5-NEXT:    [[TMP26:%.*]] = extractvalue { ptr, i32 } [[TMP25]], 0, !dbg [[DBG111]]
3562 // CHECK5-NEXT:    call void @__clang_call_terminate(ptr [[TMP26]]) #[[ATTR7:[0-9]+]], !dbg [[DBG111]]
3563 // CHECK5-NEXT:    unreachable, !dbg [[DBG111]]
3564 //
3565 //
3566 // CHECK5-LABEL: define {{[^@]+}}@__clang_call_terminate
3567 // CHECK5-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR6:[0-9]+]] {
3568 // CHECK5-NEXT:    [[TMP2:%.*]] = call ptr @__cxa_begin_catch(ptr [[TMP0]]) #[[ATTR2:[0-9]+]]
3569 // CHECK5-NEXT:    call void @_ZSt9terminatev() #[[ATTR7]]
3570 // CHECK5-NEXT:    unreachable
3571 //
3572 //
3573 // CHECK6-LABEL: define {{[^@]+}}@_Z17with_var_schedulev
3574 // CHECK6-SAME: () #[[ATTR0:[0-9]+]] {
3575 // CHECK6-NEXT:  entry:
3576 // CHECK6-NEXT:    [[A:%.*]] = alloca double, align 8
3577 // CHECK6-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
3578 // CHECK6-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
3579 // CHECK6-NEXT:    store double 5.000000e+00, ptr [[A]], align 8
3580 // CHECK6-NEXT:    [[TMP0:%.*]] = load double, ptr [[A]], align 8
3581 // CHECK6-NEXT:    [[CONV:%.*]] = fptosi double [[TMP0]] to i8
3582 // CHECK6-NEXT:    store i8 [[CONV]], ptr [[DOTCAPTURE_EXPR_]], align 1
3583 // CHECK6-NEXT:    [[TMP1:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
3584 // CHECK6-NEXT:    store i8 [[TMP1]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1
3585 // CHECK6-NEXT:    [[TMP2:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8
3586 // CHECK6-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2:[0-9]+]], i32 1, ptr @_Z17with_var_schedulev.omp_outlined, i64 [[TMP2]])
3587 // CHECK6-NEXT:    ret void
3588 //
3589 //
3590 // CHECK6-LABEL: define {{[^@]+}}@_Z17with_var_schedulev.omp_outlined
3591 // CHECK6-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] {
3592 // CHECK6-NEXT:  entry:
3593 // CHECK6-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
3594 // CHECK6-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
3595 // CHECK6-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
3596 // CHECK6-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
3597 // CHECK6-NEXT:    [[TMP:%.*]] = alloca i64, align 8
3598 // CHECK6-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca double, align 8
3599 // CHECK6-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 8
3600 // CHECK6-NEXT:    [[I:%.*]] = alloca i64, align 8
3601 // CHECK6-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
3602 // CHECK6-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
3603 // CHECK6-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
3604 // CHECK6-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3605 // CHECK6-NEXT:    [[A:%.*]] = alloca double, align 8
3606 // CHECK6-NEXT:    [[I4:%.*]] = alloca i64, align 8
3607 // CHECK6-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
3608 // CHECK6-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
3609 // CHECK6-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
3610 // CHECK6-NEXT:    [[TMP0:%.*]] = load double, ptr undef, align 8
3611 // CHECK6-NEXT:    [[ADD:%.*]] = fadd double 2.000000e+00, [[TMP0]]
3612 // CHECK6-NEXT:    store double [[ADD]], ptr [[DOTCAPTURE_EXPR_1]], align 8
3613 // CHECK6-NEXT:    [[TMP1:%.*]] = load double, ptr [[DOTCAPTURE_EXPR_1]], align 8
3614 // CHECK6-NEXT:    [[SUB:%.*]] = fsub double [[TMP1]], 1.000000e+00
3615 // CHECK6-NEXT:    [[DIV:%.*]] = fdiv double [[SUB]], 1.000000e+00
3616 // CHECK6-NEXT:    [[CONV:%.*]] = fptoui double [[DIV]] to i64
3617 // CHECK6-NEXT:    [[SUB3:%.*]] = sub i64 [[CONV]], 1
3618 // CHECK6-NEXT:    store i64 [[SUB3]], ptr [[DOTCAPTURE_EXPR_2]], align 8
3619 // CHECK6-NEXT:    store i64 1, ptr [[I]], align 8
3620 // CHECK6-NEXT:    [[TMP2:%.*]] = load double, ptr [[DOTCAPTURE_EXPR_1]], align 8
3621 // CHECK6-NEXT:    [[CMP:%.*]] = fcmp olt double 1.000000e+00, [[TMP2]]
3622 // CHECK6-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
3623 // CHECK6:       omp.precond.then:
3624 // CHECK6-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8
3625 // CHECK6-NEXT:    [[TMP3:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_2]], align 8
3626 // CHECK6-NEXT:    store i64 [[TMP3]], ptr [[DOTOMP_UB]], align 8
3627 // CHECK6-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8
3628 // CHECK6-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
3629 // CHECK6-NEXT:    [[TMP4:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1
3630 // CHECK6-NEXT:    [[CONV5:%.*]] = sext i8 [[TMP4]] to i64
3631 // CHECK6-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
3632 // CHECK6-NEXT:    [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
3633 // CHECK6-NEXT:    call void @__kmpc_for_static_init_8u(ptr @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 [[CONV5]])
3634 // CHECK6-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
3635 // CHECK6:       omp.dispatch.cond:
3636 // CHECK6-NEXT:    [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
3637 // CHECK6-NEXT:    [[TMP8:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_2]], align 8
3638 // CHECK6-NEXT:    [[CMP6:%.*]] = icmp ugt i64 [[TMP7]], [[TMP8]]
3639 // CHECK6-NEXT:    br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3640 // CHECK6:       cond.true:
3641 // CHECK6-NEXT:    [[TMP9:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_2]], align 8
3642 // CHECK6-NEXT:    br label [[COND_END:%.*]]
3643 // CHECK6:       cond.false:
3644 // CHECK6-NEXT:    [[TMP10:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
3645 // CHECK6-NEXT:    br label [[COND_END]]
3646 // CHECK6:       cond.end:
3647 // CHECK6-NEXT:    [[COND:%.*]] = phi i64 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
3648 // CHECK6-NEXT:    store i64 [[COND]], ptr [[DOTOMP_UB]], align 8
3649 // CHECK6-NEXT:    [[TMP11:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
3650 // CHECK6-NEXT:    store i64 [[TMP11]], ptr [[DOTOMP_IV]], align 8
3651 // CHECK6-NEXT:    [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
3652 // CHECK6-NEXT:    [[TMP13:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
3653 // CHECK6-NEXT:    [[ADD7:%.*]] = add i64 [[TMP13]], 1
3654 // CHECK6-NEXT:    [[CMP8:%.*]] = icmp ult i64 [[TMP12]], [[ADD7]]
3655 // CHECK6-NEXT:    br i1 [[CMP8]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
3656 // CHECK6:       omp.dispatch.body:
3657 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
3658 // CHECK6:       omp.inner.for.cond:
3659 // CHECK6-NEXT:    [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
3660 // CHECK6-NEXT:    [[TMP15:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
3661 // CHECK6-NEXT:    [[ADD9:%.*]] = add i64 [[TMP15]], 1
3662 // CHECK6-NEXT:    [[CMP10:%.*]] = icmp ult i64 [[TMP14]], [[ADD9]]
3663 // CHECK6-NEXT:    br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3664 // CHECK6:       omp.inner.for.body:
3665 // CHECK6-NEXT:    [[TMP16:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
3666 // CHECK6-NEXT:    [[MUL:%.*]] = mul i64 [[TMP16]], 1
3667 // CHECK6-NEXT:    [[ADD11:%.*]] = add i64 1, [[MUL]]
3668 // CHECK6-NEXT:    store i64 [[ADD11]], ptr [[I4]], align 8
3669 // CHECK6-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
3670 // CHECK6:       omp.body.continue:
3671 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
3672 // CHECK6:       omp.inner.for.inc:
3673 // CHECK6-NEXT:    [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
3674 // CHECK6-NEXT:    [[ADD12:%.*]] = add i64 [[TMP17]], 1
3675 // CHECK6-NEXT:    store i64 [[ADD12]], ptr [[DOTOMP_IV]], align 8
3676 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_COND]]
3677 // CHECK6:       omp.inner.for.end:
3678 // CHECK6-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
3679 // CHECK6:       omp.dispatch.inc:
3680 // CHECK6-NEXT:    [[TMP18:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
3681 // CHECK6-NEXT:    [[TMP19:%.*]] = load i64, ptr [[DOTOMP_STRIDE]], align 8
3682 // CHECK6-NEXT:    [[ADD13:%.*]] = add i64 [[TMP18]], [[TMP19]]
3683 // CHECK6-NEXT:    store i64 [[ADD13]], ptr [[DOTOMP_LB]], align 8
3684 // CHECK6-NEXT:    [[TMP20:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
3685 // CHECK6-NEXT:    [[TMP21:%.*]] = load i64, ptr [[DOTOMP_STRIDE]], align 8
3686 // CHECK6-NEXT:    [[ADD14:%.*]] = add i64 [[TMP20]], [[TMP21]]
3687 // CHECK6-NEXT:    store i64 [[ADD14]], ptr [[DOTOMP_UB]], align 8
3688 // CHECK6-NEXT:    br label [[OMP_DISPATCH_COND]]
3689 // CHECK6:       omp.dispatch.end:
3690 // CHECK6-NEXT:    [[TMP22:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
3691 // CHECK6-NEXT:    [[TMP23:%.*]] = load i32, ptr [[TMP22]], align 4
3692 // CHECK6-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP23]])
3693 // CHECK6-NEXT:    br label [[OMP_PRECOND_END]]
3694 // CHECK6:       omp.precond.end:
3695 // CHECK6-NEXT:    ret void
3696 //
3697 //
3698 // CHECK6-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_
3699 // CHECK6-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
3700 // CHECK6-NEXT:  entry:
3701 // CHECK6-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
3702 // CHECK6-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
3703 // CHECK6-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
3704 // CHECK6-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
3705 // CHECK6-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
3706 // CHECK6-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
3707 // CHECK6-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
3708 // CHECK6-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
3709 // CHECK6-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @_Z23without_schedule_clausePfS_S_S_.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])
3710 // CHECK6-NEXT:    ret void
3711 //
3712 //
3713 // CHECK6-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_.omp_outlined
3714 // CHECK6-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] {
3715 // CHECK6-NEXT:  entry:
3716 // CHECK6-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
3717 // CHECK6-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
3718 // CHECK6-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
3719 // CHECK6-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
3720 // CHECK6-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
3721 // CHECK6-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
3722 // CHECK6-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
3723 // CHECK6-NEXT:    [[TMP:%.*]] = alloca i32, align 4
3724 // CHECK6-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
3725 // CHECK6-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
3726 // CHECK6-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3727 // CHECK6-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3728 // CHECK6-NEXT:    [[I:%.*]] = alloca i32, align 4
3729 // CHECK6-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
3730 // CHECK6-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
3731 // CHECK6-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
3732 // CHECK6-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
3733 // CHECK6-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
3734 // CHECK6-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
3735 // CHECK6-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
3736 // CHECK6-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
3737 // CHECK6-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8
3738 // CHECK6-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8
3739 // CHECK6-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
3740 // CHECK6-NEXT:    store i32 4571423, ptr [[DOTOMP_UB]], align 4
3741 // CHECK6-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
3742 // CHECK6-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
3743 // CHECK6-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
3744 // CHECK6-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
3745 // CHECK6-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
3746 // CHECK6-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
3747 // CHECK6-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423
3748 // CHECK6-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3749 // CHECK6:       cond.true:
3750 // CHECK6-NEXT:    br label [[COND_END:%.*]]
3751 // CHECK6:       cond.false:
3752 // CHECK6-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
3753 // CHECK6-NEXT:    br label [[COND_END]]
3754 // CHECK6:       cond.end:
3755 // CHECK6-NEXT:    [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
3756 // CHECK6-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
3757 // CHECK6-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
3758 // CHECK6-NEXT:    store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4
3759 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
3760 // CHECK6:       omp.inner.for.cond:
3761 // CHECK6-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3762 // CHECK6-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
3763 // CHECK6-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
3764 // CHECK6-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3765 // CHECK6:       omp.inner.for.body:
3766 // CHECK6-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3767 // CHECK6-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7
3768 // CHECK6-NEXT:    [[ADD:%.*]] = add nsw i32 33, [[MUL]]
3769 // CHECK6-NEXT:    store i32 [[ADD]], ptr [[I]], align 4
3770 // CHECK6-NEXT:    [[TMP12:%.*]] = load ptr, ptr [[TMP1]], align 8
3771 // CHECK6-NEXT:    [[TMP13:%.*]] = load i32, ptr [[I]], align 4
3772 // CHECK6-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64
3773 // CHECK6-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP12]], i64 [[IDXPROM]]
3774 // CHECK6-NEXT:    [[TMP14:%.*]] = load float, ptr [[ARRAYIDX]], align 4
3775 // CHECK6-NEXT:    [[TMP15:%.*]] = load ptr, ptr [[TMP2]], align 8
3776 // CHECK6-NEXT:    [[TMP16:%.*]] = load i32, ptr [[I]], align 4
3777 // CHECK6-NEXT:    [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64
3778 // CHECK6-NEXT:    [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP15]], i64 [[IDXPROM2]]
3779 // CHECK6-NEXT:    [[TMP17:%.*]] = load float, ptr [[ARRAYIDX3]], align 4
3780 // CHECK6-NEXT:    [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]]
3781 // CHECK6-NEXT:    [[TMP18:%.*]] = load ptr, ptr [[TMP3]], align 8
3782 // CHECK6-NEXT:    [[TMP19:%.*]] = load i32, ptr [[I]], align 4
3783 // CHECK6-NEXT:    [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64
3784 // CHECK6-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP18]], i64 [[IDXPROM5]]
3785 // CHECK6-NEXT:    [[TMP20:%.*]] = load float, ptr [[ARRAYIDX6]], align 4
3786 // CHECK6-NEXT:    [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]]
3787 // CHECK6-NEXT:    [[TMP21:%.*]] = load ptr, ptr [[TMP0]], align 8
3788 // CHECK6-NEXT:    [[TMP22:%.*]] = load i32, ptr [[I]], align 4
3789 // CHECK6-NEXT:    [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64
3790 // CHECK6-NEXT:    [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP21]], i64 [[IDXPROM8]]
3791 // CHECK6-NEXT:    store float [[MUL7]], ptr [[ARRAYIDX9]], align 4
3792 // CHECK6-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
3793 // CHECK6:       omp.body.continue:
3794 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
3795 // CHECK6:       omp.inner.for.inc:
3796 // CHECK6-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3797 // CHECK6-NEXT:    [[ADD10:%.*]] = add nsw i32 [[TMP23]], 1
3798 // CHECK6-NEXT:    store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4
3799 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_COND]]
3800 // CHECK6:       omp.inner.for.end:
3801 // CHECK6-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
3802 // CHECK6:       omp.loop.exit:
3803 // CHECK6-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])
3804 // CHECK6-NEXT:    ret void
3805 //
3806 //
3807 // CHECK6-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_
3808 // CHECK6-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
3809 // CHECK6-NEXT:  entry:
3810 // CHECK6-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
3811 // CHECK6-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
3812 // CHECK6-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
3813 // CHECK6-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
3814 // CHECK6-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
3815 // CHECK6-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
3816 // CHECK6-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
3817 // CHECK6-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
3818 // CHECK6-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @_Z18static_not_chunkedPfS_S_S_.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])
3819 // CHECK6-NEXT:    ret void
3820 //
3821 //
3822 // CHECK6-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_.omp_outlined
3823 // CHECK6-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] {
3824 // CHECK6-NEXT:  entry:
3825 // CHECK6-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
3826 // CHECK6-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
3827 // CHECK6-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
3828 // CHECK6-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
3829 // CHECK6-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
3830 // CHECK6-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
3831 // CHECK6-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
3832 // CHECK6-NEXT:    [[TMP:%.*]] = alloca i32, align 4
3833 // CHECK6-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
3834 // CHECK6-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
3835 // CHECK6-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3836 // CHECK6-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3837 // CHECK6-NEXT:    [[I:%.*]] = alloca i32, align 4
3838 // CHECK6-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
3839 // CHECK6-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
3840 // CHECK6-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
3841 // CHECK6-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
3842 // CHECK6-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
3843 // CHECK6-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
3844 // CHECK6-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
3845 // CHECK6-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
3846 // CHECK6-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8
3847 // CHECK6-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8
3848 // CHECK6-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
3849 // CHECK6-NEXT:    store i32 4571423, ptr [[DOTOMP_UB]], align 4
3850 // CHECK6-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
3851 // CHECK6-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
3852 // CHECK6-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
3853 // CHECK6-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
3854 // CHECK6-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
3855 // CHECK6-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
3856 // CHECK6-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423
3857 // CHECK6-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3858 // CHECK6:       cond.true:
3859 // CHECK6-NEXT:    br label [[COND_END:%.*]]
3860 // CHECK6:       cond.false:
3861 // CHECK6-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
3862 // CHECK6-NEXT:    br label [[COND_END]]
3863 // CHECK6:       cond.end:
3864 // CHECK6-NEXT:    [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
3865 // CHECK6-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
3866 // CHECK6-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
3867 // CHECK6-NEXT:    store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4
3868 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
3869 // CHECK6:       omp.inner.for.cond:
3870 // CHECK6-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3871 // CHECK6-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
3872 // CHECK6-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
3873 // CHECK6-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3874 // CHECK6:       omp.inner.for.body:
3875 // CHECK6-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3876 // CHECK6-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7
3877 // CHECK6-NEXT:    [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]]
3878 // CHECK6-NEXT:    store i32 [[SUB]], ptr [[I]], align 4
3879 // CHECK6-NEXT:    [[TMP12:%.*]] = load ptr, ptr [[TMP1]], align 8
3880 // CHECK6-NEXT:    [[TMP13:%.*]] = load i32, ptr [[I]], align 4
3881 // CHECK6-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64
3882 // CHECK6-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP12]], i64 [[IDXPROM]]
3883 // CHECK6-NEXT:    [[TMP14:%.*]] = load float, ptr [[ARRAYIDX]], align 4
3884 // CHECK6-NEXT:    [[TMP15:%.*]] = load ptr, ptr [[TMP2]], align 8
3885 // CHECK6-NEXT:    [[TMP16:%.*]] = load i32, ptr [[I]], align 4
3886 // CHECK6-NEXT:    [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64
3887 // CHECK6-NEXT:    [[ARRAYIDX3:%.*]] = getelementptr inbounds float, ptr [[TMP15]], i64 [[IDXPROM2]]
3888 // CHECK6-NEXT:    [[TMP17:%.*]] = load float, ptr [[ARRAYIDX3]], align 4
3889 // CHECK6-NEXT:    [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]]
3890 // CHECK6-NEXT:    [[TMP18:%.*]] = load ptr, ptr [[TMP3]], align 8
3891 // CHECK6-NEXT:    [[TMP19:%.*]] = load i32, ptr [[I]], align 4
3892 // CHECK6-NEXT:    [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64
3893 // CHECK6-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP18]], i64 [[IDXPROM5]]
3894 // CHECK6-NEXT:    [[TMP20:%.*]] = load float, ptr [[ARRAYIDX6]], align 4
3895 // CHECK6-NEXT:    [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]]
3896 // CHECK6-NEXT:    [[TMP21:%.*]] = load ptr, ptr [[TMP0]], align 8
3897 // CHECK6-NEXT:    [[TMP22:%.*]] = load i32, ptr [[I]], align 4
3898 // CHECK6-NEXT:    [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64
3899 // CHECK6-NEXT:    [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP21]], i64 [[IDXPROM8]]
3900 // CHECK6-NEXT:    store float [[MUL7]], ptr [[ARRAYIDX9]], align 4
3901 // CHECK6-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
3902 // CHECK6:       omp.body.continue:
3903 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
3904 // CHECK6:       omp.inner.for.inc:
3905 // CHECK6-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3906 // CHECK6-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP23]], 1
3907 // CHECK6-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
3908 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_COND]]
3909 // CHECK6:       omp.inner.for.end:
3910 // CHECK6-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
3911 // CHECK6:       omp.loop.exit:
3912 // CHECK6-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])
3913 // CHECK6-NEXT:    ret void
3914 //
3915 //
3916 // CHECK6-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_
3917 // CHECK6-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
3918 // CHECK6-NEXT:  entry:
3919 // CHECK6-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
3920 // CHECK6-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
3921 // CHECK6-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
3922 // CHECK6-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
3923 // CHECK6-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
3924 // CHECK6-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
3925 // CHECK6-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
3926 // CHECK6-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
3927 // CHECK6-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @_Z14static_chunkedPfS_S_S_.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])
3928 // CHECK6-NEXT:    ret void
3929 //
3930 //
3931 // CHECK6-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_.omp_outlined
3932 // CHECK6-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] {
3933 // CHECK6-NEXT:  entry:
3934 // CHECK6-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
3935 // CHECK6-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
3936 // CHECK6-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
3937 // CHECK6-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
3938 // CHECK6-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
3939 // CHECK6-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
3940 // CHECK6-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
3941 // CHECK6-NEXT:    [[TMP:%.*]] = alloca i32, align 4
3942 // CHECK6-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
3943 // CHECK6-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
3944 // CHECK6-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3945 // CHECK6-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3946 // CHECK6-NEXT:    [[I:%.*]] = alloca i32, align 4
3947 // CHECK6-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
3948 // CHECK6-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
3949 // CHECK6-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
3950 // CHECK6-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
3951 // CHECK6-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
3952 // CHECK6-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
3953 // CHECK6-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
3954 // CHECK6-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
3955 // CHECK6-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8
3956 // CHECK6-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8
3957 // CHECK6-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
3958 // CHECK6-NEXT:    store i32 16908288, ptr [[DOTOMP_UB]], align 4
3959 // CHECK6-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
3960 // CHECK6-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
3961 // CHECK6-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
3962 // CHECK6-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
3963 // CHECK6-NEXT:    call void @__kmpc_for_static_init_4u(ptr @[[GLOB1]], i32 [[TMP5]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 5)
3964 // CHECK6-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
3965 // CHECK6:       omp.dispatch.cond:
3966 // CHECK6-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
3967 // CHECK6-NEXT:    [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288
3968 // CHECK6-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3969 // CHECK6:       cond.true:
3970 // CHECK6-NEXT:    br label [[COND_END:%.*]]
3971 // CHECK6:       cond.false:
3972 // CHECK6-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
3973 // CHECK6-NEXT:    br label [[COND_END]]
3974 // CHECK6:       cond.end:
3975 // CHECK6-NEXT:    [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
3976 // CHECK6-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
3977 // CHECK6-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
3978 // CHECK6-NEXT:    store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4
3979 // CHECK6-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3980 // CHECK6-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
3981 // CHECK6-NEXT:    [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]]
3982 // CHECK6-NEXT:    br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
3983 // CHECK6:       omp.dispatch.body:
3984 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
3985 // CHECK6:       omp.inner.for.cond:
3986 // CHECK6-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3987 // CHECK6-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
3988 // CHECK6-NEXT:    [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]]
3989 // CHECK6-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3990 // CHECK6:       omp.inner.for.body:
3991 // CHECK6-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3992 // CHECK6-NEXT:    [[MUL:%.*]] = mul i32 [[TMP13]], 127
3993 // CHECK6-NEXT:    [[ADD:%.*]] = add i32 131071, [[MUL]]
3994 // CHECK6-NEXT:    store i32 [[ADD]], ptr [[I]], align 4
3995 // CHECK6-NEXT:    [[TMP14:%.*]] = load ptr, ptr [[TMP1]], align 8
3996 // CHECK6-NEXT:    [[TMP15:%.*]] = load i32, ptr [[I]], align 4
3997 // CHECK6-NEXT:    [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64
3998 // CHECK6-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP14]], i64 [[IDXPROM]]
3999 // CHECK6-NEXT:    [[TMP16:%.*]] = load float, ptr [[ARRAYIDX]], align 4
4000 // CHECK6-NEXT:    [[TMP17:%.*]] = load ptr, ptr [[TMP2]], align 8
4001 // CHECK6-NEXT:    [[TMP18:%.*]] = load i32, ptr [[I]], align 4
4002 // CHECK6-NEXT:    [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64
4003 // CHECK6-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds float, ptr [[TMP17]], i64 [[IDXPROM3]]
4004 // CHECK6-NEXT:    [[TMP19:%.*]] = load float, ptr [[ARRAYIDX4]], align 4
4005 // CHECK6-NEXT:    [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]]
4006 // CHECK6-NEXT:    [[TMP20:%.*]] = load ptr, ptr [[TMP3]], align 8
4007 // CHECK6-NEXT:    [[TMP21:%.*]] = load i32, ptr [[I]], align 4
4008 // CHECK6-NEXT:    [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64
4009 // CHECK6-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds float, ptr [[TMP20]], i64 [[IDXPROM6]]
4010 // CHECK6-NEXT:    [[TMP22:%.*]] = load float, ptr [[ARRAYIDX7]], align 4
4011 // CHECK6-NEXT:    [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]]
4012 // CHECK6-NEXT:    [[TMP23:%.*]] = load ptr, ptr [[TMP0]], align 8
4013 // CHECK6-NEXT:    [[TMP24:%.*]] = load i32, ptr [[I]], align 4
4014 // CHECK6-NEXT:    [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64
4015 // CHECK6-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP23]], i64 [[IDXPROM9]]
4016 // CHECK6-NEXT:    store float [[MUL8]], ptr [[ARRAYIDX10]], align 4
4017 // CHECK6-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
4018 // CHECK6:       omp.body.continue:
4019 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4020 // CHECK6:       omp.inner.for.inc:
4021 // CHECK6-NEXT:    [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4022 // CHECK6-NEXT:    [[ADD11:%.*]] = add i32 [[TMP25]], 1
4023 // CHECK6-NEXT:    store i32 [[ADD11]], ptr [[DOTOMP_IV]], align 4
4024 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_COND]]
4025 // CHECK6:       omp.inner.for.end:
4026 // CHECK6-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
4027 // CHECK6:       omp.dispatch.inc:
4028 // CHECK6-NEXT:    [[TMP26:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
4029 // CHECK6-NEXT:    [[TMP27:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
4030 // CHECK6-NEXT:    [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]]
4031 // CHECK6-NEXT:    store i32 [[ADD12]], ptr [[DOTOMP_LB]], align 4
4032 // CHECK6-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4033 // CHECK6-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
4034 // CHECK6-NEXT:    [[ADD13:%.*]] = add i32 [[TMP28]], [[TMP29]]
4035 // CHECK6-NEXT:    store i32 [[ADD13]], ptr [[DOTOMP_UB]], align 4
4036 // CHECK6-NEXT:    br label [[OMP_DISPATCH_COND]]
4037 // CHECK6:       omp.dispatch.end:
4038 // CHECK6-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])
4039 // CHECK6-NEXT:    ret void
4040 //
4041 //
4042 // CHECK6-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_
4043 // CHECK6-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
4044 // CHECK6-NEXT:  entry:
4045 // CHECK6-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
4046 // CHECK6-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
4047 // CHECK6-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
4048 // CHECK6-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
4049 // CHECK6-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
4050 // CHECK6-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
4051 // CHECK6-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
4052 // CHECK6-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
4053 // CHECK6-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @_Z8dynamic1PfS_S_S_.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])
4054 // CHECK6-NEXT:    ret void
4055 //
4056 //
4057 // CHECK6-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_.omp_outlined
4058 // CHECK6-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] {
4059 // CHECK6-NEXT:  entry:
4060 // CHECK6-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
4061 // CHECK6-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
4062 // CHECK6-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
4063 // CHECK6-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
4064 // CHECK6-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
4065 // CHECK6-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
4066 // CHECK6-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
4067 // CHECK6-NEXT:    [[TMP:%.*]] = alloca i64, align 8
4068 // CHECK6-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
4069 // CHECK6-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
4070 // CHECK6-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
4071 // CHECK6-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4072 // CHECK6-NEXT:    [[I:%.*]] = alloca i64, align 8
4073 // CHECK6-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
4074 // CHECK6-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
4075 // CHECK6-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
4076 // CHECK6-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
4077 // CHECK6-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
4078 // CHECK6-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
4079 // CHECK6-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
4080 // CHECK6-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
4081 // CHECK6-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8
4082 // CHECK6-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8
4083 // CHECK6-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8
4084 // CHECK6-NEXT:    store i64 16908287, ptr [[DOTOMP_UB]], align 8
4085 // CHECK6-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8
4086 // CHECK6-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
4087 // CHECK6-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
4088 // CHECK6-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
4089 // CHECK6-NEXT:    call void @__kmpc_dispatch_init_8u(ptr @[[GLOB2]], i32 [[TMP5]], i32 1073741859, i64 0, i64 16908287, i64 1, i64 1)
4090 // CHECK6-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
4091 // CHECK6:       omp.dispatch.cond:
4092 // CHECK6-NEXT:    [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_8u(ptr @[[GLOB2]], i32 [[TMP5]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
4093 // CHECK6-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0
4094 // CHECK6-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
4095 // CHECK6:       omp.dispatch.body:
4096 // CHECK6-NEXT:    [[TMP7:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
4097 // CHECK6-NEXT:    store i64 [[TMP7]], ptr [[DOTOMP_IV]], align 8
4098 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
4099 // CHECK6:       omp.inner.for.cond:
4100 // CHECK6-NEXT:    [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP5:![0-9]+]]
4101 // CHECK6-NEXT:    [[TMP9:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP5]]
4102 // CHECK6-NEXT:    [[ADD:%.*]] = add i64 [[TMP9]], 1
4103 // CHECK6-NEXT:    [[CMP:%.*]] = icmp ult i64 [[TMP8]], [[ADD]]
4104 // CHECK6-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4105 // CHECK6:       omp.inner.for.body:
4106 // CHECK6-NEXT:    [[TMP10:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP5]]
4107 // CHECK6-NEXT:    [[MUL:%.*]] = mul i64 [[TMP10]], 127
4108 // CHECK6-NEXT:    [[ADD1:%.*]] = add i64 131071, [[MUL]]
4109 // CHECK6-NEXT:    store i64 [[ADD1]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP5]]
4110 // CHECK6-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP5]]
4111 // CHECK6-NEXT:    [[TMP12:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP5]]
4112 // CHECK6-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP11]], i64 [[TMP12]]
4113 // CHECK6-NEXT:    [[TMP13:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP5]]
4114 // CHECK6-NEXT:    [[TMP14:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP5]]
4115 // CHECK6-NEXT:    [[TMP15:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP5]]
4116 // CHECK6-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[TMP14]], i64 [[TMP15]]
4117 // CHECK6-NEXT:    [[TMP16:%.*]] = load float, ptr [[ARRAYIDX2]], align 4, !llvm.access.group [[ACC_GRP5]]
4118 // CHECK6-NEXT:    [[MUL3:%.*]] = fmul float [[TMP13]], [[TMP16]]
4119 // CHECK6-NEXT:    [[TMP17:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP5]]
4120 // CHECK6-NEXT:    [[TMP18:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP5]]
4121 // CHECK6-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds float, ptr [[TMP17]], i64 [[TMP18]]
4122 // CHECK6-NEXT:    [[TMP19:%.*]] = load float, ptr [[ARRAYIDX4]], align 4, !llvm.access.group [[ACC_GRP5]]
4123 // CHECK6-NEXT:    [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP19]]
4124 // CHECK6-NEXT:    [[TMP20:%.*]] = load ptr, ptr [[TMP0]], align 8, !llvm.access.group [[ACC_GRP5]]
4125 // CHECK6-NEXT:    [[TMP21:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP5]]
4126 // CHECK6-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP20]], i64 [[TMP21]]
4127 // CHECK6-NEXT:    store float [[MUL5]], ptr [[ARRAYIDX6]], align 4, !llvm.access.group [[ACC_GRP5]]
4128 // CHECK6-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
4129 // CHECK6:       omp.body.continue:
4130 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4131 // CHECK6:       omp.inner.for.inc:
4132 // CHECK6-NEXT:    [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP5]]
4133 // CHECK6-NEXT:    [[ADD7:%.*]] = add i64 [[TMP22]], 1
4134 // CHECK6-NEXT:    store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP5]]
4135 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
4136 // CHECK6:       omp.inner.for.end:
4137 // CHECK6-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
4138 // CHECK6:       omp.dispatch.inc:
4139 // CHECK6-NEXT:    br label [[OMP_DISPATCH_COND]]
4140 // CHECK6:       omp.dispatch.end:
4141 // CHECK6-NEXT:    ret void
4142 //
4143 //
4144 // CHECK6-LABEL: define {{[^@]+}}@_Z7guided7PfS_S_S_
4145 // CHECK6-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
4146 // CHECK6-NEXT:  entry:
4147 // CHECK6-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
4148 // CHECK6-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
4149 // CHECK6-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
4150 // CHECK6-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
4151 // CHECK6-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
4152 // CHECK6-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
4153 // CHECK6-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
4154 // CHECK6-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
4155 // CHECK6-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @_Z7guided7PfS_S_S_.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])
4156 // CHECK6-NEXT:    ret void
4157 //
4158 //
4159 // CHECK6-LABEL: define {{[^@]+}}@_Z7guided7PfS_S_S_.omp_outlined
4160 // CHECK6-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] {
4161 // CHECK6-NEXT:  entry:
4162 // CHECK6-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
4163 // CHECK6-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
4164 // CHECK6-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
4165 // CHECK6-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
4166 // CHECK6-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
4167 // CHECK6-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
4168 // CHECK6-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
4169 // CHECK6-NEXT:    [[TMP:%.*]] = alloca i64, align 8
4170 // CHECK6-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
4171 // CHECK6-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
4172 // CHECK6-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
4173 // CHECK6-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4174 // CHECK6-NEXT:    [[I:%.*]] = alloca i64, align 8
4175 // CHECK6-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
4176 // CHECK6-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
4177 // CHECK6-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
4178 // CHECK6-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
4179 // CHECK6-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
4180 // CHECK6-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
4181 // CHECK6-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
4182 // CHECK6-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
4183 // CHECK6-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8
4184 // CHECK6-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8
4185 // CHECK6-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8
4186 // CHECK6-NEXT:    store i64 16908287, ptr [[DOTOMP_UB]], align 8
4187 // CHECK6-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8
4188 // CHECK6-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
4189 // CHECK6-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
4190 // CHECK6-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
4191 // CHECK6-NEXT:    call void @__kmpc_dispatch_init_8u(ptr @[[GLOB2]], i32 [[TMP5]], i32 1073741860, i64 0, i64 16908287, i64 1, i64 7)
4192 // CHECK6-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
4193 // CHECK6:       omp.dispatch.cond:
4194 // CHECK6-NEXT:    [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_8u(ptr @[[GLOB2]], i32 [[TMP5]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
4195 // CHECK6-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0
4196 // CHECK6-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
4197 // CHECK6:       omp.dispatch.body:
4198 // CHECK6-NEXT:    [[TMP7:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
4199 // CHECK6-NEXT:    store i64 [[TMP7]], ptr [[DOTOMP_IV]], align 8
4200 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
4201 // CHECK6:       omp.inner.for.cond:
4202 // CHECK6-NEXT:    [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP8:![0-9]+]]
4203 // CHECK6-NEXT:    [[TMP9:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP8]]
4204 // CHECK6-NEXT:    [[ADD:%.*]] = add i64 [[TMP9]], 1
4205 // CHECK6-NEXT:    [[CMP:%.*]] = icmp ult i64 [[TMP8]], [[ADD]]
4206 // CHECK6-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4207 // CHECK6:       omp.inner.for.body:
4208 // CHECK6-NEXT:    [[TMP10:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP8]]
4209 // CHECK6-NEXT:    [[MUL:%.*]] = mul i64 [[TMP10]], 127
4210 // CHECK6-NEXT:    [[ADD1:%.*]] = add i64 131071, [[MUL]]
4211 // CHECK6-NEXT:    store i64 [[ADD1]], ptr [[I]], align 8, !llvm.access.group [[ACC_GRP8]]
4212 // CHECK6-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP8]]
4213 // CHECK6-NEXT:    [[TMP12:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP8]]
4214 // CHECK6-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP11]], i64 [[TMP12]]
4215 // CHECK6-NEXT:    [[TMP13:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP8]]
4216 // CHECK6-NEXT:    [[TMP14:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP8]]
4217 // CHECK6-NEXT:    [[TMP15:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP8]]
4218 // CHECK6-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds float, ptr [[TMP14]], i64 [[TMP15]]
4219 // CHECK6-NEXT:    [[TMP16:%.*]] = load float, ptr [[ARRAYIDX2]], align 4, !llvm.access.group [[ACC_GRP8]]
4220 // CHECK6-NEXT:    [[MUL3:%.*]] = fmul float [[TMP13]], [[TMP16]]
4221 // CHECK6-NEXT:    [[TMP17:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP8]]
4222 // CHECK6-NEXT:    [[TMP18:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP8]]
4223 // CHECK6-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds float, ptr [[TMP17]], i64 [[TMP18]]
4224 // CHECK6-NEXT:    [[TMP19:%.*]] = load float, ptr [[ARRAYIDX4]], align 4, !llvm.access.group [[ACC_GRP8]]
4225 // CHECK6-NEXT:    [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP19]]
4226 // CHECK6-NEXT:    [[TMP20:%.*]] = load ptr, ptr [[TMP0]], align 8, !llvm.access.group [[ACC_GRP8]]
4227 // CHECK6-NEXT:    [[TMP21:%.*]] = load i64, ptr [[I]], align 8, !llvm.access.group [[ACC_GRP8]]
4228 // CHECK6-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds float, ptr [[TMP20]], i64 [[TMP21]]
4229 // CHECK6-NEXT:    store float [[MUL5]], ptr [[ARRAYIDX6]], align 4, !llvm.access.group [[ACC_GRP8]]
4230 // CHECK6-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
4231 // CHECK6:       omp.body.continue:
4232 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4233 // CHECK6:       omp.inner.for.inc:
4234 // CHECK6-NEXT:    [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP8]]
4235 // CHECK6-NEXT:    [[ADD7:%.*]] = add i64 [[TMP22]], 1
4236 // CHECK6-NEXT:    store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP8]]
4237 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
4238 // CHECK6:       omp.inner.for.end:
4239 // CHECK6-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
4240 // CHECK6:       omp.dispatch.inc:
4241 // CHECK6-NEXT:    br label [[OMP_DISPATCH_COND]]
4242 // CHECK6:       omp.dispatch.end:
4243 // CHECK6-NEXT:    ret void
4244 //
4245 //
4246 // CHECK6-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_
4247 // CHECK6-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
4248 // CHECK6-NEXT:  entry:
4249 // CHECK6-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
4250 // CHECK6-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
4251 // CHECK6-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
4252 // CHECK6-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
4253 // CHECK6-NEXT:    [[X:%.*]] = alloca i32, align 4
4254 // CHECK6-NEXT:    [[Y:%.*]] = alloca i32, align 4
4255 // CHECK6-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
4256 // CHECK6-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
4257 // CHECK6-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
4258 // CHECK6-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
4259 // CHECK6-NEXT:    store i32 0, ptr [[X]], align 4
4260 // CHECK6-NEXT:    store i32 0, ptr [[Y]], align 4
4261 // CHECK6-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 5, ptr @_Z9test_autoPfS_S_S_.omp_outlined, ptr [[Y]], ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])
4262 // CHECK6-NEXT:    ret void
4263 //
4264 //
4265 // CHECK6-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_.omp_outlined
4266 // CHECK6-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[Y:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] {
4267 // CHECK6-NEXT:  entry:
4268 // CHECK6-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
4269 // CHECK6-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
4270 // CHECK6-NEXT:    [[Y_ADDR:%.*]] = alloca ptr, align 8
4271 // CHECK6-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
4272 // CHECK6-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
4273 // CHECK6-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
4274 // CHECK6-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
4275 // CHECK6-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
4276 // CHECK6-NEXT:    [[TMP:%.*]] = alloca i8, align 1
4277 // CHECK6-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
4278 // CHECK6-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
4279 // CHECK6-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 8
4280 // CHECK6-NEXT:    [[I:%.*]] = alloca i8, align 1
4281 // CHECK6-NEXT:    [[X:%.*]] = alloca i32, align 4
4282 // CHECK6-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
4283 // CHECK6-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
4284 // CHECK6-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
4285 // CHECK6-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4286 // CHECK6-NEXT:    [[I7:%.*]] = alloca i8, align 1
4287 // CHECK6-NEXT:    [[X8:%.*]] = alloca i32, align 4
4288 // CHECK6-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
4289 // CHECK6-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
4290 // CHECK6-NEXT:    store ptr [[Y]], ptr [[Y_ADDR]], align 8
4291 // CHECK6-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
4292 // CHECK6-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
4293 // CHECK6-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
4294 // CHECK6-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
4295 // CHECK6-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[Y_ADDR]], align 8
4296 // CHECK6-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[A_ADDR]], align 8
4297 // CHECK6-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[B_ADDR]], align 8
4298 // CHECK6-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
4299 // CHECK6-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[D_ADDR]], align 8
4300 // CHECK6-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP0]], align 4
4301 // CHECK6-NEXT:    [[CONV:%.*]] = trunc i32 [[TMP5]] to i8
4302 // CHECK6-NEXT:    store i8 [[CONV]], ptr [[DOTCAPTURE_EXPR_]], align 1
4303 // CHECK6-NEXT:    [[TMP6:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
4304 // CHECK6-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP6]] to i32
4305 // CHECK6-NEXT:    [[SUB:%.*]] = sub i32 57, [[CONV3]]
4306 // CHECK6-NEXT:    [[ADD:%.*]] = add i32 [[SUB]], 1
4307 // CHECK6-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
4308 // CHECK6-NEXT:    [[CONV4:%.*]] = zext i32 [[DIV]] to i64
4309 // CHECK6-NEXT:    [[MUL:%.*]] = mul nsw i64 [[CONV4]], 11
4310 // CHECK6-NEXT:    [[SUB5:%.*]] = sub nsw i64 [[MUL]], 1
4311 // CHECK6-NEXT:    store i64 [[SUB5]], ptr [[DOTCAPTURE_EXPR_2]], align 8
4312 // CHECK6-NEXT:    [[TMP7:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
4313 // CHECK6-NEXT:    store i8 [[TMP7]], ptr [[I]], align 1
4314 // CHECK6-NEXT:    store i32 11, ptr [[X]], align 4
4315 // CHECK6-NEXT:    [[TMP8:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
4316 // CHECK6-NEXT:    [[CONV6:%.*]] = sext i8 [[TMP8]] to i32
4317 // CHECK6-NEXT:    [[CMP:%.*]] = icmp sle i32 [[CONV6]], 57
4318 // CHECK6-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
4319 // CHECK6:       omp.precond.then:
4320 // CHECK6-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8
4321 // CHECK6-NEXT:    [[TMP9:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_2]], align 8
4322 // CHECK6-NEXT:    store i64 [[TMP9]], ptr [[DOTOMP_UB]], align 8
4323 // CHECK6-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8
4324 // CHECK6-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
4325 // CHECK6-NEXT:    [[TMP10:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_2]], align 8
4326 // CHECK6-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
4327 // CHECK6-NEXT:    [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4
4328 // CHECK6-NEXT:    call void @__kmpc_dispatch_init_8(ptr @[[GLOB2]], i32 [[TMP12]], i32 1073741862, i64 0, i64 [[TMP10]], i64 1, i64 1)
4329 // CHECK6-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
4330 // CHECK6:       omp.dispatch.cond:
4331 // CHECK6-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
4332 // CHECK6-NEXT:    [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4
4333 // CHECK6-NEXT:    [[TMP15:%.*]] = call i32 @__kmpc_dispatch_next_8(ptr @[[GLOB2]], i32 [[TMP14]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
4334 // CHECK6-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0
4335 // CHECK6-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
4336 // CHECK6:       omp.dispatch.body:
4337 // CHECK6-NEXT:    [[TMP16:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
4338 // CHECK6-NEXT:    store i64 [[TMP16]], ptr [[DOTOMP_IV]], align 8
4339 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
4340 // CHECK6:       omp.inner.for.cond:
4341 // CHECK6-NEXT:    [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP11:![0-9]+]]
4342 // CHECK6-NEXT:    [[TMP18:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP11]]
4343 // CHECK6-NEXT:    [[CMP9:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]]
4344 // CHECK6-NEXT:    br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4345 // CHECK6:       omp.inner.for.body:
4346 // CHECK6-NEXT:    [[TMP19:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group [[ACC_GRP11]]
4347 // CHECK6-NEXT:    [[CONV10:%.*]] = sext i8 [[TMP19]] to i64
4348 // CHECK6-NEXT:    [[TMP20:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP11]]
4349 // CHECK6-NEXT:    [[DIV11:%.*]] = sdiv i64 [[TMP20]], 11
4350 // CHECK6-NEXT:    [[MUL12:%.*]] = mul nsw i64 [[DIV11]], 1
4351 // CHECK6-NEXT:    [[ADD13:%.*]] = add nsw i64 [[CONV10]], [[MUL12]]
4352 // CHECK6-NEXT:    [[CONV14:%.*]] = trunc i64 [[ADD13]] to i8
4353 // CHECK6-NEXT:    store i8 [[CONV14]], ptr [[I7]], align 1, !llvm.access.group [[ACC_GRP11]]
4354 // CHECK6-NEXT:    [[TMP21:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP11]]
4355 // CHECK6-NEXT:    [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP11]]
4356 // CHECK6-NEXT:    [[DIV15:%.*]] = sdiv i64 [[TMP22]], 11
4357 // CHECK6-NEXT:    [[MUL16:%.*]] = mul nsw i64 [[DIV15]], 11
4358 // CHECK6-NEXT:    [[SUB17:%.*]] = sub nsw i64 [[TMP21]], [[MUL16]]
4359 // CHECK6-NEXT:    [[MUL18:%.*]] = mul nsw i64 [[SUB17]], 1
4360 // CHECK6-NEXT:    [[SUB19:%.*]] = sub nsw i64 11, [[MUL18]]
4361 // CHECK6-NEXT:    [[CONV20:%.*]] = trunc i64 [[SUB19]] to i32
4362 // CHECK6-NEXT:    store i32 [[CONV20]], ptr [[X8]], align 4, !llvm.access.group [[ACC_GRP11]]
4363 // CHECK6-NEXT:    [[TMP23:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP11]]
4364 // CHECK6-NEXT:    [[TMP24:%.*]] = load i8, ptr [[I7]], align 1, !llvm.access.group [[ACC_GRP11]]
4365 // CHECK6-NEXT:    [[IDXPROM:%.*]] = sext i8 [[TMP24]] to i64
4366 // CHECK6-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP23]], i64 [[IDXPROM]]
4367 // CHECK6-NEXT:    [[TMP25:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP11]]
4368 // CHECK6-NEXT:    [[TMP26:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP11]]
4369 // CHECK6-NEXT:    [[TMP27:%.*]] = load i8, ptr [[I7]], align 1, !llvm.access.group [[ACC_GRP11]]
4370 // CHECK6-NEXT:    [[IDXPROM21:%.*]] = sext i8 [[TMP27]] to i64
4371 // CHECK6-NEXT:    [[ARRAYIDX22:%.*]] = getelementptr inbounds float, ptr [[TMP26]], i64 [[IDXPROM21]]
4372 // CHECK6-NEXT:    [[TMP28:%.*]] = load float, ptr [[ARRAYIDX22]], align 4, !llvm.access.group [[ACC_GRP11]]
4373 // CHECK6-NEXT:    [[MUL23:%.*]] = fmul float [[TMP25]], [[TMP28]]
4374 // CHECK6-NEXT:    [[TMP29:%.*]] = load ptr, ptr [[TMP4]], align 8, !llvm.access.group [[ACC_GRP11]]
4375 // CHECK6-NEXT:    [[TMP30:%.*]] = load i8, ptr [[I7]], align 1, !llvm.access.group [[ACC_GRP11]]
4376 // CHECK6-NEXT:    [[IDXPROM24:%.*]] = sext i8 [[TMP30]] to i64
4377 // CHECK6-NEXT:    [[ARRAYIDX25:%.*]] = getelementptr inbounds float, ptr [[TMP29]], i64 [[IDXPROM24]]
4378 // CHECK6-NEXT:    [[TMP31:%.*]] = load float, ptr [[ARRAYIDX25]], align 4, !llvm.access.group [[ACC_GRP11]]
4379 // CHECK6-NEXT:    [[MUL26:%.*]] = fmul float [[MUL23]], [[TMP31]]
4380 // CHECK6-NEXT:    [[TMP32:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP11]]
4381 // CHECK6-NEXT:    [[TMP33:%.*]] = load i8, ptr [[I7]], align 1, !llvm.access.group [[ACC_GRP11]]
4382 // CHECK6-NEXT:    [[IDXPROM27:%.*]] = sext i8 [[TMP33]] to i64
4383 // CHECK6-NEXT:    [[ARRAYIDX28:%.*]] = getelementptr inbounds float, ptr [[TMP32]], i64 [[IDXPROM27]]
4384 // CHECK6-NEXT:    store float [[MUL26]], ptr [[ARRAYIDX28]], align 4, !llvm.access.group [[ACC_GRP11]]
4385 // CHECK6-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
4386 // CHECK6:       omp.body.continue:
4387 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4388 // CHECK6:       omp.inner.for.inc:
4389 // CHECK6-NEXT:    [[TMP34:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP11]]
4390 // CHECK6-NEXT:    [[ADD29:%.*]] = add nsw i64 [[TMP34]], 1
4391 // CHECK6-NEXT:    store i64 [[ADD29]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP11]]
4392 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
4393 // CHECK6:       omp.inner.for.end:
4394 // CHECK6-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
4395 // CHECK6:       omp.dispatch.inc:
4396 // CHECK6-NEXT:    br label [[OMP_DISPATCH_COND]]
4397 // CHECK6:       omp.dispatch.end:
4398 // CHECK6-NEXT:    br label [[OMP_PRECOND_END]]
4399 // CHECK6:       omp.precond.end:
4400 // CHECK6-NEXT:    ret void
4401 //
4402 //
4403 // CHECK6-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_
4404 // CHECK6-SAME: (ptr noundef [[A:%.*]], ptr noundef [[B:%.*]], ptr noundef [[C:%.*]], ptr noundef [[D:%.*]]) #[[ATTR0]] {
4405 // CHECK6-NEXT:  entry:
4406 // CHECK6-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
4407 // CHECK6-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
4408 // CHECK6-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
4409 // CHECK6-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
4410 // CHECK6-NEXT:    [[X:%.*]] = alloca i32, align 4
4411 // CHECK6-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
4412 // CHECK6-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
4413 // CHECK6-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
4414 // CHECK6-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
4415 // CHECK6-NEXT:    store i32 0, ptr [[X]], align 4
4416 // CHECK6-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @_Z7runtimePfS_S_S_.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])
4417 // CHECK6-NEXT:    ret void
4418 //
4419 //
4420 // CHECK6-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_.omp_outlined
4421 // CHECK6-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[B:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[C:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] {
4422 // CHECK6-NEXT:  entry:
4423 // CHECK6-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
4424 // CHECK6-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
4425 // CHECK6-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
4426 // CHECK6-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
4427 // CHECK6-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
4428 // CHECK6-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
4429 // CHECK6-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
4430 // CHECK6-NEXT:    [[TMP:%.*]] = alloca i8, align 1
4431 // CHECK6-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
4432 // CHECK6-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
4433 // CHECK6-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
4434 // CHECK6-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4435 // CHECK6-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4436 // CHECK6-NEXT:    [[I:%.*]] = alloca i8, align 1
4437 // CHECK6-NEXT:    [[X:%.*]] = alloca i32, align 4
4438 // CHECK6-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
4439 // CHECK6-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
4440 // CHECK6-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
4441 // CHECK6-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
4442 // CHECK6-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
4443 // CHECK6-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
4444 // CHECK6-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
4445 // CHECK6-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
4446 // CHECK6-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8
4447 // CHECK6-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8
4448 // CHECK6-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
4449 // CHECK6-NEXT:    store i32 199, ptr [[DOTOMP_UB]], align 4
4450 // CHECK6-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
4451 // CHECK6-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
4452 // CHECK6-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
4453 // CHECK6-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
4454 // CHECK6-NEXT:    call void @__kmpc_dispatch_init_4(ptr @[[GLOB2]], i32 [[TMP5]], i32 1073741861, i32 0, i32 199, i32 1, i32 1)
4455 // CHECK6-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
4456 // CHECK6:       omp.dispatch.cond:
4457 // CHECK6-NEXT:    [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB2]], i32 [[TMP5]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
4458 // CHECK6-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0
4459 // CHECK6-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
4460 // CHECK6:       omp.dispatch.body:
4461 // CHECK6-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
4462 // CHECK6-NEXT:    store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
4463 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
4464 // CHECK6:       omp.inner.for.cond:
4465 // CHECK6-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14:![0-9]+]]
4466 // CHECK6-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP14]]
4467 // CHECK6-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
4468 // CHECK6-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4469 // CHECK6:       omp.inner.for.body:
4470 // CHECK6-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]
4471 // CHECK6-NEXT:    [[DIV:%.*]] = sdiv i32 [[TMP10]], 20
4472 // CHECK6-NEXT:    [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
4473 // CHECK6-NEXT:    [[ADD:%.*]] = add nsw i32 48, [[MUL]]
4474 // CHECK6-NEXT:    [[CONV:%.*]] = trunc i32 [[ADD]] to i8
4475 // CHECK6-NEXT:    store i8 [[CONV]], ptr [[I]], align 1, !llvm.access.group [[ACC_GRP14]]
4476 // CHECK6-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]
4477 // CHECK6-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]
4478 // CHECK6-NEXT:    [[DIV2:%.*]] = sdiv i32 [[TMP12]], 20
4479 // CHECK6-NEXT:    [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 20
4480 // CHECK6-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL3]]
4481 // CHECK6-NEXT:    [[MUL4:%.*]] = mul nsw i32 [[SUB]], 1
4482 // CHECK6-NEXT:    [[ADD5:%.*]] = add nsw i32 -10, [[MUL4]]
4483 // CHECK6-NEXT:    store i32 [[ADD5]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP14]]
4484 // CHECK6-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[TMP1]], align 8, !llvm.access.group [[ACC_GRP14]]
4485 // CHECK6-NEXT:    [[TMP14:%.*]] = load i8, ptr [[I]], align 1, !llvm.access.group [[ACC_GRP14]]
4486 // CHECK6-NEXT:    [[IDXPROM:%.*]] = zext i8 [[TMP14]] to i64
4487 // CHECK6-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[TMP13]], i64 [[IDXPROM]]
4488 // CHECK6-NEXT:    [[TMP15:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP14]]
4489 // CHECK6-NEXT:    [[TMP16:%.*]] = load ptr, ptr [[TMP2]], align 8, !llvm.access.group [[ACC_GRP14]]
4490 // CHECK6-NEXT:    [[TMP17:%.*]] = load i8, ptr [[I]], align 1, !llvm.access.group [[ACC_GRP14]]
4491 // CHECK6-NEXT:    [[IDXPROM6:%.*]] = zext i8 [[TMP17]] to i64
4492 // CHECK6-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds float, ptr [[TMP16]], i64 [[IDXPROM6]]
4493 // CHECK6-NEXT:    [[TMP18:%.*]] = load float, ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP14]]
4494 // CHECK6-NEXT:    [[MUL8:%.*]] = fmul float [[TMP15]], [[TMP18]]
4495 // CHECK6-NEXT:    [[TMP19:%.*]] = load ptr, ptr [[TMP3]], align 8, !llvm.access.group [[ACC_GRP14]]
4496 // CHECK6-NEXT:    [[TMP20:%.*]] = load i8, ptr [[I]], align 1, !llvm.access.group [[ACC_GRP14]]
4497 // CHECK6-NEXT:    [[IDXPROM9:%.*]] = zext i8 [[TMP20]] to i64
4498 // CHECK6-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP19]], i64 [[IDXPROM9]]
4499 // CHECK6-NEXT:    [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP14]]
4500 // CHECK6-NEXT:    [[MUL11:%.*]] = fmul float [[MUL8]], [[TMP21]]
4501 // CHECK6-NEXT:    [[TMP22:%.*]] = load ptr, ptr [[TMP0]], align 8, !llvm.access.group [[ACC_GRP14]]
4502 // CHECK6-NEXT:    [[TMP23:%.*]] = load i8, ptr [[I]], align 1, !llvm.access.group [[ACC_GRP14]]
4503 // CHECK6-NEXT:    [[IDXPROM12:%.*]] = zext i8 [[TMP23]] to i64
4504 // CHECK6-NEXT:    [[ARRAYIDX13:%.*]] = getelementptr inbounds float, ptr [[TMP22]], i64 [[IDXPROM12]]
4505 // CHECK6-NEXT:    store float [[MUL11]], ptr [[ARRAYIDX13]], align 4, !llvm.access.group [[ACC_GRP14]]
4506 // CHECK6-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
4507 // CHECK6:       omp.body.continue:
4508 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4509 // CHECK6:       omp.inner.for.inc:
4510 // CHECK6-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]
4511 // CHECK6-NEXT:    [[ADD14:%.*]] = add nsw i32 [[TMP24]], 1
4512 // CHECK6-NEXT:    store i32 [[ADD14]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]
4513 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
4514 // CHECK6:       omp.inner.for.end:
4515 // CHECK6-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
4516 // CHECK6:       omp.dispatch.inc:
4517 // CHECK6-NEXT:    br label [[OMP_DISPATCH_COND]]
4518 // CHECK6:       omp.dispatch.end:
4519 // CHECK6-NEXT:    ret void
4520 //
4521 //
4522 // CHECK6-LABEL: define {{[^@]+}}@_Z3foov
4523 // CHECK6-SAME: () #[[ATTR0]] {
4524 // CHECK6-NEXT:  entry:
4525 // CHECK6-NEXT:    call void @_Z8mayThrowv()
4526 // CHECK6-NEXT:    ret i32 0
4527 //
4528 //
4529 // CHECK6-LABEL: define {{[^@]+}}@_Z12parallel_forPfi
4530 // CHECK6-SAME: (ptr noundef [[A:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] {
4531 // CHECK6-NEXT:  entry:
4532 // CHECK6-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
4533 // CHECK6-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
4534 // CHECK6-NEXT:    [[SAVED_STACK:%.*]] = alloca ptr, align 8
4535 // CHECK6-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
4536 // CHECK6-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8
4537 // CHECK6-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
4538 // CHECK6-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
4539 // CHECK6-NEXT:    [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
4540 // CHECK6-NEXT:    [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
4541 // CHECK6-NEXT:    [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
4542 // CHECK6-NEXT:    store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
4543 // CHECK6-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 16
4544 // CHECK6-NEXT:    store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
4545 // CHECK6-NEXT:    [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4
4546 // CHECK6-NEXT:    store i32 [[TMP3]], ptr [[N_CASTED]], align 4
4547 // CHECK6-NEXT:    [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8
4548 // CHECK6-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @_Z12parallel_forPfi.omp_outlined, ptr [[A_ADDR]], i64 [[TMP1]], i64 [[TMP4]])
4549 // CHECK6-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
4550 // CHECK6-NEXT:    call void @llvm.stackrestore.p0(ptr [[TMP5]])
4551 // CHECK6-NEXT:    ret void
4552 //
4553 //
4554 // CHECK6-LABEL: define {{[^@]+}}@_Z12parallel_forPfi.omp_outlined
4555 // CHECK6-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[A:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[N:%.*]]) #[[ATTR1]] {
4556 // CHECK6-NEXT:  entry:
4557 // CHECK6-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
4558 // CHECK6-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
4559 // CHECK6-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
4560 // CHECK6-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
4561 // CHECK6-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
4562 // CHECK6-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
4563 // CHECK6-NEXT:    [[TMP:%.*]] = alloca i32, align 4
4564 // CHECK6-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
4565 // CHECK6-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
4566 // CHECK6-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4567 // CHECK6-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4568 // CHECK6-NEXT:    [[SAVED_STACK:%.*]] = alloca ptr, align 8
4569 // CHECK6-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
4570 // CHECK6-NEXT:    [[I:%.*]] = alloca i32, align 4
4571 // CHECK6-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
4572 // CHECK6-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
4573 // CHECK6-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
4574 // CHECK6-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
4575 // CHECK6-NEXT:    store i64 [[N]], ptr [[N_ADDR]], align 8
4576 // CHECK6-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
4577 // CHECK6-NEXT:    [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
4578 // CHECK6-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
4579 // CHECK6-NEXT:    store i32 16908288, ptr [[DOTOMP_UB]], align 4
4580 // CHECK6-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
4581 // CHECK6-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
4582 // CHECK6-NEXT:    [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
4583 // CHECK6-NEXT:    store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
4584 // CHECK6-NEXT:    [[VLA1:%.*]] = alloca float, i64 [[TMP1]], align 16
4585 // CHECK6-NEXT:    store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
4586 // CHECK6-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
4587 // CHECK6-NEXT:    [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
4588 // CHECK6-NEXT:    call void @__kmpc_for_static_init_4u(ptr @[[GLOB1]], i32 [[TMP4]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 5)
4589 // CHECK6-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
4590 // CHECK6:       omp.dispatch.cond:
4591 // CHECK6-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4592 // CHECK6-NEXT:    [[CMP:%.*]] = icmp ugt i32 [[TMP5]], 16908288
4593 // CHECK6-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4594 // CHECK6:       cond.true:
4595 // CHECK6-NEXT:    br label [[COND_END:%.*]]
4596 // CHECK6:       cond.false:
4597 // CHECK6-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4598 // CHECK6-NEXT:    br label [[COND_END]]
4599 // CHECK6:       cond.end:
4600 // CHECK6-NEXT:    [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]
4601 // CHECK6-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
4602 // CHECK6-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
4603 // CHECK6-NEXT:    store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
4604 // CHECK6-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4605 // CHECK6-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4606 // CHECK6-NEXT:    [[CMP2:%.*]] = icmp ule i32 [[TMP8]], [[TMP9]]
4607 // CHECK6-NEXT:    br i1 [[CMP2]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_CLEANUP:%.*]]
4608 // CHECK6:       omp.dispatch.cleanup:
4609 // CHECK6-NEXT:    br label [[OMP_DISPATCH_END:%.*]]
4610 // CHECK6:       omp.dispatch.body:
4611 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
4612 // CHECK6:       omp.inner.for.cond:
4613 // CHECK6-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4614 // CHECK6-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4615 // CHECK6-NEXT:    [[CMP3:%.*]] = icmp ule i32 [[TMP10]], [[TMP11]]
4616 // CHECK6-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
4617 // CHECK6:       omp.inner.for.cond.cleanup:
4618 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
4619 // CHECK6:       omp.inner.for.body:
4620 // CHECK6-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4621 // CHECK6-NEXT:    [[MUL:%.*]] = mul i32 [[TMP12]], 127
4622 // CHECK6-NEXT:    [[ADD:%.*]] = add i32 131071, [[MUL]]
4623 // CHECK6-NEXT:    store i32 [[ADD]], ptr [[I]], align 4
4624 // CHECK6-NEXT:    [[CALL:%.*]] = call noundef i32 @_Z3foov()
4625 // CHECK6-NEXT:    [[CONV:%.*]] = sitofp i32 [[CALL]] to float
4626 // CHECK6-NEXT:    [[TMP13:%.*]] = load i32, ptr [[I]], align 4
4627 // CHECK6-NEXT:    [[IDXPROM:%.*]] = zext i32 [[TMP13]] to i64
4628 // CHECK6-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[VLA1]], i64 [[IDXPROM]]
4629 // CHECK6-NEXT:    [[TMP14:%.*]] = load float, ptr [[ARRAYIDX]], align 4
4630 // CHECK6-NEXT:    [[ADD4:%.*]] = fadd float [[CONV]], [[TMP14]]
4631 // CHECK6-NEXT:    [[TMP15:%.*]] = load i32, ptr [[N_ADDR]], align 4
4632 // CHECK6-NEXT:    [[CONV5:%.*]] = sitofp i32 [[TMP15]] to float
4633 // CHECK6-NEXT:    [[ADD6:%.*]] = fadd float [[ADD4]], [[CONV5]]
4634 // CHECK6-NEXT:    [[TMP16:%.*]] = load ptr, ptr [[TMP0]], align 8
4635 // CHECK6-NEXT:    [[TMP17:%.*]] = load i32, ptr [[I]], align 4
4636 // CHECK6-NEXT:    [[IDXPROM7:%.*]] = zext i32 [[TMP17]] to i64
4637 // CHECK6-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds float, ptr [[TMP16]], i64 [[IDXPROM7]]
4638 // CHECK6-NEXT:    [[TMP18:%.*]] = load float, ptr [[ARRAYIDX8]], align 4
4639 // CHECK6-NEXT:    [[ADD9:%.*]] = fadd float [[TMP18]], [[ADD6]]
4640 // CHECK6-NEXT:    store float [[ADD9]], ptr [[ARRAYIDX8]], align 4
4641 // CHECK6-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
4642 // CHECK6:       omp.body.continue:
4643 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4644 // CHECK6:       omp.inner.for.inc:
4645 // CHECK6-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4646 // CHECK6-NEXT:    [[ADD10:%.*]] = add i32 [[TMP19]], 1
4647 // CHECK6-NEXT:    store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4
4648 // CHECK6-NEXT:    br label [[OMP_INNER_FOR_COND]]
4649 // CHECK6:       omp.inner.for.end:
4650 // CHECK6-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
4651 // CHECK6:       omp.dispatch.inc:
4652 // CHECK6-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
4653 // CHECK6-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
4654 // CHECK6-NEXT:    [[ADD11:%.*]] = add i32 [[TMP20]], [[TMP21]]
4655 // CHECK6-NEXT:    store i32 [[ADD11]], ptr [[DOTOMP_LB]], align 4
4656 // CHECK6-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4657 // CHECK6-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
4658 // CHECK6-NEXT:    [[ADD12:%.*]] = add i32 [[TMP22]], [[TMP23]]
4659 // CHECK6-NEXT:    store i32 [[ADD12]], ptr [[DOTOMP_UB]], align 4
4660 // CHECK6-NEXT:    br label [[OMP_DISPATCH_COND]]
4661 // CHECK6:       omp.dispatch.end:
4662 // CHECK6-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP4]])
4663 // CHECK6-NEXT:    [[TMP24:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
4664 // CHECK6-NEXT:    call void @llvm.stackrestore.p0(ptr [[TMP24]])
4665 // CHECK6-NEXT:    ret void
4666 //
4667 //
4668 // CHECK11-LABEL: define {{[^@]+}}@_Z9incrementv
4669 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] {
4670 // CHECK11-NEXT:  entry:
4671 // CHECK11-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
4672 // CHECK11-NEXT:    [[TMP:%.*]] = alloca i32, align 4
4673 // CHECK11-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
4674 // CHECK11-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
4675 // CHECK11-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4676 // CHECK11-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4677 // CHECK11-NEXT:    [[I:%.*]] = alloca i32, align 4
4678 // CHECK11-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])
4679 // CHECK11-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
4680 // CHECK11-NEXT:    store i32 4, ptr [[DOTOMP_UB]], align 4
4681 // CHECK11-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
4682 // CHECK11-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
4683 // CHECK11-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
4684 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4685 // CHECK11-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP1]], 4
4686 // CHECK11-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4687 // CHECK11:       cond.true:
4688 // CHECK11-NEXT:    br label [[COND_END:%.*]]
4689 // CHECK11:       cond.false:
4690 // CHECK11-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4691 // CHECK11-NEXT:    br label [[COND_END]]
4692 // CHECK11:       cond.end:
4693 // CHECK11-NEXT:    [[COND:%.*]] = phi i32 [ 4, [[COND_TRUE]] ], [ [[TMP2]], [[COND_FALSE]] ]
4694 // CHECK11-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
4695 // CHECK11-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
4696 // CHECK11-NEXT:    store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
4697 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
4698 // CHECK11:       omp.inner.for.cond:
4699 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4700 // CHECK11-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4701 // CHECK11-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]
4702 // CHECK11-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4703 // CHECK11:       omp.inner.for.body:
4704 // CHECK11-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4705 // CHECK11-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1
4706 // CHECK11-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
4707 // CHECK11-NEXT:    store i32 [[ADD]], ptr [[I]], align 4
4708 // CHECK11-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
4709 // CHECK11:       omp.body.continue:
4710 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4711 // CHECK11:       omp.inner.for.inc:
4712 // CHECK11-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4713 // CHECK11-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP7]], 1
4714 // CHECK11-NEXT:    store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4
4715 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND]]
4716 // CHECK11:       omp.inner.for.end:
4717 // CHECK11-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
4718 // CHECK11:       omp.loop.exit:
4719 // CHECK11-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP0]])
4720 // CHECK11-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP0]])
4721 // CHECK11-NEXT:    ret i32 0
4722 //
4723 //
4724 // CHECK11-LABEL: define {{[^@]+}}@_Z16decrement_nowaitv
4725 // CHECK11-SAME: () #[[ATTR0]] {
4726 // CHECK11-NEXT:  entry:
4727 // CHECK11-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
4728 // CHECK11-NEXT:    [[TMP:%.*]] = alloca i32, align 4
4729 // CHECK11-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
4730 // CHECK11-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
4731 // CHECK11-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4732 // CHECK11-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4733 // CHECK11-NEXT:    [[J:%.*]] = alloca i32, align 4
4734 // CHECK11-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
4735 // CHECK11-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
4736 // CHECK11-NEXT:    store i32 4, ptr [[DOTOMP_UB]], align 4
4737 // CHECK11-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
4738 // CHECK11-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
4739 // CHECK11-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP0]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
4740 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4741 // CHECK11-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP1]], 4
4742 // CHECK11-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4743 // CHECK11:       cond.true:
4744 // CHECK11-NEXT:    br label [[COND_END:%.*]]
4745 // CHECK11:       cond.false:
4746 // CHECK11-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4747 // CHECK11-NEXT:    br label [[COND_END]]
4748 // CHECK11:       cond.end:
4749 // CHECK11-NEXT:    [[COND:%.*]] = phi i32 [ 4, [[COND_TRUE]] ], [ [[TMP2]], [[COND_FALSE]] ]
4750 // CHECK11-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
4751 // CHECK11-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
4752 // CHECK11-NEXT:    store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
4753 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
4754 // CHECK11:       omp.inner.for.cond:
4755 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4756 // CHECK11-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4757 // CHECK11-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]
4758 // CHECK11-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4759 // CHECK11:       omp.inner.for.body:
4760 // CHECK11-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4761 // CHECK11-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1
4762 // CHECK11-NEXT:    [[SUB:%.*]] = sub nsw i32 5, [[MUL]]
4763 // CHECK11-NEXT:    store i32 [[SUB]], ptr [[J]], align 4
4764 // CHECK11-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
4765 // CHECK11:       omp.body.continue:
4766 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4767 // CHECK11:       omp.inner.for.inc:
4768 // CHECK11-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4769 // CHECK11-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP7]], 1
4770 // CHECK11-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
4771 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND]]
4772 // CHECK11:       omp.inner.for.end:
4773 // CHECK11-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
4774 // CHECK11:       omp.loop.exit:
4775 // CHECK11-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP0]])
4776 // CHECK11-NEXT:    ret i32 0
4777 //
4778 //
4779 // CHECK11-LABEL: define {{[^@]+}}@_Z16range_for_singlev
4780 // CHECK11-SAME: () #[[ATTR0]] {
4781 // CHECK11-NEXT:  entry:
4782 // CHECK11-NEXT:    [[ARR:%.*]] = alloca [10 x i32], align 16
4783 // CHECK11-NEXT:    call void @llvm.memset.p0.i64(ptr align 16 [[ARR]], i8 0, i64 40, i1 false)
4784 // CHECK11-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @_Z16range_for_singlev.omp_outlined, ptr [[ARR]])
4785 // CHECK11-NEXT:    ret void
4786 //
4787 //
4788 // CHECK11-LABEL: define {{[^@]+}}@_Z16range_for_singlev.omp_outlined
4789 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[ARR:%.*]]) #[[ATTR4:[0-9]+]] {
4790 // CHECK11-NEXT:  entry:
4791 // CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
4792 // CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
4793 // CHECK11-NEXT:    [[ARR_ADDR:%.*]] = alloca ptr, align 8
4794 // CHECK11-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
4795 // CHECK11-NEXT:    [[TMP:%.*]] = alloca ptr, align 8
4796 // CHECK11-NEXT:    [[__RANGE1:%.*]] = alloca ptr, align 8
4797 // CHECK11-NEXT:    [[__END1:%.*]] = alloca ptr, align 8
4798 // CHECK11-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca ptr, align 8
4799 // CHECK11-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca ptr, align 8
4800 // CHECK11-NEXT:    [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8
4801 // CHECK11-NEXT:    [[__BEGIN1:%.*]] = alloca ptr, align 8
4802 // CHECK11-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
4803 // CHECK11-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
4804 // CHECK11-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
4805 // CHECK11-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4806 // CHECK11-NEXT:    [[__BEGIN15:%.*]] = alloca ptr, align 8
4807 // CHECK11-NEXT:    [[A:%.*]] = alloca ptr, align 8
4808 // CHECK11-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
4809 // CHECK11-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
4810 // CHECK11-NEXT:    store ptr [[ARR]], ptr [[ARR_ADDR]], align 8
4811 // CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[ARR_ADDR]], align 8
4812 // CHECK11-NEXT:    store ptr [[TMP0]], ptr [[__RANGE1]], align 8
4813 // CHECK11-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[__RANGE1]], align 8
4814 // CHECK11-NEXT:    [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP1]], i64 0, i64 0
4815 // CHECK11-NEXT:    [[ADD_PTR:%.*]] = getelementptr inbounds i32, ptr [[ARRAYDECAY]], i64 10
4816 // CHECK11-NEXT:    store ptr [[ADD_PTR]], ptr [[__END1]], align 8
4817 // CHECK11-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[__RANGE1]], align 8
4818 // CHECK11-NEXT:    [[ARRAYDECAY1:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP2]], i64 0, i64 0
4819 // CHECK11-NEXT:    store ptr [[ARRAYDECAY1]], ptr [[DOTCAPTURE_EXPR_]], align 8
4820 // CHECK11-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[__END1]], align 8
4821 // CHECK11-NEXT:    store ptr [[TMP3]], ptr [[DOTCAPTURE_EXPR_2]], align 8
4822 // CHECK11-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_2]], align 8
4823 // CHECK11-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_]], align 8
4824 // CHECK11-NEXT:    [[SUB_PTR_LHS_CAST:%.*]] = ptrtoint ptr [[TMP4]] to i64
4825 // CHECK11-NEXT:    [[SUB_PTR_RHS_CAST:%.*]] = ptrtoint ptr [[TMP5]] to i64
4826 // CHECK11-NEXT:    [[SUB_PTR_SUB:%.*]] = sub i64 [[SUB_PTR_LHS_CAST]], [[SUB_PTR_RHS_CAST]]
4827 // CHECK11-NEXT:    [[SUB_PTR_DIV:%.*]] = sdiv exact i64 [[SUB_PTR_SUB]], 4
4828 // CHECK11-NEXT:    [[SUB:%.*]] = sub nsw i64 [[SUB_PTR_DIV]], 1
4829 // CHECK11-NEXT:    [[ADD:%.*]] = add nsw i64 [[SUB]], 1
4830 // CHECK11-NEXT:    [[DIV:%.*]] = sdiv i64 [[ADD]], 1
4831 // CHECK11-NEXT:    [[SUB4:%.*]] = sub nsw i64 [[DIV]], 1
4832 // CHECK11-NEXT:    store i64 [[SUB4]], ptr [[DOTCAPTURE_EXPR_3]], align 8
4833 // CHECK11-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_]], align 8
4834 // CHECK11-NEXT:    store ptr [[TMP6]], ptr [[__BEGIN1]], align 8
4835 // CHECK11-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_]], align 8
4836 // CHECK11-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_2]], align 8
4837 // CHECK11-NEXT:    [[CMP:%.*]] = icmp ult ptr [[TMP7]], [[TMP8]]
4838 // CHECK11-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
4839 // CHECK11:       omp.precond.then:
4840 // CHECK11-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8
4841 // CHECK11-NEXT:    [[TMP9:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_3]], align 8
4842 // CHECK11-NEXT:    store i64 [[TMP9]], ptr [[DOTOMP_UB]], align 8
4843 // CHECK11-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8
4844 // CHECK11-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
4845 // CHECK11-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
4846 // CHECK11-NEXT:    [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4
4847 // CHECK11-NEXT:    call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP11]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
4848 // CHECK11-NEXT:    [[TMP12:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
4849 // CHECK11-NEXT:    [[TMP13:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_3]], align 8
4850 // CHECK11-NEXT:    [[CMP6:%.*]] = icmp sgt i64 [[TMP12]], [[TMP13]]
4851 // CHECK11-NEXT:    br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4852 // CHECK11:       cond.true:
4853 // CHECK11-NEXT:    [[TMP14:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_3]], align 8
4854 // CHECK11-NEXT:    br label [[COND_END:%.*]]
4855 // CHECK11:       cond.false:
4856 // CHECK11-NEXT:    [[TMP15:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
4857 // CHECK11-NEXT:    br label [[COND_END]]
4858 // CHECK11:       cond.end:
4859 // CHECK11-NEXT:    [[COND:%.*]] = phi i64 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ]
4860 // CHECK11-NEXT:    store i64 [[COND]], ptr [[DOTOMP_UB]], align 8
4861 // CHECK11-NEXT:    [[TMP16:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
4862 // CHECK11-NEXT:    store i64 [[TMP16]], ptr [[DOTOMP_IV]], align 8
4863 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
4864 // CHECK11:       omp.inner.for.cond:
4865 // CHECK11-NEXT:    [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
4866 // CHECK11-NEXT:    [[TMP18:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
4867 // CHECK11-NEXT:    [[CMP7:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]]
4868 // CHECK11-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4869 // CHECK11:       omp.inner.for.body:
4870 // CHECK11-NEXT:    [[TMP19:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_]], align 8
4871 // CHECK11-NEXT:    [[TMP20:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
4872 // CHECK11-NEXT:    [[MUL:%.*]] = mul nsw i64 [[TMP20]], 1
4873 // CHECK11-NEXT:    [[ADD_PTR8:%.*]] = getelementptr inbounds i32, ptr [[TMP19]], i64 [[MUL]]
4874 // CHECK11-NEXT:    store ptr [[ADD_PTR8]], ptr [[__BEGIN15]], align 8
4875 // CHECK11-NEXT:    [[TMP21:%.*]] = load ptr, ptr [[__BEGIN15]], align 8
4876 // CHECK11-NEXT:    store ptr [[TMP21]], ptr [[A]], align 8
4877 // CHECK11-NEXT:    [[TMP22:%.*]] = load ptr, ptr [[A]], align 8
4878 // CHECK11-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
4879 // CHECK11:       omp.body.continue:
4880 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4881 // CHECK11:       omp.inner.for.inc:
4882 // CHECK11-NEXT:    [[TMP23:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
4883 // CHECK11-NEXT:    [[ADD9:%.*]] = add nsw i64 [[TMP23]], 1
4884 // CHECK11-NEXT:    store i64 [[ADD9]], ptr [[DOTOMP_IV]], align 8
4885 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND]]
4886 // CHECK11:       omp.inner.for.end:
4887 // CHECK11-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
4888 // CHECK11:       omp.loop.exit:
4889 // CHECK11-NEXT:    [[TMP24:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
4890 // CHECK11-NEXT:    [[TMP25:%.*]] = load i32, ptr [[TMP24]], align 4
4891 // CHECK11-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP25]])
4892 // CHECK11-NEXT:    br label [[OMP_PRECOND_END]]
4893 // CHECK11:       omp.precond.end:
4894 // CHECK11-NEXT:    ret void
4895 //
4896 //
4897 // CHECK11-LABEL: define {{[^@]+}}@_Z19range_for_collapsedv
4898 // CHECK11-SAME: () #[[ATTR0]] {
4899 // CHECK11-NEXT:  entry:
4900 // CHECK11-NEXT:    [[ARR:%.*]] = alloca [10 x i32], align 16
4901 // CHECK11-NEXT:    call void @llvm.memset.p0.i64(ptr align 16 [[ARR]], i8 0, i64 40, i1 false)
4902 // CHECK11-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 1, ptr @_Z19range_for_collapsedv.omp_outlined, ptr [[ARR]])
4903 // CHECK11-NEXT:    ret void
4904 //
4905 //
4906 // CHECK11-LABEL: define {{[^@]+}}@_Z19range_for_collapsedv.omp_outlined
4907 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[ARR:%.*]]) #[[ATTR4]] {
4908 // CHECK11-NEXT:  entry:
4909 // CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
4910 // CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
4911 // CHECK11-NEXT:    [[ARR_ADDR:%.*]] = alloca ptr, align 8
4912 // CHECK11-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
4913 // CHECK11-NEXT:    [[TMP:%.*]] = alloca ptr, align 8
4914 // CHECK11-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 8
4915 // CHECK11-NEXT:    [[__RANGE1:%.*]] = alloca ptr, align 8
4916 // CHECK11-NEXT:    [[__END1:%.*]] = alloca ptr, align 8
4917 // CHECK11-NEXT:    [[__RANGE2:%.*]] = alloca ptr, align 8
4918 // CHECK11-NEXT:    [[__END2:%.*]] = alloca ptr, align 8
4919 // CHECK11-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca ptr, align 8
4920 // CHECK11-NEXT:    [[DOTCAPTURE_EXPR_5:%.*]] = alloca ptr, align 8
4921 // CHECK11-NEXT:    [[DOTCAPTURE_EXPR_6:%.*]] = alloca ptr, align 8
4922 // CHECK11-NEXT:    [[DOTCAPTURE_EXPR_8:%.*]] = alloca ptr, align 8
4923 // CHECK11-NEXT:    [[DOTCAPTURE_EXPR_9:%.*]] = alloca i64, align 8
4924 // CHECK11-NEXT:    [[__BEGIN1:%.*]] = alloca ptr, align 8
4925 // CHECK11-NEXT:    [[__BEGIN2:%.*]] = alloca ptr, align 8
4926 // CHECK11-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
4927 // CHECK11-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
4928 // CHECK11-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
4929 // CHECK11-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4930 // CHECK11-NEXT:    [[__BEGIN119:%.*]] = alloca ptr, align 8
4931 // CHECK11-NEXT:    [[__BEGIN220:%.*]] = alloca ptr, align 8
4932 // CHECK11-NEXT:    [[A:%.*]] = alloca ptr, align 8
4933 // CHECK11-NEXT:    [[B:%.*]] = alloca i32, align 4
4934 // CHECK11-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
4935 // CHECK11-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
4936 // CHECK11-NEXT:    store ptr [[ARR]], ptr [[ARR_ADDR]], align 8
4937 // CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[ARR_ADDR]], align 8
4938 // CHECK11-NEXT:    store ptr [[TMP0]], ptr [[__RANGE1]], align 8
4939 // CHECK11-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[__RANGE1]], align 8
4940 // CHECK11-NEXT:    [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP1]], i64 0, i64 0
4941 // CHECK11-NEXT:    [[ADD_PTR:%.*]] = getelementptr inbounds i32, ptr [[ARRAYDECAY]], i64 10
4942 // CHECK11-NEXT:    store ptr [[ADD_PTR]], ptr [[__END1]], align 8
4943 // CHECK11-NEXT:    store ptr [[TMP0]], ptr [[__RANGE2]], align 8
4944 // CHECK11-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[__RANGE2]], align 8
4945 // CHECK11-NEXT:    [[ARRAYDECAY2:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP2]], i64 0, i64 0
4946 // CHECK11-NEXT:    [[ADD_PTR3:%.*]] = getelementptr inbounds i32, ptr [[ARRAYDECAY2]], i64 10
4947 // CHECK11-NEXT:    store ptr [[ADD_PTR3]], ptr [[__END2]], align 8
4948 // CHECK11-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[__RANGE1]], align 8
4949 // CHECK11-NEXT:    [[ARRAYDECAY4:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP3]], i64 0, i64 0
4950 // CHECK11-NEXT:    store ptr [[ARRAYDECAY4]], ptr [[DOTCAPTURE_EXPR_]], align 8
4951 // CHECK11-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[__END1]], align 8
4952 // CHECK11-NEXT:    store ptr [[TMP4]], ptr [[DOTCAPTURE_EXPR_5]], align 8
4953 // CHECK11-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[__RANGE2]], align 8
4954 // CHECK11-NEXT:    [[ARRAYDECAY7:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP5]], i64 0, i64 0
4955 // CHECK11-NEXT:    store ptr [[ARRAYDECAY7]], ptr [[DOTCAPTURE_EXPR_6]], align 8
4956 // CHECK11-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[__END2]], align 8
4957 // CHECK11-NEXT:    store ptr [[TMP6]], ptr [[DOTCAPTURE_EXPR_8]], align 8
4958 // CHECK11-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_5]], align 8
4959 // CHECK11-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_]], align 8
4960 // CHECK11-NEXT:    [[SUB_PTR_LHS_CAST:%.*]] = ptrtoint ptr [[TMP7]] to i64
4961 // CHECK11-NEXT:    [[SUB_PTR_RHS_CAST:%.*]] = ptrtoint ptr [[TMP8]] to i64
4962 // CHECK11-NEXT:    [[SUB_PTR_SUB:%.*]] = sub i64 [[SUB_PTR_LHS_CAST]], [[SUB_PTR_RHS_CAST]]
4963 // CHECK11-NEXT:    [[SUB_PTR_DIV:%.*]] = sdiv exact i64 [[SUB_PTR_SUB]], 4
4964 // CHECK11-NEXT:    [[SUB:%.*]] = sub nsw i64 [[SUB_PTR_DIV]], 1
4965 // CHECK11-NEXT:    [[ADD:%.*]] = add nsw i64 [[SUB]], 1
4966 // CHECK11-NEXT:    [[DIV:%.*]] = sdiv i64 [[ADD]], 1
4967 // CHECK11-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_8]], align 8
4968 // CHECK11-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_6]], align 8
4969 // CHECK11-NEXT:    [[SUB_PTR_LHS_CAST10:%.*]] = ptrtoint ptr [[TMP9]] to i64
4970 // CHECK11-NEXT:    [[SUB_PTR_RHS_CAST11:%.*]] = ptrtoint ptr [[TMP10]] to i64
4971 // CHECK11-NEXT:    [[SUB_PTR_SUB12:%.*]] = sub i64 [[SUB_PTR_LHS_CAST10]], [[SUB_PTR_RHS_CAST11]]
4972 // CHECK11-NEXT:    [[SUB_PTR_DIV13:%.*]] = sdiv exact i64 [[SUB_PTR_SUB12]], 4
4973 // CHECK11-NEXT:    [[SUB14:%.*]] = sub nsw i64 [[SUB_PTR_DIV13]], 1
4974 // CHECK11-NEXT:    [[ADD15:%.*]] = add nsw i64 [[SUB14]], 1
4975 // CHECK11-NEXT:    [[DIV16:%.*]] = sdiv i64 [[ADD15]], 1
4976 // CHECK11-NEXT:    [[MUL:%.*]] = mul nsw i64 [[DIV]], [[DIV16]]
4977 // CHECK11-NEXT:    [[SUB17:%.*]] = sub nsw i64 [[MUL]], 1
4978 // CHECK11-NEXT:    store i64 [[SUB17]], ptr [[DOTCAPTURE_EXPR_9]], align 8
4979 // CHECK11-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_]], align 8
4980 // CHECK11-NEXT:    store ptr [[TMP11]], ptr [[__BEGIN1]], align 8
4981 // CHECK11-NEXT:    [[TMP12:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_6]], align 8
4982 // CHECK11-NEXT:    store ptr [[TMP12]], ptr [[__BEGIN2]], align 8
4983 // CHECK11-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_]], align 8
4984 // CHECK11-NEXT:    [[TMP14:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_5]], align 8
4985 // CHECK11-NEXT:    [[CMP:%.*]] = icmp ult ptr [[TMP13]], [[TMP14]]
4986 // CHECK11-NEXT:    br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]]
4987 // CHECK11:       land.lhs.true:
4988 // CHECK11-NEXT:    [[TMP15:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_6]], align 8
4989 // CHECK11-NEXT:    [[TMP16:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_8]], align 8
4990 // CHECK11-NEXT:    [[CMP18:%.*]] = icmp ult ptr [[TMP15]], [[TMP16]]
4991 // CHECK11-NEXT:    br i1 [[CMP18]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]]
4992 // CHECK11:       omp.precond.then:
4993 // CHECK11-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8
4994 // CHECK11-NEXT:    [[TMP17:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_9]], align 8
4995 // CHECK11-NEXT:    store i64 [[TMP17]], ptr [[DOTOMP_UB]], align 8
4996 // CHECK11-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8
4997 // CHECK11-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
4998 // CHECK11-NEXT:    [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
4999 // CHECK11-NEXT:    [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4
5000 // CHECK11-NEXT:    call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP19]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
5001 // CHECK11-NEXT:    [[TMP20:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
5002 // CHECK11-NEXT:    [[TMP21:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_9]], align 8
5003 // CHECK11-NEXT:    [[CMP21:%.*]] = icmp sgt i64 [[TMP20]], [[TMP21]]
5004 // CHECK11-NEXT:    br i1 [[CMP21]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
5005 // CHECK11:       cond.true:
5006 // CHECK11-NEXT:    [[TMP22:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_9]], align 8
5007 // CHECK11-NEXT:    br label [[COND_END:%.*]]
5008 // CHECK11:       cond.false:
5009 // CHECK11-NEXT:    [[TMP23:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
5010 // CHECK11-NEXT:    br label [[COND_END]]
5011 // CHECK11:       cond.end:
5012 // CHECK11-NEXT:    [[COND:%.*]] = phi i64 [ [[TMP22]], [[COND_TRUE]] ], [ [[TMP23]], [[COND_FALSE]] ]
5013 // CHECK11-NEXT:    store i64 [[COND]], ptr [[DOTOMP_UB]], align 8
5014 // CHECK11-NEXT:    [[TMP24:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
5015 // CHECK11-NEXT:    store i64 [[TMP24]], ptr [[DOTOMP_IV]], align 8
5016 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
5017 // CHECK11:       omp.inner.for.cond:
5018 // CHECK11-NEXT:    [[TMP25:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
5019 // CHECK11-NEXT:    [[TMP26:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
5020 // CHECK11-NEXT:    [[CMP22:%.*]] = icmp sle i64 [[TMP25]], [[TMP26]]
5021 // CHECK11-NEXT:    br i1 [[CMP22]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5022 // CHECK11:       omp.inner.for.body:
5023 // CHECK11-NEXT:    [[TMP27:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_]], align 8
5024 // CHECK11-NEXT:    [[TMP28:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
5025 // CHECK11-NEXT:    [[TMP29:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_8]], align 8
5026 // CHECK11-NEXT:    [[TMP30:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_6]], align 8
5027 // CHECK11-NEXT:    [[SUB_PTR_LHS_CAST23:%.*]] = ptrtoint ptr [[TMP29]] to i64
5028 // CHECK11-NEXT:    [[SUB_PTR_RHS_CAST24:%.*]] = ptrtoint ptr [[TMP30]] to i64
5029 // CHECK11-NEXT:    [[SUB_PTR_SUB25:%.*]] = sub i64 [[SUB_PTR_LHS_CAST23]], [[SUB_PTR_RHS_CAST24]]
5030 // CHECK11-NEXT:    [[SUB_PTR_DIV26:%.*]] = sdiv exact i64 [[SUB_PTR_SUB25]], 4
5031 // CHECK11-NEXT:    [[SUB27:%.*]] = sub nsw i64 [[SUB_PTR_DIV26]], 1
5032 // CHECK11-NEXT:    [[ADD28:%.*]] = add nsw i64 [[SUB27]], 1
5033 // CHECK11-NEXT:    [[DIV29:%.*]] = sdiv i64 [[ADD28]], 1
5034 // CHECK11-NEXT:    [[MUL30:%.*]] = mul nsw i64 1, [[DIV29]]
5035 // CHECK11-NEXT:    [[DIV31:%.*]] = sdiv i64 [[TMP28]], [[MUL30]]
5036 // CHECK11-NEXT:    [[MUL32:%.*]] = mul nsw i64 [[DIV31]], 1
5037 // CHECK11-NEXT:    [[ADD_PTR33:%.*]] = getelementptr inbounds i32, ptr [[TMP27]], i64 [[MUL32]]
5038 // CHECK11-NEXT:    store ptr [[ADD_PTR33]], ptr [[__BEGIN119]], align 8
5039 // CHECK11-NEXT:    [[TMP31:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_6]], align 8
5040 // CHECK11-NEXT:    [[TMP32:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
5041 // CHECK11-NEXT:    [[TMP33:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
5042 // CHECK11-NEXT:    [[TMP34:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_8]], align 8
5043 // CHECK11-NEXT:    [[TMP35:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_6]], align 8
5044 // CHECK11-NEXT:    [[SUB_PTR_LHS_CAST34:%.*]] = ptrtoint ptr [[TMP34]] to i64
5045 // CHECK11-NEXT:    [[SUB_PTR_RHS_CAST35:%.*]] = ptrtoint ptr [[TMP35]] to i64
5046 // CHECK11-NEXT:    [[SUB_PTR_SUB36:%.*]] = sub i64 [[SUB_PTR_LHS_CAST34]], [[SUB_PTR_RHS_CAST35]]
5047 // CHECK11-NEXT:    [[SUB_PTR_DIV37:%.*]] = sdiv exact i64 [[SUB_PTR_SUB36]], 4
5048 // CHECK11-NEXT:    [[SUB38:%.*]] = sub nsw i64 [[SUB_PTR_DIV37]], 1
5049 // CHECK11-NEXT:    [[ADD39:%.*]] = add nsw i64 [[SUB38]], 1
5050 // CHECK11-NEXT:    [[DIV40:%.*]] = sdiv i64 [[ADD39]], 1
5051 // CHECK11-NEXT:    [[MUL41:%.*]] = mul nsw i64 1, [[DIV40]]
5052 // CHECK11-NEXT:    [[DIV42:%.*]] = sdiv i64 [[TMP33]], [[MUL41]]
5053 // CHECK11-NEXT:    [[TMP36:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_8]], align 8
5054 // CHECK11-NEXT:    [[TMP37:%.*]] = load ptr, ptr [[DOTCAPTURE_EXPR_6]], align 8
5055 // CHECK11-NEXT:    [[SUB_PTR_LHS_CAST43:%.*]] = ptrtoint ptr [[TMP36]] to i64
5056 // CHECK11-NEXT:    [[SUB_PTR_RHS_CAST44:%.*]] = ptrtoint ptr [[TMP37]] to i64
5057 // CHECK11-NEXT:    [[SUB_PTR_SUB45:%.*]] = sub i64 [[SUB_PTR_LHS_CAST43]], [[SUB_PTR_RHS_CAST44]]
5058 // CHECK11-NEXT:    [[SUB_PTR_DIV46:%.*]] = sdiv exact i64 [[SUB_PTR_SUB45]], 4
5059 // CHECK11-NEXT:    [[SUB47:%.*]] = sub nsw i64 [[SUB_PTR_DIV46]], 1
5060 // CHECK11-NEXT:    [[ADD48:%.*]] = add nsw i64 [[SUB47]], 1
5061 // CHECK11-NEXT:    [[DIV49:%.*]] = sdiv i64 [[ADD48]], 1
5062 // CHECK11-NEXT:    [[MUL50:%.*]] = mul nsw i64 1, [[DIV49]]
5063 // CHECK11-NEXT:    [[MUL51:%.*]] = mul nsw i64 [[DIV42]], [[MUL50]]
5064 // CHECK11-NEXT:    [[SUB52:%.*]] = sub nsw i64 [[TMP32]], [[MUL51]]
5065 // CHECK11-NEXT:    [[MUL53:%.*]] = mul nsw i64 [[SUB52]], 1
5066 // CHECK11-NEXT:    [[ADD_PTR54:%.*]] = getelementptr inbounds i32, ptr [[TMP31]], i64 [[MUL53]]
5067 // CHECK11-NEXT:    store ptr [[ADD_PTR54]], ptr [[__BEGIN220]], align 8
5068 // CHECK11-NEXT:    [[TMP38:%.*]] = load ptr, ptr [[__BEGIN119]], align 8
5069 // CHECK11-NEXT:    store ptr [[TMP38]], ptr [[A]], align 8
5070 // CHECK11-NEXT:    [[TMP39:%.*]] = load ptr, ptr [[__BEGIN220]], align 8
5071 // CHECK11-NEXT:    [[TMP40:%.*]] = load i32, ptr [[TMP39]], align 4
5072 // CHECK11-NEXT:    store i32 [[TMP40]], ptr [[B]], align 4
5073 // CHECK11-NEXT:    [[TMP41:%.*]] = load i32, ptr [[B]], align 4
5074 // CHECK11-NEXT:    [[TMP42:%.*]] = load ptr, ptr [[A]], align 8
5075 // CHECK11-NEXT:    store i32 [[TMP41]], ptr [[TMP42]], align 4
5076 // CHECK11-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
5077 // CHECK11:       omp.body.continue:
5078 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
5079 // CHECK11:       omp.inner.for.inc:
5080 // CHECK11-NEXT:    [[TMP43:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
5081 // CHECK11-NEXT:    [[ADD55:%.*]] = add nsw i64 [[TMP43]], 1
5082 // CHECK11-NEXT:    store i64 [[ADD55]], ptr [[DOTOMP_IV]], align 8
5083 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND]]
5084 // CHECK11:       omp.inner.for.end:
5085 // CHECK11-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
5086 // CHECK11:       omp.loop.exit:
5087 // CHECK11-NEXT:    [[TMP44:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
5088 // CHECK11-NEXT:    [[TMP45:%.*]] = load i32, ptr [[TMP44]], align 4
5089 // CHECK11-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP45]])
5090 // CHECK11-NEXT:    br label [[OMP_PRECOND_END]]
5091 // CHECK11:       omp.precond.end:
5092 // CHECK11-NEXT:    ret void
5093 //