clang/test/OpenMP/target_codegen_global_capture.cpp

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
   2 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1
   3 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
   4 // RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1
   5 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3
   6 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
   7 // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3
   8
   9 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  10 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
  11 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  12 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  13 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
  14 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  15 // expected-no-diagnostics
  16 #ifndef HEADER
  17 #define HEADER
  18
  19
  20
  21 double Ga = 1.0;
  22 double Gb = 2.0;
  23 double Gc = 3.0;
  24 double Gd = 4.0;
  25
  26 int foo(short a, short b, short c, short d){
  27   static float Sa = 5.0;
  28   static float Sb = 6.0;
  29   static float Sc = 7.0;
  30   static float Sd = 8.0;
  31
  32
  33   // 3 local vars being captured.
  34
  35
  36
  37
  38   // 3 static vars being captured.
  39
  40
  41
  42
  43   // 3 static global vars being captured.
  44
  45
  46
  47
  48   // Capture b, Gb, Sb, Gc, c, Sc, d, Gd, Sd
  49   #pragma omp target if(Ga>0.0 && a>0 && Sa>0.0)
  50   {
  51     b += 1;
  52     Gb += 1.0;
  53     Sb += 1.0;
  54
  55     // The parallel region only uses 3 captures.
  56     // Capture d, Gd, Sd,
  57
  58     #pragma omp parallel if(Gc>0.0 && c>0 && Sc>0.0)
  59     {
  60       d += 1;
  61       Gd += 1.0;
  62       Sd += 1.0;
  63     }
  64   }
  65   return a + b + c + d + (int)Sa + (int)Sb + (int)Sc + (int)Sd;
  66 }
  67
  68 int bar(short a, short b, short c, short d){
  69   static float Sa = 9.0;
  70   static float Sb = 10.0;
  71   static float Sc = 11.0;
  72   static float Sd = 12.0;
  73
  74   // Capture a, b, c, d
  75   #pragma omp parallel
  76   {
  77
  78     // 3 local vars being captured.
  79
  80
  81
  82
  83     // 3 static vars being captured.
  84
  85
  86
  87
  88     // 3 static global vars being captured.
  89
  90
  91
  92
  93     // Capture b, Gb, Sb, Gc, c, Sc, d, Gd, Sd
  94     #pragma omp target if(Ga>0.0 && a>0 && Sa>0.0)
  95     {
  96       b += 1;
  97       Gb += 1.0;
  98       Sb += 1.0;
  99
 100
 101       // Capture d, Gd, Sd
 102       #pragma omp parallel if(Gc>0.0 && c>0 && Sc>0.0)
 103       {
 104         d += 1;
 105         Gd += 1.0;
 106         Sd += 1.0;
 107       }
 108     }
 109   }
 110   return a + b + c + d + (int)Sa + (int)Sb + (int)Sc + (int)Sd;
 111 }
 112
 113 ///
 114 /// Tests with template functions.
 115 ///
 116
 117
 118 template<typename T>
 119 int tbar(T a, T b, T c, T d){
 120   static float Sa = 17.0;
 121   static float Sb = 18.0;
 122   static float Sc = 19.0;
 123   static float Sd = 20.0;
 124
 125   // Capture a, b, c, d
 126   #pragma omp parallel
 127   {
 128
 129     // 3 local vars being captured.
 130
 131
 132
 133
 134     // 3 static vars being captured.
 135
 136
 137
 138
 139     // 3 static global vars being captured.
 140
 141
 142
 143
 144     // Capture b, Gb, Sb, Gc, c, Sc, d, Gd, Sd
 145     #pragma omp target if(Ga>0.0 && a>0 && Sa>0.0)
 146     {
 147       b += 1;
 148       Gb += 1.0;
 149       Sb += 1.0;
 150
 151
 152       // Capture d, Gd, Sd
 153       #pragma omp parallel if(Gc>0.0 && c>0 && Sc>0.0)
 154       {
 155         d += 1;
 156         Gd += 1.0;
 157         Sd += 1.0;
 158       }
 159     }
 160   }
 161   return a + b + c + d + (int)Sa + (int)Sb + (int)Sc + (int)Sd;
 162 }
 163
 164 int tbar2(short a, short b, short c, short d){
 165   return tbar(a, b, c, d);
 166 }
 167
 168 #endif
 169 // CHECK1-LABEL: define {{[^@]+}}@_Z3foossss
 170 // CHECK1-SAME: (i16 noundef signext [[A:%.*]], i16 noundef signext [[B:%.*]], i16 noundef signext [[C:%.*]], i16 noundef signext [[D:%.*]]) #[[ATTR0:[0-9]+]] {
 171 // CHECK1-NEXT:  entry:
 172 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i16, align 2
 173 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca i16, align 2
 174 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca i16, align 2
 175 // CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca i16, align 2
 176 // CHECK1-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
 177 // CHECK1-NEXT:    [[GB_CASTED:%.*]] = alloca i64, align 8
 178 // CHECK1-NEXT:    [[SB_CASTED:%.*]] = alloca i64, align 8
 179 // CHECK1-NEXT:    [[GC_CASTED:%.*]] = alloca i64, align 8
 180 // CHECK1-NEXT:    [[C_CASTED:%.*]] = alloca i64, align 8
 181 // CHECK1-NEXT:    [[SC_CASTED:%.*]] = alloca i64, align 8
 182 // CHECK1-NEXT:    [[D_CASTED:%.*]] = alloca i64, align 8
 183 // CHECK1-NEXT:    [[GD_CASTED:%.*]] = alloca i64, align 8
 184 // CHECK1-NEXT:    [[SD_CASTED:%.*]] = alloca i64, align 8
 185 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [9 x ptr], align 8
 186 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [9 x ptr], align 8
 187 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [9 x ptr], align 8
 188 // CHECK1-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
 189 // CHECK1-NEXT:    store i16 [[A]], ptr [[A_ADDR]], align 2
 190 // CHECK1-NEXT:    store i16 [[B]], ptr [[B_ADDR]], align 2
 191 // CHECK1-NEXT:    store i16 [[C]], ptr [[C_ADDR]], align 2
 192 // CHECK1-NEXT:    store i16 [[D]], ptr [[D_ADDR]], align 2
 193 // CHECK1-NEXT:    [[TMP0:%.*]] = load i16, ptr [[B_ADDR]], align 2
 194 // CHECK1-NEXT:    store i16 [[TMP0]], ptr [[B_CASTED]], align 2
 195 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[B_CASTED]], align 8
 196 // CHECK1-NEXT:    [[TMP2:%.*]] = load double, ptr @Gb, align 8
 197 // CHECK1-NEXT:    store double [[TMP2]], ptr [[GB_CASTED]], align 8
 198 // CHECK1-NEXT:    [[TMP3:%.*]] = load i64, ptr [[GB_CASTED]], align 8
 199 // CHECK1-NEXT:    [[TMP4:%.*]] = load float, ptr @_ZZ3foossssE2Sb, align 4
 200 // CHECK1-NEXT:    store float [[TMP4]], ptr [[SB_CASTED]], align 4
 201 // CHECK1-NEXT:    [[TMP5:%.*]] = load i64, ptr [[SB_CASTED]], align 8
 202 // CHECK1-NEXT:    [[TMP6:%.*]] = load double, ptr @Gc, align 8
 203 // CHECK1-NEXT:    store double [[TMP6]], ptr [[GC_CASTED]], align 8
 204 // CHECK1-NEXT:    [[TMP7:%.*]] = load i64, ptr [[GC_CASTED]], align 8
 205 // CHECK1-NEXT:    [[TMP8:%.*]] = load i16, ptr [[C_ADDR]], align 2
 206 // CHECK1-NEXT:    store i16 [[TMP8]], ptr [[C_CASTED]], align 2
 207 // CHECK1-NEXT:    [[TMP9:%.*]] = load i64, ptr [[C_CASTED]], align 8
 208 // CHECK1-NEXT:    [[TMP10:%.*]] = load float, ptr @_ZZ3foossssE2Sc, align 4
 209 // CHECK1-NEXT:    store float [[TMP10]], ptr [[SC_CASTED]], align 4
 210 // CHECK1-NEXT:    [[TMP11:%.*]] = load i64, ptr [[SC_CASTED]], align 8
 211 // CHECK1-NEXT:    [[TMP12:%.*]] = load i16, ptr [[D_ADDR]], align 2
 212 // CHECK1-NEXT:    store i16 [[TMP12]], ptr [[D_CASTED]], align 2
 213 // CHECK1-NEXT:    [[TMP13:%.*]] = load i64, ptr [[D_CASTED]], align 8
 214 // CHECK1-NEXT:    [[TMP14:%.*]] = load double, ptr @Gd, align 8
 215 // CHECK1-NEXT:    store double [[TMP14]], ptr [[GD_CASTED]], align 8
 216 // CHECK1-NEXT:    [[TMP15:%.*]] = load i64, ptr [[GD_CASTED]], align 8
 217 // CHECK1-NEXT:    [[TMP16:%.*]] = load float, ptr @_ZZ3foossssE2Sd, align 4
 218 // CHECK1-NEXT:    store float [[TMP16]], ptr [[SD_CASTED]], align 4
 219 // CHECK1-NEXT:    [[TMP17:%.*]] = load i64, ptr [[SD_CASTED]], align 8
 220 // CHECK1-NEXT:    [[TMP18:%.*]] = load double, ptr @Ga, align 8
 221 // CHECK1-NEXT:    [[CMP:%.*]] = fcmp ogt double [[TMP18]], 0.000000e+00
 222 // CHECK1-NEXT:    br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
 223 // CHECK1:       land.lhs.true:
 224 // CHECK1-NEXT:    [[TMP19:%.*]] = load i16, ptr [[A_ADDR]], align 2
 225 // CHECK1-NEXT:    [[CONV:%.*]] = sext i16 [[TMP19]] to i32
 226 // CHECK1-NEXT:    [[CMP1:%.*]] = icmp sgt i32 [[CONV]], 0
 227 // CHECK1-NEXT:    br i1 [[CMP1]], label [[LAND_LHS_TRUE2:%.*]], label [[OMP_IF_ELSE]]
 228 // CHECK1:       land.lhs.true2:
 229 // CHECK1-NEXT:    [[TMP20:%.*]] = load float, ptr @_ZZ3foossssE2Sa, align 4
 230 // CHECK1-NEXT:    [[CONV3:%.*]] = fpext float [[TMP20]] to double
 231 // CHECK1-NEXT:    [[CMP4:%.*]] = fcmp ogt double [[CONV3]], 0.000000e+00
 232 // CHECK1-NEXT:    br i1 [[CMP4]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]]
 233 // CHECK1:       omp_if.then:
 234 // CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
 235 // CHECK1-NEXT:    store i64 [[TMP1]], ptr [[TMP21]], align 8
 236 // CHECK1-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
 237 // CHECK1-NEXT:    store i64 [[TMP1]], ptr [[TMP22]], align 8
 238 // CHECK1-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
 239 // CHECK1-NEXT:    store ptr null, ptr [[TMP23]], align 8
 240 // CHECK1-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
 241 // CHECK1-NEXT:    store i64 [[TMP3]], ptr [[TMP24]], align 8
 242 // CHECK1-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
 243 // CHECK1-NEXT:    store i64 [[TMP3]], ptr [[TMP25]], align 8
 244 // CHECK1-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
 245 // CHECK1-NEXT:    store ptr null, ptr [[TMP26]], align 8
 246 // CHECK1-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
 247 // CHECK1-NEXT:    store i64 [[TMP5]], ptr [[TMP27]], align 8
 248 // CHECK1-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
 249 // CHECK1-NEXT:    store i64 [[TMP5]], ptr [[TMP28]], align 8
 250 // CHECK1-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
 251 // CHECK1-NEXT:    store ptr null, ptr [[TMP29]], align 8
 252 // CHECK1-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
 253 // CHECK1-NEXT:    store i64 [[TMP7]], ptr [[TMP30]], align 8
 254 // CHECK1-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
 255 // CHECK1-NEXT:    store i64 [[TMP7]], ptr [[TMP31]], align 8
 256 // CHECK1-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
 257 // CHECK1-NEXT:    store ptr null, ptr [[TMP32]], align 8
 258 // CHECK1-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
 259 // CHECK1-NEXT:    store i64 [[TMP9]], ptr [[TMP33]], align 8
 260 // CHECK1-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4
 261 // CHECK1-NEXT:    store i64 [[TMP9]], ptr [[TMP34]], align 8
 262 // CHECK1-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
 263 // CHECK1-NEXT:    store ptr null, ptr [[TMP35]], align 8
 264 // CHECK1-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5
 265 // CHECK1-NEXT:    store i64 [[TMP11]], ptr [[TMP36]], align 8
 266 // CHECK1-NEXT:    [[TMP37:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 5
 267 // CHECK1-NEXT:    store i64 [[TMP11]], ptr [[TMP37]], align 8
 268 // CHECK1-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 5
 269 // CHECK1-NEXT:    store ptr null, ptr [[TMP38]], align 8
 270 // CHECK1-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6
 271 // CHECK1-NEXT:    store i64 [[TMP13]], ptr [[TMP39]], align 8
 272 // CHECK1-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 6
 273 // CHECK1-NEXT:    store i64 [[TMP13]], ptr [[TMP40]], align 8
 274 // CHECK1-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 6
 275 // CHECK1-NEXT:    store ptr null, ptr [[TMP41]], align 8
 276 // CHECK1-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7
 277 // CHECK1-NEXT:    store i64 [[TMP15]], ptr [[TMP42]], align 8
 278 // CHECK1-NEXT:    [[TMP43:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 7
 279 // CHECK1-NEXT:    store i64 [[TMP15]], ptr [[TMP43]], align 8
 280 // CHECK1-NEXT:    [[TMP44:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 7
 281 // CHECK1-NEXT:    store ptr null, ptr [[TMP44]], align 8
 282 // CHECK1-NEXT:    [[TMP45:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 8
 283 // CHECK1-NEXT:    store i64 [[TMP17]], ptr [[TMP45]], align 8
 284 // CHECK1-NEXT:    [[TMP46:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 8
 285 // CHECK1-NEXT:    store i64 [[TMP17]], ptr [[TMP46]], align 8
 286 // CHECK1-NEXT:    [[TMP47:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 8
 287 // CHECK1-NEXT:    store ptr null, ptr [[TMP47]], align 8
 288 // CHECK1-NEXT:    [[TMP48:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
 289 // CHECK1-NEXT:    [[TMP49:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
 290 // CHECK1-NEXT:    [[TMP50:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
 291 // CHECK1-NEXT:    store i32 2, ptr [[TMP50]], align 4
 292 // CHECK1-NEXT:    [[TMP51:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
 293 // CHECK1-NEXT:    store i32 9, ptr [[TMP51]], align 4
 294 // CHECK1-NEXT:    [[TMP52:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
 295 // CHECK1-NEXT:    store ptr [[TMP48]], ptr [[TMP52]], align 8
 296 // CHECK1-NEXT:    [[TMP53:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
 297 // CHECK1-NEXT:    store ptr [[TMP49]], ptr [[TMP53]], align 8
 298 // CHECK1-NEXT:    [[TMP54:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
 299 // CHECK1-NEXT:    store ptr @.offload_sizes, ptr [[TMP54]], align 8
 300 // CHECK1-NEXT:    [[TMP55:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
 301 // CHECK1-NEXT:    store ptr @.offload_maptypes, ptr [[TMP55]], align 8
 302 // CHECK1-NEXT:    [[TMP56:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
 303 // CHECK1-NEXT:    store ptr null, ptr [[TMP56]], align 8
 304 // CHECK1-NEXT:    [[TMP57:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
 305 // CHECK1-NEXT:    store ptr null, ptr [[TMP57]], align 8
 306 // CHECK1-NEXT:    [[TMP58:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
 307 // CHECK1-NEXT:    store i64 0, ptr [[TMP58]], align 8
 308 // CHECK1-NEXT:    [[TMP59:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
 309 // CHECK1-NEXT:    store i64 0, ptr [[TMP59]], align 8
 310 // CHECK1-NEXT:    [[TMP60:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
 311 // CHECK1-NEXT:    store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP60]], align 4
 312 // CHECK1-NEXT:    [[TMP61:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
 313 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP61]], align 4
 314 // CHECK1-NEXT:    [[TMP62:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
 315 // CHECK1-NEXT:    store i32 0, ptr [[TMP62]], align 4
 316 // CHECK1-NEXT:    [[TMP63:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1:[0-9]+]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foossss_l49.region_id, ptr [[KERNEL_ARGS]])
 317 // CHECK1-NEXT:    [[TMP64:%.*]] = icmp ne i32 [[TMP63]], 0
 318 // CHECK1-NEXT:    br i1 [[TMP64]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
 319 // CHECK1:       omp_offload.failed:
 320 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foossss_l49(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]], i64 [[TMP15]], i64 [[TMP17]]) #[[ATTR2:[0-9]+]]
 321 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
 322 // CHECK1:       omp_offload.cont:
 323 // CHECK1-NEXT:    br label [[OMP_IF_END:%.*]]
 324 // CHECK1:       omp_if.else:
 325 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foossss_l49(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]], i64 [[TMP15]], i64 [[TMP17]]) #[[ATTR2]]
 326 // CHECK1-NEXT:    br label [[OMP_IF_END]]
 327 // CHECK1:       omp_if.end:
 328 // CHECK1-NEXT:    [[TMP65:%.*]] = load i16, ptr [[A_ADDR]], align 2
 329 // CHECK1-NEXT:    [[CONV5:%.*]] = sext i16 [[TMP65]] to i32
 330 // CHECK1-NEXT:    [[TMP66:%.*]] = load i16, ptr [[B_ADDR]], align 2
 331 // CHECK1-NEXT:    [[CONV6:%.*]] = sext i16 [[TMP66]] to i32
 332 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV5]], [[CONV6]]
 333 // CHECK1-NEXT:    [[TMP67:%.*]] = load i16, ptr [[C_ADDR]], align 2
 334 // CHECK1-NEXT:    [[CONV7:%.*]] = sext i16 [[TMP67]] to i32
 335 // CHECK1-NEXT:    [[ADD8:%.*]] = add nsw i32 [[ADD]], [[CONV7]]
 336 // CHECK1-NEXT:    [[TMP68:%.*]] = load i16, ptr [[D_ADDR]], align 2
 337 // CHECK1-NEXT:    [[CONV9:%.*]] = sext i16 [[TMP68]] to i32
 338 // CHECK1-NEXT:    [[ADD10:%.*]] = add nsw i32 [[ADD8]], [[CONV9]]
 339 // CHECK1-NEXT:    [[TMP69:%.*]] = load float, ptr @_ZZ3foossssE2Sa, align 4
 340 // CHECK1-NEXT:    [[CONV11:%.*]] = fptosi float [[TMP69]] to i32
 341 // CHECK1-NEXT:    [[ADD12:%.*]] = add nsw i32 [[ADD10]], [[CONV11]]
 342 // CHECK1-NEXT:    [[TMP70:%.*]] = load float, ptr @_ZZ3foossssE2Sb, align 4
 343 // CHECK1-NEXT:    [[CONV13:%.*]] = fptosi float [[TMP70]] to i32
 344 // CHECK1-NEXT:    [[ADD14:%.*]] = add nsw i32 [[ADD12]], [[CONV13]]
 345 // CHECK1-NEXT:    [[TMP71:%.*]] = load float, ptr @_ZZ3foossssE2Sc, align 4
 346 // CHECK1-NEXT:    [[CONV15:%.*]] = fptosi float [[TMP71]] to i32
 347 // CHECK1-NEXT:    [[ADD16:%.*]] = add nsw i32 [[ADD14]], [[CONV15]]
 348 // CHECK1-NEXT:    [[TMP72:%.*]] = load float, ptr @_ZZ3foossssE2Sd, align 4
 349 // CHECK1-NEXT:    [[CONV17:%.*]] = fptosi float [[TMP72]] to i32
 350 // CHECK1-NEXT:    [[ADD18:%.*]] = add nsw i32 [[ADD16]], [[CONV17]]
 351 // CHECK1-NEXT:    ret i32 [[ADD18]]
 352 //
 353 //
 354 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foossss_l49
 355 // CHECK1-SAME: (i64 noundef [[B:%.*]], i64 noundef [[GB:%.*]], i64 noundef [[SB:%.*]], i64 noundef [[GC:%.*]], i64 noundef [[C:%.*]], i64 noundef [[SC:%.*]], i64 noundef [[D:%.*]], i64 noundef [[GD:%.*]], i64 noundef [[SD:%.*]]) #[[ATTR1:[0-9]+]] {
 356 // CHECK1-NEXT:  entry:
 357 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
 358 // CHECK1-NEXT:    [[GB_ADDR:%.*]] = alloca i64, align 8
 359 // CHECK1-NEXT:    [[SB_ADDR:%.*]] = alloca i64, align 8
 360 // CHECK1-NEXT:    [[GC_ADDR:%.*]] = alloca i64, align 8
 361 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca i64, align 8
 362 // CHECK1-NEXT:    [[SC_ADDR:%.*]] = alloca i64, align 8
 363 // CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca i64, align 8
 364 // CHECK1-NEXT:    [[GD_ADDR:%.*]] = alloca i64, align 8
 365 // CHECK1-NEXT:    [[SD_ADDR:%.*]] = alloca i64, align 8
 366 // CHECK1-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
 367 // CHECK1-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
 368 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
 369 // CHECK1-NEXT:    store i64 [[B]], ptr [[B_ADDR]], align 8
 370 // CHECK1-NEXT:    store i64 [[GB]], ptr [[GB_ADDR]], align 8
 371 // CHECK1-NEXT:    store i64 [[SB]], ptr [[SB_ADDR]], align 8
 372 // CHECK1-NEXT:    store i64 [[GC]], ptr [[GC_ADDR]], align 8
 373 // CHECK1-NEXT:    store i64 [[C]], ptr [[C_ADDR]], align 8
 374 // CHECK1-NEXT:    store i64 [[SC]], ptr [[SC_ADDR]], align 8
 375 // CHECK1-NEXT:    store i64 [[D]], ptr [[D_ADDR]], align 8
 376 // CHECK1-NEXT:    store i64 [[GD]], ptr [[GD_ADDR]], align 8
 377 // CHECK1-NEXT:    store i64 [[SD]], ptr [[SD_ADDR]], align 8
 378 // CHECK1-NEXT:    [[TMP1:%.*]] = load i16, ptr [[B_ADDR]], align 2
 379 // CHECK1-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
 380 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV]], 1
 381 // CHECK1-NEXT:    [[CONV1:%.*]] = trunc i32 [[ADD]] to i16
 382 // CHECK1-NEXT:    store i16 [[CONV1]], ptr [[B_ADDR]], align 2
 383 // CHECK1-NEXT:    [[TMP2:%.*]] = load double, ptr [[GB_ADDR]], align 8
 384 // CHECK1-NEXT:    [[ADD2:%.*]] = fadd double [[TMP2]], 1.000000e+00
 385 // CHECK1-NEXT:    store double [[ADD2]], ptr [[GB_ADDR]], align 8
 386 // CHECK1-NEXT:    [[TMP3:%.*]] = load float, ptr [[SB_ADDR]], align 4
 387 // CHECK1-NEXT:    [[CONV3:%.*]] = fpext float [[TMP3]] to double
 388 // CHECK1-NEXT:    [[ADD4:%.*]] = fadd double [[CONV3]], 1.000000e+00
 389 // CHECK1-NEXT:    [[CONV5:%.*]] = fptrunc double [[ADD4]] to float
 390 // CHECK1-NEXT:    store float [[CONV5]], ptr [[SB_ADDR]], align 4
 391 // CHECK1-NEXT:    [[TMP4:%.*]] = load double, ptr [[GC_ADDR]], align 8
 392 // CHECK1-NEXT:    [[CMP:%.*]] = fcmp ogt double [[TMP4]], 0.000000e+00
 393 // CHECK1-NEXT:    br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
 394 // CHECK1:       land.lhs.true:
 395 // CHECK1-NEXT:    [[TMP5:%.*]] = load i16, ptr [[C_ADDR]], align 2
 396 // CHECK1-NEXT:    [[CONV6:%.*]] = sext i16 [[TMP5]] to i32
 397 // CHECK1-NEXT:    [[CMP7:%.*]] = icmp sgt i32 [[CONV6]], 0
 398 // CHECK1-NEXT:    br i1 [[CMP7]], label [[LAND_LHS_TRUE8:%.*]], label [[OMP_IF_ELSE]]
 399 // CHECK1:       land.lhs.true8:
 400 // CHECK1-NEXT:    [[TMP6:%.*]] = load float, ptr [[SC_ADDR]], align 4
 401 // CHECK1-NEXT:    [[CONV9:%.*]] = fpext float [[TMP6]] to double
 402 // CHECK1-NEXT:    [[CMP10:%.*]] = fcmp ogt double [[CONV9]], 0.000000e+00
 403 // CHECK1-NEXT:    br i1 [[CMP10]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]]
 404 // CHECK1:       omp_if.then:
 405 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foossss_l49.omp_outlined, ptr [[D_ADDR]], ptr [[GD_ADDR]], ptr [[SD_ADDR]])
 406 // CHECK1-NEXT:    br label [[OMP_IF_END:%.*]]
 407 // CHECK1:       omp_if.else:
 408 // CHECK1-NEXT:    call void @__kmpc_serialized_parallel(ptr @[[GLOB1]], i32 [[TMP0]])
 409 // CHECK1-NEXT:    store i32 [[TMP0]], ptr [[DOTTHREADID_TEMP_]], align 4
 410 // CHECK1-NEXT:    store i32 0, ptr [[DOTBOUND_ZERO_ADDR]], align 4
 411 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foossss_l49.omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], ptr [[D_ADDR]], ptr [[GD_ADDR]], ptr [[SD_ADDR]]) #[[ATTR2]]
 412 // CHECK1-NEXT:    call void @__kmpc_end_serialized_parallel(ptr @[[GLOB1]], i32 [[TMP0]])
 413 // CHECK1-NEXT:    br label [[OMP_IF_END]]
 414 // CHECK1:       omp_if.end:
 415 // CHECK1-NEXT:    ret void
 416 //
 417 //
 418 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foossss_l49.omp_outlined
 419 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[D:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[GD:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SD:%.*]]) #[[ATTR1]] {
 420 // CHECK1-NEXT:  entry:
 421 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 422 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 423 // CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
 424 // CHECK1-NEXT:    [[GD_ADDR:%.*]] = alloca ptr, align 8
 425 // CHECK1-NEXT:    [[SD_ADDR:%.*]] = alloca ptr, align 8
 426 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 427 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 428 // CHECK1-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
 429 // CHECK1-NEXT:    store ptr [[GD]], ptr [[GD_ADDR]], align 8
 430 // CHECK1-NEXT:    store ptr [[SD]], ptr [[SD_ADDR]], align 8
 431 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8
 432 // CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[GD_ADDR]], align 8
 433 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[SD_ADDR]], align 8
 434 // CHECK1-NEXT:    [[TMP3:%.*]] = load i16, ptr [[TMP0]], align 2
 435 // CHECK1-NEXT:    [[CONV:%.*]] = sext i16 [[TMP3]] to i32
 436 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV]], 1
 437 // CHECK1-NEXT:    [[CONV1:%.*]] = trunc i32 [[ADD]] to i16
 438 // CHECK1-NEXT:    store i16 [[CONV1]], ptr [[TMP0]], align 2
 439 // CHECK1-NEXT:    [[TMP4:%.*]] = load double, ptr [[TMP1]], align 8
 440 // CHECK1-NEXT:    [[ADD2:%.*]] = fadd double [[TMP4]], 1.000000e+00
 441 // CHECK1-NEXT:    store double [[ADD2]], ptr [[TMP1]], align 8
 442 // CHECK1-NEXT:    [[TMP5:%.*]] = load float, ptr [[TMP2]], align 4
 443 // CHECK1-NEXT:    [[CONV3:%.*]] = fpext float [[TMP5]] to double
 444 // CHECK1-NEXT:    [[ADD4:%.*]] = fadd double [[CONV3]], 1.000000e+00
 445 // CHECK1-NEXT:    [[CONV5:%.*]] = fptrunc double [[ADD4]] to float
 446 // CHECK1-NEXT:    store float [[CONV5]], ptr [[TMP2]], align 4
 447 // CHECK1-NEXT:    ret void
 448 //
 449 //
 450 // CHECK1-LABEL: define {{[^@]+}}@_Z3barssss
 451 // CHECK1-SAME: (i16 noundef signext [[A:%.*]], i16 noundef signext [[B:%.*]], i16 noundef signext [[C:%.*]], i16 noundef signext [[D:%.*]]) #[[ATTR0]] {
 452 // CHECK1-NEXT:  entry:
 453 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i16, align 2
 454 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca i16, align 2
 455 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca i16, align 2
 456 // CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca i16, align 2
 457 // CHECK1-NEXT:    store i16 [[A]], ptr [[A_ADDR]], align 2
 458 // CHECK1-NEXT:    store i16 [[B]], ptr [[B_ADDR]], align 2
 459 // CHECK1-NEXT:    store i16 [[C]], ptr [[C_ADDR]], align 2
 460 // CHECK1-NEXT:    store i16 [[D]], ptr [[D_ADDR]], align 2
 461 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 4, ptr @_Z3barssss.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])
 462 // CHECK1-NEXT:    [[TMP0:%.*]] = load i16, ptr [[A_ADDR]], align 2
 463 // CHECK1-NEXT:    [[CONV:%.*]] = sext i16 [[TMP0]] to i32
 464 // CHECK1-NEXT:    [[TMP1:%.*]] = load i16, ptr [[B_ADDR]], align 2
 465 // CHECK1-NEXT:    [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
 466 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV]], [[CONV1]]
 467 // CHECK1-NEXT:    [[TMP2:%.*]] = load i16, ptr [[C_ADDR]], align 2
 468 // CHECK1-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
 469 // CHECK1-NEXT:    [[ADD3:%.*]] = add nsw i32 [[ADD]], [[CONV2]]
 470 // CHECK1-NEXT:    [[TMP3:%.*]] = load i16, ptr [[D_ADDR]], align 2
 471 // CHECK1-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP3]] to i32
 472 // CHECK1-NEXT:    [[ADD5:%.*]] = add nsw i32 [[ADD3]], [[CONV4]]
 473 // CHECK1-NEXT:    [[TMP4:%.*]] = load float, ptr @_ZZ3barssssE2Sa, align 4
 474 // CHECK1-NEXT:    [[CONV6:%.*]] = fptosi float [[TMP4]] to i32
 475 // CHECK1-NEXT:    [[ADD7:%.*]] = add nsw i32 [[ADD5]], [[CONV6]]
 476 // CHECK1-NEXT:    [[TMP5:%.*]] = load float, ptr @_ZZ3barssssE2Sb, align 4
 477 // CHECK1-NEXT:    [[CONV8:%.*]] = fptosi float [[TMP5]] to i32
 478 // CHECK1-NEXT:    [[ADD9:%.*]] = add nsw i32 [[ADD7]], [[CONV8]]
 479 // CHECK1-NEXT:    [[TMP6:%.*]] = load float, ptr @_ZZ3barssssE2Sc, align 4
 480 // CHECK1-NEXT:    [[CONV10:%.*]] = fptosi float [[TMP6]] to i32
 481 // CHECK1-NEXT:    [[ADD11:%.*]] = add nsw i32 [[ADD9]], [[CONV10]]
 482 // CHECK1-NEXT:    [[TMP7:%.*]] = load float, ptr @_ZZ3barssssE2Sd, align 4
 483 // CHECK1-NEXT:    [[CONV12:%.*]] = fptosi float [[TMP7]] to i32
 484 // CHECK1-NEXT:    [[ADD13:%.*]] = add nsw i32 [[ADD11]], [[CONV12]]
 485 // CHECK1-NEXT:    ret i32 [[ADD13]]
 486 //
 487 //
 488 // CHECK1-LABEL: define {{[^@]+}}@_Z3barssss.omp_outlined
 489 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[A:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[B:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[D:%.*]]) #[[ATTR1]] {
 490 // CHECK1-NEXT:  entry:
 491 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 492 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 493 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
 494 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
 495 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
 496 // CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
 497 // CHECK1-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
 498 // CHECK1-NEXT:    [[GB_CASTED:%.*]] = alloca i64, align 8
 499 // CHECK1-NEXT:    [[SB_CASTED:%.*]] = alloca i64, align 8
 500 // CHECK1-NEXT:    [[GC_CASTED:%.*]] = alloca i64, align 8
 501 // CHECK1-NEXT:    [[C_CASTED:%.*]] = alloca i64, align 8
 502 // CHECK1-NEXT:    [[SC_CASTED:%.*]] = alloca i64, align 8
 503 // CHECK1-NEXT:    [[D_CASTED:%.*]] = alloca i64, align 8
 504 // CHECK1-NEXT:    [[GD_CASTED:%.*]] = alloca i64, align 8
 505 // CHECK1-NEXT:    [[SD_CASTED:%.*]] = alloca i64, align 8
 506 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [9 x ptr], align 8
 507 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [9 x ptr], align 8
 508 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [9 x ptr], align 8
 509 // CHECK1-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
 510 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 511 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 512 // CHECK1-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
 513 // CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
 514 // CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
 515 // CHECK1-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
 516 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
 517 // CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
 518 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8
 519 // CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8
 520 // CHECK1-NEXT:    [[TMP4:%.*]] = load i16, ptr [[TMP1]], align 2
 521 // CHECK1-NEXT:    store i16 [[TMP4]], ptr [[B_CASTED]], align 2
 522 // CHECK1-NEXT:    [[TMP5:%.*]] = load i64, ptr [[B_CASTED]], align 8
 523 // CHECK1-NEXT:    [[TMP6:%.*]] = load double, ptr @Gb, align 8
 524 // CHECK1-NEXT:    store double [[TMP6]], ptr [[GB_CASTED]], align 8
 525 // CHECK1-NEXT:    [[TMP7:%.*]] = load i64, ptr [[GB_CASTED]], align 8
 526 // CHECK1-NEXT:    [[TMP8:%.*]] = load float, ptr @_ZZ3barssssE2Sb, align 4
 527 // CHECK1-NEXT:    store float [[TMP8]], ptr [[SB_CASTED]], align 4
 528 // CHECK1-NEXT:    [[TMP9:%.*]] = load i64, ptr [[SB_CASTED]], align 8
 529 // CHECK1-NEXT:    [[TMP10:%.*]] = load double, ptr @Gc, align 8
 530 // CHECK1-NEXT:    store double [[TMP10]], ptr [[GC_CASTED]], align 8
 531 // CHECK1-NEXT:    [[TMP11:%.*]] = load i64, ptr [[GC_CASTED]], align 8
 532 // CHECK1-NEXT:    [[TMP12:%.*]] = load i16, ptr [[TMP2]], align 2
 533 // CHECK1-NEXT:    store i16 [[TMP12]], ptr [[C_CASTED]], align 2
 534 // CHECK1-NEXT:    [[TMP13:%.*]] = load i64, ptr [[C_CASTED]], align 8
 535 // CHECK1-NEXT:    [[TMP14:%.*]] = load float, ptr @_ZZ3barssssE2Sc, align 4
 536 // CHECK1-NEXT:    store float [[TMP14]], ptr [[SC_CASTED]], align 4
 537 // CHECK1-NEXT:    [[TMP15:%.*]] = load i64, ptr [[SC_CASTED]], align 8
 538 // CHECK1-NEXT:    [[TMP16:%.*]] = load i16, ptr [[TMP3]], align 2
 539 // CHECK1-NEXT:    store i16 [[TMP16]], ptr [[D_CASTED]], align 2
 540 // CHECK1-NEXT:    [[TMP17:%.*]] = load i64, ptr [[D_CASTED]], align 8
 541 // CHECK1-NEXT:    [[TMP18:%.*]] = load double, ptr @Gd, align 8
 542 // CHECK1-NEXT:    store double [[TMP18]], ptr [[GD_CASTED]], align 8
 543 // CHECK1-NEXT:    [[TMP19:%.*]] = load i64, ptr [[GD_CASTED]], align 8
 544 // CHECK1-NEXT:    [[TMP20:%.*]] = load float, ptr @_ZZ3barssssE2Sd, align 4
 545 // CHECK1-NEXT:    store float [[TMP20]], ptr [[SD_CASTED]], align 4
 546 // CHECK1-NEXT:    [[TMP21:%.*]] = load i64, ptr [[SD_CASTED]], align 8
 547 // CHECK1-NEXT:    [[TMP22:%.*]] = load double, ptr @Ga, align 8
 548 // CHECK1-NEXT:    [[CMP:%.*]] = fcmp ogt double [[TMP22]], 0.000000e+00
 549 // CHECK1-NEXT:    br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
 550 // CHECK1:       land.lhs.true:
 551 // CHECK1-NEXT:    [[TMP23:%.*]] = load i16, ptr [[TMP0]], align 2
 552 // CHECK1-NEXT:    [[CONV:%.*]] = sext i16 [[TMP23]] to i32
 553 // CHECK1-NEXT:    [[CMP1:%.*]] = icmp sgt i32 [[CONV]], 0
 554 // CHECK1-NEXT:    br i1 [[CMP1]], label [[LAND_LHS_TRUE2:%.*]], label [[OMP_IF_ELSE]]
 555 // CHECK1:       land.lhs.true2:
 556 // CHECK1-NEXT:    [[TMP24:%.*]] = load float, ptr @_ZZ3barssssE2Sa, align 4
 557 // CHECK1-NEXT:    [[CONV3:%.*]] = fpext float [[TMP24]] to double
 558 // CHECK1-NEXT:    [[CMP4:%.*]] = fcmp ogt double [[CONV3]], 0.000000e+00
 559 // CHECK1-NEXT:    br i1 [[CMP4]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]]
 560 // CHECK1:       omp_if.then:
 561 // CHECK1-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
 562 // CHECK1-NEXT:    store i64 [[TMP5]], ptr [[TMP25]], align 8
 563 // CHECK1-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
 564 // CHECK1-NEXT:    store i64 [[TMP5]], ptr [[TMP26]], align 8
 565 // CHECK1-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
 566 // CHECK1-NEXT:    store ptr null, ptr [[TMP27]], align 8
 567 // CHECK1-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
 568 // CHECK1-NEXT:    store i64 [[TMP7]], ptr [[TMP28]], align 8
 569 // CHECK1-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
 570 // CHECK1-NEXT:    store i64 [[TMP7]], ptr [[TMP29]], align 8
 571 // CHECK1-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
 572 // CHECK1-NEXT:    store ptr null, ptr [[TMP30]], align 8
 573 // CHECK1-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
 574 // CHECK1-NEXT:    store i64 [[TMP9]], ptr [[TMP31]], align 8
 575 // CHECK1-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
 576 // CHECK1-NEXT:    store i64 [[TMP9]], ptr [[TMP32]], align 8
 577 // CHECK1-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
 578 // CHECK1-NEXT:    store ptr null, ptr [[TMP33]], align 8
 579 // CHECK1-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
 580 // CHECK1-NEXT:    store i64 [[TMP11]], ptr [[TMP34]], align 8
 581 // CHECK1-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
 582 // CHECK1-NEXT:    store i64 [[TMP11]], ptr [[TMP35]], align 8
 583 // CHECK1-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
 584 // CHECK1-NEXT:    store ptr null, ptr [[TMP36]], align 8
 585 // CHECK1-NEXT:    [[TMP37:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
 586 // CHECK1-NEXT:    store i64 [[TMP13]], ptr [[TMP37]], align 8
 587 // CHECK1-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4
 588 // CHECK1-NEXT:    store i64 [[TMP13]], ptr [[TMP38]], align 8
 589 // CHECK1-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
 590 // CHECK1-NEXT:    store ptr null, ptr [[TMP39]], align 8
 591 // CHECK1-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5
 592 // CHECK1-NEXT:    store i64 [[TMP15]], ptr [[TMP40]], align 8
 593 // CHECK1-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 5
 594 // CHECK1-NEXT:    store i64 [[TMP15]], ptr [[TMP41]], align 8
 595 // CHECK1-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 5
 596 // CHECK1-NEXT:    store ptr null, ptr [[TMP42]], align 8
 597 // CHECK1-NEXT:    [[TMP43:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6
 598 // CHECK1-NEXT:    store i64 [[TMP17]], ptr [[TMP43]], align 8
 599 // CHECK1-NEXT:    [[TMP44:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 6
 600 // CHECK1-NEXT:    store i64 [[TMP17]], ptr [[TMP44]], align 8
 601 // CHECK1-NEXT:    [[TMP45:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 6
 602 // CHECK1-NEXT:    store ptr null, ptr [[TMP45]], align 8
 603 // CHECK1-NEXT:    [[TMP46:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7
 604 // CHECK1-NEXT:    store i64 [[TMP19]], ptr [[TMP46]], align 8
 605 // CHECK1-NEXT:    [[TMP47:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 7
 606 // CHECK1-NEXT:    store i64 [[TMP19]], ptr [[TMP47]], align 8
 607 // CHECK1-NEXT:    [[TMP48:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 7
 608 // CHECK1-NEXT:    store ptr null, ptr [[TMP48]], align 8
 609 // CHECK1-NEXT:    [[TMP49:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 8
 610 // CHECK1-NEXT:    store i64 [[TMP21]], ptr [[TMP49]], align 8
 611 // CHECK1-NEXT:    [[TMP50:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 8
 612 // CHECK1-NEXT:    store i64 [[TMP21]], ptr [[TMP50]], align 8
 613 // CHECK1-NEXT:    [[TMP51:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 8
 614 // CHECK1-NEXT:    store ptr null, ptr [[TMP51]], align 8
 615 // CHECK1-NEXT:    [[TMP52:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
 616 // CHECK1-NEXT:    [[TMP53:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
 617 // CHECK1-NEXT:    [[TMP54:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
 618 // CHECK1-NEXT:    store i32 2, ptr [[TMP54]], align 4
 619 // CHECK1-NEXT:    [[TMP55:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
 620 // CHECK1-NEXT:    store i32 9, ptr [[TMP55]], align 4
 621 // CHECK1-NEXT:    [[TMP56:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
 622 // CHECK1-NEXT:    store ptr [[TMP52]], ptr [[TMP56]], align 8
 623 // CHECK1-NEXT:    [[TMP57:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
 624 // CHECK1-NEXT:    store ptr [[TMP53]], ptr [[TMP57]], align 8
 625 // CHECK1-NEXT:    [[TMP58:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
 626 // CHECK1-NEXT:    store ptr @.offload_sizes.1, ptr [[TMP58]], align 8
 627 // CHECK1-NEXT:    [[TMP59:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
 628 // CHECK1-NEXT:    store ptr @.offload_maptypes.2, ptr [[TMP59]], align 8
 629 // CHECK1-NEXT:    [[TMP60:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
 630 // CHECK1-NEXT:    store ptr null, ptr [[TMP60]], align 8
 631 // CHECK1-NEXT:    [[TMP61:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
 632 // CHECK1-NEXT:    store ptr null, ptr [[TMP61]], align 8
 633 // CHECK1-NEXT:    [[TMP62:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
 634 // CHECK1-NEXT:    store i64 0, ptr [[TMP62]], align 8
 635 // CHECK1-NEXT:    [[TMP63:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
 636 // CHECK1-NEXT:    store i64 0, ptr [[TMP63]], align 8
 637 // CHECK1-NEXT:    [[TMP64:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
 638 // CHECK1-NEXT:    store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP64]], align 4
 639 // CHECK1-NEXT:    [[TMP65:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
 640 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP65]], align 4
 641 // CHECK1-NEXT:    [[TMP66:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
 642 // CHECK1-NEXT:    store i32 0, ptr [[TMP66]], align 4
 643 // CHECK1-NEXT:    [[TMP67:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barssss_l94.region_id, ptr [[KERNEL_ARGS]])
 644 // CHECK1-NEXT:    [[TMP68:%.*]] = icmp ne i32 [[TMP67]], 0
 645 // CHECK1-NEXT:    br i1 [[TMP68]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
 646 // CHECK1:       omp_offload.failed:
 647 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barssss_l94(i64 [[TMP5]], i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]], i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]]) #[[ATTR2]]
 648 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
 649 // CHECK1:       omp_offload.cont:
 650 // CHECK1-NEXT:    br label [[OMP_IF_END:%.*]]
 651 // CHECK1:       omp_if.else:
 652 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barssss_l94(i64 [[TMP5]], i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]], i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]]) #[[ATTR2]]
 653 // CHECK1-NEXT:    br label [[OMP_IF_END]]
 654 // CHECK1:       omp_if.end:
 655 // CHECK1-NEXT:    ret void
 656 //
 657 //
 658 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barssss_l94
 659 // CHECK1-SAME: (i64 noundef [[B:%.*]], i64 noundef [[GB:%.*]], i64 noundef [[SB:%.*]], i64 noundef [[GC:%.*]], i64 noundef [[C:%.*]], i64 noundef [[SC:%.*]], i64 noundef [[D:%.*]], i64 noundef [[GD:%.*]], i64 noundef [[SD:%.*]]) #[[ATTR1]] {
 660 // CHECK1-NEXT:  entry:
 661 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
 662 // CHECK1-NEXT:    [[GB_ADDR:%.*]] = alloca i64, align 8
 663 // CHECK1-NEXT:    [[SB_ADDR:%.*]] = alloca i64, align 8
 664 // CHECK1-NEXT:    [[GC_ADDR:%.*]] = alloca i64, align 8
 665 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca i64, align 8
 666 // CHECK1-NEXT:    [[SC_ADDR:%.*]] = alloca i64, align 8
 667 // CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca i64, align 8
 668 // CHECK1-NEXT:    [[GD_ADDR:%.*]] = alloca i64, align 8
 669 // CHECK1-NEXT:    [[SD_ADDR:%.*]] = alloca i64, align 8
 670 // CHECK1-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
 671 // CHECK1-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
 672 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
 673 // CHECK1-NEXT:    store i64 [[B]], ptr [[B_ADDR]], align 8
 674 // CHECK1-NEXT:    store i64 [[GB]], ptr [[GB_ADDR]], align 8
 675 // CHECK1-NEXT:    store i64 [[SB]], ptr [[SB_ADDR]], align 8
 676 // CHECK1-NEXT:    store i64 [[GC]], ptr [[GC_ADDR]], align 8
 677 // CHECK1-NEXT:    store i64 [[C]], ptr [[C_ADDR]], align 8
 678 // CHECK1-NEXT:    store i64 [[SC]], ptr [[SC_ADDR]], align 8
 679 // CHECK1-NEXT:    store i64 [[D]], ptr [[D_ADDR]], align 8
 680 // CHECK1-NEXT:    store i64 [[GD]], ptr [[GD_ADDR]], align 8
 681 // CHECK1-NEXT:    store i64 [[SD]], ptr [[SD_ADDR]], align 8
 682 // CHECK1-NEXT:    [[TMP1:%.*]] = load i16, ptr [[B_ADDR]], align 2
 683 // CHECK1-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
 684 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV]], 1
 685 // CHECK1-NEXT:    [[CONV1:%.*]] = trunc i32 [[ADD]] to i16
 686 // CHECK1-NEXT:    store i16 [[CONV1]], ptr [[B_ADDR]], align 2
 687 // CHECK1-NEXT:    [[TMP2:%.*]] = load double, ptr [[GB_ADDR]], align 8
 688 // CHECK1-NEXT:    [[ADD2:%.*]] = fadd double [[TMP2]], 1.000000e+00
 689 // CHECK1-NEXT:    store double [[ADD2]], ptr [[GB_ADDR]], align 8
 690 // CHECK1-NEXT:    [[TMP3:%.*]] = load float, ptr [[SB_ADDR]], align 4
 691 // CHECK1-NEXT:    [[CONV3:%.*]] = fpext float [[TMP3]] to double
 692 // CHECK1-NEXT:    [[ADD4:%.*]] = fadd double [[CONV3]], 1.000000e+00
 693 // CHECK1-NEXT:    [[CONV5:%.*]] = fptrunc double [[ADD4]] to float
 694 // CHECK1-NEXT:    store float [[CONV5]], ptr [[SB_ADDR]], align 4
 695 // CHECK1-NEXT:    [[TMP4:%.*]] = load double, ptr [[GC_ADDR]], align 8
 696 // CHECK1-NEXT:    [[CMP:%.*]] = fcmp ogt double [[TMP4]], 0.000000e+00
 697 // CHECK1-NEXT:    br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
 698 // CHECK1:       land.lhs.true:
 699 // CHECK1-NEXT:    [[TMP5:%.*]] = load i16, ptr [[C_ADDR]], align 2
 700 // CHECK1-NEXT:    [[CONV6:%.*]] = sext i16 [[TMP5]] to i32
 701 // CHECK1-NEXT:    [[CMP7:%.*]] = icmp sgt i32 [[CONV6]], 0
 702 // CHECK1-NEXT:    br i1 [[CMP7]], label [[LAND_LHS_TRUE8:%.*]], label [[OMP_IF_ELSE]]
 703 // CHECK1:       land.lhs.true8:
 704 // CHECK1-NEXT:    [[TMP6:%.*]] = load float, ptr [[SC_ADDR]], align 4
 705 // CHECK1-NEXT:    [[CONV9:%.*]] = fpext float [[TMP6]] to double
 706 // CHECK1-NEXT:    [[CMP10:%.*]] = fcmp ogt double [[CONV9]], 0.000000e+00
 707 // CHECK1-NEXT:    br i1 [[CMP10]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]]
 708 // CHECK1:       omp_if.then:
 709 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barssss_l94.omp_outlined, ptr [[D_ADDR]], ptr [[GD_ADDR]], ptr [[SD_ADDR]])
 710 // CHECK1-NEXT:    br label [[OMP_IF_END:%.*]]
 711 // CHECK1:       omp_if.else:
 712 // CHECK1-NEXT:    call void @__kmpc_serialized_parallel(ptr @[[GLOB1]], i32 [[TMP0]])
 713 // CHECK1-NEXT:    store i32 [[TMP0]], ptr [[DOTTHREADID_TEMP_]], align 4
 714 // CHECK1-NEXT:    store i32 0, ptr [[DOTBOUND_ZERO_ADDR]], align 4
 715 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barssss_l94.omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], ptr [[D_ADDR]], ptr [[GD_ADDR]], ptr [[SD_ADDR]]) #[[ATTR2]]
 716 // CHECK1-NEXT:    call void @__kmpc_end_serialized_parallel(ptr @[[GLOB1]], i32 [[TMP0]])
 717 // CHECK1-NEXT:    br label [[OMP_IF_END]]
 718 // CHECK1:       omp_if.end:
 719 // CHECK1-NEXT:    ret void
 720 //
 721 //
 722 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barssss_l94.omp_outlined
 723 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[D:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[GD:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SD:%.*]]) #[[ATTR1]] {
 724 // CHECK1-NEXT:  entry:
 725 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 726 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 727 // CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
 728 // CHECK1-NEXT:    [[GD_ADDR:%.*]] = alloca ptr, align 8
 729 // CHECK1-NEXT:    [[SD_ADDR:%.*]] = alloca ptr, align 8
 730 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 731 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 732 // CHECK1-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
 733 // CHECK1-NEXT:    store ptr [[GD]], ptr [[GD_ADDR]], align 8
 734 // CHECK1-NEXT:    store ptr [[SD]], ptr [[SD_ADDR]], align 8
 735 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8
 736 // CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[GD_ADDR]], align 8
 737 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[SD_ADDR]], align 8
 738 // CHECK1-NEXT:    [[TMP3:%.*]] = load i16, ptr [[TMP0]], align 2
 739 // CHECK1-NEXT:    [[CONV:%.*]] = sext i16 [[TMP3]] to i32
 740 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV]], 1
 741 // CHECK1-NEXT:    [[CONV1:%.*]] = trunc i32 [[ADD]] to i16
 742 // CHECK1-NEXT:    store i16 [[CONV1]], ptr [[TMP0]], align 2
 743 // CHECK1-NEXT:    [[TMP4:%.*]] = load double, ptr [[TMP1]], align 8
 744 // CHECK1-NEXT:    [[ADD2:%.*]] = fadd double [[TMP4]], 1.000000e+00
 745 // CHECK1-NEXT:    store double [[ADD2]], ptr [[TMP1]], align 8
 746 // CHECK1-NEXT:    [[TMP5:%.*]] = load float, ptr [[TMP2]], align 4
 747 // CHECK1-NEXT:    [[CONV3:%.*]] = fpext float [[TMP5]] to double
 748 // CHECK1-NEXT:    [[ADD4:%.*]] = fadd double [[CONV3]], 1.000000e+00
 749 // CHECK1-NEXT:    [[CONV5:%.*]] = fptrunc double [[ADD4]] to float
 750 // CHECK1-NEXT:    store float [[CONV5]], ptr [[TMP2]], align 4
 751 // CHECK1-NEXT:    ret void
 752 //
 753 //
 754 // CHECK1-LABEL: define {{[^@]+}}@_Z5tbar2ssss
 755 // CHECK1-SAME: (i16 noundef signext [[A:%.*]], i16 noundef signext [[B:%.*]], i16 noundef signext [[C:%.*]], i16 noundef signext [[D:%.*]]) #[[ATTR0]] {
 756 // CHECK1-NEXT:  entry:
 757 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i16, align 2
 758 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca i16, align 2
 759 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca i16, align 2
 760 // CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca i16, align 2
 761 // CHECK1-NEXT:    store i16 [[A]], ptr [[A_ADDR]], align 2
 762 // CHECK1-NEXT:    store i16 [[B]], ptr [[B_ADDR]], align 2
 763 // CHECK1-NEXT:    store i16 [[C]], ptr [[C_ADDR]], align 2
 764 // CHECK1-NEXT:    store i16 [[D]], ptr [[D_ADDR]], align 2
 765 // CHECK1-NEXT:    [[TMP0:%.*]] = load i16, ptr [[A_ADDR]], align 2
 766 // CHECK1-NEXT:    [[TMP1:%.*]] = load i16, ptr [[B_ADDR]], align 2
 767 // CHECK1-NEXT:    [[TMP2:%.*]] = load i16, ptr [[C_ADDR]], align 2
 768 // CHECK1-NEXT:    [[TMP3:%.*]] = load i16, ptr [[D_ADDR]], align 2
 769 // CHECK1-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_Z4tbarIsEiT_S0_S0_S0_(i16 noundef signext [[TMP0]], i16 noundef signext [[TMP1]], i16 noundef signext [[TMP2]], i16 noundef signext [[TMP3]])
 770 // CHECK1-NEXT:    ret i32 [[CALL]]
 771 //
 772 //
 773 // CHECK1-LABEL: define {{[^@]+}}@_Z4tbarIsEiT_S0_S0_S0_
 774 // CHECK1-SAME: (i16 noundef signext [[A:%.*]], i16 noundef signext [[B:%.*]], i16 noundef signext [[C:%.*]], i16 noundef signext [[D:%.*]]) #[[ATTR0]] comdat {
 775 // CHECK1-NEXT:  entry:
 776 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i16, align 2
 777 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca i16, align 2
 778 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca i16, align 2
 779 // CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca i16, align 2
 780 // CHECK1-NEXT:    store i16 [[A]], ptr [[A_ADDR]], align 2
 781 // CHECK1-NEXT:    store i16 [[B]], ptr [[B_ADDR]], align 2
 782 // CHECK1-NEXT:    store i16 [[C]], ptr [[C_ADDR]], align 2
 783 // CHECK1-NEXT:    store i16 [[D]], ptr [[D_ADDR]], align 2
 784 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 4, ptr @_Z4tbarIsEiT_S0_S0_S0_.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])
 785 // CHECK1-NEXT:    [[TMP0:%.*]] = load i16, ptr [[A_ADDR]], align 2
 786 // CHECK1-NEXT:    [[CONV:%.*]] = sext i16 [[TMP0]] to i32
 787 // CHECK1-NEXT:    [[TMP1:%.*]] = load i16, ptr [[B_ADDR]], align 2
 788 // CHECK1-NEXT:    [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
 789 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV]], [[CONV1]]
 790 // CHECK1-NEXT:    [[TMP2:%.*]] = load i16, ptr [[C_ADDR]], align 2
 791 // CHECK1-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
 792 // CHECK1-NEXT:    [[ADD3:%.*]] = add nsw i32 [[ADD]], [[CONV2]]
 793 // CHECK1-NEXT:    [[TMP3:%.*]] = load i16, ptr [[D_ADDR]], align 2
 794 // CHECK1-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP3]] to i32
 795 // CHECK1-NEXT:    [[ADD5:%.*]] = add nsw i32 [[ADD3]], [[CONV4]]
 796 // CHECK1-NEXT:    [[TMP4:%.*]] = load float, ptr @_ZZ4tbarIsEiT_S0_S0_S0_E2Sa, align 4
 797 // CHECK1-NEXT:    [[CONV6:%.*]] = fptosi float [[TMP4]] to i32
 798 // CHECK1-NEXT:    [[ADD7:%.*]] = add nsw i32 [[ADD5]], [[CONV6]]
 799 // CHECK1-NEXT:    [[TMP5:%.*]] = load float, ptr @_ZZ4tbarIsEiT_S0_S0_S0_E2Sb, align 4
 800 // CHECK1-NEXT:    [[CONV8:%.*]] = fptosi float [[TMP5]] to i32
 801 // CHECK1-NEXT:    [[ADD9:%.*]] = add nsw i32 [[ADD7]], [[CONV8]]
 802 // CHECK1-NEXT:    [[TMP6:%.*]] = load float, ptr @_ZZ4tbarIsEiT_S0_S0_S0_E2Sc, align 4
 803 // CHECK1-NEXT:    [[CONV10:%.*]] = fptosi float [[TMP6]] to i32
 804 // CHECK1-NEXT:    [[ADD11:%.*]] = add nsw i32 [[ADD9]], [[CONV10]]
 805 // CHECK1-NEXT:    [[TMP7:%.*]] = load float, ptr @_ZZ4tbarIsEiT_S0_S0_S0_E2Sd, align 4
 806 // CHECK1-NEXT:    [[CONV12:%.*]] = fptosi float [[TMP7]] to i32
 807 // CHECK1-NEXT:    [[ADD13:%.*]] = add nsw i32 [[ADD11]], [[CONV12]]
 808 // CHECK1-NEXT:    ret i32 [[ADD13]]
 809 //
 810 //
 811 // CHECK1-LABEL: define {{[^@]+}}@_Z4tbarIsEiT_S0_S0_S0_.omp_outlined
 812 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[A:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[B:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[D:%.*]]) #[[ATTR1]] {
 813 // CHECK1-NEXT:  entry:
 814 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 815 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 816 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 8
 817 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
 818 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
 819 // CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
 820 // CHECK1-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
 821 // CHECK1-NEXT:    [[GB_CASTED:%.*]] = alloca i64, align 8
 822 // CHECK1-NEXT:    [[SB_CASTED:%.*]] = alloca i64, align 8
 823 // CHECK1-NEXT:    [[GC_CASTED:%.*]] = alloca i64, align 8
 824 // CHECK1-NEXT:    [[C_CASTED:%.*]] = alloca i64, align 8
 825 // CHECK1-NEXT:    [[SC_CASTED:%.*]] = alloca i64, align 8
 826 // CHECK1-NEXT:    [[D_CASTED:%.*]] = alloca i64, align 8
 827 // CHECK1-NEXT:    [[GD_CASTED:%.*]] = alloca i64, align 8
 828 // CHECK1-NEXT:    [[SD_CASTED:%.*]] = alloca i64, align 8
 829 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [9 x ptr], align 8
 830 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [9 x ptr], align 8
 831 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [9 x ptr], align 8
 832 // CHECK1-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
 833 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 834 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 835 // CHECK1-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 8
 836 // CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
 837 // CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
 838 // CHECK1-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
 839 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
 840 // CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 8
 841 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 8
 842 // CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 8
 843 // CHECK1-NEXT:    [[TMP4:%.*]] = load i16, ptr [[TMP1]], align 2
 844 // CHECK1-NEXT:    store i16 [[TMP4]], ptr [[B_CASTED]], align 2
 845 // CHECK1-NEXT:    [[TMP5:%.*]] = load i64, ptr [[B_CASTED]], align 8
 846 // CHECK1-NEXT:    [[TMP6:%.*]] = load double, ptr @Gb, align 8
 847 // CHECK1-NEXT:    store double [[TMP6]], ptr [[GB_CASTED]], align 8
 848 // CHECK1-NEXT:    [[TMP7:%.*]] = load i64, ptr [[GB_CASTED]], align 8
 849 // CHECK1-NEXT:    [[TMP8:%.*]] = load float, ptr @_ZZ4tbarIsEiT_S0_S0_S0_E2Sb, align 4
 850 // CHECK1-NEXT:    store float [[TMP8]], ptr [[SB_CASTED]], align 4
 851 // CHECK1-NEXT:    [[TMP9:%.*]] = load i64, ptr [[SB_CASTED]], align 8
 852 // CHECK1-NEXT:    [[TMP10:%.*]] = load double, ptr @Gc, align 8
 853 // CHECK1-NEXT:    store double [[TMP10]], ptr [[GC_CASTED]], align 8
 854 // CHECK1-NEXT:    [[TMP11:%.*]] = load i64, ptr [[GC_CASTED]], align 8
 855 // CHECK1-NEXT:    [[TMP12:%.*]] = load i16, ptr [[TMP2]], align 2
 856 // CHECK1-NEXT:    store i16 [[TMP12]], ptr [[C_CASTED]], align 2
 857 // CHECK1-NEXT:    [[TMP13:%.*]] = load i64, ptr [[C_CASTED]], align 8
 858 // CHECK1-NEXT:    [[TMP14:%.*]] = load float, ptr @_ZZ4tbarIsEiT_S0_S0_S0_E2Sc, align 4
 859 // CHECK1-NEXT:    store float [[TMP14]], ptr [[SC_CASTED]], align 4
 860 // CHECK1-NEXT:    [[TMP15:%.*]] = load i64, ptr [[SC_CASTED]], align 8
 861 // CHECK1-NEXT:    [[TMP16:%.*]] = load i16, ptr [[TMP3]], align 2
 862 // CHECK1-NEXT:    store i16 [[TMP16]], ptr [[D_CASTED]], align 2
 863 // CHECK1-NEXT:    [[TMP17:%.*]] = load i64, ptr [[D_CASTED]], align 8
 864 // CHECK1-NEXT:    [[TMP18:%.*]] = load double, ptr @Gd, align 8
 865 // CHECK1-NEXT:    store double [[TMP18]], ptr [[GD_CASTED]], align 8
 866 // CHECK1-NEXT:    [[TMP19:%.*]] = load i64, ptr [[GD_CASTED]], align 8
 867 // CHECK1-NEXT:    [[TMP20:%.*]] = load float, ptr @_ZZ4tbarIsEiT_S0_S0_S0_E2Sd, align 4
 868 // CHECK1-NEXT:    store float [[TMP20]], ptr [[SD_CASTED]], align 4
 869 // CHECK1-NEXT:    [[TMP21:%.*]] = load i64, ptr [[SD_CASTED]], align 8
 870 // CHECK1-NEXT:    [[TMP22:%.*]] = load double, ptr @Ga, align 8
 871 // CHECK1-NEXT:    [[CMP:%.*]] = fcmp ogt double [[TMP22]], 0.000000e+00
 872 // CHECK1-NEXT:    br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
 873 // CHECK1:       land.lhs.true:
 874 // CHECK1-NEXT:    [[TMP23:%.*]] = load i16, ptr [[TMP0]], align 2
 875 // CHECK1-NEXT:    [[CONV:%.*]] = sext i16 [[TMP23]] to i32
 876 // CHECK1-NEXT:    [[CMP1:%.*]] = icmp sgt i32 [[CONV]], 0
 877 // CHECK1-NEXT:    br i1 [[CMP1]], label [[LAND_LHS_TRUE2:%.*]], label [[OMP_IF_ELSE]]
 878 // CHECK1:       land.lhs.true2:
 879 // CHECK1-NEXT:    [[TMP24:%.*]] = load float, ptr @_ZZ4tbarIsEiT_S0_S0_S0_E2Sa, align 4
 880 // CHECK1-NEXT:    [[CONV3:%.*]] = fpext float [[TMP24]] to double
 881 // CHECK1-NEXT:    [[CMP4:%.*]] = fcmp ogt double [[CONV3]], 0.000000e+00
 882 // CHECK1-NEXT:    br i1 [[CMP4]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]]
 883 // CHECK1:       omp_if.then:
 884 // CHECK1-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
 885 // CHECK1-NEXT:    store i64 [[TMP5]], ptr [[TMP25]], align 8
 886 // CHECK1-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
 887 // CHECK1-NEXT:    store i64 [[TMP5]], ptr [[TMP26]], align 8
 888 // CHECK1-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
 889 // CHECK1-NEXT:    store ptr null, ptr [[TMP27]], align 8
 890 // CHECK1-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
 891 // CHECK1-NEXT:    store i64 [[TMP7]], ptr [[TMP28]], align 8
 892 // CHECK1-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
 893 // CHECK1-NEXT:    store i64 [[TMP7]], ptr [[TMP29]], align 8
 894 // CHECK1-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
 895 // CHECK1-NEXT:    store ptr null, ptr [[TMP30]], align 8
 896 // CHECK1-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
 897 // CHECK1-NEXT:    store i64 [[TMP9]], ptr [[TMP31]], align 8
 898 // CHECK1-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
 899 // CHECK1-NEXT:    store i64 [[TMP9]], ptr [[TMP32]], align 8
 900 // CHECK1-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
 901 // CHECK1-NEXT:    store ptr null, ptr [[TMP33]], align 8
 902 // CHECK1-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
 903 // CHECK1-NEXT:    store i64 [[TMP11]], ptr [[TMP34]], align 8
 904 // CHECK1-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
 905 // CHECK1-NEXT:    store i64 [[TMP11]], ptr [[TMP35]], align 8
 906 // CHECK1-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
 907 // CHECK1-NEXT:    store ptr null, ptr [[TMP36]], align 8
 908 // CHECK1-NEXT:    [[TMP37:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
 909 // CHECK1-NEXT:    store i64 [[TMP13]], ptr [[TMP37]], align 8
 910 // CHECK1-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4
 911 // CHECK1-NEXT:    store i64 [[TMP13]], ptr [[TMP38]], align 8
 912 // CHECK1-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
 913 // CHECK1-NEXT:    store ptr null, ptr [[TMP39]], align 8
 914 // CHECK1-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5
 915 // CHECK1-NEXT:    store i64 [[TMP15]], ptr [[TMP40]], align 8
 916 // CHECK1-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 5
 917 // CHECK1-NEXT:    store i64 [[TMP15]], ptr [[TMP41]], align 8
 918 // CHECK1-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 5
 919 // CHECK1-NEXT:    store ptr null, ptr [[TMP42]], align 8
 920 // CHECK1-NEXT:    [[TMP43:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6
 921 // CHECK1-NEXT:    store i64 [[TMP17]], ptr [[TMP43]], align 8
 922 // CHECK1-NEXT:    [[TMP44:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 6
 923 // CHECK1-NEXT:    store i64 [[TMP17]], ptr [[TMP44]], align 8
 924 // CHECK1-NEXT:    [[TMP45:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 6
 925 // CHECK1-NEXT:    store ptr null, ptr [[TMP45]], align 8
 926 // CHECK1-NEXT:    [[TMP46:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7
 927 // CHECK1-NEXT:    store i64 [[TMP19]], ptr [[TMP46]], align 8
 928 // CHECK1-NEXT:    [[TMP47:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 7
 929 // CHECK1-NEXT:    store i64 [[TMP19]], ptr [[TMP47]], align 8
 930 // CHECK1-NEXT:    [[TMP48:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 7
 931 // CHECK1-NEXT:    store ptr null, ptr [[TMP48]], align 8
 932 // CHECK1-NEXT:    [[TMP49:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 8
 933 // CHECK1-NEXT:    store i64 [[TMP21]], ptr [[TMP49]], align 8
 934 // CHECK1-NEXT:    [[TMP50:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 8
 935 // CHECK1-NEXT:    store i64 [[TMP21]], ptr [[TMP50]], align 8
 936 // CHECK1-NEXT:    [[TMP51:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 8
 937 // CHECK1-NEXT:    store ptr null, ptr [[TMP51]], align 8
 938 // CHECK1-NEXT:    [[TMP52:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
 939 // CHECK1-NEXT:    [[TMP53:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
 940 // CHECK1-NEXT:    [[TMP54:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
 941 // CHECK1-NEXT:    store i32 2, ptr [[TMP54]], align 4
 942 // CHECK1-NEXT:    [[TMP55:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
 943 // CHECK1-NEXT:    store i32 9, ptr [[TMP55]], align 4
 944 // CHECK1-NEXT:    [[TMP56:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
 945 // CHECK1-NEXT:    store ptr [[TMP52]], ptr [[TMP56]], align 8
 946 // CHECK1-NEXT:    [[TMP57:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
 947 // CHECK1-NEXT:    store ptr [[TMP53]], ptr [[TMP57]], align 8
 948 // CHECK1-NEXT:    [[TMP58:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
 949 // CHECK1-NEXT:    store ptr @.offload_sizes.3, ptr [[TMP58]], align 8
 950 // CHECK1-NEXT:    [[TMP59:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
 951 // CHECK1-NEXT:    store ptr @.offload_maptypes.4, ptr [[TMP59]], align 8
 952 // CHECK1-NEXT:    [[TMP60:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
 953 // CHECK1-NEXT:    store ptr null, ptr [[TMP60]], align 8
 954 // CHECK1-NEXT:    [[TMP61:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
 955 // CHECK1-NEXT:    store ptr null, ptr [[TMP61]], align 8
 956 // CHECK1-NEXT:    [[TMP62:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
 957 // CHECK1-NEXT:    store i64 0, ptr [[TMP62]], align 8
 958 // CHECK1-NEXT:    [[TMP63:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
 959 // CHECK1-NEXT:    store i64 0, ptr [[TMP63]], align 8
 960 // CHECK1-NEXT:    [[TMP64:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
 961 // CHECK1-NEXT:    store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP64]], align 4
 962 // CHECK1-NEXT:    [[TMP65:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
 963 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP65]], align 4
 964 // CHECK1-NEXT:    [[TMP66:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
 965 // CHECK1-NEXT:    store i32 0, ptr [[TMP66]], align 4
 966 // CHECK1-NEXT:    [[TMP67:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4tbarIsEiT_S0_S0_S0__l145.region_id, ptr [[KERNEL_ARGS]])
 967 // CHECK1-NEXT:    [[TMP68:%.*]] = icmp ne i32 [[TMP67]], 0
 968 // CHECK1-NEXT:    br i1 [[TMP68]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
 969 // CHECK1:       omp_offload.failed:
 970 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4tbarIsEiT_S0_S0_S0__l145(i64 [[TMP5]], i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]], i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]]) #[[ATTR2]]
 971 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
 972 // CHECK1:       omp_offload.cont:
 973 // CHECK1-NEXT:    br label [[OMP_IF_END:%.*]]
 974 // CHECK1:       omp_if.else:
 975 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4tbarIsEiT_S0_S0_S0__l145(i64 [[TMP5]], i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP13]], i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], i64 [[TMP21]]) #[[ATTR2]]
 976 // CHECK1-NEXT:    br label [[OMP_IF_END]]
 977 // CHECK1:       omp_if.end:
 978 // CHECK1-NEXT:    ret void
 979 //
 980 //
 981 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4tbarIsEiT_S0_S0_S0__l145
 982 // CHECK1-SAME: (i64 noundef [[B:%.*]], i64 noundef [[GB:%.*]], i64 noundef [[SB:%.*]], i64 noundef [[GC:%.*]], i64 noundef [[C:%.*]], i64 noundef [[SC:%.*]], i64 noundef [[D:%.*]], i64 noundef [[GD:%.*]], i64 noundef [[SD:%.*]]) #[[ATTR1]] {
 983 // CHECK1-NEXT:  entry:
 984 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
 985 // CHECK1-NEXT:    [[GB_ADDR:%.*]] = alloca i64, align 8
 986 // CHECK1-NEXT:    [[SB_ADDR:%.*]] = alloca i64, align 8
 987 // CHECK1-NEXT:    [[GC_ADDR:%.*]] = alloca i64, align 8
 988 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca i64, align 8
 989 // CHECK1-NEXT:    [[SC_ADDR:%.*]] = alloca i64, align 8
 990 // CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca i64, align 8
 991 // CHECK1-NEXT:    [[GD_ADDR:%.*]] = alloca i64, align 8
 992 // CHECK1-NEXT:    [[SD_ADDR:%.*]] = alloca i64, align 8
 993 // CHECK1-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
 994 // CHECK1-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
 995 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
 996 // CHECK1-NEXT:    store i64 [[B]], ptr [[B_ADDR]], align 8
 997 // CHECK1-NEXT:    store i64 [[GB]], ptr [[GB_ADDR]], align 8
 998 // CHECK1-NEXT:    store i64 [[SB]], ptr [[SB_ADDR]], align 8
 999 // CHECK1-NEXT:    store i64 [[GC]], ptr [[GC_ADDR]], align 8
1000 // CHECK1-NEXT:    store i64 [[C]], ptr [[C_ADDR]], align 8
1001 // CHECK1-NEXT:    store i64 [[SC]], ptr [[SC_ADDR]], align 8
1002 // CHECK1-NEXT:    store i64 [[D]], ptr [[D_ADDR]], align 8
1003 // CHECK1-NEXT:    store i64 [[GD]], ptr [[GD_ADDR]], align 8
1004 // CHECK1-NEXT:    store i64 [[SD]], ptr [[SD_ADDR]], align 8
1005 // CHECK1-NEXT:    [[TMP1:%.*]] = load i16, ptr [[B_ADDR]], align 2
1006 // CHECK1-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
1007 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV]], 1
1008 // CHECK1-NEXT:    [[CONV1:%.*]] = trunc i32 [[ADD]] to i16
1009 // CHECK1-NEXT:    store i16 [[CONV1]], ptr [[B_ADDR]], align 2
1010 // CHECK1-NEXT:    [[TMP2:%.*]] = load double, ptr [[GB_ADDR]], align 8
1011 // CHECK1-NEXT:    [[ADD2:%.*]] = fadd double [[TMP2]], 1.000000e+00
1012 // CHECK1-NEXT:    store double [[ADD2]], ptr [[GB_ADDR]], align 8
1013 // CHECK1-NEXT:    [[TMP3:%.*]] = load float, ptr [[SB_ADDR]], align 4
1014 // CHECK1-NEXT:    [[CONV3:%.*]] = fpext float [[TMP3]] to double
1015 // CHECK1-NEXT:    [[ADD4:%.*]] = fadd double [[CONV3]], 1.000000e+00
1016 // CHECK1-NEXT:    [[CONV5:%.*]] = fptrunc double [[ADD4]] to float
1017 // CHECK1-NEXT:    store float [[CONV5]], ptr [[SB_ADDR]], align 4
1018 // CHECK1-NEXT:    [[TMP4:%.*]] = load double, ptr [[GC_ADDR]], align 8
1019 // CHECK1-NEXT:    [[CMP:%.*]] = fcmp ogt double [[TMP4]], 0.000000e+00
1020 // CHECK1-NEXT:    br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
1021 // CHECK1:       land.lhs.true:
1022 // CHECK1-NEXT:    [[TMP5:%.*]] = load i16, ptr [[C_ADDR]], align 2
1023 // CHECK1-NEXT:    [[CONV6:%.*]] = sext i16 [[TMP5]] to i32
1024 // CHECK1-NEXT:    [[CMP7:%.*]] = icmp sgt i32 [[CONV6]], 0
1025 // CHECK1-NEXT:    br i1 [[CMP7]], label [[LAND_LHS_TRUE8:%.*]], label [[OMP_IF_ELSE]]
1026 // CHECK1:       land.lhs.true8:
1027 // CHECK1-NEXT:    [[TMP6:%.*]] = load float, ptr [[SC_ADDR]], align 4
1028 // CHECK1-NEXT:    [[CONV9:%.*]] = fpext float [[TMP6]] to double
1029 // CHECK1-NEXT:    [[CMP10:%.*]] = fcmp ogt double [[CONV9]], 0.000000e+00
1030 // CHECK1-NEXT:    br i1 [[CMP10]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]]
1031 // CHECK1:       omp_if.then:
1032 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4tbarIsEiT_S0_S0_S0__l145.omp_outlined, ptr [[D_ADDR]], ptr [[GD_ADDR]], ptr [[SD_ADDR]])
1033 // CHECK1-NEXT:    br label [[OMP_IF_END:%.*]]
1034 // CHECK1:       omp_if.else:
1035 // CHECK1-NEXT:    call void @__kmpc_serialized_parallel(ptr @[[GLOB1]], i32 [[TMP0]])
1036 // CHECK1-NEXT:    store i32 [[TMP0]], ptr [[DOTTHREADID_TEMP_]], align 4
1037 // CHECK1-NEXT:    store i32 0, ptr [[DOTBOUND_ZERO_ADDR]], align 4
1038 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4tbarIsEiT_S0_S0_S0__l145.omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], ptr [[D_ADDR]], ptr [[GD_ADDR]], ptr [[SD_ADDR]]) #[[ATTR2]]
1039 // CHECK1-NEXT:    call void @__kmpc_end_serialized_parallel(ptr @[[GLOB1]], i32 [[TMP0]])
1040 // CHECK1-NEXT:    br label [[OMP_IF_END]]
1041 // CHECK1:       omp_if.end:
1042 // CHECK1-NEXT:    ret void
1043 //
1044 //
1045 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4tbarIsEiT_S0_S0_S0__l145.omp_outlined
1046 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[D:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[GD:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SD:%.*]]) #[[ATTR1]] {
1047 // CHECK1-NEXT:  entry:
1048 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1049 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1050 // CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
1051 // CHECK1-NEXT:    [[GD_ADDR:%.*]] = alloca ptr, align 8
1052 // CHECK1-NEXT:    [[SD_ADDR:%.*]] = alloca ptr, align 8
1053 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1054 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1055 // CHECK1-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
1056 // CHECK1-NEXT:    store ptr [[GD]], ptr [[GD_ADDR]], align 8
1057 // CHECK1-NEXT:    store ptr [[SD]], ptr [[SD_ADDR]], align 8
1058 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 8
1059 // CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[GD_ADDR]], align 8
1060 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[SD_ADDR]], align 8
1061 // CHECK1-NEXT:    [[TMP3:%.*]] = load i16, ptr [[TMP0]], align 2
1062 // CHECK1-NEXT:    [[CONV:%.*]] = sext i16 [[TMP3]] to i32
1063 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV]], 1
1064 // CHECK1-NEXT:    [[CONV1:%.*]] = trunc i32 [[ADD]] to i16
1065 // CHECK1-NEXT:    store i16 [[CONV1]], ptr [[TMP0]], align 2
1066 // CHECK1-NEXT:    [[TMP4:%.*]] = load double, ptr [[TMP1]], align 8
1067 // CHECK1-NEXT:    [[ADD2:%.*]] = fadd double [[TMP4]], 1.000000e+00
1068 // CHECK1-NEXT:    store double [[ADD2]], ptr [[TMP1]], align 8
1069 // CHECK1-NEXT:    [[TMP5:%.*]] = load float, ptr [[TMP2]], align 4
1070 // CHECK1-NEXT:    [[CONV3:%.*]] = fpext float [[TMP5]] to double
1071 // CHECK1-NEXT:    [[ADD4:%.*]] = fadd double [[CONV3]], 1.000000e+00
1072 // CHECK1-NEXT:    [[CONV5:%.*]] = fptrunc double [[ADD4]] to float
1073 // CHECK1-NEXT:    store float [[CONV5]], ptr [[TMP2]], align 4
1074 // CHECK1-NEXT:    ret void
1075 //
1076 //
1077 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
1078 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] {
1079 // CHECK1-NEXT:  entry:
1080 // CHECK1-NEXT:    call void @__tgt_register_requires(i64 1)
1081 // CHECK1-NEXT:    ret void
1082 //
1083 //
1084 // CHECK3-LABEL: define {{[^@]+}}@_Z3foossss
1085 // CHECK3-SAME: (i16 noundef signext [[A:%.*]], i16 noundef signext [[B:%.*]], i16 noundef signext [[C:%.*]], i16 noundef signext [[D:%.*]]) #[[ATTR0:[0-9]+]] {
1086 // CHECK3-NEXT:  entry:
1087 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i16, align 2
1088 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca i16, align 2
1089 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca i16, align 2
1090 // CHECK3-NEXT:    [[D_ADDR:%.*]] = alloca i16, align 2
1091 // CHECK3-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
1092 // CHECK3-NEXT:    [[SB_CASTED:%.*]] = alloca i32, align 4
1093 // CHECK3-NEXT:    [[C_CASTED:%.*]] = alloca i32, align 4
1094 // CHECK3-NEXT:    [[SC_CASTED:%.*]] = alloca i32, align 4
1095 // CHECK3-NEXT:    [[D_CASTED:%.*]] = alloca i32, align 4
1096 // CHECK3-NEXT:    [[SD_CASTED:%.*]] = alloca i32, align 4
1097 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [9 x ptr], align 4
1098 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [9 x ptr], align 4
1099 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [9 x ptr], align 4
1100 // CHECK3-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1101 // CHECK3-NEXT:    store i16 [[A]], ptr [[A_ADDR]], align 2
1102 // CHECK3-NEXT:    store i16 [[B]], ptr [[B_ADDR]], align 2
1103 // CHECK3-NEXT:    store i16 [[C]], ptr [[C_ADDR]], align 2
1104 // CHECK3-NEXT:    store i16 [[D]], ptr [[D_ADDR]], align 2
1105 // CHECK3-NEXT:    [[TMP0:%.*]] = load i16, ptr [[B_ADDR]], align 2
1106 // CHECK3-NEXT:    store i16 [[TMP0]], ptr [[B_CASTED]], align 2
1107 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[B_CASTED]], align 4
1108 // CHECK3-NEXT:    [[TMP2:%.*]] = load float, ptr @_ZZ3foossssE2Sb, align 4
1109 // CHECK3-NEXT:    store float [[TMP2]], ptr [[SB_CASTED]], align 4
1110 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[SB_CASTED]], align 4
1111 // CHECK3-NEXT:    [[TMP4:%.*]] = load i16, ptr [[C_ADDR]], align 2
1112 // CHECK3-NEXT:    store i16 [[TMP4]], ptr [[C_CASTED]], align 2
1113 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[C_CASTED]], align 4
1114 // CHECK3-NEXT:    [[TMP6:%.*]] = load float, ptr @_ZZ3foossssE2Sc, align 4
1115 // CHECK3-NEXT:    store float [[TMP6]], ptr [[SC_CASTED]], align 4
1116 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[SC_CASTED]], align 4
1117 // CHECK3-NEXT:    [[TMP8:%.*]] = load i16, ptr [[D_ADDR]], align 2
1118 // CHECK3-NEXT:    store i16 [[TMP8]], ptr [[D_CASTED]], align 2
1119 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[D_CASTED]], align 4
1120 // CHECK3-NEXT:    [[TMP10:%.*]] = load float, ptr @_ZZ3foossssE2Sd, align 4
1121 // CHECK3-NEXT:    store float [[TMP10]], ptr [[SD_CASTED]], align 4
1122 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[SD_CASTED]], align 4
1123 // CHECK3-NEXT:    [[TMP12:%.*]] = load double, ptr @Ga, align 8
1124 // CHECK3-NEXT:    [[CMP:%.*]] = fcmp ogt double [[TMP12]], 0.000000e+00
1125 // CHECK3-NEXT:    br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
1126 // CHECK3:       land.lhs.true:
1127 // CHECK3-NEXT:    [[TMP13:%.*]] = load i16, ptr [[A_ADDR]], align 2
1128 // CHECK3-NEXT:    [[CONV:%.*]] = sext i16 [[TMP13]] to i32
1129 // CHECK3-NEXT:    [[CMP1:%.*]] = icmp sgt i32 [[CONV]], 0
1130 // CHECK3-NEXT:    br i1 [[CMP1]], label [[LAND_LHS_TRUE2:%.*]], label [[OMP_IF_ELSE]]
1131 // CHECK3:       land.lhs.true2:
1132 // CHECK3-NEXT:    [[TMP14:%.*]] = load float, ptr @_ZZ3foossssE2Sa, align 4
1133 // CHECK3-NEXT:    [[CONV3:%.*]] = fpext float [[TMP14]] to double
1134 // CHECK3-NEXT:    [[CMP4:%.*]] = fcmp ogt double [[CONV3]], 0.000000e+00
1135 // CHECK3-NEXT:    br i1 [[CMP4]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]]
1136 // CHECK3:       omp_if.then:
1137 // CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1138 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[TMP15]], align 4
1139 // CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1140 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[TMP16]], align 4
1141 // CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
1142 // CHECK3-NEXT:    store ptr null, ptr [[TMP17]], align 4
1143 // CHECK3-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1144 // CHECK3-NEXT:    store ptr @Gb, ptr [[TMP18]], align 4
1145 // CHECK3-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1146 // CHECK3-NEXT:    store ptr @Gb, ptr [[TMP19]], align 4
1147 // CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
1148 // CHECK3-NEXT:    store ptr null, ptr [[TMP20]], align 4
1149 // CHECK3-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1150 // CHECK3-NEXT:    store i32 [[TMP3]], ptr [[TMP21]], align 4
1151 // CHECK3-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1152 // CHECK3-NEXT:    store i32 [[TMP3]], ptr [[TMP22]], align 4
1153 // CHECK3-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
1154 // CHECK3-NEXT:    store ptr null, ptr [[TMP23]], align 4
1155 // CHECK3-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1156 // CHECK3-NEXT:    store ptr @Gc, ptr [[TMP24]], align 4
1157 // CHECK3-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1158 // CHECK3-NEXT:    store ptr @Gc, ptr [[TMP25]], align 4
1159 // CHECK3-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
1160 // CHECK3-NEXT:    store ptr null, ptr [[TMP26]], align 4
1161 // CHECK3-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
1162 // CHECK3-NEXT:    store i32 [[TMP5]], ptr [[TMP27]], align 4
1163 // CHECK3-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4
1164 // CHECK3-NEXT:    store i32 [[TMP5]], ptr [[TMP28]], align 4
1165 // CHECK3-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
1166 // CHECK3-NEXT:    store ptr null, ptr [[TMP29]], align 4
1167 // CHECK3-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5
1168 // CHECK3-NEXT:    store i32 [[TMP7]], ptr [[TMP30]], align 4
1169 // CHECK3-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 5
1170 // CHECK3-NEXT:    store i32 [[TMP7]], ptr [[TMP31]], align 4
1171 // CHECK3-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 5
1172 // CHECK3-NEXT:    store ptr null, ptr [[TMP32]], align 4
1173 // CHECK3-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6
1174 // CHECK3-NEXT:    store i32 [[TMP9]], ptr [[TMP33]], align 4
1175 // CHECK3-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 6
1176 // CHECK3-NEXT:    store i32 [[TMP9]], ptr [[TMP34]], align 4
1177 // CHECK3-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 6
1178 // CHECK3-NEXT:    store ptr null, ptr [[TMP35]], align 4
1179 // CHECK3-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7
1180 // CHECK3-NEXT:    store ptr @Gd, ptr [[TMP36]], align 4
1181 // CHECK3-NEXT:    [[TMP37:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 7
1182 // CHECK3-NEXT:    store ptr @Gd, ptr [[TMP37]], align 4
1183 // CHECK3-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 7
1184 // CHECK3-NEXT:    store ptr null, ptr [[TMP38]], align 4
1185 // CHECK3-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 8
1186 // CHECK3-NEXT:    store i32 [[TMP11]], ptr [[TMP39]], align 4
1187 // CHECK3-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 8
1188 // CHECK3-NEXT:    store i32 [[TMP11]], ptr [[TMP40]], align 4
1189 // CHECK3-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 8
1190 // CHECK3-NEXT:    store ptr null, ptr [[TMP41]], align 4
1191 // CHECK3-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1192 // CHECK3-NEXT:    [[TMP43:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1193 // CHECK3-NEXT:    [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
1194 // CHECK3-NEXT:    store i32 2, ptr [[TMP44]], align 4
1195 // CHECK3-NEXT:    [[TMP45:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
1196 // CHECK3-NEXT:    store i32 9, ptr [[TMP45]], align 4
1197 // CHECK3-NEXT:    [[TMP46:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
1198 // CHECK3-NEXT:    store ptr [[TMP42]], ptr [[TMP46]], align 4
1199 // CHECK3-NEXT:    [[TMP47:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
1200 // CHECK3-NEXT:    store ptr [[TMP43]], ptr [[TMP47]], align 4
1201 // CHECK3-NEXT:    [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
1202 // CHECK3-NEXT:    store ptr @.offload_sizes, ptr [[TMP48]], align 4
1203 // CHECK3-NEXT:    [[TMP49:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
1204 // CHECK3-NEXT:    store ptr @.offload_maptypes, ptr [[TMP49]], align 4
1205 // CHECK3-NEXT:    [[TMP50:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
1206 // CHECK3-NEXT:    store ptr null, ptr [[TMP50]], align 4
1207 // CHECK3-NEXT:    [[TMP51:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
1208 // CHECK3-NEXT:    store ptr null, ptr [[TMP51]], align 4
1209 // CHECK3-NEXT:    [[TMP52:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
1210 // CHECK3-NEXT:    store i64 0, ptr [[TMP52]], align 8
1211 // CHECK3-NEXT:    [[TMP53:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
1212 // CHECK3-NEXT:    store i64 0, ptr [[TMP53]], align 8
1213 // CHECK3-NEXT:    [[TMP54:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
1214 // CHECK3-NEXT:    store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP54]], align 4
1215 // CHECK3-NEXT:    [[TMP55:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
1216 // CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP55]], align 4
1217 // CHECK3-NEXT:    [[TMP56:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
1218 // CHECK3-NEXT:    store i32 0, ptr [[TMP56]], align 4
1219 // CHECK3-NEXT:    [[TMP57:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1:[0-9]+]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foossss_l49.region_id, ptr [[KERNEL_ARGS]])
1220 // CHECK3-NEXT:    [[TMP58:%.*]] = icmp ne i32 [[TMP57]], 0
1221 // CHECK3-NEXT:    br i1 [[TMP58]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1222 // CHECK3:       omp_offload.failed:
1223 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foossss_l49(i32 [[TMP1]], ptr @Gb, i32 [[TMP3]], ptr @Gc, i32 [[TMP5]], i32 [[TMP7]], i32 [[TMP9]], ptr @Gd, i32 [[TMP11]]) #[[ATTR2:[0-9]+]]
1224 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]
1225 // CHECK3:       omp_offload.cont:
1226 // CHECK3-NEXT:    br label [[OMP_IF_END:%.*]]
1227 // CHECK3:       omp_if.else:
1228 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foossss_l49(i32 [[TMP1]], ptr @Gb, i32 [[TMP3]], ptr @Gc, i32 [[TMP5]], i32 [[TMP7]], i32 [[TMP9]], ptr @Gd, i32 [[TMP11]]) #[[ATTR2]]
1229 // CHECK3-NEXT:    br label [[OMP_IF_END]]
1230 // CHECK3:       omp_if.end:
1231 // CHECK3-NEXT:    [[TMP59:%.*]] = load i16, ptr [[A_ADDR]], align 2
1232 // CHECK3-NEXT:    [[CONV5:%.*]] = sext i16 [[TMP59]] to i32
1233 // CHECK3-NEXT:    [[TMP60:%.*]] = load i16, ptr [[B_ADDR]], align 2
1234 // CHECK3-NEXT:    [[CONV6:%.*]] = sext i16 [[TMP60]] to i32
1235 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV5]], [[CONV6]]
1236 // CHECK3-NEXT:    [[TMP61:%.*]] = load i16, ptr [[C_ADDR]], align 2
1237 // CHECK3-NEXT:    [[CONV7:%.*]] = sext i16 [[TMP61]] to i32
1238 // CHECK3-NEXT:    [[ADD8:%.*]] = add nsw i32 [[ADD]], [[CONV7]]
1239 // CHECK3-NEXT:    [[TMP62:%.*]] = load i16, ptr [[D_ADDR]], align 2
1240 // CHECK3-NEXT:    [[CONV9:%.*]] = sext i16 [[TMP62]] to i32
1241 // CHECK3-NEXT:    [[ADD10:%.*]] = add nsw i32 [[ADD8]], [[CONV9]]
1242 // CHECK3-NEXT:    [[TMP63:%.*]] = load float, ptr @_ZZ3foossssE2Sa, align 4
1243 // CHECK3-NEXT:    [[CONV11:%.*]] = fptosi float [[TMP63]] to i32
1244 // CHECK3-NEXT:    [[ADD12:%.*]] = add nsw i32 [[ADD10]], [[CONV11]]
1245 // CHECK3-NEXT:    [[TMP64:%.*]] = load float, ptr @_ZZ3foossssE2Sb, align 4
1246 // CHECK3-NEXT:    [[CONV13:%.*]] = fptosi float [[TMP64]] to i32
1247 // CHECK3-NEXT:    [[ADD14:%.*]] = add nsw i32 [[ADD12]], [[CONV13]]
1248 // CHECK3-NEXT:    [[TMP65:%.*]] = load float, ptr @_ZZ3foossssE2Sc, align 4
1249 // CHECK3-NEXT:    [[CONV15:%.*]] = fptosi float [[TMP65]] to i32
1250 // CHECK3-NEXT:    [[ADD16:%.*]] = add nsw i32 [[ADD14]], [[CONV15]]
1251 // CHECK3-NEXT:    [[TMP66:%.*]] = load float, ptr @_ZZ3foossssE2Sd, align 4
1252 // CHECK3-NEXT:    [[CONV17:%.*]] = fptosi float [[TMP66]] to i32
1253 // CHECK3-NEXT:    [[ADD18:%.*]] = add nsw i32 [[ADD16]], [[CONV17]]
1254 // CHECK3-NEXT:    ret i32 [[ADD18]]
1255 //
1256 //
1257 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foossss_l49
1258 // CHECK3-SAME: (i32 noundef [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[GB:%.*]], i32 noundef [[SB:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[GC:%.*]], i32 noundef [[C:%.*]], i32 noundef [[SC:%.*]], i32 noundef [[D:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[GD:%.*]], i32 noundef [[SD:%.*]]) #[[ATTR1:[0-9]+]] {
1259 // CHECK3-NEXT:  entry:
1260 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
1261 // CHECK3-NEXT:    [[GB_ADDR:%.*]] = alloca ptr, align 4
1262 // CHECK3-NEXT:    [[SB_ADDR:%.*]] = alloca i32, align 4
1263 // CHECK3-NEXT:    [[GC_ADDR:%.*]] = alloca ptr, align 4
1264 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca i32, align 4
1265 // CHECK3-NEXT:    [[SC_ADDR:%.*]] = alloca i32, align 4
1266 // CHECK3-NEXT:    [[D_ADDR:%.*]] = alloca i32, align 4
1267 // CHECK3-NEXT:    [[GD_ADDR:%.*]] = alloca ptr, align 4
1268 // CHECK3-NEXT:    [[SD_ADDR:%.*]] = alloca i32, align 4
1269 // CHECK3-NEXT:    [[GB1:%.*]] = alloca double, align 8
1270 // CHECK3-NEXT:    [[GC2:%.*]] = alloca double, align 8
1271 // CHECK3-NEXT:    [[GD3:%.*]] = alloca double, align 8
1272 // CHECK3-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
1273 // CHECK3-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
1274 // CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
1275 // CHECK3-NEXT:    store i32 [[B]], ptr [[B_ADDR]], align 4
1276 // CHECK3-NEXT:    store ptr [[GB]], ptr [[GB_ADDR]], align 4
1277 // CHECK3-NEXT:    store i32 [[SB]], ptr [[SB_ADDR]], align 4
1278 // CHECK3-NEXT:    store ptr [[GC]], ptr [[GC_ADDR]], align 4
1279 // CHECK3-NEXT:    store i32 [[C]], ptr [[C_ADDR]], align 4
1280 // CHECK3-NEXT:    store i32 [[SC]], ptr [[SC_ADDR]], align 4
1281 // CHECK3-NEXT:    store i32 [[D]], ptr [[D_ADDR]], align 4
1282 // CHECK3-NEXT:    store ptr [[GD]], ptr [[GD_ADDR]], align 4
1283 // CHECK3-NEXT:    store i32 [[SD]], ptr [[SD_ADDR]], align 4
1284 // CHECK3-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[GB_ADDR]], align 4
1285 // CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[GC_ADDR]], align 4
1286 // CHECK3-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[GD_ADDR]], align 4
1287 // CHECK3-NEXT:    [[TMP4:%.*]] = load double, ptr [[TMP1]], align 8
1288 // CHECK3-NEXT:    store double [[TMP4]], ptr [[GB1]], align 8
1289 // CHECK3-NEXT:    [[TMP5:%.*]] = load double, ptr [[TMP2]], align 8
1290 // CHECK3-NEXT:    store double [[TMP5]], ptr [[GC2]], align 8
1291 // CHECK3-NEXT:    [[TMP6:%.*]] = load double, ptr [[TMP3]], align 8
1292 // CHECK3-NEXT:    store double [[TMP6]], ptr [[GD3]], align 8
1293 // CHECK3-NEXT:    [[TMP7:%.*]] = load i16, ptr [[B_ADDR]], align 2
1294 // CHECK3-NEXT:    [[CONV:%.*]] = sext i16 [[TMP7]] to i32
1295 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV]], 1
1296 // CHECK3-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD]] to i16
1297 // CHECK3-NEXT:    store i16 [[CONV4]], ptr [[B_ADDR]], align 2
1298 // CHECK3-NEXT:    [[TMP8:%.*]] = load double, ptr [[GB1]], align 8
1299 // CHECK3-NEXT:    [[ADD5:%.*]] = fadd double [[TMP8]], 1.000000e+00
1300 // CHECK3-NEXT:    store double [[ADD5]], ptr [[GB1]], align 8
1301 // CHECK3-NEXT:    [[TMP9:%.*]] = load float, ptr [[SB_ADDR]], align 4
1302 // CHECK3-NEXT:    [[CONV6:%.*]] = fpext float [[TMP9]] to double
1303 // CHECK3-NEXT:    [[ADD7:%.*]] = fadd double [[CONV6]], 1.000000e+00
1304 // CHECK3-NEXT:    [[CONV8:%.*]] = fptrunc double [[ADD7]] to float
1305 // CHECK3-NEXT:    store float [[CONV8]], ptr [[SB_ADDR]], align 4
1306 // CHECK3-NEXT:    [[TMP10:%.*]] = load double, ptr [[GC2]], align 8
1307 // CHECK3-NEXT:    [[CMP:%.*]] = fcmp ogt double [[TMP10]], 0.000000e+00
1308 // CHECK3-NEXT:    br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
1309 // CHECK3:       land.lhs.true:
1310 // CHECK3-NEXT:    [[TMP11:%.*]] = load i16, ptr [[C_ADDR]], align 2
1311 // CHECK3-NEXT:    [[CONV9:%.*]] = sext i16 [[TMP11]] to i32
1312 // CHECK3-NEXT:    [[CMP10:%.*]] = icmp sgt i32 [[CONV9]], 0
1313 // CHECK3-NEXT:    br i1 [[CMP10]], label [[LAND_LHS_TRUE11:%.*]], label [[OMP_IF_ELSE]]
1314 // CHECK3:       land.lhs.true11:
1315 // CHECK3-NEXT:    [[TMP12:%.*]] = load float, ptr [[SC_ADDR]], align 4
1316 // CHECK3-NEXT:    [[CONV12:%.*]] = fpext float [[TMP12]] to double
1317 // CHECK3-NEXT:    [[CMP13:%.*]] = fcmp ogt double [[CONV12]], 0.000000e+00
1318 // CHECK3-NEXT:    br i1 [[CMP13]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]]
1319 // CHECK3:       omp_if.then:
1320 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foossss_l49.omp_outlined, ptr [[D_ADDR]], ptr [[GD3]], ptr [[SD_ADDR]])
1321 // CHECK3-NEXT:    br label [[OMP_IF_END:%.*]]
1322 // CHECK3:       omp_if.else:
1323 // CHECK3-NEXT:    call void @__kmpc_serialized_parallel(ptr @[[GLOB1]], i32 [[TMP0]])
1324 // CHECK3-NEXT:    store i32 [[TMP0]], ptr [[DOTTHREADID_TEMP_]], align 4
1325 // CHECK3-NEXT:    store i32 0, ptr [[DOTBOUND_ZERO_ADDR]], align 4
1326 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foossss_l49.omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], ptr [[D_ADDR]], ptr [[GD3]], ptr [[SD_ADDR]]) #[[ATTR2]]
1327 // CHECK3-NEXT:    call void @__kmpc_end_serialized_parallel(ptr @[[GLOB1]], i32 [[TMP0]])
1328 // CHECK3-NEXT:    br label [[OMP_IF_END]]
1329 // CHECK3:       omp_if.end:
1330 // CHECK3-NEXT:    ret void
1331 //
1332 //
1333 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foossss_l49.omp_outlined
1334 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[D:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[GD:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SD:%.*]]) #[[ATTR1]] {
1335 // CHECK3-NEXT:  entry:
1336 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
1337 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
1338 // CHECK3-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4
1339 // CHECK3-NEXT:    [[GD_ADDR:%.*]] = alloca ptr, align 4
1340 // CHECK3-NEXT:    [[SD_ADDR:%.*]] = alloca ptr, align 4
1341 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
1342 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
1343 // CHECK3-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4
1344 // CHECK3-NEXT:    store ptr [[GD]], ptr [[GD_ADDR]], align 4
1345 // CHECK3-NEXT:    store ptr [[SD]], ptr [[SD_ADDR]], align 4
1346 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 4
1347 // CHECK3-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[GD_ADDR]], align 4
1348 // CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[SD_ADDR]], align 4
1349 // CHECK3-NEXT:    [[TMP3:%.*]] = load i16, ptr [[TMP0]], align 2
1350 // CHECK3-NEXT:    [[CONV:%.*]] = sext i16 [[TMP3]] to i32
1351 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV]], 1
1352 // CHECK3-NEXT:    [[CONV1:%.*]] = trunc i32 [[ADD]] to i16
1353 // CHECK3-NEXT:    store i16 [[CONV1]], ptr [[TMP0]], align 2
1354 // CHECK3-NEXT:    [[TMP4:%.*]] = load double, ptr [[TMP1]], align 8
1355 // CHECK3-NEXT:    [[ADD2:%.*]] = fadd double [[TMP4]], 1.000000e+00
1356 // CHECK3-NEXT:    store double [[ADD2]], ptr [[TMP1]], align 8
1357 // CHECK3-NEXT:    [[TMP5:%.*]] = load float, ptr [[TMP2]], align 4
1358 // CHECK3-NEXT:    [[CONV3:%.*]] = fpext float [[TMP5]] to double
1359 // CHECK3-NEXT:    [[ADD4:%.*]] = fadd double [[CONV3]], 1.000000e+00
1360 // CHECK3-NEXT:    [[CONV5:%.*]] = fptrunc double [[ADD4]] to float
1361 // CHECK3-NEXT:    store float [[CONV5]], ptr [[TMP2]], align 4
1362 // CHECK3-NEXT:    ret void
1363 //
1364 //
1365 // CHECK3-LABEL: define {{[^@]+}}@_Z3barssss
1366 // CHECK3-SAME: (i16 noundef signext [[A:%.*]], i16 noundef signext [[B:%.*]], i16 noundef signext [[C:%.*]], i16 noundef signext [[D:%.*]]) #[[ATTR0]] {
1367 // CHECK3-NEXT:  entry:
1368 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i16, align 2
1369 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca i16, align 2
1370 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca i16, align 2
1371 // CHECK3-NEXT:    [[D_ADDR:%.*]] = alloca i16, align 2
1372 // CHECK3-NEXT:    store i16 [[A]], ptr [[A_ADDR]], align 2
1373 // CHECK3-NEXT:    store i16 [[B]], ptr [[B_ADDR]], align 2
1374 // CHECK3-NEXT:    store i16 [[C]], ptr [[C_ADDR]], align 2
1375 // CHECK3-NEXT:    store i16 [[D]], ptr [[D_ADDR]], align 2
1376 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 4, ptr @_Z3barssss.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])
1377 // CHECK3-NEXT:    [[TMP0:%.*]] = load i16, ptr [[A_ADDR]], align 2
1378 // CHECK3-NEXT:    [[CONV:%.*]] = sext i16 [[TMP0]] to i32
1379 // CHECK3-NEXT:    [[TMP1:%.*]] = load i16, ptr [[B_ADDR]], align 2
1380 // CHECK3-NEXT:    [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
1381 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV]], [[CONV1]]
1382 // CHECK3-NEXT:    [[TMP2:%.*]] = load i16, ptr [[C_ADDR]], align 2
1383 // CHECK3-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
1384 // CHECK3-NEXT:    [[ADD3:%.*]] = add nsw i32 [[ADD]], [[CONV2]]
1385 // CHECK3-NEXT:    [[TMP3:%.*]] = load i16, ptr [[D_ADDR]], align 2
1386 // CHECK3-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP3]] to i32
1387 // CHECK3-NEXT:    [[ADD5:%.*]] = add nsw i32 [[ADD3]], [[CONV4]]
1388 // CHECK3-NEXT:    [[TMP4:%.*]] = load float, ptr @_ZZ3barssssE2Sa, align 4
1389 // CHECK3-NEXT:    [[CONV6:%.*]] = fptosi float [[TMP4]] to i32
1390 // CHECK3-NEXT:    [[ADD7:%.*]] = add nsw i32 [[ADD5]], [[CONV6]]
1391 // CHECK3-NEXT:    [[TMP5:%.*]] = load float, ptr @_ZZ3barssssE2Sb, align 4
1392 // CHECK3-NEXT:    [[CONV8:%.*]] = fptosi float [[TMP5]] to i32
1393 // CHECK3-NEXT:    [[ADD9:%.*]] = add nsw i32 [[ADD7]], [[CONV8]]
1394 // CHECK3-NEXT:    [[TMP6:%.*]] = load float, ptr @_ZZ3barssssE2Sc, align 4
1395 // CHECK3-NEXT:    [[CONV10:%.*]] = fptosi float [[TMP6]] to i32
1396 // CHECK3-NEXT:    [[ADD11:%.*]] = add nsw i32 [[ADD9]], [[CONV10]]
1397 // CHECK3-NEXT:    [[TMP7:%.*]] = load float, ptr @_ZZ3barssssE2Sd, align 4
1398 // CHECK3-NEXT:    [[CONV12:%.*]] = fptosi float [[TMP7]] to i32
1399 // CHECK3-NEXT:    [[ADD13:%.*]] = add nsw i32 [[ADD11]], [[CONV12]]
1400 // CHECK3-NEXT:    ret i32 [[ADD13]]
1401 //
1402 //
1403 // CHECK3-LABEL: define {{[^@]+}}@_Z3barssss.omp_outlined
1404 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[A:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[B:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[D:%.*]]) #[[ATTR1]] {
1405 // CHECK3-NEXT:  entry:
1406 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
1407 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
1408 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 4
1409 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
1410 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
1411 // CHECK3-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4
1412 // CHECK3-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
1413 // CHECK3-NEXT:    [[SB_CASTED:%.*]] = alloca i32, align 4
1414 // CHECK3-NEXT:    [[C_CASTED:%.*]] = alloca i32, align 4
1415 // CHECK3-NEXT:    [[SC_CASTED:%.*]] = alloca i32, align 4
1416 // CHECK3-NEXT:    [[D_CASTED:%.*]] = alloca i32, align 4
1417 // CHECK3-NEXT:    [[SD_CASTED:%.*]] = alloca i32, align 4
1418 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [9 x ptr], align 4
1419 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [9 x ptr], align 4
1420 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [9 x ptr], align 4
1421 // CHECK3-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1422 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
1423 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
1424 // CHECK3-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 4
1425 // CHECK3-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
1426 // CHECK3-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
1427 // CHECK3-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4
1428 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4
1429 // CHECK3-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 4
1430 // CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 4
1431 // CHECK3-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 4
1432 // CHECK3-NEXT:    [[TMP4:%.*]] = load i16, ptr [[TMP1]], align 2
1433 // CHECK3-NEXT:    store i16 [[TMP4]], ptr [[B_CASTED]], align 2
1434 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4
1435 // CHECK3-NEXT:    [[TMP6:%.*]] = load float, ptr @_ZZ3barssssE2Sb, align 4
1436 // CHECK3-NEXT:    store float [[TMP6]], ptr [[SB_CASTED]], align 4
1437 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[SB_CASTED]], align 4
1438 // CHECK3-NEXT:    [[TMP8:%.*]] = load i16, ptr [[TMP2]], align 2
1439 // CHECK3-NEXT:    store i16 [[TMP8]], ptr [[C_CASTED]], align 2
1440 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[C_CASTED]], align 4
1441 // CHECK3-NEXT:    [[TMP10:%.*]] = load float, ptr @_ZZ3barssssE2Sc, align 4
1442 // CHECK3-NEXT:    store float [[TMP10]], ptr [[SC_CASTED]], align 4
1443 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[SC_CASTED]], align 4
1444 // CHECK3-NEXT:    [[TMP12:%.*]] = load i16, ptr [[TMP3]], align 2
1445 // CHECK3-NEXT:    store i16 [[TMP12]], ptr [[D_CASTED]], align 2
1446 // CHECK3-NEXT:    [[TMP13:%.*]] = load i32, ptr [[D_CASTED]], align 4
1447 // CHECK3-NEXT:    [[TMP14:%.*]] = load float, ptr @_ZZ3barssssE2Sd, align 4
1448 // CHECK3-NEXT:    store float [[TMP14]], ptr [[SD_CASTED]], align 4
1449 // CHECK3-NEXT:    [[TMP15:%.*]] = load i32, ptr [[SD_CASTED]], align 4
1450 // CHECK3-NEXT:    [[TMP16:%.*]] = load double, ptr @Ga, align 8
1451 // CHECK3-NEXT:    [[CMP:%.*]] = fcmp ogt double [[TMP16]], 0.000000e+00
1452 // CHECK3-NEXT:    br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
1453 // CHECK3:       land.lhs.true:
1454 // CHECK3-NEXT:    [[TMP17:%.*]] = load i16, ptr [[TMP0]], align 2
1455 // CHECK3-NEXT:    [[CONV:%.*]] = sext i16 [[TMP17]] to i32
1456 // CHECK3-NEXT:    [[CMP1:%.*]] = icmp sgt i32 [[CONV]], 0
1457 // CHECK3-NEXT:    br i1 [[CMP1]], label [[LAND_LHS_TRUE2:%.*]], label [[OMP_IF_ELSE]]
1458 // CHECK3:       land.lhs.true2:
1459 // CHECK3-NEXT:    [[TMP18:%.*]] = load float, ptr @_ZZ3barssssE2Sa, align 4
1460 // CHECK3-NEXT:    [[CONV3:%.*]] = fpext float [[TMP18]] to double
1461 // CHECK3-NEXT:    [[CMP4:%.*]] = fcmp ogt double [[CONV3]], 0.000000e+00
1462 // CHECK3-NEXT:    br i1 [[CMP4]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]]
1463 // CHECK3:       omp_if.then:
1464 // CHECK3-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1465 // CHECK3-NEXT:    store i32 [[TMP5]], ptr [[TMP19]], align 4
1466 // CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1467 // CHECK3-NEXT:    store i32 [[TMP5]], ptr [[TMP20]], align 4
1468 // CHECK3-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
1469 // CHECK3-NEXT:    store ptr null, ptr [[TMP21]], align 4
1470 // CHECK3-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1471 // CHECK3-NEXT:    store ptr @Gb, ptr [[TMP22]], align 4
1472 // CHECK3-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1473 // CHECK3-NEXT:    store ptr @Gb, ptr [[TMP23]], align 4
1474 // CHECK3-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
1475 // CHECK3-NEXT:    store ptr null, ptr [[TMP24]], align 4
1476 // CHECK3-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1477 // CHECK3-NEXT:    store i32 [[TMP7]], ptr [[TMP25]], align 4
1478 // CHECK3-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1479 // CHECK3-NEXT:    store i32 [[TMP7]], ptr [[TMP26]], align 4
1480 // CHECK3-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
1481 // CHECK3-NEXT:    store ptr null, ptr [[TMP27]], align 4
1482 // CHECK3-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1483 // CHECK3-NEXT:    store ptr @Gc, ptr [[TMP28]], align 4
1484 // CHECK3-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1485 // CHECK3-NEXT:    store ptr @Gc, ptr [[TMP29]], align 4
1486 // CHECK3-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
1487 // CHECK3-NEXT:    store ptr null, ptr [[TMP30]], align 4
1488 // CHECK3-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
1489 // CHECK3-NEXT:    store i32 [[TMP9]], ptr [[TMP31]], align 4
1490 // CHECK3-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4
1491 // CHECK3-NEXT:    store i32 [[TMP9]], ptr [[TMP32]], align 4
1492 // CHECK3-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
1493 // CHECK3-NEXT:    store ptr null, ptr [[TMP33]], align 4
1494 // CHECK3-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5
1495 // CHECK3-NEXT:    store i32 [[TMP11]], ptr [[TMP34]], align 4
1496 // CHECK3-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 5
1497 // CHECK3-NEXT:    store i32 [[TMP11]], ptr [[TMP35]], align 4
1498 // CHECK3-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 5
1499 // CHECK3-NEXT:    store ptr null, ptr [[TMP36]], align 4
1500 // CHECK3-NEXT:    [[TMP37:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6
1501 // CHECK3-NEXT:    store i32 [[TMP13]], ptr [[TMP37]], align 4
1502 // CHECK3-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 6
1503 // CHECK3-NEXT:    store i32 [[TMP13]], ptr [[TMP38]], align 4
1504 // CHECK3-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 6
1505 // CHECK3-NEXT:    store ptr null, ptr [[TMP39]], align 4
1506 // CHECK3-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7
1507 // CHECK3-NEXT:    store ptr @Gd, ptr [[TMP40]], align 4
1508 // CHECK3-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 7
1509 // CHECK3-NEXT:    store ptr @Gd, ptr [[TMP41]], align 4
1510 // CHECK3-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 7
1511 // CHECK3-NEXT:    store ptr null, ptr [[TMP42]], align 4
1512 // CHECK3-NEXT:    [[TMP43:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 8
1513 // CHECK3-NEXT:    store i32 [[TMP15]], ptr [[TMP43]], align 4
1514 // CHECK3-NEXT:    [[TMP44:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 8
1515 // CHECK3-NEXT:    store i32 [[TMP15]], ptr [[TMP44]], align 4
1516 // CHECK3-NEXT:    [[TMP45:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 8
1517 // CHECK3-NEXT:    store ptr null, ptr [[TMP45]], align 4
1518 // CHECK3-NEXT:    [[TMP46:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1519 // CHECK3-NEXT:    [[TMP47:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1520 // CHECK3-NEXT:    [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
1521 // CHECK3-NEXT:    store i32 2, ptr [[TMP48]], align 4
1522 // CHECK3-NEXT:    [[TMP49:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
1523 // CHECK3-NEXT:    store i32 9, ptr [[TMP49]], align 4
1524 // CHECK3-NEXT:    [[TMP50:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
1525 // CHECK3-NEXT:    store ptr [[TMP46]], ptr [[TMP50]], align 4
1526 // CHECK3-NEXT:    [[TMP51:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
1527 // CHECK3-NEXT:    store ptr [[TMP47]], ptr [[TMP51]], align 4
1528 // CHECK3-NEXT:    [[TMP52:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
1529 // CHECK3-NEXT:    store ptr @.offload_sizes.1, ptr [[TMP52]], align 4
1530 // CHECK3-NEXT:    [[TMP53:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
1531 // CHECK3-NEXT:    store ptr @.offload_maptypes.2, ptr [[TMP53]], align 4
1532 // CHECK3-NEXT:    [[TMP54:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
1533 // CHECK3-NEXT:    store ptr null, ptr [[TMP54]], align 4
1534 // CHECK3-NEXT:    [[TMP55:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
1535 // CHECK3-NEXT:    store ptr null, ptr [[TMP55]], align 4
1536 // CHECK3-NEXT:    [[TMP56:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
1537 // CHECK3-NEXT:    store i64 0, ptr [[TMP56]], align 8
1538 // CHECK3-NEXT:    [[TMP57:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
1539 // CHECK3-NEXT:    store i64 0, ptr [[TMP57]], align 8
1540 // CHECK3-NEXT:    [[TMP58:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
1541 // CHECK3-NEXT:    store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP58]], align 4
1542 // CHECK3-NEXT:    [[TMP59:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
1543 // CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP59]], align 4
1544 // CHECK3-NEXT:    [[TMP60:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
1545 // CHECK3-NEXT:    store i32 0, ptr [[TMP60]], align 4
1546 // CHECK3-NEXT:    [[TMP61:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barssss_l94.region_id, ptr [[KERNEL_ARGS]])
1547 // CHECK3-NEXT:    [[TMP62:%.*]] = icmp ne i32 [[TMP61]], 0
1548 // CHECK3-NEXT:    br i1 [[TMP62]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1549 // CHECK3:       omp_offload.failed:
1550 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barssss_l94(i32 [[TMP5]], ptr @Gb, i32 [[TMP7]], ptr @Gc, i32 [[TMP9]], i32 [[TMP11]], i32 [[TMP13]], ptr @Gd, i32 [[TMP15]]) #[[ATTR2]]
1551 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]
1552 // CHECK3:       omp_offload.cont:
1553 // CHECK3-NEXT:    br label [[OMP_IF_END:%.*]]
1554 // CHECK3:       omp_if.else:
1555 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barssss_l94(i32 [[TMP5]], ptr @Gb, i32 [[TMP7]], ptr @Gc, i32 [[TMP9]], i32 [[TMP11]], i32 [[TMP13]], ptr @Gd, i32 [[TMP15]]) #[[ATTR2]]
1556 // CHECK3-NEXT:    br label [[OMP_IF_END]]
1557 // CHECK3:       omp_if.end:
1558 // CHECK3-NEXT:    ret void
1559 //
1560 //
1561 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barssss_l94
1562 // CHECK3-SAME: (i32 noundef [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[GB:%.*]], i32 noundef [[SB:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[GC:%.*]], i32 noundef [[C:%.*]], i32 noundef [[SC:%.*]], i32 noundef [[D:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[GD:%.*]], i32 noundef [[SD:%.*]]) #[[ATTR1]] {
1563 // CHECK3-NEXT:  entry:
1564 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
1565 // CHECK3-NEXT:    [[GB_ADDR:%.*]] = alloca ptr, align 4
1566 // CHECK3-NEXT:    [[SB_ADDR:%.*]] = alloca i32, align 4
1567 // CHECK3-NEXT:    [[GC_ADDR:%.*]] = alloca ptr, align 4
1568 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca i32, align 4
1569 // CHECK3-NEXT:    [[SC_ADDR:%.*]] = alloca i32, align 4
1570 // CHECK3-NEXT:    [[D_ADDR:%.*]] = alloca i32, align 4
1571 // CHECK3-NEXT:    [[GD_ADDR:%.*]] = alloca ptr, align 4
1572 // CHECK3-NEXT:    [[SD_ADDR:%.*]] = alloca i32, align 4
1573 // CHECK3-NEXT:    [[GB1:%.*]] = alloca double, align 8
1574 // CHECK3-NEXT:    [[GC2:%.*]] = alloca double, align 8
1575 // CHECK3-NEXT:    [[GD3:%.*]] = alloca double, align 8
1576 // CHECK3-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
1577 // CHECK3-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
1578 // CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
1579 // CHECK3-NEXT:    store i32 [[B]], ptr [[B_ADDR]], align 4
1580 // CHECK3-NEXT:    store ptr [[GB]], ptr [[GB_ADDR]], align 4
1581 // CHECK3-NEXT:    store i32 [[SB]], ptr [[SB_ADDR]], align 4
1582 // CHECK3-NEXT:    store ptr [[GC]], ptr [[GC_ADDR]], align 4
1583 // CHECK3-NEXT:    store i32 [[C]], ptr [[C_ADDR]], align 4
1584 // CHECK3-NEXT:    store i32 [[SC]], ptr [[SC_ADDR]], align 4
1585 // CHECK3-NEXT:    store i32 [[D]], ptr [[D_ADDR]], align 4
1586 // CHECK3-NEXT:    store ptr [[GD]], ptr [[GD_ADDR]], align 4
1587 // CHECK3-NEXT:    store i32 [[SD]], ptr [[SD_ADDR]], align 4
1588 // CHECK3-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[GB_ADDR]], align 4
1589 // CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[GC_ADDR]], align 4
1590 // CHECK3-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[GD_ADDR]], align 4
1591 // CHECK3-NEXT:    [[TMP4:%.*]] = load double, ptr [[TMP1]], align 8
1592 // CHECK3-NEXT:    store double [[TMP4]], ptr [[GB1]], align 8
1593 // CHECK3-NEXT:    [[TMP5:%.*]] = load double, ptr [[TMP2]], align 8
1594 // CHECK3-NEXT:    store double [[TMP5]], ptr [[GC2]], align 8
1595 // CHECK3-NEXT:    [[TMP6:%.*]] = load double, ptr [[TMP3]], align 8
1596 // CHECK3-NEXT:    store double [[TMP6]], ptr [[GD3]], align 8
1597 // CHECK3-NEXT:    [[TMP7:%.*]] = load i16, ptr [[B_ADDR]], align 2
1598 // CHECK3-NEXT:    [[CONV:%.*]] = sext i16 [[TMP7]] to i32
1599 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV]], 1
1600 // CHECK3-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD]] to i16
1601 // CHECK3-NEXT:    store i16 [[CONV4]], ptr [[B_ADDR]], align 2
1602 // CHECK3-NEXT:    [[TMP8:%.*]] = load double, ptr [[GB1]], align 8
1603 // CHECK3-NEXT:    [[ADD5:%.*]] = fadd double [[TMP8]], 1.000000e+00
1604 // CHECK3-NEXT:    store double [[ADD5]], ptr [[GB1]], align 8
1605 // CHECK3-NEXT:    [[TMP9:%.*]] = load float, ptr [[SB_ADDR]], align 4
1606 // CHECK3-NEXT:    [[CONV6:%.*]] = fpext float [[TMP9]] to double
1607 // CHECK3-NEXT:    [[ADD7:%.*]] = fadd double [[CONV6]], 1.000000e+00
1608 // CHECK3-NEXT:    [[CONV8:%.*]] = fptrunc double [[ADD7]] to float
1609 // CHECK3-NEXT:    store float [[CONV8]], ptr [[SB_ADDR]], align 4
1610 // CHECK3-NEXT:    [[TMP10:%.*]] = load double, ptr [[GC2]], align 8
1611 // CHECK3-NEXT:    [[CMP:%.*]] = fcmp ogt double [[TMP10]], 0.000000e+00
1612 // CHECK3-NEXT:    br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
1613 // CHECK3:       land.lhs.true:
1614 // CHECK3-NEXT:    [[TMP11:%.*]] = load i16, ptr [[C_ADDR]], align 2
1615 // CHECK3-NEXT:    [[CONV9:%.*]] = sext i16 [[TMP11]] to i32
1616 // CHECK3-NEXT:    [[CMP10:%.*]] = icmp sgt i32 [[CONV9]], 0
1617 // CHECK3-NEXT:    br i1 [[CMP10]], label [[LAND_LHS_TRUE11:%.*]], label [[OMP_IF_ELSE]]
1618 // CHECK3:       land.lhs.true11:
1619 // CHECK3-NEXT:    [[TMP12:%.*]] = load float, ptr [[SC_ADDR]], align 4
1620 // CHECK3-NEXT:    [[CONV12:%.*]] = fpext float [[TMP12]] to double
1621 // CHECK3-NEXT:    [[CMP13:%.*]] = fcmp ogt double [[CONV12]], 0.000000e+00
1622 // CHECK3-NEXT:    br i1 [[CMP13]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]]
1623 // CHECK3:       omp_if.then:
1624 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barssss_l94.omp_outlined, ptr [[D_ADDR]], ptr [[GD3]], ptr [[SD_ADDR]])
1625 // CHECK3-NEXT:    br label [[OMP_IF_END:%.*]]
1626 // CHECK3:       omp_if.else:
1627 // CHECK3-NEXT:    call void @__kmpc_serialized_parallel(ptr @[[GLOB1]], i32 [[TMP0]])
1628 // CHECK3-NEXT:    store i32 [[TMP0]], ptr [[DOTTHREADID_TEMP_]], align 4
1629 // CHECK3-NEXT:    store i32 0, ptr [[DOTBOUND_ZERO_ADDR]], align 4
1630 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barssss_l94.omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], ptr [[D_ADDR]], ptr [[GD3]], ptr [[SD_ADDR]]) #[[ATTR2]]
1631 // CHECK3-NEXT:    call void @__kmpc_end_serialized_parallel(ptr @[[GLOB1]], i32 [[TMP0]])
1632 // CHECK3-NEXT:    br label [[OMP_IF_END]]
1633 // CHECK3:       omp_if.end:
1634 // CHECK3-NEXT:    ret void
1635 //
1636 //
1637 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3barssss_l94.omp_outlined
1638 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[D:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[GD:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SD:%.*]]) #[[ATTR1]] {
1639 // CHECK3-NEXT:  entry:
1640 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
1641 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
1642 // CHECK3-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4
1643 // CHECK3-NEXT:    [[GD_ADDR:%.*]] = alloca ptr, align 4
1644 // CHECK3-NEXT:    [[SD_ADDR:%.*]] = alloca ptr, align 4
1645 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
1646 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
1647 // CHECK3-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4
1648 // CHECK3-NEXT:    store ptr [[GD]], ptr [[GD_ADDR]], align 4
1649 // CHECK3-NEXT:    store ptr [[SD]], ptr [[SD_ADDR]], align 4
1650 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 4
1651 // CHECK3-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[GD_ADDR]], align 4
1652 // CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[SD_ADDR]], align 4
1653 // CHECK3-NEXT:    [[TMP3:%.*]] = load i16, ptr [[TMP0]], align 2
1654 // CHECK3-NEXT:    [[CONV:%.*]] = sext i16 [[TMP3]] to i32
1655 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV]], 1
1656 // CHECK3-NEXT:    [[CONV1:%.*]] = trunc i32 [[ADD]] to i16
1657 // CHECK3-NEXT:    store i16 [[CONV1]], ptr [[TMP0]], align 2
1658 // CHECK3-NEXT:    [[TMP4:%.*]] = load double, ptr [[TMP1]], align 8
1659 // CHECK3-NEXT:    [[ADD2:%.*]] = fadd double [[TMP4]], 1.000000e+00
1660 // CHECK3-NEXT:    store double [[ADD2]], ptr [[TMP1]], align 8
1661 // CHECK3-NEXT:    [[TMP5:%.*]] = load float, ptr [[TMP2]], align 4
1662 // CHECK3-NEXT:    [[CONV3:%.*]] = fpext float [[TMP5]] to double
1663 // CHECK3-NEXT:    [[ADD4:%.*]] = fadd double [[CONV3]], 1.000000e+00
1664 // CHECK3-NEXT:    [[CONV5:%.*]] = fptrunc double [[ADD4]] to float
1665 // CHECK3-NEXT:    store float [[CONV5]], ptr [[TMP2]], align 4
1666 // CHECK3-NEXT:    ret void
1667 //
1668 //
1669 // CHECK3-LABEL: define {{[^@]+}}@_Z5tbar2ssss
1670 // CHECK3-SAME: (i16 noundef signext [[A:%.*]], i16 noundef signext [[B:%.*]], i16 noundef signext [[C:%.*]], i16 noundef signext [[D:%.*]]) #[[ATTR0]] {
1671 // CHECK3-NEXT:  entry:
1672 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i16, align 2
1673 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca i16, align 2
1674 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca i16, align 2
1675 // CHECK3-NEXT:    [[D_ADDR:%.*]] = alloca i16, align 2
1676 // CHECK3-NEXT:    store i16 [[A]], ptr [[A_ADDR]], align 2
1677 // CHECK3-NEXT:    store i16 [[B]], ptr [[B_ADDR]], align 2
1678 // CHECK3-NEXT:    store i16 [[C]], ptr [[C_ADDR]], align 2
1679 // CHECK3-NEXT:    store i16 [[D]], ptr [[D_ADDR]], align 2
1680 // CHECK3-NEXT:    [[TMP0:%.*]] = load i16, ptr [[A_ADDR]], align 2
1681 // CHECK3-NEXT:    [[TMP1:%.*]] = load i16, ptr [[B_ADDR]], align 2
1682 // CHECK3-NEXT:    [[TMP2:%.*]] = load i16, ptr [[C_ADDR]], align 2
1683 // CHECK3-NEXT:    [[TMP3:%.*]] = load i16, ptr [[D_ADDR]], align 2
1684 // CHECK3-NEXT:    [[CALL:%.*]] = call noundef i32 @_Z4tbarIsEiT_S0_S0_S0_(i16 noundef signext [[TMP0]], i16 noundef signext [[TMP1]], i16 noundef signext [[TMP2]], i16 noundef signext [[TMP3]])
1685 // CHECK3-NEXT:    ret i32 [[CALL]]
1686 //
1687 //
1688 // CHECK3-LABEL: define {{[^@]+}}@_Z4tbarIsEiT_S0_S0_S0_
1689 // CHECK3-SAME: (i16 noundef signext [[A:%.*]], i16 noundef signext [[B:%.*]], i16 noundef signext [[C:%.*]], i16 noundef signext [[D:%.*]]) #[[ATTR0]] comdat {
1690 // CHECK3-NEXT:  entry:
1691 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i16, align 2
1692 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca i16, align 2
1693 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca i16, align 2
1694 // CHECK3-NEXT:    [[D_ADDR:%.*]] = alloca i16, align 2
1695 // CHECK3-NEXT:    store i16 [[A]], ptr [[A_ADDR]], align 2
1696 // CHECK3-NEXT:    store i16 [[B]], ptr [[B_ADDR]], align 2
1697 // CHECK3-NEXT:    store i16 [[C]], ptr [[C_ADDR]], align 2
1698 // CHECK3-NEXT:    store i16 [[D]], ptr [[D_ADDR]], align 2
1699 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 4, ptr @_Z4tbarIsEiT_S0_S0_S0_.omp_outlined, ptr [[A_ADDR]], ptr [[B_ADDR]], ptr [[C_ADDR]], ptr [[D_ADDR]])
1700 // CHECK3-NEXT:    [[TMP0:%.*]] = load i16, ptr [[A_ADDR]], align 2
1701 // CHECK3-NEXT:    [[CONV:%.*]] = sext i16 [[TMP0]] to i32
1702 // CHECK3-NEXT:    [[TMP1:%.*]] = load i16, ptr [[B_ADDR]], align 2
1703 // CHECK3-NEXT:    [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
1704 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV]], [[CONV1]]
1705 // CHECK3-NEXT:    [[TMP2:%.*]] = load i16, ptr [[C_ADDR]], align 2
1706 // CHECK3-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
1707 // CHECK3-NEXT:    [[ADD3:%.*]] = add nsw i32 [[ADD]], [[CONV2]]
1708 // CHECK3-NEXT:    [[TMP3:%.*]] = load i16, ptr [[D_ADDR]], align 2
1709 // CHECK3-NEXT:    [[CONV4:%.*]] = sext i16 [[TMP3]] to i32
1710 // CHECK3-NEXT:    [[ADD5:%.*]] = add nsw i32 [[ADD3]], [[CONV4]]
1711 // CHECK3-NEXT:    [[TMP4:%.*]] = load float, ptr @_ZZ4tbarIsEiT_S0_S0_S0_E2Sa, align 4
1712 // CHECK3-NEXT:    [[CONV6:%.*]] = fptosi float [[TMP4]] to i32
1713 // CHECK3-NEXT:    [[ADD7:%.*]] = add nsw i32 [[ADD5]], [[CONV6]]
1714 // CHECK3-NEXT:    [[TMP5:%.*]] = load float, ptr @_ZZ4tbarIsEiT_S0_S0_S0_E2Sb, align 4
1715 // CHECK3-NEXT:    [[CONV8:%.*]] = fptosi float [[TMP5]] to i32
1716 // CHECK3-NEXT:    [[ADD9:%.*]] = add nsw i32 [[ADD7]], [[CONV8]]
1717 // CHECK3-NEXT:    [[TMP6:%.*]] = load float, ptr @_ZZ4tbarIsEiT_S0_S0_S0_E2Sc, align 4
1718 // CHECK3-NEXT:    [[CONV10:%.*]] = fptosi float [[TMP6]] to i32
1719 // CHECK3-NEXT:    [[ADD11:%.*]] = add nsw i32 [[ADD9]], [[CONV10]]
1720 // CHECK3-NEXT:    [[TMP7:%.*]] = load float, ptr @_ZZ4tbarIsEiT_S0_S0_S0_E2Sd, align 4
1721 // CHECK3-NEXT:    [[CONV12:%.*]] = fptosi float [[TMP7]] to i32
1722 // CHECK3-NEXT:    [[ADD13:%.*]] = add nsw i32 [[ADD11]], [[CONV12]]
1723 // CHECK3-NEXT:    ret i32 [[ADD13]]
1724 //
1725 //
1726 // CHECK3-LABEL: define {{[^@]+}}@_Z4tbarIsEiT_S0_S0_S0_.omp_outlined
1727 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[A:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[B:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[D:%.*]]) #[[ATTR1]] {
1728 // CHECK3-NEXT:  entry:
1729 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
1730 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
1731 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca ptr, align 4
1732 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
1733 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
1734 // CHECK3-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4
1735 // CHECK3-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
1736 // CHECK3-NEXT:    [[SB_CASTED:%.*]] = alloca i32, align 4
1737 // CHECK3-NEXT:    [[C_CASTED:%.*]] = alloca i32, align 4
1738 // CHECK3-NEXT:    [[SC_CASTED:%.*]] = alloca i32, align 4
1739 // CHECK3-NEXT:    [[D_CASTED:%.*]] = alloca i32, align 4
1740 // CHECK3-NEXT:    [[SD_CASTED:%.*]] = alloca i32, align 4
1741 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [9 x ptr], align 4
1742 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [9 x ptr], align 4
1743 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [9 x ptr], align 4
1744 // CHECK3-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1745 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
1746 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
1747 // CHECK3-NEXT:    store ptr [[A]], ptr [[A_ADDR]], align 4
1748 // CHECK3-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
1749 // CHECK3-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
1750 // CHECK3-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4
1751 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4
1752 // CHECK3-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[B_ADDR]], align 4
1753 // CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[C_ADDR]], align 4
1754 // CHECK3-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[D_ADDR]], align 4
1755 // CHECK3-NEXT:    [[TMP4:%.*]] = load i16, ptr [[TMP1]], align 2
1756 // CHECK3-NEXT:    store i16 [[TMP4]], ptr [[B_CASTED]], align 2
1757 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4
1758 // CHECK3-NEXT:    [[TMP6:%.*]] = load float, ptr @_ZZ4tbarIsEiT_S0_S0_S0_E2Sb, align 4
1759 // CHECK3-NEXT:    store float [[TMP6]], ptr [[SB_CASTED]], align 4
1760 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[SB_CASTED]], align 4
1761 // CHECK3-NEXT:    [[TMP8:%.*]] = load i16, ptr [[TMP2]], align 2
1762 // CHECK3-NEXT:    store i16 [[TMP8]], ptr [[C_CASTED]], align 2
1763 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[C_CASTED]], align 4
1764 // CHECK3-NEXT:    [[TMP10:%.*]] = load float, ptr @_ZZ4tbarIsEiT_S0_S0_S0_E2Sc, align 4
1765 // CHECK3-NEXT:    store float [[TMP10]], ptr [[SC_CASTED]], align 4
1766 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[SC_CASTED]], align 4
1767 // CHECK3-NEXT:    [[TMP12:%.*]] = load i16, ptr [[TMP3]], align 2
1768 // CHECK3-NEXT:    store i16 [[TMP12]], ptr [[D_CASTED]], align 2
1769 // CHECK3-NEXT:    [[TMP13:%.*]] = load i32, ptr [[D_CASTED]], align 4
1770 // CHECK3-NEXT:    [[TMP14:%.*]] = load float, ptr @_ZZ4tbarIsEiT_S0_S0_S0_E2Sd, align 4
1771 // CHECK3-NEXT:    store float [[TMP14]], ptr [[SD_CASTED]], align 4
1772 // CHECK3-NEXT:    [[TMP15:%.*]] = load i32, ptr [[SD_CASTED]], align 4
1773 // CHECK3-NEXT:    [[TMP16:%.*]] = load double, ptr @Ga, align 8
1774 // CHECK3-NEXT:    [[CMP:%.*]] = fcmp ogt double [[TMP16]], 0.000000e+00
1775 // CHECK3-NEXT:    br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
1776 // CHECK3:       land.lhs.true:
1777 // CHECK3-NEXT:    [[TMP17:%.*]] = load i16, ptr [[TMP0]], align 2
1778 // CHECK3-NEXT:    [[CONV:%.*]] = sext i16 [[TMP17]] to i32
1779 // CHECK3-NEXT:    [[CMP1:%.*]] = icmp sgt i32 [[CONV]], 0
1780 // CHECK3-NEXT:    br i1 [[CMP1]], label [[LAND_LHS_TRUE2:%.*]], label [[OMP_IF_ELSE]]
1781 // CHECK3:       land.lhs.true2:
1782 // CHECK3-NEXT:    [[TMP18:%.*]] = load float, ptr @_ZZ4tbarIsEiT_S0_S0_S0_E2Sa, align 4
1783 // CHECK3-NEXT:    [[CONV3:%.*]] = fpext float [[TMP18]] to double
1784 // CHECK3-NEXT:    [[CMP4:%.*]] = fcmp ogt double [[CONV3]], 0.000000e+00
1785 // CHECK3-NEXT:    br i1 [[CMP4]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]]
1786 // CHECK3:       omp_if.then:
1787 // CHECK3-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1788 // CHECK3-NEXT:    store i32 [[TMP5]], ptr [[TMP19]], align 4
1789 // CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1790 // CHECK3-NEXT:    store i32 [[TMP5]], ptr [[TMP20]], align 4
1791 // CHECK3-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
1792 // CHECK3-NEXT:    store ptr null, ptr [[TMP21]], align 4
1793 // CHECK3-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1794 // CHECK3-NEXT:    store ptr @Gb, ptr [[TMP22]], align 4
1795 // CHECK3-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1796 // CHECK3-NEXT:    store ptr @Gb, ptr [[TMP23]], align 4
1797 // CHECK3-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
1798 // CHECK3-NEXT:    store ptr null, ptr [[TMP24]], align 4
1799 // CHECK3-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1800 // CHECK3-NEXT:    store i32 [[TMP7]], ptr [[TMP25]], align 4
1801 // CHECK3-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1802 // CHECK3-NEXT:    store i32 [[TMP7]], ptr [[TMP26]], align 4
1803 // CHECK3-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
1804 // CHECK3-NEXT:    store ptr null, ptr [[TMP27]], align 4
1805 // CHECK3-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1806 // CHECK3-NEXT:    store ptr @Gc, ptr [[TMP28]], align 4
1807 // CHECK3-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1808 // CHECK3-NEXT:    store ptr @Gc, ptr [[TMP29]], align 4
1809 // CHECK3-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
1810 // CHECK3-NEXT:    store ptr null, ptr [[TMP30]], align 4
1811 // CHECK3-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
1812 // CHECK3-NEXT:    store i32 [[TMP9]], ptr [[TMP31]], align 4
1813 // CHECK3-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4
1814 // CHECK3-NEXT:    store i32 [[TMP9]], ptr [[TMP32]], align 4
1815 // CHECK3-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
1816 // CHECK3-NEXT:    store ptr null, ptr [[TMP33]], align 4
1817 // CHECK3-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5
1818 // CHECK3-NEXT:    store i32 [[TMP11]], ptr [[TMP34]], align 4
1819 // CHECK3-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 5
1820 // CHECK3-NEXT:    store i32 [[TMP11]], ptr [[TMP35]], align 4
1821 // CHECK3-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 5
1822 // CHECK3-NEXT:    store ptr null, ptr [[TMP36]], align 4
1823 // CHECK3-NEXT:    [[TMP37:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 6
1824 // CHECK3-NEXT:    store i32 [[TMP13]], ptr [[TMP37]], align 4
1825 // CHECK3-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 6
1826 // CHECK3-NEXT:    store i32 [[TMP13]], ptr [[TMP38]], align 4
1827 // CHECK3-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 6
1828 // CHECK3-NEXT:    store ptr null, ptr [[TMP39]], align 4
1829 // CHECK3-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 7
1830 // CHECK3-NEXT:    store ptr @Gd, ptr [[TMP40]], align 4
1831 // CHECK3-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 7
1832 // CHECK3-NEXT:    store ptr @Gd, ptr [[TMP41]], align 4
1833 // CHECK3-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 7
1834 // CHECK3-NEXT:    store ptr null, ptr [[TMP42]], align 4
1835 // CHECK3-NEXT:    [[TMP43:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 8
1836 // CHECK3-NEXT:    store i32 [[TMP15]], ptr [[TMP43]], align 4
1837 // CHECK3-NEXT:    [[TMP44:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 8
1838 // CHECK3-NEXT:    store i32 [[TMP15]], ptr [[TMP44]], align 4
1839 // CHECK3-NEXT:    [[TMP45:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 8
1840 // CHECK3-NEXT:    store ptr null, ptr [[TMP45]], align 4
1841 // CHECK3-NEXT:    [[TMP46:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1842 // CHECK3-NEXT:    [[TMP47:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1843 // CHECK3-NEXT:    [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
1844 // CHECK3-NEXT:    store i32 2, ptr [[TMP48]], align 4
1845 // CHECK3-NEXT:    [[TMP49:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
1846 // CHECK3-NEXT:    store i32 9, ptr [[TMP49]], align 4
1847 // CHECK3-NEXT:    [[TMP50:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
1848 // CHECK3-NEXT:    store ptr [[TMP46]], ptr [[TMP50]], align 4
1849 // CHECK3-NEXT:    [[TMP51:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
1850 // CHECK3-NEXT:    store ptr [[TMP47]], ptr [[TMP51]], align 4
1851 // CHECK3-NEXT:    [[TMP52:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
1852 // CHECK3-NEXT:    store ptr @.offload_sizes.3, ptr [[TMP52]], align 4
1853 // CHECK3-NEXT:    [[TMP53:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
1854 // CHECK3-NEXT:    store ptr @.offload_maptypes.4, ptr [[TMP53]], align 4
1855 // CHECK3-NEXT:    [[TMP54:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
1856 // CHECK3-NEXT:    store ptr null, ptr [[TMP54]], align 4
1857 // CHECK3-NEXT:    [[TMP55:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
1858 // CHECK3-NEXT:    store ptr null, ptr [[TMP55]], align 4
1859 // CHECK3-NEXT:    [[TMP56:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
1860 // CHECK3-NEXT:    store i64 0, ptr [[TMP56]], align 8
1861 // CHECK3-NEXT:    [[TMP57:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
1862 // CHECK3-NEXT:    store i64 0, ptr [[TMP57]], align 8
1863 // CHECK3-NEXT:    [[TMP58:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
1864 // CHECK3-NEXT:    store [3 x i32] [i32 -1, i32 0, i32 0], ptr [[TMP58]], align 4
1865 // CHECK3-NEXT:    [[TMP59:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
1866 // CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP59]], align 4
1867 // CHECK3-NEXT:    [[TMP60:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
1868 // CHECK3-NEXT:    store i32 0, ptr [[TMP60]], align 4
1869 // CHECK3-NEXT:    [[TMP61:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 -1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4tbarIsEiT_S0_S0_S0__l145.region_id, ptr [[KERNEL_ARGS]])
1870 // CHECK3-NEXT:    [[TMP62:%.*]] = icmp ne i32 [[TMP61]], 0
1871 // CHECK3-NEXT:    br i1 [[TMP62]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1872 // CHECK3:       omp_offload.failed:
1873 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4tbarIsEiT_S0_S0_S0__l145(i32 [[TMP5]], ptr @Gb, i32 [[TMP7]], ptr @Gc, i32 [[TMP9]], i32 [[TMP11]], i32 [[TMP13]], ptr @Gd, i32 [[TMP15]]) #[[ATTR2]]
1874 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]
1875 // CHECK3:       omp_offload.cont:
1876 // CHECK3-NEXT:    br label [[OMP_IF_END:%.*]]
1877 // CHECK3:       omp_if.else:
1878 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4tbarIsEiT_S0_S0_S0__l145(i32 [[TMP5]], ptr @Gb, i32 [[TMP7]], ptr @Gc, i32 [[TMP9]], i32 [[TMP11]], i32 [[TMP13]], ptr @Gd, i32 [[TMP15]]) #[[ATTR2]]
1879 // CHECK3-NEXT:    br label [[OMP_IF_END]]
1880 // CHECK3:       omp_if.end:
1881 // CHECK3-NEXT:    ret void
1882 //
1883 //
1884 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4tbarIsEiT_S0_S0_S0__l145
1885 // CHECK3-SAME: (i32 noundef [[B:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[GB:%.*]], i32 noundef [[SB:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[GC:%.*]], i32 noundef [[C:%.*]], i32 noundef [[SC:%.*]], i32 noundef [[D:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[GD:%.*]], i32 noundef [[SD:%.*]]) #[[ATTR1]] {
1886 // CHECK3-NEXT:  entry:
1887 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
1888 // CHECK3-NEXT:    [[GB_ADDR:%.*]] = alloca ptr, align 4
1889 // CHECK3-NEXT:    [[SB_ADDR:%.*]] = alloca i32, align 4
1890 // CHECK3-NEXT:    [[GC_ADDR:%.*]] = alloca ptr, align 4
1891 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca i32, align 4
1892 // CHECK3-NEXT:    [[SC_ADDR:%.*]] = alloca i32, align 4
1893 // CHECK3-NEXT:    [[D_ADDR:%.*]] = alloca i32, align 4
1894 // CHECK3-NEXT:    [[GD_ADDR:%.*]] = alloca ptr, align 4
1895 // CHECK3-NEXT:    [[SD_ADDR:%.*]] = alloca i32, align 4
1896 // CHECK3-NEXT:    [[GB1:%.*]] = alloca double, align 8
1897 // CHECK3-NEXT:    [[GC2:%.*]] = alloca double, align 8
1898 // CHECK3-NEXT:    [[GD3:%.*]] = alloca double, align 8
1899 // CHECK3-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
1900 // CHECK3-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
1901 // CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
1902 // CHECK3-NEXT:    store i32 [[B]], ptr [[B_ADDR]], align 4
1903 // CHECK3-NEXT:    store ptr [[GB]], ptr [[GB_ADDR]], align 4
1904 // CHECK3-NEXT:    store i32 [[SB]], ptr [[SB_ADDR]], align 4
1905 // CHECK3-NEXT:    store ptr [[GC]], ptr [[GC_ADDR]], align 4
1906 // CHECK3-NEXT:    store i32 [[C]], ptr [[C_ADDR]], align 4
1907 // CHECK3-NEXT:    store i32 [[SC]], ptr [[SC_ADDR]], align 4
1908 // CHECK3-NEXT:    store i32 [[D]], ptr [[D_ADDR]], align 4
1909 // CHECK3-NEXT:    store ptr [[GD]], ptr [[GD_ADDR]], align 4
1910 // CHECK3-NEXT:    store i32 [[SD]], ptr [[SD_ADDR]], align 4
1911 // CHECK3-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[GB_ADDR]], align 4
1912 // CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[GC_ADDR]], align 4
1913 // CHECK3-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[GD_ADDR]], align 4
1914 // CHECK3-NEXT:    [[TMP4:%.*]] = load double, ptr [[TMP1]], align 8
1915 // CHECK3-NEXT:    store double [[TMP4]], ptr [[GB1]], align 8
1916 // CHECK3-NEXT:    [[TMP5:%.*]] = load double, ptr [[TMP2]], align 8
1917 // CHECK3-NEXT:    store double [[TMP5]], ptr [[GC2]], align 8
1918 // CHECK3-NEXT:    [[TMP6:%.*]] = load double, ptr [[TMP3]], align 8
1919 // CHECK3-NEXT:    store double [[TMP6]], ptr [[GD3]], align 8
1920 // CHECK3-NEXT:    [[TMP7:%.*]] = load i16, ptr [[B_ADDR]], align 2
1921 // CHECK3-NEXT:    [[CONV:%.*]] = sext i16 [[TMP7]] to i32
1922 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV]], 1
1923 // CHECK3-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD]] to i16
1924 // CHECK3-NEXT:    store i16 [[CONV4]], ptr [[B_ADDR]], align 2
1925 // CHECK3-NEXT:    [[TMP8:%.*]] = load double, ptr [[GB1]], align 8
1926 // CHECK3-NEXT:    [[ADD5:%.*]] = fadd double [[TMP8]], 1.000000e+00
1927 // CHECK3-NEXT:    store double [[ADD5]], ptr [[GB1]], align 8
1928 // CHECK3-NEXT:    [[TMP9:%.*]] = load float, ptr [[SB_ADDR]], align 4
1929 // CHECK3-NEXT:    [[CONV6:%.*]] = fpext float [[TMP9]] to double
1930 // CHECK3-NEXT:    [[ADD7:%.*]] = fadd double [[CONV6]], 1.000000e+00
1931 // CHECK3-NEXT:    [[CONV8:%.*]] = fptrunc double [[ADD7]] to float
1932 // CHECK3-NEXT:    store float [[CONV8]], ptr [[SB_ADDR]], align 4
1933 // CHECK3-NEXT:    [[TMP10:%.*]] = load double, ptr [[GC2]], align 8
1934 // CHECK3-NEXT:    [[CMP:%.*]] = fcmp ogt double [[TMP10]], 0.000000e+00
1935 // CHECK3-NEXT:    br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_IF_ELSE:%.*]]
1936 // CHECK3:       land.lhs.true:
1937 // CHECK3-NEXT:    [[TMP11:%.*]] = load i16, ptr [[C_ADDR]], align 2
1938 // CHECK3-NEXT:    [[CONV9:%.*]] = sext i16 [[TMP11]] to i32
1939 // CHECK3-NEXT:    [[CMP10:%.*]] = icmp sgt i32 [[CONV9]], 0
1940 // CHECK3-NEXT:    br i1 [[CMP10]], label [[LAND_LHS_TRUE11:%.*]], label [[OMP_IF_ELSE]]
1941 // CHECK3:       land.lhs.true11:
1942 // CHECK3-NEXT:    [[TMP12:%.*]] = load float, ptr [[SC_ADDR]], align 4
1943 // CHECK3-NEXT:    [[CONV12:%.*]] = fpext float [[TMP12]] to double
1944 // CHECK3-NEXT:    [[CMP13:%.*]] = fcmp ogt double [[CONV12]], 0.000000e+00
1945 // CHECK3-NEXT:    br i1 [[CMP13]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE]]
1946 // CHECK3:       omp_if.then:
1947 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4tbarIsEiT_S0_S0_S0__l145.omp_outlined, ptr [[D_ADDR]], ptr [[GD3]], ptr [[SD_ADDR]])
1948 // CHECK3-NEXT:    br label [[OMP_IF_END:%.*]]
1949 // CHECK3:       omp_if.else:
1950 // CHECK3-NEXT:    call void @__kmpc_serialized_parallel(ptr @[[GLOB1]], i32 [[TMP0]])
1951 // CHECK3-NEXT:    store i32 [[TMP0]], ptr [[DOTTHREADID_TEMP_]], align 4
1952 // CHECK3-NEXT:    store i32 0, ptr [[DOTBOUND_ZERO_ADDR]], align 4
1953 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4tbarIsEiT_S0_S0_S0__l145.omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTBOUND_ZERO_ADDR]], ptr [[D_ADDR]], ptr [[GD3]], ptr [[SD_ADDR]]) #[[ATTR2]]
1954 // CHECK3-NEXT:    call void @__kmpc_end_serialized_parallel(ptr @[[GLOB1]], i32 [[TMP0]])
1955 // CHECK3-NEXT:    br label [[OMP_IF_END]]
1956 // CHECK3:       omp_if.end:
1957 // CHECK3-NEXT:    ret void
1958 //
1959 //
1960 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4tbarIsEiT_S0_S0_S0__l145.omp_outlined
1961 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[D:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[GD:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[SD:%.*]]) #[[ATTR1]] {
1962 // CHECK3-NEXT:  entry:
1963 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
1964 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
1965 // CHECK3-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4
1966 // CHECK3-NEXT:    [[GD_ADDR:%.*]] = alloca ptr, align 4
1967 // CHECK3-NEXT:    [[SD_ADDR:%.*]] = alloca ptr, align 4
1968 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
1969 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
1970 // CHECK3-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4
1971 // CHECK3-NEXT:    store ptr [[GD]], ptr [[GD_ADDR]], align 4
1972 // CHECK3-NEXT:    store ptr [[SD]], ptr [[SD_ADDR]], align 4
1973 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[D_ADDR]], align 4
1974 // CHECK3-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[GD_ADDR]], align 4
1975 // CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[SD_ADDR]], align 4
1976 // CHECK3-NEXT:    [[TMP3:%.*]] = load i16, ptr [[TMP0]], align 2
1977 // CHECK3-NEXT:    [[CONV:%.*]] = sext i16 [[TMP3]] to i32
1978 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV]], 1
1979 // CHECK3-NEXT:    [[CONV1:%.*]] = trunc i32 [[ADD]] to i16
1980 // CHECK3-NEXT:    store i16 [[CONV1]], ptr [[TMP0]], align 2
1981 // CHECK3-NEXT:    [[TMP4:%.*]] = load double, ptr [[TMP1]], align 8
1982 // CHECK3-NEXT:    [[ADD2:%.*]] = fadd double [[TMP4]], 1.000000e+00
1983 // CHECK3-NEXT:    store double [[ADD2]], ptr [[TMP1]], align 8
1984 // CHECK3-NEXT:    [[TMP5:%.*]] = load float, ptr [[TMP2]], align 4
1985 // CHECK3-NEXT:    [[CONV3:%.*]] = fpext float [[TMP5]] to double
1986 // CHECK3-NEXT:    [[ADD4:%.*]] = fadd double [[CONV3]], 1.000000e+00
1987 // CHECK3-NEXT:    [[CONV5:%.*]] = fptrunc double [[ADD4]] to float
1988 // CHECK3-NEXT:    store float [[CONV5]], ptr [[TMP2]], align 4
1989 // CHECK3-NEXT:    ret void
1990 //
1991 //
1992 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
1993 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] {
1994 // CHECK3-NEXT:  entry:
1995 // CHECK3-NEXT:    call void @__tgt_register_requires(i64 1)
1996 // CHECK3-NEXT:    ret void
1997 //