clang/test/OpenMP/target_parallel_codegen.cpp

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
   2 // Test host codegen.
   3 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1
   4 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
   5 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1
   6 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3
   7 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
   8 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3
   9
  10 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  11 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
  12 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  13 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  14 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
  15 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  16
  17 // Test target codegen - host bc file has to be created first.
  18 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
  19 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK9
  20 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
  21 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9
  22 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
  23 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK11
  24 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
  25 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11
  26
  27 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
  28 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  29 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
  30 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  31 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
  32 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  33 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
  34 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  35
  36 // Test host codegen.
  37 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1
  38 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
  39 // RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1
  40 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3
  41 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
  42 // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3
  43
  44 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  45 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
  46 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  47 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  48 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
  49 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  50
  51 // Test target codegen - host bc file has to be created first.
  52 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
  53 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK9
  54 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
  55 // RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9
  56 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
  57 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK11
  58 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
  59 // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11
  60
  61 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
  62 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  63 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
  64 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  65 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
  66 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  67 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
  68 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  69
  70 // expected-no-diagnostics
  71 #ifndef HEADER
  72 #define HEADER
  73
  74
  75
  76
  77 // We have 8 target regions, but only 6 that actually will generate offloading
  78 // code and have mapped arguments, and only 4 have all-constant map sizes.
  79
  80
  81
  82 // Check target registration is registered as a Ctor.
  83
  84
  85 template<typename tx, typename ty>
  86 struct TT{
  87   tx X;
  88   ty Y;
  89 };
  90
  91 int foo(int n) {
  92   int a = 0;
  93   short aa = 0;
  94   float b[10];
  95   float bn[n];
  96   double c[5][10];
  97   double cn[5][n];
  98   TT<long long, char> d;
  99
 100   #pragma omp target parallel nowait
 101   {
 102   }
 103
 104   #pragma omp target parallel if(target: 0)
 105   {
 106     a += 1;
 107   }
 108
 109
 110   #pragma omp target parallel if(target: 1)
 111   {
 112     aa += 1;
 113 #pragma omp cancel parallel
 114   }
 115
 116
 117
 118
 119   #pragma omp target parallel if(target: n>10)
 120   {
 121     a += 1;
 122     aa += 1;
 123   }
 124
 125   // We capture 3 VLA sizes in this target region
 126
 127
 128
 129
 130
 131   // The names below are not necessarily consistent with the names used for the
 132   // addresses above as some are repeated.
 133
 134
 135
 136
 137
 138
 139
 140
 141
 142
 143
 144   #pragma omp target parallel if(target: n>20)
 145   {
 146     a += 1;
 147     b[2] += 1.0;
 148     bn[3] += 1.0;
 149     c[1][2] += 1.0;
 150     cn[1][3] += 1.0;
 151     d.X += 1;
 152     d.Y += 1;
 153   }
 154
 155   return a;
 156 }
 157
 158 // Check that the offloading functions are emitted and that the arguments are
 159 // correct and loaded correctly for the target regions in foo().
 160
 161
 162
 163 // Create stack storage and store argument in there.
 164
 165 // Create stack storage and store argument in there.
 166
 167 // Create stack storage and store argument in there.
 168
 169 // Create local storage for each capture.
 170
 171
 172
 173 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.
 174
 175 template<typename tx>
 176 tx ftemplate(int n) {
 177   tx a = 0;
 178   short aa = 0;
 179   tx b[10];
 180
 181   #pragma omp target parallel if(target: n>40)
 182   {
 183     a += 1;
 184     aa += 1;
 185     b[2] += 1;
 186   }
 187
 188   return a;
 189 }
 190
 191 static
 192 int fstatic(int n) {
 193   int a = 0;
 194   short aa = 0;
 195   char aaa = 0;
 196   int b[10];
 197
 198   #pragma omp target parallel if(target: n>50)
 199   {
 200     a += 1;
 201     aa += 1;
 202     aaa += 1;
 203     b[2] += 1;
 204   }
 205
 206   return a;
 207 }
 208
 209 struct S1 {
 210   double a;
 211
 212   int r1(int n){
 213     int b = n+1;
 214     short int c[2][n];
 215
 216     #pragma omp target parallel if(target: n>60)
 217     {
 218       this->a = (double)b + 1.5;
 219       c[1][1] = ++a;
 220     }
 221
 222     return c[1][1] + (int)b;
 223   }
 224 };
 225
 226 int bar(int n){
 227   int a = 0;
 228
 229   a += foo(n);
 230
 231   S1 S;
 232   a += S.r1(n);
 233
 234   a += fstatic(n);
 235
 236   a += ftemplate<int>(n);
 237
 238   return a;
 239 }
 240
 241
 242
 243 // We capture 2 VLA sizes in this target region
 244
 245
 246 // The names below are not necessarily consistent with the names used for the
 247 // addresses above as some are repeated.
 248
 249
 250
 251
 252
 253
 254
 255
 256
 257
 258
 259
 260
 261
 262
 263
 264
 265
 266
 267 // Check that the offloading functions are emitted and that the arguments are
 268 // correct and loaded correctly for the target regions of the callees of bar().
 269
 270 // Create local storage for each capture.
 271 // Store captures in the context.
 272
 273
 274 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.
 275
 276
 277 // Create local storage for each capture.
 278 // Store captures in the context.
 279
 280
 281
 282
 283 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.
 284
 285 // Create local storage for each capture.
 286 // Store captures in the context.
 287
 288
 289
 290 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.
 291
 292
 293 #endif
 294 // CHECK1-LABEL: define {{[^@]+}}@_Z3fooi
 295 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
 296 // CHECK1-NEXT:  entry:
 297 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
 298 // CHECK1-NEXT:    [[A:%.*]] = alloca i32, align 4
 299 // CHECK1-NEXT:    [[AA:%.*]] = alloca i16, align 2
 300 // CHECK1-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
 301 // CHECK1-NEXT:    [[SAVED_STACK:%.*]] = alloca ptr, align 8
 302 // CHECK1-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
 303 // CHECK1-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
 304 // CHECK1-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
 305 // CHECK1-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
 306 // CHECK1-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1
 307 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
 308 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
 309 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8
 310 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8
 311 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8
 312 // CHECK1-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
 313 // CHECK1-NEXT:    [[A_CASTED2:%.*]] = alloca i64, align 8
 314 // CHECK1-NEXT:    [[AA_CASTED3:%.*]] = alloca i64, align 8
 315 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [2 x ptr], align 8
 316 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS5:%.*]] = alloca [2 x ptr], align 8
 317 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [2 x ptr], align 8
 318 // CHECK1-NEXT:    [[KERNEL_ARGS7:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
 319 // CHECK1-NEXT:    [[A_CASTED10:%.*]] = alloca i64, align 8
 320 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS13:%.*]] = alloca [9 x ptr], align 8
 321 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS14:%.*]] = alloca [9 x ptr], align 8
 322 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS15:%.*]] = alloca [9 x ptr], align 8
 323 // CHECK1-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 8
 324 // CHECK1-NEXT:    [[KERNEL_ARGS16:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
 325 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
 326 // CHECK1-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
 327 // CHECK1-NEXT:    store i32 0, ptr [[A]], align 4
 328 // CHECK1-NEXT:    store i16 0, ptr [[AA]], align 2
 329 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
 330 // CHECK1-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
 331 // CHECK1-NEXT:    [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()
 332 // CHECK1-NEXT:    store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8
 333 // CHECK1-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4
 334 // CHECK1-NEXT:    store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8
 335 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
 336 // CHECK1-NEXT:    [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
 337 // CHECK1-NEXT:    [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]]
 338 // CHECK1-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8
 339 // CHECK1-NEXT:    store i64 [[TMP5]], ptr [[__VLA_EXPR1]], align 8
 340 // CHECK1-NEXT:    [[TMP7:%.*]] = call ptr @__kmpc_omp_target_task_alloc(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i64 40, i64 1, ptr @.omp_task_entry., i64 -1)
 341 // CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP7]], i32 0, i32 0
 342 // CHECK1-NEXT:    [[TMP9:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP7]])
 343 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[A]], align 4
 344 // CHECK1-NEXT:    store i32 [[TMP10]], ptr [[A_CASTED]], align 4
 345 // CHECK1-NEXT:    [[TMP11:%.*]] = load i64, ptr [[A_CASTED]], align 8
 346 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104(i64 [[TMP11]]) #[[ATTR3:[0-9]+]]
 347 // CHECK1-NEXT:    [[TMP12:%.*]] = load i16, ptr [[AA]], align 2
 348 // CHECK1-NEXT:    store i16 [[TMP12]], ptr [[AA_CASTED]], align 2
 349 // CHECK1-NEXT:    [[TMP13:%.*]] = load i64, ptr [[AA_CASTED]], align 8
 350 // CHECK1-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
 351 // CHECK1-NEXT:    store i64 [[TMP13]], ptr [[TMP14]], align 8
 352 // CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
 353 // CHECK1-NEXT:    store i64 [[TMP13]], ptr [[TMP15]], align 8
 354 // CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
 355 // CHECK1-NEXT:    store ptr null, ptr [[TMP16]], align 8
 356 // CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
 357 // CHECK1-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
 358 // CHECK1-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
 359 // CHECK1-NEXT:    store i32 2, ptr [[TMP19]], align 4
 360 // CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
 361 // CHECK1-NEXT:    store i32 1, ptr [[TMP20]], align 4
 362 // CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
 363 // CHECK1-NEXT:    store ptr [[TMP17]], ptr [[TMP21]], align 8
 364 // CHECK1-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
 365 // CHECK1-NEXT:    store ptr [[TMP18]], ptr [[TMP22]], align 8
 366 // CHECK1-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
 367 // CHECK1-NEXT:    store ptr @.offload_sizes, ptr [[TMP23]], align 8
 368 // CHECK1-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
 369 // CHECK1-NEXT:    store ptr @.offload_maptypes, ptr [[TMP24]], align 8
 370 // CHECK1-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
 371 // CHECK1-NEXT:    store ptr null, ptr [[TMP25]], align 8
 372 // CHECK1-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
 373 // CHECK1-NEXT:    store ptr null, ptr [[TMP26]], align 8
 374 // CHECK1-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
 375 // CHECK1-NEXT:    store i64 0, ptr [[TMP27]], align 8
 376 // CHECK1-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
 377 // CHECK1-NEXT:    store i64 0, ptr [[TMP28]], align 8
 378 // CHECK1-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
 379 // CHECK1-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP29]], align 4
 380 // CHECK1-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
 381 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP30]], align 4
 382 // CHECK1-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
 383 // CHECK1-NEXT:    store i32 0, ptr [[TMP31]], align 4
 384 // CHECK1-NEXT:    [[TMP32:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.region_id, ptr [[KERNEL_ARGS]])
 385 // CHECK1-NEXT:    [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0
 386 // CHECK1-NEXT:    br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
 387 // CHECK1:       omp_offload.failed:
 388 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i64 [[TMP13]]) #[[ATTR3]]
 389 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
 390 // CHECK1:       omp_offload.cont:
 391 // CHECK1-NEXT:    [[TMP34:%.*]] = load i32, ptr [[A]], align 4
 392 // CHECK1-NEXT:    store i32 [[TMP34]], ptr [[A_CASTED2]], align 4
 393 // CHECK1-NEXT:    [[TMP35:%.*]] = load i64, ptr [[A_CASTED2]], align 8
 394 // CHECK1-NEXT:    [[TMP36:%.*]] = load i16, ptr [[AA]], align 2
 395 // CHECK1-NEXT:    store i16 [[TMP36]], ptr [[AA_CASTED3]], align 2
 396 // CHECK1-NEXT:    [[TMP37:%.*]] = load i64, ptr [[AA_CASTED3]], align 8
 397 // CHECK1-NEXT:    [[TMP38:%.*]] = load i32, ptr [[N_ADDR]], align 4
 398 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP38]], 10
 399 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
 400 // CHECK1:       omp_if.then:
 401 // CHECK1-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0
 402 // CHECK1-NEXT:    store i64 [[TMP35]], ptr [[TMP39]], align 8
 403 // CHECK1-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS5]], i32 0, i32 0
 404 // CHECK1-NEXT:    store i64 [[TMP35]], ptr [[TMP40]], align 8
 405 // CHECK1-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0
 406 // CHECK1-NEXT:    store ptr null, ptr [[TMP41]], align 8
 407 // CHECK1-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1
 408 // CHECK1-NEXT:    store i64 [[TMP37]], ptr [[TMP42]], align 8
 409 // CHECK1-NEXT:    [[TMP43:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS5]], i32 0, i32 1
 410 // CHECK1-NEXT:    store i64 [[TMP37]], ptr [[TMP43]], align 8
 411 // CHECK1-NEXT:    [[TMP44:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 1
 412 // CHECK1-NEXT:    store ptr null, ptr [[TMP44]], align 8
 413 // CHECK1-NEXT:    [[TMP45:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0
 414 // CHECK1-NEXT:    [[TMP46:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS5]], i32 0, i32 0
 415 // CHECK1-NEXT:    [[TMP47:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS7]], i32 0, i32 0
 416 // CHECK1-NEXT:    store i32 2, ptr [[TMP47]], align 4
 417 // CHECK1-NEXT:    [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS7]], i32 0, i32 1
 418 // CHECK1-NEXT:    store i32 2, ptr [[TMP48]], align 4
 419 // CHECK1-NEXT:    [[TMP49:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS7]], i32 0, i32 2
 420 // CHECK1-NEXT:    store ptr [[TMP45]], ptr [[TMP49]], align 8
 421 // CHECK1-NEXT:    [[TMP50:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS7]], i32 0, i32 3
 422 // CHECK1-NEXT:    store ptr [[TMP46]], ptr [[TMP50]], align 8
 423 // CHECK1-NEXT:    [[TMP51:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS7]], i32 0, i32 4
 424 // CHECK1-NEXT:    store ptr @.offload_sizes.1, ptr [[TMP51]], align 8
 425 // CHECK1-NEXT:    [[TMP52:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS7]], i32 0, i32 5
 426 // CHECK1-NEXT:    store ptr @.offload_maptypes.2, ptr [[TMP52]], align 8
 427 // CHECK1-NEXT:    [[TMP53:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS7]], i32 0, i32 6
 428 // CHECK1-NEXT:    store ptr null, ptr [[TMP53]], align 8
 429 // CHECK1-NEXT:    [[TMP54:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS7]], i32 0, i32 7
 430 // CHECK1-NEXT:    store ptr null, ptr [[TMP54]], align 8
 431 // CHECK1-NEXT:    [[TMP55:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS7]], i32 0, i32 8
 432 // CHECK1-NEXT:    store i64 0, ptr [[TMP55]], align 8
 433 // CHECK1-NEXT:    [[TMP56:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS7]], i32 0, i32 9
 434 // CHECK1-NEXT:    store i64 0, ptr [[TMP56]], align 8
 435 // CHECK1-NEXT:    [[TMP57:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS7]], i32 0, i32 10
 436 // CHECK1-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP57]], align 4
 437 // CHECK1-NEXT:    [[TMP58:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS7]], i32 0, i32 11
 438 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP58]], align 4
 439 // CHECK1-NEXT:    [[TMP59:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS7]], i32 0, i32 12
 440 // CHECK1-NEXT:    store i32 0, ptr [[TMP59]], align 4
 441 // CHECK1-NEXT:    [[TMP60:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.region_id, ptr [[KERNEL_ARGS7]])
 442 // CHECK1-NEXT:    [[TMP61:%.*]] = icmp ne i32 [[TMP60]], 0
 443 // CHECK1-NEXT:    br i1 [[TMP61]], label [[OMP_OFFLOAD_FAILED8:%.*]], label [[OMP_OFFLOAD_CONT9:%.*]]
 444 // CHECK1:       omp_offload.failed8:
 445 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i64 [[TMP35]], i64 [[TMP37]]) #[[ATTR3]]
 446 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT9]]
 447 // CHECK1:       omp_offload.cont9:
 448 // CHECK1-NEXT:    br label [[OMP_IF_END:%.*]]
 449 // CHECK1:       omp_if.else:
 450 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i64 [[TMP35]], i64 [[TMP37]]) #[[ATTR3]]
 451 // CHECK1-NEXT:    br label [[OMP_IF_END]]
 452 // CHECK1:       omp_if.end:
 453 // CHECK1-NEXT:    [[TMP62:%.*]] = load i32, ptr [[A]], align 4
 454 // CHECK1-NEXT:    store i32 [[TMP62]], ptr [[A_CASTED10]], align 4
 455 // CHECK1-NEXT:    [[TMP63:%.*]] = load i64, ptr [[A_CASTED10]], align 8
 456 // CHECK1-NEXT:    [[TMP64:%.*]] = load i32, ptr [[N_ADDR]], align 4
 457 // CHECK1-NEXT:    [[CMP11:%.*]] = icmp sgt i32 [[TMP64]], 20
 458 // CHECK1-NEXT:    br i1 [[CMP11]], label [[OMP_IF_THEN12:%.*]], label [[OMP_IF_ELSE19:%.*]]
 459 // CHECK1:       omp_if.then12:
 460 // CHECK1-NEXT:    [[TMP65:%.*]] = mul nuw i64 [[TMP2]], 4
 461 // CHECK1-NEXT:    [[TMP66:%.*]] = mul nuw i64 5, [[TMP5]]
 462 // CHECK1-NEXT:    [[TMP67:%.*]] = mul nuw i64 [[TMP66]], 8
 463 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes.3, i64 72, i1 false)
 464 // CHECK1-NEXT:    [[TMP68:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0
 465 // CHECK1-NEXT:    store i64 [[TMP63]], ptr [[TMP68]], align 8
 466 // CHECK1-NEXT:    [[TMP69:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS14]], i32 0, i32 0
 467 // CHECK1-NEXT:    store i64 [[TMP63]], ptr [[TMP69]], align 8
 468 // CHECK1-NEXT:    [[TMP70:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS15]], i64 0, i64 0
 469 // CHECK1-NEXT:    store ptr null, ptr [[TMP70]], align 8
 470 // CHECK1-NEXT:    [[TMP71:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 1
 471 // CHECK1-NEXT:    store ptr [[B]], ptr [[TMP71]], align 8
 472 // CHECK1-NEXT:    [[TMP72:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS14]], i32 0, i32 1
 473 // CHECK1-NEXT:    store ptr [[B]], ptr [[TMP72]], align 8
 474 // CHECK1-NEXT:    [[TMP73:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS15]], i64 0, i64 1
 475 // CHECK1-NEXT:    store ptr null, ptr [[TMP73]], align 8
 476 // CHECK1-NEXT:    [[TMP74:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 2
 477 // CHECK1-NEXT:    store i64 [[TMP2]], ptr [[TMP74]], align 8
 478 // CHECK1-NEXT:    [[TMP75:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS14]], i32 0, i32 2
 479 // CHECK1-NEXT:    store i64 [[TMP2]], ptr [[TMP75]], align 8
 480 // CHECK1-NEXT:    [[TMP76:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS15]], i64 0, i64 2
 481 // CHECK1-NEXT:    store ptr null, ptr [[TMP76]], align 8
 482 // CHECK1-NEXT:    [[TMP77:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 3
 483 // CHECK1-NEXT:    store ptr [[VLA]], ptr [[TMP77]], align 8
 484 // CHECK1-NEXT:    [[TMP78:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS14]], i32 0, i32 3
 485 // CHECK1-NEXT:    store ptr [[VLA]], ptr [[TMP78]], align 8
 486 // CHECK1-NEXT:    [[TMP79:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 3
 487 // CHECK1-NEXT:    store i64 [[TMP65]], ptr [[TMP79]], align 8
 488 // CHECK1-NEXT:    [[TMP80:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS15]], i64 0, i64 3
 489 // CHECK1-NEXT:    store ptr null, ptr [[TMP80]], align 8
 490 // CHECK1-NEXT:    [[TMP81:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 4
 491 // CHECK1-NEXT:    store ptr [[C]], ptr [[TMP81]], align 8
 492 // CHECK1-NEXT:    [[TMP82:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS14]], i32 0, i32 4
 493 // CHECK1-NEXT:    store ptr [[C]], ptr [[TMP82]], align 8
 494 // CHECK1-NEXT:    [[TMP83:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS15]], i64 0, i64 4
 495 // CHECK1-NEXT:    store ptr null, ptr [[TMP83]], align 8
 496 // CHECK1-NEXT:    [[TMP84:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 5
 497 // CHECK1-NEXT:    store i64 5, ptr [[TMP84]], align 8
 498 // CHECK1-NEXT:    [[TMP85:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS14]], i32 0, i32 5
 499 // CHECK1-NEXT:    store i64 5, ptr [[TMP85]], align 8
 500 // CHECK1-NEXT:    [[TMP86:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS15]], i64 0, i64 5
 501 // CHECK1-NEXT:    store ptr null, ptr [[TMP86]], align 8
 502 // CHECK1-NEXT:    [[TMP87:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 6
 503 // CHECK1-NEXT:    store i64 [[TMP5]], ptr [[TMP87]], align 8
 504 // CHECK1-NEXT:    [[TMP88:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS14]], i32 0, i32 6
 505 // CHECK1-NEXT:    store i64 [[TMP5]], ptr [[TMP88]], align 8
 506 // CHECK1-NEXT:    [[TMP89:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS15]], i64 0, i64 6
 507 // CHECK1-NEXT:    store ptr null, ptr [[TMP89]], align 8
 508 // CHECK1-NEXT:    [[TMP90:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 7
 509 // CHECK1-NEXT:    store ptr [[VLA1]], ptr [[TMP90]], align 8
 510 // CHECK1-NEXT:    [[TMP91:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS14]], i32 0, i32 7
 511 // CHECK1-NEXT:    store ptr [[VLA1]], ptr [[TMP91]], align 8
 512 // CHECK1-NEXT:    [[TMP92:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 7
 513 // CHECK1-NEXT:    store i64 [[TMP67]], ptr [[TMP92]], align 8
 514 // CHECK1-NEXT:    [[TMP93:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS15]], i64 0, i64 7
 515 // CHECK1-NEXT:    store ptr null, ptr [[TMP93]], align 8
 516 // CHECK1-NEXT:    [[TMP94:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 8
 517 // CHECK1-NEXT:    store ptr [[D]], ptr [[TMP94]], align 8
 518 // CHECK1-NEXT:    [[TMP95:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS14]], i32 0, i32 8
 519 // CHECK1-NEXT:    store ptr [[D]], ptr [[TMP95]], align 8
 520 // CHECK1-NEXT:    [[TMP96:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS15]], i64 0, i64 8
 521 // CHECK1-NEXT:    store ptr null, ptr [[TMP96]], align 8
 522 // CHECK1-NEXT:    [[TMP97:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0
 523 // CHECK1-NEXT:    [[TMP98:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS14]], i32 0, i32 0
 524 // CHECK1-NEXT:    [[TMP99:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0
 525 // CHECK1-NEXT:    [[TMP100:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 0
 526 // CHECK1-NEXT:    store i32 2, ptr [[TMP100]], align 4
 527 // CHECK1-NEXT:    [[TMP101:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 1
 528 // CHECK1-NEXT:    store i32 9, ptr [[TMP101]], align 4
 529 // CHECK1-NEXT:    [[TMP102:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 2
 530 // CHECK1-NEXT:    store ptr [[TMP97]], ptr [[TMP102]], align 8
 531 // CHECK1-NEXT:    [[TMP103:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 3
 532 // CHECK1-NEXT:    store ptr [[TMP98]], ptr [[TMP103]], align 8
 533 // CHECK1-NEXT:    [[TMP104:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 4
 534 // CHECK1-NEXT:    store ptr [[TMP99]], ptr [[TMP104]], align 8
 535 // CHECK1-NEXT:    [[TMP105:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 5
 536 // CHECK1-NEXT:    store ptr @.offload_maptypes.4, ptr [[TMP105]], align 8
 537 // CHECK1-NEXT:    [[TMP106:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 6
 538 // CHECK1-NEXT:    store ptr null, ptr [[TMP106]], align 8
 539 // CHECK1-NEXT:    [[TMP107:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 7
 540 // CHECK1-NEXT:    store ptr null, ptr [[TMP107]], align 8
 541 // CHECK1-NEXT:    [[TMP108:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 8
 542 // CHECK1-NEXT:    store i64 0, ptr [[TMP108]], align 8
 543 // CHECK1-NEXT:    [[TMP109:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 9
 544 // CHECK1-NEXT:    store i64 0, ptr [[TMP109]], align 8
 545 // CHECK1-NEXT:    [[TMP110:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 10
 546 // CHECK1-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP110]], align 4
 547 // CHECK1-NEXT:    [[TMP111:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 11
 548 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP111]], align 4
 549 // CHECK1-NEXT:    [[TMP112:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 12
 550 // CHECK1-NEXT:    store i32 0, ptr [[TMP112]], align 4
 551 // CHECK1-NEXT:    [[TMP113:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.region_id, ptr [[KERNEL_ARGS16]])
 552 // CHECK1-NEXT:    [[TMP114:%.*]] = icmp ne i32 [[TMP113]], 0
 553 // CHECK1-NEXT:    br i1 [[TMP114]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]]
 554 // CHECK1:       omp_offload.failed17:
 555 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i64 [[TMP63]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]]) #[[ATTR3]]
 556 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT18]]
 557 // CHECK1:       omp_offload.cont18:
 558 // CHECK1-NEXT:    br label [[OMP_IF_END20:%.*]]
 559 // CHECK1:       omp_if.else19:
 560 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i64 [[TMP63]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]]) #[[ATTR3]]
 561 // CHECK1-NEXT:    br label [[OMP_IF_END20]]
 562 // CHECK1:       omp_if.end20:
 563 // CHECK1-NEXT:    [[TMP115:%.*]] = load i32, ptr [[A]], align 4
 564 // CHECK1-NEXT:    [[TMP116:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
 565 // CHECK1-NEXT:    call void @llvm.stackrestore.p0(ptr [[TMP116]])
 566 // CHECK1-NEXT:    ret i32 [[TMP115]]
 567 //
 568 //
 569 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100
 570 // CHECK1-SAME: () #[[ATTR2:[0-9]+]] {
 571 // CHECK1-NEXT:  entry:
 572 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.omp_outlined)
 573 // CHECK1-NEXT:    ret void
 574 //
 575 //
 576 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.omp_outlined
 577 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] {
 578 // CHECK1-NEXT:  entry:
 579 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 580 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 581 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 582 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 583 // CHECK1-NEXT:    ret void
 584 //
 585 //
 586 // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry.
 587 // CHECK1-SAME: (i32 noundef signext [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] {
 588 // CHECK1-NEXT:  entry:
 589 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
 590 // CHECK1-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8
 591 // CHECK1-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8
 592 // CHECK1-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8
 593 // CHECK1-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8
 594 // CHECK1-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8
 595 // CHECK1-NEXT:    [[KERNEL_ARGS_I:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
 596 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 4
 597 // CHECK1-NEXT:    [[DOTADDR1:%.*]] = alloca ptr, align 8
 598 // CHECK1-NEXT:    store i32 [[TMP0]], ptr [[DOTADDR]], align 4
 599 // CHECK1-NEXT:    store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
 600 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4
 601 // CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8
 602 // CHECK1-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0
 603 // CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2
 604 // CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0
 605 // CHECK1-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8
 606 // CHECK1-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
 607 // CHECK1-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])
 608 // CHECK1-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])
 609 // CHECK1-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])
 610 // CHECK1-NEXT:    store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !21
 611 // CHECK1-NEXT:    store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias !21
 612 // CHECK1-NEXT:    store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias !21
 613 // CHECK1-NEXT:    store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !21
 614 // CHECK1-NEXT:    store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias !21
 615 // CHECK1-NEXT:    store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias !21
 616 // CHECK1-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias !21
 617 // CHECK1-NEXT:    store i32 2, ptr [[KERNEL_ARGS_I]], align 4, !noalias !21
 618 // CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 1
 619 // CHECK1-NEXT:    store i32 0, ptr [[TMP9]], align 4, !noalias !21
 620 // CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 2
 621 // CHECK1-NEXT:    store ptr null, ptr [[TMP10]], align 8, !noalias !21
 622 // CHECK1-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 3
 623 // CHECK1-NEXT:    store ptr null, ptr [[TMP11]], align 8, !noalias !21
 624 // CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 4
 625 // CHECK1-NEXT:    store ptr null, ptr [[TMP12]], align 8, !noalias !21
 626 // CHECK1-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 5
 627 // CHECK1-NEXT:    store ptr null, ptr [[TMP13]], align 8, !noalias !21
 628 // CHECK1-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 6
 629 // CHECK1-NEXT:    store ptr null, ptr [[TMP14]], align 8, !noalias !21
 630 // CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 7
 631 // CHECK1-NEXT:    store ptr null, ptr [[TMP15]], align 8, !noalias !21
 632 // CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 8
 633 // CHECK1-NEXT:    store i64 0, ptr [[TMP16]], align 8, !noalias !21
 634 // CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 9
 635 // CHECK1-NEXT:    store i64 1, ptr [[TMP17]], align 8, !noalias !21
 636 // CHECK1-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 10
 637 // CHECK1-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP18]], align 4, !noalias !21
 638 // CHECK1-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 11
 639 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP19]], align 4, !noalias !21
 640 // CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 12
 641 // CHECK1-NEXT:    store i32 0, ptr [[TMP20]], align 4, !noalias !21
 642 // CHECK1-NEXT:    [[TMP21:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.region_id, ptr [[KERNEL_ARGS_I]])
 643 // CHECK1-NEXT:    [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
 644 // CHECK1-NEXT:    br i1 [[TMP22]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]]
 645 // CHECK1:       omp_offload.failed.i:
 646 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100() #[[ATTR3]]
 647 // CHECK1-NEXT:    br label [[DOTOMP_OUTLINED__EXIT]]
 648 // CHECK1:       .omp_outlined..exit:
 649 // CHECK1-NEXT:    ret i32 0
 650 //
 651 //
 652 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104
 653 // CHECK1-SAME: (i64 noundef [[A:%.*]]) #[[ATTR2]] {
 654 // CHECK1-NEXT:  entry:
 655 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
 656 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
 657 // CHECK1-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
 658 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
 659 // CHECK1-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 4
 660 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8
 661 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104.omp_outlined, i64 [[TMP1]])
 662 // CHECK1-NEXT:    ret void
 663 //
 664 //
 665 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104.omp_outlined
 666 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] {
 667 // CHECK1-NEXT:  entry:
 668 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 669 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 670 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
 671 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 672 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 673 // CHECK1-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
 674 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
 675 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
 676 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 4
 677 // CHECK1-NEXT:    ret void
 678 //
 679 //
 680 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110
 681 // CHECK1-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR2]] {
 682 // CHECK1-NEXT:  entry:
 683 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
 684 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
 685 // CHECK1-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
 686 // CHECK1-NEXT:    [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2
 687 // CHECK1-NEXT:    store i16 [[TMP0]], ptr [[AA_CASTED]], align 2
 688 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[AA_CASTED]], align 8
 689 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.omp_outlined, i64 [[TMP1]])
 690 // CHECK1-NEXT:    ret void
 691 //
 692 //
 693 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.omp_outlined
 694 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {
 695 // CHECK1-NEXT:  entry:
 696 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 697 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 698 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
 699 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 700 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 701 // CHECK1-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
 702 // CHECK1-NEXT:    [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2
 703 // CHECK1-NEXT:    [[CONV:%.*]] = sext i16 [[TMP0]] to i32
 704 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV]], 1
 705 // CHECK1-NEXT:    [[CONV1:%.*]] = trunc i32 [[ADD]] to i16
 706 // CHECK1-NEXT:    store i16 [[CONV1]], ptr [[AA_ADDR]], align 2
 707 // CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 708 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
 709 // CHECK1-NEXT:    [[TMP3:%.*]] = call i32 @__kmpc_cancel(ptr @[[GLOB1]], i32 [[TMP2]], i32 1)
 710 // CHECK1-NEXT:    [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
 711 // CHECK1-NEXT:    br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
 712 // CHECK1:       .cancel.exit:
 713 // CHECK1-NEXT:    [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(ptr @[[GLOB2:[0-9]+]], i32 [[TMP2]])
 714 // CHECK1-NEXT:    br label [[DOTCANCEL_CONTINUE]]
 715 // CHECK1:       .cancel.continue:
 716 // CHECK1-NEXT:    ret void
 717 //
 718 //
 719 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119
 720 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {
 721 // CHECK1-NEXT:  entry:
 722 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
 723 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
 724 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
 725 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
 726 // CHECK1-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
 727 // CHECK1-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
 728 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
 729 // CHECK1-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 4
 730 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8
 731 // CHECK1-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2
 732 // CHECK1-NEXT:    store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
 733 // CHECK1-NEXT:    [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8
 734 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.omp_outlined, i64 [[TMP1]], i64 [[TMP3]])
 735 // CHECK1-NEXT:    ret void
 736 //
 737 //
 738 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.omp_outlined
 739 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {
 740 // CHECK1-NEXT:  entry:
 741 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 742 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 743 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
 744 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
 745 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 746 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 747 // CHECK1-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
 748 // CHECK1-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
 749 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
 750 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
 751 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 4
 752 // CHECK1-NEXT:    [[TMP1:%.*]] = load i16, ptr [[AA_ADDR]], align 2
 753 // CHECK1-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
 754 // CHECK1-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
 755 // CHECK1-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
 756 // CHECK1-NEXT:    store i16 [[CONV2]], ptr [[AA_ADDR]], align 2
 757 // CHECK1-NEXT:    ret void
 758 //
 759 //
 760 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144
 761 // CHECK1-SAME: (i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] {
 762 // CHECK1-NEXT:  entry:
 763 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
 764 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
 765 // CHECK1-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
 766 // CHECK1-NEXT:    [[BN_ADDR:%.*]] = alloca ptr, align 8
 767 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
 768 // CHECK1-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
 769 // CHECK1-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
 770 // CHECK1-NEXT:    [[CN_ADDR:%.*]] = alloca ptr, align 8
 771 // CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
 772 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
 773 // CHECK1-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
 774 // CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
 775 // CHECK1-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
 776 // CHECK1-NEXT:    store ptr [[BN]], ptr [[BN_ADDR]], align 8
 777 // CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
 778 // CHECK1-NEXT:    store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
 779 // CHECK1-NEXT:    store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8
 780 // CHECK1-NEXT:    store ptr [[CN]], ptr [[CN_ADDR]], align 8
 781 // CHECK1-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
 782 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
 783 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
 784 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8
 785 // CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
 786 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
 787 // CHECK1-NEXT:    [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8
 788 // CHECK1-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8
 789 // CHECK1-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8
 790 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
 791 // CHECK1-NEXT:    store i32 [[TMP8]], ptr [[A_CASTED]], align 4
 792 // CHECK1-NEXT:    [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 8
 793 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.omp_outlined, i64 [[TMP9]], ptr [[TMP0]], i64 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]])
 794 // CHECK1-NEXT:    ret void
 795 //
 796 //
 797 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.omp_outlined
 798 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] {
 799 // CHECK1-NEXT:  entry:
 800 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 801 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 802 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
 803 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
 804 // CHECK1-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
 805 // CHECK1-NEXT:    [[BN_ADDR:%.*]] = alloca ptr, align 8
 806 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
 807 // CHECK1-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
 808 // CHECK1-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
 809 // CHECK1-NEXT:    [[CN_ADDR:%.*]] = alloca ptr, align 8
 810 // CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
 811 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 812 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 813 // CHECK1-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
 814 // CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
 815 // CHECK1-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
 816 // CHECK1-NEXT:    store ptr [[BN]], ptr [[BN_ADDR]], align 8
 817 // CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
 818 // CHECK1-NEXT:    store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
 819 // CHECK1-NEXT:    store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8
 820 // CHECK1-NEXT:    store ptr [[CN]], ptr [[CN_ADDR]], align 8
 821 // CHECK1-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
 822 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
 823 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
 824 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8
 825 // CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
 826 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
 827 // CHECK1-NEXT:    [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8
 828 // CHECK1-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8
 829 // CHECK1-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8
 830 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
 831 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
 832 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 4
 833 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 2
 834 // CHECK1-NEXT:    [[TMP9:%.*]] = load float, ptr [[ARRAYIDX]], align 4
 835 // CHECK1-NEXT:    [[CONV:%.*]] = fpext float [[TMP9]] to double
 836 // CHECK1-NEXT:    [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00
 837 // CHECK1-NEXT:    [[CONV6:%.*]] = fptrunc double [[ADD5]] to float
 838 // CHECK1-NEXT:    store float [[CONV6]], ptr [[ARRAYIDX]], align 4
 839 // CHECK1-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 3
 840 // CHECK1-NEXT:    [[TMP10:%.*]] = load float, ptr [[ARRAYIDX7]], align 4
 841 // CHECK1-NEXT:    [[CONV8:%.*]] = fpext float [[TMP10]] to double
 842 // CHECK1-NEXT:    [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00
 843 // CHECK1-NEXT:    [[CONV10:%.*]] = fptrunc double [[ADD9]] to float
 844 // CHECK1-NEXT:    store float [[CONV10]], ptr [[ARRAYIDX7]], align 4
 845 // CHECK1-NEXT:    [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 1
 846 // CHECK1-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX11]], i64 0, i64 2
 847 // CHECK1-NEXT:    [[TMP11:%.*]] = load double, ptr [[ARRAYIDX12]], align 8
 848 // CHECK1-NEXT:    [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00
 849 // CHECK1-NEXT:    store double [[ADD13]], ptr [[ARRAYIDX12]], align 8
 850 // CHECK1-NEXT:    [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]]
 851 // CHECK1-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i64 [[TMP12]]
 852 // CHECK1-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX14]], i64 3
 853 // CHECK1-NEXT:    [[TMP13:%.*]] = load double, ptr [[ARRAYIDX15]], align 8
 854 // CHECK1-NEXT:    [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00
 855 // CHECK1-NEXT:    store double [[ADD16]], ptr [[ARRAYIDX15]], align 8
 856 // CHECK1-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0
 857 // CHECK1-NEXT:    [[TMP14:%.*]] = load i64, ptr [[X]], align 8
 858 // CHECK1-NEXT:    [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1
 859 // CHECK1-NEXT:    store i64 [[ADD17]], ptr [[X]], align 8
 860 // CHECK1-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1
 861 // CHECK1-NEXT:    [[TMP15:%.*]] = load i8, ptr [[Y]], align 8
 862 // CHECK1-NEXT:    [[CONV18:%.*]] = sext i8 [[TMP15]] to i32
 863 // CHECK1-NEXT:    [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1
 864 // CHECK1-NEXT:    [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8
 865 // CHECK1-NEXT:    store i8 [[CONV20]], ptr [[Y]], align 8
 866 // CHECK1-NEXT:    ret void
 867 //
 868 //
 869 // CHECK1-LABEL: define {{[^@]+}}@_Z3bari
 870 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
 871 // CHECK1-NEXT:  entry:
 872 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
 873 // CHECK1-NEXT:    [[A:%.*]] = alloca i32, align 4
 874 // CHECK1-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
 875 // CHECK1-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
 876 // CHECK1-NEXT:    store i32 0, ptr [[A]], align 4
 877 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
 878 // CHECK1-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]])
 879 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A]], align 4
 880 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
 881 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[A]], align 4
 882 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
 883 // CHECK1-NEXT:    [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(ptr noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]])
 884 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A]], align 4
 885 // CHECK1-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
 886 // CHECK1-NEXT:    store i32 [[ADD2]], ptr [[A]], align 4
 887 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
 888 // CHECK1-NEXT:    [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]])
 889 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[A]], align 4
 890 // CHECK1-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
 891 // CHECK1-NEXT:    store i32 [[ADD4]], ptr [[A]], align 4
 892 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4
 893 // CHECK1-NEXT:    [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]])
 894 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[A]], align 4
 895 // CHECK1-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
 896 // CHECK1-NEXT:    store i32 [[ADD6]], ptr [[A]], align 4
 897 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A]], align 4
 898 // CHECK1-NEXT:    ret i32 [[TMP8]]
 899 //
 900 //
 901 // CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
 902 // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
 903 // CHECK1-NEXT:  entry:
 904 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 905 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
 906 // CHECK1-NEXT:    [[B:%.*]] = alloca i32, align 4
 907 // CHECK1-NEXT:    [[SAVED_STACK:%.*]] = alloca ptr, align 8
 908 // CHECK1-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
 909 // CHECK1-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
 910 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 8
 911 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 8
 912 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 8
 913 // CHECK1-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8
 914 // CHECK1-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
 915 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 916 // CHECK1-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
 917 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 918 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
 919 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
 920 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[B]], align 4
 921 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
 922 // CHECK1-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
 923 // CHECK1-NEXT:    [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()
 924 // CHECK1-NEXT:    store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8
 925 // CHECK1-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
 926 // CHECK1-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
 927 // CHECK1-NEXT:    store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8
 928 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[B]], align 4
 929 // CHECK1-NEXT:    store i32 [[TMP5]], ptr [[B_CASTED]], align 4
 930 // CHECK1-NEXT:    [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 8
 931 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 4
 932 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60
 933 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
 934 // CHECK1:       omp_if.then:
 935 // CHECK1-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0
 936 // CHECK1-NEXT:    [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]]
 937 // CHECK1-NEXT:    [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2
 938 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes.5, i64 40, i1 false)
 939 // CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
 940 // CHECK1-NEXT:    store ptr [[THIS1]], ptr [[TMP10]], align 8
 941 // CHECK1-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
 942 // CHECK1-NEXT:    store ptr [[A]], ptr [[TMP11]], align 8
 943 // CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
 944 // CHECK1-NEXT:    store ptr null, ptr [[TMP12]], align 8
 945 // CHECK1-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
 946 // CHECK1-NEXT:    store i64 [[TMP6]], ptr [[TMP13]], align 8
 947 // CHECK1-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
 948 // CHECK1-NEXT:    store i64 [[TMP6]], ptr [[TMP14]], align 8
 949 // CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
 950 // CHECK1-NEXT:    store ptr null, ptr [[TMP15]], align 8
 951 // CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
 952 // CHECK1-NEXT:    store i64 2, ptr [[TMP16]], align 8
 953 // CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
 954 // CHECK1-NEXT:    store i64 2, ptr [[TMP17]], align 8
 955 // CHECK1-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
 956 // CHECK1-NEXT:    store ptr null, ptr [[TMP18]], align 8
 957 // CHECK1-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
 958 // CHECK1-NEXT:    store i64 [[TMP2]], ptr [[TMP19]], align 8
 959 // CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
 960 // CHECK1-NEXT:    store i64 [[TMP2]], ptr [[TMP20]], align 8
 961 // CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
 962 // CHECK1-NEXT:    store ptr null, ptr [[TMP21]], align 8
 963 // CHECK1-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
 964 // CHECK1-NEXT:    store ptr [[VLA]], ptr [[TMP22]], align 8
 965 // CHECK1-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4
 966 // CHECK1-NEXT:    store ptr [[VLA]], ptr [[TMP23]], align 8
 967 // CHECK1-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 4
 968 // CHECK1-NEXT:    store i64 [[TMP9]], ptr [[TMP24]], align 8
 969 // CHECK1-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
 970 // CHECK1-NEXT:    store ptr null, ptr [[TMP25]], align 8
 971 // CHECK1-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
 972 // CHECK1-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
 973 // CHECK1-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0
 974 // CHECK1-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
 975 // CHECK1-NEXT:    store i32 2, ptr [[TMP29]], align 4
 976 // CHECK1-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
 977 // CHECK1-NEXT:    store i32 5, ptr [[TMP30]], align 4
 978 // CHECK1-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
 979 // CHECK1-NEXT:    store ptr [[TMP26]], ptr [[TMP31]], align 8
 980 // CHECK1-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
 981 // CHECK1-NEXT:    store ptr [[TMP27]], ptr [[TMP32]], align 8
 982 // CHECK1-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
 983 // CHECK1-NEXT:    store ptr [[TMP28]], ptr [[TMP33]], align 8
 984 // CHECK1-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
 985 // CHECK1-NEXT:    store ptr @.offload_maptypes.6, ptr [[TMP34]], align 8
 986 // CHECK1-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
 987 // CHECK1-NEXT:    store ptr null, ptr [[TMP35]], align 8
 988 // CHECK1-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
 989 // CHECK1-NEXT:    store ptr null, ptr [[TMP36]], align 8
 990 // CHECK1-NEXT:    [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
 991 // CHECK1-NEXT:    store i64 0, ptr [[TMP37]], align 8
 992 // CHECK1-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
 993 // CHECK1-NEXT:    store i64 0, ptr [[TMP38]], align 8
 994 // CHECK1-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
 995 // CHECK1-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP39]], align 4
 996 // CHECK1-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
 997 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP40]], align 4
 998 // CHECK1-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
 999 // CHECK1-NEXT:    store i32 0, ptr [[TMP41]], align 4
1000 // CHECK1-NEXT:    [[TMP42:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.region_id, ptr [[KERNEL_ARGS]])
1001 // CHECK1-NEXT:    [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0
1002 // CHECK1-NEXT:    br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1003 // CHECK1:       omp_offload.failed:
1004 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(ptr [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], ptr [[VLA]]) #[[ATTR3]]
1005 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
1006 // CHECK1:       omp_offload.cont:
1007 // CHECK1-NEXT:    br label [[OMP_IF_END:%.*]]
1008 // CHECK1:       omp_if.else:
1009 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(ptr [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], ptr [[VLA]]) #[[ATTR3]]
1010 // CHECK1-NEXT:    br label [[OMP_IF_END]]
1011 // CHECK1:       omp_if.end:
1012 // CHECK1-NEXT:    [[TMP44:%.*]] = mul nsw i64 1, [[TMP2]]
1013 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP44]]
1014 // CHECK1-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1
1015 // CHECK1-NEXT:    [[TMP45:%.*]] = load i16, ptr [[ARRAYIDX2]], align 2
1016 // CHECK1-NEXT:    [[CONV:%.*]] = sext i16 [[TMP45]] to i32
1017 // CHECK1-NEXT:    [[TMP46:%.*]] = load i32, ptr [[B]], align 4
1018 // CHECK1-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP46]]
1019 // CHECK1-NEXT:    [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
1020 // CHECK1-NEXT:    call void @llvm.stackrestore.p0(ptr [[TMP47]])
1021 // CHECK1-NEXT:    ret i32 [[ADD3]]
1022 //
1023 //
1024 // CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici
1025 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
1026 // CHECK1-NEXT:  entry:
1027 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
1028 // CHECK1-NEXT:    [[A:%.*]] = alloca i32, align 4
1029 // CHECK1-NEXT:    [[AA:%.*]] = alloca i16, align 2
1030 // CHECK1-NEXT:    [[AAA:%.*]] = alloca i8, align 1
1031 // CHECK1-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
1032 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
1033 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
1034 // CHECK1-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
1035 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 8
1036 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 8
1037 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 8
1038 // CHECK1-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1039 // CHECK1-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
1040 // CHECK1-NEXT:    store i32 0, ptr [[A]], align 4
1041 // CHECK1-NEXT:    store i16 0, ptr [[AA]], align 2
1042 // CHECK1-NEXT:    store i8 0, ptr [[AAA]], align 1
1043 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A]], align 4
1044 // CHECK1-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 4
1045 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8
1046 // CHECK1-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA]], align 2
1047 // CHECK1-NEXT:    store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
1048 // CHECK1-NEXT:    [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8
1049 // CHECK1-NEXT:    [[TMP4:%.*]] = load i8, ptr [[AAA]], align 1
1050 // CHECK1-NEXT:    store i8 [[TMP4]], ptr [[AAA_CASTED]], align 1
1051 // CHECK1-NEXT:    [[TMP5:%.*]] = load i64, ptr [[AAA_CASTED]], align 8
1052 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4
1053 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50
1054 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
1055 // CHECK1:       omp_if.then:
1056 // CHECK1-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1057 // CHECK1-NEXT:    store i64 [[TMP1]], ptr [[TMP7]], align 8
1058 // CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1059 // CHECK1-NEXT:    store i64 [[TMP1]], ptr [[TMP8]], align 8
1060 // CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
1061 // CHECK1-NEXT:    store ptr null, ptr [[TMP9]], align 8
1062 // CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1063 // CHECK1-NEXT:    store i64 [[TMP3]], ptr [[TMP10]], align 8
1064 // CHECK1-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1065 // CHECK1-NEXT:    store i64 [[TMP3]], ptr [[TMP11]], align 8
1066 // CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
1067 // CHECK1-NEXT:    store ptr null, ptr [[TMP12]], align 8
1068 // CHECK1-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1069 // CHECK1-NEXT:    store i64 [[TMP5]], ptr [[TMP13]], align 8
1070 // CHECK1-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1071 // CHECK1-NEXT:    store i64 [[TMP5]], ptr [[TMP14]], align 8
1072 // CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
1073 // CHECK1-NEXT:    store ptr null, ptr [[TMP15]], align 8
1074 // CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1075 // CHECK1-NEXT:    store ptr [[B]], ptr [[TMP16]], align 8
1076 // CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1077 // CHECK1-NEXT:    store ptr [[B]], ptr [[TMP17]], align 8
1078 // CHECK1-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
1079 // CHECK1-NEXT:    store ptr null, ptr [[TMP18]], align 8
1080 // CHECK1-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1081 // CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1082 // CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
1083 // CHECK1-NEXT:    store i32 2, ptr [[TMP21]], align 4
1084 // CHECK1-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
1085 // CHECK1-NEXT:    store i32 4, ptr [[TMP22]], align 4
1086 // CHECK1-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
1087 // CHECK1-NEXT:    store ptr [[TMP19]], ptr [[TMP23]], align 8
1088 // CHECK1-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
1089 // CHECK1-NEXT:    store ptr [[TMP20]], ptr [[TMP24]], align 8
1090 // CHECK1-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
1091 // CHECK1-NEXT:    store ptr @.offload_sizes.7, ptr [[TMP25]], align 8
1092 // CHECK1-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
1093 // CHECK1-NEXT:    store ptr @.offload_maptypes.8, ptr [[TMP26]], align 8
1094 // CHECK1-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
1095 // CHECK1-NEXT:    store ptr null, ptr [[TMP27]], align 8
1096 // CHECK1-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
1097 // CHECK1-NEXT:    store ptr null, ptr [[TMP28]], align 8
1098 // CHECK1-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
1099 // CHECK1-NEXT:    store i64 0, ptr [[TMP29]], align 8
1100 // CHECK1-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
1101 // CHECK1-NEXT:    store i64 0, ptr [[TMP30]], align 8
1102 // CHECK1-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
1103 // CHECK1-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP31]], align 4
1104 // CHECK1-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
1105 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP32]], align 4
1106 // CHECK1-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
1107 // CHECK1-NEXT:    store i32 0, ptr [[TMP33]], align 4
1108 // CHECK1-NEXT:    [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.region_id, ptr [[KERNEL_ARGS]])
1109 // CHECK1-NEXT:    [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0
1110 // CHECK1-NEXT:    br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1111 // CHECK1:       omp_offload.failed:
1112 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], ptr [[B]]) #[[ATTR3]]
1113 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
1114 // CHECK1:       omp_offload.cont:
1115 // CHECK1-NEXT:    br label [[OMP_IF_END:%.*]]
1116 // CHECK1:       omp_if.else:
1117 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], ptr [[B]]) #[[ATTR3]]
1118 // CHECK1-NEXT:    br label [[OMP_IF_END]]
1119 // CHECK1:       omp_if.end:
1120 // CHECK1-NEXT:    [[TMP36:%.*]] = load i32, ptr [[A]], align 4
1121 // CHECK1-NEXT:    ret i32 [[TMP36]]
1122 //
1123 //
1124 // CHECK1-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
1125 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
1126 // CHECK1-NEXT:  entry:
1127 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
1128 // CHECK1-NEXT:    [[A:%.*]] = alloca i32, align 4
1129 // CHECK1-NEXT:    [[AA:%.*]] = alloca i16, align 2
1130 // CHECK1-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
1131 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
1132 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
1133 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8
1134 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 8
1135 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 8
1136 // CHECK1-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1137 // CHECK1-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
1138 // CHECK1-NEXT:    store i32 0, ptr [[A]], align 4
1139 // CHECK1-NEXT:    store i16 0, ptr [[AA]], align 2
1140 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A]], align 4
1141 // CHECK1-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 4
1142 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8
1143 // CHECK1-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA]], align 2
1144 // CHECK1-NEXT:    store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
1145 // CHECK1-NEXT:    [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8
1146 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
1147 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
1148 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
1149 // CHECK1:       omp_if.then:
1150 // CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1151 // CHECK1-NEXT:    store i64 [[TMP1]], ptr [[TMP5]], align 8
1152 // CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1153 // CHECK1-NEXT:    store i64 [[TMP1]], ptr [[TMP6]], align 8
1154 // CHECK1-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
1155 // CHECK1-NEXT:    store ptr null, ptr [[TMP7]], align 8
1156 // CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1157 // CHECK1-NEXT:    store i64 [[TMP3]], ptr [[TMP8]], align 8
1158 // CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1159 // CHECK1-NEXT:    store i64 [[TMP3]], ptr [[TMP9]], align 8
1160 // CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
1161 // CHECK1-NEXT:    store ptr null, ptr [[TMP10]], align 8
1162 // CHECK1-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1163 // CHECK1-NEXT:    store ptr [[B]], ptr [[TMP11]], align 8
1164 // CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1165 // CHECK1-NEXT:    store ptr [[B]], ptr [[TMP12]], align 8
1166 // CHECK1-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
1167 // CHECK1-NEXT:    store ptr null, ptr [[TMP13]], align 8
1168 // CHECK1-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1169 // CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1170 // CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
1171 // CHECK1-NEXT:    store i32 2, ptr [[TMP16]], align 4
1172 // CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
1173 // CHECK1-NEXT:    store i32 3, ptr [[TMP17]], align 4
1174 // CHECK1-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
1175 // CHECK1-NEXT:    store ptr [[TMP14]], ptr [[TMP18]], align 8
1176 // CHECK1-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
1177 // CHECK1-NEXT:    store ptr [[TMP15]], ptr [[TMP19]], align 8
1178 // CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
1179 // CHECK1-NEXT:    store ptr @.offload_sizes.9, ptr [[TMP20]], align 8
1180 // CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
1181 // CHECK1-NEXT:    store ptr @.offload_maptypes.10, ptr [[TMP21]], align 8
1182 // CHECK1-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
1183 // CHECK1-NEXT:    store ptr null, ptr [[TMP22]], align 8
1184 // CHECK1-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
1185 // CHECK1-NEXT:    store ptr null, ptr [[TMP23]], align 8
1186 // CHECK1-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
1187 // CHECK1-NEXT:    store i64 0, ptr [[TMP24]], align 8
1188 // CHECK1-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
1189 // CHECK1-NEXT:    store i64 0, ptr [[TMP25]], align 8
1190 // CHECK1-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
1191 // CHECK1-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP26]], align 4
1192 // CHECK1-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
1193 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP27]], align 4
1194 // CHECK1-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
1195 // CHECK1-NEXT:    store i32 0, ptr [[TMP28]], align 4
1196 // CHECK1-NEXT:    [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.region_id, ptr [[KERNEL_ARGS]])
1197 // CHECK1-NEXT:    [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
1198 // CHECK1-NEXT:    br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1199 // CHECK1:       omp_offload.failed:
1200 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR3]]
1201 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
1202 // CHECK1:       omp_offload.cont:
1203 // CHECK1-NEXT:    br label [[OMP_IF_END:%.*]]
1204 // CHECK1:       omp_if.else:
1205 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR3]]
1206 // CHECK1-NEXT:    br label [[OMP_IF_END]]
1207 // CHECK1:       omp_if.end:
1208 // CHECK1-NEXT:    [[TMP31:%.*]] = load i32, ptr [[A]], align 4
1209 // CHECK1-NEXT:    ret i32 [[TMP31]]
1210 //
1211 //
1212 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216
1213 // CHECK1-SAME: (ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
1214 // CHECK1-NEXT:  entry:
1215 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1216 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
1217 // CHECK1-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
1218 // CHECK1-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
1219 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
1220 // CHECK1-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
1221 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1222 // CHECK1-NEXT:    store i64 [[B]], ptr [[B_ADDR]], align 8
1223 // CHECK1-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
1224 // CHECK1-NEXT:    store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
1225 // CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
1226 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1227 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
1228 // CHECK1-NEXT:    [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
1229 // CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
1230 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4
1231 // CHECK1-NEXT:    store i32 [[TMP4]], ptr [[B_CASTED]], align 4
1232 // CHECK1-NEXT:    [[TMP5:%.*]] = load i64, ptr [[B_CASTED]], align 8
1233 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.omp_outlined, ptr [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], ptr [[TMP3]])
1234 // CHECK1-NEXT:    ret void
1235 //
1236 //
1237 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.omp_outlined
1238 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
1239 // CHECK1-NEXT:  entry:
1240 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1241 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1242 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1243 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
1244 // CHECK1-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
1245 // CHECK1-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
1246 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
1247 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1248 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1249 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1250 // CHECK1-NEXT:    store i64 [[B]], ptr [[B_ADDR]], align 8
1251 // CHECK1-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
1252 // CHECK1-NEXT:    store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
1253 // CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
1254 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1255 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
1256 // CHECK1-NEXT:    [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
1257 // CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
1258 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4
1259 // CHECK1-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP4]] to double
1260 // CHECK1-NEXT:    [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
1261 // CHECK1-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0
1262 // CHECK1-NEXT:    store double [[ADD]], ptr [[A]], align 8
1263 // CHECK1-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0
1264 // CHECK1-NEXT:    [[TMP5:%.*]] = load double, ptr [[A3]], align 8
1265 // CHECK1-NEXT:    [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
1266 // CHECK1-NEXT:    store double [[INC]], ptr [[A3]], align 8
1267 // CHECK1-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
1268 // CHECK1-NEXT:    [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]]
1269 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i64 [[TMP6]]
1270 // CHECK1-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1
1271 // CHECK1-NEXT:    store i16 [[CONV4]], ptr [[ARRAYIDX5]], align 2
1272 // CHECK1-NEXT:    ret void
1273 //
1274 //
1275 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198
1276 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
1277 // CHECK1-NEXT:  entry:
1278 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1279 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
1280 // CHECK1-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
1281 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
1282 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
1283 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
1284 // CHECK1-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
1285 // CHECK1-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
1286 // CHECK1-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
1287 // CHECK1-NEXT:    store i64 [[AAA]], ptr [[AAA_ADDR]], align 8
1288 // CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
1289 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
1290 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
1291 // CHECK1-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 4
1292 // CHECK1-NEXT:    [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8
1293 // CHECK1-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
1294 // CHECK1-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
1295 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8
1296 // CHECK1-NEXT:    [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 1
1297 // CHECK1-NEXT:    store i8 [[TMP5]], ptr [[AAA_CASTED]], align 1
1298 // CHECK1-NEXT:    [[TMP6:%.*]] = load i64, ptr [[AAA_CASTED]], align 8
1299 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], ptr [[TMP0]])
1300 // CHECK1-NEXT:    ret void
1301 //
1302 //
1303 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.omp_outlined
1304 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
1305 // CHECK1-NEXT:  entry:
1306 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1307 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1308 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1309 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
1310 // CHECK1-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
1311 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
1312 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1313 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1314 // CHECK1-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
1315 // CHECK1-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
1316 // CHECK1-NEXT:    store i64 [[AAA]], ptr [[AAA_ADDR]], align 8
1317 // CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
1318 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
1319 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
1320 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
1321 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 4
1322 // CHECK1-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2
1323 // CHECK1-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i32
1324 // CHECK1-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
1325 // CHECK1-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
1326 // CHECK1-NEXT:    store i16 [[CONV2]], ptr [[AA_ADDR]], align 2
1327 // CHECK1-NEXT:    [[TMP3:%.*]] = load i8, ptr [[AAA_ADDR]], align 1
1328 // CHECK1-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP3]] to i32
1329 // CHECK1-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
1330 // CHECK1-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8
1331 // CHECK1-NEXT:    store i8 [[CONV5]], ptr [[AAA_ADDR]], align 1
1332 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2
1333 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
1334 // CHECK1-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP4]], 1
1335 // CHECK1-NEXT:    store i32 [[ADD6]], ptr [[ARRAYIDX]], align 4
1336 // CHECK1-NEXT:    ret void
1337 //
1338 //
1339 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181
1340 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
1341 // CHECK1-NEXT:  entry:
1342 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1343 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
1344 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
1345 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
1346 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
1347 // CHECK1-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
1348 // CHECK1-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
1349 // CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
1350 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
1351 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
1352 // CHECK1-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 4
1353 // CHECK1-NEXT:    [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8
1354 // CHECK1-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
1355 // CHECK1-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
1356 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8
1357 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], ptr [[TMP0]])
1358 // CHECK1-NEXT:    ret void
1359 //
1360 //
1361 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.omp_outlined
1362 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
1363 // CHECK1-NEXT:  entry:
1364 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1365 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1366 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1367 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
1368 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
1369 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1370 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1371 // CHECK1-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
1372 // CHECK1-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
1373 // CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
1374 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
1375 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
1376 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
1377 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 4
1378 // CHECK1-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2
1379 // CHECK1-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i32
1380 // CHECK1-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
1381 // CHECK1-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
1382 // CHECK1-NEXT:    store i16 [[CONV2]], ptr [[AA_ADDR]], align 2
1383 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2
1384 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
1385 // CHECK1-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1
1386 // CHECK1-NEXT:    store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4
1387 // CHECK1-NEXT:    ret void
1388 //
1389 //
1390 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
1391 // CHECK1-SAME: () #[[ATTR7:[0-9]+]] {
1392 // CHECK1-NEXT:  entry:
1393 // CHECK1-NEXT:    call void @__tgt_register_requires(i64 1)
1394 // CHECK1-NEXT:    ret void
1395 //
1396 //
1397 // CHECK3-LABEL: define {{[^@]+}}@_Z3fooi
1398 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] {
1399 // CHECK3-NEXT:  entry:
1400 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
1401 // CHECK3-NEXT:    [[A:%.*]] = alloca i32, align 4
1402 // CHECK3-NEXT:    [[AA:%.*]] = alloca i16, align 2
1403 // CHECK3-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
1404 // CHECK3-NEXT:    [[SAVED_STACK:%.*]] = alloca ptr, align 4
1405 // CHECK3-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
1406 // CHECK3-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
1407 // CHECK3-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
1408 // CHECK3-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
1409 // CHECK3-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1
1410 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
1411 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
1412 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 4
1413 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 4
1414 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 4
1415 // CHECK3-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1416 // CHECK3-NEXT:    [[A_CASTED2:%.*]] = alloca i32, align 4
1417 // CHECK3-NEXT:    [[AA_CASTED3:%.*]] = alloca i32, align 4
1418 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [2 x ptr], align 4
1419 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS5:%.*]] = alloca [2 x ptr], align 4
1420 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [2 x ptr], align 4
1421 // CHECK3-NEXT:    [[KERNEL_ARGS7:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
1422 // CHECK3-NEXT:    [[A_CASTED10:%.*]] = alloca i32, align 4
1423 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS13:%.*]] = alloca [9 x ptr], align 4
1424 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS14:%.*]] = alloca [9 x ptr], align 4
1425 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS15:%.*]] = alloca [9 x ptr], align 4
1426 // CHECK3-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 4
1427 // CHECK3-NEXT:    [[KERNEL_ARGS16:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
1428 // CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
1429 // CHECK3-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
1430 // CHECK3-NEXT:    store i32 0, ptr [[A]], align 4
1431 // CHECK3-NEXT:    store i16 0, ptr [[AA]], align 2
1432 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
1433 // CHECK3-NEXT:    [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
1434 // CHECK3-NEXT:    store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4
1435 // CHECK3-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4
1436 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4
1437 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4
1438 // CHECK3-NEXT:    [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]]
1439 // CHECK3-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8
1440 // CHECK3-NEXT:    store i32 [[TMP3]], ptr [[__VLA_EXPR1]], align 4
1441 // CHECK3-NEXT:    [[TMP5:%.*]] = call ptr @__kmpc_omp_target_task_alloc(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i32 20, i32 1, ptr @.omp_task_entry., i64 -1)
1442 // CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP5]], i32 0, i32 0
1443 // CHECK3-NEXT:    [[TMP7:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP5]])
1444 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A]], align 4
1445 // CHECK3-NEXT:    store i32 [[TMP8]], ptr [[A_CASTED]], align 4
1446 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4
1447 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104(i32 [[TMP9]]) #[[ATTR3:[0-9]+]]
1448 // CHECK3-NEXT:    [[TMP10:%.*]] = load i16, ptr [[AA]], align 2
1449 // CHECK3-NEXT:    store i16 [[TMP10]], ptr [[AA_CASTED]], align 2
1450 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[AA_CASTED]], align 4
1451 // CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1452 // CHECK3-NEXT:    store i32 [[TMP11]], ptr [[TMP12]], align 4
1453 // CHECK3-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1454 // CHECK3-NEXT:    store i32 [[TMP11]], ptr [[TMP13]], align 4
1455 // CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
1456 // CHECK3-NEXT:    store ptr null, ptr [[TMP14]], align 4
1457 // CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1458 // CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1459 // CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
1460 // CHECK3-NEXT:    store i32 2, ptr [[TMP17]], align 4
1461 // CHECK3-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
1462 // CHECK3-NEXT:    store i32 1, ptr [[TMP18]], align 4
1463 // CHECK3-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
1464 // CHECK3-NEXT:    store ptr [[TMP15]], ptr [[TMP19]], align 4
1465 // CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
1466 // CHECK3-NEXT:    store ptr [[TMP16]], ptr [[TMP20]], align 4
1467 // CHECK3-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
1468 // CHECK3-NEXT:    store ptr @.offload_sizes, ptr [[TMP21]], align 4
1469 // CHECK3-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
1470 // CHECK3-NEXT:    store ptr @.offload_maptypes, ptr [[TMP22]], align 4
1471 // CHECK3-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
1472 // CHECK3-NEXT:    store ptr null, ptr [[TMP23]], align 4
1473 // CHECK3-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
1474 // CHECK3-NEXT:    store ptr null, ptr [[TMP24]], align 4
1475 // CHECK3-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
1476 // CHECK3-NEXT:    store i64 0, ptr [[TMP25]], align 8
1477 // CHECK3-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
1478 // CHECK3-NEXT:    store i64 0, ptr [[TMP26]], align 8
1479 // CHECK3-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
1480 // CHECK3-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP27]], align 4
1481 // CHECK3-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
1482 // CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP28]], align 4
1483 // CHECK3-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
1484 // CHECK3-NEXT:    store i32 0, ptr [[TMP29]], align 4
1485 // CHECK3-NEXT:    [[TMP30:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.region_id, ptr [[KERNEL_ARGS]])
1486 // CHECK3-NEXT:    [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0
1487 // CHECK3-NEXT:    br i1 [[TMP31]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1488 // CHECK3:       omp_offload.failed:
1489 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i32 [[TMP11]]) #[[ATTR3]]
1490 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]
1491 // CHECK3:       omp_offload.cont:
1492 // CHECK3-NEXT:    [[TMP32:%.*]] = load i32, ptr [[A]], align 4
1493 // CHECK3-NEXT:    store i32 [[TMP32]], ptr [[A_CASTED2]], align 4
1494 // CHECK3-NEXT:    [[TMP33:%.*]] = load i32, ptr [[A_CASTED2]], align 4
1495 // CHECK3-NEXT:    [[TMP34:%.*]] = load i16, ptr [[AA]], align 2
1496 // CHECK3-NEXT:    store i16 [[TMP34]], ptr [[AA_CASTED3]], align 2
1497 // CHECK3-NEXT:    [[TMP35:%.*]] = load i32, ptr [[AA_CASTED3]], align 4
1498 // CHECK3-NEXT:    [[TMP36:%.*]] = load i32, ptr [[N_ADDR]], align 4
1499 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP36]], 10
1500 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
1501 // CHECK3:       omp_if.then:
1502 // CHECK3-NEXT:    [[TMP37:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0
1503 // CHECK3-NEXT:    store i32 [[TMP33]], ptr [[TMP37]], align 4
1504 // CHECK3-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS5]], i32 0, i32 0
1505 // CHECK3-NEXT:    store i32 [[TMP33]], ptr [[TMP38]], align 4
1506 // CHECK3-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 0
1507 // CHECK3-NEXT:    store ptr null, ptr [[TMP39]], align 4
1508 // CHECK3-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1
1509 // CHECK3-NEXT:    store i32 [[TMP35]], ptr [[TMP40]], align 4
1510 // CHECK3-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS5]], i32 0, i32 1
1511 // CHECK3-NEXT:    store i32 [[TMP35]], ptr [[TMP41]], align 4
1512 // CHECK3-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS6]], i32 0, i32 1
1513 // CHECK3-NEXT:    store ptr null, ptr [[TMP42]], align 4
1514 // CHECK3-NEXT:    [[TMP43:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0
1515 // CHECK3-NEXT:    [[TMP44:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS5]], i32 0, i32 0
1516 // CHECK3-NEXT:    [[TMP45:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS7]], i32 0, i32 0
1517 // CHECK3-NEXT:    store i32 2, ptr [[TMP45]], align 4
1518 // CHECK3-NEXT:    [[TMP46:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS7]], i32 0, i32 1
1519 // CHECK3-NEXT:    store i32 2, ptr [[TMP46]], align 4
1520 // CHECK3-NEXT:    [[TMP47:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS7]], i32 0, i32 2
1521 // CHECK3-NEXT:    store ptr [[TMP43]], ptr [[TMP47]], align 4
1522 // CHECK3-NEXT:    [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS7]], i32 0, i32 3
1523 // CHECK3-NEXT:    store ptr [[TMP44]], ptr [[TMP48]], align 4
1524 // CHECK3-NEXT:    [[TMP49:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS7]], i32 0, i32 4
1525 // CHECK3-NEXT:    store ptr @.offload_sizes.1, ptr [[TMP49]], align 4
1526 // CHECK3-NEXT:    [[TMP50:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS7]], i32 0, i32 5
1527 // CHECK3-NEXT:    store ptr @.offload_maptypes.2, ptr [[TMP50]], align 4
1528 // CHECK3-NEXT:    [[TMP51:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS7]], i32 0, i32 6
1529 // CHECK3-NEXT:    store ptr null, ptr [[TMP51]], align 4
1530 // CHECK3-NEXT:    [[TMP52:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS7]], i32 0, i32 7
1531 // CHECK3-NEXT:    store ptr null, ptr [[TMP52]], align 4
1532 // CHECK3-NEXT:    [[TMP53:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS7]], i32 0, i32 8
1533 // CHECK3-NEXT:    store i64 0, ptr [[TMP53]], align 8
1534 // CHECK3-NEXT:    [[TMP54:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS7]], i32 0, i32 9
1535 // CHECK3-NEXT:    store i64 0, ptr [[TMP54]], align 8
1536 // CHECK3-NEXT:    [[TMP55:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS7]], i32 0, i32 10
1537 // CHECK3-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP55]], align 4
1538 // CHECK3-NEXT:    [[TMP56:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS7]], i32 0, i32 11
1539 // CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP56]], align 4
1540 // CHECK3-NEXT:    [[TMP57:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS7]], i32 0, i32 12
1541 // CHECK3-NEXT:    store i32 0, ptr [[TMP57]], align 4
1542 // CHECK3-NEXT:    [[TMP58:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.region_id, ptr [[KERNEL_ARGS7]])
1543 // CHECK3-NEXT:    [[TMP59:%.*]] = icmp ne i32 [[TMP58]], 0
1544 // CHECK3-NEXT:    br i1 [[TMP59]], label [[OMP_OFFLOAD_FAILED8:%.*]], label [[OMP_OFFLOAD_CONT9:%.*]]
1545 // CHECK3:       omp_offload.failed8:
1546 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i32 [[TMP33]], i32 [[TMP35]]) #[[ATTR3]]
1547 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT9]]
1548 // CHECK3:       omp_offload.cont9:
1549 // CHECK3-NEXT:    br label [[OMP_IF_END:%.*]]
1550 // CHECK3:       omp_if.else:
1551 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i32 [[TMP33]], i32 [[TMP35]]) #[[ATTR3]]
1552 // CHECK3-NEXT:    br label [[OMP_IF_END]]
1553 // CHECK3:       omp_if.end:
1554 // CHECK3-NEXT:    [[TMP60:%.*]] = load i32, ptr [[A]], align 4
1555 // CHECK3-NEXT:    store i32 [[TMP60]], ptr [[A_CASTED10]], align 4
1556 // CHECK3-NEXT:    [[TMP61:%.*]] = load i32, ptr [[A_CASTED10]], align 4
1557 // CHECK3-NEXT:    [[TMP62:%.*]] = load i32, ptr [[N_ADDR]], align 4
1558 // CHECK3-NEXT:    [[CMP11:%.*]] = icmp sgt i32 [[TMP62]], 20
1559 // CHECK3-NEXT:    br i1 [[CMP11]], label [[OMP_IF_THEN12:%.*]], label [[OMP_IF_ELSE19:%.*]]
1560 // CHECK3:       omp_if.then12:
1561 // CHECK3-NEXT:    [[TMP63:%.*]] = mul nuw i32 [[TMP1]], 4
1562 // CHECK3-NEXT:    [[TMP64:%.*]] = sext i32 [[TMP63]] to i64
1563 // CHECK3-NEXT:    [[TMP65:%.*]] = mul nuw i32 5, [[TMP3]]
1564 // CHECK3-NEXT:    [[TMP66:%.*]] = mul nuw i32 [[TMP65]], 8
1565 // CHECK3-NEXT:    [[TMP67:%.*]] = sext i32 [[TMP66]] to i64
1566 // CHECK3-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes.3, i32 72, i1 false)
1567 // CHECK3-NEXT:    [[TMP68:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0
1568 // CHECK3-NEXT:    store i32 [[TMP61]], ptr [[TMP68]], align 4
1569 // CHECK3-NEXT:    [[TMP69:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS14]], i32 0, i32 0
1570 // CHECK3-NEXT:    store i32 [[TMP61]], ptr [[TMP69]], align 4
1571 // CHECK3-NEXT:    [[TMP70:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 0
1572 // CHECK3-NEXT:    store ptr null, ptr [[TMP70]], align 4
1573 // CHECK3-NEXT:    [[TMP71:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 1
1574 // CHECK3-NEXT:    store ptr [[B]], ptr [[TMP71]], align 4
1575 // CHECK3-NEXT:    [[TMP72:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS14]], i32 0, i32 1
1576 // CHECK3-NEXT:    store ptr [[B]], ptr [[TMP72]], align 4
1577 // CHECK3-NEXT:    [[TMP73:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 1
1578 // CHECK3-NEXT:    store ptr null, ptr [[TMP73]], align 4
1579 // CHECK3-NEXT:    [[TMP74:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 2
1580 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[TMP74]], align 4
1581 // CHECK3-NEXT:    [[TMP75:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS14]], i32 0, i32 2
1582 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[TMP75]], align 4
1583 // CHECK3-NEXT:    [[TMP76:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 2
1584 // CHECK3-NEXT:    store ptr null, ptr [[TMP76]], align 4
1585 // CHECK3-NEXT:    [[TMP77:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 3
1586 // CHECK3-NEXT:    store ptr [[VLA]], ptr [[TMP77]], align 4
1587 // CHECK3-NEXT:    [[TMP78:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS14]], i32 0, i32 3
1588 // CHECK3-NEXT:    store ptr [[VLA]], ptr [[TMP78]], align 4
1589 // CHECK3-NEXT:    [[TMP79:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 3
1590 // CHECK3-NEXT:    store i64 [[TMP64]], ptr [[TMP79]], align 4
1591 // CHECK3-NEXT:    [[TMP80:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 3
1592 // CHECK3-NEXT:    store ptr null, ptr [[TMP80]], align 4
1593 // CHECK3-NEXT:    [[TMP81:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 4
1594 // CHECK3-NEXT:    store ptr [[C]], ptr [[TMP81]], align 4
1595 // CHECK3-NEXT:    [[TMP82:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS14]], i32 0, i32 4
1596 // CHECK3-NEXT:    store ptr [[C]], ptr [[TMP82]], align 4
1597 // CHECK3-NEXT:    [[TMP83:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 4
1598 // CHECK3-NEXT:    store ptr null, ptr [[TMP83]], align 4
1599 // CHECK3-NEXT:    [[TMP84:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 5
1600 // CHECK3-NEXT:    store i32 5, ptr [[TMP84]], align 4
1601 // CHECK3-NEXT:    [[TMP85:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS14]], i32 0, i32 5
1602 // CHECK3-NEXT:    store i32 5, ptr [[TMP85]], align 4
1603 // CHECK3-NEXT:    [[TMP86:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 5
1604 // CHECK3-NEXT:    store ptr null, ptr [[TMP86]], align 4
1605 // CHECK3-NEXT:    [[TMP87:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 6
1606 // CHECK3-NEXT:    store i32 [[TMP3]], ptr [[TMP87]], align 4
1607 // CHECK3-NEXT:    [[TMP88:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS14]], i32 0, i32 6
1608 // CHECK3-NEXT:    store i32 [[TMP3]], ptr [[TMP88]], align 4
1609 // CHECK3-NEXT:    [[TMP89:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 6
1610 // CHECK3-NEXT:    store ptr null, ptr [[TMP89]], align 4
1611 // CHECK3-NEXT:    [[TMP90:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 7
1612 // CHECK3-NEXT:    store ptr [[VLA1]], ptr [[TMP90]], align 4
1613 // CHECK3-NEXT:    [[TMP91:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS14]], i32 0, i32 7
1614 // CHECK3-NEXT:    store ptr [[VLA1]], ptr [[TMP91]], align 4
1615 // CHECK3-NEXT:    [[TMP92:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 7
1616 // CHECK3-NEXT:    store i64 [[TMP67]], ptr [[TMP92]], align 4
1617 // CHECK3-NEXT:    [[TMP93:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 7
1618 // CHECK3-NEXT:    store ptr null, ptr [[TMP93]], align 4
1619 // CHECK3-NEXT:    [[TMP94:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 8
1620 // CHECK3-NEXT:    store ptr [[D]], ptr [[TMP94]], align 4
1621 // CHECK3-NEXT:    [[TMP95:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS14]], i32 0, i32 8
1622 // CHECK3-NEXT:    store ptr [[D]], ptr [[TMP95]], align 4
1623 // CHECK3-NEXT:    [[TMP96:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 8
1624 // CHECK3-NEXT:    store ptr null, ptr [[TMP96]], align 4
1625 // CHECK3-NEXT:    [[TMP97:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0
1626 // CHECK3-NEXT:    [[TMP98:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS14]], i32 0, i32 0
1627 // CHECK3-NEXT:    [[TMP99:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0
1628 // CHECK3-NEXT:    [[TMP100:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 0
1629 // CHECK3-NEXT:    store i32 2, ptr [[TMP100]], align 4
1630 // CHECK3-NEXT:    [[TMP101:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 1
1631 // CHECK3-NEXT:    store i32 9, ptr [[TMP101]], align 4
1632 // CHECK3-NEXT:    [[TMP102:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 2
1633 // CHECK3-NEXT:    store ptr [[TMP97]], ptr [[TMP102]], align 4
1634 // CHECK3-NEXT:    [[TMP103:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 3
1635 // CHECK3-NEXT:    store ptr [[TMP98]], ptr [[TMP103]], align 4
1636 // CHECK3-NEXT:    [[TMP104:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 4
1637 // CHECK3-NEXT:    store ptr [[TMP99]], ptr [[TMP104]], align 4
1638 // CHECK3-NEXT:    [[TMP105:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 5
1639 // CHECK3-NEXT:    store ptr @.offload_maptypes.4, ptr [[TMP105]], align 4
1640 // CHECK3-NEXT:    [[TMP106:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 6
1641 // CHECK3-NEXT:    store ptr null, ptr [[TMP106]], align 4
1642 // CHECK3-NEXT:    [[TMP107:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 7
1643 // CHECK3-NEXT:    store ptr null, ptr [[TMP107]], align 4
1644 // CHECK3-NEXT:    [[TMP108:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 8
1645 // CHECK3-NEXT:    store i64 0, ptr [[TMP108]], align 8
1646 // CHECK3-NEXT:    [[TMP109:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 9
1647 // CHECK3-NEXT:    store i64 0, ptr [[TMP109]], align 8
1648 // CHECK3-NEXT:    [[TMP110:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 10
1649 // CHECK3-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP110]], align 4
1650 // CHECK3-NEXT:    [[TMP111:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 11
1651 // CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP111]], align 4
1652 // CHECK3-NEXT:    [[TMP112:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS16]], i32 0, i32 12
1653 // CHECK3-NEXT:    store i32 0, ptr [[TMP112]], align 4
1654 // CHECK3-NEXT:    [[TMP113:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.region_id, ptr [[KERNEL_ARGS16]])
1655 // CHECK3-NEXT:    [[TMP114:%.*]] = icmp ne i32 [[TMP113]], 0
1656 // CHECK3-NEXT:    br i1 [[TMP114]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]]
1657 // CHECK3:       omp_offload.failed17:
1658 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i32 [[TMP61]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]]) #[[ATTR3]]
1659 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT18]]
1660 // CHECK3:       omp_offload.cont18:
1661 // CHECK3-NEXT:    br label [[OMP_IF_END20:%.*]]
1662 // CHECK3:       omp_if.else19:
1663 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i32 [[TMP61]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]]) #[[ATTR3]]
1664 // CHECK3-NEXT:    br label [[OMP_IF_END20]]
1665 // CHECK3:       omp_if.end20:
1666 // CHECK3-NEXT:    [[TMP115:%.*]] = load i32, ptr [[A]], align 4
1667 // CHECK3-NEXT:    [[TMP116:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
1668 // CHECK3-NEXT:    call void @llvm.stackrestore.p0(ptr [[TMP116]])
1669 // CHECK3-NEXT:    ret i32 [[TMP115]]
1670 //
1671 //
1672 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100
1673 // CHECK3-SAME: () #[[ATTR2:[0-9]+]] {
1674 // CHECK3-NEXT:  entry:
1675 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.omp_outlined)
1676 // CHECK3-NEXT:    ret void
1677 //
1678 //
1679 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.omp_outlined
1680 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] {
1681 // CHECK3-NEXT:  entry:
1682 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
1683 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
1684 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
1685 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
1686 // CHECK3-NEXT:    ret void
1687 //
1688 //
1689 // CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry.
1690 // CHECK3-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] {
1691 // CHECK3-NEXT:  entry:
1692 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
1693 // CHECK3-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 4
1694 // CHECK3-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 4
1695 // CHECK3-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 4
1696 // CHECK3-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 4
1697 // CHECK3-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 4
1698 // CHECK3-NEXT:    [[KERNEL_ARGS_I:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1699 // CHECK3-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 4
1700 // CHECK3-NEXT:    [[DOTADDR1:%.*]] = alloca ptr, align 4
1701 // CHECK3-NEXT:    store i32 [[TMP0]], ptr [[DOTADDR]], align 4
1702 // CHECK3-NEXT:    store ptr [[TMP1]], ptr [[DOTADDR1]], align 4
1703 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4
1704 // CHECK3-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 4
1705 // CHECK3-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0
1706 // CHECK3-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2
1707 // CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0
1708 // CHECK3-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 4
1709 // CHECK3-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META13:![0-9]+]])
1710 // CHECK3-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]])
1711 // CHECK3-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])
1712 // CHECK3-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
1713 // CHECK3-NEXT:    store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !22
1714 // CHECK3-NEXT:    store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 4, !noalias !22
1715 // CHECK3-NEXT:    store ptr null, ptr [[DOTPRIVATES__ADDR_I]], align 4, !noalias !22
1716 // CHECK3-NEXT:    store ptr null, ptr [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !22
1717 // CHECK3-NEXT:    store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 4, !noalias !22
1718 // CHECK3-NEXT:    store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 4, !noalias !22
1719 // CHECK3-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 4, !noalias !22
1720 // CHECK3-NEXT:    store i32 2, ptr [[KERNEL_ARGS_I]], align 4, !noalias !22
1721 // CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 1
1722 // CHECK3-NEXT:    store i32 0, ptr [[TMP9]], align 4, !noalias !22
1723 // CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 2
1724 // CHECK3-NEXT:    store ptr null, ptr [[TMP10]], align 4, !noalias !22
1725 // CHECK3-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 3
1726 // CHECK3-NEXT:    store ptr null, ptr [[TMP11]], align 4, !noalias !22
1727 // CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 4
1728 // CHECK3-NEXT:    store ptr null, ptr [[TMP12]], align 4, !noalias !22
1729 // CHECK3-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 5
1730 // CHECK3-NEXT:    store ptr null, ptr [[TMP13]], align 4, !noalias !22
1731 // CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 6
1732 // CHECK3-NEXT:    store ptr null, ptr [[TMP14]], align 4, !noalias !22
1733 // CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 7
1734 // CHECK3-NEXT:    store ptr null, ptr [[TMP15]], align 4, !noalias !22
1735 // CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 8
1736 // CHECK3-NEXT:    store i64 0, ptr [[TMP16]], align 8, !noalias !22
1737 // CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 9
1738 // CHECK3-NEXT:    store i64 1, ptr [[TMP17]], align 8, !noalias !22
1739 // CHECK3-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 10
1740 // CHECK3-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP18]], align 4, !noalias !22
1741 // CHECK3-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 11
1742 // CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP19]], align 4, !noalias !22
1743 // CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 12
1744 // CHECK3-NEXT:    store i32 0, ptr [[TMP20]], align 4, !noalias !22
1745 // CHECK3-NEXT:    [[TMP21:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.region_id, ptr [[KERNEL_ARGS_I]])
1746 // CHECK3-NEXT:    [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
1747 // CHECK3-NEXT:    br i1 [[TMP22]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]]
1748 // CHECK3:       omp_offload.failed.i:
1749 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100() #[[ATTR3]]
1750 // CHECK3-NEXT:    br label [[DOTOMP_OUTLINED__EXIT]]
1751 // CHECK3:       .omp_outlined..exit:
1752 // CHECK3-NEXT:    ret i32 0
1753 //
1754 //
1755 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104
1756 // CHECK3-SAME: (i32 noundef [[A:%.*]]) #[[ATTR2]] {
1757 // CHECK3-NEXT:  entry:
1758 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
1759 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
1760 // CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
1761 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
1762 // CHECK3-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 4
1763 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4
1764 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104.omp_outlined, i32 [[TMP1]])
1765 // CHECK3-NEXT:    ret void
1766 //
1767 //
1768 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104.omp_outlined
1769 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] {
1770 // CHECK3-NEXT:  entry:
1771 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
1772 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
1773 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
1774 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
1775 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
1776 // CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
1777 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
1778 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
1779 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 4
1780 // CHECK3-NEXT:    ret void
1781 //
1782 //
1783 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110
1784 // CHECK3-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR2]] {
1785 // CHECK3-NEXT:  entry:
1786 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
1787 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
1788 // CHECK3-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
1789 // CHECK3-NEXT:    [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2
1790 // CHECK3-NEXT:    store i16 [[TMP0]], ptr [[AA_CASTED]], align 2
1791 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[AA_CASTED]], align 4
1792 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.omp_outlined, i32 [[TMP1]])
1793 // CHECK3-NEXT:    ret void
1794 //
1795 //
1796 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.omp_outlined
1797 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {
1798 // CHECK3-NEXT:  entry:
1799 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
1800 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
1801 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
1802 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
1803 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
1804 // CHECK3-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
1805 // CHECK3-NEXT:    [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2
1806 // CHECK3-NEXT:    [[CONV:%.*]] = sext i16 [[TMP0]] to i32
1807 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV]], 1
1808 // CHECK3-NEXT:    [[CONV1:%.*]] = trunc i32 [[ADD]] to i16
1809 // CHECK3-NEXT:    store i16 [[CONV1]], ptr [[AA_ADDR]], align 2
1810 // CHECK3-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
1811 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
1812 // CHECK3-NEXT:    [[TMP3:%.*]] = call i32 @__kmpc_cancel(ptr @[[GLOB1]], i32 [[TMP2]], i32 1)
1813 // CHECK3-NEXT:    [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
1814 // CHECK3-NEXT:    br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
1815 // CHECK3:       .cancel.exit:
1816 // CHECK3-NEXT:    [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(ptr @[[GLOB2:[0-9]+]], i32 [[TMP2]])
1817 // CHECK3-NEXT:    br label [[DOTCANCEL_CONTINUE]]
1818 // CHECK3:       .cancel.continue:
1819 // CHECK3-NEXT:    ret void
1820 //
1821 //
1822 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119
1823 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {
1824 // CHECK3-NEXT:  entry:
1825 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
1826 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
1827 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
1828 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
1829 // CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
1830 // CHECK3-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
1831 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
1832 // CHECK3-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 4
1833 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4
1834 // CHECK3-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2
1835 // CHECK3-NEXT:    store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
1836 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4
1837 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.omp_outlined, i32 [[TMP1]], i32 [[TMP3]])
1838 // CHECK3-NEXT:    ret void
1839 //
1840 //
1841 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.omp_outlined
1842 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {
1843 // CHECK3-NEXT:  entry:
1844 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
1845 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
1846 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
1847 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
1848 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
1849 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
1850 // CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
1851 // CHECK3-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
1852 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
1853 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
1854 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 4
1855 // CHECK3-NEXT:    [[TMP1:%.*]] = load i16, ptr [[AA_ADDR]], align 2
1856 // CHECK3-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
1857 // CHECK3-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
1858 // CHECK3-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
1859 // CHECK3-NEXT:    store i16 [[CONV2]], ptr [[AA_ADDR]], align 2
1860 // CHECK3-NEXT:    ret void
1861 //
1862 //
1863 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144
1864 // CHECK3-SAME: (i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] {
1865 // CHECK3-NEXT:  entry:
1866 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
1867 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
1868 // CHECK3-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
1869 // CHECK3-NEXT:    [[BN_ADDR:%.*]] = alloca ptr, align 4
1870 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
1871 // CHECK3-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
1872 // CHECK3-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
1873 // CHECK3-NEXT:    [[CN_ADDR:%.*]] = alloca ptr, align 4
1874 // CHECK3-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4
1875 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
1876 // CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
1877 // CHECK3-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
1878 // CHECK3-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
1879 // CHECK3-NEXT:    store ptr [[BN]], ptr [[BN_ADDR]], align 4
1880 // CHECK3-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
1881 // CHECK3-NEXT:    store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
1882 // CHECK3-NEXT:    store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4
1883 // CHECK3-NEXT:    store ptr [[CN]], ptr [[CN_ADDR]], align 4
1884 // CHECK3-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4
1885 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
1886 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
1887 // CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4
1888 // CHECK3-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
1889 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
1890 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4
1891 // CHECK3-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4
1892 // CHECK3-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4
1893 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
1894 // CHECK3-NEXT:    store i32 [[TMP8]], ptr [[A_CASTED]], align 4
1895 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4
1896 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.omp_outlined, i32 [[TMP9]], ptr [[TMP0]], i32 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]])
1897 // CHECK3-NEXT:    ret void
1898 //
1899 //
1900 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.omp_outlined
1901 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] {
1902 // CHECK3-NEXT:  entry:
1903 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
1904 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
1905 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
1906 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
1907 // CHECK3-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
1908 // CHECK3-NEXT:    [[BN_ADDR:%.*]] = alloca ptr, align 4
1909 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
1910 // CHECK3-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
1911 // CHECK3-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
1912 // CHECK3-NEXT:    [[CN_ADDR:%.*]] = alloca ptr, align 4
1913 // CHECK3-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4
1914 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
1915 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
1916 // CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
1917 // CHECK3-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
1918 // CHECK3-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
1919 // CHECK3-NEXT:    store ptr [[BN]], ptr [[BN_ADDR]], align 4
1920 // CHECK3-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
1921 // CHECK3-NEXT:    store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
1922 // CHECK3-NEXT:    store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4
1923 // CHECK3-NEXT:    store ptr [[CN]], ptr [[CN_ADDR]], align 4
1924 // CHECK3-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4
1925 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
1926 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
1927 // CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4
1928 // CHECK3-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
1929 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
1930 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4
1931 // CHECK3-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4
1932 // CHECK3-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4
1933 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
1934 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
1935 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 4
1936 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 2
1937 // CHECK3-NEXT:    [[TMP9:%.*]] = load float, ptr [[ARRAYIDX]], align 4
1938 // CHECK3-NEXT:    [[CONV:%.*]] = fpext float [[TMP9]] to double
1939 // CHECK3-NEXT:    [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00
1940 // CHECK3-NEXT:    [[CONV6:%.*]] = fptrunc double [[ADD5]] to float
1941 // CHECK3-NEXT:    store float [[CONV6]], ptr [[ARRAYIDX]], align 4
1942 // CHECK3-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i32 3
1943 // CHECK3-NEXT:    [[TMP10:%.*]] = load float, ptr [[ARRAYIDX7]], align 4
1944 // CHECK3-NEXT:    [[CONV8:%.*]] = fpext float [[TMP10]] to double
1945 // CHECK3-NEXT:    [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00
1946 // CHECK3-NEXT:    [[CONV10:%.*]] = fptrunc double [[ADD9]] to float
1947 // CHECK3-NEXT:    store float [[CONV10]], ptr [[ARRAYIDX7]], align 4
1948 // CHECK3-NEXT:    [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 1
1949 // CHECK3-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX11]], i32 0, i32 2
1950 // CHECK3-NEXT:    [[TMP11:%.*]] = load double, ptr [[ARRAYIDX12]], align 8
1951 // CHECK3-NEXT:    [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00
1952 // CHECK3-NEXT:    store double [[ADD13]], ptr [[ARRAYIDX12]], align 8
1953 // CHECK3-NEXT:    [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]]
1954 // CHECK3-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i32 [[TMP12]]
1955 // CHECK3-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX14]], i32 3
1956 // CHECK3-NEXT:    [[TMP13:%.*]] = load double, ptr [[ARRAYIDX15]], align 8
1957 // CHECK3-NEXT:    [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00
1958 // CHECK3-NEXT:    store double [[ADD16]], ptr [[ARRAYIDX15]], align 8
1959 // CHECK3-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0
1960 // CHECK3-NEXT:    [[TMP14:%.*]] = load i64, ptr [[X]], align 4
1961 // CHECK3-NEXT:    [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1
1962 // CHECK3-NEXT:    store i64 [[ADD17]], ptr [[X]], align 4
1963 // CHECK3-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1
1964 // CHECK3-NEXT:    [[TMP15:%.*]] = load i8, ptr [[Y]], align 4
1965 // CHECK3-NEXT:    [[CONV18:%.*]] = sext i8 [[TMP15]] to i32
1966 // CHECK3-NEXT:    [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1
1967 // CHECK3-NEXT:    [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8
1968 // CHECK3-NEXT:    store i8 [[CONV20]], ptr [[Y]], align 4
1969 // CHECK3-NEXT:    ret void
1970 //
1971 //
1972 // CHECK3-LABEL: define {{[^@]+}}@_Z3bari
1973 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
1974 // CHECK3-NEXT:  entry:
1975 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
1976 // CHECK3-NEXT:    [[A:%.*]] = alloca i32, align 4
1977 // CHECK3-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
1978 // CHECK3-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
1979 // CHECK3-NEXT:    store i32 0, ptr [[A]], align 4
1980 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
1981 // CHECK3-NEXT:    [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]])
1982 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A]], align 4
1983 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
1984 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[A]], align 4
1985 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
1986 // CHECK3-NEXT:    [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]])
1987 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A]], align 4
1988 // CHECK3-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
1989 // CHECK3-NEXT:    store i32 [[ADD2]], ptr [[A]], align 4
1990 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
1991 // CHECK3-NEXT:    [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]])
1992 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[A]], align 4
1993 // CHECK3-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
1994 // CHECK3-NEXT:    store i32 [[ADD4]], ptr [[A]], align 4
1995 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4
1996 // CHECK3-NEXT:    [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]])
1997 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[A]], align 4
1998 // CHECK3-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
1999 // CHECK3-NEXT:    store i32 [[ADD6]], ptr [[A]], align 4
2000 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A]], align 4
2001 // CHECK3-NEXT:    ret i32 [[TMP8]]
2002 //
2003 //
2004 // CHECK3-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
2005 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 {
2006 // CHECK3-NEXT:  entry:
2007 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2008 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
2009 // CHECK3-NEXT:    [[B:%.*]] = alloca i32, align 4
2010 // CHECK3-NEXT:    [[SAVED_STACK:%.*]] = alloca ptr, align 4
2011 // CHECK3-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
2012 // CHECK3-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
2013 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 4
2014 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 4
2015 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 4
2016 // CHECK3-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4
2017 // CHECK3-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
2018 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2019 // CHECK3-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
2020 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2021 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
2022 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
2023 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[B]], align 4
2024 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
2025 // CHECK3-NEXT:    [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
2026 // CHECK3-NEXT:    store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4
2027 // CHECK3-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
2028 // CHECK3-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
2029 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4
2030 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[B]], align 4
2031 // CHECK3-NEXT:    store i32 [[TMP4]], ptr [[B_CASTED]], align 4
2032 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4
2033 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4
2034 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60
2035 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
2036 // CHECK3:       omp_if.then:
2037 // CHECK3-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0
2038 // CHECK3-NEXT:    [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]]
2039 // CHECK3-NEXT:    [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2
2040 // CHECK3-NEXT:    [[TMP9:%.*]] = sext i32 [[TMP8]] to i64
2041 // CHECK3-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes.5, i32 40, i1 false)
2042 // CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2043 // CHECK3-NEXT:    store ptr [[THIS1]], ptr [[TMP10]], align 4
2044 // CHECK3-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2045 // CHECK3-NEXT:    store ptr [[A]], ptr [[TMP11]], align 4
2046 // CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
2047 // CHECK3-NEXT:    store ptr null, ptr [[TMP12]], align 4
2048 // CHECK3-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
2049 // CHECK3-NEXT:    store i32 [[TMP5]], ptr [[TMP13]], align 4
2050 // CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
2051 // CHECK3-NEXT:    store i32 [[TMP5]], ptr [[TMP14]], align 4
2052 // CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
2053 // CHECK3-NEXT:    store ptr null, ptr [[TMP15]], align 4
2054 // CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
2055 // CHECK3-NEXT:    store i32 2, ptr [[TMP16]], align 4
2056 // CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
2057 // CHECK3-NEXT:    store i32 2, ptr [[TMP17]], align 4
2058 // CHECK3-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
2059 // CHECK3-NEXT:    store ptr null, ptr [[TMP18]], align 4
2060 // CHECK3-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
2061 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[TMP19]], align 4
2062 // CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
2063 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[TMP20]], align 4
2064 // CHECK3-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
2065 // CHECK3-NEXT:    store ptr null, ptr [[TMP21]], align 4
2066 // CHECK3-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
2067 // CHECK3-NEXT:    store ptr [[VLA]], ptr [[TMP22]], align 4
2068 // CHECK3-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4
2069 // CHECK3-NEXT:    store ptr [[VLA]], ptr [[TMP23]], align 4
2070 // CHECK3-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 4
2071 // CHECK3-NEXT:    store i64 [[TMP9]], ptr [[TMP24]], align 4
2072 // CHECK3-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
2073 // CHECK3-NEXT:    store ptr null, ptr [[TMP25]], align 4
2074 // CHECK3-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2075 // CHECK3-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2076 // CHECK3-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0
2077 // CHECK3-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
2078 // CHECK3-NEXT:    store i32 2, ptr [[TMP29]], align 4
2079 // CHECK3-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
2080 // CHECK3-NEXT:    store i32 5, ptr [[TMP30]], align 4
2081 // CHECK3-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
2082 // CHECK3-NEXT:    store ptr [[TMP26]], ptr [[TMP31]], align 4
2083 // CHECK3-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
2084 // CHECK3-NEXT:    store ptr [[TMP27]], ptr [[TMP32]], align 4
2085 // CHECK3-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
2086 // CHECK3-NEXT:    store ptr [[TMP28]], ptr [[TMP33]], align 4
2087 // CHECK3-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
2088 // CHECK3-NEXT:    store ptr @.offload_maptypes.6, ptr [[TMP34]], align 4
2089 // CHECK3-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
2090 // CHECK3-NEXT:    store ptr null, ptr [[TMP35]], align 4
2091 // CHECK3-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
2092 // CHECK3-NEXT:    store ptr null, ptr [[TMP36]], align 4
2093 // CHECK3-NEXT:    [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
2094 // CHECK3-NEXT:    store i64 0, ptr [[TMP37]], align 8
2095 // CHECK3-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
2096 // CHECK3-NEXT:    store i64 0, ptr [[TMP38]], align 8
2097 // CHECK3-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
2098 // CHECK3-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP39]], align 4
2099 // CHECK3-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
2100 // CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP40]], align 4
2101 // CHECK3-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
2102 // CHECK3-NEXT:    store i32 0, ptr [[TMP41]], align 4
2103 // CHECK3-NEXT:    [[TMP42:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.region_id, ptr [[KERNEL_ARGS]])
2104 // CHECK3-NEXT:    [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0
2105 // CHECK3-NEXT:    br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
2106 // CHECK3:       omp_offload.failed:
2107 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(ptr [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], ptr [[VLA]]) #[[ATTR3]]
2108 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]
2109 // CHECK3:       omp_offload.cont:
2110 // CHECK3-NEXT:    br label [[OMP_IF_END:%.*]]
2111 // CHECK3:       omp_if.else:
2112 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(ptr [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], ptr [[VLA]]) #[[ATTR3]]
2113 // CHECK3-NEXT:    br label [[OMP_IF_END]]
2114 // CHECK3:       omp_if.end:
2115 // CHECK3-NEXT:    [[TMP44:%.*]] = mul nsw i32 1, [[TMP1]]
2116 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP44]]
2117 // CHECK3-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1
2118 // CHECK3-NEXT:    [[TMP45:%.*]] = load i16, ptr [[ARRAYIDX2]], align 2
2119 // CHECK3-NEXT:    [[CONV:%.*]] = sext i16 [[TMP45]] to i32
2120 // CHECK3-NEXT:    [[TMP46:%.*]] = load i32, ptr [[B]], align 4
2121 // CHECK3-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP46]]
2122 // CHECK3-NEXT:    [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
2123 // CHECK3-NEXT:    call void @llvm.stackrestore.p0(ptr [[TMP47]])
2124 // CHECK3-NEXT:    ret i32 [[ADD3]]
2125 //
2126 //
2127 // CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici
2128 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
2129 // CHECK3-NEXT:  entry:
2130 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
2131 // CHECK3-NEXT:    [[A:%.*]] = alloca i32, align 4
2132 // CHECK3-NEXT:    [[AA:%.*]] = alloca i16, align 2
2133 // CHECK3-NEXT:    [[AAA:%.*]] = alloca i8, align 1
2134 // CHECK3-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
2135 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
2136 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
2137 // CHECK3-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
2138 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 4
2139 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 4
2140 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 4
2141 // CHECK3-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
2142 // CHECK3-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
2143 // CHECK3-NEXT:    store i32 0, ptr [[A]], align 4
2144 // CHECK3-NEXT:    store i16 0, ptr [[AA]], align 2
2145 // CHECK3-NEXT:    store i8 0, ptr [[AAA]], align 1
2146 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A]], align 4
2147 // CHECK3-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 4
2148 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4
2149 // CHECK3-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA]], align 2
2150 // CHECK3-NEXT:    store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
2151 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4
2152 // CHECK3-NEXT:    [[TMP4:%.*]] = load i8, ptr [[AAA]], align 1
2153 // CHECK3-NEXT:    store i8 [[TMP4]], ptr [[AAA_CASTED]], align 1
2154 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[AAA_CASTED]], align 4
2155 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4
2156 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50
2157 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
2158 // CHECK3:       omp_if.then:
2159 // CHECK3-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2160 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[TMP7]], align 4
2161 // CHECK3-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2162 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[TMP8]], align 4
2163 // CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
2164 // CHECK3-NEXT:    store ptr null, ptr [[TMP9]], align 4
2165 // CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
2166 // CHECK3-NEXT:    store i32 [[TMP3]], ptr [[TMP10]], align 4
2167 // CHECK3-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
2168 // CHECK3-NEXT:    store i32 [[TMP3]], ptr [[TMP11]], align 4
2169 // CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
2170 // CHECK3-NEXT:    store ptr null, ptr [[TMP12]], align 4
2171 // CHECK3-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
2172 // CHECK3-NEXT:    store i32 [[TMP5]], ptr [[TMP13]], align 4
2173 // CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
2174 // CHECK3-NEXT:    store i32 [[TMP5]], ptr [[TMP14]], align 4
2175 // CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
2176 // CHECK3-NEXT:    store ptr null, ptr [[TMP15]], align 4
2177 // CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
2178 // CHECK3-NEXT:    store ptr [[B]], ptr [[TMP16]], align 4
2179 // CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
2180 // CHECK3-NEXT:    store ptr [[B]], ptr [[TMP17]], align 4
2181 // CHECK3-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
2182 // CHECK3-NEXT:    store ptr null, ptr [[TMP18]], align 4
2183 // CHECK3-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2184 // CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2185 // CHECK3-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
2186 // CHECK3-NEXT:    store i32 2, ptr [[TMP21]], align 4
2187 // CHECK3-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
2188 // CHECK3-NEXT:    store i32 4, ptr [[TMP22]], align 4
2189 // CHECK3-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
2190 // CHECK3-NEXT:    store ptr [[TMP19]], ptr [[TMP23]], align 4
2191 // CHECK3-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
2192 // CHECK3-NEXT:    store ptr [[TMP20]], ptr [[TMP24]], align 4
2193 // CHECK3-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
2194 // CHECK3-NEXT:    store ptr @.offload_sizes.7, ptr [[TMP25]], align 4
2195 // CHECK3-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
2196 // CHECK3-NEXT:    store ptr @.offload_maptypes.8, ptr [[TMP26]], align 4
2197 // CHECK3-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
2198 // CHECK3-NEXT:    store ptr null, ptr [[TMP27]], align 4
2199 // CHECK3-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
2200 // CHECK3-NEXT:    store ptr null, ptr [[TMP28]], align 4
2201 // CHECK3-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
2202 // CHECK3-NEXT:    store i64 0, ptr [[TMP29]], align 8
2203 // CHECK3-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
2204 // CHECK3-NEXT:    store i64 0, ptr [[TMP30]], align 8
2205 // CHECK3-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
2206 // CHECK3-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP31]], align 4
2207 // CHECK3-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
2208 // CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP32]], align 4
2209 // CHECK3-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
2210 // CHECK3-NEXT:    store i32 0, ptr [[TMP33]], align 4
2211 // CHECK3-NEXT:    [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.region_id, ptr [[KERNEL_ARGS]])
2212 // CHECK3-NEXT:    [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0
2213 // CHECK3-NEXT:    br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
2214 // CHECK3:       omp_offload.failed:
2215 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], ptr [[B]]) #[[ATTR3]]
2216 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]
2217 // CHECK3:       omp_offload.cont:
2218 // CHECK3-NEXT:    br label [[OMP_IF_END:%.*]]
2219 // CHECK3:       omp_if.else:
2220 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], ptr [[B]]) #[[ATTR3]]
2221 // CHECK3-NEXT:    br label [[OMP_IF_END]]
2222 // CHECK3:       omp_if.end:
2223 // CHECK3-NEXT:    [[TMP36:%.*]] = load i32, ptr [[A]], align 4
2224 // CHECK3-NEXT:    ret i32 [[TMP36]]
2225 //
2226 //
2227 // CHECK3-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
2228 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat {
2229 // CHECK3-NEXT:  entry:
2230 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
2231 // CHECK3-NEXT:    [[A:%.*]] = alloca i32, align 4
2232 // CHECK3-NEXT:    [[AA:%.*]] = alloca i16, align 2
2233 // CHECK3-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
2234 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
2235 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
2236 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 4
2237 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 4
2238 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 4
2239 // CHECK3-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
2240 // CHECK3-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
2241 // CHECK3-NEXT:    store i32 0, ptr [[A]], align 4
2242 // CHECK3-NEXT:    store i16 0, ptr [[AA]], align 2
2243 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A]], align 4
2244 // CHECK3-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 4
2245 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4
2246 // CHECK3-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA]], align 2
2247 // CHECK3-NEXT:    store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
2248 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4
2249 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
2250 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
2251 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
2252 // CHECK3:       omp_if.then:
2253 // CHECK3-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2254 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[TMP5]], align 4
2255 // CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2256 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[TMP6]], align 4
2257 // CHECK3-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
2258 // CHECK3-NEXT:    store ptr null, ptr [[TMP7]], align 4
2259 // CHECK3-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
2260 // CHECK3-NEXT:    store i32 [[TMP3]], ptr [[TMP8]], align 4
2261 // CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
2262 // CHECK3-NEXT:    store i32 [[TMP3]], ptr [[TMP9]], align 4
2263 // CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
2264 // CHECK3-NEXT:    store ptr null, ptr [[TMP10]], align 4
2265 // CHECK3-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
2266 // CHECK3-NEXT:    store ptr [[B]], ptr [[TMP11]], align 4
2267 // CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
2268 // CHECK3-NEXT:    store ptr [[B]], ptr [[TMP12]], align 4
2269 // CHECK3-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
2270 // CHECK3-NEXT:    store ptr null, ptr [[TMP13]], align 4
2271 // CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2272 // CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2273 // CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
2274 // CHECK3-NEXT:    store i32 2, ptr [[TMP16]], align 4
2275 // CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
2276 // CHECK3-NEXT:    store i32 3, ptr [[TMP17]], align 4
2277 // CHECK3-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
2278 // CHECK3-NEXT:    store ptr [[TMP14]], ptr [[TMP18]], align 4
2279 // CHECK3-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
2280 // CHECK3-NEXT:    store ptr [[TMP15]], ptr [[TMP19]], align 4
2281 // CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
2282 // CHECK3-NEXT:    store ptr @.offload_sizes.9, ptr [[TMP20]], align 4
2283 // CHECK3-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
2284 // CHECK3-NEXT:    store ptr @.offload_maptypes.10, ptr [[TMP21]], align 4
2285 // CHECK3-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
2286 // CHECK3-NEXT:    store ptr null, ptr [[TMP22]], align 4
2287 // CHECK3-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
2288 // CHECK3-NEXT:    store ptr null, ptr [[TMP23]], align 4
2289 // CHECK3-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
2290 // CHECK3-NEXT:    store i64 0, ptr [[TMP24]], align 8
2291 // CHECK3-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
2292 // CHECK3-NEXT:    store i64 0, ptr [[TMP25]], align 8
2293 // CHECK3-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
2294 // CHECK3-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP26]], align 4
2295 // CHECK3-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
2296 // CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP27]], align 4
2297 // CHECK3-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
2298 // CHECK3-NEXT:    store i32 0, ptr [[TMP28]], align 4
2299 // CHECK3-NEXT:    [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.region_id, ptr [[KERNEL_ARGS]])
2300 // CHECK3-NEXT:    [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
2301 // CHECK3-NEXT:    br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
2302 // CHECK3:       omp_offload.failed:
2303 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR3]]
2304 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]
2305 // CHECK3:       omp_offload.cont:
2306 // CHECK3-NEXT:    br label [[OMP_IF_END:%.*]]
2307 // CHECK3:       omp_if.else:
2308 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR3]]
2309 // CHECK3-NEXT:    br label [[OMP_IF_END]]
2310 // CHECK3:       omp_if.end:
2311 // CHECK3-NEXT:    [[TMP31:%.*]] = load i32, ptr [[A]], align 4
2312 // CHECK3-NEXT:    ret i32 [[TMP31]]
2313 //
2314 //
2315 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216
2316 // CHECK3-SAME: (ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
2317 // CHECK3-NEXT:  entry:
2318 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2319 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
2320 // CHECK3-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
2321 // CHECK3-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
2322 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
2323 // CHECK3-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
2324 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2325 // CHECK3-NEXT:    store i32 [[B]], ptr [[B_ADDR]], align 4
2326 // CHECK3-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
2327 // CHECK3-NEXT:    store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
2328 // CHECK3-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
2329 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2330 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
2331 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
2332 // CHECK3-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
2333 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4
2334 // CHECK3-NEXT:    store i32 [[TMP4]], ptr [[B_CASTED]], align 4
2335 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4
2336 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.omp_outlined, ptr [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], ptr [[TMP3]])
2337 // CHECK3-NEXT:    ret void
2338 //
2339 //
2340 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.omp_outlined
2341 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
2342 // CHECK3-NEXT:  entry:
2343 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
2344 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
2345 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2346 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
2347 // CHECK3-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
2348 // CHECK3-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
2349 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
2350 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
2351 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
2352 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2353 // CHECK3-NEXT:    store i32 [[B]], ptr [[B_ADDR]], align 4
2354 // CHECK3-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
2355 // CHECK3-NEXT:    store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
2356 // CHECK3-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
2357 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2358 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
2359 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
2360 // CHECK3-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
2361 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4
2362 // CHECK3-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP4]] to double
2363 // CHECK3-NEXT:    [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
2364 // CHECK3-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0
2365 // CHECK3-NEXT:    store double [[ADD]], ptr [[A]], align 4
2366 // CHECK3-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0
2367 // CHECK3-NEXT:    [[TMP5:%.*]] = load double, ptr [[A3]], align 4
2368 // CHECK3-NEXT:    [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
2369 // CHECK3-NEXT:    store double [[INC]], ptr [[A3]], align 4
2370 // CHECK3-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
2371 // CHECK3-NEXT:    [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]]
2372 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i32 [[TMP6]]
2373 // CHECK3-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1
2374 // CHECK3-NEXT:    store i16 [[CONV4]], ptr [[ARRAYIDX5]], align 2
2375 // CHECK3-NEXT:    ret void
2376 //
2377 //
2378 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198
2379 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
2380 // CHECK3-NEXT:  entry:
2381 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2382 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
2383 // CHECK3-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
2384 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
2385 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
2386 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
2387 // CHECK3-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
2388 // CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
2389 // CHECK3-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
2390 // CHECK3-NEXT:    store i32 [[AAA]], ptr [[AAA_ADDR]], align 4
2391 // CHECK3-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
2392 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
2393 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
2394 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 4
2395 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4
2396 // CHECK3-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
2397 // CHECK3-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
2398 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4
2399 // CHECK3-NEXT:    [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 1
2400 // CHECK3-NEXT:    store i8 [[TMP5]], ptr [[AAA_CASTED]], align 1
2401 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[AAA_CASTED]], align 4
2402 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], ptr [[TMP0]])
2403 // CHECK3-NEXT:    ret void
2404 //
2405 //
2406 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.omp_outlined
2407 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
2408 // CHECK3-NEXT:  entry:
2409 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
2410 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
2411 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2412 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
2413 // CHECK3-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
2414 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
2415 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
2416 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
2417 // CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
2418 // CHECK3-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
2419 // CHECK3-NEXT:    store i32 [[AAA]], ptr [[AAA_ADDR]], align 4
2420 // CHECK3-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
2421 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
2422 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
2423 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
2424 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 4
2425 // CHECK3-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2
2426 // CHECK3-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i32
2427 // CHECK3-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
2428 // CHECK3-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
2429 // CHECK3-NEXT:    store i16 [[CONV2]], ptr [[AA_ADDR]], align 2
2430 // CHECK3-NEXT:    [[TMP3:%.*]] = load i8, ptr [[AAA_ADDR]], align 1
2431 // CHECK3-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP3]] to i32
2432 // CHECK3-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
2433 // CHECK3-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8
2434 // CHECK3-NEXT:    store i8 [[CONV5]], ptr [[AAA_ADDR]], align 1
2435 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2
2436 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
2437 // CHECK3-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP4]], 1
2438 // CHECK3-NEXT:    store i32 [[ADD6]], ptr [[ARRAYIDX]], align 4
2439 // CHECK3-NEXT:    ret void
2440 //
2441 //
2442 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181
2443 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
2444 // CHECK3-NEXT:  entry:
2445 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2446 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
2447 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
2448 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
2449 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
2450 // CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
2451 // CHECK3-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
2452 // CHECK3-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
2453 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
2454 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
2455 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 4
2456 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4
2457 // CHECK3-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
2458 // CHECK3-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
2459 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4
2460 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], ptr [[TMP0]])
2461 // CHECK3-NEXT:    ret void
2462 //
2463 //
2464 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.omp_outlined
2465 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
2466 // CHECK3-NEXT:  entry:
2467 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
2468 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
2469 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2470 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
2471 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
2472 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
2473 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
2474 // CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
2475 // CHECK3-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
2476 // CHECK3-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
2477 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
2478 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
2479 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
2480 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 4
2481 // CHECK3-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2
2482 // CHECK3-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i32
2483 // CHECK3-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
2484 // CHECK3-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
2485 // CHECK3-NEXT:    store i16 [[CONV2]], ptr [[AA_ADDR]], align 2
2486 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2
2487 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
2488 // CHECK3-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1
2489 // CHECK3-NEXT:    store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4
2490 // CHECK3-NEXT:    ret void
2491 //
2492 //
2493 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
2494 // CHECK3-SAME: () #[[ATTR7:[0-9]+]] {
2495 // CHECK3-NEXT:  entry:
2496 // CHECK3-NEXT:    call void @__tgt_register_requires(i64 1)
2497 // CHECK3-NEXT:    ret void
2498 //
2499 //
2500 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100
2501 // CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
2502 // CHECK9-NEXT:  entry:
2503 // CHECK9-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
2504 // CHECK9-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
2505 // CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.omp_outlined)
2506 // CHECK9-NEXT:    ret void
2507 //
2508 //
2509 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.omp_outlined
2510 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
2511 // CHECK9-NEXT:  entry:
2512 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
2513 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
2514 // CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
2515 // CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
2516 // CHECK9-NEXT:    ret void
2517 //
2518 //
2519 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110
2520 // CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {
2521 // CHECK9-NEXT:  entry:
2522 // CHECK9-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
2523 // CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
2524 // CHECK9-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
2525 // CHECK9-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
2526 // CHECK9-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
2527 // CHECK9-NEXT:    [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2
2528 // CHECK9-NEXT:    store i16 [[TMP0]], ptr [[AA_CASTED]], align 2
2529 // CHECK9-NEXT:    [[TMP1:%.*]] = load i64, ptr [[AA_CASTED]], align 8
2530 // CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.omp_outlined, i64 [[TMP1]])
2531 // CHECK9-NEXT:    ret void
2532 //
2533 //
2534 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.omp_outlined
2535 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {
2536 // CHECK9-NEXT:  entry:
2537 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
2538 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
2539 // CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
2540 // CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
2541 // CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
2542 // CHECK9-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
2543 // CHECK9-NEXT:    [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2
2544 // CHECK9-NEXT:    [[CONV:%.*]] = sext i16 [[TMP0]] to i32
2545 // CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV]], 1
2546 // CHECK9-NEXT:    [[CONV1:%.*]] = trunc i32 [[ADD]] to i16
2547 // CHECK9-NEXT:    store i16 [[CONV1]], ptr [[AA_ADDR]], align 2
2548 // CHECK9-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
2549 // CHECK9-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
2550 // CHECK9-NEXT:    [[TMP3:%.*]] = call i32 @__kmpc_cancel(ptr @[[GLOB1]], i32 [[TMP2]], i32 1)
2551 // CHECK9-NEXT:    [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
2552 // CHECK9-NEXT:    br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
2553 // CHECK9:       .cancel.exit:
2554 // CHECK9-NEXT:    [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(ptr @[[GLOB2:[0-9]+]], i32 [[TMP2]])
2555 // CHECK9-NEXT:    br label [[DOTCANCEL_CONTINUE]]
2556 // CHECK9:       .cancel.continue:
2557 // CHECK9-NEXT:    ret void
2558 //
2559 //
2560 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119
2561 // CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {
2562 // CHECK9-NEXT:  entry:
2563 // CHECK9-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
2564 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
2565 // CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
2566 // CHECK9-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
2567 // CHECK9-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
2568 // CHECK9-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
2569 // CHECK9-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
2570 // CHECK9-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
2571 // CHECK9-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
2572 // CHECK9-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 4
2573 // CHECK9-NEXT:    [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8
2574 // CHECK9-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2
2575 // CHECK9-NEXT:    store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
2576 // CHECK9-NEXT:    [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8
2577 // CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.omp_outlined, i64 [[TMP1]], i64 [[TMP3]])
2578 // CHECK9-NEXT:    ret void
2579 //
2580 //
2581 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.omp_outlined
2582 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {
2583 // CHECK9-NEXT:  entry:
2584 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
2585 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
2586 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
2587 // CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
2588 // CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
2589 // CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
2590 // CHECK9-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
2591 // CHECK9-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
2592 // CHECK9-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
2593 // CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
2594 // CHECK9-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 4
2595 // CHECK9-NEXT:    [[TMP1:%.*]] = load i16, ptr [[AA_ADDR]], align 2
2596 // CHECK9-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
2597 // CHECK9-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
2598 // CHECK9-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
2599 // CHECK9-NEXT:    store i16 [[CONV2]], ptr [[AA_ADDR]], align 2
2600 // CHECK9-NEXT:    ret void
2601 //
2602 //
2603 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144
2604 // CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] {
2605 // CHECK9-NEXT:  entry:
2606 // CHECK9-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
2607 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
2608 // CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
2609 // CHECK9-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
2610 // CHECK9-NEXT:    [[BN_ADDR:%.*]] = alloca ptr, align 8
2611 // CHECK9-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
2612 // CHECK9-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
2613 // CHECK9-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
2614 // CHECK9-NEXT:    [[CN_ADDR:%.*]] = alloca ptr, align 8
2615 // CHECK9-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
2616 // CHECK9-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
2617 // CHECK9-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
2618 // CHECK9-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
2619 // CHECK9-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
2620 // CHECK9-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
2621 // CHECK9-NEXT:    store ptr [[BN]], ptr [[BN_ADDR]], align 8
2622 // CHECK9-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
2623 // CHECK9-NEXT:    store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
2624 // CHECK9-NEXT:    store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8
2625 // CHECK9-NEXT:    store ptr [[CN]], ptr [[CN_ADDR]], align 8
2626 // CHECK9-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
2627 // CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
2628 // CHECK9-NEXT:    [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
2629 // CHECK9-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8
2630 // CHECK9-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
2631 // CHECK9-NEXT:    [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
2632 // CHECK9-NEXT:    [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8
2633 // CHECK9-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8
2634 // CHECK9-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8
2635 // CHECK9-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
2636 // CHECK9-NEXT:    store i32 [[TMP8]], ptr [[A_CASTED]], align 4
2637 // CHECK9-NEXT:    [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 8
2638 // CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.omp_outlined, i64 [[TMP9]], ptr [[TMP0]], i64 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]])
2639 // CHECK9-NEXT:    ret void
2640 //
2641 //
2642 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.omp_outlined
2643 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] {
2644 // CHECK9-NEXT:  entry:
2645 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
2646 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
2647 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
2648 // CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
2649 // CHECK9-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
2650 // CHECK9-NEXT:    [[BN_ADDR:%.*]] = alloca ptr, align 8
2651 // CHECK9-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
2652 // CHECK9-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
2653 // CHECK9-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
2654 // CHECK9-NEXT:    [[CN_ADDR:%.*]] = alloca ptr, align 8
2655 // CHECK9-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
2656 // CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
2657 // CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
2658 // CHECK9-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
2659 // CHECK9-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
2660 // CHECK9-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
2661 // CHECK9-NEXT:    store ptr [[BN]], ptr [[BN_ADDR]], align 8
2662 // CHECK9-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
2663 // CHECK9-NEXT:    store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
2664 // CHECK9-NEXT:    store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8
2665 // CHECK9-NEXT:    store ptr [[CN]], ptr [[CN_ADDR]], align 8
2666 // CHECK9-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
2667 // CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
2668 // CHECK9-NEXT:    [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
2669 // CHECK9-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8
2670 // CHECK9-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
2671 // CHECK9-NEXT:    [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
2672 // CHECK9-NEXT:    [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8
2673 // CHECK9-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8
2674 // CHECK9-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8
2675 // CHECK9-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
2676 // CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
2677 // CHECK9-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 4
2678 // CHECK9-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 2
2679 // CHECK9-NEXT:    [[TMP9:%.*]] = load float, ptr [[ARRAYIDX]], align 4
2680 // CHECK9-NEXT:    [[CONV:%.*]] = fpext float [[TMP9]] to double
2681 // CHECK9-NEXT:    [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00
2682 // CHECK9-NEXT:    [[CONV6:%.*]] = fptrunc double [[ADD5]] to float
2683 // CHECK9-NEXT:    store float [[CONV6]], ptr [[ARRAYIDX]], align 4
2684 // CHECK9-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 3
2685 // CHECK9-NEXT:    [[TMP10:%.*]] = load float, ptr [[ARRAYIDX7]], align 4
2686 // CHECK9-NEXT:    [[CONV8:%.*]] = fpext float [[TMP10]] to double
2687 // CHECK9-NEXT:    [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00
2688 // CHECK9-NEXT:    [[CONV10:%.*]] = fptrunc double [[ADD9]] to float
2689 // CHECK9-NEXT:    store float [[CONV10]], ptr [[ARRAYIDX7]], align 4
2690 // CHECK9-NEXT:    [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 1
2691 // CHECK9-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX11]], i64 0, i64 2
2692 // CHECK9-NEXT:    [[TMP11:%.*]] = load double, ptr [[ARRAYIDX12]], align 8
2693 // CHECK9-NEXT:    [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00
2694 // CHECK9-NEXT:    store double [[ADD13]], ptr [[ARRAYIDX12]], align 8
2695 // CHECK9-NEXT:    [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]]
2696 // CHECK9-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i64 [[TMP12]]
2697 // CHECK9-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX14]], i64 3
2698 // CHECK9-NEXT:    [[TMP13:%.*]] = load double, ptr [[ARRAYIDX15]], align 8
2699 // CHECK9-NEXT:    [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00
2700 // CHECK9-NEXT:    store double [[ADD16]], ptr [[ARRAYIDX15]], align 8
2701 // CHECK9-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0
2702 // CHECK9-NEXT:    [[TMP14:%.*]] = load i64, ptr [[X]], align 8
2703 // CHECK9-NEXT:    [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1
2704 // CHECK9-NEXT:    store i64 [[ADD17]], ptr [[X]], align 8
2705 // CHECK9-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1
2706 // CHECK9-NEXT:    [[TMP15:%.*]] = load i8, ptr [[Y]], align 8
2707 // CHECK9-NEXT:    [[CONV18:%.*]] = sext i8 [[TMP15]] to i32
2708 // CHECK9-NEXT:    [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1
2709 // CHECK9-NEXT:    [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8
2710 // CHECK9-NEXT:    store i8 [[CONV20]], ptr [[Y]], align 8
2711 // CHECK9-NEXT:    ret void
2712 //
2713 //
2714 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198
2715 // CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
2716 // CHECK9-NEXT:  entry:
2717 // CHECK9-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
2718 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
2719 // CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
2720 // CHECK9-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
2721 // CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
2722 // CHECK9-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
2723 // CHECK9-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
2724 // CHECK9-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
2725 // CHECK9-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
2726 // CHECK9-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
2727 // CHECK9-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
2728 // CHECK9-NEXT:    store i64 [[AAA]], ptr [[AAA_ADDR]], align 8
2729 // CHECK9-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
2730 // CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
2731 // CHECK9-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
2732 // CHECK9-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 4
2733 // CHECK9-NEXT:    [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8
2734 // CHECK9-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
2735 // CHECK9-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
2736 // CHECK9-NEXT:    [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8
2737 // CHECK9-NEXT:    [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 1
2738 // CHECK9-NEXT:    store i8 [[TMP5]], ptr [[AAA_CASTED]], align 1
2739 // CHECK9-NEXT:    [[TMP6:%.*]] = load i64, ptr [[AAA_CASTED]], align 8
2740 // CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], ptr [[TMP0]])
2741 // CHECK9-NEXT:    ret void
2742 //
2743 //
2744 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.omp_outlined
2745 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
2746 // CHECK9-NEXT:  entry:
2747 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
2748 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
2749 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
2750 // CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
2751 // CHECK9-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
2752 // CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
2753 // CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
2754 // CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
2755 // CHECK9-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
2756 // CHECK9-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
2757 // CHECK9-NEXT:    store i64 [[AAA]], ptr [[AAA_ADDR]], align 8
2758 // CHECK9-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
2759 // CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
2760 // CHECK9-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
2761 // CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
2762 // CHECK9-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 4
2763 // CHECK9-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2
2764 // CHECK9-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i32
2765 // CHECK9-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
2766 // CHECK9-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
2767 // CHECK9-NEXT:    store i16 [[CONV2]], ptr [[AA_ADDR]], align 2
2768 // CHECK9-NEXT:    [[TMP3:%.*]] = load i8, ptr [[AAA_ADDR]], align 1
2769 // CHECK9-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP3]] to i32
2770 // CHECK9-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
2771 // CHECK9-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8
2772 // CHECK9-NEXT:    store i8 [[CONV5]], ptr [[AAA_ADDR]], align 1
2773 // CHECK9-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2
2774 // CHECK9-NEXT:    [[TMP4:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
2775 // CHECK9-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP4]], 1
2776 // CHECK9-NEXT:    store i32 [[ADD6]], ptr [[ARRAYIDX]], align 4
2777 // CHECK9-NEXT:    ret void
2778 //
2779 //
2780 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216
2781 // CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
2782 // CHECK9-NEXT:  entry:
2783 // CHECK9-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
2784 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2785 // CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
2786 // CHECK9-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
2787 // CHECK9-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
2788 // CHECK9-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
2789 // CHECK9-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
2790 // CHECK9-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
2791 // CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2792 // CHECK9-NEXT:    store i64 [[B]], ptr [[B_ADDR]], align 8
2793 // CHECK9-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
2794 // CHECK9-NEXT:    store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
2795 // CHECK9-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
2796 // CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2797 // CHECK9-NEXT:    [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
2798 // CHECK9-NEXT:    [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
2799 // CHECK9-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
2800 // CHECK9-NEXT:    [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4
2801 // CHECK9-NEXT:    store i32 [[TMP4]], ptr [[B_CASTED]], align 4
2802 // CHECK9-NEXT:    [[TMP5:%.*]] = load i64, ptr [[B_CASTED]], align 8
2803 // CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.omp_outlined, ptr [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], ptr [[TMP3]])
2804 // CHECK9-NEXT:    ret void
2805 //
2806 //
2807 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.omp_outlined
2808 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
2809 // CHECK9-NEXT:  entry:
2810 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
2811 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
2812 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2813 // CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
2814 // CHECK9-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
2815 // CHECK9-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
2816 // CHECK9-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
2817 // CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
2818 // CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
2819 // CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2820 // CHECK9-NEXT:    store i64 [[B]], ptr [[B_ADDR]], align 8
2821 // CHECK9-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
2822 // CHECK9-NEXT:    store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
2823 // CHECK9-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
2824 // CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2825 // CHECK9-NEXT:    [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
2826 // CHECK9-NEXT:    [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
2827 // CHECK9-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
2828 // CHECK9-NEXT:    [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4
2829 // CHECK9-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP4]] to double
2830 // CHECK9-NEXT:    [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
2831 // CHECK9-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0
2832 // CHECK9-NEXT:    store double [[ADD]], ptr [[A]], align 8
2833 // CHECK9-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0
2834 // CHECK9-NEXT:    [[TMP5:%.*]] = load double, ptr [[A3]], align 8
2835 // CHECK9-NEXT:    [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
2836 // CHECK9-NEXT:    store double [[INC]], ptr [[A3]], align 8
2837 // CHECK9-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
2838 // CHECK9-NEXT:    [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]]
2839 // CHECK9-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i64 [[TMP6]]
2840 // CHECK9-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1
2841 // CHECK9-NEXT:    store i16 [[CONV4]], ptr [[ARRAYIDX5]], align 2
2842 // CHECK9-NEXT:    ret void
2843 //
2844 //
2845 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181
2846 // CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
2847 // CHECK9-NEXT:  entry:
2848 // CHECK9-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
2849 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
2850 // CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
2851 // CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
2852 // CHECK9-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
2853 // CHECK9-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
2854 // CHECK9-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
2855 // CHECK9-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
2856 // CHECK9-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
2857 // CHECK9-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
2858 // CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
2859 // CHECK9-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
2860 // CHECK9-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 4
2861 // CHECK9-NEXT:    [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8
2862 // CHECK9-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
2863 // CHECK9-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
2864 // CHECK9-NEXT:    [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8
2865 // CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], ptr [[TMP0]])
2866 // CHECK9-NEXT:    ret void
2867 //
2868 //
2869 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.omp_outlined
2870 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
2871 // CHECK9-NEXT:  entry:
2872 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
2873 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
2874 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
2875 // CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
2876 // CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
2877 // CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
2878 // CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
2879 // CHECK9-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
2880 // CHECK9-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
2881 // CHECK9-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
2882 // CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
2883 // CHECK9-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
2884 // CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
2885 // CHECK9-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 4
2886 // CHECK9-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2
2887 // CHECK9-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i32
2888 // CHECK9-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
2889 // CHECK9-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
2890 // CHECK9-NEXT:    store i16 [[CONV2]], ptr [[AA_ADDR]], align 2
2891 // CHECK9-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2
2892 // CHECK9-NEXT:    [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
2893 // CHECK9-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1
2894 // CHECK9-NEXT:    store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4
2895 // CHECK9-NEXT:    ret void
2896 //
2897 //
2898 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100
2899 // CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
2900 // CHECK11-NEXT:  entry:
2901 // CHECK11-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
2902 // CHECK11-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
2903 // CHECK11-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.omp_outlined)
2904 // CHECK11-NEXT:    ret void
2905 //
2906 //
2907 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.omp_outlined
2908 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
2909 // CHECK11-NEXT:  entry:
2910 // CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
2911 // CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
2912 // CHECK11-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
2913 // CHECK11-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
2914 // CHECK11-NEXT:    ret void
2915 //
2916 //
2917 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110
2918 // CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {
2919 // CHECK11-NEXT:  entry:
2920 // CHECK11-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
2921 // CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
2922 // CHECK11-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
2923 // CHECK11-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
2924 // CHECK11-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
2925 // CHECK11-NEXT:    [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2
2926 // CHECK11-NEXT:    store i16 [[TMP0]], ptr [[AA_CASTED]], align 2
2927 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[AA_CASTED]], align 4
2928 // CHECK11-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.omp_outlined, i32 [[TMP1]])
2929 // CHECK11-NEXT:    ret void
2930 //
2931 //
2932 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.omp_outlined
2933 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {
2934 // CHECK11-NEXT:  entry:
2935 // CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
2936 // CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
2937 // CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
2938 // CHECK11-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
2939 // CHECK11-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
2940 // CHECK11-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
2941 // CHECK11-NEXT:    [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2
2942 // CHECK11-NEXT:    [[CONV:%.*]] = sext i16 [[TMP0]] to i32
2943 // CHECK11-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV]], 1
2944 // CHECK11-NEXT:    [[CONV1:%.*]] = trunc i32 [[ADD]] to i16
2945 // CHECK11-NEXT:    store i16 [[CONV1]], ptr [[AA_ADDR]], align 2
2946 // CHECK11-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
2947 // CHECK11-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
2948 // CHECK11-NEXT:    [[TMP3:%.*]] = call i32 @__kmpc_cancel(ptr @[[GLOB1]], i32 [[TMP2]], i32 1)
2949 // CHECK11-NEXT:    [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
2950 // CHECK11-NEXT:    br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
2951 // CHECK11:       .cancel.exit:
2952 // CHECK11-NEXT:    [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(ptr @[[GLOB2:[0-9]+]], i32 [[TMP2]])
2953 // CHECK11-NEXT:    br label [[DOTCANCEL_CONTINUE]]
2954 // CHECK11:       .cancel.continue:
2955 // CHECK11-NEXT:    ret void
2956 //
2957 //
2958 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119
2959 // CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {
2960 // CHECK11-NEXT:  entry:
2961 // CHECK11-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
2962 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2963 // CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
2964 // CHECK11-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
2965 // CHECK11-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
2966 // CHECK11-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
2967 // CHECK11-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
2968 // CHECK11-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
2969 // CHECK11-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
2970 // CHECK11-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 4
2971 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4
2972 // CHECK11-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2
2973 // CHECK11-NEXT:    store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
2974 // CHECK11-NEXT:    [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4
2975 // CHECK11-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.omp_outlined, i32 [[TMP1]], i32 [[TMP3]])
2976 // CHECK11-NEXT:    ret void
2977 //
2978 //
2979 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.omp_outlined
2980 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {
2981 // CHECK11-NEXT:  entry:
2982 // CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
2983 // CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
2984 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2985 // CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
2986 // CHECK11-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
2987 // CHECK11-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
2988 // CHECK11-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
2989 // CHECK11-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
2990 // CHECK11-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
2991 // CHECK11-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
2992 // CHECK11-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 4
2993 // CHECK11-NEXT:    [[TMP1:%.*]] = load i16, ptr [[AA_ADDR]], align 2
2994 // CHECK11-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
2995 // CHECK11-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
2996 // CHECK11-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
2997 // CHECK11-NEXT:    store i16 [[CONV2]], ptr [[AA_ADDR]], align 2
2998 // CHECK11-NEXT:    ret void
2999 //
3000 //
3001 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144
3002 // CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] {
3003 // CHECK11-NEXT:  entry:
3004 // CHECK11-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
3005 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
3006 // CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
3007 // CHECK11-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
3008 // CHECK11-NEXT:    [[BN_ADDR:%.*]] = alloca ptr, align 4
3009 // CHECK11-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
3010 // CHECK11-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
3011 // CHECK11-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
3012 // CHECK11-NEXT:    [[CN_ADDR:%.*]] = alloca ptr, align 4
3013 // CHECK11-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4
3014 // CHECK11-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
3015 // CHECK11-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
3016 // CHECK11-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
3017 // CHECK11-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
3018 // CHECK11-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
3019 // CHECK11-NEXT:    store ptr [[BN]], ptr [[BN_ADDR]], align 4
3020 // CHECK11-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
3021 // CHECK11-NEXT:    store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
3022 // CHECK11-NEXT:    store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4
3023 // CHECK11-NEXT:    store ptr [[CN]], ptr [[CN_ADDR]], align 4
3024 // CHECK11-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4
3025 // CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
3026 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
3027 // CHECK11-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4
3028 // CHECK11-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
3029 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
3030 // CHECK11-NEXT:    [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4
3031 // CHECK11-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4
3032 // CHECK11-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4
3033 // CHECK11-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
3034 // CHECK11-NEXT:    store i32 [[TMP8]], ptr [[A_CASTED]], align 4
3035 // CHECK11-NEXT:    [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4
3036 // CHECK11-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.omp_outlined, i32 [[TMP9]], ptr [[TMP0]], i32 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]])
3037 // CHECK11-NEXT:    ret void
3038 //
3039 //
3040 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.omp_outlined
3041 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] {
3042 // CHECK11-NEXT:  entry:
3043 // CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
3044 // CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
3045 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
3046 // CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
3047 // CHECK11-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
3048 // CHECK11-NEXT:    [[BN_ADDR:%.*]] = alloca ptr, align 4
3049 // CHECK11-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
3050 // CHECK11-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
3051 // CHECK11-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
3052 // CHECK11-NEXT:    [[CN_ADDR:%.*]] = alloca ptr, align 4
3053 // CHECK11-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4
3054 // CHECK11-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
3055 // CHECK11-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
3056 // CHECK11-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
3057 // CHECK11-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
3058 // CHECK11-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
3059 // CHECK11-NEXT:    store ptr [[BN]], ptr [[BN_ADDR]], align 4
3060 // CHECK11-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
3061 // CHECK11-NEXT:    store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
3062 // CHECK11-NEXT:    store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4
3063 // CHECK11-NEXT:    store ptr [[CN]], ptr [[CN_ADDR]], align 4
3064 // CHECK11-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4
3065 // CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
3066 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
3067 // CHECK11-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4
3068 // CHECK11-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
3069 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
3070 // CHECK11-NEXT:    [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4
3071 // CHECK11-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4
3072 // CHECK11-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4
3073 // CHECK11-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
3074 // CHECK11-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
3075 // CHECK11-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 4
3076 // CHECK11-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 2
3077 // CHECK11-NEXT:    [[TMP9:%.*]] = load float, ptr [[ARRAYIDX]], align 4
3078 // CHECK11-NEXT:    [[CONV:%.*]] = fpext float [[TMP9]] to double
3079 // CHECK11-NEXT:    [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00
3080 // CHECK11-NEXT:    [[CONV6:%.*]] = fptrunc double [[ADD5]] to float
3081 // CHECK11-NEXT:    store float [[CONV6]], ptr [[ARRAYIDX]], align 4
3082 // CHECK11-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i32 3
3083 // CHECK11-NEXT:    [[TMP10:%.*]] = load float, ptr [[ARRAYIDX7]], align 4
3084 // CHECK11-NEXT:    [[CONV8:%.*]] = fpext float [[TMP10]] to double
3085 // CHECK11-NEXT:    [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00
3086 // CHECK11-NEXT:    [[CONV10:%.*]] = fptrunc double [[ADD9]] to float
3087 // CHECK11-NEXT:    store float [[CONV10]], ptr [[ARRAYIDX7]], align 4
3088 // CHECK11-NEXT:    [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 1
3089 // CHECK11-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX11]], i32 0, i32 2
3090 // CHECK11-NEXT:    [[TMP11:%.*]] = load double, ptr [[ARRAYIDX12]], align 8
3091 // CHECK11-NEXT:    [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00
3092 // CHECK11-NEXT:    store double [[ADD13]], ptr [[ARRAYIDX12]], align 8
3093 // CHECK11-NEXT:    [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]]
3094 // CHECK11-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i32 [[TMP12]]
3095 // CHECK11-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX14]], i32 3
3096 // CHECK11-NEXT:    [[TMP13:%.*]] = load double, ptr [[ARRAYIDX15]], align 8
3097 // CHECK11-NEXT:    [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00
3098 // CHECK11-NEXT:    store double [[ADD16]], ptr [[ARRAYIDX15]], align 8
3099 // CHECK11-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0
3100 // CHECK11-NEXT:    [[TMP14:%.*]] = load i64, ptr [[X]], align 4
3101 // CHECK11-NEXT:    [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1
3102 // CHECK11-NEXT:    store i64 [[ADD17]], ptr [[X]], align 4
3103 // CHECK11-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1
3104 // CHECK11-NEXT:    [[TMP15:%.*]] = load i8, ptr [[Y]], align 4
3105 // CHECK11-NEXT:    [[CONV18:%.*]] = sext i8 [[TMP15]] to i32
3106 // CHECK11-NEXT:    [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1
3107 // CHECK11-NEXT:    [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8
3108 // CHECK11-NEXT:    store i8 [[CONV20]], ptr [[Y]], align 4
3109 // CHECK11-NEXT:    ret void
3110 //
3111 //
3112 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198
3113 // CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
3114 // CHECK11-NEXT:  entry:
3115 // CHECK11-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
3116 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
3117 // CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
3118 // CHECK11-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
3119 // CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
3120 // CHECK11-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
3121 // CHECK11-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
3122 // CHECK11-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
3123 // CHECK11-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
3124 // CHECK11-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
3125 // CHECK11-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
3126 // CHECK11-NEXT:    store i32 [[AAA]], ptr [[AAA_ADDR]], align 4
3127 // CHECK11-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
3128 // CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
3129 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
3130 // CHECK11-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 4
3131 // CHECK11-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4
3132 // CHECK11-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
3133 // CHECK11-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
3134 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4
3135 // CHECK11-NEXT:    [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 1
3136 // CHECK11-NEXT:    store i8 [[TMP5]], ptr [[AAA_CASTED]], align 1
3137 // CHECK11-NEXT:    [[TMP6:%.*]] = load i32, ptr [[AAA_CASTED]], align 4
3138 // CHECK11-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], ptr [[TMP0]])
3139 // CHECK11-NEXT:    ret void
3140 //
3141 //
3142 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.omp_outlined
3143 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
3144 // CHECK11-NEXT:  entry:
3145 // CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
3146 // CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
3147 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
3148 // CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
3149 // CHECK11-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
3150 // CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
3151 // CHECK11-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
3152 // CHECK11-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
3153 // CHECK11-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
3154 // CHECK11-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
3155 // CHECK11-NEXT:    store i32 [[AAA]], ptr [[AAA_ADDR]], align 4
3156 // CHECK11-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
3157 // CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
3158 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
3159 // CHECK11-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
3160 // CHECK11-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 4
3161 // CHECK11-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2
3162 // CHECK11-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i32
3163 // CHECK11-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
3164 // CHECK11-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
3165 // CHECK11-NEXT:    store i16 [[CONV2]], ptr [[AA_ADDR]], align 2
3166 // CHECK11-NEXT:    [[TMP3:%.*]] = load i8, ptr [[AAA_ADDR]], align 1
3167 // CHECK11-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP3]] to i32
3168 // CHECK11-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
3169 // CHECK11-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8
3170 // CHECK11-NEXT:    store i8 [[CONV5]], ptr [[AAA_ADDR]], align 1
3171 // CHECK11-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2
3172 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
3173 // CHECK11-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP4]], 1
3174 // CHECK11-NEXT:    store i32 [[ADD6]], ptr [[ARRAYIDX]], align 4
3175 // CHECK11-NEXT:    ret void
3176 //
3177 //
3178 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216
3179 // CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
3180 // CHECK11-NEXT:  entry:
3181 // CHECK11-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
3182 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
3183 // CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
3184 // CHECK11-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
3185 // CHECK11-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
3186 // CHECK11-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
3187 // CHECK11-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
3188 // CHECK11-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
3189 // CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
3190 // CHECK11-NEXT:    store i32 [[B]], ptr [[B_ADDR]], align 4
3191 // CHECK11-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
3192 // CHECK11-NEXT:    store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
3193 // CHECK11-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
3194 // CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
3195 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
3196 // CHECK11-NEXT:    [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
3197 // CHECK11-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
3198 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4
3199 // CHECK11-NEXT:    store i32 [[TMP4]], ptr [[B_CASTED]], align 4
3200 // CHECK11-NEXT:    [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4
3201 // CHECK11-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.omp_outlined, ptr [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], ptr [[TMP3]])
3202 // CHECK11-NEXT:    ret void
3203 //
3204 //
3205 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.omp_outlined
3206 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
3207 // CHECK11-NEXT:  entry:
3208 // CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
3209 // CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
3210 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
3211 // CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
3212 // CHECK11-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
3213 // CHECK11-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
3214 // CHECK11-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
3215 // CHECK11-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
3216 // CHECK11-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
3217 // CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
3218 // CHECK11-NEXT:    store i32 [[B]], ptr [[B_ADDR]], align 4
3219 // CHECK11-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
3220 // CHECK11-NEXT:    store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
3221 // CHECK11-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
3222 // CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
3223 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
3224 // CHECK11-NEXT:    [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
3225 // CHECK11-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
3226 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4
3227 // CHECK11-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP4]] to double
3228 // CHECK11-NEXT:    [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
3229 // CHECK11-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0
3230 // CHECK11-NEXT:    store double [[ADD]], ptr [[A]], align 4
3231 // CHECK11-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0
3232 // CHECK11-NEXT:    [[TMP5:%.*]] = load double, ptr [[A3]], align 4
3233 // CHECK11-NEXT:    [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
3234 // CHECK11-NEXT:    store double [[INC]], ptr [[A3]], align 4
3235 // CHECK11-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
3236 // CHECK11-NEXT:    [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]]
3237 // CHECK11-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i32 [[TMP6]]
3238 // CHECK11-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1
3239 // CHECK11-NEXT:    store i16 [[CONV4]], ptr [[ARRAYIDX5]], align 2
3240 // CHECK11-NEXT:    ret void
3241 //
3242 //
3243 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181
3244 // CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
3245 // CHECK11-NEXT:  entry:
3246 // CHECK11-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
3247 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
3248 // CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
3249 // CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
3250 // CHECK11-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
3251 // CHECK11-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
3252 // CHECK11-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
3253 // CHECK11-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
3254 // CHECK11-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
3255 // CHECK11-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
3256 // CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
3257 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
3258 // CHECK11-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 4
3259 // CHECK11-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4
3260 // CHECK11-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
3261 // CHECK11-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
3262 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4
3263 // CHECK11-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], ptr [[TMP0]])
3264 // CHECK11-NEXT:    ret void
3265 //
3266 //
3267 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.omp_outlined
3268 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
3269 // CHECK11-NEXT:  entry:
3270 // CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
3271 // CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
3272 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
3273 // CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
3274 // CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
3275 // CHECK11-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
3276 // CHECK11-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
3277 // CHECK11-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
3278 // CHECK11-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
3279 // CHECK11-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
3280 // CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
3281 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
3282 // CHECK11-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
3283 // CHECK11-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 4
3284 // CHECK11-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2
3285 // CHECK11-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i32
3286 // CHECK11-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
3287 // CHECK11-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
3288 // CHECK11-NEXT:    store i16 [[CONV2]], ptr [[AA_ADDR]], align 2
3289 // CHECK11-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2
3290 // CHECK11-NEXT:    [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
3291 // CHECK11-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1
3292 // CHECK11-NEXT:    store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4
3293 // CHECK11-NEXT:    ret void
3294 //