clang/test/OpenMP/target_parallel_for_codegen.cpp

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
   2 // Test host codegen.
   3 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK1
   4 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
   5 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK1
   6 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK3
   7 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
   8 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK3
   9
  10 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  11 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
  12 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  13 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  14 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
  15 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  16
  17 // Test target codegen - host bc file has to be created first.
  18 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
  19 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK9
  20 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
  21 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK9
  22 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
  23 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK11
  24 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
  25 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK11
  26
  27 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
  28 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  29 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
  30 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  31 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
  32 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  33 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
  34 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  35
  36 // Test host codegen.
  37 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK17
  38 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
  39 // RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK17
  40 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK19
  41 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
  42 // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK19
  43
  44 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  45 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
  46 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  47 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  48 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
  49 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  50
  51 // Test target codegen - host bc file has to be created first.
  52 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
  53 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK9
  54 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
  55 // RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK9
  56 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
  57 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK11
  58 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
  59 // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK11
  60
  61 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
  62 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  63 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
  64 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  65 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
  66 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  67 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
  68 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  69
  70 // expected-no-diagnostics
  71 #ifndef HEADER
  72 #define HEADER
  73
  74
  75
  76
  77 // We have 8 target regions, but only 7 that actually will generate offloading
  78 // code, only 6 will have mapped arguments, and only 4 have all-constant map
  79 // sizes.
  80
  81
  82
  83 // Check target registration is registered as a Ctor.
  84
  85
  86 template<typename tx, typename ty>
  87 struct TT{
  88   tx X;
  89   ty Y;
  90 };
  91
  92 long long get_val() { return 0; }
  93
  94 int foo(int n) {
  95   int a = 0;
  96   short aa = 0;
  97   float b[10];
  98   float bn[n];
  99   double c[5][10];
 100   double cn[5][n];
 101   TT<long long, char> d;
 102
 103   #pragma omp target parallel for
 104   for (int i = 3; i < 32; i += 5) {
 105 #pragma omp cancel for
 106 #pragma omp cancellation point for
 107   }
 108
 109   long long k = get_val();
 110   #pragma omp target parallel for if(target: 0) linear(k : 3) schedule(dynamic)
 111   for (int i = 10; i > 1; i--) {
 112     a += 1;
 113   }
 114
 115   // CHECK-32:    [[FPSIZEGEP]] = getelementptr inbounds [[KMP_PRIVATES_T]], ptr [[KMP_PRIVATES]], i32 0, i32 0
 116   // CHECK-32:    call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[FPSIZEGEP]], ptr align 8 [[SIZET2]], i64 24, i1 false)
 117   // CHECK-32:    [[FPBPGEP:%.+]] = getelementptr inbounds [[KMP_PRIVATES_T]], ptr [[KMP_PRIVATES]], i32 0, i32 1
 118   // CHECK-32:    call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[FPBPGEP]], ptr align 8 [[BPGEP]], i64 24, i1 false)
 119   // CHECK-32:    [[FPPGEP:%.+]] = getelementptr inbounds [[KMP_PRIVATES_T]], ptr [[KMP_PRIVATES]], i32 0, i32 2
 120   // CHECK-32:    call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[FPPGEP]], ptr align 8 [[BCAST]], i64 24, i1 false)
 121   // CHECK-64:    [[FPBPGEP:%.+]] = getelementptr inbounds [[KMP_PRIVATES_T]], ptr [[KMP_PRIVATES]], i32 0, i32 0
 122   // CHECK-64:    call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[FPBPGEP]], ptr align 8 [[BPGEP]], i64 24, i1 false)
 123   // CHECK-64:    [[FPPGEP:%.+]] = getelementptr inbounds [[KMP_PRIVATES_T]], ptr [[KMP_PRIVATES]], i32 0, i32 1
 124   // CHECK-64:    call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[FPPGEP]], ptr align 8 [[BCAST]], i64 24, i1 false)
 125   // CHECK-64:    [[FPSIZEGEP]] = getelementptr inbounds [[KMP_PRIVATES_T]], ptr [[KMP_PRIVATES]], i32 0, i32 2
 126   // CHECK-64:    call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[FPSIZEGEP]], ptr align 8 [[SIZET2]], i64 24, i1 false)
 127   int lin = 12;
 128   #pragma omp target parallel for if(target: 1) linear(lin, a : get_val()) nowait
 129   for (unsigned long long it = 2000; it >= 600; it-=400) {
 130     aa += 1;
 131   }
 132
 133
 134
 135
 136   #pragma omp target parallel for if(target: n>10)
 137   for (short it = 6; it <= 20; it-=-4) {
 138     a += 1;
 139     aa += 1;
 140   }
 141
 142   // We capture 3 VLA sizes in this target region
 143
 144
 145
 146
 147
 148   // The names below are not necessarily consistent with the names used for the
 149   // addresses above as some are repeated.
 150
 151
 152
 153
 154
 155
 156
 157
 158
 159
 160   #pragma omp target parallel for if(target: n>20) schedule(static, a)
 161   for (unsigned char it = 'z'; it >= 'a'; it+=-1) {
 162     a += 1;
 163     b[2] += 1.0;
 164     bn[3] += 1.0;
 165     c[1][2] += 1.0;
 166     cn[1][3] += 1.0;
 167     d.X += 1;
 168     d.Y += 1;
 169   }
 170
 171   return a;
 172 }
 173
 174 // Check that the offloading functions are emitted and that the arguments are
 175 // correct and loaded correctly for the target regions in foo().
 176
 177
 178 // Create stack storage and store argument in there.
 179
 180 // Create stack storage and store argument in there.
 181
 182
 183 // Create stack storage and store argument in there.
 184
 185 // Create local storage for each capture.
 186
 187
 188
 189 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.
 190
 191 template<typename tx>
 192 tx ftemplate(int n) {
 193   tx a = 0;
 194   short aa = 0;
 195   tx b[10];
 196
 197   #pragma omp target parallel for if(target: n>40)
 198   for (long long i = -10; i < 10; i += 3) {
 199     a += 1;
 200     aa += 1;
 201     b[2] += 1;
 202   }
 203
 204   return a;
 205 }
 206
 207 static
 208 int fstatic(int n) {
 209   int a = 0;
 210   short aa = 0;
 211   char aaa = 0;
 212   int b[10];
 213
 214   #pragma omp target parallel for if(target: n>50)
 215   for (unsigned i=100; i<10; i+=10) {
 216     a += 1;
 217     aa += 1;
 218     aaa += 1;
 219     b[2] += 1;
 220   }
 221
 222   return a;
 223 }
 224
 225 struct S1 {
 226   double a;
 227
 228   int r1(int n){
 229     int b = n+1;
 230     short int c[2][n];
 231
 232     #pragma omp target parallel for if(target: n>60)
 233     for (unsigned long long it = 2000; it >= 600; it -= 400) {
 234       this->a = (double)b + 1.5;
 235       c[1][1] = ++a;
 236     }
 237
 238     return c[1][1] + (int)b;
 239   }
 240 };
 241
 242 int bar(int n){
 243   int a = 0;
 244
 245   a += foo(n);
 246
 247   S1 S;
 248   a += S.r1(n);
 249
 250   a += fstatic(n);
 251
 252   a += ftemplate<int>(n);
 253
 254   return a;
 255 }
 256
 257
 258
 259 // We capture 2 VLA sizes in this target region
 260
 261
 262 // The names below are not necessarily consistent with the names used for the
 263 // addresses above as some are repeated.
 264
 265
 266
 267
 268
 269
 270
 271
 272
 273
 274
 275
 276
 277
 278
 279
 280
 281
 282 // Check that the offloading functions are emitted and that the arguments are
 283 // correct and loaded correctly for the target regions of the callees of bar().
 284
 285 // Create local storage for each capture.
 286 // Store captures in the context.
 287
 288
 289 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.
 290
 291
 292 // Create local storage for each capture.
 293 // Store captures in the context.
 294
 295
 296
 297
 298 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.
 299
 300 // Create local storage for each capture.
 301 // Store captures in the context.
 302
 303
 304
 305 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.
 306
 307
 308 #endif
 309 // CHECK1-LABEL: define {{[^@]+}}@_Z7get_valv
 310 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
 311 // CHECK1-NEXT:  entry:
 312 // CHECK1-NEXT:    ret i64 0
 313 //
 314 //
 315 // CHECK1-LABEL: define {{[^@]+}}@_Z3fooi
 316 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
 317 // CHECK1-NEXT:  entry:
 318 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
 319 // CHECK1-NEXT:    [[A:%.*]] = alloca i32, align 4
 320 // CHECK1-NEXT:    [[AA:%.*]] = alloca i16, align 2
 321 // CHECK1-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
 322 // CHECK1-NEXT:    [[SAVED_STACK:%.*]] = alloca ptr, align 8
 323 // CHECK1-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
 324 // CHECK1-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
 325 // CHECK1-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
 326 // CHECK1-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
 327 // CHECK1-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
 328 // CHECK1-NEXT:    [[K:%.*]] = alloca i64, align 8
 329 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
 330 // CHECK1-NEXT:    [[K_CASTED:%.*]] = alloca i64, align 8
 331 // CHECK1-NEXT:    [[LIN:%.*]] = alloca i32, align 4
 332 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
 333 // CHECK1-NEXT:    [[LIN_CASTED:%.*]] = alloca i64, align 8
 334 // CHECK1-NEXT:    [[A_CASTED2:%.*]] = alloca i64, align 8
 335 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8
 336 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 8
 337 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 8
 338 // CHECK1-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4
 339 // CHECK1-NEXT:    [[A_CASTED3:%.*]] = alloca i64, align 8
 340 // CHECK1-NEXT:    [[AA_CASTED4:%.*]] = alloca i64, align 8
 341 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [2 x ptr], align 8
 342 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS6:%.*]] = alloca [2 x ptr], align 8
 343 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [2 x ptr], align 8
 344 // CHECK1-NEXT:    [[KERNEL_ARGS8:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
 345 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
 346 // CHECK1-NEXT:    [[A_CASTED11:%.*]] = alloca i64, align 8
 347 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
 348 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [10 x ptr], align 8
 349 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS15:%.*]] = alloca [10 x ptr], align 8
 350 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [10 x ptr], align 8
 351 // CHECK1-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8
 352 // CHECK1-NEXT:    [[KERNEL_ARGS17:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
 353 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])
 354 // CHECK1-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
 355 // CHECK1-NEXT:    store i32 0, ptr [[A]], align 4
 356 // CHECK1-NEXT:    store i16 0, ptr [[AA]], align 2
 357 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
 358 // CHECK1-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
 359 // CHECK1-NEXT:    [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()
 360 // CHECK1-NEXT:    store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8
 361 // CHECK1-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4
 362 // CHECK1-NEXT:    store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8
 363 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
 364 // CHECK1-NEXT:    [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
 365 // CHECK1-NEXT:    [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]]
 366 // CHECK1-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8
 367 // CHECK1-NEXT:    store i64 [[TMP5]], ptr [[__VLA_EXPR1]], align 8
 368 // CHECK1-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
 369 // CHECK1-NEXT:    store i32 2, ptr [[TMP7]], align 4
 370 // CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
 371 // CHECK1-NEXT:    store i32 0, ptr [[TMP8]], align 4
 372 // CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
 373 // CHECK1-NEXT:    store ptr null, ptr [[TMP9]], align 8
 374 // CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
 375 // CHECK1-NEXT:    store ptr null, ptr [[TMP10]], align 8
 376 // CHECK1-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
 377 // CHECK1-NEXT:    store ptr null, ptr [[TMP11]], align 8
 378 // CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
 379 // CHECK1-NEXT:    store ptr null, ptr [[TMP12]], align 8
 380 // CHECK1-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
 381 // CHECK1-NEXT:    store ptr null, ptr [[TMP13]], align 8
 382 // CHECK1-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
 383 // CHECK1-NEXT:    store ptr null, ptr [[TMP14]], align 8
 384 // CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
 385 // CHECK1-NEXT:    store i64 0, ptr [[TMP15]], align 8
 386 // CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
 387 // CHECK1-NEXT:    store i64 0, ptr [[TMP16]], align 8
 388 // CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
 389 // CHECK1-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP17]], align 4
 390 // CHECK1-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
 391 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP18]], align 4
 392 // CHECK1-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
 393 // CHECK1-NEXT:    store i32 0, ptr [[TMP19]], align 4
 394 // CHECK1-NEXT:    [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, ptr [[KERNEL_ARGS]])
 395 // CHECK1-NEXT:    [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
 396 // CHECK1-NEXT:    br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
 397 // CHECK1:       omp_offload.failed:
 398 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR3:[0-9]+]]
 399 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
 400 // CHECK1:       omp_offload.cont:
 401 // CHECK1-NEXT:    [[CALL:%.*]] = call noundef i64 @_Z7get_valv()
 402 // CHECK1-NEXT:    store i64 [[CALL]], ptr [[K]], align 8
 403 // CHECK1-NEXT:    [[TMP22:%.*]] = load i32, ptr [[A]], align 4
 404 // CHECK1-NEXT:    store i32 [[TMP22]], ptr [[A_CASTED]], align 4
 405 // CHECK1-NEXT:    [[TMP23:%.*]] = load i64, ptr [[A_CASTED]], align 8
 406 // CHECK1-NEXT:    [[TMP24:%.*]] = load i64, ptr [[K]], align 8
 407 // CHECK1-NEXT:    store i64 [[TMP24]], ptr [[K_CASTED]], align 8
 408 // CHECK1-NEXT:    [[TMP25:%.*]] = load i64, ptr [[K_CASTED]], align 8
 409 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i64 [[TMP23]], i64 [[TMP25]]) #[[ATTR3]]
 410 // CHECK1-NEXT:    store i32 12, ptr [[LIN]], align 4
 411 // CHECK1-NEXT:    [[TMP26:%.*]] = load i16, ptr [[AA]], align 2
 412 // CHECK1-NEXT:    store i16 [[TMP26]], ptr [[AA_CASTED]], align 2
 413 // CHECK1-NEXT:    [[TMP27:%.*]] = load i64, ptr [[AA_CASTED]], align 8
 414 // CHECK1-NEXT:    [[TMP28:%.*]] = load i32, ptr [[LIN]], align 4
 415 // CHECK1-NEXT:    store i32 [[TMP28]], ptr [[LIN_CASTED]], align 4
 416 // CHECK1-NEXT:    [[TMP29:%.*]] = load i64, ptr [[LIN_CASTED]], align 8
 417 // CHECK1-NEXT:    [[TMP30:%.*]] = load i32, ptr [[A]], align 4
 418 // CHECK1-NEXT:    store i32 [[TMP30]], ptr [[A_CASTED2]], align 4
 419 // CHECK1-NEXT:    [[TMP31:%.*]] = load i64, ptr [[A_CASTED2]], align 8
 420 // CHECK1-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
 421 // CHECK1-NEXT:    store i64 [[TMP27]], ptr [[TMP32]], align 8
 422 // CHECK1-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
 423 // CHECK1-NEXT:    store i64 [[TMP27]], ptr [[TMP33]], align 8
 424 // CHECK1-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
 425 // CHECK1-NEXT:    store ptr null, ptr [[TMP34]], align 8
 426 // CHECK1-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
 427 // CHECK1-NEXT:    store i64 [[TMP29]], ptr [[TMP35]], align 8
 428 // CHECK1-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
 429 // CHECK1-NEXT:    store i64 [[TMP29]], ptr [[TMP36]], align 8
 430 // CHECK1-NEXT:    [[TMP37:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
 431 // CHECK1-NEXT:    store ptr null, ptr [[TMP37]], align 8
 432 // CHECK1-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
 433 // CHECK1-NEXT:    store i64 [[TMP31]], ptr [[TMP38]], align 8
 434 // CHECK1-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
 435 // CHECK1-NEXT:    store i64 [[TMP31]], ptr [[TMP39]], align 8
 436 // CHECK1-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
 437 // CHECK1-NEXT:    store ptr null, ptr [[TMP40]], align 8
 438 // CHECK1-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
 439 // CHECK1-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
 440 // CHECK1-NEXT:    [[TMP43:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0
 441 // CHECK1-NEXT:    [[TMP44:%.*]] = load i16, ptr [[AA]], align 2
 442 // CHECK1-NEXT:    store i16 [[TMP44]], ptr [[TMP43]], align 4
 443 // CHECK1-NEXT:    [[TMP45:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 1
 444 // CHECK1-NEXT:    [[TMP46:%.*]] = load i32, ptr [[LIN]], align 4
 445 // CHECK1-NEXT:    store i32 [[TMP46]], ptr [[TMP45]], align 4
 446 // CHECK1-NEXT:    [[TMP47:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 2
 447 // CHECK1-NEXT:    [[TMP48:%.*]] = load i32, ptr [[A]], align 4
 448 // CHECK1-NEXT:    store i32 [[TMP48]], ptr [[TMP47]], align 4
 449 // CHECK1-NEXT:    [[TMP49:%.*]] = call ptr @__kmpc_omp_target_task_alloc(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i64 120, i64 12, ptr @.omp_task_entry., i64 -1)
 450 // CHECK1-NEXT:    [[TMP50:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP49]], i32 0, i32 0
 451 // CHECK1-NEXT:    [[TMP51:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP50]], i32 0, i32 0
 452 // CHECK1-NEXT:    [[TMP52:%.*]] = load ptr, ptr [[TMP51]], align 8
 453 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP52]], ptr align 4 [[AGG_CAPTURED]], i64 12, i1 false)
 454 // CHECK1-NEXT:    [[TMP53:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP49]], i32 0, i32 1
 455 // CHECK1-NEXT:    [[TMP54:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP53]], i32 0, i32 0
 456 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP54]], ptr align 8 [[TMP41]], i64 24, i1 false)
 457 // CHECK1-NEXT:    [[TMP55:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP53]], i32 0, i32 1
 458 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP55]], ptr align 8 [[TMP42]], i64 24, i1 false)
 459 // CHECK1-NEXT:    [[TMP56:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP53]], i32 0, i32 2
 460 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP56]], ptr align 8 @.offload_sizes, i64 24, i1 false)
 461 // CHECK1-NEXT:    [[TMP57:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP53]], i32 0, i32 3
 462 // CHECK1-NEXT:    [[TMP58:%.*]] = load i16, ptr [[AA]], align 2
 463 // CHECK1-NEXT:    store i16 [[TMP58]], ptr [[TMP57]], align 8
 464 // CHECK1-NEXT:    [[TMP59:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB2]], i32 [[TMP0]], ptr [[TMP49]])
 465 // CHECK1-NEXT:    [[TMP60:%.*]] = load i32, ptr [[A]], align 4
 466 // CHECK1-NEXT:    store i32 [[TMP60]], ptr [[A_CASTED3]], align 4
 467 // CHECK1-NEXT:    [[TMP61:%.*]] = load i64, ptr [[A_CASTED3]], align 8
 468 // CHECK1-NEXT:    [[TMP62:%.*]] = load i16, ptr [[AA]], align 2
 469 // CHECK1-NEXT:    store i16 [[TMP62]], ptr [[AA_CASTED4]], align 2
 470 // CHECK1-NEXT:    [[TMP63:%.*]] = load i64, ptr [[AA_CASTED4]], align 8
 471 // CHECK1-NEXT:    [[TMP64:%.*]] = load i32, ptr [[N_ADDR]], align 4
 472 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP64]], 10
 473 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
 474 // CHECK1:       omp_if.then:
 475 // CHECK1-NEXT:    [[TMP65:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0
 476 // CHECK1-NEXT:    store i64 [[TMP61]], ptr [[TMP65]], align 8
 477 // CHECK1-NEXT:    [[TMP66:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0
 478 // CHECK1-NEXT:    store i64 [[TMP61]], ptr [[TMP66]], align 8
 479 // CHECK1-NEXT:    [[TMP67:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 0
 480 // CHECK1-NEXT:    store ptr null, ptr [[TMP67]], align 8
 481 // CHECK1-NEXT:    [[TMP68:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1
 482 // CHECK1-NEXT:    store i64 [[TMP63]], ptr [[TMP68]], align 8
 483 // CHECK1-NEXT:    [[TMP69:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 1
 484 // CHECK1-NEXT:    store i64 [[TMP63]], ptr [[TMP69]], align 8
 485 // CHECK1-NEXT:    [[TMP70:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 1
 486 // CHECK1-NEXT:    store ptr null, ptr [[TMP70]], align 8
 487 // CHECK1-NEXT:    [[TMP71:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0
 488 // CHECK1-NEXT:    [[TMP72:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0
 489 // CHECK1-NEXT:    [[TMP73:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 0
 490 // CHECK1-NEXT:    store i32 2, ptr [[TMP73]], align 4
 491 // CHECK1-NEXT:    [[TMP74:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 1
 492 // CHECK1-NEXT:    store i32 2, ptr [[TMP74]], align 4
 493 // CHECK1-NEXT:    [[TMP75:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 2
 494 // CHECK1-NEXT:    store ptr [[TMP71]], ptr [[TMP75]], align 8
 495 // CHECK1-NEXT:    [[TMP76:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 3
 496 // CHECK1-NEXT:    store ptr [[TMP72]], ptr [[TMP76]], align 8
 497 // CHECK1-NEXT:    [[TMP77:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 4
 498 // CHECK1-NEXT:    store ptr @.offload_sizes.1, ptr [[TMP77]], align 8
 499 // CHECK1-NEXT:    [[TMP78:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 5
 500 // CHECK1-NEXT:    store ptr @.offload_maptypes.2, ptr [[TMP78]], align 8
 501 // CHECK1-NEXT:    [[TMP79:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 6
 502 // CHECK1-NEXT:    store ptr null, ptr [[TMP79]], align 8
 503 // CHECK1-NEXT:    [[TMP80:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 7
 504 // CHECK1-NEXT:    store ptr null, ptr [[TMP80]], align 8
 505 // CHECK1-NEXT:    [[TMP81:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 8
 506 // CHECK1-NEXT:    store i64 0, ptr [[TMP81]], align 8
 507 // CHECK1-NEXT:    [[TMP82:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 9
 508 // CHECK1-NEXT:    store i64 0, ptr [[TMP82]], align 8
 509 // CHECK1-NEXT:    [[TMP83:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 10
 510 // CHECK1-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP83]], align 4
 511 // CHECK1-NEXT:    [[TMP84:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 11
 512 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP84]], align 4
 513 // CHECK1-NEXT:    [[TMP85:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 12
 514 // CHECK1-NEXT:    store i32 0, ptr [[TMP85]], align 4
 515 // CHECK1-NEXT:    [[TMP86:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.region_id, ptr [[KERNEL_ARGS8]])
 516 // CHECK1-NEXT:    [[TMP87:%.*]] = icmp ne i32 [[TMP86]], 0
 517 // CHECK1-NEXT:    br i1 [[TMP87]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]]
 518 // CHECK1:       omp_offload.failed9:
 519 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136(i64 [[TMP61]], i64 [[TMP63]]) #[[ATTR3]]
 520 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT10]]
 521 // CHECK1:       omp_offload.cont10:
 522 // CHECK1-NEXT:    br label [[OMP_IF_END:%.*]]
 523 // CHECK1:       omp_if.else:
 524 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136(i64 [[TMP61]], i64 [[TMP63]]) #[[ATTR3]]
 525 // CHECK1-NEXT:    br label [[OMP_IF_END]]
 526 // CHECK1:       omp_if.end:
 527 // CHECK1-NEXT:    [[TMP88:%.*]] = load i32, ptr [[A]], align 4
 528 // CHECK1-NEXT:    store i32 [[TMP88]], ptr [[DOTCAPTURE_EXPR_]], align 4
 529 // CHECK1-NEXT:    [[TMP89:%.*]] = load i32, ptr [[A]], align 4
 530 // CHECK1-NEXT:    store i32 [[TMP89]], ptr [[A_CASTED11]], align 4
 531 // CHECK1-NEXT:    [[TMP90:%.*]] = load i64, ptr [[A_CASTED11]], align 8
 532 // CHECK1-NEXT:    [[TMP91:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
 533 // CHECK1-NEXT:    store i32 [[TMP91]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
 534 // CHECK1-NEXT:    [[TMP92:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8
 535 // CHECK1-NEXT:    [[TMP93:%.*]] = load i32, ptr [[N_ADDR]], align 4
 536 // CHECK1-NEXT:    [[CMP12:%.*]] = icmp sgt i32 [[TMP93]], 20
 537 // CHECK1-NEXT:    br i1 [[CMP12]], label [[OMP_IF_THEN13:%.*]], label [[OMP_IF_ELSE20:%.*]]
 538 // CHECK1:       omp_if.then13:
 539 // CHECK1-NEXT:    [[TMP94:%.*]] = mul nuw i64 [[TMP2]], 4
 540 // CHECK1-NEXT:    [[TMP95:%.*]] = mul nuw i64 5, [[TMP5]]
 541 // CHECK1-NEXT:    [[TMP96:%.*]] = mul nuw i64 [[TMP95]], 8
 542 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes.3, i64 80, i1 false)
 543 // CHECK1-NEXT:    [[TMP97:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0
 544 // CHECK1-NEXT:    store i64 [[TMP90]], ptr [[TMP97]], align 8
 545 // CHECK1-NEXT:    [[TMP98:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 0
 546 // CHECK1-NEXT:    store i64 [[TMP90]], ptr [[TMP98]], align 8
 547 // CHECK1-NEXT:    [[TMP99:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 0
 548 // CHECK1-NEXT:    store ptr null, ptr [[TMP99]], align 8
 549 // CHECK1-NEXT:    [[TMP100:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 1
 550 // CHECK1-NEXT:    store ptr [[B]], ptr [[TMP100]], align 8
 551 // CHECK1-NEXT:    [[TMP101:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 1
 552 // CHECK1-NEXT:    store ptr [[B]], ptr [[TMP101]], align 8
 553 // CHECK1-NEXT:    [[TMP102:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 1
 554 // CHECK1-NEXT:    store ptr null, ptr [[TMP102]], align 8
 555 // CHECK1-NEXT:    [[TMP103:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 2
 556 // CHECK1-NEXT:    store i64 [[TMP2]], ptr [[TMP103]], align 8
 557 // CHECK1-NEXT:    [[TMP104:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 2
 558 // CHECK1-NEXT:    store i64 [[TMP2]], ptr [[TMP104]], align 8
 559 // CHECK1-NEXT:    [[TMP105:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 2
 560 // CHECK1-NEXT:    store ptr null, ptr [[TMP105]], align 8
 561 // CHECK1-NEXT:    [[TMP106:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 3
 562 // CHECK1-NEXT:    store ptr [[VLA]], ptr [[TMP106]], align 8
 563 // CHECK1-NEXT:    [[TMP107:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 3
 564 // CHECK1-NEXT:    store ptr [[VLA]], ptr [[TMP107]], align 8
 565 // CHECK1-NEXT:    [[TMP108:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 3
 566 // CHECK1-NEXT:    store i64 [[TMP94]], ptr [[TMP108]], align 8
 567 // CHECK1-NEXT:    [[TMP109:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 3
 568 // CHECK1-NEXT:    store ptr null, ptr [[TMP109]], align 8
 569 // CHECK1-NEXT:    [[TMP110:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 4
 570 // CHECK1-NEXT:    store ptr [[C]], ptr [[TMP110]], align 8
 571 // CHECK1-NEXT:    [[TMP111:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 4
 572 // CHECK1-NEXT:    store ptr [[C]], ptr [[TMP111]], align 8
 573 // CHECK1-NEXT:    [[TMP112:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 4
 574 // CHECK1-NEXT:    store ptr null, ptr [[TMP112]], align 8
 575 // CHECK1-NEXT:    [[TMP113:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 5
 576 // CHECK1-NEXT:    store i64 5, ptr [[TMP113]], align 8
 577 // CHECK1-NEXT:    [[TMP114:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 5
 578 // CHECK1-NEXT:    store i64 5, ptr [[TMP114]], align 8
 579 // CHECK1-NEXT:    [[TMP115:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 5
 580 // CHECK1-NEXT:    store ptr null, ptr [[TMP115]], align 8
 581 // CHECK1-NEXT:    [[TMP116:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 6
 582 // CHECK1-NEXT:    store i64 [[TMP5]], ptr [[TMP116]], align 8
 583 // CHECK1-NEXT:    [[TMP117:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 6
 584 // CHECK1-NEXT:    store i64 [[TMP5]], ptr [[TMP117]], align 8
 585 // CHECK1-NEXT:    [[TMP118:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 6
 586 // CHECK1-NEXT:    store ptr null, ptr [[TMP118]], align 8
 587 // CHECK1-NEXT:    [[TMP119:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 7
 588 // CHECK1-NEXT:    store ptr [[VLA1]], ptr [[TMP119]], align 8
 589 // CHECK1-NEXT:    [[TMP120:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 7
 590 // CHECK1-NEXT:    store ptr [[VLA1]], ptr [[TMP120]], align 8
 591 // CHECK1-NEXT:    [[TMP121:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 7
 592 // CHECK1-NEXT:    store i64 [[TMP96]], ptr [[TMP121]], align 8
 593 // CHECK1-NEXT:    [[TMP122:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 7
 594 // CHECK1-NEXT:    store ptr null, ptr [[TMP122]], align 8
 595 // CHECK1-NEXT:    [[TMP123:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 8
 596 // CHECK1-NEXT:    store ptr [[D]], ptr [[TMP123]], align 8
 597 // CHECK1-NEXT:    [[TMP124:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 8
 598 // CHECK1-NEXT:    store ptr [[D]], ptr [[TMP124]], align 8
 599 // CHECK1-NEXT:    [[TMP125:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 8
 600 // CHECK1-NEXT:    store ptr null, ptr [[TMP125]], align 8
 601 // CHECK1-NEXT:    [[TMP126:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 9
 602 // CHECK1-NEXT:    store i64 [[TMP92]], ptr [[TMP126]], align 8
 603 // CHECK1-NEXT:    [[TMP127:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 9
 604 // CHECK1-NEXT:    store i64 [[TMP92]], ptr [[TMP127]], align 8
 605 // CHECK1-NEXT:    [[TMP128:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 9
 606 // CHECK1-NEXT:    store ptr null, ptr [[TMP128]], align 8
 607 // CHECK1-NEXT:    [[TMP129:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0
 608 // CHECK1-NEXT:    [[TMP130:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 0
 609 // CHECK1-NEXT:    [[TMP131:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0
 610 // CHECK1-NEXT:    [[TMP132:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 0
 611 // CHECK1-NEXT:    store i32 2, ptr [[TMP132]], align 4
 612 // CHECK1-NEXT:    [[TMP133:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 1
 613 // CHECK1-NEXT:    store i32 10, ptr [[TMP133]], align 4
 614 // CHECK1-NEXT:    [[TMP134:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 2
 615 // CHECK1-NEXT:    store ptr [[TMP129]], ptr [[TMP134]], align 8
 616 // CHECK1-NEXT:    [[TMP135:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 3
 617 // CHECK1-NEXT:    store ptr [[TMP130]], ptr [[TMP135]], align 8
 618 // CHECK1-NEXT:    [[TMP136:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 4
 619 // CHECK1-NEXT:    store ptr [[TMP131]], ptr [[TMP136]], align 8
 620 // CHECK1-NEXT:    [[TMP137:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 5
 621 // CHECK1-NEXT:    store ptr @.offload_maptypes.4, ptr [[TMP137]], align 8
 622 // CHECK1-NEXT:    [[TMP138:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 6
 623 // CHECK1-NEXT:    store ptr null, ptr [[TMP138]], align 8
 624 // CHECK1-NEXT:    [[TMP139:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 7
 625 // CHECK1-NEXT:    store ptr null, ptr [[TMP139]], align 8
 626 // CHECK1-NEXT:    [[TMP140:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 8
 627 // CHECK1-NEXT:    store i64 0, ptr [[TMP140]], align 8
 628 // CHECK1-NEXT:    [[TMP141:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 9
 629 // CHECK1-NEXT:    store i64 0, ptr [[TMP141]], align 8
 630 // CHECK1-NEXT:    [[TMP142:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 10
 631 // CHECK1-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP142]], align 4
 632 // CHECK1-NEXT:    [[TMP143:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 11
 633 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP143]], align 4
 634 // CHECK1-NEXT:    [[TMP144:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 12
 635 // CHECK1-NEXT:    store i32 0, ptr [[TMP144]], align 4
 636 // CHECK1-NEXT:    [[TMP145:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.region_id, ptr [[KERNEL_ARGS17]])
 637 // CHECK1-NEXT:    [[TMP146:%.*]] = icmp ne i32 [[TMP145]], 0
 638 // CHECK1-NEXT:    br i1 [[TMP146]], label [[OMP_OFFLOAD_FAILED18:%.*]], label [[OMP_OFFLOAD_CONT19:%.*]]
 639 // CHECK1:       omp_offload.failed18:
 640 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160(i64 [[TMP90]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]], i64 [[TMP92]]) #[[ATTR3]]
 641 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT19]]
 642 // CHECK1:       omp_offload.cont19:
 643 // CHECK1-NEXT:    br label [[OMP_IF_END21:%.*]]
 644 // CHECK1:       omp_if.else20:
 645 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160(i64 [[TMP90]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]], i64 [[TMP92]]) #[[ATTR3]]
 646 // CHECK1-NEXT:    br label [[OMP_IF_END21]]
 647 // CHECK1:       omp_if.end21:
 648 // CHECK1-NEXT:    [[TMP147:%.*]] = load i32, ptr [[A]], align 4
 649 // CHECK1-NEXT:    [[TMP148:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
 650 // CHECK1-NEXT:    call void @llvm.stackrestore.p0(ptr [[TMP148]])
 651 // CHECK1-NEXT:    ret i32 [[TMP147]]
 652 //
 653 //
 654 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
 655 // CHECK1-SAME: () #[[ATTR2:[0-9]+]] {
 656 // CHECK1-NEXT:  entry:
 657 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined)
 658 // CHECK1-NEXT:    ret void
 659 //
 660 //
 661 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined
 662 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] {
 663 // CHECK1-NEXT:  entry:
 664 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 665 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 666 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 667 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 668 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
 669 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
 670 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 671 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 672 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
 673 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 674 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 675 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
 676 // CHECK1-NEXT:    store i32 5, ptr [[DOTOMP_UB]], align 4
 677 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 678 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 679 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 680 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
 681 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
 682 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 683 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
 684 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 685 // CHECK1:       cond.true:
 686 // CHECK1-NEXT:    br label [[COND_END:%.*]]
 687 // CHECK1:       cond.false:
 688 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 689 // CHECK1-NEXT:    br label [[COND_END]]
 690 // CHECK1:       cond.end:
 691 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
 692 // CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
 693 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
 694 // CHECK1-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
 695 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 696 // CHECK1:       omp.inner.for.cond:
 697 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 698 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 699 // CHECK1-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
 700 // CHECK1-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 701 // CHECK1:       omp.inner.for.body:
 702 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 703 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
 704 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 3, [[MUL]]
 705 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[I]], align 4
 706 // CHECK1-NEXT:    [[TMP8:%.*]] = call i32 @__kmpc_cancel(ptr @[[GLOB2]], i32 [[TMP1]], i32 2)
 707 // CHECK1-NEXT:    [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0
 708 // CHECK1-NEXT:    br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
 709 // CHECK1:       .cancel.exit:
 710 // CHECK1-NEXT:    br label [[CANCEL_EXIT:%.*]]
 711 // CHECK1:       .cancel.continue:
 712 // CHECK1-NEXT:    [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(ptr @[[GLOB2]], i32 [[TMP1]], i32 2)
 713 // CHECK1-NEXT:    [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
 714 // CHECK1-NEXT:    br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]]
 715 // CHECK1:       .cancel.exit2:
 716 // CHECK1-NEXT:    br label [[CANCEL_EXIT]]
 717 // CHECK1:       .cancel.continue3:
 718 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 719 // CHECK1:       omp.body.continue:
 720 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 721 // CHECK1:       omp.inner.for.inc:
 722 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 723 // CHECK1-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
 724 // CHECK1-NEXT:    store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4
 725 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]
 726 // CHECK1:       omp.inner.for.end:
 727 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
 728 // CHECK1:       omp.loop.exit:
 729 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
 730 // CHECK1-NEXT:    br label [[CANCEL_CONT:%.*]]
 731 // CHECK1:       cancel.cont:
 732 // CHECK1-NEXT:    ret void
 733 // CHECK1:       cancel.exit:
 734 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
 735 // CHECK1-NEXT:    br label [[CANCEL_CONT]]
 736 //
 737 //
 738 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110
 739 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR2]] {
 740 // CHECK1-NEXT:  entry:
 741 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
 742 // CHECK1-NEXT:    [[K_ADDR:%.*]] = alloca i64, align 8
 743 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
 744 // CHECK1-NEXT:    [[K_CASTED:%.*]] = alloca i64, align 8
 745 // CHECK1-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
 746 // CHECK1-NEXT:    store i64 [[K]], ptr [[K_ADDR]], align 8
 747 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
 748 // CHECK1-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 4
 749 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8
 750 // CHECK1-NEXT:    [[TMP2:%.*]] = load i64, ptr [[K_ADDR]], align 8
 751 // CHECK1-NEXT:    store i64 [[TMP2]], ptr [[K_CASTED]], align 8
 752 // CHECK1-NEXT:    [[TMP3:%.*]] = load i64, ptr [[K_CASTED]], align 8
 753 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.omp_outlined, i64 [[TMP1]], i64 [[TMP3]])
 754 // CHECK1-NEXT:    ret void
 755 //
 756 //
 757 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.omp_outlined
 758 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR2]] {
 759 // CHECK1-NEXT:  entry:
 760 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 761 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 762 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
 763 // CHECK1-NEXT:    [[K_ADDR:%.*]] = alloca i64, align 8
 764 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 765 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 766 // CHECK1-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i64, align 8
 767 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
 768 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
 769 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 770 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 771 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
 772 // CHECK1-NEXT:    [[K1:%.*]] = alloca i64, align 8
 773 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 774 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 775 // CHECK1-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
 776 // CHECK1-NEXT:    store i64 [[K]], ptr [[K_ADDR]], align 8
 777 // CHECK1-NEXT:    [[TMP0:%.*]] = load i64, ptr [[K_ADDR]], align 8
 778 // CHECK1-NEXT:    store i64 [[TMP0]], ptr [[DOTLINEAR_START]], align 8
 779 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
 780 // CHECK1-NEXT:    store i32 8, ptr [[DOTOMP_UB]], align 4
 781 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 782 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 783 // CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 784 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
 785 // CHECK1-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP2]])
 786 // CHECK1-NEXT:    call void @__kmpc_dispatch_init_4(ptr @[[GLOB2]], i32 [[TMP2]], i32 35, i32 0, i32 8, i32 1, i32 1)
 787 // CHECK1-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
 788 // CHECK1:       omp.dispatch.cond:
 789 // CHECK1-NEXT:    [[TMP3:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB2]], i32 [[TMP2]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
 790 // CHECK1-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP3]], 0
 791 // CHECK1-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
 792 // CHECK1:       omp.dispatch.body:
 793 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
 794 // CHECK1-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
 795 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 796 // CHECK1:       omp.inner.for.cond:
 797 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12:![0-9]+]]
 798 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP12]]
 799 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
 800 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 801 // CHECK1:       omp.inner.for.body:
 802 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]
 803 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
 804 // CHECK1-NEXT:    [[SUB:%.*]] = sub nsw i32 10, [[MUL]]
 805 // CHECK1-NEXT:    store i32 [[SUB]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]]
 806 // CHECK1-NEXT:    [[TMP8:%.*]] = load i64, ptr [[DOTLINEAR_START]], align 8, !llvm.access.group [[ACC_GRP12]]
 807 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]
 808 // CHECK1-NEXT:    [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3
 809 // CHECK1-NEXT:    [[CONV:%.*]] = sext i32 [[MUL2]] to i64
 810 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV]]
 811 // CHECK1-NEXT:    store i64 [[ADD]], ptr [[K1]], align 8, !llvm.access.group [[ACC_GRP12]]
 812 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP12]]
 813 // CHECK1-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
 814 // CHECK1-NEXT:    store i32 [[ADD3]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP12]]
 815 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 816 // CHECK1:       omp.body.continue:
 817 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 818 // CHECK1:       omp.inner.for.inc:
 819 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]
 820 // CHECK1-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1
 821 // CHECK1-NEXT:    store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]
 822 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
 823 // CHECK1:       omp.inner.for.end:
 824 // CHECK1-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
 825 // CHECK1:       omp.dispatch.inc:
 826 // CHECK1-NEXT:    br label [[OMP_DISPATCH_COND]]
 827 // CHECK1:       omp.dispatch.end:
 828 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
 829 // CHECK1-NEXT:    [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
 830 // CHECK1-NEXT:    br i1 [[TMP13]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
 831 // CHECK1:       .omp.linear.pu:
 832 // CHECK1-NEXT:    [[TMP14:%.*]] = load i64, ptr [[K1]], align 8
 833 // CHECK1-NEXT:    store i64 [[TMP14]], ptr [[K_ADDR]], align 8
 834 // CHECK1-NEXT:    br label [[DOTOMP_LINEAR_PU_DONE]]
 835 // CHECK1:       .omp.linear.pu.done:
 836 // CHECK1-NEXT:    ret void
 837 //
 838 //
 839 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128
 840 // CHECK1-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] {
 841 // CHECK1-NEXT:  entry:
 842 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
 843 // CHECK1-NEXT:    [[LIN_ADDR:%.*]] = alloca i64, align 8
 844 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
 845 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
 846 // CHECK1-NEXT:    [[LIN_CASTED:%.*]] = alloca i64, align 8
 847 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
 848 // CHECK1-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
 849 // CHECK1-NEXT:    store i64 [[LIN]], ptr [[LIN_ADDR]], align 8
 850 // CHECK1-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
 851 // CHECK1-NEXT:    [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2
 852 // CHECK1-NEXT:    store i16 [[TMP0]], ptr [[AA_CASTED]], align 2
 853 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[AA_CASTED]], align 8
 854 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[LIN_ADDR]], align 4
 855 // CHECK1-NEXT:    store i32 [[TMP2]], ptr [[LIN_CASTED]], align 4
 856 // CHECK1-NEXT:    [[TMP3:%.*]] = load i64, ptr [[LIN_CASTED]], align 8
 857 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4
 858 // CHECK1-NEXT:    store i32 [[TMP4]], ptr [[A_CASTED]], align 4
 859 // CHECK1-NEXT:    [[TMP5:%.*]] = load i64, ptr [[A_CASTED]], align 8
 860 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128.omp_outlined, i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]])
 861 // CHECK1-NEXT:    ret void
 862 //
 863 //
 864 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128.omp_outlined
 865 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] {
 866 // CHECK1-NEXT:  entry:
 867 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 868 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 869 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
 870 // CHECK1-NEXT:    [[LIN_ADDR:%.*]] = alloca i64, align 8
 871 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
 872 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
 873 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i64, align 8
 874 // CHECK1-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i32, align 4
 875 // CHECK1-NEXT:    [[DOTLINEAR_START1:%.*]] = alloca i32, align 4
 876 // CHECK1-NEXT:    [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
 877 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
 878 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
 879 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
 880 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 881 // CHECK1-NEXT:    [[IT:%.*]] = alloca i64, align 8
 882 // CHECK1-NEXT:    [[LIN2:%.*]] = alloca i32, align 4
 883 // CHECK1-NEXT:    [[A3:%.*]] = alloca i32, align 4
 884 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 885 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 886 // CHECK1-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
 887 // CHECK1-NEXT:    store i64 [[LIN]], ptr [[LIN_ADDR]], align 8
 888 // CHECK1-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
 889 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[LIN_ADDR]], align 4
 890 // CHECK1-NEXT:    store i32 [[TMP0]], ptr [[DOTLINEAR_START]], align 4
 891 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
 892 // CHECK1-NEXT:    store i32 [[TMP1]], ptr [[DOTLINEAR_START1]], align 4
 893 // CHECK1-NEXT:    [[CALL:%.*]] = call noundef i64 @_Z7get_valv()
 894 // CHECK1-NEXT:    store i64 [[CALL]], ptr [[DOTLINEAR_STEP]], align 8
 895 // CHECK1-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8
 896 // CHECK1-NEXT:    store i64 3, ptr [[DOTOMP_UB]], align 8
 897 // CHECK1-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8
 898 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 899 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 900 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
 901 // CHECK1-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP3]])
 902 // CHECK1-NEXT:    call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
 903 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
 904 // CHECK1-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
 905 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 906 // CHECK1:       cond.true:
 907 // CHECK1-NEXT:    br label [[COND_END:%.*]]
 908 // CHECK1:       cond.false:
 909 // CHECK1-NEXT:    [[TMP5:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
 910 // CHECK1-NEXT:    br label [[COND_END]]
 911 // CHECK1:       cond.end:
 912 // CHECK1-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
 913 // CHECK1-NEXT:    store i64 [[COND]], ptr [[DOTOMP_UB]], align 8
 914 // CHECK1-NEXT:    [[TMP6:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
 915 // CHECK1-NEXT:    store i64 [[TMP6]], ptr [[DOTOMP_IV]], align 8
 916 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 917 // CHECK1:       omp.inner.for.cond:
 918 // CHECK1-NEXT:    [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
 919 // CHECK1-NEXT:    [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
 920 // CHECK1-NEXT:    [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
 921 // CHECK1-NEXT:    br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 922 // CHECK1:       omp.inner.for.body:
 923 // CHECK1-NEXT:    [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
 924 // CHECK1-NEXT:    [[MUL:%.*]] = mul i64 [[TMP9]], 400
 925 // CHECK1-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
 926 // CHECK1-NEXT:    store i64 [[SUB]], ptr [[IT]], align 8
 927 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTLINEAR_START]], align 4
 928 // CHECK1-NEXT:    [[CONV:%.*]] = sext i32 [[TMP10]] to i64
 929 // CHECK1-NEXT:    [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
 930 // CHECK1-NEXT:    [[TMP12:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8
 931 // CHECK1-NEXT:    [[MUL5:%.*]] = mul i64 [[TMP11]], [[TMP12]]
 932 // CHECK1-NEXT:    [[ADD:%.*]] = add i64 [[CONV]], [[MUL5]]
 933 // CHECK1-NEXT:    [[CONV6:%.*]] = trunc i64 [[ADD]] to i32
 934 // CHECK1-NEXT:    store i32 [[CONV6]], ptr [[LIN2]], align 4
 935 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTLINEAR_START1]], align 4
 936 // CHECK1-NEXT:    [[CONV7:%.*]] = sext i32 [[TMP13]] to i64
 937 // CHECK1-NEXT:    [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
 938 // CHECK1-NEXT:    [[TMP15:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8
 939 // CHECK1-NEXT:    [[MUL8:%.*]] = mul i64 [[TMP14]], [[TMP15]]
 940 // CHECK1-NEXT:    [[ADD9:%.*]] = add i64 [[CONV7]], [[MUL8]]
 941 // CHECK1-NEXT:    [[CONV10:%.*]] = trunc i64 [[ADD9]] to i32
 942 // CHECK1-NEXT:    store i32 [[CONV10]], ptr [[A3]], align 4
 943 // CHECK1-NEXT:    [[TMP16:%.*]] = load i16, ptr [[AA_ADDR]], align 2
 944 // CHECK1-NEXT:    [[CONV11:%.*]] = sext i16 [[TMP16]] to i32
 945 // CHECK1-NEXT:    [[ADD12:%.*]] = add nsw i32 [[CONV11]], 1
 946 // CHECK1-NEXT:    [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16
 947 // CHECK1-NEXT:    store i16 [[CONV13]], ptr [[AA_ADDR]], align 2
 948 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 949 // CHECK1:       omp.body.continue:
 950 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 951 // CHECK1:       omp.inner.for.inc:
 952 // CHECK1-NEXT:    [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
 953 // CHECK1-NEXT:    [[ADD14:%.*]] = add i64 [[TMP17]], 1
 954 // CHECK1-NEXT:    store i64 [[ADD14]], ptr [[DOTOMP_IV]], align 8
 955 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]
 956 // CHECK1:       omp.inner.for.end:
 957 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
 958 // CHECK1:       omp.loop.exit:
 959 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]])
 960 // CHECK1-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
 961 // CHECK1-NEXT:    [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
 962 // CHECK1-NEXT:    br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
 963 // CHECK1:       .omp.linear.pu:
 964 // CHECK1-NEXT:    [[TMP20:%.*]] = load i32, ptr [[LIN2]], align 4
 965 // CHECK1-NEXT:    store i32 [[TMP20]], ptr [[LIN_ADDR]], align 4
 966 // CHECK1-NEXT:    [[TMP21:%.*]] = load i32, ptr [[A3]], align 4
 967 // CHECK1-NEXT:    store i32 [[TMP21]], ptr [[A_ADDR]], align 4
 968 // CHECK1-NEXT:    br label [[DOTOMP_LINEAR_PU_DONE]]
 969 // CHECK1:       .omp.linear.pu.done:
 970 // CHECK1-NEXT:    ret void
 971 //
 972 //
 973 // CHECK1-LABEL: define {{[^@]+}}@.omp_task_privates_map.
 974 // CHECK1-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]], ptr noalias noundef [[TMP3:%.*]], ptr noalias noundef [[TMP4:%.*]]) #[[ATTR5:[0-9]+]] {
 975 // CHECK1-NEXT:  entry:
 976 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
 977 // CHECK1-NEXT:    [[DOTADDR1:%.*]] = alloca ptr, align 8
 978 // CHECK1-NEXT:    [[DOTADDR2:%.*]] = alloca ptr, align 8
 979 // CHECK1-NEXT:    [[DOTADDR3:%.*]] = alloca ptr, align 8
 980 // CHECK1-NEXT:    [[DOTADDR4:%.*]] = alloca ptr, align 8
 981 // CHECK1-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
 982 // CHECK1-NEXT:    store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
 983 // CHECK1-NEXT:    store ptr [[TMP2]], ptr [[DOTADDR2]], align 8
 984 // CHECK1-NEXT:    store ptr [[TMP3]], ptr [[DOTADDR3]], align 8
 985 // CHECK1-NEXT:    store ptr [[TMP4]], ptr [[DOTADDR4]], align 8
 986 // CHECK1-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[DOTADDR]], align 8
 987 // CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP5]], i32 0, i32 0
 988 // CHECK1-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[DOTADDR2]], align 8
 989 // CHECK1-NEXT:    store ptr [[TMP6]], ptr [[TMP7]], align 8
 990 // CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 1
 991 // CHECK1-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[DOTADDR3]], align 8
 992 // CHECK1-NEXT:    store ptr [[TMP8]], ptr [[TMP9]], align 8
 993 // CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 2
 994 // CHECK1-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[DOTADDR4]], align 8
 995 // CHECK1-NEXT:    store ptr [[TMP10]], ptr [[TMP11]], align 8
 996 // CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 3
 997 // CHECK1-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[DOTADDR1]], align 8
 998 // CHECK1-NEXT:    store ptr [[TMP12]], ptr [[TMP13]], align 8
 999 // CHECK1-NEXT:    ret void
1000 //
1001 //
1002 // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry.
1003 // CHECK1-SAME: (i32 noundef signext [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] {
1004 // CHECK1-NEXT:  entry:
1005 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
1006 // CHECK1-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8
1007 // CHECK1-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8
1008 // CHECK1-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8
1009 // CHECK1-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8
1010 // CHECK1-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8
1011 // CHECK1-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca ptr, align 8
1012 // CHECK1-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca ptr, align 8
1013 // CHECK1-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca ptr, align 8
1014 // CHECK1-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca ptr, align 8
1015 // CHECK1-NEXT:    [[KERNEL_ARGS_I:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1016 // CHECK1-NEXT:    [[AA_CASTED_I:%.*]] = alloca i64, align 8
1017 // CHECK1-NEXT:    [[LIN_CASTED_I:%.*]] = alloca i64, align 8
1018 // CHECK1-NEXT:    [[A_CASTED_I:%.*]] = alloca i64, align 8
1019 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 4
1020 // CHECK1-NEXT:    [[DOTADDR1:%.*]] = alloca ptr, align 8
1021 // CHECK1-NEXT:    store i32 [[TMP0]], ptr [[DOTADDR]], align 4
1022 // CHECK1-NEXT:    store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
1023 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4
1024 // CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8
1025 // CHECK1-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0
1026 // CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2
1027 // CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0
1028 // CHECK1-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8
1029 // CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 1
1030 // CHECK1-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])
1031 // CHECK1-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])
1032 // CHECK1-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
1033 // CHECK1-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])
1034 // CHECK1-NEXT:    store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24
1035 // CHECK1-NEXT:    store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias !24
1036 // CHECK1-NEXT:    store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24
1037 // CHECK1-NEXT:    store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24
1038 // CHECK1-NEXT:    store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias !24
1039 // CHECK1-NEXT:    store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias !24
1040 // CHECK1-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias !24
1041 // CHECK1-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24
1042 // CHECK1-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24
1043 // CHECK1-NEXT:    call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]
1044 // CHECK1-NEXT:    [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !24
1045 // CHECK1-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !24
1046 // CHECK1-NEXT:    [[TMP14:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !24
1047 // CHECK1-NEXT:    [[TMP15:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !24
1048 // CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP9]], i32 0, i32 1
1049 // CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP9]], i32 0, i32 2
1050 // CHECK1-NEXT:    store i32 2, ptr [[KERNEL_ARGS_I]], align 4, !noalias !24
1051 // CHECK1-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 1
1052 // CHECK1-NEXT:    store i32 3, ptr [[TMP18]], align 4, !noalias !24
1053 // CHECK1-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 2
1054 // CHECK1-NEXT:    store ptr [[TMP13]], ptr [[TMP19]], align 8, !noalias !24
1055 // CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 3
1056 // CHECK1-NEXT:    store ptr [[TMP14]], ptr [[TMP20]], align 8, !noalias !24
1057 // CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 4
1058 // CHECK1-NEXT:    store ptr [[TMP15]], ptr [[TMP21]], align 8, !noalias !24
1059 // CHECK1-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 5
1060 // CHECK1-NEXT:    store ptr @.offload_maptypes, ptr [[TMP22]], align 8, !noalias !24
1061 // CHECK1-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 6
1062 // CHECK1-NEXT:    store ptr null, ptr [[TMP23]], align 8, !noalias !24
1063 // CHECK1-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 7
1064 // CHECK1-NEXT:    store ptr null, ptr [[TMP24]], align 8, !noalias !24
1065 // CHECK1-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 8
1066 // CHECK1-NEXT:    store i64 0, ptr [[TMP25]], align 8, !noalias !24
1067 // CHECK1-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 9
1068 // CHECK1-NEXT:    store i64 1, ptr [[TMP26]], align 8, !noalias !24
1069 // CHECK1-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 10
1070 // CHECK1-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP27]], align 4, !noalias !24
1071 // CHECK1-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 11
1072 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP28]], align 4, !noalias !24
1073 // CHECK1-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 12
1074 // CHECK1-NEXT:    store i32 0, ptr [[TMP29]], align 4, !noalias !24
1075 // CHECK1-NEXT:    [[TMP30:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128.region_id, ptr [[KERNEL_ARGS_I]])
1076 // CHECK1-NEXT:    [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0
1077 // CHECK1-NEXT:    br i1 [[TMP31]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]]
1078 // CHECK1:       omp_offload.failed.i:
1079 // CHECK1-NEXT:    [[TMP32:%.*]] = load i16, ptr [[TMP12]], align 2
1080 // CHECK1-NEXT:    store i16 [[TMP32]], ptr [[AA_CASTED_I]], align 2, !noalias !24
1081 // CHECK1-NEXT:    [[TMP33:%.*]] = load i64, ptr [[AA_CASTED_I]], align 8, !noalias !24
1082 // CHECK1-NEXT:    [[TMP34:%.*]] = load i32, ptr [[TMP16]], align 4
1083 // CHECK1-NEXT:    store i32 [[TMP34]], ptr [[LIN_CASTED_I]], align 4, !noalias !24
1084 // CHECK1-NEXT:    [[TMP35:%.*]] = load i64, ptr [[LIN_CASTED_I]], align 8, !noalias !24
1085 // CHECK1-NEXT:    [[TMP36:%.*]] = load i32, ptr [[TMP17]], align 4
1086 // CHECK1-NEXT:    store i32 [[TMP36]], ptr [[A_CASTED_I]], align 4, !noalias !24
1087 // CHECK1-NEXT:    [[TMP37:%.*]] = load i64, ptr [[A_CASTED_I]], align 8, !noalias !24
1088 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128(i64 [[TMP33]], i64 [[TMP35]], i64 [[TMP37]]) #[[ATTR3]]
1089 // CHECK1-NEXT:    br label [[DOTOMP_OUTLINED__EXIT]]
1090 // CHECK1:       .omp_outlined..exit:
1091 // CHECK1-NEXT:    ret i32 0
1092 //
1093 //
1094 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136
1095 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {
1096 // CHECK1-NEXT:  entry:
1097 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1098 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
1099 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
1100 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
1101 // CHECK1-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
1102 // CHECK1-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
1103 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
1104 // CHECK1-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 4
1105 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8
1106 // CHECK1-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2
1107 // CHECK1-NEXT:    store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
1108 // CHECK1-NEXT:    [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8
1109 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.omp_outlined, i64 [[TMP1]], i64 [[TMP3]])
1110 // CHECK1-NEXT:    ret void
1111 //
1112 //
1113 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.omp_outlined
1114 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {
1115 // CHECK1-NEXT:  entry:
1116 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1117 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1118 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1119 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
1120 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1121 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i16, align 2
1122 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1123 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1124 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1125 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1126 // CHECK1-NEXT:    [[IT:%.*]] = alloca i16, align 2
1127 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1128 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1129 // CHECK1-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
1130 // CHECK1-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
1131 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
1132 // CHECK1-NEXT:    store i32 3, ptr [[DOTOMP_UB]], align 4
1133 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1134 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1135 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1136 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
1137 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
1138 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1139 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
1140 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1141 // CHECK1:       cond.true:
1142 // CHECK1-NEXT:    br label [[COND_END:%.*]]
1143 // CHECK1:       cond.false:
1144 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1145 // CHECK1-NEXT:    br label [[COND_END]]
1146 // CHECK1:       cond.end:
1147 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
1148 // CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
1149 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1150 // CHECK1-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
1151 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1152 // CHECK1:       omp.inner.for.cond:
1153 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1154 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1155 // CHECK1-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
1156 // CHECK1-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1157 // CHECK1:       omp.inner.for.body:
1158 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1159 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
1160 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 6, [[MUL]]
1161 // CHECK1-NEXT:    [[CONV:%.*]] = trunc i32 [[ADD]] to i16
1162 // CHECK1-NEXT:    store i16 [[CONV]], ptr [[IT]], align 2
1163 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
1164 // CHECK1-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
1165 // CHECK1-NEXT:    store i32 [[ADD2]], ptr [[A_ADDR]], align 4
1166 // CHECK1-NEXT:    [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2
1167 // CHECK1-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP9]] to i32
1168 // CHECK1-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
1169 // CHECK1-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
1170 // CHECK1-NEXT:    store i16 [[CONV5]], ptr [[AA_ADDR]], align 2
1171 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1172 // CHECK1:       omp.body.continue:
1173 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1174 // CHECK1:       omp.inner.for.inc:
1175 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1176 // CHECK1-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1
1177 // CHECK1-NEXT:    store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4
1178 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]
1179 // CHECK1:       omp.inner.for.end:
1180 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1181 // CHECK1:       omp.loop.exit:
1182 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
1183 // CHECK1-NEXT:    ret void
1184 //
1185 //
1186 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160
1187 // CHECK1-SAME: (i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
1188 // CHECK1-NEXT:  entry:
1189 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1190 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
1191 // CHECK1-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
1192 // CHECK1-NEXT:    [[BN_ADDR:%.*]] = alloca ptr, align 8
1193 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
1194 // CHECK1-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
1195 // CHECK1-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
1196 // CHECK1-NEXT:    [[CN_ADDR:%.*]] = alloca ptr, align 8
1197 // CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
1198 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
1199 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
1200 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
1201 // CHECK1-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
1202 // CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
1203 // CHECK1-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
1204 // CHECK1-NEXT:    store ptr [[BN]], ptr [[BN_ADDR]], align 8
1205 // CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
1206 // CHECK1-NEXT:    store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
1207 // CHECK1-NEXT:    store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8
1208 // CHECK1-NEXT:    store ptr [[CN]], ptr [[CN_ADDR]], align 8
1209 // CHECK1-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
1210 // CHECK1-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
1211 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
1212 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
1213 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8
1214 // CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
1215 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
1216 // CHECK1-NEXT:    [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8
1217 // CHECK1-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8
1218 // CHECK1-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8
1219 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
1220 // CHECK1-NEXT:    store i32 [[TMP8]], ptr [[A_CASTED]], align 4
1221 // CHECK1-NEXT:    [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 8
1222 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
1223 // CHECK1-NEXT:    store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
1224 // CHECK1-NEXT:    [[TMP11:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8
1225 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined, i64 [[TMP9]], ptr [[TMP0]], i64 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i64 [[TMP11]])
1226 // CHECK1-NEXT:    ret void
1227 //
1228 //
1229 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined
1230 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
1231 // CHECK1-NEXT:  entry:
1232 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1233 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1234 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1235 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
1236 // CHECK1-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
1237 // CHECK1-NEXT:    [[BN_ADDR:%.*]] = alloca ptr, align 8
1238 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
1239 // CHECK1-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
1240 // CHECK1-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
1241 // CHECK1-NEXT:    [[CN_ADDR:%.*]] = alloca ptr, align 8
1242 // CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
1243 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
1244 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1245 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i8, align 1
1246 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1247 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1248 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1249 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1250 // CHECK1-NEXT:    [[IT:%.*]] = alloca i8, align 1
1251 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1252 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1253 // CHECK1-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
1254 // CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
1255 // CHECK1-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
1256 // CHECK1-NEXT:    store ptr [[BN]], ptr [[BN_ADDR]], align 8
1257 // CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
1258 // CHECK1-NEXT:    store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
1259 // CHECK1-NEXT:    store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8
1260 // CHECK1-NEXT:    store ptr [[CN]], ptr [[CN_ADDR]], align 8
1261 // CHECK1-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
1262 // CHECK1-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
1263 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
1264 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
1265 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8
1266 // CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
1267 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
1268 // CHECK1-NEXT:    [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8
1269 // CHECK1-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8
1270 // CHECK1-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8
1271 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
1272 // CHECK1-NEXT:    store i32 25, ptr [[DOTOMP_UB]], align 4
1273 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1274 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1275 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
1276 // CHECK1-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1277 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4
1278 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP10]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
1279 // CHECK1-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
1280 // CHECK1:       omp.dispatch.cond:
1281 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1282 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
1283 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1284 // CHECK1:       cond.true:
1285 // CHECK1-NEXT:    br label [[COND_END:%.*]]
1286 // CHECK1:       cond.false:
1287 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1288 // CHECK1-NEXT:    br label [[COND_END]]
1289 // CHECK1:       cond.end:
1290 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
1291 // CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
1292 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1293 // CHECK1-NEXT:    store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4
1294 // CHECK1-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1295 // CHECK1-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1296 // CHECK1-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
1297 // CHECK1-NEXT:    br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
1298 // CHECK1:       omp.dispatch.body:
1299 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1300 // CHECK1:       omp.inner.for.cond:
1301 // CHECK1-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1302 // CHECK1-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1303 // CHECK1-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
1304 // CHECK1-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1305 // CHECK1:       omp.inner.for.body:
1306 // CHECK1-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1307 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
1308 // CHECK1-NEXT:    [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
1309 // CHECK1-NEXT:    [[CONV:%.*]] = trunc i32 [[SUB]] to i8
1310 // CHECK1-NEXT:    store i8 [[CONV]], ptr [[IT]], align 1
1311 // CHECK1-NEXT:    [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4
1312 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
1313 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 4
1314 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 2
1315 // CHECK1-NEXT:    [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4
1316 // CHECK1-NEXT:    [[CONV7:%.*]] = fpext float [[TMP20]] to double
1317 // CHECK1-NEXT:    [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00
1318 // CHECK1-NEXT:    [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
1319 // CHECK1-NEXT:    store float [[CONV9]], ptr [[ARRAYIDX]], align 4
1320 // CHECK1-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 3
1321 // CHECK1-NEXT:    [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4
1322 // CHECK1-NEXT:    [[CONV11:%.*]] = fpext float [[TMP21]] to double
1323 // CHECK1-NEXT:    [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
1324 // CHECK1-NEXT:    [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
1325 // CHECK1-NEXT:    store float [[CONV13]], ptr [[ARRAYIDX10]], align 4
1326 // CHECK1-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 1
1327 // CHECK1-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i64 0, i64 2
1328 // CHECK1-NEXT:    [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8
1329 // CHECK1-NEXT:    [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
1330 // CHECK1-NEXT:    store double [[ADD16]], ptr [[ARRAYIDX15]], align 8
1331 // CHECK1-NEXT:    [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]
1332 // CHECK1-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i64 [[TMP23]]
1333 // CHECK1-NEXT:    [[ARRAYIDX18:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX17]], i64 3
1334 // CHECK1-NEXT:    [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 8
1335 // CHECK1-NEXT:    [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
1336 // CHECK1-NEXT:    store double [[ADD19]], ptr [[ARRAYIDX18]], align 8
1337 // CHECK1-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0
1338 // CHECK1-NEXT:    [[TMP25:%.*]] = load i64, ptr [[X]], align 8
1339 // CHECK1-NEXT:    [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
1340 // CHECK1-NEXT:    store i64 [[ADD20]], ptr [[X]], align 8
1341 // CHECK1-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1
1342 // CHECK1-NEXT:    [[TMP26:%.*]] = load i8, ptr [[Y]], align 8
1343 // CHECK1-NEXT:    [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
1344 // CHECK1-NEXT:    [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
1345 // CHECK1-NEXT:    [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
1346 // CHECK1-NEXT:    store i8 [[CONV23]], ptr [[Y]], align 8
1347 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1348 // CHECK1:       omp.body.continue:
1349 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1350 // CHECK1:       omp.inner.for.inc:
1351 // CHECK1-NEXT:    [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1352 // CHECK1-NEXT:    [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
1353 // CHECK1-NEXT:    store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4
1354 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]
1355 // CHECK1:       omp.inner.for.end:
1356 // CHECK1-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
1357 // CHECK1:       omp.dispatch.inc:
1358 // CHECK1-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1359 // CHECK1-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
1360 // CHECK1-NEXT:    [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
1361 // CHECK1-NEXT:    store i32 [[ADD25]], ptr [[DOTOMP_LB]], align 4
1362 // CHECK1-NEXT:    [[TMP30:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1363 // CHECK1-NEXT:    [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
1364 // CHECK1-NEXT:    [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
1365 // CHECK1-NEXT:    store i32 [[ADD26]], ptr [[DOTOMP_UB]], align 4
1366 // CHECK1-NEXT:    br label [[OMP_DISPATCH_COND]]
1367 // CHECK1:       omp.dispatch.end:
1368 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP10]])
1369 // CHECK1-NEXT:    ret void
1370 //
1371 //
1372 // CHECK1-LABEL: define {{[^@]+}}@_Z3bari
1373 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
1374 // CHECK1-NEXT:  entry:
1375 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
1376 // CHECK1-NEXT:    [[A:%.*]] = alloca i32, align 4
1377 // CHECK1-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
1378 // CHECK1-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
1379 // CHECK1-NEXT:    store i32 0, ptr [[A]], align 4
1380 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
1381 // CHECK1-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]])
1382 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A]], align 4
1383 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
1384 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[A]], align 4
1385 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
1386 // CHECK1-NEXT:    [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(ptr noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]])
1387 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A]], align 4
1388 // CHECK1-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
1389 // CHECK1-NEXT:    store i32 [[ADD2]], ptr [[A]], align 4
1390 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
1391 // CHECK1-NEXT:    [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]])
1392 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[A]], align 4
1393 // CHECK1-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
1394 // CHECK1-NEXT:    store i32 [[ADD4]], ptr [[A]], align 4
1395 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4
1396 // CHECK1-NEXT:    [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]])
1397 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[A]], align 4
1398 // CHECK1-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
1399 // CHECK1-NEXT:    store i32 [[ADD6]], ptr [[A]], align 4
1400 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A]], align 4
1401 // CHECK1-NEXT:    ret i32 [[TMP8]]
1402 //
1403 //
1404 // CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
1405 // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
1406 // CHECK1-NEXT:  entry:
1407 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1408 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
1409 // CHECK1-NEXT:    [[B:%.*]] = alloca i32, align 4
1410 // CHECK1-NEXT:    [[SAVED_STACK:%.*]] = alloca ptr, align 8
1411 // CHECK1-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
1412 // CHECK1-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
1413 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 8
1414 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 8
1415 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 8
1416 // CHECK1-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8
1417 // CHECK1-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1418 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1419 // CHECK1-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
1420 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1421 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
1422 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
1423 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[B]], align 4
1424 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
1425 // CHECK1-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
1426 // CHECK1-NEXT:    [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()
1427 // CHECK1-NEXT:    store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8
1428 // CHECK1-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
1429 // CHECK1-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
1430 // CHECK1-NEXT:    store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8
1431 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[B]], align 4
1432 // CHECK1-NEXT:    store i32 [[TMP5]], ptr [[B_CASTED]], align 4
1433 // CHECK1-NEXT:    [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 8
1434 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 4
1435 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60
1436 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
1437 // CHECK1:       omp_if.then:
1438 // CHECK1-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0
1439 // CHECK1-NEXT:    [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]]
1440 // CHECK1-NEXT:    [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2
1441 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes.5, i64 40, i1 false)
1442 // CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1443 // CHECK1-NEXT:    store ptr [[THIS1]], ptr [[TMP10]], align 8
1444 // CHECK1-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1445 // CHECK1-NEXT:    store ptr [[A]], ptr [[TMP11]], align 8
1446 // CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
1447 // CHECK1-NEXT:    store ptr null, ptr [[TMP12]], align 8
1448 // CHECK1-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1449 // CHECK1-NEXT:    store i64 [[TMP6]], ptr [[TMP13]], align 8
1450 // CHECK1-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1451 // CHECK1-NEXT:    store i64 [[TMP6]], ptr [[TMP14]], align 8
1452 // CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
1453 // CHECK1-NEXT:    store ptr null, ptr [[TMP15]], align 8
1454 // CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1455 // CHECK1-NEXT:    store i64 2, ptr [[TMP16]], align 8
1456 // CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1457 // CHECK1-NEXT:    store i64 2, ptr [[TMP17]], align 8
1458 // CHECK1-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
1459 // CHECK1-NEXT:    store ptr null, ptr [[TMP18]], align 8
1460 // CHECK1-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1461 // CHECK1-NEXT:    store i64 [[TMP2]], ptr [[TMP19]], align 8
1462 // CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1463 // CHECK1-NEXT:    store i64 [[TMP2]], ptr [[TMP20]], align 8
1464 // CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
1465 // CHECK1-NEXT:    store ptr null, ptr [[TMP21]], align 8
1466 // CHECK1-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
1467 // CHECK1-NEXT:    store ptr [[VLA]], ptr [[TMP22]], align 8
1468 // CHECK1-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4
1469 // CHECK1-NEXT:    store ptr [[VLA]], ptr [[TMP23]], align 8
1470 // CHECK1-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 4
1471 // CHECK1-NEXT:    store i64 [[TMP9]], ptr [[TMP24]], align 8
1472 // CHECK1-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
1473 // CHECK1-NEXT:    store ptr null, ptr [[TMP25]], align 8
1474 // CHECK1-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1475 // CHECK1-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1476 // CHECK1-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0
1477 // CHECK1-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
1478 // CHECK1-NEXT:    store i32 2, ptr [[TMP29]], align 4
1479 // CHECK1-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
1480 // CHECK1-NEXT:    store i32 5, ptr [[TMP30]], align 4
1481 // CHECK1-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
1482 // CHECK1-NEXT:    store ptr [[TMP26]], ptr [[TMP31]], align 8
1483 // CHECK1-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
1484 // CHECK1-NEXT:    store ptr [[TMP27]], ptr [[TMP32]], align 8
1485 // CHECK1-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
1486 // CHECK1-NEXT:    store ptr [[TMP28]], ptr [[TMP33]], align 8
1487 // CHECK1-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
1488 // CHECK1-NEXT:    store ptr @.offload_maptypes.6, ptr [[TMP34]], align 8
1489 // CHECK1-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
1490 // CHECK1-NEXT:    store ptr null, ptr [[TMP35]], align 8
1491 // CHECK1-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
1492 // CHECK1-NEXT:    store ptr null, ptr [[TMP36]], align 8
1493 // CHECK1-NEXT:    [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
1494 // CHECK1-NEXT:    store i64 0, ptr [[TMP37]], align 8
1495 // CHECK1-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
1496 // CHECK1-NEXT:    store i64 0, ptr [[TMP38]], align 8
1497 // CHECK1-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
1498 // CHECK1-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP39]], align 4
1499 // CHECK1-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
1500 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP40]], align 4
1501 // CHECK1-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
1502 // CHECK1-NEXT:    store i32 0, ptr [[TMP41]], align 4
1503 // CHECK1-NEXT:    [[TMP42:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232.region_id, ptr [[KERNEL_ARGS]])
1504 // CHECK1-NEXT:    [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0
1505 // CHECK1-NEXT:    br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1506 // CHECK1:       omp_offload.failed:
1507 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232(ptr [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], ptr [[VLA]]) #[[ATTR3]]
1508 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
1509 // CHECK1:       omp_offload.cont:
1510 // CHECK1-NEXT:    br label [[OMP_IF_END:%.*]]
1511 // CHECK1:       omp_if.else:
1512 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232(ptr [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], ptr [[VLA]]) #[[ATTR3]]
1513 // CHECK1-NEXT:    br label [[OMP_IF_END]]
1514 // CHECK1:       omp_if.end:
1515 // CHECK1-NEXT:    [[TMP44:%.*]] = mul nsw i64 1, [[TMP2]]
1516 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP44]]
1517 // CHECK1-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1
1518 // CHECK1-NEXT:    [[TMP45:%.*]] = load i16, ptr [[ARRAYIDX2]], align 2
1519 // CHECK1-NEXT:    [[CONV:%.*]] = sext i16 [[TMP45]] to i32
1520 // CHECK1-NEXT:    [[TMP46:%.*]] = load i32, ptr [[B]], align 4
1521 // CHECK1-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP46]]
1522 // CHECK1-NEXT:    [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
1523 // CHECK1-NEXT:    call void @llvm.stackrestore.p0(ptr [[TMP47]])
1524 // CHECK1-NEXT:    ret i32 [[ADD3]]
1525 //
1526 //
1527 // CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici
1528 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
1529 // CHECK1-NEXT:  entry:
1530 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
1531 // CHECK1-NEXT:    [[A:%.*]] = alloca i32, align 4
1532 // CHECK1-NEXT:    [[AA:%.*]] = alloca i16, align 2
1533 // CHECK1-NEXT:    [[AAA:%.*]] = alloca i8, align 1
1534 // CHECK1-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
1535 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
1536 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
1537 // CHECK1-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
1538 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 8
1539 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 8
1540 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 8
1541 // CHECK1-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1542 // CHECK1-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
1543 // CHECK1-NEXT:    store i32 0, ptr [[A]], align 4
1544 // CHECK1-NEXT:    store i16 0, ptr [[AA]], align 2
1545 // CHECK1-NEXT:    store i8 0, ptr [[AAA]], align 1
1546 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A]], align 4
1547 // CHECK1-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 4
1548 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8
1549 // CHECK1-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA]], align 2
1550 // CHECK1-NEXT:    store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
1551 // CHECK1-NEXT:    [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8
1552 // CHECK1-NEXT:    [[TMP4:%.*]] = load i8, ptr [[AAA]], align 1
1553 // CHECK1-NEXT:    store i8 [[TMP4]], ptr [[AAA_CASTED]], align 1
1554 // CHECK1-NEXT:    [[TMP5:%.*]] = load i64, ptr [[AAA_CASTED]], align 8
1555 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4
1556 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50
1557 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
1558 // CHECK1:       omp_if.then:
1559 // CHECK1-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1560 // CHECK1-NEXT:    store i64 [[TMP1]], ptr [[TMP7]], align 8
1561 // CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1562 // CHECK1-NEXT:    store i64 [[TMP1]], ptr [[TMP8]], align 8
1563 // CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
1564 // CHECK1-NEXT:    store ptr null, ptr [[TMP9]], align 8
1565 // CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1566 // CHECK1-NEXT:    store i64 [[TMP3]], ptr [[TMP10]], align 8
1567 // CHECK1-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1568 // CHECK1-NEXT:    store i64 [[TMP3]], ptr [[TMP11]], align 8
1569 // CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
1570 // CHECK1-NEXT:    store ptr null, ptr [[TMP12]], align 8
1571 // CHECK1-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1572 // CHECK1-NEXT:    store i64 [[TMP5]], ptr [[TMP13]], align 8
1573 // CHECK1-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1574 // CHECK1-NEXT:    store i64 [[TMP5]], ptr [[TMP14]], align 8
1575 // CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
1576 // CHECK1-NEXT:    store ptr null, ptr [[TMP15]], align 8
1577 // CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1578 // CHECK1-NEXT:    store ptr [[B]], ptr [[TMP16]], align 8
1579 // CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1580 // CHECK1-NEXT:    store ptr [[B]], ptr [[TMP17]], align 8
1581 // CHECK1-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
1582 // CHECK1-NEXT:    store ptr null, ptr [[TMP18]], align 8
1583 // CHECK1-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1584 // CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1585 // CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
1586 // CHECK1-NEXT:    store i32 2, ptr [[TMP21]], align 4
1587 // CHECK1-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
1588 // CHECK1-NEXT:    store i32 4, ptr [[TMP22]], align 4
1589 // CHECK1-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
1590 // CHECK1-NEXT:    store ptr [[TMP19]], ptr [[TMP23]], align 8
1591 // CHECK1-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
1592 // CHECK1-NEXT:    store ptr [[TMP20]], ptr [[TMP24]], align 8
1593 // CHECK1-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
1594 // CHECK1-NEXT:    store ptr @.offload_sizes.7, ptr [[TMP25]], align 8
1595 // CHECK1-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
1596 // CHECK1-NEXT:    store ptr @.offload_maptypes.8, ptr [[TMP26]], align 8
1597 // CHECK1-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
1598 // CHECK1-NEXT:    store ptr null, ptr [[TMP27]], align 8
1599 // CHECK1-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
1600 // CHECK1-NEXT:    store ptr null, ptr [[TMP28]], align 8
1601 // CHECK1-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
1602 // CHECK1-NEXT:    store i64 0, ptr [[TMP29]], align 8
1603 // CHECK1-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
1604 // CHECK1-NEXT:    store i64 0, ptr [[TMP30]], align 8
1605 // CHECK1-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
1606 // CHECK1-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP31]], align 4
1607 // CHECK1-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
1608 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP32]], align 4
1609 // CHECK1-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
1610 // CHECK1-NEXT:    store i32 0, ptr [[TMP33]], align 4
1611 // CHECK1-NEXT:    [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214.region_id, ptr [[KERNEL_ARGS]])
1612 // CHECK1-NEXT:    [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0
1613 // CHECK1-NEXT:    br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1614 // CHECK1:       omp_offload.failed:
1615 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], ptr [[B]]) #[[ATTR3]]
1616 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
1617 // CHECK1:       omp_offload.cont:
1618 // CHECK1-NEXT:    br label [[OMP_IF_END:%.*]]
1619 // CHECK1:       omp_if.else:
1620 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], ptr [[B]]) #[[ATTR3]]
1621 // CHECK1-NEXT:    br label [[OMP_IF_END]]
1622 // CHECK1:       omp_if.end:
1623 // CHECK1-NEXT:    [[TMP36:%.*]] = load i32, ptr [[A]], align 4
1624 // CHECK1-NEXT:    ret i32 [[TMP36]]
1625 //
1626 //
1627 // CHECK1-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
1628 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
1629 // CHECK1-NEXT:  entry:
1630 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
1631 // CHECK1-NEXT:    [[A:%.*]] = alloca i32, align 4
1632 // CHECK1-NEXT:    [[AA:%.*]] = alloca i16, align 2
1633 // CHECK1-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
1634 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
1635 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
1636 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8
1637 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 8
1638 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 8
1639 // CHECK1-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1640 // CHECK1-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
1641 // CHECK1-NEXT:    store i32 0, ptr [[A]], align 4
1642 // CHECK1-NEXT:    store i16 0, ptr [[AA]], align 2
1643 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A]], align 4
1644 // CHECK1-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 4
1645 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8
1646 // CHECK1-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA]], align 2
1647 // CHECK1-NEXT:    store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
1648 // CHECK1-NEXT:    [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8
1649 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
1650 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
1651 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
1652 // CHECK1:       omp_if.then:
1653 // CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1654 // CHECK1-NEXT:    store i64 [[TMP1]], ptr [[TMP5]], align 8
1655 // CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1656 // CHECK1-NEXT:    store i64 [[TMP1]], ptr [[TMP6]], align 8
1657 // CHECK1-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
1658 // CHECK1-NEXT:    store ptr null, ptr [[TMP7]], align 8
1659 // CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1660 // CHECK1-NEXT:    store i64 [[TMP3]], ptr [[TMP8]], align 8
1661 // CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1662 // CHECK1-NEXT:    store i64 [[TMP3]], ptr [[TMP9]], align 8
1663 // CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
1664 // CHECK1-NEXT:    store ptr null, ptr [[TMP10]], align 8
1665 // CHECK1-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1666 // CHECK1-NEXT:    store ptr [[B]], ptr [[TMP11]], align 8
1667 // CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1668 // CHECK1-NEXT:    store ptr [[B]], ptr [[TMP12]], align 8
1669 // CHECK1-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
1670 // CHECK1-NEXT:    store ptr null, ptr [[TMP13]], align 8
1671 // CHECK1-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1672 // CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1673 // CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
1674 // CHECK1-NEXT:    store i32 2, ptr [[TMP16]], align 4
1675 // CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
1676 // CHECK1-NEXT:    store i32 3, ptr [[TMP17]], align 4
1677 // CHECK1-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
1678 // CHECK1-NEXT:    store ptr [[TMP14]], ptr [[TMP18]], align 8
1679 // CHECK1-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
1680 // CHECK1-NEXT:    store ptr [[TMP15]], ptr [[TMP19]], align 8
1681 // CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
1682 // CHECK1-NEXT:    store ptr @.offload_sizes.9, ptr [[TMP20]], align 8
1683 // CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
1684 // CHECK1-NEXT:    store ptr @.offload_maptypes.10, ptr [[TMP21]], align 8
1685 // CHECK1-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
1686 // CHECK1-NEXT:    store ptr null, ptr [[TMP22]], align 8
1687 // CHECK1-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
1688 // CHECK1-NEXT:    store ptr null, ptr [[TMP23]], align 8
1689 // CHECK1-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
1690 // CHECK1-NEXT:    store i64 0, ptr [[TMP24]], align 8
1691 // CHECK1-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
1692 // CHECK1-NEXT:    store i64 0, ptr [[TMP25]], align 8
1693 // CHECK1-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
1694 // CHECK1-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP26]], align 4
1695 // CHECK1-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
1696 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP27]], align 4
1697 // CHECK1-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
1698 // CHECK1-NEXT:    store i32 0, ptr [[TMP28]], align 4
1699 // CHECK1-NEXT:    [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197.region_id, ptr [[KERNEL_ARGS]])
1700 // CHECK1-NEXT:    [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
1701 // CHECK1-NEXT:    br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1702 // CHECK1:       omp_offload.failed:
1703 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR3]]
1704 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
1705 // CHECK1:       omp_offload.cont:
1706 // CHECK1-NEXT:    br label [[OMP_IF_END:%.*]]
1707 // CHECK1:       omp_if.else:
1708 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR3]]
1709 // CHECK1-NEXT:    br label [[OMP_IF_END]]
1710 // CHECK1:       omp_if.end:
1711 // CHECK1-NEXT:    [[TMP31:%.*]] = load i32, ptr [[A]], align 4
1712 // CHECK1-NEXT:    ret i32 [[TMP31]]
1713 //
1714 //
1715 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232
1716 // CHECK1-SAME: (ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
1717 // CHECK1-NEXT:  entry:
1718 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1719 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
1720 // CHECK1-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
1721 // CHECK1-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
1722 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
1723 // CHECK1-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
1724 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1725 // CHECK1-NEXT:    store i64 [[B]], ptr [[B_ADDR]], align 8
1726 // CHECK1-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
1727 // CHECK1-NEXT:    store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
1728 // CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
1729 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1730 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
1731 // CHECK1-NEXT:    [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
1732 // CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
1733 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4
1734 // CHECK1-NEXT:    store i32 [[TMP4]], ptr [[B_CASTED]], align 4
1735 // CHECK1-NEXT:    [[TMP5:%.*]] = load i64, ptr [[B_CASTED]], align 8
1736 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232.omp_outlined, ptr [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], ptr [[TMP3]])
1737 // CHECK1-NEXT:    ret void
1738 //
1739 //
1740 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232.omp_outlined
1741 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
1742 // CHECK1-NEXT:  entry:
1743 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1744 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1745 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1746 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
1747 // CHECK1-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
1748 // CHECK1-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
1749 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
1750 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
1751 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i64, align 8
1752 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
1753 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
1754 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
1755 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1756 // CHECK1-NEXT:    [[IT:%.*]] = alloca i64, align 8
1757 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1758 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1759 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1760 // CHECK1-NEXT:    store i64 [[B]], ptr [[B_ADDR]], align 8
1761 // CHECK1-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
1762 // CHECK1-NEXT:    store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
1763 // CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
1764 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1765 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
1766 // CHECK1-NEXT:    [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
1767 // CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
1768 // CHECK1-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8
1769 // CHECK1-NEXT:    store i64 3, ptr [[DOTOMP_UB]], align 8
1770 // CHECK1-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8
1771 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1772 // CHECK1-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1773 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
1774 // CHECK1-NEXT:    call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP5]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
1775 // CHECK1-NEXT:    [[TMP6:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
1776 // CHECK1-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3
1777 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1778 // CHECK1:       cond.true:
1779 // CHECK1-NEXT:    br label [[COND_END:%.*]]
1780 // CHECK1:       cond.false:
1781 // CHECK1-NEXT:    [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
1782 // CHECK1-NEXT:    br label [[COND_END]]
1783 // CHECK1:       cond.end:
1784 // CHECK1-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
1785 // CHECK1-NEXT:    store i64 [[COND]], ptr [[DOTOMP_UB]], align 8
1786 // CHECK1-NEXT:    [[TMP8:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
1787 // CHECK1-NEXT:    store i64 [[TMP8]], ptr [[DOTOMP_IV]], align 8
1788 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1789 // CHECK1:       omp.inner.for.cond:
1790 // CHECK1-NEXT:    [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
1791 // CHECK1-NEXT:    [[TMP10:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
1792 // CHECK1-NEXT:    [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
1793 // CHECK1-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1794 // CHECK1:       omp.inner.for.body:
1795 // CHECK1-NEXT:    [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
1796 // CHECK1-NEXT:    [[MUL:%.*]] = mul i64 [[TMP11]], 400
1797 // CHECK1-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
1798 // CHECK1-NEXT:    store i64 [[SUB]], ptr [[IT]], align 8
1799 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[B_ADDR]], align 4
1800 // CHECK1-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP12]] to double
1801 // CHECK1-NEXT:    [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
1802 // CHECK1-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0
1803 // CHECK1-NEXT:    store double [[ADD]], ptr [[A]], align 8
1804 // CHECK1-NEXT:    [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0
1805 // CHECK1-NEXT:    [[TMP13:%.*]] = load double, ptr [[A4]], align 8
1806 // CHECK1-NEXT:    [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
1807 // CHECK1-NEXT:    store double [[INC]], ptr [[A4]], align 8
1808 // CHECK1-NEXT:    [[CONV5:%.*]] = fptosi double [[INC]] to i16
1809 // CHECK1-NEXT:    [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]]
1810 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i64 [[TMP14]]
1811 // CHECK1-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1
1812 // CHECK1-NEXT:    store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2
1813 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1814 // CHECK1:       omp.body.continue:
1815 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1816 // CHECK1:       omp.inner.for.inc:
1817 // CHECK1-NEXT:    [[TMP15:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
1818 // CHECK1-NEXT:    [[ADD7:%.*]] = add i64 [[TMP15]], 1
1819 // CHECK1-NEXT:    store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8
1820 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]
1821 // CHECK1:       omp.inner.for.end:
1822 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1823 // CHECK1:       omp.loop.exit:
1824 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])
1825 // CHECK1-NEXT:    ret void
1826 //
1827 //
1828 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214
1829 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
1830 // CHECK1-NEXT:  entry:
1831 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1832 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
1833 // CHECK1-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
1834 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
1835 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
1836 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
1837 // CHECK1-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
1838 // CHECK1-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
1839 // CHECK1-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
1840 // CHECK1-NEXT:    store i64 [[AAA]], ptr [[AAA_ADDR]], align 8
1841 // CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
1842 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
1843 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
1844 // CHECK1-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 4
1845 // CHECK1-NEXT:    [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8
1846 // CHECK1-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
1847 // CHECK1-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
1848 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8
1849 // CHECK1-NEXT:    [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 1
1850 // CHECK1-NEXT:    store i8 [[TMP5]], ptr [[AAA_CASTED]], align 1
1851 // CHECK1-NEXT:    [[TMP6:%.*]] = load i64, ptr [[AAA_CASTED]], align 8
1852 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], ptr [[TMP0]])
1853 // CHECK1-NEXT:    ret void
1854 //
1855 //
1856 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214.omp_outlined
1857 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
1858 // CHECK1-NEXT:  entry:
1859 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1860 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1861 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1862 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
1863 // CHECK1-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
1864 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
1865 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1866 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1867 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1868 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1869 // CHECK1-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
1870 // CHECK1-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
1871 // CHECK1-NEXT:    store i64 [[AAA]], ptr [[AAA_ADDR]], align 8
1872 // CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
1873 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
1874 // CHECK1-NEXT:    ret void
1875 //
1876 //
1877 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197
1878 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
1879 // CHECK1-NEXT:  entry:
1880 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1881 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
1882 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
1883 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
1884 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
1885 // CHECK1-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
1886 // CHECK1-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
1887 // CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
1888 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
1889 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
1890 // CHECK1-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 4
1891 // CHECK1-NEXT:    [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8
1892 // CHECK1-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
1893 // CHECK1-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
1894 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8
1895 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], ptr [[TMP0]])
1896 // CHECK1-NEXT:    ret void
1897 //
1898 //
1899 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197.omp_outlined
1900 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
1901 // CHECK1-NEXT:  entry:
1902 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1903 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1904 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1905 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
1906 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
1907 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
1908 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i64, align 8
1909 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
1910 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
1911 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
1912 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1913 // CHECK1-NEXT:    [[I:%.*]] = alloca i64, align 8
1914 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1915 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1916 // CHECK1-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
1917 // CHECK1-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
1918 // CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
1919 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
1920 // CHECK1-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8
1921 // CHECK1-NEXT:    store i64 6, ptr [[DOTOMP_UB]], align 8
1922 // CHECK1-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8
1923 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1924 // CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1925 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
1926 // CHECK1-NEXT:    call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP2]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
1927 // CHECK1-NEXT:    [[TMP3:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
1928 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
1929 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1930 // CHECK1:       cond.true:
1931 // CHECK1-NEXT:    br label [[COND_END:%.*]]
1932 // CHECK1:       cond.false:
1933 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
1934 // CHECK1-NEXT:    br label [[COND_END]]
1935 // CHECK1:       cond.end:
1936 // CHECK1-NEXT:    [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
1937 // CHECK1-NEXT:    store i64 [[COND]], ptr [[DOTOMP_UB]], align 8
1938 // CHECK1-NEXT:    [[TMP5:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
1939 // CHECK1-NEXT:    store i64 [[TMP5]], ptr [[DOTOMP_IV]], align 8
1940 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1941 // CHECK1:       omp.inner.for.cond:
1942 // CHECK1-NEXT:    [[TMP6:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
1943 // CHECK1-NEXT:    [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
1944 // CHECK1-NEXT:    [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
1945 // CHECK1-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1946 // CHECK1:       omp.inner.for.body:
1947 // CHECK1-NEXT:    [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
1948 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
1949 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
1950 // CHECK1-NEXT:    store i64 [[ADD]], ptr [[I]], align 8
1951 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4
1952 // CHECK1-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
1953 // CHECK1-NEXT:    store i32 [[ADD2]], ptr [[A_ADDR]], align 4
1954 // CHECK1-NEXT:    [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2
1955 // CHECK1-NEXT:    [[CONV:%.*]] = sext i16 [[TMP10]] to i32
1956 // CHECK1-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV]], 1
1957 // CHECK1-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
1958 // CHECK1-NEXT:    store i16 [[CONV4]], ptr [[AA_ADDR]], align 2
1959 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2
1960 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
1961 // CHECK1-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1
1962 // CHECK1-NEXT:    store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4
1963 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1964 // CHECK1:       omp.body.continue:
1965 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1966 // CHECK1:       omp.inner.for.inc:
1967 // CHECK1-NEXT:    [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
1968 // CHECK1-NEXT:    [[ADD6:%.*]] = add nsw i64 [[TMP12]], 1
1969 // CHECK1-NEXT:    store i64 [[ADD6]], ptr [[DOTOMP_IV]], align 8
1970 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]
1971 // CHECK1:       omp.inner.for.end:
1972 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1973 // CHECK1:       omp.loop.exit:
1974 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])
1975 // CHECK1-NEXT:    ret void
1976 //
1977 //
1978 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
1979 // CHECK1-SAME: () #[[ATTR5]] {
1980 // CHECK1-NEXT:  entry:
1981 // CHECK1-NEXT:    call void @__tgt_register_requires(i64 1)
1982 // CHECK1-NEXT:    ret void
1983 //
1984 //
1985 // CHECK3-LABEL: define {{[^@]+}}@_Z7get_valv
1986 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] {
1987 // CHECK3-NEXT:  entry:
1988 // CHECK3-NEXT:    ret i64 0
1989 //
1990 //
1991 // CHECK3-LABEL: define {{[^@]+}}@_Z3fooi
1992 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
1993 // CHECK3-NEXT:  entry:
1994 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
1995 // CHECK3-NEXT:    [[A:%.*]] = alloca i32, align 4
1996 // CHECK3-NEXT:    [[AA:%.*]] = alloca i16, align 2
1997 // CHECK3-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
1998 // CHECK3-NEXT:    [[SAVED_STACK:%.*]] = alloca ptr, align 4
1999 // CHECK3-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
2000 // CHECK3-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
2001 // CHECK3-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
2002 // CHECK3-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
2003 // CHECK3-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
2004 // CHECK3-NEXT:    [[K:%.*]] = alloca i64, align 8
2005 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
2006 // CHECK3-NEXT:    [[LIN:%.*]] = alloca i32, align 4
2007 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
2008 // CHECK3-NEXT:    [[LIN_CASTED:%.*]] = alloca i32, align 4
2009 // CHECK3-NEXT:    [[A_CASTED2:%.*]] = alloca i32, align 4
2010 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 4
2011 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 4
2012 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 4
2013 // CHECK3-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4
2014 // CHECK3-NEXT:    [[A_CASTED3:%.*]] = alloca i32, align 4
2015 // CHECK3-NEXT:    [[AA_CASTED4:%.*]] = alloca i32, align 4
2016 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [2 x ptr], align 4
2017 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS6:%.*]] = alloca [2 x ptr], align 4
2018 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [2 x ptr], align 4
2019 // CHECK3-NEXT:    [[KERNEL_ARGS8:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
2020 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
2021 // CHECK3-NEXT:    [[A_CASTED11:%.*]] = alloca i32, align 4
2022 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
2023 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [10 x ptr], align 4
2024 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS15:%.*]] = alloca [10 x ptr], align 4
2025 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [10 x ptr], align 4
2026 // CHECK3-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4
2027 // CHECK3-NEXT:    [[KERNEL_ARGS17:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
2028 // CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])
2029 // CHECK3-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
2030 // CHECK3-NEXT:    store i32 0, ptr [[A]], align 4
2031 // CHECK3-NEXT:    store i16 0, ptr [[AA]], align 2
2032 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
2033 // CHECK3-NEXT:    [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
2034 // CHECK3-NEXT:    store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4
2035 // CHECK3-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4
2036 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4
2037 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4
2038 // CHECK3-NEXT:    [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]]
2039 // CHECK3-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8
2040 // CHECK3-NEXT:    store i32 [[TMP3]], ptr [[__VLA_EXPR1]], align 4
2041 // CHECK3-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
2042 // CHECK3-NEXT:    store i32 2, ptr [[TMP5]], align 4
2043 // CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
2044 // CHECK3-NEXT:    store i32 0, ptr [[TMP6]], align 4
2045 // CHECK3-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
2046 // CHECK3-NEXT:    store ptr null, ptr [[TMP7]], align 4
2047 // CHECK3-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
2048 // CHECK3-NEXT:    store ptr null, ptr [[TMP8]], align 4
2049 // CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
2050 // CHECK3-NEXT:    store ptr null, ptr [[TMP9]], align 4
2051 // CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
2052 // CHECK3-NEXT:    store ptr null, ptr [[TMP10]], align 4
2053 // CHECK3-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
2054 // CHECK3-NEXT:    store ptr null, ptr [[TMP11]], align 4
2055 // CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
2056 // CHECK3-NEXT:    store ptr null, ptr [[TMP12]], align 4
2057 // CHECK3-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
2058 // CHECK3-NEXT:    store i64 0, ptr [[TMP13]], align 8
2059 // CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
2060 // CHECK3-NEXT:    store i64 0, ptr [[TMP14]], align 8
2061 // CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
2062 // CHECK3-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP15]], align 4
2063 // CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
2064 // CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP16]], align 4
2065 // CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
2066 // CHECK3-NEXT:    store i32 0, ptr [[TMP17]], align 4
2067 // CHECK3-NEXT:    [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, ptr [[KERNEL_ARGS]])
2068 // CHECK3-NEXT:    [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
2069 // CHECK3-NEXT:    br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
2070 // CHECK3:       omp_offload.failed:
2071 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR3:[0-9]+]]
2072 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]
2073 // CHECK3:       omp_offload.cont:
2074 // CHECK3-NEXT:    [[CALL:%.*]] = call noundef i64 @_Z7get_valv()
2075 // CHECK3-NEXT:    store i64 [[CALL]], ptr [[K]], align 8
2076 // CHECK3-NEXT:    [[TMP20:%.*]] = load i32, ptr [[A]], align 4
2077 // CHECK3-NEXT:    store i32 [[TMP20]], ptr [[A_CASTED]], align 4
2078 // CHECK3-NEXT:    [[TMP21:%.*]] = load i32, ptr [[A_CASTED]], align 4
2079 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i32 [[TMP21]], ptr [[K]]) #[[ATTR3]]
2080 // CHECK3-NEXT:    store i32 12, ptr [[LIN]], align 4
2081 // CHECK3-NEXT:    [[TMP22:%.*]] = load i16, ptr [[AA]], align 2
2082 // CHECK3-NEXT:    store i16 [[TMP22]], ptr [[AA_CASTED]], align 2
2083 // CHECK3-NEXT:    [[TMP23:%.*]] = load i32, ptr [[AA_CASTED]], align 4
2084 // CHECK3-NEXT:    [[TMP24:%.*]] = load i32, ptr [[LIN]], align 4
2085 // CHECK3-NEXT:    store i32 [[TMP24]], ptr [[LIN_CASTED]], align 4
2086 // CHECK3-NEXT:    [[TMP25:%.*]] = load i32, ptr [[LIN_CASTED]], align 4
2087 // CHECK3-NEXT:    [[TMP26:%.*]] = load i32, ptr [[A]], align 4
2088 // CHECK3-NEXT:    store i32 [[TMP26]], ptr [[A_CASTED2]], align 4
2089 // CHECK3-NEXT:    [[TMP27:%.*]] = load i32, ptr [[A_CASTED2]], align 4
2090 // CHECK3-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2091 // CHECK3-NEXT:    store i32 [[TMP23]], ptr [[TMP28]], align 4
2092 // CHECK3-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2093 // CHECK3-NEXT:    store i32 [[TMP23]], ptr [[TMP29]], align 4
2094 // CHECK3-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
2095 // CHECK3-NEXT:    store ptr null, ptr [[TMP30]], align 4
2096 // CHECK3-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
2097 // CHECK3-NEXT:    store i32 [[TMP25]], ptr [[TMP31]], align 4
2098 // CHECK3-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
2099 // CHECK3-NEXT:    store i32 [[TMP25]], ptr [[TMP32]], align 4
2100 // CHECK3-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
2101 // CHECK3-NEXT:    store ptr null, ptr [[TMP33]], align 4
2102 // CHECK3-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
2103 // CHECK3-NEXT:    store i32 [[TMP27]], ptr [[TMP34]], align 4
2104 // CHECK3-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
2105 // CHECK3-NEXT:    store i32 [[TMP27]], ptr [[TMP35]], align 4
2106 // CHECK3-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
2107 // CHECK3-NEXT:    store ptr null, ptr [[TMP36]], align 4
2108 // CHECK3-NEXT:    [[TMP37:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2109 // CHECK3-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2110 // CHECK3-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0
2111 // CHECK3-NEXT:    [[TMP40:%.*]] = load i16, ptr [[AA]], align 2
2112 // CHECK3-NEXT:    store i16 [[TMP40]], ptr [[TMP39]], align 4
2113 // CHECK3-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 1
2114 // CHECK3-NEXT:    [[TMP42:%.*]] = load i32, ptr [[LIN]], align 4
2115 // CHECK3-NEXT:    store i32 [[TMP42]], ptr [[TMP41]], align 4
2116 // CHECK3-NEXT:    [[TMP43:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 2
2117 // CHECK3-NEXT:    [[TMP44:%.*]] = load i32, ptr [[A]], align 4
2118 // CHECK3-NEXT:    store i32 [[TMP44]], ptr [[TMP43]], align 4
2119 // CHECK3-NEXT:    [[TMP45:%.*]] = call ptr @__kmpc_omp_target_task_alloc(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 72, i32 12, ptr @.omp_task_entry., i64 -1)
2120 // CHECK3-NEXT:    [[TMP46:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP45]], i32 0, i32 0
2121 // CHECK3-NEXT:    [[TMP47:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP46]], i32 0, i32 0
2122 // CHECK3-NEXT:    [[TMP48:%.*]] = load ptr, ptr [[TMP47]], align 4
2123 // CHECK3-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP48]], ptr align 4 [[AGG_CAPTURED]], i32 12, i1 false)
2124 // CHECK3-NEXT:    [[TMP49:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP45]], i32 0, i32 1
2125 // CHECK3-NEXT:    [[TMP50:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP49]], i32 0, i32 0
2126 // CHECK3-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP50]], ptr align 4 @.offload_sizes, i32 24, i1 false)
2127 // CHECK3-NEXT:    [[TMP51:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP49]], i32 0, i32 1
2128 // CHECK3-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP51]], ptr align 4 [[TMP37]], i32 12, i1 false)
2129 // CHECK3-NEXT:    [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP49]], i32 0, i32 2
2130 // CHECK3-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP52]], ptr align 4 [[TMP38]], i32 12, i1 false)
2131 // CHECK3-NEXT:    [[TMP53:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP49]], i32 0, i32 3
2132 // CHECK3-NEXT:    [[TMP54:%.*]] = load i16, ptr [[AA]], align 2
2133 // CHECK3-NEXT:    store i16 [[TMP54]], ptr [[TMP53]], align 4
2134 // CHECK3-NEXT:    [[TMP55:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB2]], i32 [[TMP0]], ptr [[TMP45]])
2135 // CHECK3-NEXT:    [[TMP56:%.*]] = load i32, ptr [[A]], align 4
2136 // CHECK3-NEXT:    store i32 [[TMP56]], ptr [[A_CASTED3]], align 4
2137 // CHECK3-NEXT:    [[TMP57:%.*]] = load i32, ptr [[A_CASTED3]], align 4
2138 // CHECK3-NEXT:    [[TMP58:%.*]] = load i16, ptr [[AA]], align 2
2139 // CHECK3-NEXT:    store i16 [[TMP58]], ptr [[AA_CASTED4]], align 2
2140 // CHECK3-NEXT:    [[TMP59:%.*]] = load i32, ptr [[AA_CASTED4]], align 4
2141 // CHECK3-NEXT:    [[TMP60:%.*]] = load i32, ptr [[N_ADDR]], align 4
2142 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP60]], 10
2143 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
2144 // CHECK3:       omp_if.then:
2145 // CHECK3-NEXT:    [[TMP61:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0
2146 // CHECK3-NEXT:    store i32 [[TMP57]], ptr [[TMP61]], align 4
2147 // CHECK3-NEXT:    [[TMP62:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0
2148 // CHECK3-NEXT:    store i32 [[TMP57]], ptr [[TMP62]], align 4
2149 // CHECK3-NEXT:    [[TMP63:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 0
2150 // CHECK3-NEXT:    store ptr null, ptr [[TMP63]], align 4
2151 // CHECK3-NEXT:    [[TMP64:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1
2152 // CHECK3-NEXT:    store i32 [[TMP59]], ptr [[TMP64]], align 4
2153 // CHECK3-NEXT:    [[TMP65:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 1
2154 // CHECK3-NEXT:    store i32 [[TMP59]], ptr [[TMP65]], align 4
2155 // CHECK3-NEXT:    [[TMP66:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 1
2156 // CHECK3-NEXT:    store ptr null, ptr [[TMP66]], align 4
2157 // CHECK3-NEXT:    [[TMP67:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0
2158 // CHECK3-NEXT:    [[TMP68:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0
2159 // CHECK3-NEXT:    [[TMP69:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 0
2160 // CHECK3-NEXT:    store i32 2, ptr [[TMP69]], align 4
2161 // CHECK3-NEXT:    [[TMP70:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 1
2162 // CHECK3-NEXT:    store i32 2, ptr [[TMP70]], align 4
2163 // CHECK3-NEXT:    [[TMP71:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 2
2164 // CHECK3-NEXT:    store ptr [[TMP67]], ptr [[TMP71]], align 4
2165 // CHECK3-NEXT:    [[TMP72:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 3
2166 // CHECK3-NEXT:    store ptr [[TMP68]], ptr [[TMP72]], align 4
2167 // CHECK3-NEXT:    [[TMP73:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 4
2168 // CHECK3-NEXT:    store ptr @.offload_sizes.1, ptr [[TMP73]], align 4
2169 // CHECK3-NEXT:    [[TMP74:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 5
2170 // CHECK3-NEXT:    store ptr @.offload_maptypes.2, ptr [[TMP74]], align 4
2171 // CHECK3-NEXT:    [[TMP75:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 6
2172 // CHECK3-NEXT:    store ptr null, ptr [[TMP75]], align 4
2173 // CHECK3-NEXT:    [[TMP76:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 7
2174 // CHECK3-NEXT:    store ptr null, ptr [[TMP76]], align 4
2175 // CHECK3-NEXT:    [[TMP77:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 8
2176 // CHECK3-NEXT:    store i64 0, ptr [[TMP77]], align 8
2177 // CHECK3-NEXT:    [[TMP78:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 9
2178 // CHECK3-NEXT:    store i64 0, ptr [[TMP78]], align 8
2179 // CHECK3-NEXT:    [[TMP79:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 10
2180 // CHECK3-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP79]], align 4
2181 // CHECK3-NEXT:    [[TMP80:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 11
2182 // CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP80]], align 4
2183 // CHECK3-NEXT:    [[TMP81:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 12
2184 // CHECK3-NEXT:    store i32 0, ptr [[TMP81]], align 4
2185 // CHECK3-NEXT:    [[TMP82:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.region_id, ptr [[KERNEL_ARGS8]])
2186 // CHECK3-NEXT:    [[TMP83:%.*]] = icmp ne i32 [[TMP82]], 0
2187 // CHECK3-NEXT:    br i1 [[TMP83]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]]
2188 // CHECK3:       omp_offload.failed9:
2189 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136(i32 [[TMP57]], i32 [[TMP59]]) #[[ATTR3]]
2190 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT10]]
2191 // CHECK3:       omp_offload.cont10:
2192 // CHECK3-NEXT:    br label [[OMP_IF_END:%.*]]
2193 // CHECK3:       omp_if.else:
2194 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136(i32 [[TMP57]], i32 [[TMP59]]) #[[ATTR3]]
2195 // CHECK3-NEXT:    br label [[OMP_IF_END]]
2196 // CHECK3:       omp_if.end:
2197 // CHECK3-NEXT:    [[TMP84:%.*]] = load i32, ptr [[A]], align 4
2198 // CHECK3-NEXT:    store i32 [[TMP84]], ptr [[DOTCAPTURE_EXPR_]], align 4
2199 // CHECK3-NEXT:    [[TMP85:%.*]] = load i32, ptr [[A]], align 4
2200 // CHECK3-NEXT:    store i32 [[TMP85]], ptr [[A_CASTED11]], align 4
2201 // CHECK3-NEXT:    [[TMP86:%.*]] = load i32, ptr [[A_CASTED11]], align 4
2202 // CHECK3-NEXT:    [[TMP87:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
2203 // CHECK3-NEXT:    store i32 [[TMP87]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
2204 // CHECK3-NEXT:    [[TMP88:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
2205 // CHECK3-NEXT:    [[TMP89:%.*]] = load i32, ptr [[N_ADDR]], align 4
2206 // CHECK3-NEXT:    [[CMP12:%.*]] = icmp sgt i32 [[TMP89]], 20
2207 // CHECK3-NEXT:    br i1 [[CMP12]], label [[OMP_IF_THEN13:%.*]], label [[OMP_IF_ELSE20:%.*]]
2208 // CHECK3:       omp_if.then13:
2209 // CHECK3-NEXT:    [[TMP90:%.*]] = mul nuw i32 [[TMP1]], 4
2210 // CHECK3-NEXT:    [[TMP91:%.*]] = sext i32 [[TMP90]] to i64
2211 // CHECK3-NEXT:    [[TMP92:%.*]] = mul nuw i32 5, [[TMP3]]
2212 // CHECK3-NEXT:    [[TMP93:%.*]] = mul nuw i32 [[TMP92]], 8
2213 // CHECK3-NEXT:    [[TMP94:%.*]] = sext i32 [[TMP93]] to i64
2214 // CHECK3-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes.3, i32 80, i1 false)
2215 // CHECK3-NEXT:    [[TMP95:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0
2216 // CHECK3-NEXT:    store i32 [[TMP86]], ptr [[TMP95]], align 4
2217 // CHECK3-NEXT:    [[TMP96:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 0
2218 // CHECK3-NEXT:    store i32 [[TMP86]], ptr [[TMP96]], align 4
2219 // CHECK3-NEXT:    [[TMP97:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 0
2220 // CHECK3-NEXT:    store ptr null, ptr [[TMP97]], align 4
2221 // CHECK3-NEXT:    [[TMP98:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 1
2222 // CHECK3-NEXT:    store ptr [[B]], ptr [[TMP98]], align 4
2223 // CHECK3-NEXT:    [[TMP99:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 1
2224 // CHECK3-NEXT:    store ptr [[B]], ptr [[TMP99]], align 4
2225 // CHECK3-NEXT:    [[TMP100:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 1
2226 // CHECK3-NEXT:    store ptr null, ptr [[TMP100]], align 4
2227 // CHECK3-NEXT:    [[TMP101:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 2
2228 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[TMP101]], align 4
2229 // CHECK3-NEXT:    [[TMP102:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 2
2230 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[TMP102]], align 4
2231 // CHECK3-NEXT:    [[TMP103:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 2
2232 // CHECK3-NEXT:    store ptr null, ptr [[TMP103]], align 4
2233 // CHECK3-NEXT:    [[TMP104:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 3
2234 // CHECK3-NEXT:    store ptr [[VLA]], ptr [[TMP104]], align 4
2235 // CHECK3-NEXT:    [[TMP105:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 3
2236 // CHECK3-NEXT:    store ptr [[VLA]], ptr [[TMP105]], align 4
2237 // CHECK3-NEXT:    [[TMP106:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 3
2238 // CHECK3-NEXT:    store i64 [[TMP91]], ptr [[TMP106]], align 4
2239 // CHECK3-NEXT:    [[TMP107:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 3
2240 // CHECK3-NEXT:    store ptr null, ptr [[TMP107]], align 4
2241 // CHECK3-NEXT:    [[TMP108:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 4
2242 // CHECK3-NEXT:    store ptr [[C]], ptr [[TMP108]], align 4
2243 // CHECK3-NEXT:    [[TMP109:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 4
2244 // CHECK3-NEXT:    store ptr [[C]], ptr [[TMP109]], align 4
2245 // CHECK3-NEXT:    [[TMP110:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 4
2246 // CHECK3-NEXT:    store ptr null, ptr [[TMP110]], align 4
2247 // CHECK3-NEXT:    [[TMP111:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 5
2248 // CHECK3-NEXT:    store i32 5, ptr [[TMP111]], align 4
2249 // CHECK3-NEXT:    [[TMP112:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 5
2250 // CHECK3-NEXT:    store i32 5, ptr [[TMP112]], align 4
2251 // CHECK3-NEXT:    [[TMP113:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 5
2252 // CHECK3-NEXT:    store ptr null, ptr [[TMP113]], align 4
2253 // CHECK3-NEXT:    [[TMP114:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 6
2254 // CHECK3-NEXT:    store i32 [[TMP3]], ptr [[TMP114]], align 4
2255 // CHECK3-NEXT:    [[TMP115:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 6
2256 // CHECK3-NEXT:    store i32 [[TMP3]], ptr [[TMP115]], align 4
2257 // CHECK3-NEXT:    [[TMP116:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 6
2258 // CHECK3-NEXT:    store ptr null, ptr [[TMP116]], align 4
2259 // CHECK3-NEXT:    [[TMP117:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 7
2260 // CHECK3-NEXT:    store ptr [[VLA1]], ptr [[TMP117]], align 4
2261 // CHECK3-NEXT:    [[TMP118:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 7
2262 // CHECK3-NEXT:    store ptr [[VLA1]], ptr [[TMP118]], align 4
2263 // CHECK3-NEXT:    [[TMP119:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 7
2264 // CHECK3-NEXT:    store i64 [[TMP94]], ptr [[TMP119]], align 4
2265 // CHECK3-NEXT:    [[TMP120:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 7
2266 // CHECK3-NEXT:    store ptr null, ptr [[TMP120]], align 4
2267 // CHECK3-NEXT:    [[TMP121:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 8
2268 // CHECK3-NEXT:    store ptr [[D]], ptr [[TMP121]], align 4
2269 // CHECK3-NEXT:    [[TMP122:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 8
2270 // CHECK3-NEXT:    store ptr [[D]], ptr [[TMP122]], align 4
2271 // CHECK3-NEXT:    [[TMP123:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 8
2272 // CHECK3-NEXT:    store ptr null, ptr [[TMP123]], align 4
2273 // CHECK3-NEXT:    [[TMP124:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 9
2274 // CHECK3-NEXT:    store i32 [[TMP88]], ptr [[TMP124]], align 4
2275 // CHECK3-NEXT:    [[TMP125:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 9
2276 // CHECK3-NEXT:    store i32 [[TMP88]], ptr [[TMP125]], align 4
2277 // CHECK3-NEXT:    [[TMP126:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 9
2278 // CHECK3-NEXT:    store ptr null, ptr [[TMP126]], align 4
2279 // CHECK3-NEXT:    [[TMP127:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0
2280 // CHECK3-NEXT:    [[TMP128:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 0
2281 // CHECK3-NEXT:    [[TMP129:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0
2282 // CHECK3-NEXT:    [[TMP130:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 0
2283 // CHECK3-NEXT:    store i32 2, ptr [[TMP130]], align 4
2284 // CHECK3-NEXT:    [[TMP131:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 1
2285 // CHECK3-NEXT:    store i32 10, ptr [[TMP131]], align 4
2286 // CHECK3-NEXT:    [[TMP132:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 2
2287 // CHECK3-NEXT:    store ptr [[TMP127]], ptr [[TMP132]], align 4
2288 // CHECK3-NEXT:    [[TMP133:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 3
2289 // CHECK3-NEXT:    store ptr [[TMP128]], ptr [[TMP133]], align 4
2290 // CHECK3-NEXT:    [[TMP134:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 4
2291 // CHECK3-NEXT:    store ptr [[TMP129]], ptr [[TMP134]], align 4
2292 // CHECK3-NEXT:    [[TMP135:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 5
2293 // CHECK3-NEXT:    store ptr @.offload_maptypes.4, ptr [[TMP135]], align 4
2294 // CHECK3-NEXT:    [[TMP136:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 6
2295 // CHECK3-NEXT:    store ptr null, ptr [[TMP136]], align 4
2296 // CHECK3-NEXT:    [[TMP137:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 7
2297 // CHECK3-NEXT:    store ptr null, ptr [[TMP137]], align 4
2298 // CHECK3-NEXT:    [[TMP138:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 8
2299 // CHECK3-NEXT:    store i64 0, ptr [[TMP138]], align 8
2300 // CHECK3-NEXT:    [[TMP139:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 9
2301 // CHECK3-NEXT:    store i64 0, ptr [[TMP139]], align 8
2302 // CHECK3-NEXT:    [[TMP140:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 10
2303 // CHECK3-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP140]], align 4
2304 // CHECK3-NEXT:    [[TMP141:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 11
2305 // CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP141]], align 4
2306 // CHECK3-NEXT:    [[TMP142:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 12
2307 // CHECK3-NEXT:    store i32 0, ptr [[TMP142]], align 4
2308 // CHECK3-NEXT:    [[TMP143:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.region_id, ptr [[KERNEL_ARGS17]])
2309 // CHECK3-NEXT:    [[TMP144:%.*]] = icmp ne i32 [[TMP143]], 0
2310 // CHECK3-NEXT:    br i1 [[TMP144]], label [[OMP_OFFLOAD_FAILED18:%.*]], label [[OMP_OFFLOAD_CONT19:%.*]]
2311 // CHECK3:       omp_offload.failed18:
2312 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160(i32 [[TMP86]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]], i32 [[TMP88]]) #[[ATTR3]]
2313 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT19]]
2314 // CHECK3:       omp_offload.cont19:
2315 // CHECK3-NEXT:    br label [[OMP_IF_END21:%.*]]
2316 // CHECK3:       omp_if.else20:
2317 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160(i32 [[TMP86]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]], i32 [[TMP88]]) #[[ATTR3]]
2318 // CHECK3-NEXT:    br label [[OMP_IF_END21]]
2319 // CHECK3:       omp_if.end21:
2320 // CHECK3-NEXT:    [[TMP145:%.*]] = load i32, ptr [[A]], align 4
2321 // CHECK3-NEXT:    [[TMP146:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
2322 // CHECK3-NEXT:    call void @llvm.stackrestore.p0(ptr [[TMP146]])
2323 // CHECK3-NEXT:    ret i32 [[TMP145]]
2324 //
2325 //
2326 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
2327 // CHECK3-SAME: () #[[ATTR2:[0-9]+]] {
2328 // CHECK3-NEXT:  entry:
2329 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined)
2330 // CHECK3-NEXT:    ret void
2331 //
2332 //
2333 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined
2334 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] {
2335 // CHECK3-NEXT:  entry:
2336 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
2337 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
2338 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2339 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2340 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2341 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2342 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2343 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2344 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
2345 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
2346 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
2347 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
2348 // CHECK3-NEXT:    store i32 5, ptr [[DOTOMP_UB]], align 4
2349 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
2350 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2351 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
2352 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
2353 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
2354 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2355 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
2356 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2357 // CHECK3:       cond.true:
2358 // CHECK3-NEXT:    br label [[COND_END:%.*]]
2359 // CHECK3:       cond.false:
2360 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2361 // CHECK3-NEXT:    br label [[COND_END]]
2362 // CHECK3:       cond.end:
2363 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
2364 // CHECK3-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
2365 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
2366 // CHECK3-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
2367 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2368 // CHECK3:       omp.inner.for.cond:
2369 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2370 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2371 // CHECK3-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
2372 // CHECK3-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2373 // CHECK3:       omp.inner.for.body:
2374 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2375 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
2376 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 3, [[MUL]]
2377 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[I]], align 4
2378 // CHECK3-NEXT:    [[TMP8:%.*]] = call i32 @__kmpc_cancel(ptr @[[GLOB2]], i32 [[TMP1]], i32 2)
2379 // CHECK3-NEXT:    [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0
2380 // CHECK3-NEXT:    br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
2381 // CHECK3:       .cancel.exit:
2382 // CHECK3-NEXT:    br label [[CANCEL_EXIT:%.*]]
2383 // CHECK3:       .cancel.continue:
2384 // CHECK3-NEXT:    [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(ptr @[[GLOB2]], i32 [[TMP1]], i32 2)
2385 // CHECK3-NEXT:    [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
2386 // CHECK3-NEXT:    br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]]
2387 // CHECK3:       .cancel.exit2:
2388 // CHECK3-NEXT:    br label [[CANCEL_EXIT]]
2389 // CHECK3:       .cancel.continue3:
2390 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2391 // CHECK3:       omp.body.continue:
2392 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2393 // CHECK3:       omp.inner.for.inc:
2394 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2395 // CHECK3-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
2396 // CHECK3-NEXT:    store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4
2397 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]]
2398 // CHECK3:       omp.inner.for.end:
2399 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2400 // CHECK3:       omp.loop.exit:
2401 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
2402 // CHECK3-NEXT:    br label [[CANCEL_CONT:%.*]]
2403 // CHECK3:       cancel.cont:
2404 // CHECK3-NEXT:    ret void
2405 // CHECK3:       cancel.exit:
2406 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
2407 // CHECK3-NEXT:    br label [[CANCEL_CONT]]
2408 //
2409 //
2410 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110
2411 // CHECK3-SAME: (i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR2]] {
2412 // CHECK3-NEXT:  entry:
2413 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2414 // CHECK3-NEXT:    [[K_ADDR:%.*]] = alloca ptr, align 4
2415 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
2416 // CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
2417 // CHECK3-NEXT:    store ptr [[K]], ptr [[K_ADDR]], align 4
2418 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[K_ADDR]], align 4
2419 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
2420 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 4
2421 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4
2422 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.omp_outlined, i32 [[TMP2]], ptr [[TMP0]])
2423 // CHECK3-NEXT:    ret void
2424 //
2425 //
2426 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.omp_outlined
2427 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR2]] {
2428 // CHECK3-NEXT:  entry:
2429 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
2430 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
2431 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2432 // CHECK3-NEXT:    [[K_ADDR:%.*]] = alloca ptr, align 4
2433 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2434 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2435 // CHECK3-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i64, align 8
2436 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2437 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2438 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2439 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2440 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
2441 // CHECK3-NEXT:    [[K1:%.*]] = alloca i64, align 8
2442 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
2443 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
2444 // CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
2445 // CHECK3-NEXT:    store ptr [[K]], ptr [[K_ADDR]], align 4
2446 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[K_ADDR]], align 4
2447 // CHECK3-NEXT:    [[TMP1:%.*]] = load i64, ptr [[TMP0]], align 8
2448 // CHECK3-NEXT:    store i64 [[TMP1]], ptr [[DOTLINEAR_START]], align 8
2449 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
2450 // CHECK3-NEXT:    store i32 8, ptr [[DOTOMP_UB]], align 4
2451 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
2452 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2453 // CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
2454 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
2455 // CHECK3-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP3]])
2456 // CHECK3-NEXT:    call void @__kmpc_dispatch_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 35, i32 0, i32 8, i32 1, i32 1)
2457 // CHECK3-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
2458 // CHECK3:       omp.dispatch.cond:
2459 // CHECK3-NEXT:    [[TMP4:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB2]], i32 [[TMP3]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
2460 // CHECK3-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0
2461 // CHECK3-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
2462 // CHECK3:       omp.dispatch.body:
2463 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
2464 // CHECK3-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
2465 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2466 // CHECK3:       omp.inner.for.cond:
2467 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13:![0-9]+]]
2468 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP13]]
2469 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
2470 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2471 // CHECK3:       omp.inner.for.body:
2472 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]]
2473 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
2474 // CHECK3-NEXT:    [[SUB:%.*]] = sub nsw i32 10, [[MUL]]
2475 // CHECK3-NEXT:    store i32 [[SUB]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]]
2476 // CHECK3-NEXT:    [[TMP9:%.*]] = load i64, ptr [[DOTLINEAR_START]], align 8, !llvm.access.group [[ACC_GRP13]]
2477 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]]
2478 // CHECK3-NEXT:    [[MUL2:%.*]] = mul nsw i32 [[TMP10]], 3
2479 // CHECK3-NEXT:    [[CONV:%.*]] = sext i32 [[MUL2]] to i64
2480 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i64 [[TMP9]], [[CONV]]
2481 // CHECK3-NEXT:    store i64 [[ADD]], ptr [[K1]], align 8, !llvm.access.group [[ACC_GRP13]]
2482 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP13]]
2483 // CHECK3-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP11]], 1
2484 // CHECK3-NEXT:    store i32 [[ADD3]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP13]]
2485 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2486 // CHECK3:       omp.body.continue:
2487 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2488 // CHECK3:       omp.inner.for.inc:
2489 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]]
2490 // CHECK3-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
2491 // CHECK3-NEXT:    store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]]
2492 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
2493 // CHECK3:       omp.inner.for.end:
2494 // CHECK3-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
2495 // CHECK3:       omp.dispatch.inc:
2496 // CHECK3-NEXT:    br label [[OMP_DISPATCH_COND]]
2497 // CHECK3:       omp.dispatch.end:
2498 // CHECK3-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
2499 // CHECK3-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
2500 // CHECK3-NEXT:    br i1 [[TMP14]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
2501 // CHECK3:       .omp.linear.pu:
2502 // CHECK3-NEXT:    [[TMP15:%.*]] = load i64, ptr [[K1]], align 8
2503 // CHECK3-NEXT:    store i64 [[TMP15]], ptr [[TMP0]], align 8
2504 // CHECK3-NEXT:    br label [[DOTOMP_LINEAR_PU_DONE]]
2505 // CHECK3:       .omp.linear.pu.done:
2506 // CHECK3-NEXT:    ret void
2507 //
2508 //
2509 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128
2510 // CHECK3-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] {
2511 // CHECK3-NEXT:  entry:
2512 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
2513 // CHECK3-NEXT:    [[LIN_ADDR:%.*]] = alloca i32, align 4
2514 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2515 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
2516 // CHECK3-NEXT:    [[LIN_CASTED:%.*]] = alloca i32, align 4
2517 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
2518 // CHECK3-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
2519 // CHECK3-NEXT:    store i32 [[LIN]], ptr [[LIN_ADDR]], align 4
2520 // CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
2521 // CHECK3-NEXT:    [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2
2522 // CHECK3-NEXT:    store i16 [[TMP0]], ptr [[AA_CASTED]], align 2
2523 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[AA_CASTED]], align 4
2524 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[LIN_ADDR]], align 4
2525 // CHECK3-NEXT:    store i32 [[TMP2]], ptr [[LIN_CASTED]], align 4
2526 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[LIN_CASTED]], align 4
2527 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4
2528 // CHECK3-NEXT:    store i32 [[TMP4]], ptr [[A_CASTED]], align 4
2529 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[A_CASTED]], align 4
2530 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128.omp_outlined, i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]])
2531 // CHECK3-NEXT:    ret void
2532 //
2533 //
2534 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128.omp_outlined
2535 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] {
2536 // CHECK3-NEXT:  entry:
2537 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
2538 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
2539 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
2540 // CHECK3-NEXT:    [[LIN_ADDR:%.*]] = alloca i32, align 4
2541 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2542 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
2543 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i64, align 4
2544 // CHECK3-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i32, align 4
2545 // CHECK3-NEXT:    [[DOTLINEAR_START1:%.*]] = alloca i32, align 4
2546 // CHECK3-NEXT:    [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
2547 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
2548 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
2549 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
2550 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2551 // CHECK3-NEXT:    [[IT:%.*]] = alloca i64, align 8
2552 // CHECK3-NEXT:    [[LIN2:%.*]] = alloca i32, align 4
2553 // CHECK3-NEXT:    [[A3:%.*]] = alloca i32, align 4
2554 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
2555 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
2556 // CHECK3-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
2557 // CHECK3-NEXT:    store i32 [[LIN]], ptr [[LIN_ADDR]], align 4
2558 // CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
2559 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[LIN_ADDR]], align 4
2560 // CHECK3-NEXT:    store i32 [[TMP0]], ptr [[DOTLINEAR_START]], align 4
2561 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
2562 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[DOTLINEAR_START1]], align 4
2563 // CHECK3-NEXT:    [[CALL:%.*]] = call noundef i64 @_Z7get_valv()
2564 // CHECK3-NEXT:    store i64 [[CALL]], ptr [[DOTLINEAR_STEP]], align 8
2565 // CHECK3-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8
2566 // CHECK3-NEXT:    store i64 3, ptr [[DOTOMP_UB]], align 8
2567 // CHECK3-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8
2568 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2569 // CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
2570 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
2571 // CHECK3-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP3]])
2572 // CHECK3-NEXT:    call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
2573 // CHECK3-NEXT:    [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
2574 // CHECK3-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
2575 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2576 // CHECK3:       cond.true:
2577 // CHECK3-NEXT:    br label [[COND_END:%.*]]
2578 // CHECK3:       cond.false:
2579 // CHECK3-NEXT:    [[TMP5:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
2580 // CHECK3-NEXT:    br label [[COND_END]]
2581 // CHECK3:       cond.end:
2582 // CHECK3-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
2583 // CHECK3-NEXT:    store i64 [[COND]], ptr [[DOTOMP_UB]], align 8
2584 // CHECK3-NEXT:    [[TMP6:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
2585 // CHECK3-NEXT:    store i64 [[TMP6]], ptr [[DOTOMP_IV]], align 8
2586 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2587 // CHECK3:       omp.inner.for.cond:
2588 // CHECK3-NEXT:    [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
2589 // CHECK3-NEXT:    [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
2590 // CHECK3-NEXT:    [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
2591 // CHECK3-NEXT:    br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2592 // CHECK3:       omp.inner.for.body:
2593 // CHECK3-NEXT:    [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
2594 // CHECK3-NEXT:    [[MUL:%.*]] = mul i64 [[TMP9]], 400
2595 // CHECK3-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
2596 // CHECK3-NEXT:    store i64 [[SUB]], ptr [[IT]], align 8
2597 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTLINEAR_START]], align 4
2598 // CHECK3-NEXT:    [[CONV:%.*]] = sext i32 [[TMP10]] to i64
2599 // CHECK3-NEXT:    [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
2600 // CHECK3-NEXT:    [[TMP12:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8
2601 // CHECK3-NEXT:    [[MUL5:%.*]] = mul i64 [[TMP11]], [[TMP12]]
2602 // CHECK3-NEXT:    [[ADD:%.*]] = add i64 [[CONV]], [[MUL5]]
2603 // CHECK3-NEXT:    [[CONV6:%.*]] = trunc i64 [[ADD]] to i32
2604 // CHECK3-NEXT:    store i32 [[CONV6]], ptr [[LIN2]], align 4
2605 // CHECK3-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTLINEAR_START1]], align 4
2606 // CHECK3-NEXT:    [[CONV7:%.*]] = sext i32 [[TMP13]] to i64
2607 // CHECK3-NEXT:    [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
2608 // CHECK3-NEXT:    [[TMP15:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8
2609 // CHECK3-NEXT:    [[MUL8:%.*]] = mul i64 [[TMP14]], [[TMP15]]
2610 // CHECK3-NEXT:    [[ADD9:%.*]] = add i64 [[CONV7]], [[MUL8]]
2611 // CHECK3-NEXT:    [[CONV10:%.*]] = trunc i64 [[ADD9]] to i32
2612 // CHECK3-NEXT:    store i32 [[CONV10]], ptr [[A3]], align 4
2613 // CHECK3-NEXT:    [[TMP16:%.*]] = load i16, ptr [[AA_ADDR]], align 2
2614 // CHECK3-NEXT:    [[CONV11:%.*]] = sext i16 [[TMP16]] to i32
2615 // CHECK3-NEXT:    [[ADD12:%.*]] = add nsw i32 [[CONV11]], 1
2616 // CHECK3-NEXT:    [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16
2617 // CHECK3-NEXT:    store i16 [[CONV13]], ptr [[AA_ADDR]], align 2
2618 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2619 // CHECK3:       omp.body.continue:
2620 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2621 // CHECK3:       omp.inner.for.inc:
2622 // CHECK3-NEXT:    [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
2623 // CHECK3-NEXT:    [[ADD14:%.*]] = add i64 [[TMP17]], 1
2624 // CHECK3-NEXT:    store i64 [[ADD14]], ptr [[DOTOMP_IV]], align 8
2625 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]]
2626 // CHECK3:       omp.inner.for.end:
2627 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2628 // CHECK3:       omp.loop.exit:
2629 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]])
2630 // CHECK3-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
2631 // CHECK3-NEXT:    [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
2632 // CHECK3-NEXT:    br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
2633 // CHECK3:       .omp.linear.pu:
2634 // CHECK3-NEXT:    [[TMP20:%.*]] = load i32, ptr [[LIN2]], align 4
2635 // CHECK3-NEXT:    store i32 [[TMP20]], ptr [[LIN_ADDR]], align 4
2636 // CHECK3-NEXT:    [[TMP21:%.*]] = load i32, ptr [[A3]], align 4
2637 // CHECK3-NEXT:    store i32 [[TMP21]], ptr [[A_ADDR]], align 4
2638 // CHECK3-NEXT:    br label [[DOTOMP_LINEAR_PU_DONE]]
2639 // CHECK3:       .omp.linear.pu.done:
2640 // CHECK3-NEXT:    ret void
2641 //
2642 //
2643 // CHECK3-LABEL: define {{[^@]+}}@.omp_task_privates_map.
2644 // CHECK3-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]], ptr noalias noundef [[TMP3:%.*]], ptr noalias noundef [[TMP4:%.*]]) #[[ATTR5:[0-9]+]] {
2645 // CHECK3-NEXT:  entry:
2646 // CHECK3-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 4
2647 // CHECK3-NEXT:    [[DOTADDR1:%.*]] = alloca ptr, align 4
2648 // CHECK3-NEXT:    [[DOTADDR2:%.*]] = alloca ptr, align 4
2649 // CHECK3-NEXT:    [[DOTADDR3:%.*]] = alloca ptr, align 4
2650 // CHECK3-NEXT:    [[DOTADDR4:%.*]] = alloca ptr, align 4
2651 // CHECK3-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 4
2652 // CHECK3-NEXT:    store ptr [[TMP1]], ptr [[DOTADDR1]], align 4
2653 // CHECK3-NEXT:    store ptr [[TMP2]], ptr [[DOTADDR2]], align 4
2654 // CHECK3-NEXT:    store ptr [[TMP3]], ptr [[DOTADDR3]], align 4
2655 // CHECK3-NEXT:    store ptr [[TMP4]], ptr [[DOTADDR4]], align 4
2656 // CHECK3-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[DOTADDR]], align 4
2657 // CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP5]], i32 0, i32 0
2658 // CHECK3-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[DOTADDR4]], align 4
2659 // CHECK3-NEXT:    store ptr [[TMP6]], ptr [[TMP7]], align 4
2660 // CHECK3-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 1
2661 // CHECK3-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[DOTADDR2]], align 4
2662 // CHECK3-NEXT:    store ptr [[TMP8]], ptr [[TMP9]], align 4
2663 // CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 2
2664 // CHECK3-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[DOTADDR3]], align 4
2665 // CHECK3-NEXT:    store ptr [[TMP10]], ptr [[TMP11]], align 4
2666 // CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 3
2667 // CHECK3-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[DOTADDR1]], align 4
2668 // CHECK3-NEXT:    store ptr [[TMP12]], ptr [[TMP13]], align 4
2669 // CHECK3-NEXT:    ret void
2670 //
2671 //
2672 // CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry.
2673 // CHECK3-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] {
2674 // CHECK3-NEXT:  entry:
2675 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
2676 // CHECK3-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 4
2677 // CHECK3-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 4
2678 // CHECK3-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 4
2679 // CHECK3-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 4
2680 // CHECK3-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 4
2681 // CHECK3-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca ptr, align 4
2682 // CHECK3-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca ptr, align 4
2683 // CHECK3-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca ptr, align 4
2684 // CHECK3-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca ptr, align 4
2685 // CHECK3-NEXT:    [[KERNEL_ARGS_I:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
2686 // CHECK3-NEXT:    [[AA_CASTED_I:%.*]] = alloca i32, align 4
2687 // CHECK3-NEXT:    [[LIN_CASTED_I:%.*]] = alloca i32, align 4
2688 // CHECK3-NEXT:    [[A_CASTED_I:%.*]] = alloca i32, align 4
2689 // CHECK3-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 4
2690 // CHECK3-NEXT:    [[DOTADDR1:%.*]] = alloca ptr, align 4
2691 // CHECK3-NEXT:    store i32 [[TMP0]], ptr [[DOTADDR]], align 4
2692 // CHECK3-NEXT:    store ptr [[TMP1]], ptr [[DOTADDR1]], align 4
2693 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4
2694 // CHECK3-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 4
2695 // CHECK3-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0
2696 // CHECK3-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2
2697 // CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0
2698 // CHECK3-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 4
2699 // CHECK3-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 1
2700 // CHECK3-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]])
2701 // CHECK3-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])
2702 // CHECK3-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])
2703 // CHECK3-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]])
2704 // CHECK3-NEXT:    store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !25
2705 // CHECK3-NEXT:    store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 4, !noalias !25
2706 // CHECK3-NEXT:    store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25
2707 // CHECK3-NEXT:    store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25
2708 // CHECK3-NEXT:    store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 4, !noalias !25
2709 // CHECK3-NEXT:    store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 4, !noalias !25
2710 // CHECK3-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 4, !noalias !25
2711 // CHECK3-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25
2712 // CHECK3-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25
2713 // CHECK3-NEXT:    call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]
2714 // CHECK3-NEXT:    [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !25
2715 // CHECK3-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !25
2716 // CHECK3-NEXT:    [[TMP14:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !25
2717 // CHECK3-NEXT:    [[TMP15:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !25
2718 // CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP9]], i32 0, i32 1
2719 // CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP9]], i32 0, i32 2
2720 // CHECK3-NEXT:    store i32 2, ptr [[KERNEL_ARGS_I]], align 4, !noalias !25
2721 // CHECK3-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 1
2722 // CHECK3-NEXT:    store i32 3, ptr [[TMP18]], align 4, !noalias !25
2723 // CHECK3-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 2
2724 // CHECK3-NEXT:    store ptr [[TMP13]], ptr [[TMP19]], align 4, !noalias !25
2725 // CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 3
2726 // CHECK3-NEXT:    store ptr [[TMP14]], ptr [[TMP20]], align 4, !noalias !25
2727 // CHECK3-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 4
2728 // CHECK3-NEXT:    store ptr [[TMP15]], ptr [[TMP21]], align 4, !noalias !25
2729 // CHECK3-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 5
2730 // CHECK3-NEXT:    store ptr @.offload_maptypes, ptr [[TMP22]], align 4, !noalias !25
2731 // CHECK3-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 6
2732 // CHECK3-NEXT:    store ptr null, ptr [[TMP23]], align 4, !noalias !25
2733 // CHECK3-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 7
2734 // CHECK3-NEXT:    store ptr null, ptr [[TMP24]], align 4, !noalias !25
2735 // CHECK3-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 8
2736 // CHECK3-NEXT:    store i64 0, ptr [[TMP25]], align 8, !noalias !25
2737 // CHECK3-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 9
2738 // CHECK3-NEXT:    store i64 1, ptr [[TMP26]], align 8, !noalias !25
2739 // CHECK3-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 10
2740 // CHECK3-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP27]], align 4, !noalias !25
2741 // CHECK3-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 11
2742 // CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP28]], align 4, !noalias !25
2743 // CHECK3-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 12
2744 // CHECK3-NEXT:    store i32 0, ptr [[TMP29]], align 4, !noalias !25
2745 // CHECK3-NEXT:    [[TMP30:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128.region_id, ptr [[KERNEL_ARGS_I]])
2746 // CHECK3-NEXT:    [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0
2747 // CHECK3-NEXT:    br i1 [[TMP31]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]]
2748 // CHECK3:       omp_offload.failed.i:
2749 // CHECK3-NEXT:    [[TMP32:%.*]] = load i16, ptr [[TMP12]], align 2
2750 // CHECK3-NEXT:    store i16 [[TMP32]], ptr [[AA_CASTED_I]], align 2, !noalias !25
2751 // CHECK3-NEXT:    [[TMP33:%.*]] = load i32, ptr [[AA_CASTED_I]], align 4, !noalias !25
2752 // CHECK3-NEXT:    [[TMP34:%.*]] = load i32, ptr [[TMP16]], align 4
2753 // CHECK3-NEXT:    store i32 [[TMP34]], ptr [[LIN_CASTED_I]], align 4, !noalias !25
2754 // CHECK3-NEXT:    [[TMP35:%.*]] = load i32, ptr [[LIN_CASTED_I]], align 4, !noalias !25
2755 // CHECK3-NEXT:    [[TMP36:%.*]] = load i32, ptr [[TMP17]], align 4
2756 // CHECK3-NEXT:    store i32 [[TMP36]], ptr [[A_CASTED_I]], align 4, !noalias !25
2757 // CHECK3-NEXT:    [[TMP37:%.*]] = load i32, ptr [[A_CASTED_I]], align 4, !noalias !25
2758 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128(i32 [[TMP33]], i32 [[TMP35]], i32 [[TMP37]]) #[[ATTR3]]
2759 // CHECK3-NEXT:    br label [[DOTOMP_OUTLINED__EXIT]]
2760 // CHECK3:       .omp_outlined..exit:
2761 // CHECK3-NEXT:    ret i32 0
2762 //
2763 //
2764 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136
2765 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {
2766 // CHECK3-NEXT:  entry:
2767 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2768 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
2769 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
2770 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
2771 // CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
2772 // CHECK3-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
2773 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
2774 // CHECK3-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 4
2775 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4
2776 // CHECK3-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2
2777 // CHECK3-NEXT:    store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
2778 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4
2779 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.omp_outlined, i32 [[TMP1]], i32 [[TMP3]])
2780 // CHECK3-NEXT:    ret void
2781 //
2782 //
2783 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.omp_outlined
2784 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {
2785 // CHECK3-NEXT:  entry:
2786 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
2787 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
2788 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2789 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
2790 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2791 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i16, align 2
2792 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2793 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2794 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2795 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2796 // CHECK3-NEXT:    [[IT:%.*]] = alloca i16, align 2
2797 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
2798 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
2799 // CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
2800 // CHECK3-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
2801 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
2802 // CHECK3-NEXT:    store i32 3, ptr [[DOTOMP_UB]], align 4
2803 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
2804 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2805 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
2806 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
2807 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
2808 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2809 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
2810 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2811 // CHECK3:       cond.true:
2812 // CHECK3-NEXT:    br label [[COND_END:%.*]]
2813 // CHECK3:       cond.false:
2814 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2815 // CHECK3-NEXT:    br label [[COND_END]]
2816 // CHECK3:       cond.end:
2817 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
2818 // CHECK3-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
2819 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
2820 // CHECK3-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
2821 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2822 // CHECK3:       omp.inner.for.cond:
2823 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2824 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2825 // CHECK3-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
2826 // CHECK3-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2827 // CHECK3:       omp.inner.for.body:
2828 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2829 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
2830 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 6, [[MUL]]
2831 // CHECK3-NEXT:    [[CONV:%.*]] = trunc i32 [[ADD]] to i16
2832 // CHECK3-NEXT:    store i16 [[CONV]], ptr [[IT]], align 2
2833 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
2834 // CHECK3-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
2835 // CHECK3-NEXT:    store i32 [[ADD2]], ptr [[A_ADDR]], align 4
2836 // CHECK3-NEXT:    [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2
2837 // CHECK3-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP9]] to i32
2838 // CHECK3-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
2839 // CHECK3-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
2840 // CHECK3-NEXT:    store i16 [[CONV5]], ptr [[AA_ADDR]], align 2
2841 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2842 // CHECK3:       omp.body.continue:
2843 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2844 // CHECK3:       omp.inner.for.inc:
2845 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2846 // CHECK3-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1
2847 // CHECK3-NEXT:    store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4
2848 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]]
2849 // CHECK3:       omp.inner.for.end:
2850 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2851 // CHECK3:       omp.loop.exit:
2852 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
2853 // CHECK3-NEXT:    ret void
2854 //
2855 //
2856 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160
2857 // CHECK3-SAME: (i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
2858 // CHECK3-NEXT:  entry:
2859 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2860 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
2861 // CHECK3-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
2862 // CHECK3-NEXT:    [[BN_ADDR:%.*]] = alloca ptr, align 4
2863 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
2864 // CHECK3-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
2865 // CHECK3-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
2866 // CHECK3-NEXT:    [[CN_ADDR:%.*]] = alloca ptr, align 4
2867 // CHECK3-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4
2868 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
2869 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
2870 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
2871 // CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
2872 // CHECK3-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
2873 // CHECK3-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
2874 // CHECK3-NEXT:    store ptr [[BN]], ptr [[BN_ADDR]], align 4
2875 // CHECK3-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
2876 // CHECK3-NEXT:    store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
2877 // CHECK3-NEXT:    store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4
2878 // CHECK3-NEXT:    store ptr [[CN]], ptr [[CN_ADDR]], align 4
2879 // CHECK3-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4
2880 // CHECK3-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
2881 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
2882 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
2883 // CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4
2884 // CHECK3-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
2885 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
2886 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4
2887 // CHECK3-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4
2888 // CHECK3-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4
2889 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
2890 // CHECK3-NEXT:    store i32 [[TMP8]], ptr [[A_CASTED]], align 4
2891 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4
2892 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
2893 // CHECK3-NEXT:    store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
2894 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
2895 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined, i32 [[TMP9]], ptr [[TMP0]], i32 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i32 [[TMP11]])
2896 // CHECK3-NEXT:    ret void
2897 //
2898 //
2899 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined
2900 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
2901 // CHECK3-NEXT:  entry:
2902 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
2903 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
2904 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2905 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
2906 // CHECK3-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
2907 // CHECK3-NEXT:    [[BN_ADDR:%.*]] = alloca ptr, align 4
2908 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
2909 // CHECK3-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
2910 // CHECK3-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
2911 // CHECK3-NEXT:    [[CN_ADDR:%.*]] = alloca ptr, align 4
2912 // CHECK3-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4
2913 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
2914 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2915 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i8, align 1
2916 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2917 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2918 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2919 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2920 // CHECK3-NEXT:    [[IT:%.*]] = alloca i8, align 1
2921 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
2922 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
2923 // CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
2924 // CHECK3-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
2925 // CHECK3-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
2926 // CHECK3-NEXT:    store ptr [[BN]], ptr [[BN_ADDR]], align 4
2927 // CHECK3-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
2928 // CHECK3-NEXT:    store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
2929 // CHECK3-NEXT:    store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4
2930 // CHECK3-NEXT:    store ptr [[CN]], ptr [[CN_ADDR]], align 4
2931 // CHECK3-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4
2932 // CHECK3-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
2933 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
2934 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
2935 // CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4
2936 // CHECK3-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
2937 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
2938 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4
2939 // CHECK3-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4
2940 // CHECK3-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4
2941 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
2942 // CHECK3-NEXT:    store i32 25, ptr [[DOTOMP_UB]], align 4
2943 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
2944 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2945 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
2946 // CHECK3-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
2947 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4
2948 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP10]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
2949 // CHECK3-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
2950 // CHECK3:       omp.dispatch.cond:
2951 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2952 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
2953 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2954 // CHECK3:       cond.true:
2955 // CHECK3-NEXT:    br label [[COND_END:%.*]]
2956 // CHECK3:       cond.false:
2957 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2958 // CHECK3-NEXT:    br label [[COND_END]]
2959 // CHECK3:       cond.end:
2960 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
2961 // CHECK3-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
2962 // CHECK3-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
2963 // CHECK3-NEXT:    store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4
2964 // CHECK3-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2965 // CHECK3-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2966 // CHECK3-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
2967 // CHECK3-NEXT:    br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
2968 // CHECK3:       omp.dispatch.body:
2969 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2970 // CHECK3:       omp.inner.for.cond:
2971 // CHECK3-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2972 // CHECK3-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2973 // CHECK3-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
2974 // CHECK3-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2975 // CHECK3:       omp.inner.for.body:
2976 // CHECK3-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2977 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
2978 // CHECK3-NEXT:    [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
2979 // CHECK3-NEXT:    [[CONV:%.*]] = trunc i32 [[SUB]] to i8
2980 // CHECK3-NEXT:    store i8 [[CONV]], ptr [[IT]], align 1
2981 // CHECK3-NEXT:    [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4
2982 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
2983 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 4
2984 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 2
2985 // CHECK3-NEXT:    [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4
2986 // CHECK3-NEXT:    [[CONV7:%.*]] = fpext float [[TMP20]] to double
2987 // CHECK3-NEXT:    [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00
2988 // CHECK3-NEXT:    [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
2989 // CHECK3-NEXT:    store float [[CONV9]], ptr [[ARRAYIDX]], align 4
2990 // CHECK3-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i32 3
2991 // CHECK3-NEXT:    [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4
2992 // CHECK3-NEXT:    [[CONV11:%.*]] = fpext float [[TMP21]] to double
2993 // CHECK3-NEXT:    [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
2994 // CHECK3-NEXT:    [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
2995 // CHECK3-NEXT:    store float [[CONV13]], ptr [[ARRAYIDX10]], align 4
2996 // CHECK3-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 1
2997 // CHECK3-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i32 0, i32 2
2998 // CHECK3-NEXT:    [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8
2999 // CHECK3-NEXT:    [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
3000 // CHECK3-NEXT:    store double [[ADD16]], ptr [[ARRAYIDX15]], align 8
3001 // CHECK3-NEXT:    [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]
3002 // CHECK3-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i32 [[TMP23]]
3003 // CHECK3-NEXT:    [[ARRAYIDX18:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX17]], i32 3
3004 // CHECK3-NEXT:    [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 8
3005 // CHECK3-NEXT:    [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
3006 // CHECK3-NEXT:    store double [[ADD19]], ptr [[ARRAYIDX18]], align 8
3007 // CHECK3-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0
3008 // CHECK3-NEXT:    [[TMP25:%.*]] = load i64, ptr [[X]], align 4
3009 // CHECK3-NEXT:    [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
3010 // CHECK3-NEXT:    store i64 [[ADD20]], ptr [[X]], align 4
3011 // CHECK3-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1
3012 // CHECK3-NEXT:    [[TMP26:%.*]] = load i8, ptr [[Y]], align 4
3013 // CHECK3-NEXT:    [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
3014 // CHECK3-NEXT:    [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
3015 // CHECK3-NEXT:    [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
3016 // CHECK3-NEXT:    store i8 [[CONV23]], ptr [[Y]], align 4
3017 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
3018 // CHECK3:       omp.body.continue:
3019 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
3020 // CHECK3:       omp.inner.for.inc:
3021 // CHECK3-NEXT:    [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3022 // CHECK3-NEXT:    [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
3023 // CHECK3-NEXT:    store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4
3024 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]]
3025 // CHECK3:       omp.inner.for.end:
3026 // CHECK3-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
3027 // CHECK3:       omp.dispatch.inc:
3028 // CHECK3-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
3029 // CHECK3-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
3030 // CHECK3-NEXT:    [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
3031 // CHECK3-NEXT:    store i32 [[ADD25]], ptr [[DOTOMP_LB]], align 4
3032 // CHECK3-NEXT:    [[TMP30:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
3033 // CHECK3-NEXT:    [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
3034 // CHECK3-NEXT:    [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
3035 // CHECK3-NEXT:    store i32 [[ADD26]], ptr [[DOTOMP_UB]], align 4
3036 // CHECK3-NEXT:    br label [[OMP_DISPATCH_COND]]
3037 // CHECK3:       omp.dispatch.end:
3038 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP10]])
3039 // CHECK3-NEXT:    ret void
3040 //
3041 //
3042 // CHECK3-LABEL: define {{[^@]+}}@_Z3bari
3043 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
3044 // CHECK3-NEXT:  entry:
3045 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
3046 // CHECK3-NEXT:    [[A:%.*]] = alloca i32, align 4
3047 // CHECK3-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
3048 // CHECK3-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
3049 // CHECK3-NEXT:    store i32 0, ptr [[A]], align 4
3050 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
3051 // CHECK3-NEXT:    [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]])
3052 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A]], align 4
3053 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
3054 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[A]], align 4
3055 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
3056 // CHECK3-NEXT:    [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]])
3057 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A]], align 4
3058 // CHECK3-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
3059 // CHECK3-NEXT:    store i32 [[ADD2]], ptr [[A]], align 4
3060 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
3061 // CHECK3-NEXT:    [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]])
3062 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[A]], align 4
3063 // CHECK3-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
3064 // CHECK3-NEXT:    store i32 [[ADD4]], ptr [[A]], align 4
3065 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4
3066 // CHECK3-NEXT:    [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]])
3067 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[A]], align 4
3068 // CHECK3-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
3069 // CHECK3-NEXT:    store i32 [[ADD6]], ptr [[A]], align 4
3070 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A]], align 4
3071 // CHECK3-NEXT:    ret i32 [[TMP8]]
3072 //
3073 //
3074 // CHECK3-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
3075 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 {
3076 // CHECK3-NEXT:  entry:
3077 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
3078 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
3079 // CHECK3-NEXT:    [[B:%.*]] = alloca i32, align 4
3080 // CHECK3-NEXT:    [[SAVED_STACK:%.*]] = alloca ptr, align 4
3081 // CHECK3-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
3082 // CHECK3-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
3083 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 4
3084 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 4
3085 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 4
3086 // CHECK3-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4
3087 // CHECK3-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
3088 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
3089 // CHECK3-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
3090 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
3091 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
3092 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
3093 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[B]], align 4
3094 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
3095 // CHECK3-NEXT:    [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
3096 // CHECK3-NEXT:    store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4
3097 // CHECK3-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
3098 // CHECK3-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
3099 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4
3100 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[B]], align 4
3101 // CHECK3-NEXT:    store i32 [[TMP4]], ptr [[B_CASTED]], align 4
3102 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4
3103 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4
3104 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60
3105 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
3106 // CHECK3:       omp_if.then:
3107 // CHECK3-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0
3108 // CHECK3-NEXT:    [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]]
3109 // CHECK3-NEXT:    [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2
3110 // CHECK3-NEXT:    [[TMP9:%.*]] = sext i32 [[TMP8]] to i64
3111 // CHECK3-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes.5, i32 40, i1 false)
3112 // CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3113 // CHECK3-NEXT:    store ptr [[THIS1]], ptr [[TMP10]], align 4
3114 // CHECK3-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3115 // CHECK3-NEXT:    store ptr [[A]], ptr [[TMP11]], align 4
3116 // CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
3117 // CHECK3-NEXT:    store ptr null, ptr [[TMP12]], align 4
3118 // CHECK3-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
3119 // CHECK3-NEXT:    store i32 [[TMP5]], ptr [[TMP13]], align 4
3120 // CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
3121 // CHECK3-NEXT:    store i32 [[TMP5]], ptr [[TMP14]], align 4
3122 // CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
3123 // CHECK3-NEXT:    store ptr null, ptr [[TMP15]], align 4
3124 // CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
3125 // CHECK3-NEXT:    store i32 2, ptr [[TMP16]], align 4
3126 // CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
3127 // CHECK3-NEXT:    store i32 2, ptr [[TMP17]], align 4
3128 // CHECK3-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
3129 // CHECK3-NEXT:    store ptr null, ptr [[TMP18]], align 4
3130 // CHECK3-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
3131 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[TMP19]], align 4
3132 // CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
3133 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[TMP20]], align 4
3134 // CHECK3-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
3135 // CHECK3-NEXT:    store ptr null, ptr [[TMP21]], align 4
3136 // CHECK3-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
3137 // CHECK3-NEXT:    store ptr [[VLA]], ptr [[TMP22]], align 4
3138 // CHECK3-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4
3139 // CHECK3-NEXT:    store ptr [[VLA]], ptr [[TMP23]], align 4
3140 // CHECK3-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 4
3141 // CHECK3-NEXT:    store i64 [[TMP9]], ptr [[TMP24]], align 4
3142 // CHECK3-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
3143 // CHECK3-NEXT:    store ptr null, ptr [[TMP25]], align 4
3144 // CHECK3-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3145 // CHECK3-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3146 // CHECK3-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0
3147 // CHECK3-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
3148 // CHECK3-NEXT:    store i32 2, ptr [[TMP29]], align 4
3149 // CHECK3-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
3150 // CHECK3-NEXT:    store i32 5, ptr [[TMP30]], align 4
3151 // CHECK3-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
3152 // CHECK3-NEXT:    store ptr [[TMP26]], ptr [[TMP31]], align 4
3153 // CHECK3-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
3154 // CHECK3-NEXT:    store ptr [[TMP27]], ptr [[TMP32]], align 4
3155 // CHECK3-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
3156 // CHECK3-NEXT:    store ptr [[TMP28]], ptr [[TMP33]], align 4
3157 // CHECK3-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
3158 // CHECK3-NEXT:    store ptr @.offload_maptypes.6, ptr [[TMP34]], align 4
3159 // CHECK3-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
3160 // CHECK3-NEXT:    store ptr null, ptr [[TMP35]], align 4
3161 // CHECK3-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
3162 // CHECK3-NEXT:    store ptr null, ptr [[TMP36]], align 4
3163 // CHECK3-NEXT:    [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
3164 // CHECK3-NEXT:    store i64 0, ptr [[TMP37]], align 8
3165 // CHECK3-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
3166 // CHECK3-NEXT:    store i64 0, ptr [[TMP38]], align 8
3167 // CHECK3-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
3168 // CHECK3-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP39]], align 4
3169 // CHECK3-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
3170 // CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP40]], align 4
3171 // CHECK3-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
3172 // CHECK3-NEXT:    store i32 0, ptr [[TMP41]], align 4
3173 // CHECK3-NEXT:    [[TMP42:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232.region_id, ptr [[KERNEL_ARGS]])
3174 // CHECK3-NEXT:    [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0
3175 // CHECK3-NEXT:    br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
3176 // CHECK3:       omp_offload.failed:
3177 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232(ptr [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], ptr [[VLA]]) #[[ATTR3]]
3178 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]
3179 // CHECK3:       omp_offload.cont:
3180 // CHECK3-NEXT:    br label [[OMP_IF_END:%.*]]
3181 // CHECK3:       omp_if.else:
3182 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232(ptr [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], ptr [[VLA]]) #[[ATTR3]]
3183 // CHECK3-NEXT:    br label [[OMP_IF_END]]
3184 // CHECK3:       omp_if.end:
3185 // CHECK3-NEXT:    [[TMP44:%.*]] = mul nsw i32 1, [[TMP1]]
3186 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP44]]
3187 // CHECK3-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1
3188 // CHECK3-NEXT:    [[TMP45:%.*]] = load i16, ptr [[ARRAYIDX2]], align 2
3189 // CHECK3-NEXT:    [[CONV:%.*]] = sext i16 [[TMP45]] to i32
3190 // CHECK3-NEXT:    [[TMP46:%.*]] = load i32, ptr [[B]], align 4
3191 // CHECK3-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP46]]
3192 // CHECK3-NEXT:    [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
3193 // CHECK3-NEXT:    call void @llvm.stackrestore.p0(ptr [[TMP47]])
3194 // CHECK3-NEXT:    ret i32 [[ADD3]]
3195 //
3196 //
3197 // CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici
3198 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
3199 // CHECK3-NEXT:  entry:
3200 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
3201 // CHECK3-NEXT:    [[A:%.*]] = alloca i32, align 4
3202 // CHECK3-NEXT:    [[AA:%.*]] = alloca i16, align 2
3203 // CHECK3-NEXT:    [[AAA:%.*]] = alloca i8, align 1
3204 // CHECK3-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
3205 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
3206 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
3207 // CHECK3-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
3208 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 4
3209 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 4
3210 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 4
3211 // CHECK3-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
3212 // CHECK3-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
3213 // CHECK3-NEXT:    store i32 0, ptr [[A]], align 4
3214 // CHECK3-NEXT:    store i16 0, ptr [[AA]], align 2
3215 // CHECK3-NEXT:    store i8 0, ptr [[AAA]], align 1
3216 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A]], align 4
3217 // CHECK3-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 4
3218 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4
3219 // CHECK3-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA]], align 2
3220 // CHECK3-NEXT:    store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
3221 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4
3222 // CHECK3-NEXT:    [[TMP4:%.*]] = load i8, ptr [[AAA]], align 1
3223 // CHECK3-NEXT:    store i8 [[TMP4]], ptr [[AAA_CASTED]], align 1
3224 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[AAA_CASTED]], align 4
3225 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4
3226 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50
3227 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
3228 // CHECK3:       omp_if.then:
3229 // CHECK3-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3230 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[TMP7]], align 4
3231 // CHECK3-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3232 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[TMP8]], align 4
3233 // CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
3234 // CHECK3-NEXT:    store ptr null, ptr [[TMP9]], align 4
3235 // CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
3236 // CHECK3-NEXT:    store i32 [[TMP3]], ptr [[TMP10]], align 4
3237 // CHECK3-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
3238 // CHECK3-NEXT:    store i32 [[TMP3]], ptr [[TMP11]], align 4
3239 // CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
3240 // CHECK3-NEXT:    store ptr null, ptr [[TMP12]], align 4
3241 // CHECK3-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
3242 // CHECK3-NEXT:    store i32 [[TMP5]], ptr [[TMP13]], align 4
3243 // CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
3244 // CHECK3-NEXT:    store i32 [[TMP5]], ptr [[TMP14]], align 4
3245 // CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
3246 // CHECK3-NEXT:    store ptr null, ptr [[TMP15]], align 4
3247 // CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
3248 // CHECK3-NEXT:    store ptr [[B]], ptr [[TMP16]], align 4
3249 // CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
3250 // CHECK3-NEXT:    store ptr [[B]], ptr [[TMP17]], align 4
3251 // CHECK3-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
3252 // CHECK3-NEXT:    store ptr null, ptr [[TMP18]], align 4
3253 // CHECK3-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3254 // CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3255 // CHECK3-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
3256 // CHECK3-NEXT:    store i32 2, ptr [[TMP21]], align 4
3257 // CHECK3-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
3258 // CHECK3-NEXT:    store i32 4, ptr [[TMP22]], align 4
3259 // CHECK3-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
3260 // CHECK3-NEXT:    store ptr [[TMP19]], ptr [[TMP23]], align 4
3261 // CHECK3-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
3262 // CHECK3-NEXT:    store ptr [[TMP20]], ptr [[TMP24]], align 4
3263 // CHECK3-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
3264 // CHECK3-NEXT:    store ptr @.offload_sizes.7, ptr [[TMP25]], align 4
3265 // CHECK3-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
3266 // CHECK3-NEXT:    store ptr @.offload_maptypes.8, ptr [[TMP26]], align 4
3267 // CHECK3-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
3268 // CHECK3-NEXT:    store ptr null, ptr [[TMP27]], align 4
3269 // CHECK3-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
3270 // CHECK3-NEXT:    store ptr null, ptr [[TMP28]], align 4
3271 // CHECK3-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
3272 // CHECK3-NEXT:    store i64 0, ptr [[TMP29]], align 8
3273 // CHECK3-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
3274 // CHECK3-NEXT:    store i64 0, ptr [[TMP30]], align 8
3275 // CHECK3-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
3276 // CHECK3-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP31]], align 4
3277 // CHECK3-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
3278 // CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP32]], align 4
3279 // CHECK3-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
3280 // CHECK3-NEXT:    store i32 0, ptr [[TMP33]], align 4
3281 // CHECK3-NEXT:    [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214.region_id, ptr [[KERNEL_ARGS]])
3282 // CHECK3-NEXT:    [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0
3283 // CHECK3-NEXT:    br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
3284 // CHECK3:       omp_offload.failed:
3285 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], ptr [[B]]) #[[ATTR3]]
3286 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]
3287 // CHECK3:       omp_offload.cont:
3288 // CHECK3-NEXT:    br label [[OMP_IF_END:%.*]]
3289 // CHECK3:       omp_if.else:
3290 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], ptr [[B]]) #[[ATTR3]]
3291 // CHECK3-NEXT:    br label [[OMP_IF_END]]
3292 // CHECK3:       omp_if.end:
3293 // CHECK3-NEXT:    [[TMP36:%.*]] = load i32, ptr [[A]], align 4
3294 // CHECK3-NEXT:    ret i32 [[TMP36]]
3295 //
3296 //
3297 // CHECK3-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
3298 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat {
3299 // CHECK3-NEXT:  entry:
3300 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
3301 // CHECK3-NEXT:    [[A:%.*]] = alloca i32, align 4
3302 // CHECK3-NEXT:    [[AA:%.*]] = alloca i16, align 2
3303 // CHECK3-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
3304 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
3305 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
3306 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 4
3307 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 4
3308 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 4
3309 // CHECK3-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
3310 // CHECK3-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
3311 // CHECK3-NEXT:    store i32 0, ptr [[A]], align 4
3312 // CHECK3-NEXT:    store i16 0, ptr [[AA]], align 2
3313 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A]], align 4
3314 // CHECK3-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 4
3315 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4
3316 // CHECK3-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA]], align 2
3317 // CHECK3-NEXT:    store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
3318 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4
3319 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
3320 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
3321 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
3322 // CHECK3:       omp_if.then:
3323 // CHECK3-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3324 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[TMP5]], align 4
3325 // CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3326 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[TMP6]], align 4
3327 // CHECK3-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
3328 // CHECK3-NEXT:    store ptr null, ptr [[TMP7]], align 4
3329 // CHECK3-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
3330 // CHECK3-NEXT:    store i32 [[TMP3]], ptr [[TMP8]], align 4
3331 // CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
3332 // CHECK3-NEXT:    store i32 [[TMP3]], ptr [[TMP9]], align 4
3333 // CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
3334 // CHECK3-NEXT:    store ptr null, ptr [[TMP10]], align 4
3335 // CHECK3-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
3336 // CHECK3-NEXT:    store ptr [[B]], ptr [[TMP11]], align 4
3337 // CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
3338 // CHECK3-NEXT:    store ptr [[B]], ptr [[TMP12]], align 4
3339 // CHECK3-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
3340 // CHECK3-NEXT:    store ptr null, ptr [[TMP13]], align 4
3341 // CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3342 // CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3343 // CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
3344 // CHECK3-NEXT:    store i32 2, ptr [[TMP16]], align 4
3345 // CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
3346 // CHECK3-NEXT:    store i32 3, ptr [[TMP17]], align 4
3347 // CHECK3-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
3348 // CHECK3-NEXT:    store ptr [[TMP14]], ptr [[TMP18]], align 4
3349 // CHECK3-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
3350 // CHECK3-NEXT:    store ptr [[TMP15]], ptr [[TMP19]], align 4
3351 // CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
3352 // CHECK3-NEXT:    store ptr @.offload_sizes.9, ptr [[TMP20]], align 4
3353 // CHECK3-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
3354 // CHECK3-NEXT:    store ptr @.offload_maptypes.10, ptr [[TMP21]], align 4
3355 // CHECK3-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
3356 // CHECK3-NEXT:    store ptr null, ptr [[TMP22]], align 4
3357 // CHECK3-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
3358 // CHECK3-NEXT:    store ptr null, ptr [[TMP23]], align 4
3359 // CHECK3-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
3360 // CHECK3-NEXT:    store i64 0, ptr [[TMP24]], align 8
3361 // CHECK3-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
3362 // CHECK3-NEXT:    store i64 0, ptr [[TMP25]], align 8
3363 // CHECK3-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
3364 // CHECK3-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP26]], align 4
3365 // CHECK3-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
3366 // CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP27]], align 4
3367 // CHECK3-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
3368 // CHECK3-NEXT:    store i32 0, ptr [[TMP28]], align 4
3369 // CHECK3-NEXT:    [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197.region_id, ptr [[KERNEL_ARGS]])
3370 // CHECK3-NEXT:    [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
3371 // CHECK3-NEXT:    br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
3372 // CHECK3:       omp_offload.failed:
3373 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR3]]
3374 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]
3375 // CHECK3:       omp_offload.cont:
3376 // CHECK3-NEXT:    br label [[OMP_IF_END:%.*]]
3377 // CHECK3:       omp_if.else:
3378 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR3]]
3379 // CHECK3-NEXT:    br label [[OMP_IF_END]]
3380 // CHECK3:       omp_if.end:
3381 // CHECK3-NEXT:    [[TMP31:%.*]] = load i32, ptr [[A]], align 4
3382 // CHECK3-NEXT:    ret i32 [[TMP31]]
3383 //
3384 //
3385 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232
3386 // CHECK3-SAME: (ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
3387 // CHECK3-NEXT:  entry:
3388 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
3389 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
3390 // CHECK3-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
3391 // CHECK3-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
3392 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
3393 // CHECK3-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
3394 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
3395 // CHECK3-NEXT:    store i32 [[B]], ptr [[B_ADDR]], align 4
3396 // CHECK3-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
3397 // CHECK3-NEXT:    store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
3398 // CHECK3-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
3399 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
3400 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
3401 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
3402 // CHECK3-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
3403 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4
3404 // CHECK3-NEXT:    store i32 [[TMP4]], ptr [[B_CASTED]], align 4
3405 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4
3406 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232.omp_outlined, ptr [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], ptr [[TMP3]])
3407 // CHECK3-NEXT:    ret void
3408 //
3409 //
3410 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232.omp_outlined
3411 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
3412 // CHECK3-NEXT:  entry:
3413 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
3414 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
3415 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
3416 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
3417 // CHECK3-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
3418 // CHECK3-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
3419 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
3420 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
3421 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i64, align 4
3422 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
3423 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
3424 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
3425 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3426 // CHECK3-NEXT:    [[IT:%.*]] = alloca i64, align 8
3427 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
3428 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
3429 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
3430 // CHECK3-NEXT:    store i32 [[B]], ptr [[B_ADDR]], align 4
3431 // CHECK3-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
3432 // CHECK3-NEXT:    store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
3433 // CHECK3-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
3434 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
3435 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
3436 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
3437 // CHECK3-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
3438 // CHECK3-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8
3439 // CHECK3-NEXT:    store i64 3, ptr [[DOTOMP_UB]], align 8
3440 // CHECK3-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8
3441 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
3442 // CHECK3-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
3443 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
3444 // CHECK3-NEXT:    call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP5]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
3445 // CHECK3-NEXT:    [[TMP6:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
3446 // CHECK3-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3
3447 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3448 // CHECK3:       cond.true:
3449 // CHECK3-NEXT:    br label [[COND_END:%.*]]
3450 // CHECK3:       cond.false:
3451 // CHECK3-NEXT:    [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
3452 // CHECK3-NEXT:    br label [[COND_END]]
3453 // CHECK3:       cond.end:
3454 // CHECK3-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
3455 // CHECK3-NEXT:    store i64 [[COND]], ptr [[DOTOMP_UB]], align 8
3456 // CHECK3-NEXT:    [[TMP8:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
3457 // CHECK3-NEXT:    store i64 [[TMP8]], ptr [[DOTOMP_IV]], align 8
3458 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
3459 // CHECK3:       omp.inner.for.cond:
3460 // CHECK3-NEXT:    [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
3461 // CHECK3-NEXT:    [[TMP10:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
3462 // CHECK3-NEXT:    [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
3463 // CHECK3-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3464 // CHECK3:       omp.inner.for.body:
3465 // CHECK3-NEXT:    [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
3466 // CHECK3-NEXT:    [[MUL:%.*]] = mul i64 [[TMP11]], 400
3467 // CHECK3-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
3468 // CHECK3-NEXT:    store i64 [[SUB]], ptr [[IT]], align 8
3469 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, ptr [[B_ADDR]], align 4
3470 // CHECK3-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP12]] to double
3471 // CHECK3-NEXT:    [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
3472 // CHECK3-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0
3473 // CHECK3-NEXT:    store double [[ADD]], ptr [[A]], align 4
3474 // CHECK3-NEXT:    [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0
3475 // CHECK3-NEXT:    [[TMP13:%.*]] = load double, ptr [[A4]], align 4
3476 // CHECK3-NEXT:    [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
3477 // CHECK3-NEXT:    store double [[INC]], ptr [[A4]], align 4
3478 // CHECK3-NEXT:    [[CONV5:%.*]] = fptosi double [[INC]] to i16
3479 // CHECK3-NEXT:    [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]]
3480 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i32 [[TMP14]]
3481 // CHECK3-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1
3482 // CHECK3-NEXT:    store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2
3483 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
3484 // CHECK3:       omp.body.continue:
3485 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
3486 // CHECK3:       omp.inner.for.inc:
3487 // CHECK3-NEXT:    [[TMP15:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
3488 // CHECK3-NEXT:    [[ADD7:%.*]] = add i64 [[TMP15]], 1
3489 // CHECK3-NEXT:    store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8
3490 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]]
3491 // CHECK3:       omp.inner.for.end:
3492 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
3493 // CHECK3:       omp.loop.exit:
3494 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])
3495 // CHECK3-NEXT:    ret void
3496 //
3497 //
3498 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214
3499 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
3500 // CHECK3-NEXT:  entry:
3501 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
3502 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
3503 // CHECK3-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
3504 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
3505 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
3506 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
3507 // CHECK3-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
3508 // CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
3509 // CHECK3-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
3510 // CHECK3-NEXT:    store i32 [[AAA]], ptr [[AAA_ADDR]], align 4
3511 // CHECK3-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
3512 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
3513 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
3514 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 4
3515 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4
3516 // CHECK3-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
3517 // CHECK3-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
3518 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4
3519 // CHECK3-NEXT:    [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 1
3520 // CHECK3-NEXT:    store i8 [[TMP5]], ptr [[AAA_CASTED]], align 1
3521 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[AAA_CASTED]], align 4
3522 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], ptr [[TMP0]])
3523 // CHECK3-NEXT:    ret void
3524 //
3525 //
3526 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214.omp_outlined
3527 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
3528 // CHECK3-NEXT:  entry:
3529 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
3530 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
3531 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
3532 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
3533 // CHECK3-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
3534 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
3535 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
3536 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
3537 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
3538 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
3539 // CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
3540 // CHECK3-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
3541 // CHECK3-NEXT:    store i32 [[AAA]], ptr [[AAA_ADDR]], align 4
3542 // CHECK3-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
3543 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
3544 // CHECK3-NEXT:    ret void
3545 //
3546 //
3547 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197
3548 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
3549 // CHECK3-NEXT:  entry:
3550 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
3551 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
3552 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
3553 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
3554 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
3555 // CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
3556 // CHECK3-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
3557 // CHECK3-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
3558 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
3559 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
3560 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 4
3561 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4
3562 // CHECK3-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
3563 // CHECK3-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
3564 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4
3565 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], ptr [[TMP0]])
3566 // CHECK3-NEXT:    ret void
3567 //
3568 //
3569 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197.omp_outlined
3570 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
3571 // CHECK3-NEXT:  entry:
3572 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
3573 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
3574 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
3575 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
3576 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
3577 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
3578 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i64, align 4
3579 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
3580 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
3581 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
3582 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3583 // CHECK3-NEXT:    [[I:%.*]] = alloca i64, align 8
3584 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
3585 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
3586 // CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
3587 // CHECK3-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
3588 // CHECK3-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
3589 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
3590 // CHECK3-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8
3591 // CHECK3-NEXT:    store i64 6, ptr [[DOTOMP_UB]], align 8
3592 // CHECK3-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8
3593 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
3594 // CHECK3-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
3595 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
3596 // CHECK3-NEXT:    call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP2]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
3597 // CHECK3-NEXT:    [[TMP3:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
3598 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
3599 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3600 // CHECK3:       cond.true:
3601 // CHECK3-NEXT:    br label [[COND_END:%.*]]
3602 // CHECK3:       cond.false:
3603 // CHECK3-NEXT:    [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
3604 // CHECK3-NEXT:    br label [[COND_END]]
3605 // CHECK3:       cond.end:
3606 // CHECK3-NEXT:    [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
3607 // CHECK3-NEXT:    store i64 [[COND]], ptr [[DOTOMP_UB]], align 8
3608 // CHECK3-NEXT:    [[TMP5:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
3609 // CHECK3-NEXT:    store i64 [[TMP5]], ptr [[DOTOMP_IV]], align 8
3610 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
3611 // CHECK3:       omp.inner.for.cond:
3612 // CHECK3-NEXT:    [[TMP6:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
3613 // CHECK3-NEXT:    [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
3614 // CHECK3-NEXT:    [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
3615 // CHECK3-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3616 // CHECK3:       omp.inner.for.body:
3617 // CHECK3-NEXT:    [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
3618 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
3619 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
3620 // CHECK3-NEXT:    store i64 [[ADD]], ptr [[I]], align 8
3621 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4
3622 // CHECK3-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
3623 // CHECK3-NEXT:    store i32 [[ADD2]], ptr [[A_ADDR]], align 4
3624 // CHECK3-NEXT:    [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2
3625 // CHECK3-NEXT:    [[CONV:%.*]] = sext i16 [[TMP10]] to i32
3626 // CHECK3-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV]], 1
3627 // CHECK3-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
3628 // CHECK3-NEXT:    store i16 [[CONV4]], ptr [[AA_ADDR]], align 2
3629 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2
3630 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
3631 // CHECK3-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1
3632 // CHECK3-NEXT:    store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4
3633 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
3634 // CHECK3:       omp.body.continue:
3635 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
3636 // CHECK3:       omp.inner.for.inc:
3637 // CHECK3-NEXT:    [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
3638 // CHECK3-NEXT:    [[ADD6:%.*]] = add nsw i64 [[TMP12]], 1
3639 // CHECK3-NEXT:    store i64 [[ADD6]], ptr [[DOTOMP_IV]], align 8
3640 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]]
3641 // CHECK3:       omp.inner.for.end:
3642 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
3643 // CHECK3:       omp.loop.exit:
3644 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])
3645 // CHECK3-NEXT:    ret void
3646 //
3647 //
3648 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
3649 // CHECK3-SAME: () #[[ATTR5]] {
3650 // CHECK3-NEXT:  entry:
3651 // CHECK3-NEXT:    call void @__tgt_register_requires(i64 1)
3652 // CHECK3-NEXT:    ret void
3653 //
3654 //
3655 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
3656 // CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
3657 // CHECK9-NEXT:  entry:
3658 // CHECK9-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
3659 // CHECK9-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
3660 // CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined)
3661 // CHECK9-NEXT:    ret void
3662 //
3663 //
3664 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined
3665 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
3666 // CHECK9-NEXT:  entry:
3667 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
3668 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
3669 // CHECK9-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
3670 // CHECK9-NEXT:    [[TMP:%.*]] = alloca i32, align 4
3671 // CHECK9-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
3672 // CHECK9-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
3673 // CHECK9-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3674 // CHECK9-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3675 // CHECK9-NEXT:    [[I:%.*]] = alloca i32, align 4
3676 // CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
3677 // CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
3678 // CHECK9-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
3679 // CHECK9-NEXT:    store i32 5, ptr [[DOTOMP_UB]], align 4
3680 // CHECK9-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
3681 // CHECK9-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
3682 // CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
3683 // CHECK9-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
3684 // CHECK9-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
3685 // CHECK9-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
3686 // CHECK9-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
3687 // CHECK9-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3688 // CHECK9:       cond.true:
3689 // CHECK9-NEXT:    br label [[COND_END:%.*]]
3690 // CHECK9:       cond.false:
3691 // CHECK9-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
3692 // CHECK9-NEXT:    br label [[COND_END]]
3693 // CHECK9:       cond.end:
3694 // CHECK9-NEXT:    [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
3695 // CHECK9-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
3696 // CHECK9-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
3697 // CHECK9-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
3698 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
3699 // CHECK9:       omp.inner.for.cond:
3700 // CHECK9-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3701 // CHECK9-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
3702 // CHECK9-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
3703 // CHECK9-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3704 // CHECK9:       omp.inner.for.body:
3705 // CHECK9-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3706 // CHECK9-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
3707 // CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 3, [[MUL]]
3708 // CHECK9-NEXT:    store i32 [[ADD]], ptr [[I]], align 4
3709 // CHECK9-NEXT:    [[TMP8:%.*]] = call i32 @__kmpc_cancel(ptr @[[GLOB2]], i32 [[TMP1]], i32 2)
3710 // CHECK9-NEXT:    [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0
3711 // CHECK9-NEXT:    br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
3712 // CHECK9:       .cancel.exit:
3713 // CHECK9-NEXT:    br label [[CANCEL_EXIT:%.*]]
3714 // CHECK9:       .cancel.continue:
3715 // CHECK9-NEXT:    [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(ptr @[[GLOB2]], i32 [[TMP1]], i32 2)
3716 // CHECK9-NEXT:    [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
3717 // CHECK9-NEXT:    br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]]
3718 // CHECK9:       .cancel.exit2:
3719 // CHECK9-NEXT:    br label [[CANCEL_EXIT]]
3720 // CHECK9:       .cancel.continue3:
3721 // CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
3722 // CHECK9:       omp.body.continue:
3723 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
3724 // CHECK9:       omp.inner.for.inc:
3725 // CHECK9-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3726 // CHECK9-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
3727 // CHECK9-NEXT:    store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4
3728 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND]]
3729 // CHECK9:       omp.inner.for.end:
3730 // CHECK9-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
3731 // CHECK9:       omp.loop.exit:
3732 // CHECK9-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
3733 // CHECK9-NEXT:    br label [[CANCEL_CONT:%.*]]
3734 // CHECK9:       cancel.cont:
3735 // CHECK9-NEXT:    ret void
3736 // CHECK9:       cancel.exit:
3737 // CHECK9-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
3738 // CHECK9-NEXT:    br label [[CANCEL_CONT]]
3739 //
3740 //
3741 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128
3742 // CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] {
3743 // CHECK9-NEXT:  entry:
3744 // CHECK9-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
3745 // CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
3746 // CHECK9-NEXT:    [[LIN_ADDR:%.*]] = alloca i64, align 8
3747 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
3748 // CHECK9-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
3749 // CHECK9-NEXT:    [[LIN_CASTED:%.*]] = alloca i64, align 8
3750 // CHECK9-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
3751 // CHECK9-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
3752 // CHECK9-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
3753 // CHECK9-NEXT:    store i64 [[LIN]], ptr [[LIN_ADDR]], align 8
3754 // CHECK9-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
3755 // CHECK9-NEXT:    [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2
3756 // CHECK9-NEXT:    store i16 [[TMP0]], ptr [[AA_CASTED]], align 2
3757 // CHECK9-NEXT:    [[TMP1:%.*]] = load i64, ptr [[AA_CASTED]], align 8
3758 // CHECK9-NEXT:    [[TMP2:%.*]] = load i32, ptr [[LIN_ADDR]], align 4
3759 // CHECK9-NEXT:    store i32 [[TMP2]], ptr [[LIN_CASTED]], align 4
3760 // CHECK9-NEXT:    [[TMP3:%.*]] = load i64, ptr [[LIN_CASTED]], align 8
3761 // CHECK9-NEXT:    [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4
3762 // CHECK9-NEXT:    store i32 [[TMP4]], ptr [[A_CASTED]], align 4
3763 // CHECK9-NEXT:    [[TMP5:%.*]] = load i64, ptr [[A_CASTED]], align 8
3764 // CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128.omp_outlined, i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]])
3765 // CHECK9-NEXT:    ret void
3766 //
3767 //
3768 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128.omp_outlined
3769 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] {
3770 // CHECK9-NEXT:  entry:
3771 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
3772 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
3773 // CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
3774 // CHECK9-NEXT:    [[LIN_ADDR:%.*]] = alloca i64, align 8
3775 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
3776 // CHECK9-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
3777 // CHECK9-NEXT:    [[TMP:%.*]] = alloca i64, align 8
3778 // CHECK9-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i32, align 4
3779 // CHECK9-NEXT:    [[DOTLINEAR_START1:%.*]] = alloca i32, align 4
3780 // CHECK9-NEXT:    [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
3781 // CHECK9-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
3782 // CHECK9-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
3783 // CHECK9-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
3784 // CHECK9-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3785 // CHECK9-NEXT:    [[IT:%.*]] = alloca i64, align 8
3786 // CHECK9-NEXT:    [[LIN2:%.*]] = alloca i32, align 4
3787 // CHECK9-NEXT:    [[A3:%.*]] = alloca i32, align 4
3788 // CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
3789 // CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
3790 // CHECK9-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
3791 // CHECK9-NEXT:    store i64 [[LIN]], ptr [[LIN_ADDR]], align 8
3792 // CHECK9-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
3793 // CHECK9-NEXT:    [[TMP0:%.*]] = load i32, ptr [[LIN_ADDR]], align 4
3794 // CHECK9-NEXT:    store i32 [[TMP0]], ptr [[DOTLINEAR_START]], align 4
3795 // CHECK9-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
3796 // CHECK9-NEXT:    store i32 [[TMP1]], ptr [[DOTLINEAR_START1]], align 4
3797 // CHECK9-NEXT:    [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR4:[0-9]+]]
3798 // CHECK9-NEXT:    store i64 [[CALL]], ptr [[DOTLINEAR_STEP]], align 8
3799 // CHECK9-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8
3800 // CHECK9-NEXT:    store i64 3, ptr [[DOTOMP_UB]], align 8
3801 // CHECK9-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8
3802 // CHECK9-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
3803 // CHECK9-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
3804 // CHECK9-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
3805 // CHECK9-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP3]])
3806 // CHECK9-NEXT:    call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
3807 // CHECK9-NEXT:    [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
3808 // CHECK9-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
3809 // CHECK9-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3810 // CHECK9:       cond.true:
3811 // CHECK9-NEXT:    br label [[COND_END:%.*]]
3812 // CHECK9:       cond.false:
3813 // CHECK9-NEXT:    [[TMP5:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
3814 // CHECK9-NEXT:    br label [[COND_END]]
3815 // CHECK9:       cond.end:
3816 // CHECK9-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
3817 // CHECK9-NEXT:    store i64 [[COND]], ptr [[DOTOMP_UB]], align 8
3818 // CHECK9-NEXT:    [[TMP6:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
3819 // CHECK9-NEXT:    store i64 [[TMP6]], ptr [[DOTOMP_IV]], align 8
3820 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
3821 // CHECK9:       omp.inner.for.cond:
3822 // CHECK9-NEXT:    [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
3823 // CHECK9-NEXT:    [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
3824 // CHECK9-NEXT:    [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
3825 // CHECK9-NEXT:    br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3826 // CHECK9:       omp.inner.for.body:
3827 // CHECK9-NEXT:    [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
3828 // CHECK9-NEXT:    [[MUL:%.*]] = mul i64 [[TMP9]], 400
3829 // CHECK9-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
3830 // CHECK9-NEXT:    store i64 [[SUB]], ptr [[IT]], align 8
3831 // CHECK9-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTLINEAR_START]], align 4
3832 // CHECK9-NEXT:    [[CONV:%.*]] = sext i32 [[TMP10]] to i64
3833 // CHECK9-NEXT:    [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
3834 // CHECK9-NEXT:    [[TMP12:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8
3835 // CHECK9-NEXT:    [[MUL5:%.*]] = mul i64 [[TMP11]], [[TMP12]]
3836 // CHECK9-NEXT:    [[ADD:%.*]] = add i64 [[CONV]], [[MUL5]]
3837 // CHECK9-NEXT:    [[CONV6:%.*]] = trunc i64 [[ADD]] to i32
3838 // CHECK9-NEXT:    store i32 [[CONV6]], ptr [[LIN2]], align 4
3839 // CHECK9-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTLINEAR_START1]], align 4
3840 // CHECK9-NEXT:    [[CONV7:%.*]] = sext i32 [[TMP13]] to i64
3841 // CHECK9-NEXT:    [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
3842 // CHECK9-NEXT:    [[TMP15:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8
3843 // CHECK9-NEXT:    [[MUL8:%.*]] = mul i64 [[TMP14]], [[TMP15]]
3844 // CHECK9-NEXT:    [[ADD9:%.*]] = add i64 [[CONV7]], [[MUL8]]
3845 // CHECK9-NEXT:    [[CONV10:%.*]] = trunc i64 [[ADD9]] to i32
3846 // CHECK9-NEXT:    store i32 [[CONV10]], ptr [[A3]], align 4
3847 // CHECK9-NEXT:    [[TMP16:%.*]] = load i16, ptr [[AA_ADDR]], align 2
3848 // CHECK9-NEXT:    [[CONV11:%.*]] = sext i16 [[TMP16]] to i32
3849 // CHECK9-NEXT:    [[ADD12:%.*]] = add nsw i32 [[CONV11]], 1
3850 // CHECK9-NEXT:    [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16
3851 // CHECK9-NEXT:    store i16 [[CONV13]], ptr [[AA_ADDR]], align 2
3852 // CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
3853 // CHECK9:       omp.body.continue:
3854 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
3855 // CHECK9:       omp.inner.for.inc:
3856 // CHECK9-NEXT:    [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
3857 // CHECK9-NEXT:    [[ADD14:%.*]] = add i64 [[TMP17]], 1
3858 // CHECK9-NEXT:    store i64 [[ADD14]], ptr [[DOTOMP_IV]], align 8
3859 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND]]
3860 // CHECK9:       omp.inner.for.end:
3861 // CHECK9-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
3862 // CHECK9:       omp.loop.exit:
3863 // CHECK9-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]])
3864 // CHECK9-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
3865 // CHECK9-NEXT:    [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
3866 // CHECK9-NEXT:    br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
3867 // CHECK9:       .omp.linear.pu:
3868 // CHECK9-NEXT:    [[TMP20:%.*]] = load i32, ptr [[LIN2]], align 4
3869 // CHECK9-NEXT:    store i32 [[TMP20]], ptr [[LIN_ADDR]], align 4
3870 // CHECK9-NEXT:    [[TMP21:%.*]] = load i32, ptr [[A3]], align 4
3871 // CHECK9-NEXT:    store i32 [[TMP21]], ptr [[A_ADDR]], align 4
3872 // CHECK9-NEXT:    br label [[DOTOMP_LINEAR_PU_DONE]]
3873 // CHECK9:       .omp.linear.pu.done:
3874 // CHECK9-NEXT:    ret void
3875 //
3876 //
3877 // CHECK9-LABEL: define {{[^@]+}}@_Z7get_valv
3878 // CHECK9-SAME: () #[[ATTR2:[0-9]+]] {
3879 // CHECK9-NEXT:  entry:
3880 // CHECK9-NEXT:    ret i64 0
3881 //
3882 //
3883 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136
3884 // CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {
3885 // CHECK9-NEXT:  entry:
3886 // CHECK9-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
3887 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
3888 // CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
3889 // CHECK9-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
3890 // CHECK9-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
3891 // CHECK9-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
3892 // CHECK9-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
3893 // CHECK9-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
3894 // CHECK9-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
3895 // CHECK9-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 4
3896 // CHECK9-NEXT:    [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8
3897 // CHECK9-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2
3898 // CHECK9-NEXT:    store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
3899 // CHECK9-NEXT:    [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8
3900 // CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.omp_outlined, i64 [[TMP1]], i64 [[TMP3]])
3901 // CHECK9-NEXT:    ret void
3902 //
3903 //
3904 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.omp_outlined
3905 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {
3906 // CHECK9-NEXT:  entry:
3907 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
3908 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
3909 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
3910 // CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
3911 // CHECK9-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
3912 // CHECK9-NEXT:    [[TMP:%.*]] = alloca i16, align 2
3913 // CHECK9-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
3914 // CHECK9-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
3915 // CHECK9-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3916 // CHECK9-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3917 // CHECK9-NEXT:    [[IT:%.*]] = alloca i16, align 2
3918 // CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
3919 // CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
3920 // CHECK9-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
3921 // CHECK9-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
3922 // CHECK9-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
3923 // CHECK9-NEXT:    store i32 3, ptr [[DOTOMP_UB]], align 4
3924 // CHECK9-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
3925 // CHECK9-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
3926 // CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
3927 // CHECK9-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
3928 // CHECK9-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
3929 // CHECK9-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
3930 // CHECK9-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
3931 // CHECK9-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3932 // CHECK9:       cond.true:
3933 // CHECK9-NEXT:    br label [[COND_END:%.*]]
3934 // CHECK9:       cond.false:
3935 // CHECK9-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
3936 // CHECK9-NEXT:    br label [[COND_END]]
3937 // CHECK9:       cond.end:
3938 // CHECK9-NEXT:    [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
3939 // CHECK9-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
3940 // CHECK9-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
3941 // CHECK9-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
3942 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
3943 // CHECK9:       omp.inner.for.cond:
3944 // CHECK9-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3945 // CHECK9-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
3946 // CHECK9-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
3947 // CHECK9-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3948 // CHECK9:       omp.inner.for.body:
3949 // CHECK9-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3950 // CHECK9-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
3951 // CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 6, [[MUL]]
3952 // CHECK9-NEXT:    [[CONV:%.*]] = trunc i32 [[ADD]] to i16
3953 // CHECK9-NEXT:    store i16 [[CONV]], ptr [[IT]], align 2
3954 // CHECK9-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
3955 // CHECK9-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
3956 // CHECK9-NEXT:    store i32 [[ADD2]], ptr [[A_ADDR]], align 4
3957 // CHECK9-NEXT:    [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2
3958 // CHECK9-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP9]] to i32
3959 // CHECK9-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
3960 // CHECK9-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
3961 // CHECK9-NEXT:    store i16 [[CONV5]], ptr [[AA_ADDR]], align 2
3962 // CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
3963 // CHECK9:       omp.body.continue:
3964 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
3965 // CHECK9:       omp.inner.for.inc:
3966 // CHECK9-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3967 // CHECK9-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1
3968 // CHECK9-NEXT:    store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4
3969 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND]]
3970 // CHECK9:       omp.inner.for.end:
3971 // CHECK9-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
3972 // CHECK9:       omp.loop.exit:
3973 // CHECK9-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
3974 // CHECK9-NEXT:    ret void
3975 //
3976 //
3977 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160
3978 // CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
3979 // CHECK9-NEXT:  entry:
3980 // CHECK9-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
3981 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
3982 // CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
3983 // CHECK9-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
3984 // CHECK9-NEXT:    [[BN_ADDR:%.*]] = alloca ptr, align 8
3985 // CHECK9-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
3986 // CHECK9-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
3987 // CHECK9-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
3988 // CHECK9-NEXT:    [[CN_ADDR:%.*]] = alloca ptr, align 8
3989 // CHECK9-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
3990 // CHECK9-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
3991 // CHECK9-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
3992 // CHECK9-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
3993 // CHECK9-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
3994 // CHECK9-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
3995 // CHECK9-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
3996 // CHECK9-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
3997 // CHECK9-NEXT:    store ptr [[BN]], ptr [[BN_ADDR]], align 8
3998 // CHECK9-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
3999 // CHECK9-NEXT:    store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
4000 // CHECK9-NEXT:    store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8
4001 // CHECK9-NEXT:    store ptr [[CN]], ptr [[CN_ADDR]], align 8
4002 // CHECK9-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
4003 // CHECK9-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
4004 // CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
4005 // CHECK9-NEXT:    [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
4006 // CHECK9-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8
4007 // CHECK9-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
4008 // CHECK9-NEXT:    [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
4009 // CHECK9-NEXT:    [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8
4010 // CHECK9-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8
4011 // CHECK9-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8
4012 // CHECK9-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
4013 // CHECK9-NEXT:    store i32 [[TMP8]], ptr [[A_CASTED]], align 4
4014 // CHECK9-NEXT:    [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 8
4015 // CHECK9-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
4016 // CHECK9-NEXT:    store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
4017 // CHECK9-NEXT:    [[TMP11:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8
4018 // CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined, i64 [[TMP9]], ptr [[TMP0]], i64 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i64 [[TMP11]])
4019 // CHECK9-NEXT:    ret void
4020 //
4021 //
4022 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined
4023 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
4024 // CHECK9-NEXT:  entry:
4025 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
4026 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
4027 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
4028 // CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
4029 // CHECK9-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
4030 // CHECK9-NEXT:    [[BN_ADDR:%.*]] = alloca ptr, align 8
4031 // CHECK9-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
4032 // CHECK9-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
4033 // CHECK9-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
4034 // CHECK9-NEXT:    [[CN_ADDR:%.*]] = alloca ptr, align 8
4035 // CHECK9-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
4036 // CHECK9-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
4037 // CHECK9-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
4038 // CHECK9-NEXT:    [[TMP:%.*]] = alloca i8, align 1
4039 // CHECK9-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
4040 // CHECK9-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
4041 // CHECK9-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4042 // CHECK9-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4043 // CHECK9-NEXT:    [[IT:%.*]] = alloca i8, align 1
4044 // CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
4045 // CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
4046 // CHECK9-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
4047 // CHECK9-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
4048 // CHECK9-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
4049 // CHECK9-NEXT:    store ptr [[BN]], ptr [[BN_ADDR]], align 8
4050 // CHECK9-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
4051 // CHECK9-NEXT:    store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
4052 // CHECK9-NEXT:    store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8
4053 // CHECK9-NEXT:    store ptr [[CN]], ptr [[CN_ADDR]], align 8
4054 // CHECK9-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
4055 // CHECK9-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
4056 // CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
4057 // CHECK9-NEXT:    [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
4058 // CHECK9-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8
4059 // CHECK9-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
4060 // CHECK9-NEXT:    [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
4061 // CHECK9-NEXT:    [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8
4062 // CHECK9-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8
4063 // CHECK9-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8
4064 // CHECK9-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
4065 // CHECK9-NEXT:    store i32 25, ptr [[DOTOMP_UB]], align 4
4066 // CHECK9-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
4067 // CHECK9-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
4068 // CHECK9-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
4069 // CHECK9-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
4070 // CHECK9-NEXT:    [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4
4071 // CHECK9-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP10]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
4072 // CHECK9-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
4073 // CHECK9:       omp.dispatch.cond:
4074 // CHECK9-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4075 // CHECK9-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
4076 // CHECK9-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4077 // CHECK9:       cond.true:
4078 // CHECK9-NEXT:    br label [[COND_END:%.*]]
4079 // CHECK9:       cond.false:
4080 // CHECK9-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4081 // CHECK9-NEXT:    br label [[COND_END]]
4082 // CHECK9:       cond.end:
4083 // CHECK9-NEXT:    [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
4084 // CHECK9-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
4085 // CHECK9-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
4086 // CHECK9-NEXT:    store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4
4087 // CHECK9-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4088 // CHECK9-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4089 // CHECK9-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
4090 // CHECK9-NEXT:    br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
4091 // CHECK9:       omp.dispatch.body:
4092 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
4093 // CHECK9:       omp.inner.for.cond:
4094 // CHECK9-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4095 // CHECK9-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4096 // CHECK9-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
4097 // CHECK9-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4098 // CHECK9:       omp.inner.for.body:
4099 // CHECK9-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4100 // CHECK9-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
4101 // CHECK9-NEXT:    [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
4102 // CHECK9-NEXT:    [[CONV:%.*]] = trunc i32 [[SUB]] to i8
4103 // CHECK9-NEXT:    store i8 [[CONV]], ptr [[IT]], align 1
4104 // CHECK9-NEXT:    [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4
4105 // CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
4106 // CHECK9-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 4
4107 // CHECK9-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 2
4108 // CHECK9-NEXT:    [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4
4109 // CHECK9-NEXT:    [[CONV7:%.*]] = fpext float [[TMP20]] to double
4110 // CHECK9-NEXT:    [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00
4111 // CHECK9-NEXT:    [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
4112 // CHECK9-NEXT:    store float [[CONV9]], ptr [[ARRAYIDX]], align 4
4113 // CHECK9-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 3
4114 // CHECK9-NEXT:    [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4
4115 // CHECK9-NEXT:    [[CONV11:%.*]] = fpext float [[TMP21]] to double
4116 // CHECK9-NEXT:    [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
4117 // CHECK9-NEXT:    [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
4118 // CHECK9-NEXT:    store float [[CONV13]], ptr [[ARRAYIDX10]], align 4
4119 // CHECK9-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 1
4120 // CHECK9-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i64 0, i64 2
4121 // CHECK9-NEXT:    [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8
4122 // CHECK9-NEXT:    [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
4123 // CHECK9-NEXT:    store double [[ADD16]], ptr [[ARRAYIDX15]], align 8
4124 // CHECK9-NEXT:    [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]
4125 // CHECK9-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i64 [[TMP23]]
4126 // CHECK9-NEXT:    [[ARRAYIDX18:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX17]], i64 3
4127 // CHECK9-NEXT:    [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 8
4128 // CHECK9-NEXT:    [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
4129 // CHECK9-NEXT:    store double [[ADD19]], ptr [[ARRAYIDX18]], align 8
4130 // CHECK9-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0
4131 // CHECK9-NEXT:    [[TMP25:%.*]] = load i64, ptr [[X]], align 8
4132 // CHECK9-NEXT:    [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
4133 // CHECK9-NEXT:    store i64 [[ADD20]], ptr [[X]], align 8
4134 // CHECK9-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1
4135 // CHECK9-NEXT:    [[TMP26:%.*]] = load i8, ptr [[Y]], align 8
4136 // CHECK9-NEXT:    [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
4137 // CHECK9-NEXT:    [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
4138 // CHECK9-NEXT:    [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
4139 // CHECK9-NEXT:    store i8 [[CONV23]], ptr [[Y]], align 8
4140 // CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
4141 // CHECK9:       omp.body.continue:
4142 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4143 // CHECK9:       omp.inner.for.inc:
4144 // CHECK9-NEXT:    [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4145 // CHECK9-NEXT:    [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
4146 // CHECK9-NEXT:    store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4
4147 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND]]
4148 // CHECK9:       omp.inner.for.end:
4149 // CHECK9-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
4150 // CHECK9:       omp.dispatch.inc:
4151 // CHECK9-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
4152 // CHECK9-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
4153 // CHECK9-NEXT:    [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
4154 // CHECK9-NEXT:    store i32 [[ADD25]], ptr [[DOTOMP_LB]], align 4
4155 // CHECK9-NEXT:    [[TMP30:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4156 // CHECK9-NEXT:    [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
4157 // CHECK9-NEXT:    [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
4158 // CHECK9-NEXT:    store i32 [[ADD26]], ptr [[DOTOMP_UB]], align 4
4159 // CHECK9-NEXT:    br label [[OMP_DISPATCH_COND]]
4160 // CHECK9:       omp.dispatch.end:
4161 // CHECK9-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP10]])
4162 // CHECK9-NEXT:    ret void
4163 //
4164 //
4165 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214
4166 // CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
4167 // CHECK9-NEXT:  entry:
4168 // CHECK9-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
4169 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
4170 // CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
4171 // CHECK9-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
4172 // CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
4173 // CHECK9-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
4174 // CHECK9-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
4175 // CHECK9-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
4176 // CHECK9-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
4177 // CHECK9-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
4178 // CHECK9-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
4179 // CHECK9-NEXT:    store i64 [[AAA]], ptr [[AAA_ADDR]], align 8
4180 // CHECK9-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
4181 // CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
4182 // CHECK9-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
4183 // CHECK9-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 4
4184 // CHECK9-NEXT:    [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8
4185 // CHECK9-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
4186 // CHECK9-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
4187 // CHECK9-NEXT:    [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8
4188 // CHECK9-NEXT:    [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 1
4189 // CHECK9-NEXT:    store i8 [[TMP5]], ptr [[AAA_CASTED]], align 1
4190 // CHECK9-NEXT:    [[TMP6:%.*]] = load i64, ptr [[AAA_CASTED]], align 8
4191 // CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], ptr [[TMP0]])
4192 // CHECK9-NEXT:    ret void
4193 //
4194 //
4195 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214.omp_outlined
4196 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
4197 // CHECK9-NEXT:  entry:
4198 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
4199 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
4200 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
4201 // CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
4202 // CHECK9-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
4203 // CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
4204 // CHECK9-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
4205 // CHECK9-NEXT:    [[TMP:%.*]] = alloca i32, align 4
4206 // CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
4207 // CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
4208 // CHECK9-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
4209 // CHECK9-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
4210 // CHECK9-NEXT:    store i64 [[AAA]], ptr [[AAA_ADDR]], align 8
4211 // CHECK9-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
4212 // CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
4213 // CHECK9-NEXT:    ret void
4214 //
4215 //
4216 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232
4217 // CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
4218 // CHECK9-NEXT:  entry:
4219 // CHECK9-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
4220 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
4221 // CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
4222 // CHECK9-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
4223 // CHECK9-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
4224 // CHECK9-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
4225 // CHECK9-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
4226 // CHECK9-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
4227 // CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
4228 // CHECK9-NEXT:    store i64 [[B]], ptr [[B_ADDR]], align 8
4229 // CHECK9-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
4230 // CHECK9-NEXT:    store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
4231 // CHECK9-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
4232 // CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
4233 // CHECK9-NEXT:    [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
4234 // CHECK9-NEXT:    [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
4235 // CHECK9-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
4236 // CHECK9-NEXT:    [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4
4237 // CHECK9-NEXT:    store i32 [[TMP4]], ptr [[B_CASTED]], align 4
4238 // CHECK9-NEXT:    [[TMP5:%.*]] = load i64, ptr [[B_CASTED]], align 8
4239 // CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232.omp_outlined, ptr [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], ptr [[TMP3]])
4240 // CHECK9-NEXT:    ret void
4241 //
4242 //
4243 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232.omp_outlined
4244 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
4245 // CHECK9-NEXT:  entry:
4246 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
4247 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
4248 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
4249 // CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
4250 // CHECK9-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
4251 // CHECK9-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
4252 // CHECK9-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
4253 // CHECK9-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
4254 // CHECK9-NEXT:    [[TMP:%.*]] = alloca i64, align 8
4255 // CHECK9-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
4256 // CHECK9-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
4257 // CHECK9-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
4258 // CHECK9-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4259 // CHECK9-NEXT:    [[IT:%.*]] = alloca i64, align 8
4260 // CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
4261 // CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
4262 // CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
4263 // CHECK9-NEXT:    store i64 [[B]], ptr [[B_ADDR]], align 8
4264 // CHECK9-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
4265 // CHECK9-NEXT:    store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
4266 // CHECK9-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
4267 // CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
4268 // CHECK9-NEXT:    [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
4269 // CHECK9-NEXT:    [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
4270 // CHECK9-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
4271 // CHECK9-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8
4272 // CHECK9-NEXT:    store i64 3, ptr [[DOTOMP_UB]], align 8
4273 // CHECK9-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8
4274 // CHECK9-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
4275 // CHECK9-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
4276 // CHECK9-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
4277 // CHECK9-NEXT:    call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP5]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
4278 // CHECK9-NEXT:    [[TMP6:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
4279 // CHECK9-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3
4280 // CHECK9-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4281 // CHECK9:       cond.true:
4282 // CHECK9-NEXT:    br label [[COND_END:%.*]]
4283 // CHECK9:       cond.false:
4284 // CHECK9-NEXT:    [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
4285 // CHECK9-NEXT:    br label [[COND_END]]
4286 // CHECK9:       cond.end:
4287 // CHECK9-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
4288 // CHECK9-NEXT:    store i64 [[COND]], ptr [[DOTOMP_UB]], align 8
4289 // CHECK9-NEXT:    [[TMP8:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
4290 // CHECK9-NEXT:    store i64 [[TMP8]], ptr [[DOTOMP_IV]], align 8
4291 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
4292 // CHECK9:       omp.inner.for.cond:
4293 // CHECK9-NEXT:    [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
4294 // CHECK9-NEXT:    [[TMP10:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
4295 // CHECK9-NEXT:    [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
4296 // CHECK9-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4297 // CHECK9:       omp.inner.for.body:
4298 // CHECK9-NEXT:    [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
4299 // CHECK9-NEXT:    [[MUL:%.*]] = mul i64 [[TMP11]], 400
4300 // CHECK9-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
4301 // CHECK9-NEXT:    store i64 [[SUB]], ptr [[IT]], align 8
4302 // CHECK9-NEXT:    [[TMP12:%.*]] = load i32, ptr [[B_ADDR]], align 4
4303 // CHECK9-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP12]] to double
4304 // CHECK9-NEXT:    [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
4305 // CHECK9-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0
4306 // CHECK9-NEXT:    store double [[ADD]], ptr [[A]], align 8
4307 // CHECK9-NEXT:    [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0
4308 // CHECK9-NEXT:    [[TMP13:%.*]] = load double, ptr [[A4]], align 8
4309 // CHECK9-NEXT:    [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
4310 // CHECK9-NEXT:    store double [[INC]], ptr [[A4]], align 8
4311 // CHECK9-NEXT:    [[CONV5:%.*]] = fptosi double [[INC]] to i16
4312 // CHECK9-NEXT:    [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]]
4313 // CHECK9-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i64 [[TMP14]]
4314 // CHECK9-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1
4315 // CHECK9-NEXT:    store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2
4316 // CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
4317 // CHECK9:       omp.body.continue:
4318 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4319 // CHECK9:       omp.inner.for.inc:
4320 // CHECK9-NEXT:    [[TMP15:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
4321 // CHECK9-NEXT:    [[ADD7:%.*]] = add i64 [[TMP15]], 1
4322 // CHECK9-NEXT:    store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8
4323 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND]]
4324 // CHECK9:       omp.inner.for.end:
4325 // CHECK9-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
4326 // CHECK9:       omp.loop.exit:
4327 // CHECK9-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])
4328 // CHECK9-NEXT:    ret void
4329 //
4330 //
4331 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197
4332 // CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
4333 // CHECK9-NEXT:  entry:
4334 // CHECK9-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
4335 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
4336 // CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
4337 // CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
4338 // CHECK9-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
4339 // CHECK9-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
4340 // CHECK9-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
4341 // CHECK9-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
4342 // CHECK9-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
4343 // CHECK9-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
4344 // CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
4345 // CHECK9-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
4346 // CHECK9-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 4
4347 // CHECK9-NEXT:    [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8
4348 // CHECK9-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
4349 // CHECK9-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
4350 // CHECK9-NEXT:    [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8
4351 // CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], ptr [[TMP0]])
4352 // CHECK9-NEXT:    ret void
4353 //
4354 //
4355 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197.omp_outlined
4356 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
4357 // CHECK9-NEXT:  entry:
4358 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
4359 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
4360 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
4361 // CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
4362 // CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
4363 // CHECK9-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
4364 // CHECK9-NEXT:    [[TMP:%.*]] = alloca i64, align 8
4365 // CHECK9-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
4366 // CHECK9-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
4367 // CHECK9-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
4368 // CHECK9-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4369 // CHECK9-NEXT:    [[I:%.*]] = alloca i64, align 8
4370 // CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
4371 // CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
4372 // CHECK9-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
4373 // CHECK9-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
4374 // CHECK9-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
4375 // CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
4376 // CHECK9-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8
4377 // CHECK9-NEXT:    store i64 6, ptr [[DOTOMP_UB]], align 8
4378 // CHECK9-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8
4379 // CHECK9-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
4380 // CHECK9-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
4381 // CHECK9-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
4382 // CHECK9-NEXT:    call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP2]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
4383 // CHECK9-NEXT:    [[TMP3:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
4384 // CHECK9-NEXT:    [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
4385 // CHECK9-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4386 // CHECK9:       cond.true:
4387 // CHECK9-NEXT:    br label [[COND_END:%.*]]
4388 // CHECK9:       cond.false:
4389 // CHECK9-NEXT:    [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
4390 // CHECK9-NEXT:    br label [[COND_END]]
4391 // CHECK9:       cond.end:
4392 // CHECK9-NEXT:    [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
4393 // CHECK9-NEXT:    store i64 [[COND]], ptr [[DOTOMP_UB]], align 8
4394 // CHECK9-NEXT:    [[TMP5:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
4395 // CHECK9-NEXT:    store i64 [[TMP5]], ptr [[DOTOMP_IV]], align 8
4396 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
4397 // CHECK9:       omp.inner.for.cond:
4398 // CHECK9-NEXT:    [[TMP6:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
4399 // CHECK9-NEXT:    [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
4400 // CHECK9-NEXT:    [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
4401 // CHECK9-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4402 // CHECK9:       omp.inner.for.body:
4403 // CHECK9-NEXT:    [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
4404 // CHECK9-NEXT:    [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
4405 // CHECK9-NEXT:    [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
4406 // CHECK9-NEXT:    store i64 [[ADD]], ptr [[I]], align 8
4407 // CHECK9-NEXT:    [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4
4408 // CHECK9-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
4409 // CHECK9-NEXT:    store i32 [[ADD2]], ptr [[A_ADDR]], align 4
4410 // CHECK9-NEXT:    [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2
4411 // CHECK9-NEXT:    [[CONV:%.*]] = sext i16 [[TMP10]] to i32
4412 // CHECK9-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV]], 1
4413 // CHECK9-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
4414 // CHECK9-NEXT:    store i16 [[CONV4]], ptr [[AA_ADDR]], align 2
4415 // CHECK9-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2
4416 // CHECK9-NEXT:    [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
4417 // CHECK9-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1
4418 // CHECK9-NEXT:    store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4
4419 // CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
4420 // CHECK9:       omp.body.continue:
4421 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4422 // CHECK9:       omp.inner.for.inc:
4423 // CHECK9-NEXT:    [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
4424 // CHECK9-NEXT:    [[ADD6:%.*]] = add nsw i64 [[TMP12]], 1
4425 // CHECK9-NEXT:    store i64 [[ADD6]], ptr [[DOTOMP_IV]], align 8
4426 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND]]
4427 // CHECK9:       omp.inner.for.end:
4428 // CHECK9-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
4429 // CHECK9:       omp.loop.exit:
4430 // CHECK9-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])
4431 // CHECK9-NEXT:    ret void
4432 //
4433 //
4434 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
4435 // CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
4436 // CHECK11-NEXT:  entry:
4437 // CHECK11-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
4438 // CHECK11-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
4439 // CHECK11-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined)
4440 // CHECK11-NEXT:    ret void
4441 //
4442 //
4443 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined
4444 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
4445 // CHECK11-NEXT:  entry:
4446 // CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
4447 // CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
4448 // CHECK11-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
4449 // CHECK11-NEXT:    [[TMP:%.*]] = alloca i32, align 4
4450 // CHECK11-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
4451 // CHECK11-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
4452 // CHECK11-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4453 // CHECK11-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4454 // CHECK11-NEXT:    [[I:%.*]] = alloca i32, align 4
4455 // CHECK11-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
4456 // CHECK11-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
4457 // CHECK11-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
4458 // CHECK11-NEXT:    store i32 5, ptr [[DOTOMP_UB]], align 4
4459 // CHECK11-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
4460 // CHECK11-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
4461 // CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
4462 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
4463 // CHECK11-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
4464 // CHECK11-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4465 // CHECK11-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
4466 // CHECK11-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4467 // CHECK11:       cond.true:
4468 // CHECK11-NEXT:    br label [[COND_END:%.*]]
4469 // CHECK11:       cond.false:
4470 // CHECK11-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4471 // CHECK11-NEXT:    br label [[COND_END]]
4472 // CHECK11:       cond.end:
4473 // CHECK11-NEXT:    [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
4474 // CHECK11-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
4475 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
4476 // CHECK11-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
4477 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
4478 // CHECK11:       omp.inner.for.cond:
4479 // CHECK11-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4480 // CHECK11-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4481 // CHECK11-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
4482 // CHECK11-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4483 // CHECK11:       omp.inner.for.body:
4484 // CHECK11-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4485 // CHECK11-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
4486 // CHECK11-NEXT:    [[ADD:%.*]] = add nsw i32 3, [[MUL]]
4487 // CHECK11-NEXT:    store i32 [[ADD]], ptr [[I]], align 4
4488 // CHECK11-NEXT:    [[TMP8:%.*]] = call i32 @__kmpc_cancel(ptr @[[GLOB2]], i32 [[TMP1]], i32 2)
4489 // CHECK11-NEXT:    [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0
4490 // CHECK11-NEXT:    br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
4491 // CHECK11:       .cancel.exit:
4492 // CHECK11-NEXT:    br label [[CANCEL_EXIT:%.*]]
4493 // CHECK11:       .cancel.continue:
4494 // CHECK11-NEXT:    [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(ptr @[[GLOB2]], i32 [[TMP1]], i32 2)
4495 // CHECK11-NEXT:    [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
4496 // CHECK11-NEXT:    br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]]
4497 // CHECK11:       .cancel.exit2:
4498 // CHECK11-NEXT:    br label [[CANCEL_EXIT]]
4499 // CHECK11:       .cancel.continue3:
4500 // CHECK11-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
4501 // CHECK11:       omp.body.continue:
4502 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4503 // CHECK11:       omp.inner.for.inc:
4504 // CHECK11-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4505 // CHECK11-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
4506 // CHECK11-NEXT:    store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4
4507 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND]]
4508 // CHECK11:       omp.inner.for.end:
4509 // CHECK11-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
4510 // CHECK11:       omp.loop.exit:
4511 // CHECK11-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
4512 // CHECK11-NEXT:    br label [[CANCEL_CONT:%.*]]
4513 // CHECK11:       cancel.cont:
4514 // CHECK11-NEXT:    ret void
4515 // CHECK11:       cancel.exit:
4516 // CHECK11-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
4517 // CHECK11-NEXT:    br label [[CANCEL_CONT]]
4518 //
4519 //
4520 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128
4521 // CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] {
4522 // CHECK11-NEXT:  entry:
4523 // CHECK11-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
4524 // CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
4525 // CHECK11-NEXT:    [[LIN_ADDR:%.*]] = alloca i32, align 4
4526 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
4527 // CHECK11-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
4528 // CHECK11-NEXT:    [[LIN_CASTED:%.*]] = alloca i32, align 4
4529 // CHECK11-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
4530 // CHECK11-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
4531 // CHECK11-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
4532 // CHECK11-NEXT:    store i32 [[LIN]], ptr [[LIN_ADDR]], align 4
4533 // CHECK11-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
4534 // CHECK11-NEXT:    [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2
4535 // CHECK11-NEXT:    store i16 [[TMP0]], ptr [[AA_CASTED]], align 2
4536 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[AA_CASTED]], align 4
4537 // CHECK11-NEXT:    [[TMP2:%.*]] = load i32, ptr [[LIN_ADDR]], align 4
4538 // CHECK11-NEXT:    store i32 [[TMP2]], ptr [[LIN_CASTED]], align 4
4539 // CHECK11-NEXT:    [[TMP3:%.*]] = load i32, ptr [[LIN_CASTED]], align 4
4540 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4
4541 // CHECK11-NEXT:    store i32 [[TMP4]], ptr [[A_CASTED]], align 4
4542 // CHECK11-NEXT:    [[TMP5:%.*]] = load i32, ptr [[A_CASTED]], align 4
4543 // CHECK11-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128.omp_outlined, i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]])
4544 // CHECK11-NEXT:    ret void
4545 //
4546 //
4547 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128.omp_outlined
4548 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] {
4549 // CHECK11-NEXT:  entry:
4550 // CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
4551 // CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
4552 // CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
4553 // CHECK11-NEXT:    [[LIN_ADDR:%.*]] = alloca i32, align 4
4554 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
4555 // CHECK11-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
4556 // CHECK11-NEXT:    [[TMP:%.*]] = alloca i64, align 4
4557 // CHECK11-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i32, align 4
4558 // CHECK11-NEXT:    [[DOTLINEAR_START1:%.*]] = alloca i32, align 4
4559 // CHECK11-NEXT:    [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
4560 // CHECK11-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
4561 // CHECK11-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
4562 // CHECK11-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
4563 // CHECK11-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4564 // CHECK11-NEXT:    [[IT:%.*]] = alloca i64, align 8
4565 // CHECK11-NEXT:    [[LIN2:%.*]] = alloca i32, align 4
4566 // CHECK11-NEXT:    [[A3:%.*]] = alloca i32, align 4
4567 // CHECK11-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
4568 // CHECK11-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
4569 // CHECK11-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
4570 // CHECK11-NEXT:    store i32 [[LIN]], ptr [[LIN_ADDR]], align 4
4571 // CHECK11-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
4572 // CHECK11-NEXT:    [[TMP0:%.*]] = load i32, ptr [[LIN_ADDR]], align 4
4573 // CHECK11-NEXT:    store i32 [[TMP0]], ptr [[DOTLINEAR_START]], align 4
4574 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
4575 // CHECK11-NEXT:    store i32 [[TMP1]], ptr [[DOTLINEAR_START1]], align 4
4576 // CHECK11-NEXT:    [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR4:[0-9]+]]
4577 // CHECK11-NEXT:    store i64 [[CALL]], ptr [[DOTLINEAR_STEP]], align 8
4578 // CHECK11-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8
4579 // CHECK11-NEXT:    store i64 3, ptr [[DOTOMP_UB]], align 8
4580 // CHECK11-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8
4581 // CHECK11-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
4582 // CHECK11-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
4583 // CHECK11-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
4584 // CHECK11-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP3]])
4585 // CHECK11-NEXT:    call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
4586 // CHECK11-NEXT:    [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
4587 // CHECK11-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
4588 // CHECK11-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4589 // CHECK11:       cond.true:
4590 // CHECK11-NEXT:    br label [[COND_END:%.*]]
4591 // CHECK11:       cond.false:
4592 // CHECK11-NEXT:    [[TMP5:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
4593 // CHECK11-NEXT:    br label [[COND_END]]
4594 // CHECK11:       cond.end:
4595 // CHECK11-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
4596 // CHECK11-NEXT:    store i64 [[COND]], ptr [[DOTOMP_UB]], align 8
4597 // CHECK11-NEXT:    [[TMP6:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
4598 // CHECK11-NEXT:    store i64 [[TMP6]], ptr [[DOTOMP_IV]], align 8
4599 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
4600 // CHECK11:       omp.inner.for.cond:
4601 // CHECK11-NEXT:    [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
4602 // CHECK11-NEXT:    [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
4603 // CHECK11-NEXT:    [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
4604 // CHECK11-NEXT:    br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4605 // CHECK11:       omp.inner.for.body:
4606 // CHECK11-NEXT:    [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
4607 // CHECK11-NEXT:    [[MUL:%.*]] = mul i64 [[TMP9]], 400
4608 // CHECK11-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
4609 // CHECK11-NEXT:    store i64 [[SUB]], ptr [[IT]], align 8
4610 // CHECK11-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTLINEAR_START]], align 4
4611 // CHECK11-NEXT:    [[CONV:%.*]] = sext i32 [[TMP10]] to i64
4612 // CHECK11-NEXT:    [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
4613 // CHECK11-NEXT:    [[TMP12:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8
4614 // CHECK11-NEXT:    [[MUL5:%.*]] = mul i64 [[TMP11]], [[TMP12]]
4615 // CHECK11-NEXT:    [[ADD:%.*]] = add i64 [[CONV]], [[MUL5]]
4616 // CHECK11-NEXT:    [[CONV6:%.*]] = trunc i64 [[ADD]] to i32
4617 // CHECK11-NEXT:    store i32 [[CONV6]], ptr [[LIN2]], align 4
4618 // CHECK11-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTLINEAR_START1]], align 4
4619 // CHECK11-NEXT:    [[CONV7:%.*]] = sext i32 [[TMP13]] to i64
4620 // CHECK11-NEXT:    [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
4621 // CHECK11-NEXT:    [[TMP15:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8
4622 // CHECK11-NEXT:    [[MUL8:%.*]] = mul i64 [[TMP14]], [[TMP15]]
4623 // CHECK11-NEXT:    [[ADD9:%.*]] = add i64 [[CONV7]], [[MUL8]]
4624 // CHECK11-NEXT:    [[CONV10:%.*]] = trunc i64 [[ADD9]] to i32
4625 // CHECK11-NEXT:    store i32 [[CONV10]], ptr [[A3]], align 4
4626 // CHECK11-NEXT:    [[TMP16:%.*]] = load i16, ptr [[AA_ADDR]], align 2
4627 // CHECK11-NEXT:    [[CONV11:%.*]] = sext i16 [[TMP16]] to i32
4628 // CHECK11-NEXT:    [[ADD12:%.*]] = add nsw i32 [[CONV11]], 1
4629 // CHECK11-NEXT:    [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16
4630 // CHECK11-NEXT:    store i16 [[CONV13]], ptr [[AA_ADDR]], align 2
4631 // CHECK11-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
4632 // CHECK11:       omp.body.continue:
4633 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4634 // CHECK11:       omp.inner.for.inc:
4635 // CHECK11-NEXT:    [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
4636 // CHECK11-NEXT:    [[ADD14:%.*]] = add i64 [[TMP17]], 1
4637 // CHECK11-NEXT:    store i64 [[ADD14]], ptr [[DOTOMP_IV]], align 8
4638 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND]]
4639 // CHECK11:       omp.inner.for.end:
4640 // CHECK11-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
4641 // CHECK11:       omp.loop.exit:
4642 // CHECK11-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]])
4643 // CHECK11-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
4644 // CHECK11-NEXT:    [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
4645 // CHECK11-NEXT:    br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
4646 // CHECK11:       .omp.linear.pu:
4647 // CHECK11-NEXT:    [[TMP20:%.*]] = load i32, ptr [[LIN2]], align 4
4648 // CHECK11-NEXT:    store i32 [[TMP20]], ptr [[LIN_ADDR]], align 4
4649 // CHECK11-NEXT:    [[TMP21:%.*]] = load i32, ptr [[A3]], align 4
4650 // CHECK11-NEXT:    store i32 [[TMP21]], ptr [[A_ADDR]], align 4
4651 // CHECK11-NEXT:    br label [[DOTOMP_LINEAR_PU_DONE]]
4652 // CHECK11:       .omp.linear.pu.done:
4653 // CHECK11-NEXT:    ret void
4654 //
4655 //
4656 // CHECK11-LABEL: define {{[^@]+}}@_Z7get_valv
4657 // CHECK11-SAME: () #[[ATTR2:[0-9]+]] {
4658 // CHECK11-NEXT:  entry:
4659 // CHECK11-NEXT:    ret i64 0
4660 //
4661 //
4662 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136
4663 // CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {
4664 // CHECK11-NEXT:  entry:
4665 // CHECK11-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
4666 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
4667 // CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
4668 // CHECK11-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
4669 // CHECK11-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
4670 // CHECK11-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
4671 // CHECK11-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
4672 // CHECK11-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
4673 // CHECK11-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
4674 // CHECK11-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 4
4675 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4
4676 // CHECK11-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2
4677 // CHECK11-NEXT:    store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
4678 // CHECK11-NEXT:    [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4
4679 // CHECK11-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.omp_outlined, i32 [[TMP1]], i32 [[TMP3]])
4680 // CHECK11-NEXT:    ret void
4681 //
4682 //
4683 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.omp_outlined
4684 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {
4685 // CHECK11-NEXT:  entry:
4686 // CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
4687 // CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
4688 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
4689 // CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
4690 // CHECK11-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
4691 // CHECK11-NEXT:    [[TMP:%.*]] = alloca i16, align 2
4692 // CHECK11-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
4693 // CHECK11-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
4694 // CHECK11-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4695 // CHECK11-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4696 // CHECK11-NEXT:    [[IT:%.*]] = alloca i16, align 2
4697 // CHECK11-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
4698 // CHECK11-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
4699 // CHECK11-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
4700 // CHECK11-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
4701 // CHECK11-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
4702 // CHECK11-NEXT:    store i32 3, ptr [[DOTOMP_UB]], align 4
4703 // CHECK11-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
4704 // CHECK11-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
4705 // CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
4706 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
4707 // CHECK11-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
4708 // CHECK11-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4709 // CHECK11-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
4710 // CHECK11-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4711 // CHECK11:       cond.true:
4712 // CHECK11-NEXT:    br label [[COND_END:%.*]]
4713 // CHECK11:       cond.false:
4714 // CHECK11-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4715 // CHECK11-NEXT:    br label [[COND_END]]
4716 // CHECK11:       cond.end:
4717 // CHECK11-NEXT:    [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
4718 // CHECK11-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
4719 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
4720 // CHECK11-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
4721 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
4722 // CHECK11:       omp.inner.for.cond:
4723 // CHECK11-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4724 // CHECK11-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4725 // CHECK11-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
4726 // CHECK11-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4727 // CHECK11:       omp.inner.for.body:
4728 // CHECK11-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4729 // CHECK11-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
4730 // CHECK11-NEXT:    [[ADD:%.*]] = add nsw i32 6, [[MUL]]
4731 // CHECK11-NEXT:    [[CONV:%.*]] = trunc i32 [[ADD]] to i16
4732 // CHECK11-NEXT:    store i16 [[CONV]], ptr [[IT]], align 2
4733 // CHECK11-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
4734 // CHECK11-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
4735 // CHECK11-NEXT:    store i32 [[ADD2]], ptr [[A_ADDR]], align 4
4736 // CHECK11-NEXT:    [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2
4737 // CHECK11-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP9]] to i32
4738 // CHECK11-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
4739 // CHECK11-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
4740 // CHECK11-NEXT:    store i16 [[CONV5]], ptr [[AA_ADDR]], align 2
4741 // CHECK11-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
4742 // CHECK11:       omp.body.continue:
4743 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4744 // CHECK11:       omp.inner.for.inc:
4745 // CHECK11-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4746 // CHECK11-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1
4747 // CHECK11-NEXT:    store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4
4748 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND]]
4749 // CHECK11:       omp.inner.for.end:
4750 // CHECK11-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
4751 // CHECK11:       omp.loop.exit:
4752 // CHECK11-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
4753 // CHECK11-NEXT:    ret void
4754 //
4755 //
4756 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160
4757 // CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
4758 // CHECK11-NEXT:  entry:
4759 // CHECK11-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
4760 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
4761 // CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
4762 // CHECK11-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
4763 // CHECK11-NEXT:    [[BN_ADDR:%.*]] = alloca ptr, align 4
4764 // CHECK11-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
4765 // CHECK11-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
4766 // CHECK11-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
4767 // CHECK11-NEXT:    [[CN_ADDR:%.*]] = alloca ptr, align 4
4768 // CHECK11-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4
4769 // CHECK11-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
4770 // CHECK11-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
4771 // CHECK11-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
4772 // CHECK11-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
4773 // CHECK11-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
4774 // CHECK11-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
4775 // CHECK11-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
4776 // CHECK11-NEXT:    store ptr [[BN]], ptr [[BN_ADDR]], align 4
4777 // CHECK11-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
4778 // CHECK11-NEXT:    store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
4779 // CHECK11-NEXT:    store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4
4780 // CHECK11-NEXT:    store ptr [[CN]], ptr [[CN_ADDR]], align 4
4781 // CHECK11-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4
4782 // CHECK11-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
4783 // CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
4784 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
4785 // CHECK11-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4
4786 // CHECK11-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
4787 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
4788 // CHECK11-NEXT:    [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4
4789 // CHECK11-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4
4790 // CHECK11-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4
4791 // CHECK11-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
4792 // CHECK11-NEXT:    store i32 [[TMP8]], ptr [[A_CASTED]], align 4
4793 // CHECK11-NEXT:    [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4
4794 // CHECK11-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
4795 // CHECK11-NEXT:    store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
4796 // CHECK11-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
4797 // CHECK11-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined, i32 [[TMP9]], ptr [[TMP0]], i32 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i32 [[TMP11]])
4798 // CHECK11-NEXT:    ret void
4799 //
4800 //
4801 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined
4802 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
4803 // CHECK11-NEXT:  entry:
4804 // CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
4805 // CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
4806 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
4807 // CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
4808 // CHECK11-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
4809 // CHECK11-NEXT:    [[BN_ADDR:%.*]] = alloca ptr, align 4
4810 // CHECK11-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
4811 // CHECK11-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
4812 // CHECK11-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
4813 // CHECK11-NEXT:    [[CN_ADDR:%.*]] = alloca ptr, align 4
4814 // CHECK11-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4
4815 // CHECK11-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
4816 // CHECK11-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
4817 // CHECK11-NEXT:    [[TMP:%.*]] = alloca i8, align 1
4818 // CHECK11-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
4819 // CHECK11-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
4820 // CHECK11-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4821 // CHECK11-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4822 // CHECK11-NEXT:    [[IT:%.*]] = alloca i8, align 1
4823 // CHECK11-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
4824 // CHECK11-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
4825 // CHECK11-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
4826 // CHECK11-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
4827 // CHECK11-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
4828 // CHECK11-NEXT:    store ptr [[BN]], ptr [[BN_ADDR]], align 4
4829 // CHECK11-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
4830 // CHECK11-NEXT:    store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
4831 // CHECK11-NEXT:    store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4
4832 // CHECK11-NEXT:    store ptr [[CN]], ptr [[CN_ADDR]], align 4
4833 // CHECK11-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4
4834 // CHECK11-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
4835 // CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
4836 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
4837 // CHECK11-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4
4838 // CHECK11-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
4839 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
4840 // CHECK11-NEXT:    [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4
4841 // CHECK11-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4
4842 // CHECK11-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4
4843 // CHECK11-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
4844 // CHECK11-NEXT:    store i32 25, ptr [[DOTOMP_UB]], align 4
4845 // CHECK11-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
4846 // CHECK11-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
4847 // CHECK11-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
4848 // CHECK11-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
4849 // CHECK11-NEXT:    [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4
4850 // CHECK11-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP10]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
4851 // CHECK11-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
4852 // CHECK11:       omp.dispatch.cond:
4853 // CHECK11-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4854 // CHECK11-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
4855 // CHECK11-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4856 // CHECK11:       cond.true:
4857 // CHECK11-NEXT:    br label [[COND_END:%.*]]
4858 // CHECK11:       cond.false:
4859 // CHECK11-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4860 // CHECK11-NEXT:    br label [[COND_END]]
4861 // CHECK11:       cond.end:
4862 // CHECK11-NEXT:    [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
4863 // CHECK11-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
4864 // CHECK11-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
4865 // CHECK11-NEXT:    store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4
4866 // CHECK11-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4867 // CHECK11-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4868 // CHECK11-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
4869 // CHECK11-NEXT:    br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
4870 // CHECK11:       omp.dispatch.body:
4871 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
4872 // CHECK11:       omp.inner.for.cond:
4873 // CHECK11-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4874 // CHECK11-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4875 // CHECK11-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
4876 // CHECK11-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4877 // CHECK11:       omp.inner.for.body:
4878 // CHECK11-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4879 // CHECK11-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
4880 // CHECK11-NEXT:    [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
4881 // CHECK11-NEXT:    [[CONV:%.*]] = trunc i32 [[SUB]] to i8
4882 // CHECK11-NEXT:    store i8 [[CONV]], ptr [[IT]], align 1
4883 // CHECK11-NEXT:    [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4
4884 // CHECK11-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
4885 // CHECK11-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 4
4886 // CHECK11-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 2
4887 // CHECK11-NEXT:    [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4
4888 // CHECK11-NEXT:    [[CONV7:%.*]] = fpext float [[TMP20]] to double
4889 // CHECK11-NEXT:    [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00
4890 // CHECK11-NEXT:    [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
4891 // CHECK11-NEXT:    store float [[CONV9]], ptr [[ARRAYIDX]], align 4
4892 // CHECK11-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i32 3
4893 // CHECK11-NEXT:    [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4
4894 // CHECK11-NEXT:    [[CONV11:%.*]] = fpext float [[TMP21]] to double
4895 // CHECK11-NEXT:    [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
4896 // CHECK11-NEXT:    [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
4897 // CHECK11-NEXT:    store float [[CONV13]], ptr [[ARRAYIDX10]], align 4
4898 // CHECK11-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 1
4899 // CHECK11-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i32 0, i32 2
4900 // CHECK11-NEXT:    [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8
4901 // CHECK11-NEXT:    [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
4902 // CHECK11-NEXT:    store double [[ADD16]], ptr [[ARRAYIDX15]], align 8
4903 // CHECK11-NEXT:    [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]
4904 // CHECK11-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i32 [[TMP23]]
4905 // CHECK11-NEXT:    [[ARRAYIDX18:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX17]], i32 3
4906 // CHECK11-NEXT:    [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 8
4907 // CHECK11-NEXT:    [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
4908 // CHECK11-NEXT:    store double [[ADD19]], ptr [[ARRAYIDX18]], align 8
4909 // CHECK11-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0
4910 // CHECK11-NEXT:    [[TMP25:%.*]] = load i64, ptr [[X]], align 4
4911 // CHECK11-NEXT:    [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
4912 // CHECK11-NEXT:    store i64 [[ADD20]], ptr [[X]], align 4
4913 // CHECK11-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1
4914 // CHECK11-NEXT:    [[TMP26:%.*]] = load i8, ptr [[Y]], align 4
4915 // CHECK11-NEXT:    [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
4916 // CHECK11-NEXT:    [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
4917 // CHECK11-NEXT:    [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
4918 // CHECK11-NEXT:    store i8 [[CONV23]], ptr [[Y]], align 4
4919 // CHECK11-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
4920 // CHECK11:       omp.body.continue:
4921 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4922 // CHECK11:       omp.inner.for.inc:
4923 // CHECK11-NEXT:    [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4924 // CHECK11-NEXT:    [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
4925 // CHECK11-NEXT:    store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4
4926 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND]]
4927 // CHECK11:       omp.inner.for.end:
4928 // CHECK11-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
4929 // CHECK11:       omp.dispatch.inc:
4930 // CHECK11-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
4931 // CHECK11-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
4932 // CHECK11-NEXT:    [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
4933 // CHECK11-NEXT:    store i32 [[ADD25]], ptr [[DOTOMP_LB]], align 4
4934 // CHECK11-NEXT:    [[TMP30:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4935 // CHECK11-NEXT:    [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
4936 // CHECK11-NEXT:    [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
4937 // CHECK11-NEXT:    store i32 [[ADD26]], ptr [[DOTOMP_UB]], align 4
4938 // CHECK11-NEXT:    br label [[OMP_DISPATCH_COND]]
4939 // CHECK11:       omp.dispatch.end:
4940 // CHECK11-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP10]])
4941 // CHECK11-NEXT:    ret void
4942 //
4943 //
4944 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214
4945 // CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
4946 // CHECK11-NEXT:  entry:
4947 // CHECK11-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
4948 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
4949 // CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
4950 // CHECK11-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
4951 // CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
4952 // CHECK11-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
4953 // CHECK11-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
4954 // CHECK11-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
4955 // CHECK11-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
4956 // CHECK11-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
4957 // CHECK11-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
4958 // CHECK11-NEXT:    store i32 [[AAA]], ptr [[AAA_ADDR]], align 4
4959 // CHECK11-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
4960 // CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
4961 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
4962 // CHECK11-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 4
4963 // CHECK11-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4
4964 // CHECK11-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
4965 // CHECK11-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
4966 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4
4967 // CHECK11-NEXT:    [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 1
4968 // CHECK11-NEXT:    store i8 [[TMP5]], ptr [[AAA_CASTED]], align 1
4969 // CHECK11-NEXT:    [[TMP6:%.*]] = load i32, ptr [[AAA_CASTED]], align 4
4970 // CHECK11-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], ptr [[TMP0]])
4971 // CHECK11-NEXT:    ret void
4972 //
4973 //
4974 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214.omp_outlined
4975 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
4976 // CHECK11-NEXT:  entry:
4977 // CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
4978 // CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
4979 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
4980 // CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
4981 // CHECK11-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
4982 // CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
4983 // CHECK11-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
4984 // CHECK11-NEXT:    [[TMP:%.*]] = alloca i32, align 4
4985 // CHECK11-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
4986 // CHECK11-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
4987 // CHECK11-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
4988 // CHECK11-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
4989 // CHECK11-NEXT:    store i32 [[AAA]], ptr [[AAA_ADDR]], align 4
4990 // CHECK11-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
4991 // CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
4992 // CHECK11-NEXT:    ret void
4993 //
4994 //
4995 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232
4996 // CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
4997 // CHECK11-NEXT:  entry:
4998 // CHECK11-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
4999 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
5000 // CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
5001 // CHECK11-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
5002 // CHECK11-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
5003 // CHECK11-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
5004 // CHECK11-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
5005 // CHECK11-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
5006 // CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
5007 // CHECK11-NEXT:    store i32 [[B]], ptr [[B_ADDR]], align 4
5008 // CHECK11-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
5009 // CHECK11-NEXT:    store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
5010 // CHECK11-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
5011 // CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
5012 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
5013 // CHECK11-NEXT:    [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
5014 // CHECK11-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
5015 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4
5016 // CHECK11-NEXT:    store i32 [[TMP4]], ptr [[B_CASTED]], align 4
5017 // CHECK11-NEXT:    [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4
5018 // CHECK11-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232.omp_outlined, ptr [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], ptr [[TMP3]])
5019 // CHECK11-NEXT:    ret void
5020 //
5021 //
5022 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232.omp_outlined
5023 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
5024 // CHECK11-NEXT:  entry:
5025 // CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
5026 // CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
5027 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
5028 // CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
5029 // CHECK11-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
5030 // CHECK11-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
5031 // CHECK11-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
5032 // CHECK11-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
5033 // CHECK11-NEXT:    [[TMP:%.*]] = alloca i64, align 4
5034 // CHECK11-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
5035 // CHECK11-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
5036 // CHECK11-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
5037 // CHECK11-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
5038 // CHECK11-NEXT:    [[IT:%.*]] = alloca i64, align 8
5039 // CHECK11-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
5040 // CHECK11-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
5041 // CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
5042 // CHECK11-NEXT:    store i32 [[B]], ptr [[B_ADDR]], align 4
5043 // CHECK11-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
5044 // CHECK11-NEXT:    store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
5045 // CHECK11-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
5046 // CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
5047 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
5048 // CHECK11-NEXT:    [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
5049 // CHECK11-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
5050 // CHECK11-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8
5051 // CHECK11-NEXT:    store i64 3, ptr [[DOTOMP_UB]], align 8
5052 // CHECK11-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8
5053 // CHECK11-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
5054 // CHECK11-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
5055 // CHECK11-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
5056 // CHECK11-NEXT:    call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP5]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
5057 // CHECK11-NEXT:    [[TMP6:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
5058 // CHECK11-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3
5059 // CHECK11-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
5060 // CHECK11:       cond.true:
5061 // CHECK11-NEXT:    br label [[COND_END:%.*]]
5062 // CHECK11:       cond.false:
5063 // CHECK11-NEXT:    [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
5064 // CHECK11-NEXT:    br label [[COND_END]]
5065 // CHECK11:       cond.end:
5066 // CHECK11-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
5067 // CHECK11-NEXT:    store i64 [[COND]], ptr [[DOTOMP_UB]], align 8
5068 // CHECK11-NEXT:    [[TMP8:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
5069 // CHECK11-NEXT:    store i64 [[TMP8]], ptr [[DOTOMP_IV]], align 8
5070 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
5071 // CHECK11:       omp.inner.for.cond:
5072 // CHECK11-NEXT:    [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
5073 // CHECK11-NEXT:    [[TMP10:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
5074 // CHECK11-NEXT:    [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
5075 // CHECK11-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5076 // CHECK11:       omp.inner.for.body:
5077 // CHECK11-NEXT:    [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
5078 // CHECK11-NEXT:    [[MUL:%.*]] = mul i64 [[TMP11]], 400
5079 // CHECK11-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
5080 // CHECK11-NEXT:    store i64 [[SUB]], ptr [[IT]], align 8
5081 // CHECK11-NEXT:    [[TMP12:%.*]] = load i32, ptr [[B_ADDR]], align 4
5082 // CHECK11-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP12]] to double
5083 // CHECK11-NEXT:    [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
5084 // CHECK11-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0
5085 // CHECK11-NEXT:    store double [[ADD]], ptr [[A]], align 4
5086 // CHECK11-NEXT:    [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0
5087 // CHECK11-NEXT:    [[TMP13:%.*]] = load double, ptr [[A4]], align 4
5088 // CHECK11-NEXT:    [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
5089 // CHECK11-NEXT:    store double [[INC]], ptr [[A4]], align 4
5090 // CHECK11-NEXT:    [[CONV5:%.*]] = fptosi double [[INC]] to i16
5091 // CHECK11-NEXT:    [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]]
5092 // CHECK11-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i32 [[TMP14]]
5093 // CHECK11-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1
5094 // CHECK11-NEXT:    store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2
5095 // CHECK11-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
5096 // CHECK11:       omp.body.continue:
5097 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
5098 // CHECK11:       omp.inner.for.inc:
5099 // CHECK11-NEXT:    [[TMP15:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
5100 // CHECK11-NEXT:    [[ADD7:%.*]] = add i64 [[TMP15]], 1
5101 // CHECK11-NEXT:    store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8
5102 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND]]
5103 // CHECK11:       omp.inner.for.end:
5104 // CHECK11-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
5105 // CHECK11:       omp.loop.exit:
5106 // CHECK11-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])
5107 // CHECK11-NEXT:    ret void
5108 //
5109 //
5110 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197
5111 // CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
5112 // CHECK11-NEXT:  entry:
5113 // CHECK11-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
5114 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
5115 // CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
5116 // CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
5117 // CHECK11-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
5118 // CHECK11-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
5119 // CHECK11-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
5120 // CHECK11-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
5121 // CHECK11-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
5122 // CHECK11-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
5123 // CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
5124 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
5125 // CHECK11-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 4
5126 // CHECK11-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4
5127 // CHECK11-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
5128 // CHECK11-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
5129 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4
5130 // CHECK11-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], ptr [[TMP0]])
5131 // CHECK11-NEXT:    ret void
5132 //
5133 //
5134 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197.omp_outlined
5135 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
5136 // CHECK11-NEXT:  entry:
5137 // CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
5138 // CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
5139 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
5140 // CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
5141 // CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
5142 // CHECK11-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
5143 // CHECK11-NEXT:    [[TMP:%.*]] = alloca i64, align 4
5144 // CHECK11-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
5145 // CHECK11-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
5146 // CHECK11-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
5147 // CHECK11-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
5148 // CHECK11-NEXT:    [[I:%.*]] = alloca i64, align 8
5149 // CHECK11-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
5150 // CHECK11-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
5151 // CHECK11-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
5152 // CHECK11-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
5153 // CHECK11-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
5154 // CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
5155 // CHECK11-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8
5156 // CHECK11-NEXT:    store i64 6, ptr [[DOTOMP_UB]], align 8
5157 // CHECK11-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8
5158 // CHECK11-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
5159 // CHECK11-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
5160 // CHECK11-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
5161 // CHECK11-NEXT:    call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP2]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
5162 // CHECK11-NEXT:    [[TMP3:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
5163 // CHECK11-NEXT:    [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
5164 // CHECK11-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
5165 // CHECK11:       cond.true:
5166 // CHECK11-NEXT:    br label [[COND_END:%.*]]
5167 // CHECK11:       cond.false:
5168 // CHECK11-NEXT:    [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
5169 // CHECK11-NEXT:    br label [[COND_END]]
5170 // CHECK11:       cond.end:
5171 // CHECK11-NEXT:    [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
5172 // CHECK11-NEXT:    store i64 [[COND]], ptr [[DOTOMP_UB]], align 8
5173 // CHECK11-NEXT:    [[TMP5:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
5174 // CHECK11-NEXT:    store i64 [[TMP5]], ptr [[DOTOMP_IV]], align 8
5175 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
5176 // CHECK11:       omp.inner.for.cond:
5177 // CHECK11-NEXT:    [[TMP6:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
5178 // CHECK11-NEXT:    [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
5179 // CHECK11-NEXT:    [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
5180 // CHECK11-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5181 // CHECK11:       omp.inner.for.body:
5182 // CHECK11-NEXT:    [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
5183 // CHECK11-NEXT:    [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
5184 // CHECK11-NEXT:    [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
5185 // CHECK11-NEXT:    store i64 [[ADD]], ptr [[I]], align 8
5186 // CHECK11-NEXT:    [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4
5187 // CHECK11-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
5188 // CHECK11-NEXT:    store i32 [[ADD2]], ptr [[A_ADDR]], align 4
5189 // CHECK11-NEXT:    [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2
5190 // CHECK11-NEXT:    [[CONV:%.*]] = sext i16 [[TMP10]] to i32
5191 // CHECK11-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV]], 1
5192 // CHECK11-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
5193 // CHECK11-NEXT:    store i16 [[CONV4]], ptr [[AA_ADDR]], align 2
5194 // CHECK11-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2
5195 // CHECK11-NEXT:    [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
5196 // CHECK11-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1
5197 // CHECK11-NEXT:    store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4
5198 // CHECK11-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
5199 // CHECK11:       omp.body.continue:
5200 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
5201 // CHECK11:       omp.inner.for.inc:
5202 // CHECK11-NEXT:    [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
5203 // CHECK11-NEXT:    [[ADD6:%.*]] = add nsw i64 [[TMP12]], 1
5204 // CHECK11-NEXT:    store i64 [[ADD6]], ptr [[DOTOMP_IV]], align 8
5205 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND]]
5206 // CHECK11:       omp.inner.for.end:
5207 // CHECK11-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
5208 // CHECK11:       omp.loop.exit:
5209 // CHECK11-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])
5210 // CHECK11-NEXT:    ret void
5211 //
5212 //
5213 // CHECK17-LABEL: define {{[^@]+}}@_Z7get_valv
5214 // CHECK17-SAME: () #[[ATTR0:[0-9]+]] {
5215 // CHECK17-NEXT:  entry:
5216 // CHECK17-NEXT:    ret i64 0
5217 //
5218 //
5219 // CHECK17-LABEL: define {{[^@]+}}@_Z3fooi
5220 // CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
5221 // CHECK17-NEXT:  entry:
5222 // CHECK17-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
5223 // CHECK17-NEXT:    [[A:%.*]] = alloca i32, align 4
5224 // CHECK17-NEXT:    [[AA:%.*]] = alloca i16, align 2
5225 // CHECK17-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
5226 // CHECK17-NEXT:    [[SAVED_STACK:%.*]] = alloca ptr, align 8
5227 // CHECK17-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
5228 // CHECK17-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
5229 // CHECK17-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
5230 // CHECK17-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
5231 // CHECK17-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
5232 // CHECK17-NEXT:    [[K:%.*]] = alloca i64, align 8
5233 // CHECK17-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
5234 // CHECK17-NEXT:    [[K_CASTED:%.*]] = alloca i64, align 8
5235 // CHECK17-NEXT:    [[LIN:%.*]] = alloca i32, align 4
5236 // CHECK17-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
5237 // CHECK17-NEXT:    [[LIN_CASTED:%.*]] = alloca i64, align 8
5238 // CHECK17-NEXT:    [[A_CASTED2:%.*]] = alloca i64, align 8
5239 // CHECK17-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8
5240 // CHECK17-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 8
5241 // CHECK17-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 8
5242 // CHECK17-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4
5243 // CHECK17-NEXT:    [[A_CASTED3:%.*]] = alloca i64, align 8
5244 // CHECK17-NEXT:    [[AA_CASTED4:%.*]] = alloca i64, align 8
5245 // CHECK17-NEXT:    [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [2 x ptr], align 8
5246 // CHECK17-NEXT:    [[DOTOFFLOAD_PTRS6:%.*]] = alloca [2 x ptr], align 8
5247 // CHECK17-NEXT:    [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [2 x ptr], align 8
5248 // CHECK17-NEXT:    [[KERNEL_ARGS8:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
5249 // CHECK17-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
5250 // CHECK17-NEXT:    [[A_CASTED11:%.*]] = alloca i64, align 8
5251 // CHECK17-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
5252 // CHECK17-NEXT:    [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [10 x ptr], align 8
5253 // CHECK17-NEXT:    [[DOTOFFLOAD_PTRS15:%.*]] = alloca [10 x ptr], align 8
5254 // CHECK17-NEXT:    [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [10 x ptr], align 8
5255 // CHECK17-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8
5256 // CHECK17-NEXT:    [[KERNEL_ARGS17:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
5257 // CHECK17-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])
5258 // CHECK17-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
5259 // CHECK17-NEXT:    store i32 0, ptr [[A]], align 4
5260 // CHECK17-NEXT:    store i16 0, ptr [[AA]], align 2
5261 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
5262 // CHECK17-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
5263 // CHECK17-NEXT:    [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()
5264 // CHECK17-NEXT:    store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8
5265 // CHECK17-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4
5266 // CHECK17-NEXT:    store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8
5267 // CHECK17-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
5268 // CHECK17-NEXT:    [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
5269 // CHECK17-NEXT:    [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]]
5270 // CHECK17-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8
5271 // CHECK17-NEXT:    store i64 [[TMP5]], ptr [[__VLA_EXPR1]], align 8
5272 // CHECK17-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
5273 // CHECK17-NEXT:    store i32 2, ptr [[TMP7]], align 4
5274 // CHECK17-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
5275 // CHECK17-NEXT:    store i32 0, ptr [[TMP8]], align 4
5276 // CHECK17-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
5277 // CHECK17-NEXT:    store ptr null, ptr [[TMP9]], align 8
5278 // CHECK17-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
5279 // CHECK17-NEXT:    store ptr null, ptr [[TMP10]], align 8
5280 // CHECK17-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
5281 // CHECK17-NEXT:    store ptr null, ptr [[TMP11]], align 8
5282 // CHECK17-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
5283 // CHECK17-NEXT:    store ptr null, ptr [[TMP12]], align 8
5284 // CHECK17-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
5285 // CHECK17-NEXT:    store ptr null, ptr [[TMP13]], align 8
5286 // CHECK17-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
5287 // CHECK17-NEXT:    store ptr null, ptr [[TMP14]], align 8
5288 // CHECK17-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
5289 // CHECK17-NEXT:    store i64 0, ptr [[TMP15]], align 8
5290 // CHECK17-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
5291 // CHECK17-NEXT:    store i64 0, ptr [[TMP16]], align 8
5292 // CHECK17-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
5293 // CHECK17-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP17]], align 4
5294 // CHECK17-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
5295 // CHECK17-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP18]], align 4
5296 // CHECK17-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
5297 // CHECK17-NEXT:    store i32 0, ptr [[TMP19]], align 4
5298 // CHECK17-NEXT:    [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, ptr [[KERNEL_ARGS]])
5299 // CHECK17-NEXT:    [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
5300 // CHECK17-NEXT:    br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
5301 // CHECK17:       omp_offload.failed:
5302 // CHECK17-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR3:[0-9]+]]
5303 // CHECK17-NEXT:    br label [[OMP_OFFLOAD_CONT]]
5304 // CHECK17:       omp_offload.cont:
5305 // CHECK17-NEXT:    [[CALL:%.*]] = call noundef i64 @_Z7get_valv()
5306 // CHECK17-NEXT:    store i64 [[CALL]], ptr [[K]], align 8
5307 // CHECK17-NEXT:    [[TMP22:%.*]] = load i32, ptr [[A]], align 4
5308 // CHECK17-NEXT:    store i32 [[TMP22]], ptr [[A_CASTED]], align 4
5309 // CHECK17-NEXT:    [[TMP23:%.*]] = load i64, ptr [[A_CASTED]], align 8
5310 // CHECK17-NEXT:    [[TMP24:%.*]] = load i64, ptr [[K]], align 8
5311 // CHECK17-NEXT:    store i64 [[TMP24]], ptr [[K_CASTED]], align 8
5312 // CHECK17-NEXT:    [[TMP25:%.*]] = load i64, ptr [[K_CASTED]], align 8
5313 // CHECK17-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i64 [[TMP23]], i64 [[TMP25]]) #[[ATTR3]]
5314 // CHECK17-NEXT:    store i32 12, ptr [[LIN]], align 4
5315 // CHECK17-NEXT:    [[TMP26:%.*]] = load i16, ptr [[AA]], align 2
5316 // CHECK17-NEXT:    store i16 [[TMP26]], ptr [[AA_CASTED]], align 2
5317 // CHECK17-NEXT:    [[TMP27:%.*]] = load i64, ptr [[AA_CASTED]], align 8
5318 // CHECK17-NEXT:    [[TMP28:%.*]] = load i32, ptr [[LIN]], align 4
5319 // CHECK17-NEXT:    store i32 [[TMP28]], ptr [[LIN_CASTED]], align 4
5320 // CHECK17-NEXT:    [[TMP29:%.*]] = load i64, ptr [[LIN_CASTED]], align 8
5321 // CHECK17-NEXT:    [[TMP30:%.*]] = load i32, ptr [[A]], align 4
5322 // CHECK17-NEXT:    store i32 [[TMP30]], ptr [[A_CASTED2]], align 4
5323 // CHECK17-NEXT:    [[TMP31:%.*]] = load i64, ptr [[A_CASTED2]], align 8
5324 // CHECK17-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
5325 // CHECK17-NEXT:    store i64 [[TMP27]], ptr [[TMP32]], align 8
5326 // CHECK17-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
5327 // CHECK17-NEXT:    store i64 [[TMP27]], ptr [[TMP33]], align 8
5328 // CHECK17-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
5329 // CHECK17-NEXT:    store ptr null, ptr [[TMP34]], align 8
5330 // CHECK17-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
5331 // CHECK17-NEXT:    store i64 [[TMP29]], ptr [[TMP35]], align 8
5332 // CHECK17-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
5333 // CHECK17-NEXT:    store i64 [[TMP29]], ptr [[TMP36]], align 8
5334 // CHECK17-NEXT:    [[TMP37:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
5335 // CHECK17-NEXT:    store ptr null, ptr [[TMP37]], align 8
5336 // CHECK17-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
5337 // CHECK17-NEXT:    store i64 [[TMP31]], ptr [[TMP38]], align 8
5338 // CHECK17-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
5339 // CHECK17-NEXT:    store i64 [[TMP31]], ptr [[TMP39]], align 8
5340 // CHECK17-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
5341 // CHECK17-NEXT:    store ptr null, ptr [[TMP40]], align 8
5342 // CHECK17-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
5343 // CHECK17-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
5344 // CHECK17-NEXT:    [[TMP43:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0
5345 // CHECK17-NEXT:    [[TMP44:%.*]] = load i16, ptr [[AA]], align 2
5346 // CHECK17-NEXT:    store i16 [[TMP44]], ptr [[TMP43]], align 4
5347 // CHECK17-NEXT:    [[TMP45:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 1
5348 // CHECK17-NEXT:    [[TMP46:%.*]] = load i32, ptr [[LIN]], align 4
5349 // CHECK17-NEXT:    store i32 [[TMP46]], ptr [[TMP45]], align 4
5350 // CHECK17-NEXT:    [[TMP47:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 2
5351 // CHECK17-NEXT:    [[TMP48:%.*]] = load i32, ptr [[A]], align 4
5352 // CHECK17-NEXT:    store i32 [[TMP48]], ptr [[TMP47]], align 4
5353 // CHECK17-NEXT:    [[TMP49:%.*]] = call ptr @__kmpc_omp_target_task_alloc(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i64 120, i64 12, ptr @.omp_task_entry., i64 -1)
5354 // CHECK17-NEXT:    [[TMP50:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP49]], i32 0, i32 0
5355 // CHECK17-NEXT:    [[TMP51:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP50]], i32 0, i32 0
5356 // CHECK17-NEXT:    [[TMP52:%.*]] = load ptr, ptr [[TMP51]], align 8
5357 // CHECK17-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP52]], ptr align 4 [[AGG_CAPTURED]], i64 12, i1 false)
5358 // CHECK17-NEXT:    [[TMP53:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP49]], i32 0, i32 1
5359 // CHECK17-NEXT:    [[TMP54:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP53]], i32 0, i32 0
5360 // CHECK17-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP54]], ptr align 8 [[TMP41]], i64 24, i1 false)
5361 // CHECK17-NEXT:    [[TMP55:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP53]], i32 0, i32 1
5362 // CHECK17-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP55]], ptr align 8 [[TMP42]], i64 24, i1 false)
5363 // CHECK17-NEXT:    [[TMP56:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP53]], i32 0, i32 2
5364 // CHECK17-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP56]], ptr align 8 @.offload_sizes, i64 24, i1 false)
5365 // CHECK17-NEXT:    [[TMP57:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP53]], i32 0, i32 3
5366 // CHECK17-NEXT:    [[TMP58:%.*]] = load i16, ptr [[AA]], align 2
5367 // CHECK17-NEXT:    store i16 [[TMP58]], ptr [[TMP57]], align 8
5368 // CHECK17-NEXT:    [[TMP59:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB2]], i32 [[TMP0]], ptr [[TMP49]])
5369 // CHECK17-NEXT:    [[TMP60:%.*]] = load i32, ptr [[A]], align 4
5370 // CHECK17-NEXT:    store i32 [[TMP60]], ptr [[A_CASTED3]], align 4
5371 // CHECK17-NEXT:    [[TMP61:%.*]] = load i64, ptr [[A_CASTED3]], align 8
5372 // CHECK17-NEXT:    [[TMP62:%.*]] = load i16, ptr [[AA]], align 2
5373 // CHECK17-NEXT:    store i16 [[TMP62]], ptr [[AA_CASTED4]], align 2
5374 // CHECK17-NEXT:    [[TMP63:%.*]] = load i64, ptr [[AA_CASTED4]], align 8
5375 // CHECK17-NEXT:    [[TMP64:%.*]] = load i32, ptr [[N_ADDR]], align 4
5376 // CHECK17-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP64]], 10
5377 // CHECK17-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
5378 // CHECK17:       omp_if.then:
5379 // CHECK17-NEXT:    [[TMP65:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0
5380 // CHECK17-NEXT:    store i64 [[TMP61]], ptr [[TMP65]], align 8
5381 // CHECK17-NEXT:    [[TMP66:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0
5382 // CHECK17-NEXT:    store i64 [[TMP61]], ptr [[TMP66]], align 8
5383 // CHECK17-NEXT:    [[TMP67:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 0
5384 // CHECK17-NEXT:    store ptr null, ptr [[TMP67]], align 8
5385 // CHECK17-NEXT:    [[TMP68:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1
5386 // CHECK17-NEXT:    store i64 [[TMP63]], ptr [[TMP68]], align 8
5387 // CHECK17-NEXT:    [[TMP69:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 1
5388 // CHECK17-NEXT:    store i64 [[TMP63]], ptr [[TMP69]], align 8
5389 // CHECK17-NEXT:    [[TMP70:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 1
5390 // CHECK17-NEXT:    store ptr null, ptr [[TMP70]], align 8
5391 // CHECK17-NEXT:    [[TMP71:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0
5392 // CHECK17-NEXT:    [[TMP72:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0
5393 // CHECK17-NEXT:    [[TMP73:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 0
5394 // CHECK17-NEXT:    store i32 2, ptr [[TMP73]], align 4
5395 // CHECK17-NEXT:    [[TMP74:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 1
5396 // CHECK17-NEXT:    store i32 2, ptr [[TMP74]], align 4
5397 // CHECK17-NEXT:    [[TMP75:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 2
5398 // CHECK17-NEXT:    store ptr [[TMP71]], ptr [[TMP75]], align 8
5399 // CHECK17-NEXT:    [[TMP76:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 3
5400 // CHECK17-NEXT:    store ptr [[TMP72]], ptr [[TMP76]], align 8
5401 // CHECK17-NEXT:    [[TMP77:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 4
5402 // CHECK17-NEXT:    store ptr @.offload_sizes.1, ptr [[TMP77]], align 8
5403 // CHECK17-NEXT:    [[TMP78:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 5
5404 // CHECK17-NEXT:    store ptr @.offload_maptypes.2, ptr [[TMP78]], align 8
5405 // CHECK17-NEXT:    [[TMP79:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 6
5406 // CHECK17-NEXT:    store ptr null, ptr [[TMP79]], align 8
5407 // CHECK17-NEXT:    [[TMP80:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 7
5408 // CHECK17-NEXT:    store ptr null, ptr [[TMP80]], align 8
5409 // CHECK17-NEXT:    [[TMP81:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 8
5410 // CHECK17-NEXT:    store i64 0, ptr [[TMP81]], align 8
5411 // CHECK17-NEXT:    [[TMP82:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 9
5412 // CHECK17-NEXT:    store i64 0, ptr [[TMP82]], align 8
5413 // CHECK17-NEXT:    [[TMP83:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 10
5414 // CHECK17-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP83]], align 4
5415 // CHECK17-NEXT:    [[TMP84:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 11
5416 // CHECK17-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP84]], align 4
5417 // CHECK17-NEXT:    [[TMP85:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 12
5418 // CHECK17-NEXT:    store i32 0, ptr [[TMP85]], align 4
5419 // CHECK17-NEXT:    [[TMP86:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.region_id, ptr [[KERNEL_ARGS8]])
5420 // CHECK17-NEXT:    [[TMP87:%.*]] = icmp ne i32 [[TMP86]], 0
5421 // CHECK17-NEXT:    br i1 [[TMP87]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]]
5422 // CHECK17:       omp_offload.failed9:
5423 // CHECK17-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136(i64 [[TMP61]], i64 [[TMP63]]) #[[ATTR3]]
5424 // CHECK17-NEXT:    br label [[OMP_OFFLOAD_CONT10]]
5425 // CHECK17:       omp_offload.cont10:
5426 // CHECK17-NEXT:    br label [[OMP_IF_END:%.*]]
5427 // CHECK17:       omp_if.else:
5428 // CHECK17-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136(i64 [[TMP61]], i64 [[TMP63]]) #[[ATTR3]]
5429 // CHECK17-NEXT:    br label [[OMP_IF_END]]
5430 // CHECK17:       omp_if.end:
5431 // CHECK17-NEXT:    [[TMP88:%.*]] = load i32, ptr [[A]], align 4
5432 // CHECK17-NEXT:    store i32 [[TMP88]], ptr [[DOTCAPTURE_EXPR_]], align 4
5433 // CHECK17-NEXT:    [[TMP89:%.*]] = load i32, ptr [[A]], align 4
5434 // CHECK17-NEXT:    store i32 [[TMP89]], ptr [[A_CASTED11]], align 4
5435 // CHECK17-NEXT:    [[TMP90:%.*]] = load i64, ptr [[A_CASTED11]], align 8
5436 // CHECK17-NEXT:    [[TMP91:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
5437 // CHECK17-NEXT:    store i32 [[TMP91]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
5438 // CHECK17-NEXT:    [[TMP92:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8
5439 // CHECK17-NEXT:    [[TMP93:%.*]] = load i32, ptr [[N_ADDR]], align 4
5440 // CHECK17-NEXT:    [[CMP12:%.*]] = icmp sgt i32 [[TMP93]], 20
5441 // CHECK17-NEXT:    br i1 [[CMP12]], label [[OMP_IF_THEN13:%.*]], label [[OMP_IF_ELSE20:%.*]]
5442 // CHECK17:       omp_if.then13:
5443 // CHECK17-NEXT:    [[TMP94:%.*]] = mul nuw i64 [[TMP2]], 4
5444 // CHECK17-NEXT:    [[TMP95:%.*]] = mul nuw i64 5, [[TMP5]]
5445 // CHECK17-NEXT:    [[TMP96:%.*]] = mul nuw i64 [[TMP95]], 8
5446 // CHECK17-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes.3, i64 80, i1 false)
5447 // CHECK17-NEXT:    [[TMP97:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0
5448 // CHECK17-NEXT:    store i64 [[TMP90]], ptr [[TMP97]], align 8
5449 // CHECK17-NEXT:    [[TMP98:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 0
5450 // CHECK17-NEXT:    store i64 [[TMP90]], ptr [[TMP98]], align 8
5451 // CHECK17-NEXT:    [[TMP99:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 0
5452 // CHECK17-NEXT:    store ptr null, ptr [[TMP99]], align 8
5453 // CHECK17-NEXT:    [[TMP100:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 1
5454 // CHECK17-NEXT:    store ptr [[B]], ptr [[TMP100]], align 8
5455 // CHECK17-NEXT:    [[TMP101:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 1
5456 // CHECK17-NEXT:    store ptr [[B]], ptr [[TMP101]], align 8
5457 // CHECK17-NEXT:    [[TMP102:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 1
5458 // CHECK17-NEXT:    store ptr null, ptr [[TMP102]], align 8
5459 // CHECK17-NEXT:    [[TMP103:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 2
5460 // CHECK17-NEXT:    store i64 [[TMP2]], ptr [[TMP103]], align 8
5461 // CHECK17-NEXT:    [[TMP104:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 2
5462 // CHECK17-NEXT:    store i64 [[TMP2]], ptr [[TMP104]], align 8
5463 // CHECK17-NEXT:    [[TMP105:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 2
5464 // CHECK17-NEXT:    store ptr null, ptr [[TMP105]], align 8
5465 // CHECK17-NEXT:    [[TMP106:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 3
5466 // CHECK17-NEXT:    store ptr [[VLA]], ptr [[TMP106]], align 8
5467 // CHECK17-NEXT:    [[TMP107:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 3
5468 // CHECK17-NEXT:    store ptr [[VLA]], ptr [[TMP107]], align 8
5469 // CHECK17-NEXT:    [[TMP108:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 3
5470 // CHECK17-NEXT:    store i64 [[TMP94]], ptr [[TMP108]], align 8
5471 // CHECK17-NEXT:    [[TMP109:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 3
5472 // CHECK17-NEXT:    store ptr null, ptr [[TMP109]], align 8
5473 // CHECK17-NEXT:    [[TMP110:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 4
5474 // CHECK17-NEXT:    store ptr [[C]], ptr [[TMP110]], align 8
5475 // CHECK17-NEXT:    [[TMP111:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 4
5476 // CHECK17-NEXT:    store ptr [[C]], ptr [[TMP111]], align 8
5477 // CHECK17-NEXT:    [[TMP112:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 4
5478 // CHECK17-NEXT:    store ptr null, ptr [[TMP112]], align 8
5479 // CHECK17-NEXT:    [[TMP113:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 5
5480 // CHECK17-NEXT:    store i64 5, ptr [[TMP113]], align 8
5481 // CHECK17-NEXT:    [[TMP114:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 5
5482 // CHECK17-NEXT:    store i64 5, ptr [[TMP114]], align 8
5483 // CHECK17-NEXT:    [[TMP115:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 5
5484 // CHECK17-NEXT:    store ptr null, ptr [[TMP115]], align 8
5485 // CHECK17-NEXT:    [[TMP116:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 6
5486 // CHECK17-NEXT:    store i64 [[TMP5]], ptr [[TMP116]], align 8
5487 // CHECK17-NEXT:    [[TMP117:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 6
5488 // CHECK17-NEXT:    store i64 [[TMP5]], ptr [[TMP117]], align 8
5489 // CHECK17-NEXT:    [[TMP118:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 6
5490 // CHECK17-NEXT:    store ptr null, ptr [[TMP118]], align 8
5491 // CHECK17-NEXT:    [[TMP119:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 7
5492 // CHECK17-NEXT:    store ptr [[VLA1]], ptr [[TMP119]], align 8
5493 // CHECK17-NEXT:    [[TMP120:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 7
5494 // CHECK17-NEXT:    store ptr [[VLA1]], ptr [[TMP120]], align 8
5495 // CHECK17-NEXT:    [[TMP121:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 7
5496 // CHECK17-NEXT:    store i64 [[TMP96]], ptr [[TMP121]], align 8
5497 // CHECK17-NEXT:    [[TMP122:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 7
5498 // CHECK17-NEXT:    store ptr null, ptr [[TMP122]], align 8
5499 // CHECK17-NEXT:    [[TMP123:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 8
5500 // CHECK17-NEXT:    store ptr [[D]], ptr [[TMP123]], align 8
5501 // CHECK17-NEXT:    [[TMP124:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 8
5502 // CHECK17-NEXT:    store ptr [[D]], ptr [[TMP124]], align 8
5503 // CHECK17-NEXT:    [[TMP125:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 8
5504 // CHECK17-NEXT:    store ptr null, ptr [[TMP125]], align 8
5505 // CHECK17-NEXT:    [[TMP126:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 9
5506 // CHECK17-NEXT:    store i64 [[TMP92]], ptr [[TMP126]], align 8
5507 // CHECK17-NEXT:    [[TMP127:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 9
5508 // CHECK17-NEXT:    store i64 [[TMP92]], ptr [[TMP127]], align 8
5509 // CHECK17-NEXT:    [[TMP128:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 9
5510 // CHECK17-NEXT:    store ptr null, ptr [[TMP128]], align 8
5511 // CHECK17-NEXT:    [[TMP129:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0
5512 // CHECK17-NEXT:    [[TMP130:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 0
5513 // CHECK17-NEXT:    [[TMP131:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0
5514 // CHECK17-NEXT:    [[TMP132:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 0
5515 // CHECK17-NEXT:    store i32 2, ptr [[TMP132]], align 4
5516 // CHECK17-NEXT:    [[TMP133:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 1
5517 // CHECK17-NEXT:    store i32 10, ptr [[TMP133]], align 4
5518 // CHECK17-NEXT:    [[TMP134:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 2
5519 // CHECK17-NEXT:    store ptr [[TMP129]], ptr [[TMP134]], align 8
5520 // CHECK17-NEXT:    [[TMP135:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 3
5521 // CHECK17-NEXT:    store ptr [[TMP130]], ptr [[TMP135]], align 8
5522 // CHECK17-NEXT:    [[TMP136:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 4
5523 // CHECK17-NEXT:    store ptr [[TMP131]], ptr [[TMP136]], align 8
5524 // CHECK17-NEXT:    [[TMP137:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 5
5525 // CHECK17-NEXT:    store ptr @.offload_maptypes.4, ptr [[TMP137]], align 8
5526 // CHECK17-NEXT:    [[TMP138:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 6
5527 // CHECK17-NEXT:    store ptr null, ptr [[TMP138]], align 8
5528 // CHECK17-NEXT:    [[TMP139:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 7
5529 // CHECK17-NEXT:    store ptr null, ptr [[TMP139]], align 8
5530 // CHECK17-NEXT:    [[TMP140:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 8
5531 // CHECK17-NEXT:    store i64 0, ptr [[TMP140]], align 8
5532 // CHECK17-NEXT:    [[TMP141:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 9
5533 // CHECK17-NEXT:    store i64 0, ptr [[TMP141]], align 8
5534 // CHECK17-NEXT:    [[TMP142:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 10
5535 // CHECK17-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP142]], align 4
5536 // CHECK17-NEXT:    [[TMP143:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 11
5537 // CHECK17-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP143]], align 4
5538 // CHECK17-NEXT:    [[TMP144:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 12
5539 // CHECK17-NEXT:    store i32 0, ptr [[TMP144]], align 4
5540 // CHECK17-NEXT:    [[TMP145:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.region_id, ptr [[KERNEL_ARGS17]])
5541 // CHECK17-NEXT:    [[TMP146:%.*]] = icmp ne i32 [[TMP145]], 0
5542 // CHECK17-NEXT:    br i1 [[TMP146]], label [[OMP_OFFLOAD_FAILED18:%.*]], label [[OMP_OFFLOAD_CONT19:%.*]]
5543 // CHECK17:       omp_offload.failed18:
5544 // CHECK17-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160(i64 [[TMP90]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]], i64 [[TMP92]]) #[[ATTR3]]
5545 // CHECK17-NEXT:    br label [[OMP_OFFLOAD_CONT19]]
5546 // CHECK17:       omp_offload.cont19:
5547 // CHECK17-NEXT:    br label [[OMP_IF_END21:%.*]]
5548 // CHECK17:       omp_if.else20:
5549 // CHECK17-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160(i64 [[TMP90]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]], i64 [[TMP92]]) #[[ATTR3]]
5550 // CHECK17-NEXT:    br label [[OMP_IF_END21]]
5551 // CHECK17:       omp_if.end21:
5552 // CHECK17-NEXT:    [[TMP147:%.*]] = load i32, ptr [[A]], align 4
5553 // CHECK17-NEXT:    [[TMP148:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
5554 // CHECK17-NEXT:    call void @llvm.stackrestore.p0(ptr [[TMP148]])
5555 // CHECK17-NEXT:    ret i32 [[TMP147]]
5556 //
5557 //
5558 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
5559 // CHECK17-SAME: () #[[ATTR2:[0-9]+]] {
5560 // CHECK17-NEXT:  entry:
5561 // CHECK17-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined)
5562 // CHECK17-NEXT:    ret void
5563 //
5564 //
5565 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined
5566 // CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] {
5567 // CHECK17-NEXT:  entry:
5568 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
5569 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
5570 // CHECK17-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
5571 // CHECK17-NEXT:    [[TMP:%.*]] = alloca i32, align 4
5572 // CHECK17-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
5573 // CHECK17-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
5574 // CHECK17-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
5575 // CHECK17-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
5576 // CHECK17-NEXT:    [[I:%.*]] = alloca i32, align 4
5577 // CHECK17-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
5578 // CHECK17-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
5579 // CHECK17-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
5580 // CHECK17-NEXT:    store i32 5, ptr [[DOTOMP_UB]], align 4
5581 // CHECK17-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
5582 // CHECK17-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
5583 // CHECK17-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
5584 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
5585 // CHECK17-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
5586 // CHECK17-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
5587 // CHECK17-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
5588 // CHECK17-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
5589 // CHECK17:       cond.true:
5590 // CHECK17-NEXT:    br label [[COND_END:%.*]]
5591 // CHECK17:       cond.false:
5592 // CHECK17-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
5593 // CHECK17-NEXT:    br label [[COND_END]]
5594 // CHECK17:       cond.end:
5595 // CHECK17-NEXT:    [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
5596 // CHECK17-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
5597 // CHECK17-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
5598 // CHECK17-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
5599 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
5600 // CHECK17:       omp.inner.for.cond:
5601 // CHECK17-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
5602 // CHECK17-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
5603 // CHECK17-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
5604 // CHECK17-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5605 // CHECK17:       omp.inner.for.body:
5606 // CHECK17-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
5607 // CHECK17-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
5608 // CHECK17-NEXT:    [[ADD:%.*]] = add nsw i32 3, [[MUL]]
5609 // CHECK17-NEXT:    store i32 [[ADD]], ptr [[I]], align 4
5610 // CHECK17-NEXT:    [[TMP8:%.*]] = call i32 @__kmpc_cancel(ptr @[[GLOB2]], i32 [[TMP1]], i32 2)
5611 // CHECK17-NEXT:    [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0
5612 // CHECK17-NEXT:    br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
5613 // CHECK17:       .cancel.exit:
5614 // CHECK17-NEXT:    br label [[CANCEL_EXIT:%.*]]
5615 // CHECK17:       .cancel.continue:
5616 // CHECK17-NEXT:    [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(ptr @[[GLOB2]], i32 [[TMP1]], i32 2)
5617 // CHECK17-NEXT:    [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
5618 // CHECK17-NEXT:    br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]]
5619 // CHECK17:       .cancel.exit2:
5620 // CHECK17-NEXT:    br label [[CANCEL_EXIT]]
5621 // CHECK17:       .cancel.continue3:
5622 // CHECK17-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
5623 // CHECK17:       omp.body.continue:
5624 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
5625 // CHECK17:       omp.inner.for.inc:
5626 // CHECK17-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
5627 // CHECK17-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
5628 // CHECK17-NEXT:    store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4
5629 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND]]
5630 // CHECK17:       omp.inner.for.end:
5631 // CHECK17-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
5632 // CHECK17:       omp.loop.exit:
5633 // CHECK17-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
5634 // CHECK17-NEXT:    br label [[CANCEL_CONT:%.*]]
5635 // CHECK17:       cancel.cont:
5636 // CHECK17-NEXT:    ret void
5637 // CHECK17:       cancel.exit:
5638 // CHECK17-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
5639 // CHECK17-NEXT:    br label [[CANCEL_CONT]]
5640 //
5641 //
5642 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110
5643 // CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR2]] {
5644 // CHECK17-NEXT:  entry:
5645 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
5646 // CHECK17-NEXT:    [[K_ADDR:%.*]] = alloca i64, align 8
5647 // CHECK17-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
5648 // CHECK17-NEXT:    [[K_CASTED:%.*]] = alloca i64, align 8
5649 // CHECK17-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
5650 // CHECK17-NEXT:    store i64 [[K]], ptr [[K_ADDR]], align 8
5651 // CHECK17-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
5652 // CHECK17-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 4
5653 // CHECK17-NEXT:    [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8
5654 // CHECK17-NEXT:    [[TMP2:%.*]] = load i64, ptr [[K_ADDR]], align 8
5655 // CHECK17-NEXT:    store i64 [[TMP2]], ptr [[K_CASTED]], align 8
5656 // CHECK17-NEXT:    [[TMP3:%.*]] = load i64, ptr [[K_CASTED]], align 8
5657 // CHECK17-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.omp_outlined, i64 [[TMP1]], i64 [[TMP3]])
5658 // CHECK17-NEXT:    ret void
5659 //
5660 //
5661 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.omp_outlined
5662 // CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR2]] {
5663 // CHECK17-NEXT:  entry:
5664 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
5665 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
5666 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
5667 // CHECK17-NEXT:    [[K_ADDR:%.*]] = alloca i64, align 8
5668 // CHECK17-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
5669 // CHECK17-NEXT:    [[TMP:%.*]] = alloca i32, align 4
5670 // CHECK17-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i64, align 8
5671 // CHECK17-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
5672 // CHECK17-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
5673 // CHECK17-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
5674 // CHECK17-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
5675 // CHECK17-NEXT:    [[I:%.*]] = alloca i32, align 4
5676 // CHECK17-NEXT:    [[K1:%.*]] = alloca i64, align 8
5677 // CHECK17-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
5678 // CHECK17-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
5679 // CHECK17-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
5680 // CHECK17-NEXT:    store i64 [[K]], ptr [[K_ADDR]], align 8
5681 // CHECK17-NEXT:    [[TMP0:%.*]] = load i64, ptr [[K_ADDR]], align 8
5682 // CHECK17-NEXT:    store i64 [[TMP0]], ptr [[DOTLINEAR_START]], align 8
5683 // CHECK17-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
5684 // CHECK17-NEXT:    store i32 8, ptr [[DOTOMP_UB]], align 4
5685 // CHECK17-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
5686 // CHECK17-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
5687 // CHECK17-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
5688 // CHECK17-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
5689 // CHECK17-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP2]])
5690 // CHECK17-NEXT:    call void @__kmpc_dispatch_init_4(ptr @[[GLOB2]], i32 [[TMP2]], i32 1073741859, i32 0, i32 8, i32 1, i32 1)
5691 // CHECK17-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
5692 // CHECK17:       omp.dispatch.cond:
5693 // CHECK17-NEXT:    [[TMP3:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB2]], i32 [[TMP2]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
5694 // CHECK17-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP3]], 0
5695 // CHECK17-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
5696 // CHECK17:       omp.dispatch.body:
5697 // CHECK17-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
5698 // CHECK17-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
5699 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
5700 // CHECK17:       omp.inner.for.cond:
5701 // CHECK17-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12:![0-9]+]]
5702 // CHECK17-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP12]]
5703 // CHECK17-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
5704 // CHECK17-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5705 // CHECK17:       omp.inner.for.body:
5706 // CHECK17-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]
5707 // CHECK17-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
5708 // CHECK17-NEXT:    [[SUB:%.*]] = sub nsw i32 10, [[MUL]]
5709 // CHECK17-NEXT:    store i32 [[SUB]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]]
5710 // CHECK17-NEXT:    [[TMP8:%.*]] = load i64, ptr [[DOTLINEAR_START]], align 8, !llvm.access.group [[ACC_GRP12]]
5711 // CHECK17-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]
5712 // CHECK17-NEXT:    [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3
5713 // CHECK17-NEXT:    [[CONV:%.*]] = sext i32 [[MUL2]] to i64
5714 // CHECK17-NEXT:    [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV]]
5715 // CHECK17-NEXT:    store i64 [[ADD]], ptr [[K1]], align 8, !llvm.access.group [[ACC_GRP12]]
5716 // CHECK17-NEXT:    [[TMP10:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP12]]
5717 // CHECK17-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
5718 // CHECK17-NEXT:    store i32 [[ADD3]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP12]]
5719 // CHECK17-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
5720 // CHECK17:       omp.body.continue:
5721 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
5722 // CHECK17:       omp.inner.for.inc:
5723 // CHECK17-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]
5724 // CHECK17-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1
5725 // CHECK17-NEXT:    store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]
5726 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
5727 // CHECK17:       omp.inner.for.end:
5728 // CHECK17-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
5729 // CHECK17:       omp.dispatch.inc:
5730 // CHECK17-NEXT:    br label [[OMP_DISPATCH_COND]]
5731 // CHECK17:       omp.dispatch.end:
5732 // CHECK17-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
5733 // CHECK17-NEXT:    [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
5734 // CHECK17-NEXT:    br i1 [[TMP13]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
5735 // CHECK17:       .omp.linear.pu:
5736 // CHECK17-NEXT:    [[TMP14:%.*]] = load i64, ptr [[K1]], align 8
5737 // CHECK17-NEXT:    store i64 [[TMP14]], ptr [[K_ADDR]], align 8
5738 // CHECK17-NEXT:    br label [[DOTOMP_LINEAR_PU_DONE]]
5739 // CHECK17:       .omp.linear.pu.done:
5740 // CHECK17-NEXT:    ret void
5741 //
5742 //
5743 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128
5744 // CHECK17-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] {
5745 // CHECK17-NEXT:  entry:
5746 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
5747 // CHECK17-NEXT:    [[LIN_ADDR:%.*]] = alloca i64, align 8
5748 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
5749 // CHECK17-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
5750 // CHECK17-NEXT:    [[LIN_CASTED:%.*]] = alloca i64, align 8
5751 // CHECK17-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
5752 // CHECK17-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
5753 // CHECK17-NEXT:    store i64 [[LIN]], ptr [[LIN_ADDR]], align 8
5754 // CHECK17-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
5755 // CHECK17-NEXT:    [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2
5756 // CHECK17-NEXT:    store i16 [[TMP0]], ptr [[AA_CASTED]], align 2
5757 // CHECK17-NEXT:    [[TMP1:%.*]] = load i64, ptr [[AA_CASTED]], align 8
5758 // CHECK17-NEXT:    [[TMP2:%.*]] = load i32, ptr [[LIN_ADDR]], align 4
5759 // CHECK17-NEXT:    store i32 [[TMP2]], ptr [[LIN_CASTED]], align 4
5760 // CHECK17-NEXT:    [[TMP3:%.*]] = load i64, ptr [[LIN_CASTED]], align 8
5761 // CHECK17-NEXT:    [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4
5762 // CHECK17-NEXT:    store i32 [[TMP4]], ptr [[A_CASTED]], align 4
5763 // CHECK17-NEXT:    [[TMP5:%.*]] = load i64, ptr [[A_CASTED]], align 8
5764 // CHECK17-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128.omp_outlined, i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]])
5765 // CHECK17-NEXT:    ret void
5766 //
5767 //
5768 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128.omp_outlined
5769 // CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] {
5770 // CHECK17-NEXT:  entry:
5771 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
5772 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
5773 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
5774 // CHECK17-NEXT:    [[LIN_ADDR:%.*]] = alloca i64, align 8
5775 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
5776 // CHECK17-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
5777 // CHECK17-NEXT:    [[TMP:%.*]] = alloca i64, align 8
5778 // CHECK17-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i32, align 4
5779 // CHECK17-NEXT:    [[DOTLINEAR_START1:%.*]] = alloca i32, align 4
5780 // CHECK17-NEXT:    [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
5781 // CHECK17-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
5782 // CHECK17-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
5783 // CHECK17-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
5784 // CHECK17-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
5785 // CHECK17-NEXT:    [[IT:%.*]] = alloca i64, align 8
5786 // CHECK17-NEXT:    [[LIN2:%.*]] = alloca i32, align 4
5787 // CHECK17-NEXT:    [[A3:%.*]] = alloca i32, align 4
5788 // CHECK17-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
5789 // CHECK17-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
5790 // CHECK17-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
5791 // CHECK17-NEXT:    store i64 [[LIN]], ptr [[LIN_ADDR]], align 8
5792 // CHECK17-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
5793 // CHECK17-NEXT:    [[TMP0:%.*]] = load i32, ptr [[LIN_ADDR]], align 4
5794 // CHECK17-NEXT:    store i32 [[TMP0]], ptr [[DOTLINEAR_START]], align 4
5795 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
5796 // CHECK17-NEXT:    store i32 [[TMP1]], ptr [[DOTLINEAR_START1]], align 4
5797 // CHECK17-NEXT:    [[CALL:%.*]] = call noundef i64 @_Z7get_valv()
5798 // CHECK17-NEXT:    store i64 [[CALL]], ptr [[DOTLINEAR_STEP]], align 8
5799 // CHECK17-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8
5800 // CHECK17-NEXT:    store i64 3, ptr [[DOTOMP_UB]], align 8
5801 // CHECK17-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8
5802 // CHECK17-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
5803 // CHECK17-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
5804 // CHECK17-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
5805 // CHECK17-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP3]])
5806 // CHECK17-NEXT:    call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
5807 // CHECK17-NEXT:    [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
5808 // CHECK17-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
5809 // CHECK17-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
5810 // CHECK17:       cond.true:
5811 // CHECK17-NEXT:    br label [[COND_END:%.*]]
5812 // CHECK17:       cond.false:
5813 // CHECK17-NEXT:    [[TMP5:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
5814 // CHECK17-NEXT:    br label [[COND_END]]
5815 // CHECK17:       cond.end:
5816 // CHECK17-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
5817 // CHECK17-NEXT:    store i64 [[COND]], ptr [[DOTOMP_UB]], align 8
5818 // CHECK17-NEXT:    [[TMP6:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
5819 // CHECK17-NEXT:    store i64 [[TMP6]], ptr [[DOTOMP_IV]], align 8
5820 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
5821 // CHECK17:       omp.inner.for.cond:
5822 // CHECK17-NEXT:    [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
5823 // CHECK17-NEXT:    [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
5824 // CHECK17-NEXT:    [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
5825 // CHECK17-NEXT:    br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5826 // CHECK17:       omp.inner.for.body:
5827 // CHECK17-NEXT:    [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
5828 // CHECK17-NEXT:    [[MUL:%.*]] = mul i64 [[TMP9]], 400
5829 // CHECK17-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
5830 // CHECK17-NEXT:    store i64 [[SUB]], ptr [[IT]], align 8
5831 // CHECK17-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTLINEAR_START]], align 4
5832 // CHECK17-NEXT:    [[CONV:%.*]] = sext i32 [[TMP10]] to i64
5833 // CHECK17-NEXT:    [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
5834 // CHECK17-NEXT:    [[TMP12:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8
5835 // CHECK17-NEXT:    [[MUL5:%.*]] = mul i64 [[TMP11]], [[TMP12]]
5836 // CHECK17-NEXT:    [[ADD:%.*]] = add i64 [[CONV]], [[MUL5]]
5837 // CHECK17-NEXT:    [[CONV6:%.*]] = trunc i64 [[ADD]] to i32
5838 // CHECK17-NEXT:    store i32 [[CONV6]], ptr [[LIN2]], align 4
5839 // CHECK17-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTLINEAR_START1]], align 4
5840 // CHECK17-NEXT:    [[CONV7:%.*]] = sext i32 [[TMP13]] to i64
5841 // CHECK17-NEXT:    [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
5842 // CHECK17-NEXT:    [[TMP15:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8
5843 // CHECK17-NEXT:    [[MUL8:%.*]] = mul i64 [[TMP14]], [[TMP15]]
5844 // CHECK17-NEXT:    [[ADD9:%.*]] = add i64 [[CONV7]], [[MUL8]]
5845 // CHECK17-NEXT:    [[CONV10:%.*]] = trunc i64 [[ADD9]] to i32
5846 // CHECK17-NEXT:    store i32 [[CONV10]], ptr [[A3]], align 4
5847 // CHECK17-NEXT:    [[TMP16:%.*]] = load i16, ptr [[AA_ADDR]], align 2
5848 // CHECK17-NEXT:    [[CONV11:%.*]] = sext i16 [[TMP16]] to i32
5849 // CHECK17-NEXT:    [[ADD12:%.*]] = add nsw i32 [[CONV11]], 1
5850 // CHECK17-NEXT:    [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16
5851 // CHECK17-NEXT:    store i16 [[CONV13]], ptr [[AA_ADDR]], align 2
5852 // CHECK17-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
5853 // CHECK17:       omp.body.continue:
5854 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
5855 // CHECK17:       omp.inner.for.inc:
5856 // CHECK17-NEXT:    [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
5857 // CHECK17-NEXT:    [[ADD14:%.*]] = add i64 [[TMP17]], 1
5858 // CHECK17-NEXT:    store i64 [[ADD14]], ptr [[DOTOMP_IV]], align 8
5859 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND]]
5860 // CHECK17:       omp.inner.for.end:
5861 // CHECK17-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
5862 // CHECK17:       omp.loop.exit:
5863 // CHECK17-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]])
5864 // CHECK17-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
5865 // CHECK17-NEXT:    [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
5866 // CHECK17-NEXT:    br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
5867 // CHECK17:       .omp.linear.pu:
5868 // CHECK17-NEXT:    [[TMP20:%.*]] = load i32, ptr [[LIN2]], align 4
5869 // CHECK17-NEXT:    store i32 [[TMP20]], ptr [[LIN_ADDR]], align 4
5870 // CHECK17-NEXT:    [[TMP21:%.*]] = load i32, ptr [[A3]], align 4
5871 // CHECK17-NEXT:    store i32 [[TMP21]], ptr [[A_ADDR]], align 4
5872 // CHECK17-NEXT:    br label [[DOTOMP_LINEAR_PU_DONE]]
5873 // CHECK17:       .omp.linear.pu.done:
5874 // CHECK17-NEXT:    ret void
5875 //
5876 //
5877 // CHECK17-LABEL: define {{[^@]+}}@.omp_task_privates_map.
5878 // CHECK17-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]], ptr noalias noundef [[TMP3:%.*]], ptr noalias noundef [[TMP4:%.*]]) #[[ATTR5:[0-9]+]] {
5879 // CHECK17-NEXT:  entry:
5880 // CHECK17-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
5881 // CHECK17-NEXT:    [[DOTADDR1:%.*]] = alloca ptr, align 8
5882 // CHECK17-NEXT:    [[DOTADDR2:%.*]] = alloca ptr, align 8
5883 // CHECK17-NEXT:    [[DOTADDR3:%.*]] = alloca ptr, align 8
5884 // CHECK17-NEXT:    [[DOTADDR4:%.*]] = alloca ptr, align 8
5885 // CHECK17-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
5886 // CHECK17-NEXT:    store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
5887 // CHECK17-NEXT:    store ptr [[TMP2]], ptr [[DOTADDR2]], align 8
5888 // CHECK17-NEXT:    store ptr [[TMP3]], ptr [[DOTADDR3]], align 8
5889 // CHECK17-NEXT:    store ptr [[TMP4]], ptr [[DOTADDR4]], align 8
5890 // CHECK17-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[DOTADDR]], align 8
5891 // CHECK17-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP5]], i32 0, i32 0
5892 // CHECK17-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[DOTADDR2]], align 8
5893 // CHECK17-NEXT:    store ptr [[TMP6]], ptr [[TMP7]], align 8
5894 // CHECK17-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 1
5895 // CHECK17-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[DOTADDR3]], align 8
5896 // CHECK17-NEXT:    store ptr [[TMP8]], ptr [[TMP9]], align 8
5897 // CHECK17-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 2
5898 // CHECK17-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[DOTADDR4]], align 8
5899 // CHECK17-NEXT:    store ptr [[TMP10]], ptr [[TMP11]], align 8
5900 // CHECK17-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 3
5901 // CHECK17-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[DOTADDR1]], align 8
5902 // CHECK17-NEXT:    store ptr [[TMP12]], ptr [[TMP13]], align 8
5903 // CHECK17-NEXT:    ret void
5904 //
5905 //
5906 // CHECK17-LABEL: define {{[^@]+}}@.omp_task_entry.
5907 // CHECK17-SAME: (i32 noundef signext [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] {
5908 // CHECK17-NEXT:  entry:
5909 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
5910 // CHECK17-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8
5911 // CHECK17-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8
5912 // CHECK17-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8
5913 // CHECK17-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8
5914 // CHECK17-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8
5915 // CHECK17-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca ptr, align 8
5916 // CHECK17-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca ptr, align 8
5917 // CHECK17-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca ptr, align 8
5918 // CHECK17-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca ptr, align 8
5919 // CHECK17-NEXT:    [[KERNEL_ARGS_I:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
5920 // CHECK17-NEXT:    [[AA_CASTED_I:%.*]] = alloca i64, align 8
5921 // CHECK17-NEXT:    [[LIN_CASTED_I:%.*]] = alloca i64, align 8
5922 // CHECK17-NEXT:    [[A_CASTED_I:%.*]] = alloca i64, align 8
5923 // CHECK17-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 4
5924 // CHECK17-NEXT:    [[DOTADDR1:%.*]] = alloca ptr, align 8
5925 // CHECK17-NEXT:    store i32 [[TMP0]], ptr [[DOTADDR]], align 4
5926 // CHECK17-NEXT:    store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
5927 // CHECK17-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4
5928 // CHECK17-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8
5929 // CHECK17-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0
5930 // CHECK17-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2
5931 // CHECK17-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0
5932 // CHECK17-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8
5933 // CHECK17-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 1
5934 // CHECK17-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])
5935 // CHECK17-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])
5936 // CHECK17-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
5937 // CHECK17-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])
5938 // CHECK17-NEXT:    store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24
5939 // CHECK17-NEXT:    store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias !24
5940 // CHECK17-NEXT:    store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24
5941 // CHECK17-NEXT:    store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24
5942 // CHECK17-NEXT:    store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias !24
5943 // CHECK17-NEXT:    store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias !24
5944 // CHECK17-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias !24
5945 // CHECK17-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24
5946 // CHECK17-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24
5947 // CHECK17-NEXT:    call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]
5948 // CHECK17-NEXT:    [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !24
5949 // CHECK17-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !24
5950 // CHECK17-NEXT:    [[TMP14:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !24
5951 // CHECK17-NEXT:    [[TMP15:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !24
5952 // CHECK17-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP9]], i32 0, i32 1
5953 // CHECK17-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP9]], i32 0, i32 2
5954 // CHECK17-NEXT:    store i32 2, ptr [[KERNEL_ARGS_I]], align 4, !noalias !24
5955 // CHECK17-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 1
5956 // CHECK17-NEXT:    store i32 3, ptr [[TMP18]], align 4, !noalias !24
5957 // CHECK17-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 2
5958 // CHECK17-NEXT:    store ptr [[TMP13]], ptr [[TMP19]], align 8, !noalias !24
5959 // CHECK17-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 3
5960 // CHECK17-NEXT:    store ptr [[TMP14]], ptr [[TMP20]], align 8, !noalias !24
5961 // CHECK17-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 4
5962 // CHECK17-NEXT:    store ptr [[TMP15]], ptr [[TMP21]], align 8, !noalias !24
5963 // CHECK17-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 5
5964 // CHECK17-NEXT:    store ptr @.offload_maptypes, ptr [[TMP22]], align 8, !noalias !24
5965 // CHECK17-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 6
5966 // CHECK17-NEXT:    store ptr null, ptr [[TMP23]], align 8, !noalias !24
5967 // CHECK17-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 7
5968 // CHECK17-NEXT:    store ptr null, ptr [[TMP24]], align 8, !noalias !24
5969 // CHECK17-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 8
5970 // CHECK17-NEXT:    store i64 0, ptr [[TMP25]], align 8, !noalias !24
5971 // CHECK17-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 9
5972 // CHECK17-NEXT:    store i64 1, ptr [[TMP26]], align 8, !noalias !24
5973 // CHECK17-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 10
5974 // CHECK17-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP27]], align 4, !noalias !24
5975 // CHECK17-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 11
5976 // CHECK17-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP28]], align 4, !noalias !24
5977 // CHECK17-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 12
5978 // CHECK17-NEXT:    store i32 0, ptr [[TMP29]], align 4, !noalias !24
5979 // CHECK17-NEXT:    [[TMP30:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128.region_id, ptr [[KERNEL_ARGS_I]])
5980 // CHECK17-NEXT:    [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0
5981 // CHECK17-NEXT:    br i1 [[TMP31]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]]
5982 // CHECK17:       omp_offload.failed.i:
5983 // CHECK17-NEXT:    [[TMP32:%.*]] = load i16, ptr [[TMP12]], align 2
5984 // CHECK17-NEXT:    store i16 [[TMP32]], ptr [[AA_CASTED_I]], align 2, !noalias !24
5985 // CHECK17-NEXT:    [[TMP33:%.*]] = load i64, ptr [[AA_CASTED_I]], align 8, !noalias !24
5986 // CHECK17-NEXT:    [[TMP34:%.*]] = load i32, ptr [[TMP16]], align 4
5987 // CHECK17-NEXT:    store i32 [[TMP34]], ptr [[LIN_CASTED_I]], align 4, !noalias !24
5988 // CHECK17-NEXT:    [[TMP35:%.*]] = load i64, ptr [[LIN_CASTED_I]], align 8, !noalias !24
5989 // CHECK17-NEXT:    [[TMP36:%.*]] = load i32, ptr [[TMP17]], align 4
5990 // CHECK17-NEXT:    store i32 [[TMP36]], ptr [[A_CASTED_I]], align 4, !noalias !24
5991 // CHECK17-NEXT:    [[TMP37:%.*]] = load i64, ptr [[A_CASTED_I]], align 8, !noalias !24
5992 // CHECK17-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128(i64 [[TMP33]], i64 [[TMP35]], i64 [[TMP37]]) #[[ATTR3]]
5993 // CHECK17-NEXT:    br label [[DOTOMP_OUTLINED__EXIT]]
5994 // CHECK17:       .omp_outlined..exit:
5995 // CHECK17-NEXT:    ret i32 0
5996 //
5997 //
5998 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136
5999 // CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {
6000 // CHECK17-NEXT:  entry:
6001 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
6002 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
6003 // CHECK17-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
6004 // CHECK17-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
6005 // CHECK17-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
6006 // CHECK17-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
6007 // CHECK17-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
6008 // CHECK17-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 4
6009 // CHECK17-NEXT:    [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8
6010 // CHECK17-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2
6011 // CHECK17-NEXT:    store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
6012 // CHECK17-NEXT:    [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8
6013 // CHECK17-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.omp_outlined, i64 [[TMP1]], i64 [[TMP3]])
6014 // CHECK17-NEXT:    ret void
6015 //
6016 //
6017 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.omp_outlined
6018 // CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {
6019 // CHECK17-NEXT:  entry:
6020 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
6021 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
6022 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
6023 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
6024 // CHECK17-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
6025 // CHECK17-NEXT:    [[TMP:%.*]] = alloca i16, align 2
6026 // CHECK17-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
6027 // CHECK17-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
6028 // CHECK17-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
6029 // CHECK17-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
6030 // CHECK17-NEXT:    [[IT:%.*]] = alloca i16, align 2
6031 // CHECK17-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
6032 // CHECK17-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
6033 // CHECK17-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
6034 // CHECK17-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
6035 // CHECK17-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
6036 // CHECK17-NEXT:    store i32 3, ptr [[DOTOMP_UB]], align 4
6037 // CHECK17-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
6038 // CHECK17-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
6039 // CHECK17-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
6040 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
6041 // CHECK17-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
6042 // CHECK17-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
6043 // CHECK17-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
6044 // CHECK17-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
6045 // CHECK17:       cond.true:
6046 // CHECK17-NEXT:    br label [[COND_END:%.*]]
6047 // CHECK17:       cond.false:
6048 // CHECK17-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
6049 // CHECK17-NEXT:    br label [[COND_END]]
6050 // CHECK17:       cond.end:
6051 // CHECK17-NEXT:    [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
6052 // CHECK17-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
6053 // CHECK17-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
6054 // CHECK17-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
6055 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
6056 // CHECK17:       omp.inner.for.cond:
6057 // CHECK17-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
6058 // CHECK17-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
6059 // CHECK17-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
6060 // CHECK17-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
6061 // CHECK17:       omp.inner.for.body:
6062 // CHECK17-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
6063 // CHECK17-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
6064 // CHECK17-NEXT:    [[ADD:%.*]] = add nsw i32 6, [[MUL]]
6065 // CHECK17-NEXT:    [[CONV:%.*]] = trunc i32 [[ADD]] to i16
6066 // CHECK17-NEXT:    store i16 [[CONV]], ptr [[IT]], align 2
6067 // CHECK17-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
6068 // CHECK17-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
6069 // CHECK17-NEXT:    store i32 [[ADD2]], ptr [[A_ADDR]], align 4
6070 // CHECK17-NEXT:    [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2
6071 // CHECK17-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP9]] to i32
6072 // CHECK17-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
6073 // CHECK17-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
6074 // CHECK17-NEXT:    store i16 [[CONV5]], ptr [[AA_ADDR]], align 2
6075 // CHECK17-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
6076 // CHECK17:       omp.body.continue:
6077 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
6078 // CHECK17:       omp.inner.for.inc:
6079 // CHECK17-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
6080 // CHECK17-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1
6081 // CHECK17-NEXT:    store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4
6082 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND]]
6083 // CHECK17:       omp.inner.for.end:
6084 // CHECK17-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
6085 // CHECK17:       omp.loop.exit:
6086 // CHECK17-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
6087 // CHECK17-NEXT:    ret void
6088 //
6089 //
6090 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160
6091 // CHECK17-SAME: (i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
6092 // CHECK17-NEXT:  entry:
6093 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
6094 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
6095 // CHECK17-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
6096 // CHECK17-NEXT:    [[BN_ADDR:%.*]] = alloca ptr, align 8
6097 // CHECK17-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
6098 // CHECK17-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
6099 // CHECK17-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
6100 // CHECK17-NEXT:    [[CN_ADDR:%.*]] = alloca ptr, align 8
6101 // CHECK17-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
6102 // CHECK17-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
6103 // CHECK17-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
6104 // CHECK17-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
6105 // CHECK17-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
6106 // CHECK17-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
6107 // CHECK17-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
6108 // CHECK17-NEXT:    store ptr [[BN]], ptr [[BN_ADDR]], align 8
6109 // CHECK17-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
6110 // CHECK17-NEXT:    store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
6111 // CHECK17-NEXT:    store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8
6112 // CHECK17-NEXT:    store ptr [[CN]], ptr [[CN_ADDR]], align 8
6113 // CHECK17-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
6114 // CHECK17-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
6115 // CHECK17-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
6116 // CHECK17-NEXT:    [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
6117 // CHECK17-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8
6118 // CHECK17-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
6119 // CHECK17-NEXT:    [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
6120 // CHECK17-NEXT:    [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8
6121 // CHECK17-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8
6122 // CHECK17-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8
6123 // CHECK17-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
6124 // CHECK17-NEXT:    store i32 [[TMP8]], ptr [[A_CASTED]], align 4
6125 // CHECK17-NEXT:    [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 8
6126 // CHECK17-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
6127 // CHECK17-NEXT:    store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
6128 // CHECK17-NEXT:    [[TMP11:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8
6129 // CHECK17-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined, i64 [[TMP9]], ptr [[TMP0]], i64 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i64 [[TMP11]])
6130 // CHECK17-NEXT:    ret void
6131 //
6132 //
6133 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined
6134 // CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
6135 // CHECK17-NEXT:  entry:
6136 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
6137 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
6138 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
6139 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
6140 // CHECK17-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
6141 // CHECK17-NEXT:    [[BN_ADDR:%.*]] = alloca ptr, align 8
6142 // CHECK17-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
6143 // CHECK17-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
6144 // CHECK17-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
6145 // CHECK17-NEXT:    [[CN_ADDR:%.*]] = alloca ptr, align 8
6146 // CHECK17-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
6147 // CHECK17-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
6148 // CHECK17-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
6149 // CHECK17-NEXT:    [[TMP:%.*]] = alloca i8, align 1
6150 // CHECK17-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
6151 // CHECK17-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
6152 // CHECK17-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
6153 // CHECK17-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
6154 // CHECK17-NEXT:    [[IT:%.*]] = alloca i8, align 1
6155 // CHECK17-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
6156 // CHECK17-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
6157 // CHECK17-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
6158 // CHECK17-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
6159 // CHECK17-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
6160 // CHECK17-NEXT:    store ptr [[BN]], ptr [[BN_ADDR]], align 8
6161 // CHECK17-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
6162 // CHECK17-NEXT:    store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
6163 // CHECK17-NEXT:    store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8
6164 // CHECK17-NEXT:    store ptr [[CN]], ptr [[CN_ADDR]], align 8
6165 // CHECK17-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
6166 // CHECK17-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
6167 // CHECK17-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
6168 // CHECK17-NEXT:    [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
6169 // CHECK17-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8
6170 // CHECK17-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
6171 // CHECK17-NEXT:    [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
6172 // CHECK17-NEXT:    [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8
6173 // CHECK17-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8
6174 // CHECK17-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8
6175 // CHECK17-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
6176 // CHECK17-NEXT:    store i32 25, ptr [[DOTOMP_UB]], align 4
6177 // CHECK17-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
6178 // CHECK17-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
6179 // CHECK17-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
6180 // CHECK17-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
6181 // CHECK17-NEXT:    [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4
6182 // CHECK17-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP10]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
6183 // CHECK17-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
6184 // CHECK17:       omp.dispatch.cond:
6185 // CHECK17-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
6186 // CHECK17-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
6187 // CHECK17-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
6188 // CHECK17:       cond.true:
6189 // CHECK17-NEXT:    br label [[COND_END:%.*]]
6190 // CHECK17:       cond.false:
6191 // CHECK17-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
6192 // CHECK17-NEXT:    br label [[COND_END]]
6193 // CHECK17:       cond.end:
6194 // CHECK17-NEXT:    [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
6195 // CHECK17-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
6196 // CHECK17-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
6197 // CHECK17-NEXT:    store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4
6198 // CHECK17-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
6199 // CHECK17-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
6200 // CHECK17-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
6201 // CHECK17-NEXT:    br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
6202 // CHECK17:       omp.dispatch.body:
6203 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
6204 // CHECK17:       omp.inner.for.cond:
6205 // CHECK17-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
6206 // CHECK17-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
6207 // CHECK17-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
6208 // CHECK17-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
6209 // CHECK17:       omp.inner.for.body:
6210 // CHECK17-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
6211 // CHECK17-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
6212 // CHECK17-NEXT:    [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
6213 // CHECK17-NEXT:    [[CONV:%.*]] = trunc i32 [[SUB]] to i8
6214 // CHECK17-NEXT:    store i8 [[CONV]], ptr [[IT]], align 1
6215 // CHECK17-NEXT:    [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4
6216 // CHECK17-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
6217 // CHECK17-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 4
6218 // CHECK17-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 2
6219 // CHECK17-NEXT:    [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4
6220 // CHECK17-NEXT:    [[CONV7:%.*]] = fpext float [[TMP20]] to double
6221 // CHECK17-NEXT:    [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00
6222 // CHECK17-NEXT:    [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
6223 // CHECK17-NEXT:    store float [[CONV9]], ptr [[ARRAYIDX]], align 4
6224 // CHECK17-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 3
6225 // CHECK17-NEXT:    [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4
6226 // CHECK17-NEXT:    [[CONV11:%.*]] = fpext float [[TMP21]] to double
6227 // CHECK17-NEXT:    [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
6228 // CHECK17-NEXT:    [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
6229 // CHECK17-NEXT:    store float [[CONV13]], ptr [[ARRAYIDX10]], align 4
6230 // CHECK17-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 1
6231 // CHECK17-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i64 0, i64 2
6232 // CHECK17-NEXT:    [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8
6233 // CHECK17-NEXT:    [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
6234 // CHECK17-NEXT:    store double [[ADD16]], ptr [[ARRAYIDX15]], align 8
6235 // CHECK17-NEXT:    [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]
6236 // CHECK17-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i64 [[TMP23]]
6237 // CHECK17-NEXT:    [[ARRAYIDX18:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX17]], i64 3
6238 // CHECK17-NEXT:    [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 8
6239 // CHECK17-NEXT:    [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
6240 // CHECK17-NEXT:    store double [[ADD19]], ptr [[ARRAYIDX18]], align 8
6241 // CHECK17-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0
6242 // CHECK17-NEXT:    [[TMP25:%.*]] = load i64, ptr [[X]], align 8
6243 // CHECK17-NEXT:    [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
6244 // CHECK17-NEXT:    store i64 [[ADD20]], ptr [[X]], align 8
6245 // CHECK17-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1
6246 // CHECK17-NEXT:    [[TMP26:%.*]] = load i8, ptr [[Y]], align 8
6247 // CHECK17-NEXT:    [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
6248 // CHECK17-NEXT:    [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
6249 // CHECK17-NEXT:    [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
6250 // CHECK17-NEXT:    store i8 [[CONV23]], ptr [[Y]], align 8
6251 // CHECK17-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
6252 // CHECK17:       omp.body.continue:
6253 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
6254 // CHECK17:       omp.inner.for.inc:
6255 // CHECK17-NEXT:    [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
6256 // CHECK17-NEXT:    [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
6257 // CHECK17-NEXT:    store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4
6258 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND]]
6259 // CHECK17:       omp.inner.for.end:
6260 // CHECK17-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
6261 // CHECK17:       omp.dispatch.inc:
6262 // CHECK17-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
6263 // CHECK17-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
6264 // CHECK17-NEXT:    [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
6265 // CHECK17-NEXT:    store i32 [[ADD25]], ptr [[DOTOMP_LB]], align 4
6266 // CHECK17-NEXT:    [[TMP30:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
6267 // CHECK17-NEXT:    [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
6268 // CHECK17-NEXT:    [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
6269 // CHECK17-NEXT:    store i32 [[ADD26]], ptr [[DOTOMP_UB]], align 4
6270 // CHECK17-NEXT:    br label [[OMP_DISPATCH_COND]]
6271 // CHECK17:       omp.dispatch.end:
6272 // CHECK17-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP10]])
6273 // CHECK17-NEXT:    ret void
6274 //
6275 //
6276 // CHECK17-LABEL: define {{[^@]+}}@_Z3bari
6277 // CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
6278 // CHECK17-NEXT:  entry:
6279 // CHECK17-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
6280 // CHECK17-NEXT:    [[A:%.*]] = alloca i32, align 4
6281 // CHECK17-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
6282 // CHECK17-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
6283 // CHECK17-NEXT:    store i32 0, ptr [[A]], align 4
6284 // CHECK17-NEXT:    [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
6285 // CHECK17-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]])
6286 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A]], align 4
6287 // CHECK17-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
6288 // CHECK17-NEXT:    store i32 [[ADD]], ptr [[A]], align 4
6289 // CHECK17-NEXT:    [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
6290 // CHECK17-NEXT:    [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(ptr noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]])
6291 // CHECK17-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A]], align 4
6292 // CHECK17-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
6293 // CHECK17-NEXT:    store i32 [[ADD2]], ptr [[A]], align 4
6294 // CHECK17-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
6295 // CHECK17-NEXT:    [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]])
6296 // CHECK17-NEXT:    [[TMP5:%.*]] = load i32, ptr [[A]], align 4
6297 // CHECK17-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
6298 // CHECK17-NEXT:    store i32 [[ADD4]], ptr [[A]], align 4
6299 // CHECK17-NEXT:    [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4
6300 // CHECK17-NEXT:    [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]])
6301 // CHECK17-NEXT:    [[TMP7:%.*]] = load i32, ptr [[A]], align 4
6302 // CHECK17-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
6303 // CHECK17-NEXT:    store i32 [[ADD6]], ptr [[A]], align 4
6304 // CHECK17-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A]], align 4
6305 // CHECK17-NEXT:    ret i32 [[TMP8]]
6306 //
6307 //
6308 // CHECK17-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
6309 // CHECK17-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
6310 // CHECK17-NEXT:  entry:
6311 // CHECK17-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
6312 // CHECK17-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
6313 // CHECK17-NEXT:    [[B:%.*]] = alloca i32, align 4
6314 // CHECK17-NEXT:    [[SAVED_STACK:%.*]] = alloca ptr, align 8
6315 // CHECK17-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
6316 // CHECK17-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
6317 // CHECK17-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 8
6318 // CHECK17-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 8
6319 // CHECK17-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 8
6320 // CHECK17-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8
6321 // CHECK17-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
6322 // CHECK17-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
6323 // CHECK17-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
6324 // CHECK17-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
6325 // CHECK17-NEXT:    [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
6326 // CHECK17-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
6327 // CHECK17-NEXT:    store i32 [[ADD]], ptr [[B]], align 4
6328 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
6329 // CHECK17-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
6330 // CHECK17-NEXT:    [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()
6331 // CHECK17-NEXT:    store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8
6332 // CHECK17-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
6333 // CHECK17-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
6334 // CHECK17-NEXT:    store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8
6335 // CHECK17-NEXT:    [[TMP5:%.*]] = load i32, ptr [[B]], align 4
6336 // CHECK17-NEXT:    store i32 [[TMP5]], ptr [[B_CASTED]], align 4
6337 // CHECK17-NEXT:    [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 8
6338 // CHECK17-NEXT:    [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 4
6339 // CHECK17-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60
6340 // CHECK17-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
6341 // CHECK17:       omp_if.then:
6342 // CHECK17-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0
6343 // CHECK17-NEXT:    [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]]
6344 // CHECK17-NEXT:    [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2
6345 // CHECK17-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes.5, i64 40, i1 false)
6346 // CHECK17-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
6347 // CHECK17-NEXT:    store ptr [[THIS1]], ptr [[TMP10]], align 8
6348 // CHECK17-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
6349 // CHECK17-NEXT:    store ptr [[A]], ptr [[TMP11]], align 8
6350 // CHECK17-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
6351 // CHECK17-NEXT:    store ptr null, ptr [[TMP12]], align 8
6352 // CHECK17-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
6353 // CHECK17-NEXT:    store i64 [[TMP6]], ptr [[TMP13]], align 8
6354 // CHECK17-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
6355 // CHECK17-NEXT:    store i64 [[TMP6]], ptr [[TMP14]], align 8
6356 // CHECK17-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
6357 // CHECK17-NEXT:    store ptr null, ptr [[TMP15]], align 8
6358 // CHECK17-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
6359 // CHECK17-NEXT:    store i64 2, ptr [[TMP16]], align 8
6360 // CHECK17-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
6361 // CHECK17-NEXT:    store i64 2, ptr [[TMP17]], align 8
6362 // CHECK17-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
6363 // CHECK17-NEXT:    store ptr null, ptr [[TMP18]], align 8
6364 // CHECK17-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
6365 // CHECK17-NEXT:    store i64 [[TMP2]], ptr [[TMP19]], align 8
6366 // CHECK17-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
6367 // CHECK17-NEXT:    store i64 [[TMP2]], ptr [[TMP20]], align 8
6368 // CHECK17-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
6369 // CHECK17-NEXT:    store ptr null, ptr [[TMP21]], align 8
6370 // CHECK17-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
6371 // CHECK17-NEXT:    store ptr [[VLA]], ptr [[TMP22]], align 8
6372 // CHECK17-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4
6373 // CHECK17-NEXT:    store ptr [[VLA]], ptr [[TMP23]], align 8
6374 // CHECK17-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 4
6375 // CHECK17-NEXT:    store i64 [[TMP9]], ptr [[TMP24]], align 8
6376 // CHECK17-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
6377 // CHECK17-NEXT:    store ptr null, ptr [[TMP25]], align 8
6378 // CHECK17-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
6379 // CHECK17-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
6380 // CHECK17-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0
6381 // CHECK17-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
6382 // CHECK17-NEXT:    store i32 2, ptr [[TMP29]], align 4
6383 // CHECK17-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
6384 // CHECK17-NEXT:    store i32 5, ptr [[TMP30]], align 4
6385 // CHECK17-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
6386 // CHECK17-NEXT:    store ptr [[TMP26]], ptr [[TMP31]], align 8
6387 // CHECK17-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
6388 // CHECK17-NEXT:    store ptr [[TMP27]], ptr [[TMP32]], align 8
6389 // CHECK17-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
6390 // CHECK17-NEXT:    store ptr [[TMP28]], ptr [[TMP33]], align 8
6391 // CHECK17-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
6392 // CHECK17-NEXT:    store ptr @.offload_maptypes.6, ptr [[TMP34]], align 8
6393 // CHECK17-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
6394 // CHECK17-NEXT:    store ptr null, ptr [[TMP35]], align 8
6395 // CHECK17-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
6396 // CHECK17-NEXT:    store ptr null, ptr [[TMP36]], align 8
6397 // CHECK17-NEXT:    [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
6398 // CHECK17-NEXT:    store i64 0, ptr [[TMP37]], align 8
6399 // CHECK17-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
6400 // CHECK17-NEXT:    store i64 0, ptr [[TMP38]], align 8
6401 // CHECK17-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
6402 // CHECK17-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP39]], align 4
6403 // CHECK17-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
6404 // CHECK17-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP40]], align 4
6405 // CHECK17-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
6406 // CHECK17-NEXT:    store i32 0, ptr [[TMP41]], align 4
6407 // CHECK17-NEXT:    [[TMP42:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232.region_id, ptr [[KERNEL_ARGS]])
6408 // CHECK17-NEXT:    [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0
6409 // CHECK17-NEXT:    br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
6410 // CHECK17:       omp_offload.failed:
6411 // CHECK17-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232(ptr [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], ptr [[VLA]]) #[[ATTR3]]
6412 // CHECK17-NEXT:    br label [[OMP_OFFLOAD_CONT]]
6413 // CHECK17:       omp_offload.cont:
6414 // CHECK17-NEXT:    br label [[OMP_IF_END:%.*]]
6415 // CHECK17:       omp_if.else:
6416 // CHECK17-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232(ptr [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], ptr [[VLA]]) #[[ATTR3]]
6417 // CHECK17-NEXT:    br label [[OMP_IF_END]]
6418 // CHECK17:       omp_if.end:
6419 // CHECK17-NEXT:    [[TMP44:%.*]] = mul nsw i64 1, [[TMP2]]
6420 // CHECK17-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP44]]
6421 // CHECK17-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1
6422 // CHECK17-NEXT:    [[TMP45:%.*]] = load i16, ptr [[ARRAYIDX2]], align 2
6423 // CHECK17-NEXT:    [[CONV:%.*]] = sext i16 [[TMP45]] to i32
6424 // CHECK17-NEXT:    [[TMP46:%.*]] = load i32, ptr [[B]], align 4
6425 // CHECK17-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP46]]
6426 // CHECK17-NEXT:    [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
6427 // CHECK17-NEXT:    call void @llvm.stackrestore.p0(ptr [[TMP47]])
6428 // CHECK17-NEXT:    ret i32 [[ADD3]]
6429 //
6430 //
6431 // CHECK17-LABEL: define {{[^@]+}}@_ZL7fstatici
6432 // CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
6433 // CHECK17-NEXT:  entry:
6434 // CHECK17-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
6435 // CHECK17-NEXT:    [[A:%.*]] = alloca i32, align 4
6436 // CHECK17-NEXT:    [[AA:%.*]] = alloca i16, align 2
6437 // CHECK17-NEXT:    [[AAA:%.*]] = alloca i8, align 1
6438 // CHECK17-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
6439 // CHECK17-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
6440 // CHECK17-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
6441 // CHECK17-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
6442 // CHECK17-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 8
6443 // CHECK17-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 8
6444 // CHECK17-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 8
6445 // CHECK17-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
6446 // CHECK17-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
6447 // CHECK17-NEXT:    store i32 0, ptr [[A]], align 4
6448 // CHECK17-NEXT:    store i16 0, ptr [[AA]], align 2
6449 // CHECK17-NEXT:    store i8 0, ptr [[AAA]], align 1
6450 // CHECK17-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A]], align 4
6451 // CHECK17-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 4
6452 // CHECK17-NEXT:    [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8
6453 // CHECK17-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA]], align 2
6454 // CHECK17-NEXT:    store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
6455 // CHECK17-NEXT:    [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8
6456 // CHECK17-NEXT:    [[TMP4:%.*]] = load i8, ptr [[AAA]], align 1
6457 // CHECK17-NEXT:    store i8 [[TMP4]], ptr [[AAA_CASTED]], align 1
6458 // CHECK17-NEXT:    [[TMP5:%.*]] = load i64, ptr [[AAA_CASTED]], align 8
6459 // CHECK17-NEXT:    [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4
6460 // CHECK17-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50
6461 // CHECK17-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
6462 // CHECK17:       omp_if.then:
6463 // CHECK17-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
6464 // CHECK17-NEXT:    store i64 [[TMP1]], ptr [[TMP7]], align 8
6465 // CHECK17-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
6466 // CHECK17-NEXT:    store i64 [[TMP1]], ptr [[TMP8]], align 8
6467 // CHECK17-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
6468 // CHECK17-NEXT:    store ptr null, ptr [[TMP9]], align 8
6469 // CHECK17-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
6470 // CHECK17-NEXT:    store i64 [[TMP3]], ptr [[TMP10]], align 8
6471 // CHECK17-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
6472 // CHECK17-NEXT:    store i64 [[TMP3]], ptr [[TMP11]], align 8
6473 // CHECK17-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
6474 // CHECK17-NEXT:    store ptr null, ptr [[TMP12]], align 8
6475 // CHECK17-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
6476 // CHECK17-NEXT:    store i64 [[TMP5]], ptr [[TMP13]], align 8
6477 // CHECK17-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
6478 // CHECK17-NEXT:    store i64 [[TMP5]], ptr [[TMP14]], align 8
6479 // CHECK17-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
6480 // CHECK17-NEXT:    store ptr null, ptr [[TMP15]], align 8
6481 // CHECK17-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
6482 // CHECK17-NEXT:    store ptr [[B]], ptr [[TMP16]], align 8
6483 // CHECK17-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
6484 // CHECK17-NEXT:    store ptr [[B]], ptr [[TMP17]], align 8
6485 // CHECK17-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
6486 // CHECK17-NEXT:    store ptr null, ptr [[TMP18]], align 8
6487 // CHECK17-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
6488 // CHECK17-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
6489 // CHECK17-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
6490 // CHECK17-NEXT:    store i32 2, ptr [[TMP21]], align 4
6491 // CHECK17-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
6492 // CHECK17-NEXT:    store i32 4, ptr [[TMP22]], align 4
6493 // CHECK17-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
6494 // CHECK17-NEXT:    store ptr [[TMP19]], ptr [[TMP23]], align 8
6495 // CHECK17-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
6496 // CHECK17-NEXT:    store ptr [[TMP20]], ptr [[TMP24]], align 8
6497 // CHECK17-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
6498 // CHECK17-NEXT:    store ptr @.offload_sizes.7, ptr [[TMP25]], align 8
6499 // CHECK17-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
6500 // CHECK17-NEXT:    store ptr @.offload_maptypes.8, ptr [[TMP26]], align 8
6501 // CHECK17-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
6502 // CHECK17-NEXT:    store ptr null, ptr [[TMP27]], align 8
6503 // CHECK17-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
6504 // CHECK17-NEXT:    store ptr null, ptr [[TMP28]], align 8
6505 // CHECK17-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
6506 // CHECK17-NEXT:    store i64 0, ptr [[TMP29]], align 8
6507 // CHECK17-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
6508 // CHECK17-NEXT:    store i64 0, ptr [[TMP30]], align 8
6509 // CHECK17-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
6510 // CHECK17-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP31]], align 4
6511 // CHECK17-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
6512 // CHECK17-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP32]], align 4
6513 // CHECK17-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
6514 // CHECK17-NEXT:    store i32 0, ptr [[TMP33]], align 4
6515 // CHECK17-NEXT:    [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214.region_id, ptr [[KERNEL_ARGS]])
6516 // CHECK17-NEXT:    [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0
6517 // CHECK17-NEXT:    br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
6518 // CHECK17:       omp_offload.failed:
6519 // CHECK17-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], ptr [[B]]) #[[ATTR3]]
6520 // CHECK17-NEXT:    br label [[OMP_OFFLOAD_CONT]]
6521 // CHECK17:       omp_offload.cont:
6522 // CHECK17-NEXT:    br label [[OMP_IF_END:%.*]]
6523 // CHECK17:       omp_if.else:
6524 // CHECK17-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], ptr [[B]]) #[[ATTR3]]
6525 // CHECK17-NEXT:    br label [[OMP_IF_END]]
6526 // CHECK17:       omp_if.end:
6527 // CHECK17-NEXT:    [[TMP36:%.*]] = load i32, ptr [[A]], align 4
6528 // CHECK17-NEXT:    ret i32 [[TMP36]]
6529 //
6530 //
6531 // CHECK17-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
6532 // CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
6533 // CHECK17-NEXT:  entry:
6534 // CHECK17-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
6535 // CHECK17-NEXT:    [[A:%.*]] = alloca i32, align 4
6536 // CHECK17-NEXT:    [[AA:%.*]] = alloca i16, align 2
6537 // CHECK17-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
6538 // CHECK17-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
6539 // CHECK17-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
6540 // CHECK17-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8
6541 // CHECK17-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 8
6542 // CHECK17-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 8
6543 // CHECK17-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
6544 // CHECK17-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
6545 // CHECK17-NEXT:    store i32 0, ptr [[A]], align 4
6546 // CHECK17-NEXT:    store i16 0, ptr [[AA]], align 2
6547 // CHECK17-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A]], align 4
6548 // CHECK17-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 4
6549 // CHECK17-NEXT:    [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8
6550 // CHECK17-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA]], align 2
6551 // CHECK17-NEXT:    store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
6552 // CHECK17-NEXT:    [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8
6553 // CHECK17-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
6554 // CHECK17-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
6555 // CHECK17-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
6556 // CHECK17:       omp_if.then:
6557 // CHECK17-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
6558 // CHECK17-NEXT:    store i64 [[TMP1]], ptr [[TMP5]], align 8
6559 // CHECK17-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
6560 // CHECK17-NEXT:    store i64 [[TMP1]], ptr [[TMP6]], align 8
6561 // CHECK17-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
6562 // CHECK17-NEXT:    store ptr null, ptr [[TMP7]], align 8
6563 // CHECK17-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
6564 // CHECK17-NEXT:    store i64 [[TMP3]], ptr [[TMP8]], align 8
6565 // CHECK17-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
6566 // CHECK17-NEXT:    store i64 [[TMP3]], ptr [[TMP9]], align 8
6567 // CHECK17-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
6568 // CHECK17-NEXT:    store ptr null, ptr [[TMP10]], align 8
6569 // CHECK17-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
6570 // CHECK17-NEXT:    store ptr [[B]], ptr [[TMP11]], align 8
6571 // CHECK17-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
6572 // CHECK17-NEXT:    store ptr [[B]], ptr [[TMP12]], align 8
6573 // CHECK17-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
6574 // CHECK17-NEXT:    store ptr null, ptr [[TMP13]], align 8
6575 // CHECK17-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
6576 // CHECK17-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
6577 // CHECK17-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
6578 // CHECK17-NEXT:    store i32 2, ptr [[TMP16]], align 4
6579 // CHECK17-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
6580 // CHECK17-NEXT:    store i32 3, ptr [[TMP17]], align 4
6581 // CHECK17-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
6582 // CHECK17-NEXT:    store ptr [[TMP14]], ptr [[TMP18]], align 8
6583 // CHECK17-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
6584 // CHECK17-NEXT:    store ptr [[TMP15]], ptr [[TMP19]], align 8
6585 // CHECK17-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
6586 // CHECK17-NEXT:    store ptr @.offload_sizes.9, ptr [[TMP20]], align 8
6587 // CHECK17-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
6588 // CHECK17-NEXT:    store ptr @.offload_maptypes.10, ptr [[TMP21]], align 8
6589 // CHECK17-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
6590 // CHECK17-NEXT:    store ptr null, ptr [[TMP22]], align 8
6591 // CHECK17-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
6592 // CHECK17-NEXT:    store ptr null, ptr [[TMP23]], align 8
6593 // CHECK17-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
6594 // CHECK17-NEXT:    store i64 0, ptr [[TMP24]], align 8
6595 // CHECK17-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
6596 // CHECK17-NEXT:    store i64 0, ptr [[TMP25]], align 8
6597 // CHECK17-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
6598 // CHECK17-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP26]], align 4
6599 // CHECK17-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
6600 // CHECK17-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP27]], align 4
6601 // CHECK17-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
6602 // CHECK17-NEXT:    store i32 0, ptr [[TMP28]], align 4
6603 // CHECK17-NEXT:    [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197.region_id, ptr [[KERNEL_ARGS]])
6604 // CHECK17-NEXT:    [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
6605 // CHECK17-NEXT:    br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
6606 // CHECK17:       omp_offload.failed:
6607 // CHECK17-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR3]]
6608 // CHECK17-NEXT:    br label [[OMP_OFFLOAD_CONT]]
6609 // CHECK17:       omp_offload.cont:
6610 // CHECK17-NEXT:    br label [[OMP_IF_END:%.*]]
6611 // CHECK17:       omp_if.else:
6612 // CHECK17-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR3]]
6613 // CHECK17-NEXT:    br label [[OMP_IF_END]]
6614 // CHECK17:       omp_if.end:
6615 // CHECK17-NEXT:    [[TMP31:%.*]] = load i32, ptr [[A]], align 4
6616 // CHECK17-NEXT:    ret i32 [[TMP31]]
6617 //
6618 //
6619 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232
6620 // CHECK17-SAME: (ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
6621 // CHECK17-NEXT:  entry:
6622 // CHECK17-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
6623 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
6624 // CHECK17-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
6625 // CHECK17-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
6626 // CHECK17-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
6627 // CHECK17-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
6628 // CHECK17-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
6629 // CHECK17-NEXT:    store i64 [[B]], ptr [[B_ADDR]], align 8
6630 // CHECK17-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
6631 // CHECK17-NEXT:    store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
6632 // CHECK17-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
6633 // CHECK17-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
6634 // CHECK17-NEXT:    [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
6635 // CHECK17-NEXT:    [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
6636 // CHECK17-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
6637 // CHECK17-NEXT:    [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4
6638 // CHECK17-NEXT:    store i32 [[TMP4]], ptr [[B_CASTED]], align 4
6639 // CHECK17-NEXT:    [[TMP5:%.*]] = load i64, ptr [[B_CASTED]], align 8
6640 // CHECK17-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232.omp_outlined, ptr [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], ptr [[TMP3]])
6641 // CHECK17-NEXT:    ret void
6642 //
6643 //
6644 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232.omp_outlined
6645 // CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
6646 // CHECK17-NEXT:  entry:
6647 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
6648 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
6649 // CHECK17-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
6650 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
6651 // CHECK17-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
6652 // CHECK17-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
6653 // CHECK17-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
6654 // CHECK17-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
6655 // CHECK17-NEXT:    [[TMP:%.*]] = alloca i64, align 8
6656 // CHECK17-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
6657 // CHECK17-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
6658 // CHECK17-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
6659 // CHECK17-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
6660 // CHECK17-NEXT:    [[IT:%.*]] = alloca i64, align 8
6661 // CHECK17-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
6662 // CHECK17-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
6663 // CHECK17-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
6664 // CHECK17-NEXT:    store i64 [[B]], ptr [[B_ADDR]], align 8
6665 // CHECK17-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
6666 // CHECK17-NEXT:    store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
6667 // CHECK17-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
6668 // CHECK17-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
6669 // CHECK17-NEXT:    [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
6670 // CHECK17-NEXT:    [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
6671 // CHECK17-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
6672 // CHECK17-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8
6673 // CHECK17-NEXT:    store i64 3, ptr [[DOTOMP_UB]], align 8
6674 // CHECK17-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8
6675 // CHECK17-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
6676 // CHECK17-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
6677 // CHECK17-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
6678 // CHECK17-NEXT:    call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP5]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
6679 // CHECK17-NEXT:    [[TMP6:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
6680 // CHECK17-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3
6681 // CHECK17-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
6682 // CHECK17:       cond.true:
6683 // CHECK17-NEXT:    br label [[COND_END:%.*]]
6684 // CHECK17:       cond.false:
6685 // CHECK17-NEXT:    [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
6686 // CHECK17-NEXT:    br label [[COND_END]]
6687 // CHECK17:       cond.end:
6688 // CHECK17-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
6689 // CHECK17-NEXT:    store i64 [[COND]], ptr [[DOTOMP_UB]], align 8
6690 // CHECK17-NEXT:    [[TMP8:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
6691 // CHECK17-NEXT:    store i64 [[TMP8]], ptr [[DOTOMP_IV]], align 8
6692 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
6693 // CHECK17:       omp.inner.for.cond:
6694 // CHECK17-NEXT:    [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
6695 // CHECK17-NEXT:    [[TMP10:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
6696 // CHECK17-NEXT:    [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
6697 // CHECK17-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
6698 // CHECK17:       omp.inner.for.body:
6699 // CHECK17-NEXT:    [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
6700 // CHECK17-NEXT:    [[MUL:%.*]] = mul i64 [[TMP11]], 400
6701 // CHECK17-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
6702 // CHECK17-NEXT:    store i64 [[SUB]], ptr [[IT]], align 8
6703 // CHECK17-NEXT:    [[TMP12:%.*]] = load i32, ptr [[B_ADDR]], align 4
6704 // CHECK17-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP12]] to double
6705 // CHECK17-NEXT:    [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
6706 // CHECK17-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0
6707 // CHECK17-NEXT:    store double [[ADD]], ptr [[A]], align 8
6708 // CHECK17-NEXT:    [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0
6709 // CHECK17-NEXT:    [[TMP13:%.*]] = load double, ptr [[A4]], align 8
6710 // CHECK17-NEXT:    [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
6711 // CHECK17-NEXT:    store double [[INC]], ptr [[A4]], align 8
6712 // CHECK17-NEXT:    [[CONV5:%.*]] = fptosi double [[INC]] to i16
6713 // CHECK17-NEXT:    [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]]
6714 // CHECK17-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i64 [[TMP14]]
6715 // CHECK17-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1
6716 // CHECK17-NEXT:    store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2
6717 // CHECK17-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
6718 // CHECK17:       omp.body.continue:
6719 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
6720 // CHECK17:       omp.inner.for.inc:
6721 // CHECK17-NEXT:    [[TMP15:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
6722 // CHECK17-NEXT:    [[ADD7:%.*]] = add i64 [[TMP15]], 1
6723 // CHECK17-NEXT:    store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8
6724 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND]]
6725 // CHECK17:       omp.inner.for.end:
6726 // CHECK17-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
6727 // CHECK17:       omp.loop.exit:
6728 // CHECK17-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])
6729 // CHECK17-NEXT:    ret void
6730 //
6731 //
6732 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214
6733 // CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
6734 // CHECK17-NEXT:  entry:
6735 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
6736 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
6737 // CHECK17-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
6738 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
6739 // CHECK17-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
6740 // CHECK17-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
6741 // CHECK17-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
6742 // CHECK17-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
6743 // CHECK17-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
6744 // CHECK17-NEXT:    store i64 [[AAA]], ptr [[AAA_ADDR]], align 8
6745 // CHECK17-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
6746 // CHECK17-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
6747 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
6748 // CHECK17-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 4
6749 // CHECK17-NEXT:    [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8
6750 // CHECK17-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
6751 // CHECK17-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
6752 // CHECK17-NEXT:    [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8
6753 // CHECK17-NEXT:    [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 1
6754 // CHECK17-NEXT:    store i8 [[TMP5]], ptr [[AAA_CASTED]], align 1
6755 // CHECK17-NEXT:    [[TMP6:%.*]] = load i64, ptr [[AAA_CASTED]], align 8
6756 // CHECK17-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], ptr [[TMP0]])
6757 // CHECK17-NEXT:    ret void
6758 //
6759 //
6760 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214.omp_outlined
6761 // CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
6762 // CHECK17-NEXT:  entry:
6763 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
6764 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
6765 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
6766 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
6767 // CHECK17-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
6768 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
6769 // CHECK17-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
6770 // CHECK17-NEXT:    [[TMP:%.*]] = alloca i32, align 4
6771 // CHECK17-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
6772 // CHECK17-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
6773 // CHECK17-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
6774 // CHECK17-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
6775 // CHECK17-NEXT:    store i64 [[AAA]], ptr [[AAA_ADDR]], align 8
6776 // CHECK17-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
6777 // CHECK17-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
6778 // CHECK17-NEXT:    ret void
6779 //
6780 //
6781 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197
6782 // CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
6783 // CHECK17-NEXT:  entry:
6784 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
6785 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
6786 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
6787 // CHECK17-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
6788 // CHECK17-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
6789 // CHECK17-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
6790 // CHECK17-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
6791 // CHECK17-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
6792 // CHECK17-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
6793 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
6794 // CHECK17-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 4
6795 // CHECK17-NEXT:    [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8
6796 // CHECK17-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
6797 // CHECK17-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
6798 // CHECK17-NEXT:    [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8
6799 // CHECK17-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], ptr [[TMP0]])
6800 // CHECK17-NEXT:    ret void
6801 //
6802 //
6803 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197.omp_outlined
6804 // CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
6805 // CHECK17-NEXT:  entry:
6806 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
6807 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
6808 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
6809 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
6810 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
6811 // CHECK17-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
6812 // CHECK17-NEXT:    [[TMP:%.*]] = alloca i64, align 8
6813 // CHECK17-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
6814 // CHECK17-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
6815 // CHECK17-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
6816 // CHECK17-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
6817 // CHECK17-NEXT:    [[I:%.*]] = alloca i64, align 8
6818 // CHECK17-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
6819 // CHECK17-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
6820 // CHECK17-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
6821 // CHECK17-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
6822 // CHECK17-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
6823 // CHECK17-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
6824 // CHECK17-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8
6825 // CHECK17-NEXT:    store i64 6, ptr [[DOTOMP_UB]], align 8
6826 // CHECK17-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8
6827 // CHECK17-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
6828 // CHECK17-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
6829 // CHECK17-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
6830 // CHECK17-NEXT:    call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP2]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
6831 // CHECK17-NEXT:    [[TMP3:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
6832 // CHECK17-NEXT:    [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
6833 // CHECK17-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
6834 // CHECK17:       cond.true:
6835 // CHECK17-NEXT:    br label [[COND_END:%.*]]
6836 // CHECK17:       cond.false:
6837 // CHECK17-NEXT:    [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
6838 // CHECK17-NEXT:    br label [[COND_END]]
6839 // CHECK17:       cond.end:
6840 // CHECK17-NEXT:    [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
6841 // CHECK17-NEXT:    store i64 [[COND]], ptr [[DOTOMP_UB]], align 8
6842 // CHECK17-NEXT:    [[TMP5:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
6843 // CHECK17-NEXT:    store i64 [[TMP5]], ptr [[DOTOMP_IV]], align 8
6844 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
6845 // CHECK17:       omp.inner.for.cond:
6846 // CHECK17-NEXT:    [[TMP6:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
6847 // CHECK17-NEXT:    [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
6848 // CHECK17-NEXT:    [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
6849 // CHECK17-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
6850 // CHECK17:       omp.inner.for.body:
6851 // CHECK17-NEXT:    [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
6852 // CHECK17-NEXT:    [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
6853 // CHECK17-NEXT:    [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
6854 // CHECK17-NEXT:    store i64 [[ADD]], ptr [[I]], align 8
6855 // CHECK17-NEXT:    [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4
6856 // CHECK17-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
6857 // CHECK17-NEXT:    store i32 [[ADD2]], ptr [[A_ADDR]], align 4
6858 // CHECK17-NEXT:    [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2
6859 // CHECK17-NEXT:    [[CONV:%.*]] = sext i16 [[TMP10]] to i32
6860 // CHECK17-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV]], 1
6861 // CHECK17-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
6862 // CHECK17-NEXT:    store i16 [[CONV4]], ptr [[AA_ADDR]], align 2
6863 // CHECK17-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2
6864 // CHECK17-NEXT:    [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
6865 // CHECK17-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1
6866 // CHECK17-NEXT:    store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4
6867 // CHECK17-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
6868 // CHECK17:       omp.body.continue:
6869 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
6870 // CHECK17:       omp.inner.for.inc:
6871 // CHECK17-NEXT:    [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
6872 // CHECK17-NEXT:    [[ADD6:%.*]] = add nsw i64 [[TMP12]], 1
6873 // CHECK17-NEXT:    store i64 [[ADD6]], ptr [[DOTOMP_IV]], align 8
6874 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND]]
6875 // CHECK17:       omp.inner.for.end:
6876 // CHECK17-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
6877 // CHECK17:       omp.loop.exit:
6878 // CHECK17-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])
6879 // CHECK17-NEXT:    ret void
6880 //
6881 //
6882 // CHECK17-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
6883 // CHECK17-SAME: () #[[ATTR5]] {
6884 // CHECK17-NEXT:  entry:
6885 // CHECK17-NEXT:    call void @__tgt_register_requires(i64 1)
6886 // CHECK17-NEXT:    ret void
6887 //
6888 //
6889 // CHECK19-LABEL: define {{[^@]+}}@_Z7get_valv
6890 // CHECK19-SAME: () #[[ATTR0:[0-9]+]] {
6891 // CHECK19-NEXT:  entry:
6892 // CHECK19-NEXT:    ret i64 0
6893 //
6894 //
6895 // CHECK19-LABEL: define {{[^@]+}}@_Z3fooi
6896 // CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
6897 // CHECK19-NEXT:  entry:
6898 // CHECK19-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
6899 // CHECK19-NEXT:    [[A:%.*]] = alloca i32, align 4
6900 // CHECK19-NEXT:    [[AA:%.*]] = alloca i16, align 2
6901 // CHECK19-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
6902 // CHECK19-NEXT:    [[SAVED_STACK:%.*]] = alloca ptr, align 4
6903 // CHECK19-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
6904 // CHECK19-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
6905 // CHECK19-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
6906 // CHECK19-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
6907 // CHECK19-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
6908 // CHECK19-NEXT:    [[K:%.*]] = alloca i64, align 8
6909 // CHECK19-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
6910 // CHECK19-NEXT:    [[LIN:%.*]] = alloca i32, align 4
6911 // CHECK19-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
6912 // CHECK19-NEXT:    [[LIN_CASTED:%.*]] = alloca i32, align 4
6913 // CHECK19-NEXT:    [[A_CASTED2:%.*]] = alloca i32, align 4
6914 // CHECK19-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 4
6915 // CHECK19-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 4
6916 // CHECK19-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 4
6917 // CHECK19-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4
6918 // CHECK19-NEXT:    [[A_CASTED3:%.*]] = alloca i32, align 4
6919 // CHECK19-NEXT:    [[AA_CASTED4:%.*]] = alloca i32, align 4
6920 // CHECK19-NEXT:    [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [2 x ptr], align 4
6921 // CHECK19-NEXT:    [[DOTOFFLOAD_PTRS6:%.*]] = alloca [2 x ptr], align 4
6922 // CHECK19-NEXT:    [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [2 x ptr], align 4
6923 // CHECK19-NEXT:    [[KERNEL_ARGS8:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
6924 // CHECK19-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
6925 // CHECK19-NEXT:    [[A_CASTED11:%.*]] = alloca i32, align 4
6926 // CHECK19-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
6927 // CHECK19-NEXT:    [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [10 x ptr], align 4
6928 // CHECK19-NEXT:    [[DOTOFFLOAD_PTRS15:%.*]] = alloca [10 x ptr], align 4
6929 // CHECK19-NEXT:    [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [10 x ptr], align 4
6930 // CHECK19-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4
6931 // CHECK19-NEXT:    [[KERNEL_ARGS17:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
6932 // CHECK19-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])
6933 // CHECK19-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
6934 // CHECK19-NEXT:    store i32 0, ptr [[A]], align 4
6935 // CHECK19-NEXT:    store i16 0, ptr [[AA]], align 2
6936 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
6937 // CHECK19-NEXT:    [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
6938 // CHECK19-NEXT:    store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4
6939 // CHECK19-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4
6940 // CHECK19-NEXT:    store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4
6941 // CHECK19-NEXT:    [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4
6942 // CHECK19-NEXT:    [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]]
6943 // CHECK19-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8
6944 // CHECK19-NEXT:    store i32 [[TMP3]], ptr [[__VLA_EXPR1]], align 4
6945 // CHECK19-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
6946 // CHECK19-NEXT:    store i32 2, ptr [[TMP5]], align 4
6947 // CHECK19-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
6948 // CHECK19-NEXT:    store i32 0, ptr [[TMP6]], align 4
6949 // CHECK19-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
6950 // CHECK19-NEXT:    store ptr null, ptr [[TMP7]], align 4
6951 // CHECK19-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
6952 // CHECK19-NEXT:    store ptr null, ptr [[TMP8]], align 4
6953 // CHECK19-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
6954 // CHECK19-NEXT:    store ptr null, ptr [[TMP9]], align 4
6955 // CHECK19-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
6956 // CHECK19-NEXT:    store ptr null, ptr [[TMP10]], align 4
6957 // CHECK19-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
6958 // CHECK19-NEXT:    store ptr null, ptr [[TMP11]], align 4
6959 // CHECK19-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
6960 // CHECK19-NEXT:    store ptr null, ptr [[TMP12]], align 4
6961 // CHECK19-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
6962 // CHECK19-NEXT:    store i64 0, ptr [[TMP13]], align 8
6963 // CHECK19-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
6964 // CHECK19-NEXT:    store i64 0, ptr [[TMP14]], align 8
6965 // CHECK19-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
6966 // CHECK19-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP15]], align 4
6967 // CHECK19-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
6968 // CHECK19-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP16]], align 4
6969 // CHECK19-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
6970 // CHECK19-NEXT:    store i32 0, ptr [[TMP17]], align 4
6971 // CHECK19-NEXT:    [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, ptr [[KERNEL_ARGS]])
6972 // CHECK19-NEXT:    [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
6973 // CHECK19-NEXT:    br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
6974 // CHECK19:       omp_offload.failed:
6975 // CHECK19-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR3:[0-9]+]]
6976 // CHECK19-NEXT:    br label [[OMP_OFFLOAD_CONT]]
6977 // CHECK19:       omp_offload.cont:
6978 // CHECK19-NEXT:    [[CALL:%.*]] = call noundef i64 @_Z7get_valv()
6979 // CHECK19-NEXT:    store i64 [[CALL]], ptr [[K]], align 8
6980 // CHECK19-NEXT:    [[TMP20:%.*]] = load i32, ptr [[A]], align 4
6981 // CHECK19-NEXT:    store i32 [[TMP20]], ptr [[A_CASTED]], align 4
6982 // CHECK19-NEXT:    [[TMP21:%.*]] = load i32, ptr [[A_CASTED]], align 4
6983 // CHECK19-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i32 [[TMP21]], ptr [[K]]) #[[ATTR3]]
6984 // CHECK19-NEXT:    store i32 12, ptr [[LIN]], align 4
6985 // CHECK19-NEXT:    [[TMP22:%.*]] = load i16, ptr [[AA]], align 2
6986 // CHECK19-NEXT:    store i16 [[TMP22]], ptr [[AA_CASTED]], align 2
6987 // CHECK19-NEXT:    [[TMP23:%.*]] = load i32, ptr [[AA_CASTED]], align 4
6988 // CHECK19-NEXT:    [[TMP24:%.*]] = load i32, ptr [[LIN]], align 4
6989 // CHECK19-NEXT:    store i32 [[TMP24]], ptr [[LIN_CASTED]], align 4
6990 // CHECK19-NEXT:    [[TMP25:%.*]] = load i32, ptr [[LIN_CASTED]], align 4
6991 // CHECK19-NEXT:    [[TMP26:%.*]] = load i32, ptr [[A]], align 4
6992 // CHECK19-NEXT:    store i32 [[TMP26]], ptr [[A_CASTED2]], align 4
6993 // CHECK19-NEXT:    [[TMP27:%.*]] = load i32, ptr [[A_CASTED2]], align 4
6994 // CHECK19-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
6995 // CHECK19-NEXT:    store i32 [[TMP23]], ptr [[TMP28]], align 4
6996 // CHECK19-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
6997 // CHECK19-NEXT:    store i32 [[TMP23]], ptr [[TMP29]], align 4
6998 // CHECK19-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
6999 // CHECK19-NEXT:    store ptr null, ptr [[TMP30]], align 4
7000 // CHECK19-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
7001 // CHECK19-NEXT:    store i32 [[TMP25]], ptr [[TMP31]], align 4
7002 // CHECK19-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
7003 // CHECK19-NEXT:    store i32 [[TMP25]], ptr [[TMP32]], align 4
7004 // CHECK19-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
7005 // CHECK19-NEXT:    store ptr null, ptr [[TMP33]], align 4
7006 // CHECK19-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
7007 // CHECK19-NEXT:    store i32 [[TMP27]], ptr [[TMP34]], align 4
7008 // CHECK19-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
7009 // CHECK19-NEXT:    store i32 [[TMP27]], ptr [[TMP35]], align 4
7010 // CHECK19-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
7011 // CHECK19-NEXT:    store ptr null, ptr [[TMP36]], align 4
7012 // CHECK19-NEXT:    [[TMP37:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
7013 // CHECK19-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
7014 // CHECK19-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0
7015 // CHECK19-NEXT:    [[TMP40:%.*]] = load i16, ptr [[AA]], align 2
7016 // CHECK19-NEXT:    store i16 [[TMP40]], ptr [[TMP39]], align 4
7017 // CHECK19-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 1
7018 // CHECK19-NEXT:    [[TMP42:%.*]] = load i32, ptr [[LIN]], align 4
7019 // CHECK19-NEXT:    store i32 [[TMP42]], ptr [[TMP41]], align 4
7020 // CHECK19-NEXT:    [[TMP43:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 2
7021 // CHECK19-NEXT:    [[TMP44:%.*]] = load i32, ptr [[A]], align 4
7022 // CHECK19-NEXT:    store i32 [[TMP44]], ptr [[TMP43]], align 4
7023 // CHECK19-NEXT:    [[TMP45:%.*]] = call ptr @__kmpc_omp_target_task_alloc(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 72, i32 12, ptr @.omp_task_entry., i64 -1)
7024 // CHECK19-NEXT:    [[TMP46:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP45]], i32 0, i32 0
7025 // CHECK19-NEXT:    [[TMP47:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP46]], i32 0, i32 0
7026 // CHECK19-NEXT:    [[TMP48:%.*]] = load ptr, ptr [[TMP47]], align 4
7027 // CHECK19-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP48]], ptr align 4 [[AGG_CAPTURED]], i32 12, i1 false)
7028 // CHECK19-NEXT:    [[TMP49:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP45]], i32 0, i32 1
7029 // CHECK19-NEXT:    [[TMP50:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP49]], i32 0, i32 0
7030 // CHECK19-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP50]], ptr align 4 @.offload_sizes, i32 24, i1 false)
7031 // CHECK19-NEXT:    [[TMP51:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP49]], i32 0, i32 1
7032 // CHECK19-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP51]], ptr align 4 [[TMP37]], i32 12, i1 false)
7033 // CHECK19-NEXT:    [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP49]], i32 0, i32 2
7034 // CHECK19-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP52]], ptr align 4 [[TMP38]], i32 12, i1 false)
7035 // CHECK19-NEXT:    [[TMP53:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP49]], i32 0, i32 3
7036 // CHECK19-NEXT:    [[TMP54:%.*]] = load i16, ptr [[AA]], align 2
7037 // CHECK19-NEXT:    store i16 [[TMP54]], ptr [[TMP53]], align 4
7038 // CHECK19-NEXT:    [[TMP55:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB2]], i32 [[TMP0]], ptr [[TMP45]])
7039 // CHECK19-NEXT:    [[TMP56:%.*]] = load i32, ptr [[A]], align 4
7040 // CHECK19-NEXT:    store i32 [[TMP56]], ptr [[A_CASTED3]], align 4
7041 // CHECK19-NEXT:    [[TMP57:%.*]] = load i32, ptr [[A_CASTED3]], align 4
7042 // CHECK19-NEXT:    [[TMP58:%.*]] = load i16, ptr [[AA]], align 2
7043 // CHECK19-NEXT:    store i16 [[TMP58]], ptr [[AA_CASTED4]], align 2
7044 // CHECK19-NEXT:    [[TMP59:%.*]] = load i32, ptr [[AA_CASTED4]], align 4
7045 // CHECK19-NEXT:    [[TMP60:%.*]] = load i32, ptr [[N_ADDR]], align 4
7046 // CHECK19-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP60]], 10
7047 // CHECK19-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
7048 // CHECK19:       omp_if.then:
7049 // CHECK19-NEXT:    [[TMP61:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0
7050 // CHECK19-NEXT:    store i32 [[TMP57]], ptr [[TMP61]], align 4
7051 // CHECK19-NEXT:    [[TMP62:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0
7052 // CHECK19-NEXT:    store i32 [[TMP57]], ptr [[TMP62]], align 4
7053 // CHECK19-NEXT:    [[TMP63:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 0
7054 // CHECK19-NEXT:    store ptr null, ptr [[TMP63]], align 4
7055 // CHECK19-NEXT:    [[TMP64:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1
7056 // CHECK19-NEXT:    store i32 [[TMP59]], ptr [[TMP64]], align 4
7057 // CHECK19-NEXT:    [[TMP65:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 1
7058 // CHECK19-NEXT:    store i32 [[TMP59]], ptr [[TMP65]], align 4
7059 // CHECK19-NEXT:    [[TMP66:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 1
7060 // CHECK19-NEXT:    store ptr null, ptr [[TMP66]], align 4
7061 // CHECK19-NEXT:    [[TMP67:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0
7062 // CHECK19-NEXT:    [[TMP68:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0
7063 // CHECK19-NEXT:    [[TMP69:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 0
7064 // CHECK19-NEXT:    store i32 2, ptr [[TMP69]], align 4
7065 // CHECK19-NEXT:    [[TMP70:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 1
7066 // CHECK19-NEXT:    store i32 2, ptr [[TMP70]], align 4
7067 // CHECK19-NEXT:    [[TMP71:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 2
7068 // CHECK19-NEXT:    store ptr [[TMP67]], ptr [[TMP71]], align 4
7069 // CHECK19-NEXT:    [[TMP72:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 3
7070 // CHECK19-NEXT:    store ptr [[TMP68]], ptr [[TMP72]], align 4
7071 // CHECK19-NEXT:    [[TMP73:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 4
7072 // CHECK19-NEXT:    store ptr @.offload_sizes.1, ptr [[TMP73]], align 4
7073 // CHECK19-NEXT:    [[TMP74:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 5
7074 // CHECK19-NEXT:    store ptr @.offload_maptypes.2, ptr [[TMP74]], align 4
7075 // CHECK19-NEXT:    [[TMP75:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 6
7076 // CHECK19-NEXT:    store ptr null, ptr [[TMP75]], align 4
7077 // CHECK19-NEXT:    [[TMP76:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 7
7078 // CHECK19-NEXT:    store ptr null, ptr [[TMP76]], align 4
7079 // CHECK19-NEXT:    [[TMP77:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 8
7080 // CHECK19-NEXT:    store i64 0, ptr [[TMP77]], align 8
7081 // CHECK19-NEXT:    [[TMP78:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 9
7082 // CHECK19-NEXT:    store i64 0, ptr [[TMP78]], align 8
7083 // CHECK19-NEXT:    [[TMP79:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 10
7084 // CHECK19-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP79]], align 4
7085 // CHECK19-NEXT:    [[TMP80:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 11
7086 // CHECK19-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP80]], align 4
7087 // CHECK19-NEXT:    [[TMP81:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 12
7088 // CHECK19-NEXT:    store i32 0, ptr [[TMP81]], align 4
7089 // CHECK19-NEXT:    [[TMP82:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.region_id, ptr [[KERNEL_ARGS8]])
7090 // CHECK19-NEXT:    [[TMP83:%.*]] = icmp ne i32 [[TMP82]], 0
7091 // CHECK19-NEXT:    br i1 [[TMP83]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]]
7092 // CHECK19:       omp_offload.failed9:
7093 // CHECK19-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136(i32 [[TMP57]], i32 [[TMP59]]) #[[ATTR3]]
7094 // CHECK19-NEXT:    br label [[OMP_OFFLOAD_CONT10]]
7095 // CHECK19:       omp_offload.cont10:
7096 // CHECK19-NEXT:    br label [[OMP_IF_END:%.*]]
7097 // CHECK19:       omp_if.else:
7098 // CHECK19-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136(i32 [[TMP57]], i32 [[TMP59]]) #[[ATTR3]]
7099 // CHECK19-NEXT:    br label [[OMP_IF_END]]
7100 // CHECK19:       omp_if.end:
7101 // CHECK19-NEXT:    [[TMP84:%.*]] = load i32, ptr [[A]], align 4
7102 // CHECK19-NEXT:    store i32 [[TMP84]], ptr [[DOTCAPTURE_EXPR_]], align 4
7103 // CHECK19-NEXT:    [[TMP85:%.*]] = load i32, ptr [[A]], align 4
7104 // CHECK19-NEXT:    store i32 [[TMP85]], ptr [[A_CASTED11]], align 4
7105 // CHECK19-NEXT:    [[TMP86:%.*]] = load i32, ptr [[A_CASTED11]], align 4
7106 // CHECK19-NEXT:    [[TMP87:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
7107 // CHECK19-NEXT:    store i32 [[TMP87]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
7108 // CHECK19-NEXT:    [[TMP88:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
7109 // CHECK19-NEXT:    [[TMP89:%.*]] = load i32, ptr [[N_ADDR]], align 4
7110 // CHECK19-NEXT:    [[CMP12:%.*]] = icmp sgt i32 [[TMP89]], 20
7111 // CHECK19-NEXT:    br i1 [[CMP12]], label [[OMP_IF_THEN13:%.*]], label [[OMP_IF_ELSE20:%.*]]
7112 // CHECK19:       omp_if.then13:
7113 // CHECK19-NEXT:    [[TMP90:%.*]] = mul nuw i32 [[TMP1]], 4
7114 // CHECK19-NEXT:    [[TMP91:%.*]] = sext i32 [[TMP90]] to i64
7115 // CHECK19-NEXT:    [[TMP92:%.*]] = mul nuw i32 5, [[TMP3]]
7116 // CHECK19-NEXT:    [[TMP93:%.*]] = mul nuw i32 [[TMP92]], 8
7117 // CHECK19-NEXT:    [[TMP94:%.*]] = sext i32 [[TMP93]] to i64
7118 // CHECK19-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes.3, i32 80, i1 false)
7119 // CHECK19-NEXT:    [[TMP95:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0
7120 // CHECK19-NEXT:    store i32 [[TMP86]], ptr [[TMP95]], align 4
7121 // CHECK19-NEXT:    [[TMP96:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 0
7122 // CHECK19-NEXT:    store i32 [[TMP86]], ptr [[TMP96]], align 4
7123 // CHECK19-NEXT:    [[TMP97:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 0
7124 // CHECK19-NEXT:    store ptr null, ptr [[TMP97]], align 4
7125 // CHECK19-NEXT:    [[TMP98:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 1
7126 // CHECK19-NEXT:    store ptr [[B]], ptr [[TMP98]], align 4
7127 // CHECK19-NEXT:    [[TMP99:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 1
7128 // CHECK19-NEXT:    store ptr [[B]], ptr [[TMP99]], align 4
7129 // CHECK19-NEXT:    [[TMP100:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 1
7130 // CHECK19-NEXT:    store ptr null, ptr [[TMP100]], align 4
7131 // CHECK19-NEXT:    [[TMP101:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 2
7132 // CHECK19-NEXT:    store i32 [[TMP1]], ptr [[TMP101]], align 4
7133 // CHECK19-NEXT:    [[TMP102:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 2
7134 // CHECK19-NEXT:    store i32 [[TMP1]], ptr [[TMP102]], align 4
7135 // CHECK19-NEXT:    [[TMP103:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 2
7136 // CHECK19-NEXT:    store ptr null, ptr [[TMP103]], align 4
7137 // CHECK19-NEXT:    [[TMP104:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 3
7138 // CHECK19-NEXT:    store ptr [[VLA]], ptr [[TMP104]], align 4
7139 // CHECK19-NEXT:    [[TMP105:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 3
7140 // CHECK19-NEXT:    store ptr [[VLA]], ptr [[TMP105]], align 4
7141 // CHECK19-NEXT:    [[TMP106:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 3
7142 // CHECK19-NEXT:    store i64 [[TMP91]], ptr [[TMP106]], align 4
7143 // CHECK19-NEXT:    [[TMP107:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 3
7144 // CHECK19-NEXT:    store ptr null, ptr [[TMP107]], align 4
7145 // CHECK19-NEXT:    [[TMP108:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 4
7146 // CHECK19-NEXT:    store ptr [[C]], ptr [[TMP108]], align 4
7147 // CHECK19-NEXT:    [[TMP109:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 4
7148 // CHECK19-NEXT:    store ptr [[C]], ptr [[TMP109]], align 4
7149 // CHECK19-NEXT:    [[TMP110:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 4
7150 // CHECK19-NEXT:    store ptr null, ptr [[TMP110]], align 4
7151 // CHECK19-NEXT:    [[TMP111:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 5
7152 // CHECK19-NEXT:    store i32 5, ptr [[TMP111]], align 4
7153 // CHECK19-NEXT:    [[TMP112:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 5
7154 // CHECK19-NEXT:    store i32 5, ptr [[TMP112]], align 4
7155 // CHECK19-NEXT:    [[TMP113:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 5
7156 // CHECK19-NEXT:    store ptr null, ptr [[TMP113]], align 4
7157 // CHECK19-NEXT:    [[TMP114:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 6
7158 // CHECK19-NEXT:    store i32 [[TMP3]], ptr [[TMP114]], align 4
7159 // CHECK19-NEXT:    [[TMP115:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 6
7160 // CHECK19-NEXT:    store i32 [[TMP3]], ptr [[TMP115]], align 4
7161 // CHECK19-NEXT:    [[TMP116:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 6
7162 // CHECK19-NEXT:    store ptr null, ptr [[TMP116]], align 4
7163 // CHECK19-NEXT:    [[TMP117:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 7
7164 // CHECK19-NEXT:    store ptr [[VLA1]], ptr [[TMP117]], align 4
7165 // CHECK19-NEXT:    [[TMP118:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 7
7166 // CHECK19-NEXT:    store ptr [[VLA1]], ptr [[TMP118]], align 4
7167 // CHECK19-NEXT:    [[TMP119:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 7
7168 // CHECK19-NEXT:    store i64 [[TMP94]], ptr [[TMP119]], align 4
7169 // CHECK19-NEXT:    [[TMP120:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 7
7170 // CHECK19-NEXT:    store ptr null, ptr [[TMP120]], align 4
7171 // CHECK19-NEXT:    [[TMP121:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 8
7172 // CHECK19-NEXT:    store ptr [[D]], ptr [[TMP121]], align 4
7173 // CHECK19-NEXT:    [[TMP122:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 8
7174 // CHECK19-NEXT:    store ptr [[D]], ptr [[TMP122]], align 4
7175 // CHECK19-NEXT:    [[TMP123:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 8
7176 // CHECK19-NEXT:    store ptr null, ptr [[TMP123]], align 4
7177 // CHECK19-NEXT:    [[TMP124:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 9
7178 // CHECK19-NEXT:    store i32 [[TMP88]], ptr [[TMP124]], align 4
7179 // CHECK19-NEXT:    [[TMP125:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 9
7180 // CHECK19-NEXT:    store i32 [[TMP88]], ptr [[TMP125]], align 4
7181 // CHECK19-NEXT:    [[TMP126:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 9
7182 // CHECK19-NEXT:    store ptr null, ptr [[TMP126]], align 4
7183 // CHECK19-NEXT:    [[TMP127:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0
7184 // CHECK19-NEXT:    [[TMP128:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 0
7185 // CHECK19-NEXT:    [[TMP129:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0
7186 // CHECK19-NEXT:    [[TMP130:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 0
7187 // CHECK19-NEXT:    store i32 2, ptr [[TMP130]], align 4
7188 // CHECK19-NEXT:    [[TMP131:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 1
7189 // CHECK19-NEXT:    store i32 10, ptr [[TMP131]], align 4
7190 // CHECK19-NEXT:    [[TMP132:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 2
7191 // CHECK19-NEXT:    store ptr [[TMP127]], ptr [[TMP132]], align 4
7192 // CHECK19-NEXT:    [[TMP133:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 3
7193 // CHECK19-NEXT:    store ptr [[TMP128]], ptr [[TMP133]], align 4
7194 // CHECK19-NEXT:    [[TMP134:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 4
7195 // CHECK19-NEXT:    store ptr [[TMP129]], ptr [[TMP134]], align 4
7196 // CHECK19-NEXT:    [[TMP135:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 5
7197 // CHECK19-NEXT:    store ptr @.offload_maptypes.4, ptr [[TMP135]], align 4
7198 // CHECK19-NEXT:    [[TMP136:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 6
7199 // CHECK19-NEXT:    store ptr null, ptr [[TMP136]], align 4
7200 // CHECK19-NEXT:    [[TMP137:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 7
7201 // CHECK19-NEXT:    store ptr null, ptr [[TMP137]], align 4
7202 // CHECK19-NEXT:    [[TMP138:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 8
7203 // CHECK19-NEXT:    store i64 0, ptr [[TMP138]], align 8
7204 // CHECK19-NEXT:    [[TMP139:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 9
7205 // CHECK19-NEXT:    store i64 0, ptr [[TMP139]], align 8
7206 // CHECK19-NEXT:    [[TMP140:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 10
7207 // CHECK19-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP140]], align 4
7208 // CHECK19-NEXT:    [[TMP141:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 11
7209 // CHECK19-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP141]], align 4
7210 // CHECK19-NEXT:    [[TMP142:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 12
7211 // CHECK19-NEXT:    store i32 0, ptr [[TMP142]], align 4
7212 // CHECK19-NEXT:    [[TMP143:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.region_id, ptr [[KERNEL_ARGS17]])
7213 // CHECK19-NEXT:    [[TMP144:%.*]] = icmp ne i32 [[TMP143]], 0
7214 // CHECK19-NEXT:    br i1 [[TMP144]], label [[OMP_OFFLOAD_FAILED18:%.*]], label [[OMP_OFFLOAD_CONT19:%.*]]
7215 // CHECK19:       omp_offload.failed18:
7216 // CHECK19-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160(i32 [[TMP86]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]], i32 [[TMP88]]) #[[ATTR3]]
7217 // CHECK19-NEXT:    br label [[OMP_OFFLOAD_CONT19]]
7218 // CHECK19:       omp_offload.cont19:
7219 // CHECK19-NEXT:    br label [[OMP_IF_END21:%.*]]
7220 // CHECK19:       omp_if.else20:
7221 // CHECK19-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160(i32 [[TMP86]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]], i32 [[TMP88]]) #[[ATTR3]]
7222 // CHECK19-NEXT:    br label [[OMP_IF_END21]]
7223 // CHECK19:       omp_if.end21:
7224 // CHECK19-NEXT:    [[TMP145:%.*]] = load i32, ptr [[A]], align 4
7225 // CHECK19-NEXT:    [[TMP146:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
7226 // CHECK19-NEXT:    call void @llvm.stackrestore.p0(ptr [[TMP146]])
7227 // CHECK19-NEXT:    ret i32 [[TMP145]]
7228 //
7229 //
7230 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
7231 // CHECK19-SAME: () #[[ATTR2:[0-9]+]] {
7232 // CHECK19-NEXT:  entry:
7233 // CHECK19-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined)
7234 // CHECK19-NEXT:    ret void
7235 //
7236 //
7237 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined
7238 // CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] {
7239 // CHECK19-NEXT:  entry:
7240 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
7241 // CHECK19-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
7242 // CHECK19-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
7243 // CHECK19-NEXT:    [[TMP:%.*]] = alloca i32, align 4
7244 // CHECK19-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
7245 // CHECK19-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
7246 // CHECK19-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
7247 // CHECK19-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
7248 // CHECK19-NEXT:    [[I:%.*]] = alloca i32, align 4
7249 // CHECK19-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
7250 // CHECK19-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
7251 // CHECK19-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
7252 // CHECK19-NEXT:    store i32 5, ptr [[DOTOMP_UB]], align 4
7253 // CHECK19-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
7254 // CHECK19-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
7255 // CHECK19-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
7256 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
7257 // CHECK19-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
7258 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
7259 // CHECK19-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
7260 // CHECK19-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
7261 // CHECK19:       cond.true:
7262 // CHECK19-NEXT:    br label [[COND_END:%.*]]
7263 // CHECK19:       cond.false:
7264 // CHECK19-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
7265 // CHECK19-NEXT:    br label [[COND_END]]
7266 // CHECK19:       cond.end:
7267 // CHECK19-NEXT:    [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
7268 // CHECK19-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
7269 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
7270 // CHECK19-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
7271 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
7272 // CHECK19:       omp.inner.for.cond:
7273 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
7274 // CHECK19-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
7275 // CHECK19-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
7276 // CHECK19-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
7277 // CHECK19:       omp.inner.for.body:
7278 // CHECK19-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
7279 // CHECK19-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
7280 // CHECK19-NEXT:    [[ADD:%.*]] = add nsw i32 3, [[MUL]]
7281 // CHECK19-NEXT:    store i32 [[ADD]], ptr [[I]], align 4
7282 // CHECK19-NEXT:    [[TMP8:%.*]] = call i32 @__kmpc_cancel(ptr @[[GLOB2]], i32 [[TMP1]], i32 2)
7283 // CHECK19-NEXT:    [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0
7284 // CHECK19-NEXT:    br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
7285 // CHECK19:       .cancel.exit:
7286 // CHECK19-NEXT:    br label [[CANCEL_EXIT:%.*]]
7287 // CHECK19:       .cancel.continue:
7288 // CHECK19-NEXT:    [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(ptr @[[GLOB2]], i32 [[TMP1]], i32 2)
7289 // CHECK19-NEXT:    [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
7290 // CHECK19-NEXT:    br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]]
7291 // CHECK19:       .cancel.exit2:
7292 // CHECK19-NEXT:    br label [[CANCEL_EXIT]]
7293 // CHECK19:       .cancel.continue3:
7294 // CHECK19-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
7295 // CHECK19:       omp.body.continue:
7296 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
7297 // CHECK19:       omp.inner.for.inc:
7298 // CHECK19-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
7299 // CHECK19-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
7300 // CHECK19-NEXT:    store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4
7301 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND]]
7302 // CHECK19:       omp.inner.for.end:
7303 // CHECK19-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
7304 // CHECK19:       omp.loop.exit:
7305 // CHECK19-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
7306 // CHECK19-NEXT:    br label [[CANCEL_CONT:%.*]]
7307 // CHECK19:       cancel.cont:
7308 // CHECK19-NEXT:    ret void
7309 // CHECK19:       cancel.exit:
7310 // CHECK19-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
7311 // CHECK19-NEXT:    br label [[CANCEL_CONT]]
7312 //
7313 //
7314 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110
7315 // CHECK19-SAME: (i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR2]] {
7316 // CHECK19-NEXT:  entry:
7317 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
7318 // CHECK19-NEXT:    [[K_ADDR:%.*]] = alloca ptr, align 4
7319 // CHECK19-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
7320 // CHECK19-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
7321 // CHECK19-NEXT:    store ptr [[K]], ptr [[K_ADDR]], align 4
7322 // CHECK19-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[K_ADDR]], align 4
7323 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
7324 // CHECK19-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 4
7325 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4
7326 // CHECK19-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.omp_outlined, i32 [[TMP2]], ptr [[TMP0]])
7327 // CHECK19-NEXT:    ret void
7328 //
7329 //
7330 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.omp_outlined
7331 // CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR2]] {
7332 // CHECK19-NEXT:  entry:
7333 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
7334 // CHECK19-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
7335 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
7336 // CHECK19-NEXT:    [[K_ADDR:%.*]] = alloca ptr, align 4
7337 // CHECK19-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
7338 // CHECK19-NEXT:    [[TMP:%.*]] = alloca i32, align 4
7339 // CHECK19-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i64, align 8
7340 // CHECK19-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
7341 // CHECK19-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
7342 // CHECK19-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
7343 // CHECK19-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
7344 // CHECK19-NEXT:    [[I:%.*]] = alloca i32, align 4
7345 // CHECK19-NEXT:    [[K1:%.*]] = alloca i64, align 8
7346 // CHECK19-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
7347 // CHECK19-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
7348 // CHECK19-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
7349 // CHECK19-NEXT:    store ptr [[K]], ptr [[K_ADDR]], align 4
7350 // CHECK19-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[K_ADDR]], align 4
7351 // CHECK19-NEXT:    [[TMP1:%.*]] = load i64, ptr [[TMP0]], align 8
7352 // CHECK19-NEXT:    store i64 [[TMP1]], ptr [[DOTLINEAR_START]], align 8
7353 // CHECK19-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
7354 // CHECK19-NEXT:    store i32 8, ptr [[DOTOMP_UB]], align 4
7355 // CHECK19-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
7356 // CHECK19-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
7357 // CHECK19-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
7358 // CHECK19-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
7359 // CHECK19-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP3]])
7360 // CHECK19-NEXT:    call void @__kmpc_dispatch_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 1073741859, i32 0, i32 8, i32 1, i32 1)
7361 // CHECK19-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
7362 // CHECK19:       omp.dispatch.cond:
7363 // CHECK19-NEXT:    [[TMP4:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB2]], i32 [[TMP3]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
7364 // CHECK19-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0
7365 // CHECK19-NEXT:    br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
7366 // CHECK19:       omp.dispatch.body:
7367 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
7368 // CHECK19-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
7369 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
7370 // CHECK19:       omp.inner.for.cond:
7371 // CHECK19-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13:![0-9]+]]
7372 // CHECK19-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP13]]
7373 // CHECK19-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
7374 // CHECK19-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
7375 // CHECK19:       omp.inner.for.body:
7376 // CHECK19-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]]
7377 // CHECK19-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
7378 // CHECK19-NEXT:    [[SUB:%.*]] = sub nsw i32 10, [[MUL]]
7379 // CHECK19-NEXT:    store i32 [[SUB]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]]
7380 // CHECK19-NEXT:    [[TMP9:%.*]] = load i64, ptr [[DOTLINEAR_START]], align 8, !llvm.access.group [[ACC_GRP13]]
7381 // CHECK19-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]]
7382 // CHECK19-NEXT:    [[MUL2:%.*]] = mul nsw i32 [[TMP10]], 3
7383 // CHECK19-NEXT:    [[CONV:%.*]] = sext i32 [[MUL2]] to i64
7384 // CHECK19-NEXT:    [[ADD:%.*]] = add nsw i64 [[TMP9]], [[CONV]]
7385 // CHECK19-NEXT:    store i64 [[ADD]], ptr [[K1]], align 8, !llvm.access.group [[ACC_GRP13]]
7386 // CHECK19-NEXT:    [[TMP11:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP13]]
7387 // CHECK19-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP11]], 1
7388 // CHECK19-NEXT:    store i32 [[ADD3]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP13]]
7389 // CHECK19-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
7390 // CHECK19:       omp.body.continue:
7391 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
7392 // CHECK19:       omp.inner.for.inc:
7393 // CHECK19-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]]
7394 // CHECK19-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
7395 // CHECK19-NEXT:    store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]]
7396 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
7397 // CHECK19:       omp.inner.for.end:
7398 // CHECK19-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
7399 // CHECK19:       omp.dispatch.inc:
7400 // CHECK19-NEXT:    br label [[OMP_DISPATCH_COND]]
7401 // CHECK19:       omp.dispatch.end:
7402 // CHECK19-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
7403 // CHECK19-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
7404 // CHECK19-NEXT:    br i1 [[TMP14]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
7405 // CHECK19:       .omp.linear.pu:
7406 // CHECK19-NEXT:    [[TMP15:%.*]] = load i64, ptr [[K1]], align 8
7407 // CHECK19-NEXT:    store i64 [[TMP15]], ptr [[TMP0]], align 8
7408 // CHECK19-NEXT:    br label [[DOTOMP_LINEAR_PU_DONE]]
7409 // CHECK19:       .omp.linear.pu.done:
7410 // CHECK19-NEXT:    ret void
7411 //
7412 //
7413 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128
7414 // CHECK19-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] {
7415 // CHECK19-NEXT:  entry:
7416 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
7417 // CHECK19-NEXT:    [[LIN_ADDR:%.*]] = alloca i32, align 4
7418 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
7419 // CHECK19-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
7420 // CHECK19-NEXT:    [[LIN_CASTED:%.*]] = alloca i32, align 4
7421 // CHECK19-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
7422 // CHECK19-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
7423 // CHECK19-NEXT:    store i32 [[LIN]], ptr [[LIN_ADDR]], align 4
7424 // CHECK19-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
7425 // CHECK19-NEXT:    [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2
7426 // CHECK19-NEXT:    store i16 [[TMP0]], ptr [[AA_CASTED]], align 2
7427 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, ptr [[AA_CASTED]], align 4
7428 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, ptr [[LIN_ADDR]], align 4
7429 // CHECK19-NEXT:    store i32 [[TMP2]], ptr [[LIN_CASTED]], align 4
7430 // CHECK19-NEXT:    [[TMP3:%.*]] = load i32, ptr [[LIN_CASTED]], align 4
7431 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4
7432 // CHECK19-NEXT:    store i32 [[TMP4]], ptr [[A_CASTED]], align 4
7433 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, ptr [[A_CASTED]], align 4
7434 // CHECK19-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128.omp_outlined, i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]])
7435 // CHECK19-NEXT:    ret void
7436 //
7437 //
7438 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128.omp_outlined
7439 // CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] {
7440 // CHECK19-NEXT:  entry:
7441 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
7442 // CHECK19-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
7443 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
7444 // CHECK19-NEXT:    [[LIN_ADDR:%.*]] = alloca i32, align 4
7445 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
7446 // CHECK19-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
7447 // CHECK19-NEXT:    [[TMP:%.*]] = alloca i64, align 4
7448 // CHECK19-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i32, align 4
7449 // CHECK19-NEXT:    [[DOTLINEAR_START1:%.*]] = alloca i32, align 4
7450 // CHECK19-NEXT:    [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
7451 // CHECK19-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
7452 // CHECK19-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
7453 // CHECK19-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
7454 // CHECK19-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
7455 // CHECK19-NEXT:    [[IT:%.*]] = alloca i64, align 8
7456 // CHECK19-NEXT:    [[LIN2:%.*]] = alloca i32, align 4
7457 // CHECK19-NEXT:    [[A3:%.*]] = alloca i32, align 4
7458 // CHECK19-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
7459 // CHECK19-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
7460 // CHECK19-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
7461 // CHECK19-NEXT:    store i32 [[LIN]], ptr [[LIN_ADDR]], align 4
7462 // CHECK19-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
7463 // CHECK19-NEXT:    [[TMP0:%.*]] = load i32, ptr [[LIN_ADDR]], align 4
7464 // CHECK19-NEXT:    store i32 [[TMP0]], ptr [[DOTLINEAR_START]], align 4
7465 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
7466 // CHECK19-NEXT:    store i32 [[TMP1]], ptr [[DOTLINEAR_START1]], align 4
7467 // CHECK19-NEXT:    [[CALL:%.*]] = call noundef i64 @_Z7get_valv()
7468 // CHECK19-NEXT:    store i64 [[CALL]], ptr [[DOTLINEAR_STEP]], align 8
7469 // CHECK19-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8
7470 // CHECK19-NEXT:    store i64 3, ptr [[DOTOMP_UB]], align 8
7471 // CHECK19-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8
7472 // CHECK19-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
7473 // CHECK19-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
7474 // CHECK19-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
7475 // CHECK19-NEXT:    call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP3]])
7476 // CHECK19-NEXT:    call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
7477 // CHECK19-NEXT:    [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
7478 // CHECK19-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
7479 // CHECK19-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
7480 // CHECK19:       cond.true:
7481 // CHECK19-NEXT:    br label [[COND_END:%.*]]
7482 // CHECK19:       cond.false:
7483 // CHECK19-NEXT:    [[TMP5:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
7484 // CHECK19-NEXT:    br label [[COND_END]]
7485 // CHECK19:       cond.end:
7486 // CHECK19-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
7487 // CHECK19-NEXT:    store i64 [[COND]], ptr [[DOTOMP_UB]], align 8
7488 // CHECK19-NEXT:    [[TMP6:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
7489 // CHECK19-NEXT:    store i64 [[TMP6]], ptr [[DOTOMP_IV]], align 8
7490 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
7491 // CHECK19:       omp.inner.for.cond:
7492 // CHECK19-NEXT:    [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
7493 // CHECK19-NEXT:    [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
7494 // CHECK19-NEXT:    [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
7495 // CHECK19-NEXT:    br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
7496 // CHECK19:       omp.inner.for.body:
7497 // CHECK19-NEXT:    [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
7498 // CHECK19-NEXT:    [[MUL:%.*]] = mul i64 [[TMP9]], 400
7499 // CHECK19-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
7500 // CHECK19-NEXT:    store i64 [[SUB]], ptr [[IT]], align 8
7501 // CHECK19-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTLINEAR_START]], align 4
7502 // CHECK19-NEXT:    [[CONV:%.*]] = sext i32 [[TMP10]] to i64
7503 // CHECK19-NEXT:    [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
7504 // CHECK19-NEXT:    [[TMP12:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8
7505 // CHECK19-NEXT:    [[MUL5:%.*]] = mul i64 [[TMP11]], [[TMP12]]
7506 // CHECK19-NEXT:    [[ADD:%.*]] = add i64 [[CONV]], [[MUL5]]
7507 // CHECK19-NEXT:    [[CONV6:%.*]] = trunc i64 [[ADD]] to i32
7508 // CHECK19-NEXT:    store i32 [[CONV6]], ptr [[LIN2]], align 4
7509 // CHECK19-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTLINEAR_START1]], align 4
7510 // CHECK19-NEXT:    [[CONV7:%.*]] = sext i32 [[TMP13]] to i64
7511 // CHECK19-NEXT:    [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
7512 // CHECK19-NEXT:    [[TMP15:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8
7513 // CHECK19-NEXT:    [[MUL8:%.*]] = mul i64 [[TMP14]], [[TMP15]]
7514 // CHECK19-NEXT:    [[ADD9:%.*]] = add i64 [[CONV7]], [[MUL8]]
7515 // CHECK19-NEXT:    [[CONV10:%.*]] = trunc i64 [[ADD9]] to i32
7516 // CHECK19-NEXT:    store i32 [[CONV10]], ptr [[A3]], align 4
7517 // CHECK19-NEXT:    [[TMP16:%.*]] = load i16, ptr [[AA_ADDR]], align 2
7518 // CHECK19-NEXT:    [[CONV11:%.*]] = sext i16 [[TMP16]] to i32
7519 // CHECK19-NEXT:    [[ADD12:%.*]] = add nsw i32 [[CONV11]], 1
7520 // CHECK19-NEXT:    [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16
7521 // CHECK19-NEXT:    store i16 [[CONV13]], ptr [[AA_ADDR]], align 2
7522 // CHECK19-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
7523 // CHECK19:       omp.body.continue:
7524 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
7525 // CHECK19:       omp.inner.for.inc:
7526 // CHECK19-NEXT:    [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
7527 // CHECK19-NEXT:    [[ADD14:%.*]] = add i64 [[TMP17]], 1
7528 // CHECK19-NEXT:    store i64 [[ADD14]], ptr [[DOTOMP_IV]], align 8
7529 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND]]
7530 // CHECK19:       omp.inner.for.end:
7531 // CHECK19-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
7532 // CHECK19:       omp.loop.exit:
7533 // CHECK19-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]])
7534 // CHECK19-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
7535 // CHECK19-NEXT:    [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
7536 // CHECK19-NEXT:    br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
7537 // CHECK19:       .omp.linear.pu:
7538 // CHECK19-NEXT:    [[TMP20:%.*]] = load i32, ptr [[LIN2]], align 4
7539 // CHECK19-NEXT:    store i32 [[TMP20]], ptr [[LIN_ADDR]], align 4
7540 // CHECK19-NEXT:    [[TMP21:%.*]] = load i32, ptr [[A3]], align 4
7541 // CHECK19-NEXT:    store i32 [[TMP21]], ptr [[A_ADDR]], align 4
7542 // CHECK19-NEXT:    br label [[DOTOMP_LINEAR_PU_DONE]]
7543 // CHECK19:       .omp.linear.pu.done:
7544 // CHECK19-NEXT:    ret void
7545 //
7546 //
7547 // CHECK19-LABEL: define {{[^@]+}}@.omp_task_privates_map.
7548 // CHECK19-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]], ptr noalias noundef [[TMP3:%.*]], ptr noalias noundef [[TMP4:%.*]]) #[[ATTR5:[0-9]+]] {
7549 // CHECK19-NEXT:  entry:
7550 // CHECK19-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 4
7551 // CHECK19-NEXT:    [[DOTADDR1:%.*]] = alloca ptr, align 4
7552 // CHECK19-NEXT:    [[DOTADDR2:%.*]] = alloca ptr, align 4
7553 // CHECK19-NEXT:    [[DOTADDR3:%.*]] = alloca ptr, align 4
7554 // CHECK19-NEXT:    [[DOTADDR4:%.*]] = alloca ptr, align 4
7555 // CHECK19-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 4
7556 // CHECK19-NEXT:    store ptr [[TMP1]], ptr [[DOTADDR1]], align 4
7557 // CHECK19-NEXT:    store ptr [[TMP2]], ptr [[DOTADDR2]], align 4
7558 // CHECK19-NEXT:    store ptr [[TMP3]], ptr [[DOTADDR3]], align 4
7559 // CHECK19-NEXT:    store ptr [[TMP4]], ptr [[DOTADDR4]], align 4
7560 // CHECK19-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[DOTADDR]], align 4
7561 // CHECK19-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP5]], i32 0, i32 0
7562 // CHECK19-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[DOTADDR4]], align 4
7563 // CHECK19-NEXT:    store ptr [[TMP6]], ptr [[TMP7]], align 4
7564 // CHECK19-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 1
7565 // CHECK19-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[DOTADDR2]], align 4
7566 // CHECK19-NEXT:    store ptr [[TMP8]], ptr [[TMP9]], align 4
7567 // CHECK19-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 2
7568 // CHECK19-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[DOTADDR3]], align 4
7569 // CHECK19-NEXT:    store ptr [[TMP10]], ptr [[TMP11]], align 4
7570 // CHECK19-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 3
7571 // CHECK19-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[DOTADDR1]], align 4
7572 // CHECK19-NEXT:    store ptr [[TMP12]], ptr [[TMP13]], align 4
7573 // CHECK19-NEXT:    ret void
7574 //
7575 //
7576 // CHECK19-LABEL: define {{[^@]+}}@.omp_task_entry.
7577 // CHECK19-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] {
7578 // CHECK19-NEXT:  entry:
7579 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
7580 // CHECK19-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 4
7581 // CHECK19-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 4
7582 // CHECK19-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 4
7583 // CHECK19-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 4
7584 // CHECK19-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 4
7585 // CHECK19-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca ptr, align 4
7586 // CHECK19-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca ptr, align 4
7587 // CHECK19-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca ptr, align 4
7588 // CHECK19-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca ptr, align 4
7589 // CHECK19-NEXT:    [[KERNEL_ARGS_I:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
7590 // CHECK19-NEXT:    [[AA_CASTED_I:%.*]] = alloca i32, align 4
7591 // CHECK19-NEXT:    [[LIN_CASTED_I:%.*]] = alloca i32, align 4
7592 // CHECK19-NEXT:    [[A_CASTED_I:%.*]] = alloca i32, align 4
7593 // CHECK19-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 4
7594 // CHECK19-NEXT:    [[DOTADDR1:%.*]] = alloca ptr, align 4
7595 // CHECK19-NEXT:    store i32 [[TMP0]], ptr [[DOTADDR]], align 4
7596 // CHECK19-NEXT:    store ptr [[TMP1]], ptr [[DOTADDR1]], align 4
7597 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4
7598 // CHECK19-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 4
7599 // CHECK19-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0
7600 // CHECK19-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2
7601 // CHECK19-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0
7602 // CHECK19-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 4
7603 // CHECK19-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 1
7604 // CHECK19-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]])
7605 // CHECK19-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])
7606 // CHECK19-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])
7607 // CHECK19-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]])
7608 // CHECK19-NEXT:    store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !25
7609 // CHECK19-NEXT:    store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 4, !noalias !25
7610 // CHECK19-NEXT:    store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25
7611 // CHECK19-NEXT:    store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25
7612 // CHECK19-NEXT:    store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 4, !noalias !25
7613 // CHECK19-NEXT:    store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 4, !noalias !25
7614 // CHECK19-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 4, !noalias !25
7615 // CHECK19-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25
7616 // CHECK19-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25
7617 // CHECK19-NEXT:    call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]
7618 // CHECK19-NEXT:    [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !25
7619 // CHECK19-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !25
7620 // CHECK19-NEXT:    [[TMP14:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !25
7621 // CHECK19-NEXT:    [[TMP15:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !25
7622 // CHECK19-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP9]], i32 0, i32 1
7623 // CHECK19-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP9]], i32 0, i32 2
7624 // CHECK19-NEXT:    store i32 2, ptr [[KERNEL_ARGS_I]], align 4, !noalias !25
7625 // CHECK19-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 1
7626 // CHECK19-NEXT:    store i32 3, ptr [[TMP18]], align 4, !noalias !25
7627 // CHECK19-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 2
7628 // CHECK19-NEXT:    store ptr [[TMP13]], ptr [[TMP19]], align 4, !noalias !25
7629 // CHECK19-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 3
7630 // CHECK19-NEXT:    store ptr [[TMP14]], ptr [[TMP20]], align 4, !noalias !25
7631 // CHECK19-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 4
7632 // CHECK19-NEXT:    store ptr [[TMP15]], ptr [[TMP21]], align 4, !noalias !25
7633 // CHECK19-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 5
7634 // CHECK19-NEXT:    store ptr @.offload_maptypes, ptr [[TMP22]], align 4, !noalias !25
7635 // CHECK19-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 6
7636 // CHECK19-NEXT:    store ptr null, ptr [[TMP23]], align 4, !noalias !25
7637 // CHECK19-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 7
7638 // CHECK19-NEXT:    store ptr null, ptr [[TMP24]], align 4, !noalias !25
7639 // CHECK19-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 8
7640 // CHECK19-NEXT:    store i64 0, ptr [[TMP25]], align 8, !noalias !25
7641 // CHECK19-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 9
7642 // CHECK19-NEXT:    store i64 1, ptr [[TMP26]], align 8, !noalias !25
7643 // CHECK19-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 10
7644 // CHECK19-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP27]], align 4, !noalias !25
7645 // CHECK19-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 11
7646 // CHECK19-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP28]], align 4, !noalias !25
7647 // CHECK19-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 12
7648 // CHECK19-NEXT:    store i32 0, ptr [[TMP29]], align 4, !noalias !25
7649 // CHECK19-NEXT:    [[TMP30:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128.region_id, ptr [[KERNEL_ARGS_I]])
7650 // CHECK19-NEXT:    [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0
7651 // CHECK19-NEXT:    br i1 [[TMP31]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]]
7652 // CHECK19:       omp_offload.failed.i:
7653 // CHECK19-NEXT:    [[TMP32:%.*]] = load i16, ptr [[TMP12]], align 2
7654 // CHECK19-NEXT:    store i16 [[TMP32]], ptr [[AA_CASTED_I]], align 2, !noalias !25
7655 // CHECK19-NEXT:    [[TMP33:%.*]] = load i32, ptr [[AA_CASTED_I]], align 4, !noalias !25
7656 // CHECK19-NEXT:    [[TMP34:%.*]] = load i32, ptr [[TMP16]], align 4
7657 // CHECK19-NEXT:    store i32 [[TMP34]], ptr [[LIN_CASTED_I]], align 4, !noalias !25
7658 // CHECK19-NEXT:    [[TMP35:%.*]] = load i32, ptr [[LIN_CASTED_I]], align 4, !noalias !25
7659 // CHECK19-NEXT:    [[TMP36:%.*]] = load i32, ptr [[TMP17]], align 4
7660 // CHECK19-NEXT:    store i32 [[TMP36]], ptr [[A_CASTED_I]], align 4, !noalias !25
7661 // CHECK19-NEXT:    [[TMP37:%.*]] = load i32, ptr [[A_CASTED_I]], align 4, !noalias !25
7662 // CHECK19-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128(i32 [[TMP33]], i32 [[TMP35]], i32 [[TMP37]]) #[[ATTR3]]
7663 // CHECK19-NEXT:    br label [[DOTOMP_OUTLINED__EXIT]]
7664 // CHECK19:       .omp_outlined..exit:
7665 // CHECK19-NEXT:    ret i32 0
7666 //
7667 //
7668 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136
7669 // CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {
7670 // CHECK19-NEXT:  entry:
7671 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
7672 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
7673 // CHECK19-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
7674 // CHECK19-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
7675 // CHECK19-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
7676 // CHECK19-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
7677 // CHECK19-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
7678 // CHECK19-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 4
7679 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4
7680 // CHECK19-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2
7681 // CHECK19-NEXT:    store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
7682 // CHECK19-NEXT:    [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4
7683 // CHECK19-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.omp_outlined, i32 [[TMP1]], i32 [[TMP3]])
7684 // CHECK19-NEXT:    ret void
7685 //
7686 //
7687 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.omp_outlined
7688 // CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {
7689 // CHECK19-NEXT:  entry:
7690 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
7691 // CHECK19-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
7692 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
7693 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
7694 // CHECK19-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
7695 // CHECK19-NEXT:    [[TMP:%.*]] = alloca i16, align 2
7696 // CHECK19-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
7697 // CHECK19-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
7698 // CHECK19-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
7699 // CHECK19-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
7700 // CHECK19-NEXT:    [[IT:%.*]] = alloca i16, align 2
7701 // CHECK19-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
7702 // CHECK19-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
7703 // CHECK19-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
7704 // CHECK19-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
7705 // CHECK19-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
7706 // CHECK19-NEXT:    store i32 3, ptr [[DOTOMP_UB]], align 4
7707 // CHECK19-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
7708 // CHECK19-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
7709 // CHECK19-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
7710 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
7711 // CHECK19-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
7712 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
7713 // CHECK19-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
7714 // CHECK19-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
7715 // CHECK19:       cond.true:
7716 // CHECK19-NEXT:    br label [[COND_END:%.*]]
7717 // CHECK19:       cond.false:
7718 // CHECK19-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
7719 // CHECK19-NEXT:    br label [[COND_END]]
7720 // CHECK19:       cond.end:
7721 // CHECK19-NEXT:    [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
7722 // CHECK19-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
7723 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
7724 // CHECK19-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
7725 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
7726 // CHECK19:       omp.inner.for.cond:
7727 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
7728 // CHECK19-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
7729 // CHECK19-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
7730 // CHECK19-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
7731 // CHECK19:       omp.inner.for.body:
7732 // CHECK19-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
7733 // CHECK19-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
7734 // CHECK19-NEXT:    [[ADD:%.*]] = add nsw i32 6, [[MUL]]
7735 // CHECK19-NEXT:    [[CONV:%.*]] = trunc i32 [[ADD]] to i16
7736 // CHECK19-NEXT:    store i16 [[CONV]], ptr [[IT]], align 2
7737 // CHECK19-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
7738 // CHECK19-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
7739 // CHECK19-NEXT:    store i32 [[ADD2]], ptr [[A_ADDR]], align 4
7740 // CHECK19-NEXT:    [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2
7741 // CHECK19-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP9]] to i32
7742 // CHECK19-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
7743 // CHECK19-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
7744 // CHECK19-NEXT:    store i16 [[CONV5]], ptr [[AA_ADDR]], align 2
7745 // CHECK19-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
7746 // CHECK19:       omp.body.continue:
7747 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
7748 // CHECK19:       omp.inner.for.inc:
7749 // CHECK19-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
7750 // CHECK19-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1
7751 // CHECK19-NEXT:    store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4
7752 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND]]
7753 // CHECK19:       omp.inner.for.end:
7754 // CHECK19-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
7755 // CHECK19:       omp.loop.exit:
7756 // CHECK19-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
7757 // CHECK19-NEXT:    ret void
7758 //
7759 //
7760 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160
7761 // CHECK19-SAME: (i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
7762 // CHECK19-NEXT:  entry:
7763 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
7764 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
7765 // CHECK19-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
7766 // CHECK19-NEXT:    [[BN_ADDR:%.*]] = alloca ptr, align 4
7767 // CHECK19-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
7768 // CHECK19-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
7769 // CHECK19-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
7770 // CHECK19-NEXT:    [[CN_ADDR:%.*]] = alloca ptr, align 4
7771 // CHECK19-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4
7772 // CHECK19-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
7773 // CHECK19-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
7774 // CHECK19-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
7775 // CHECK19-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
7776 // CHECK19-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
7777 // CHECK19-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
7778 // CHECK19-NEXT:    store ptr [[BN]], ptr [[BN_ADDR]], align 4
7779 // CHECK19-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
7780 // CHECK19-NEXT:    store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
7781 // CHECK19-NEXT:    store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4
7782 // CHECK19-NEXT:    store ptr [[CN]], ptr [[CN_ADDR]], align 4
7783 // CHECK19-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4
7784 // CHECK19-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
7785 // CHECK19-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
7786 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
7787 // CHECK19-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4
7788 // CHECK19-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
7789 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
7790 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4
7791 // CHECK19-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4
7792 // CHECK19-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4
7793 // CHECK19-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
7794 // CHECK19-NEXT:    store i32 [[TMP8]], ptr [[A_CASTED]], align 4
7795 // CHECK19-NEXT:    [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4
7796 // CHECK19-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
7797 // CHECK19-NEXT:    store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
7798 // CHECK19-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
7799 // CHECK19-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined, i32 [[TMP9]], ptr [[TMP0]], i32 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i32 [[TMP11]])
7800 // CHECK19-NEXT:    ret void
7801 //
7802 //
7803 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined
7804 // CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
7805 // CHECK19-NEXT:  entry:
7806 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
7807 // CHECK19-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
7808 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
7809 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
7810 // CHECK19-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
7811 // CHECK19-NEXT:    [[BN_ADDR:%.*]] = alloca ptr, align 4
7812 // CHECK19-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
7813 // CHECK19-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
7814 // CHECK19-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
7815 // CHECK19-NEXT:    [[CN_ADDR:%.*]] = alloca ptr, align 4
7816 // CHECK19-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4
7817 // CHECK19-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
7818 // CHECK19-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
7819 // CHECK19-NEXT:    [[TMP:%.*]] = alloca i8, align 1
7820 // CHECK19-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
7821 // CHECK19-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
7822 // CHECK19-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
7823 // CHECK19-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
7824 // CHECK19-NEXT:    [[IT:%.*]] = alloca i8, align 1
7825 // CHECK19-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
7826 // CHECK19-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
7827 // CHECK19-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
7828 // CHECK19-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
7829 // CHECK19-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
7830 // CHECK19-NEXT:    store ptr [[BN]], ptr [[BN_ADDR]], align 4
7831 // CHECK19-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
7832 // CHECK19-NEXT:    store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
7833 // CHECK19-NEXT:    store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4
7834 // CHECK19-NEXT:    store ptr [[CN]], ptr [[CN_ADDR]], align 4
7835 // CHECK19-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4
7836 // CHECK19-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
7837 // CHECK19-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
7838 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
7839 // CHECK19-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4
7840 // CHECK19-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
7841 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
7842 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4
7843 // CHECK19-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4
7844 // CHECK19-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4
7845 // CHECK19-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
7846 // CHECK19-NEXT:    store i32 25, ptr [[DOTOMP_UB]], align 4
7847 // CHECK19-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
7848 // CHECK19-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
7849 // CHECK19-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
7850 // CHECK19-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
7851 // CHECK19-NEXT:    [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4
7852 // CHECK19-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP10]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
7853 // CHECK19-NEXT:    br label [[OMP_DISPATCH_COND:%.*]]
7854 // CHECK19:       omp.dispatch.cond:
7855 // CHECK19-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
7856 // CHECK19-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
7857 // CHECK19-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
7858 // CHECK19:       cond.true:
7859 // CHECK19-NEXT:    br label [[COND_END:%.*]]
7860 // CHECK19:       cond.false:
7861 // CHECK19-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
7862 // CHECK19-NEXT:    br label [[COND_END]]
7863 // CHECK19:       cond.end:
7864 // CHECK19-NEXT:    [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
7865 // CHECK19-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
7866 // CHECK19-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
7867 // CHECK19-NEXT:    store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4
7868 // CHECK19-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
7869 // CHECK19-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
7870 // CHECK19-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
7871 // CHECK19-NEXT:    br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
7872 // CHECK19:       omp.dispatch.body:
7873 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
7874 // CHECK19:       omp.inner.for.cond:
7875 // CHECK19-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
7876 // CHECK19-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
7877 // CHECK19-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
7878 // CHECK19-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
7879 // CHECK19:       omp.inner.for.body:
7880 // CHECK19-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
7881 // CHECK19-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
7882 // CHECK19-NEXT:    [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
7883 // CHECK19-NEXT:    [[CONV:%.*]] = trunc i32 [[SUB]] to i8
7884 // CHECK19-NEXT:    store i8 [[CONV]], ptr [[IT]], align 1
7885 // CHECK19-NEXT:    [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4
7886 // CHECK19-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
7887 // CHECK19-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 4
7888 // CHECK19-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 2
7889 // CHECK19-NEXT:    [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4
7890 // CHECK19-NEXT:    [[CONV7:%.*]] = fpext float [[TMP20]] to double
7891 // CHECK19-NEXT:    [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00
7892 // CHECK19-NEXT:    [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
7893 // CHECK19-NEXT:    store float [[CONV9]], ptr [[ARRAYIDX]], align 4
7894 // CHECK19-NEXT:    [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i32 3
7895 // CHECK19-NEXT:    [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4
7896 // CHECK19-NEXT:    [[CONV11:%.*]] = fpext float [[TMP21]] to double
7897 // CHECK19-NEXT:    [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
7898 // CHECK19-NEXT:    [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
7899 // CHECK19-NEXT:    store float [[CONV13]], ptr [[ARRAYIDX10]], align 4
7900 // CHECK19-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 1
7901 // CHECK19-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i32 0, i32 2
7902 // CHECK19-NEXT:    [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8
7903 // CHECK19-NEXT:    [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
7904 // CHECK19-NEXT:    store double [[ADD16]], ptr [[ARRAYIDX15]], align 8
7905 // CHECK19-NEXT:    [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]
7906 // CHECK19-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i32 [[TMP23]]
7907 // CHECK19-NEXT:    [[ARRAYIDX18:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX17]], i32 3
7908 // CHECK19-NEXT:    [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 8
7909 // CHECK19-NEXT:    [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
7910 // CHECK19-NEXT:    store double [[ADD19]], ptr [[ARRAYIDX18]], align 8
7911 // CHECK19-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0
7912 // CHECK19-NEXT:    [[TMP25:%.*]] = load i64, ptr [[X]], align 4
7913 // CHECK19-NEXT:    [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
7914 // CHECK19-NEXT:    store i64 [[ADD20]], ptr [[X]], align 4
7915 // CHECK19-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1
7916 // CHECK19-NEXT:    [[TMP26:%.*]] = load i8, ptr [[Y]], align 4
7917 // CHECK19-NEXT:    [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
7918 // CHECK19-NEXT:    [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
7919 // CHECK19-NEXT:    [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
7920 // CHECK19-NEXT:    store i8 [[CONV23]], ptr [[Y]], align 4
7921 // CHECK19-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
7922 // CHECK19:       omp.body.continue:
7923 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
7924 // CHECK19:       omp.inner.for.inc:
7925 // CHECK19-NEXT:    [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
7926 // CHECK19-NEXT:    [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
7927 // CHECK19-NEXT:    store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4
7928 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND]]
7929 // CHECK19:       omp.inner.for.end:
7930 // CHECK19-NEXT:    br label [[OMP_DISPATCH_INC:%.*]]
7931 // CHECK19:       omp.dispatch.inc:
7932 // CHECK19-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
7933 // CHECK19-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
7934 // CHECK19-NEXT:    [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
7935 // CHECK19-NEXT:    store i32 [[ADD25]], ptr [[DOTOMP_LB]], align 4
7936 // CHECK19-NEXT:    [[TMP30:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
7937 // CHECK19-NEXT:    [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
7938 // CHECK19-NEXT:    [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
7939 // CHECK19-NEXT:    store i32 [[ADD26]], ptr [[DOTOMP_UB]], align 4
7940 // CHECK19-NEXT:    br label [[OMP_DISPATCH_COND]]
7941 // CHECK19:       omp.dispatch.end:
7942 // CHECK19-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP10]])
7943 // CHECK19-NEXT:    ret void
7944 //
7945 //
7946 // CHECK19-LABEL: define {{[^@]+}}@_Z3bari
7947 // CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
7948 // CHECK19-NEXT:  entry:
7949 // CHECK19-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7950 // CHECK19-NEXT:    [[A:%.*]] = alloca i32, align 4
7951 // CHECK19-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
7952 // CHECK19-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
7953 // CHECK19-NEXT:    store i32 0, ptr [[A]], align 4
7954 // CHECK19-NEXT:    [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
7955 // CHECK19-NEXT:    [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]])
7956 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A]], align 4
7957 // CHECK19-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
7958 // CHECK19-NEXT:    store i32 [[ADD]], ptr [[A]], align 4
7959 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
7960 // CHECK19-NEXT:    [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]])
7961 // CHECK19-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A]], align 4
7962 // CHECK19-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
7963 // CHECK19-NEXT:    store i32 [[ADD2]], ptr [[A]], align 4
7964 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
7965 // CHECK19-NEXT:    [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]])
7966 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, ptr [[A]], align 4
7967 // CHECK19-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
7968 // CHECK19-NEXT:    store i32 [[ADD4]], ptr [[A]], align 4
7969 // CHECK19-NEXT:    [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4
7970 // CHECK19-NEXT:    [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]])
7971 // CHECK19-NEXT:    [[TMP7:%.*]] = load i32, ptr [[A]], align 4
7972 // CHECK19-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
7973 // CHECK19-NEXT:    store i32 [[ADD6]], ptr [[A]], align 4
7974 // CHECK19-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A]], align 4
7975 // CHECK19-NEXT:    ret i32 [[TMP8]]
7976 //
7977 //
7978 // CHECK19-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
7979 // CHECK19-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 {
7980 // CHECK19-NEXT:  entry:
7981 // CHECK19-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
7982 // CHECK19-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7983 // CHECK19-NEXT:    [[B:%.*]] = alloca i32, align 4
7984 // CHECK19-NEXT:    [[SAVED_STACK:%.*]] = alloca ptr, align 4
7985 // CHECK19-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
7986 // CHECK19-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
7987 // CHECK19-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 4
7988 // CHECK19-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 4
7989 // CHECK19-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 4
7990 // CHECK19-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4
7991 // CHECK19-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
7992 // CHECK19-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
7993 // CHECK19-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
7994 // CHECK19-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
7995 // CHECK19-NEXT:    [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
7996 // CHECK19-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
7997 // CHECK19-NEXT:    store i32 [[ADD]], ptr [[B]], align 4
7998 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
7999 // CHECK19-NEXT:    [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
8000 // CHECK19-NEXT:    store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4
8001 // CHECK19-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
8002 // CHECK19-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
8003 // CHECK19-NEXT:    store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4
8004 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, ptr [[B]], align 4
8005 // CHECK19-NEXT:    store i32 [[TMP4]], ptr [[B_CASTED]], align 4
8006 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4
8007 // CHECK19-NEXT:    [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4
8008 // CHECK19-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60
8009 // CHECK19-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
8010 // CHECK19:       omp_if.then:
8011 // CHECK19-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0
8012 // CHECK19-NEXT:    [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]]
8013 // CHECK19-NEXT:    [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2
8014 // CHECK19-NEXT:    [[TMP9:%.*]] = sext i32 [[TMP8]] to i64
8015 // CHECK19-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes.5, i32 40, i1 false)
8016 // CHECK19-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
8017 // CHECK19-NEXT:    store ptr [[THIS1]], ptr [[TMP10]], align 4
8018 // CHECK19-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
8019 // CHECK19-NEXT:    store ptr [[A]], ptr [[TMP11]], align 4
8020 // CHECK19-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
8021 // CHECK19-NEXT:    store ptr null, ptr [[TMP12]], align 4
8022 // CHECK19-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
8023 // CHECK19-NEXT:    store i32 [[TMP5]], ptr [[TMP13]], align 4
8024 // CHECK19-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
8025 // CHECK19-NEXT:    store i32 [[TMP5]], ptr [[TMP14]], align 4
8026 // CHECK19-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
8027 // CHECK19-NEXT:    store ptr null, ptr [[TMP15]], align 4
8028 // CHECK19-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
8029 // CHECK19-NEXT:    store i32 2, ptr [[TMP16]], align 4
8030 // CHECK19-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
8031 // CHECK19-NEXT:    store i32 2, ptr [[TMP17]], align 4
8032 // CHECK19-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
8033 // CHECK19-NEXT:    store ptr null, ptr [[TMP18]], align 4
8034 // CHECK19-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
8035 // CHECK19-NEXT:    store i32 [[TMP1]], ptr [[TMP19]], align 4
8036 // CHECK19-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
8037 // CHECK19-NEXT:    store i32 [[TMP1]], ptr [[TMP20]], align 4
8038 // CHECK19-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
8039 // CHECK19-NEXT:    store ptr null, ptr [[TMP21]], align 4
8040 // CHECK19-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
8041 // CHECK19-NEXT:    store ptr [[VLA]], ptr [[TMP22]], align 4
8042 // CHECK19-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4
8043 // CHECK19-NEXT:    store ptr [[VLA]], ptr [[TMP23]], align 4
8044 // CHECK19-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 4
8045 // CHECK19-NEXT:    store i64 [[TMP9]], ptr [[TMP24]], align 4
8046 // CHECK19-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
8047 // CHECK19-NEXT:    store ptr null, ptr [[TMP25]], align 4
8048 // CHECK19-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
8049 // CHECK19-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
8050 // CHECK19-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0
8051 // CHECK19-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
8052 // CHECK19-NEXT:    store i32 2, ptr [[TMP29]], align 4
8053 // CHECK19-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
8054 // CHECK19-NEXT:    store i32 5, ptr [[TMP30]], align 4
8055 // CHECK19-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
8056 // CHECK19-NEXT:    store ptr [[TMP26]], ptr [[TMP31]], align 4
8057 // CHECK19-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
8058 // CHECK19-NEXT:    store ptr [[TMP27]], ptr [[TMP32]], align 4
8059 // CHECK19-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
8060 // CHECK19-NEXT:    store ptr [[TMP28]], ptr [[TMP33]], align 4
8061 // CHECK19-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
8062 // CHECK19-NEXT:    store ptr @.offload_maptypes.6, ptr [[TMP34]], align 4
8063 // CHECK19-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
8064 // CHECK19-NEXT:    store ptr null, ptr [[TMP35]], align 4
8065 // CHECK19-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
8066 // CHECK19-NEXT:    store ptr null, ptr [[TMP36]], align 4
8067 // CHECK19-NEXT:    [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
8068 // CHECK19-NEXT:    store i64 0, ptr [[TMP37]], align 8
8069 // CHECK19-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
8070 // CHECK19-NEXT:    store i64 0, ptr [[TMP38]], align 8
8071 // CHECK19-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
8072 // CHECK19-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP39]], align 4
8073 // CHECK19-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
8074 // CHECK19-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP40]], align 4
8075 // CHECK19-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
8076 // CHECK19-NEXT:    store i32 0, ptr [[TMP41]], align 4
8077 // CHECK19-NEXT:    [[TMP42:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232.region_id, ptr [[KERNEL_ARGS]])
8078 // CHECK19-NEXT:    [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0
8079 // CHECK19-NEXT:    br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
8080 // CHECK19:       omp_offload.failed:
8081 // CHECK19-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232(ptr [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], ptr [[VLA]]) #[[ATTR3]]
8082 // CHECK19-NEXT:    br label [[OMP_OFFLOAD_CONT]]
8083 // CHECK19:       omp_offload.cont:
8084 // CHECK19-NEXT:    br label [[OMP_IF_END:%.*]]
8085 // CHECK19:       omp_if.else:
8086 // CHECK19-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232(ptr [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], ptr [[VLA]]) #[[ATTR3]]
8087 // CHECK19-NEXT:    br label [[OMP_IF_END]]
8088 // CHECK19:       omp_if.end:
8089 // CHECK19-NEXT:    [[TMP44:%.*]] = mul nsw i32 1, [[TMP1]]
8090 // CHECK19-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP44]]
8091 // CHECK19-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1
8092 // CHECK19-NEXT:    [[TMP45:%.*]] = load i16, ptr [[ARRAYIDX2]], align 2
8093 // CHECK19-NEXT:    [[CONV:%.*]] = sext i16 [[TMP45]] to i32
8094 // CHECK19-NEXT:    [[TMP46:%.*]] = load i32, ptr [[B]], align 4
8095 // CHECK19-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP46]]
8096 // CHECK19-NEXT:    [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
8097 // CHECK19-NEXT:    call void @llvm.stackrestore.p0(ptr [[TMP47]])
8098 // CHECK19-NEXT:    ret i32 [[ADD3]]
8099 //
8100 //
8101 // CHECK19-LABEL: define {{[^@]+}}@_ZL7fstatici
8102 // CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
8103 // CHECK19-NEXT:  entry:
8104 // CHECK19-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
8105 // CHECK19-NEXT:    [[A:%.*]] = alloca i32, align 4
8106 // CHECK19-NEXT:    [[AA:%.*]] = alloca i16, align 2
8107 // CHECK19-NEXT:    [[AAA:%.*]] = alloca i8, align 1
8108 // CHECK19-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
8109 // CHECK19-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
8110 // CHECK19-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
8111 // CHECK19-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
8112 // CHECK19-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 4
8113 // CHECK19-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 4
8114 // CHECK19-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 4
8115 // CHECK19-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
8116 // CHECK19-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
8117 // CHECK19-NEXT:    store i32 0, ptr [[A]], align 4
8118 // CHECK19-NEXT:    store i16 0, ptr [[AA]], align 2
8119 // CHECK19-NEXT:    store i8 0, ptr [[AAA]], align 1
8120 // CHECK19-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A]], align 4
8121 // CHECK19-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 4
8122 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4
8123 // CHECK19-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA]], align 2
8124 // CHECK19-NEXT:    store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
8125 // CHECK19-NEXT:    [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4
8126 // CHECK19-NEXT:    [[TMP4:%.*]] = load i8, ptr [[AAA]], align 1
8127 // CHECK19-NEXT:    store i8 [[TMP4]], ptr [[AAA_CASTED]], align 1
8128 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, ptr [[AAA_CASTED]], align 4
8129 // CHECK19-NEXT:    [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4
8130 // CHECK19-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50
8131 // CHECK19-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
8132 // CHECK19:       omp_if.then:
8133 // CHECK19-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
8134 // CHECK19-NEXT:    store i32 [[TMP1]], ptr [[TMP7]], align 4
8135 // CHECK19-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
8136 // CHECK19-NEXT:    store i32 [[TMP1]], ptr [[TMP8]], align 4
8137 // CHECK19-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
8138 // CHECK19-NEXT:    store ptr null, ptr [[TMP9]], align 4
8139 // CHECK19-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
8140 // CHECK19-NEXT:    store i32 [[TMP3]], ptr [[TMP10]], align 4
8141 // CHECK19-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
8142 // CHECK19-NEXT:    store i32 [[TMP3]], ptr [[TMP11]], align 4
8143 // CHECK19-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
8144 // CHECK19-NEXT:    store ptr null, ptr [[TMP12]], align 4
8145 // CHECK19-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
8146 // CHECK19-NEXT:    store i32 [[TMP5]], ptr [[TMP13]], align 4
8147 // CHECK19-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
8148 // CHECK19-NEXT:    store i32 [[TMP5]], ptr [[TMP14]], align 4
8149 // CHECK19-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
8150 // CHECK19-NEXT:    store ptr null, ptr [[TMP15]], align 4
8151 // CHECK19-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
8152 // CHECK19-NEXT:    store ptr [[B]], ptr [[TMP16]], align 4
8153 // CHECK19-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
8154 // CHECK19-NEXT:    store ptr [[B]], ptr [[TMP17]], align 4
8155 // CHECK19-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
8156 // CHECK19-NEXT:    store ptr null, ptr [[TMP18]], align 4
8157 // CHECK19-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
8158 // CHECK19-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
8159 // CHECK19-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
8160 // CHECK19-NEXT:    store i32 2, ptr [[TMP21]], align 4
8161 // CHECK19-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
8162 // CHECK19-NEXT:    store i32 4, ptr [[TMP22]], align 4
8163 // CHECK19-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
8164 // CHECK19-NEXT:    store ptr [[TMP19]], ptr [[TMP23]], align 4
8165 // CHECK19-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
8166 // CHECK19-NEXT:    store ptr [[TMP20]], ptr [[TMP24]], align 4
8167 // CHECK19-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
8168 // CHECK19-NEXT:    store ptr @.offload_sizes.7, ptr [[TMP25]], align 4
8169 // CHECK19-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
8170 // CHECK19-NEXT:    store ptr @.offload_maptypes.8, ptr [[TMP26]], align 4
8171 // CHECK19-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
8172 // CHECK19-NEXT:    store ptr null, ptr [[TMP27]], align 4
8173 // CHECK19-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
8174 // CHECK19-NEXT:    store ptr null, ptr [[TMP28]], align 4
8175 // CHECK19-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
8176 // CHECK19-NEXT:    store i64 0, ptr [[TMP29]], align 8
8177 // CHECK19-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
8178 // CHECK19-NEXT:    store i64 0, ptr [[TMP30]], align 8
8179 // CHECK19-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
8180 // CHECK19-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP31]], align 4
8181 // CHECK19-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
8182 // CHECK19-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP32]], align 4
8183 // CHECK19-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
8184 // CHECK19-NEXT:    store i32 0, ptr [[TMP33]], align 4
8185 // CHECK19-NEXT:    [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214.region_id, ptr [[KERNEL_ARGS]])
8186 // CHECK19-NEXT:    [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0
8187 // CHECK19-NEXT:    br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
8188 // CHECK19:       omp_offload.failed:
8189 // CHECK19-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], ptr [[B]]) #[[ATTR3]]
8190 // CHECK19-NEXT:    br label [[OMP_OFFLOAD_CONT]]
8191 // CHECK19:       omp_offload.cont:
8192 // CHECK19-NEXT:    br label [[OMP_IF_END:%.*]]
8193 // CHECK19:       omp_if.else:
8194 // CHECK19-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], ptr [[B]]) #[[ATTR3]]
8195 // CHECK19-NEXT:    br label [[OMP_IF_END]]
8196 // CHECK19:       omp_if.end:
8197 // CHECK19-NEXT:    [[TMP36:%.*]] = load i32, ptr [[A]], align 4
8198 // CHECK19-NEXT:    ret i32 [[TMP36]]
8199 //
8200 //
8201 // CHECK19-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
8202 // CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat {
8203 // CHECK19-NEXT:  entry:
8204 // CHECK19-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
8205 // CHECK19-NEXT:    [[A:%.*]] = alloca i32, align 4
8206 // CHECK19-NEXT:    [[AA:%.*]] = alloca i16, align 2
8207 // CHECK19-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
8208 // CHECK19-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
8209 // CHECK19-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
8210 // CHECK19-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 4
8211 // CHECK19-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 4
8212 // CHECK19-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 4
8213 // CHECK19-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
8214 // CHECK19-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
8215 // CHECK19-NEXT:    store i32 0, ptr [[A]], align 4
8216 // CHECK19-NEXT:    store i16 0, ptr [[AA]], align 2
8217 // CHECK19-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A]], align 4
8218 // CHECK19-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 4
8219 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4
8220 // CHECK19-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA]], align 2
8221 // CHECK19-NEXT:    store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
8222 // CHECK19-NEXT:    [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4
8223 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
8224 // CHECK19-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
8225 // CHECK19-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
8226 // CHECK19:       omp_if.then:
8227 // CHECK19-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
8228 // CHECK19-NEXT:    store i32 [[TMP1]], ptr [[TMP5]], align 4
8229 // CHECK19-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
8230 // CHECK19-NEXT:    store i32 [[TMP1]], ptr [[TMP6]], align 4
8231 // CHECK19-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
8232 // CHECK19-NEXT:    store ptr null, ptr [[TMP7]], align 4
8233 // CHECK19-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
8234 // CHECK19-NEXT:    store i32 [[TMP3]], ptr [[TMP8]], align 4
8235 // CHECK19-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
8236 // CHECK19-NEXT:    store i32 [[TMP3]], ptr [[TMP9]], align 4
8237 // CHECK19-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
8238 // CHECK19-NEXT:    store ptr null, ptr [[TMP10]], align 4
8239 // CHECK19-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
8240 // CHECK19-NEXT:    store ptr [[B]], ptr [[TMP11]], align 4
8241 // CHECK19-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
8242 // CHECK19-NEXT:    store ptr [[B]], ptr [[TMP12]], align 4
8243 // CHECK19-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
8244 // CHECK19-NEXT:    store ptr null, ptr [[TMP13]], align 4
8245 // CHECK19-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
8246 // CHECK19-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
8247 // CHECK19-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
8248 // CHECK19-NEXT:    store i32 2, ptr [[TMP16]], align 4
8249 // CHECK19-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
8250 // CHECK19-NEXT:    store i32 3, ptr [[TMP17]], align 4
8251 // CHECK19-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
8252 // CHECK19-NEXT:    store ptr [[TMP14]], ptr [[TMP18]], align 4
8253 // CHECK19-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
8254 // CHECK19-NEXT:    store ptr [[TMP15]], ptr [[TMP19]], align 4
8255 // CHECK19-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
8256 // CHECK19-NEXT:    store ptr @.offload_sizes.9, ptr [[TMP20]], align 4
8257 // CHECK19-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
8258 // CHECK19-NEXT:    store ptr @.offload_maptypes.10, ptr [[TMP21]], align 4
8259 // CHECK19-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
8260 // CHECK19-NEXT:    store ptr null, ptr [[TMP22]], align 4
8261 // CHECK19-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
8262 // CHECK19-NEXT:    store ptr null, ptr [[TMP23]], align 4
8263 // CHECK19-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
8264 // CHECK19-NEXT:    store i64 0, ptr [[TMP24]], align 8
8265 // CHECK19-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
8266 // CHECK19-NEXT:    store i64 0, ptr [[TMP25]], align 8
8267 // CHECK19-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
8268 // CHECK19-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP26]], align 4
8269 // CHECK19-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
8270 // CHECK19-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP27]], align 4
8271 // CHECK19-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
8272 // CHECK19-NEXT:    store i32 0, ptr [[TMP28]], align 4
8273 // CHECK19-NEXT:    [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197.region_id, ptr [[KERNEL_ARGS]])
8274 // CHECK19-NEXT:    [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
8275 // CHECK19-NEXT:    br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
8276 // CHECK19:       omp_offload.failed:
8277 // CHECK19-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR3]]
8278 // CHECK19-NEXT:    br label [[OMP_OFFLOAD_CONT]]
8279 // CHECK19:       omp_offload.cont:
8280 // CHECK19-NEXT:    br label [[OMP_IF_END:%.*]]
8281 // CHECK19:       omp_if.else:
8282 // CHECK19-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR3]]
8283 // CHECK19-NEXT:    br label [[OMP_IF_END]]
8284 // CHECK19:       omp_if.end:
8285 // CHECK19-NEXT:    [[TMP31:%.*]] = load i32, ptr [[A]], align 4
8286 // CHECK19-NEXT:    ret i32 [[TMP31]]
8287 //
8288 //
8289 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232
8290 // CHECK19-SAME: (ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
8291 // CHECK19-NEXT:  entry:
8292 // CHECK19-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
8293 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
8294 // CHECK19-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
8295 // CHECK19-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
8296 // CHECK19-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
8297 // CHECK19-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
8298 // CHECK19-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
8299 // CHECK19-NEXT:    store i32 [[B]], ptr [[B_ADDR]], align 4
8300 // CHECK19-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
8301 // CHECK19-NEXT:    store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
8302 // CHECK19-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
8303 // CHECK19-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
8304 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
8305 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
8306 // CHECK19-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
8307 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4
8308 // CHECK19-NEXT:    store i32 [[TMP4]], ptr [[B_CASTED]], align 4
8309 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4
8310 // CHECK19-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232.omp_outlined, ptr [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], ptr [[TMP3]])
8311 // CHECK19-NEXT:    ret void
8312 //
8313 //
8314 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232.omp_outlined
8315 // CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
8316 // CHECK19-NEXT:  entry:
8317 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
8318 // CHECK19-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
8319 // CHECK19-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
8320 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
8321 // CHECK19-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
8322 // CHECK19-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
8323 // CHECK19-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
8324 // CHECK19-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
8325 // CHECK19-NEXT:    [[TMP:%.*]] = alloca i64, align 4
8326 // CHECK19-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
8327 // CHECK19-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
8328 // CHECK19-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
8329 // CHECK19-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
8330 // CHECK19-NEXT:    [[IT:%.*]] = alloca i64, align 8
8331 // CHECK19-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
8332 // CHECK19-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
8333 // CHECK19-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
8334 // CHECK19-NEXT:    store i32 [[B]], ptr [[B_ADDR]], align 4
8335 // CHECK19-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
8336 // CHECK19-NEXT:    store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
8337 // CHECK19-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
8338 // CHECK19-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
8339 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
8340 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
8341 // CHECK19-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
8342 // CHECK19-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8
8343 // CHECK19-NEXT:    store i64 3, ptr [[DOTOMP_UB]], align 8
8344 // CHECK19-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8
8345 // CHECK19-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
8346 // CHECK19-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
8347 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
8348 // CHECK19-NEXT:    call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP5]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
8349 // CHECK19-NEXT:    [[TMP6:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
8350 // CHECK19-NEXT:    [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3
8351 // CHECK19-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
8352 // CHECK19:       cond.true:
8353 // CHECK19-NEXT:    br label [[COND_END:%.*]]
8354 // CHECK19:       cond.false:
8355 // CHECK19-NEXT:    [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
8356 // CHECK19-NEXT:    br label [[COND_END]]
8357 // CHECK19:       cond.end:
8358 // CHECK19-NEXT:    [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
8359 // CHECK19-NEXT:    store i64 [[COND]], ptr [[DOTOMP_UB]], align 8
8360 // CHECK19-NEXT:    [[TMP8:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
8361 // CHECK19-NEXT:    store i64 [[TMP8]], ptr [[DOTOMP_IV]], align 8
8362 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
8363 // CHECK19:       omp.inner.for.cond:
8364 // CHECK19-NEXT:    [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
8365 // CHECK19-NEXT:    [[TMP10:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
8366 // CHECK19-NEXT:    [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
8367 // CHECK19-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
8368 // CHECK19:       omp.inner.for.body:
8369 // CHECK19-NEXT:    [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
8370 // CHECK19-NEXT:    [[MUL:%.*]] = mul i64 [[TMP11]], 400
8371 // CHECK19-NEXT:    [[SUB:%.*]] = sub i64 2000, [[MUL]]
8372 // CHECK19-NEXT:    store i64 [[SUB]], ptr [[IT]], align 8
8373 // CHECK19-NEXT:    [[TMP12:%.*]] = load i32, ptr [[B_ADDR]], align 4
8374 // CHECK19-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP12]] to double
8375 // CHECK19-NEXT:    [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
8376 // CHECK19-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0
8377 // CHECK19-NEXT:    store double [[ADD]], ptr [[A]], align 4
8378 // CHECK19-NEXT:    [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0
8379 // CHECK19-NEXT:    [[TMP13:%.*]] = load double, ptr [[A4]], align 4
8380 // CHECK19-NEXT:    [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
8381 // CHECK19-NEXT:    store double [[INC]], ptr [[A4]], align 4
8382 // CHECK19-NEXT:    [[CONV5:%.*]] = fptosi double [[INC]] to i16
8383 // CHECK19-NEXT:    [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]]
8384 // CHECK19-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i32 [[TMP14]]
8385 // CHECK19-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1
8386 // CHECK19-NEXT:    store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2
8387 // CHECK19-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
8388 // CHECK19:       omp.body.continue:
8389 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
8390 // CHECK19:       omp.inner.for.inc:
8391 // CHECK19-NEXT:    [[TMP15:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
8392 // CHECK19-NEXT:    [[ADD7:%.*]] = add i64 [[TMP15]], 1
8393 // CHECK19-NEXT:    store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8
8394 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND]]
8395 // CHECK19:       omp.inner.for.end:
8396 // CHECK19-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
8397 // CHECK19:       omp.loop.exit:
8398 // CHECK19-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])
8399 // CHECK19-NEXT:    ret void
8400 //
8401 //
8402 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214
8403 // CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
8404 // CHECK19-NEXT:  entry:
8405 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
8406 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
8407 // CHECK19-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
8408 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
8409 // CHECK19-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
8410 // CHECK19-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
8411 // CHECK19-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
8412 // CHECK19-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
8413 // CHECK19-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
8414 // CHECK19-NEXT:    store i32 [[AAA]], ptr [[AAA_ADDR]], align 4
8415 // CHECK19-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
8416 // CHECK19-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
8417 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
8418 // CHECK19-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 4
8419 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4
8420 // CHECK19-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
8421 // CHECK19-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
8422 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4
8423 // CHECK19-NEXT:    [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 1
8424 // CHECK19-NEXT:    store i8 [[TMP5]], ptr [[AAA_CASTED]], align 1
8425 // CHECK19-NEXT:    [[TMP6:%.*]] = load i32, ptr [[AAA_CASTED]], align 4
8426 // CHECK19-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], ptr [[TMP0]])
8427 // CHECK19-NEXT:    ret void
8428 //
8429 //
8430 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214.omp_outlined
8431 // CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
8432 // CHECK19-NEXT:  entry:
8433 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
8434 // CHECK19-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
8435 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
8436 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
8437 // CHECK19-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
8438 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
8439 // CHECK19-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
8440 // CHECK19-NEXT:    [[TMP:%.*]] = alloca i32, align 4
8441 // CHECK19-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
8442 // CHECK19-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
8443 // CHECK19-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
8444 // CHECK19-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
8445 // CHECK19-NEXT:    store i32 [[AAA]], ptr [[AAA_ADDR]], align 4
8446 // CHECK19-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
8447 // CHECK19-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
8448 // CHECK19-NEXT:    ret void
8449 //
8450 //
8451 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197
8452 // CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
8453 // CHECK19-NEXT:  entry:
8454 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
8455 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
8456 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
8457 // CHECK19-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
8458 // CHECK19-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
8459 // CHECK19-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
8460 // CHECK19-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
8461 // CHECK19-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
8462 // CHECK19-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
8463 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
8464 // CHECK19-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 4
8465 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4
8466 // CHECK19-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
8467 // CHECK19-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
8468 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4
8469 // CHECK19-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], ptr [[TMP0]])
8470 // CHECK19-NEXT:    ret void
8471 //
8472 //
8473 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197.omp_outlined
8474 // CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
8475 // CHECK19-NEXT:  entry:
8476 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
8477 // CHECK19-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
8478 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
8479 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
8480 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
8481 // CHECK19-NEXT:    [[DOTOMP_IV:%.*]] = alloca i64, align 8
8482 // CHECK19-NEXT:    [[TMP:%.*]] = alloca i64, align 4
8483 // CHECK19-NEXT:    [[DOTOMP_LB:%.*]] = alloca i64, align 8
8484 // CHECK19-NEXT:    [[DOTOMP_UB:%.*]] = alloca i64, align 8
8485 // CHECK19-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
8486 // CHECK19-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
8487 // CHECK19-NEXT:    [[I:%.*]] = alloca i64, align 8
8488 // CHECK19-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
8489 // CHECK19-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
8490 // CHECK19-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
8491 // CHECK19-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
8492 // CHECK19-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
8493 // CHECK19-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
8494 // CHECK19-NEXT:    store i64 0, ptr [[DOTOMP_LB]], align 8
8495 // CHECK19-NEXT:    store i64 6, ptr [[DOTOMP_UB]], align 8
8496 // CHECK19-NEXT:    store i64 1, ptr [[DOTOMP_STRIDE]], align 8
8497 // CHECK19-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
8498 // CHECK19-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
8499 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
8500 // CHECK19-NEXT:    call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP2]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
8501 // CHECK19-NEXT:    [[TMP3:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
8502 // CHECK19-NEXT:    [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
8503 // CHECK19-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
8504 // CHECK19:       cond.true:
8505 // CHECK19-NEXT:    br label [[COND_END:%.*]]
8506 // CHECK19:       cond.false:
8507 // CHECK19-NEXT:    [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
8508 // CHECK19-NEXT:    br label [[COND_END]]
8509 // CHECK19:       cond.end:
8510 // CHECK19-NEXT:    [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
8511 // CHECK19-NEXT:    store i64 [[COND]], ptr [[DOTOMP_UB]], align 8
8512 // CHECK19-NEXT:    [[TMP5:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
8513 // CHECK19-NEXT:    store i64 [[TMP5]], ptr [[DOTOMP_IV]], align 8
8514 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
8515 // CHECK19:       omp.inner.for.cond:
8516 // CHECK19-NEXT:    [[TMP6:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
8517 // CHECK19-NEXT:    [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
8518 // CHECK19-NEXT:    [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
8519 // CHECK19-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
8520 // CHECK19:       omp.inner.for.body:
8521 // CHECK19-NEXT:    [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
8522 // CHECK19-NEXT:    [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
8523 // CHECK19-NEXT:    [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
8524 // CHECK19-NEXT:    store i64 [[ADD]], ptr [[I]], align 8
8525 // CHECK19-NEXT:    [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4
8526 // CHECK19-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
8527 // CHECK19-NEXT:    store i32 [[ADD2]], ptr [[A_ADDR]], align 4
8528 // CHECK19-NEXT:    [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2
8529 // CHECK19-NEXT:    [[CONV:%.*]] = sext i16 [[TMP10]] to i32
8530 // CHECK19-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV]], 1
8531 // CHECK19-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
8532 // CHECK19-NEXT:    store i16 [[CONV4]], ptr [[AA_ADDR]], align 2
8533 // CHECK19-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2
8534 // CHECK19-NEXT:    [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
8535 // CHECK19-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1
8536 // CHECK19-NEXT:    store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4
8537 // CHECK19-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
8538 // CHECK19:       omp.body.continue:
8539 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
8540 // CHECK19:       omp.inner.for.inc:
8541 // CHECK19-NEXT:    [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
8542 // CHECK19-NEXT:    [[ADD6:%.*]] = add nsw i64 [[TMP12]], 1
8543 // CHECK19-NEXT:    store i64 [[ADD6]], ptr [[DOTOMP_IV]], align 8
8544 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND]]
8545 // CHECK19:       omp.inner.for.end:
8546 // CHECK19-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
8547 // CHECK19:       omp.loop.exit:
8548 // CHECK19-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])
8549 // CHECK19-NEXT:    ret void
8550 //
8551 //
8552 // CHECK19-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
8553 // CHECK19-SAME: () #[[ATTR5]] {
8554 // CHECK19-NEXT:  entry:
8555 // CHECK19-NEXT:    call void @__tgt_register_requires(i64 1)
8556 // CHECK19-NEXT:    ret void
8557 //