clang/test/OpenMP/target_teams_codegen.cpp

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
   2 // Test host codegen.
   3 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK1
   4 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
   5 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK1
   6 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK3
   7 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
   8 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK3
   9
  10 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  11 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
  12 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  13 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  14 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
  15 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  16
  17 // Test target codegen - host bc file has to be created first.
  18 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
  19 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK9
  20 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
  21 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK9
  22 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
  23 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK11
  24 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
  25 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK11
  26
  27 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
  28 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  29 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
  30 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  31 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
  32 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  33 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
  34 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  35
  36 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK1
  37 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
  38 // RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK1
  39 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK3
  40 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
  41 // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK3
  42
  43 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  44 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
  45 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  46 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  47 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
  48 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  49
  50 // Test target codegen - host bc file has to be created first.
  51 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
  52 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK9
  53 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
  54 // RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK9
  55 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
  56 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK11
  57 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
  58 // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK11
  59
  60 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
  61 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  62 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
  63 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  64 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
  65 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  66 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
  67 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  68
  69 // expected-no-diagnostics
  70 #ifndef HEADER
  71 #define HEADER
  72
  73
  74
  75
  76 // We have 8 target regions, but only 6 that actually will generate offloading
  77 // code and have mapped arguments, and only 4 have all-constant map sizes.
  78
  79
  80
  81 // Check target registration is registered as a Ctor.
  82
  83
  84 template<typename tx, typename ty>
  85 struct TT{
  86   tx X;
  87   ty Y;
  88 };
  89
  90 int global;
  91
  92 int foo(int n) {
  93   int a = 0;
  94   short aa = 0;
  95   float b[10];
  96   float bn[n];
  97   double c[5][10];
  98   double cn[5][n];
  99   TT<long long, char> d;
 100
 101   #pragma omp target teams num_teams(a) thread_limit(a) firstprivate(aa) nowait
 102   {
 103   }
 104
 105   #pragma omp target teams if(target: 0)
 106   {
 107     a += 1;
 108   }
 109
 110
 111   #pragma omp target teams if(target: 1)
 112   {
 113     aa += 1;
 114   }
 115
 116
 117
 118   #pragma omp target teams if(target: n>10)
 119   {
 120     a += 1;
 121     aa += 1;
 122   }
 123
 124   #pragma omp target teams ompx_bare
 125   {
 126     a += 1;
 127     aa += 1;
 128   }
 129
 130   // We capture 3 VLA sizes in this target region
 131
 132
 133
 134
 135
 136   // The names below are not necessarily consistent with the names used for the
 137   // addresses above as some are repeated.
 138
 139
 140
 141
 142
 143
 144
 145
 146
 147
 148   #pragma omp target teams if(target: n>20)
 149   {
 150     a += 1;
 151     b[2] += 1.0;
 152     bn[3] += 1.0;
 153     c[1][2] += 1.0;
 154     cn[1][3] += 1.0;
 155     d.X += 1;
 156     d.Y += 1;
 157   }
 158
 159   const int nn = 0;
 160   #pragma omp target teams shared(nn)
 161   #pragma omp parallel firstprivate(nn)
 162   (void)nn;
 163   #pragma omp target teams firstprivate(nn)
 164   #pragma omp parallel shared(nn)
 165   (void)nn;
 166   return a;
 167 }
 168
 169 // Check that the offloading functions are emitted and that the arguments are
 170 // correct and loaded correctly for the target regions in foo().
 171
 172
 173
 174 // Create stack storage and store argument in there.
 175
 176 // Create stack storage and store argument in there.
 177
 178 // Create stack storage and store argument in there.
 179
 180 // Create local storage for each capture.
 181
 182
 183
 184 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.
 185
 186
 187 void bazzzz(int n, int f[n]) {
 188 #pragma omp target teams private(f)
 189   ;
 190 }
 191
 192 template<typename tx>
 193 tx ftemplate(int n) {
 194   tx a = 0;
 195   short aa = 0;
 196   tx b[10];
 197
 198   #pragma omp target teams if(target: n>40)
 199   {
 200     a += 1;
 201     aa += 1;
 202     b[2] += 1;
 203   }
 204
 205   return a;
 206 }
 207
 208 static
 209 int fstatic(int n) {
 210   int a = 0;
 211   short aa = 0;
 212   char aaa = 0;
 213   int b[10];
 214
 215   #pragma omp target teams if(target: n>50)
 216   {
 217     a += 1;
 218     aa += 1;
 219     aaa += 1;
 220     b[2] += 1;
 221   }
 222
 223   return a;
 224 }
 225
 226 struct S1 {
 227   double a;
 228
 229   int r1(int n){
 230     int b = n+1;
 231     short int c[2][n];
 232
 233     #pragma omp target teams if(target: n>60)
 234     {
 235       this->a = (double)b + 1.5;
 236       c[1][1] = ++a;
 237     }
 238
 239     return c[1][1] + (int)b;
 240   }
 241 };
 242
 243 int bar(int n){
 244   int a = 0;
 245
 246   a += foo(n);
 247
 248   S1 S;
 249   a += S.r1(n);
 250
 251   a += fstatic(n);
 252
 253   a += ftemplate<int>(n);
 254
 255   return a;
 256 }
 257
 258
 259
 260 // We capture 2 VLA sizes in this target region
 261
 262
 263 // The names below are not necessarily consistent with the names used for the
 264 // addresses above as some are repeated.
 265
 266
 267
 268
 269
 270
 271
 272
 273
 274
 275
 276
 277
 278
 279
 280
 281
 282
 283
 284
 285 // Check that the offloading functions are emitted and that the arguments are
 286 // correct and loaded correctly for the target regions of the callees of bar().
 287
 288 // Create local storage for each capture.
 289 // Store captures in the context.
 290
 291
 292 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.
 293
 294
 295 // Create local storage for each capture.
 296 // Store captures in the context.
 297
 298
 299
 300
 301 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.
 302
 303 // Create local storage for each capture.
 304 // Store captures in the context.
 305
 306
 307
 308 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.
 309
 310 #endif
 311 // CHECK1-LABEL: define {{[^@]+}}@_Z3fooi
 312 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
 313 // CHECK1-NEXT:  entry:
 314 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
 315 // CHECK1-NEXT:    [[A:%.*]] = alloca i32, align 4
 316 // CHECK1-NEXT:    [[AA:%.*]] = alloca i16, align 2
 317 // CHECK1-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
 318 // CHECK1-NEXT:    [[SAVED_STACK:%.*]] = alloca ptr, align 8
 319 // CHECK1-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
 320 // CHECK1-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
 321 // CHECK1-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
 322 // CHECK1-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
 323 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
 324 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
 325 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
 326 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
 327 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR__CASTED3:%.*]] = alloca i64, align 8
 328 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8
 329 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 8
 330 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 8
 331 // CHECK1-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4
 332 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
 333 // CHECK1-NEXT:    [[AA_CASTED4:%.*]] = alloca i64, align 8
 334 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [1 x ptr], align 8
 335 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS6:%.*]] = alloca [1 x ptr], align 8
 336 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [1 x ptr], align 8
 337 // CHECK1-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
 338 // CHECK1-NEXT:    [[A_CASTED8:%.*]] = alloca i64, align 8
 339 // CHECK1-NEXT:    [[AA_CASTED9:%.*]] = alloca i64, align 8
 340 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [2 x ptr], align 8
 341 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS11:%.*]] = alloca [2 x ptr], align 8
 342 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [2 x ptr], align 8
 343 // CHECK1-NEXT:    [[KERNEL_ARGS13:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
 344 // CHECK1-NEXT:    [[A_CASTED16:%.*]] = alloca i64, align 8
 345 // CHECK1-NEXT:    [[AA_CASTED17:%.*]] = alloca i64, align 8
 346 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS18:%.*]] = alloca [2 x ptr], align 8
 347 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS19:%.*]] = alloca [2 x ptr], align 8
 348 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS20:%.*]] = alloca [2 x ptr], align 8
 349 // CHECK1-NEXT:    [[KERNEL_ARGS21:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
 350 // CHECK1-NEXT:    [[A_CASTED24:%.*]] = alloca i64, align 8
 351 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS27:%.*]] = alloca [9 x ptr], align 8
 352 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS28:%.*]] = alloca [9 x ptr], align 8
 353 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS29:%.*]] = alloca [9 x ptr], align 8
 354 // CHECK1-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 8
 355 // CHECK1-NEXT:    [[KERNEL_ARGS30:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
 356 // CHECK1-NEXT:    [[NN:%.*]] = alloca i32, align 4
 357 // CHECK1-NEXT:    [[NN_CASTED:%.*]] = alloca i64, align 8
 358 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS35:%.*]] = alloca [1 x ptr], align 8
 359 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS36:%.*]] = alloca [1 x ptr], align 8
 360 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS37:%.*]] = alloca [1 x ptr], align 8
 361 // CHECK1-NEXT:    [[KERNEL_ARGS38:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
 362 // CHECK1-NEXT:    [[NN_CASTED41:%.*]] = alloca i64, align 8
 363 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS42:%.*]] = alloca [1 x ptr], align 8
 364 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS43:%.*]] = alloca [1 x ptr], align 8
 365 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS44:%.*]] = alloca [1 x ptr], align 8
 366 // CHECK1-NEXT:    [[KERNEL_ARGS45:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
 367 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
 368 // CHECK1-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
 369 // CHECK1-NEXT:    store i32 0, ptr [[A]], align 4
 370 // CHECK1-NEXT:    store i16 0, ptr [[AA]], align 2
 371 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
 372 // CHECK1-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
 373 // CHECK1-NEXT:    [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()
 374 // CHECK1-NEXT:    store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8
 375 // CHECK1-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4
 376 // CHECK1-NEXT:    store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8
 377 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
 378 // CHECK1-NEXT:    [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
 379 // CHECK1-NEXT:    [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]]
 380 // CHECK1-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8
 381 // CHECK1-NEXT:    store i64 [[TMP5]], ptr [[__VLA_EXPR1]], align 8
 382 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[A]], align 4
 383 // CHECK1-NEXT:    store i32 [[TMP7]], ptr [[DOTCAPTURE_EXPR_]], align 4
 384 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A]], align 4
 385 // CHECK1-NEXT:    store i32 [[TMP8]], ptr [[DOTCAPTURE_EXPR_2]], align 4
 386 // CHECK1-NEXT:    [[TMP9:%.*]] = load i16, ptr [[AA]], align 2
 387 // CHECK1-NEXT:    store i16 [[TMP9]], ptr [[AA_CASTED]], align 2
 388 // CHECK1-NEXT:    [[TMP10:%.*]] = load i64, ptr [[AA_CASTED]], align 8
 389 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
 390 // CHECK1-NEXT:    store i32 [[TMP11]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
 391 // CHECK1-NEXT:    [[TMP12:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8
 392 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
 393 // CHECK1-NEXT:    store i32 [[TMP13]], ptr [[DOTCAPTURE_EXPR__CASTED3]], align 4
 394 // CHECK1-NEXT:    [[TMP14:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED3]], align 8
 395 // CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
 396 // CHECK1-NEXT:    store i64 [[TMP10]], ptr [[TMP15]], align 8
 397 // CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
 398 // CHECK1-NEXT:    store i64 [[TMP10]], ptr [[TMP16]], align 8
 399 // CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
 400 // CHECK1-NEXT:    store ptr null, ptr [[TMP17]], align 8
 401 // CHECK1-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
 402 // CHECK1-NEXT:    store i64 [[TMP12]], ptr [[TMP18]], align 8
 403 // CHECK1-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
 404 // CHECK1-NEXT:    store i64 [[TMP12]], ptr [[TMP19]], align 8
 405 // CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
 406 // CHECK1-NEXT:    store ptr null, ptr [[TMP20]], align 8
 407 // CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
 408 // CHECK1-NEXT:    store i64 [[TMP14]], ptr [[TMP21]], align 8
 409 // CHECK1-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
 410 // CHECK1-NEXT:    store i64 [[TMP14]], ptr [[TMP22]], align 8
 411 // CHECK1-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
 412 // CHECK1-NEXT:    store ptr null, ptr [[TMP23]], align 8
 413 // CHECK1-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
 414 // CHECK1-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
 415 // CHECK1-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0
 416 // CHECK1-NEXT:    [[TMP27:%.*]] = load i16, ptr [[AA]], align 2
 417 // CHECK1-NEXT:    store i16 [[TMP27]], ptr [[TMP26]], align 4
 418 // CHECK1-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 1
 419 // CHECK1-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
 420 // CHECK1-NEXT:    store i32 [[TMP29]], ptr [[TMP28]], align 4
 421 // CHECK1-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 2
 422 // CHECK1-NEXT:    [[TMP31:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
 423 // CHECK1-NEXT:    store i32 [[TMP31]], ptr [[TMP30]], align 4
 424 // CHECK1-NEXT:    [[TMP32:%.*]] = call ptr @__kmpc_omp_target_task_alloc(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i64 120, i64 12, ptr @.omp_task_entry., i64 -1)
 425 // CHECK1-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP32]], i32 0, i32 0
 426 // CHECK1-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP33]], i32 0, i32 0
 427 // CHECK1-NEXT:    [[TMP35:%.*]] = load ptr, ptr [[TMP34]], align 8
 428 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP35]], ptr align 4 [[AGG_CAPTURED]], i64 12, i1 false)
 429 // CHECK1-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP32]], i32 0, i32 1
 430 // CHECK1-NEXT:    [[TMP37:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP36]], i32 0, i32 0
 431 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP37]], ptr align 8 [[TMP24]], i64 24, i1 false)
 432 // CHECK1-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP36]], i32 0, i32 1
 433 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP38]], ptr align 8 [[TMP25]], i64 24, i1 false)
 434 // CHECK1-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP36]], i32 0, i32 2
 435 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP39]], ptr align 8 @.offload_sizes, i64 24, i1 false)
 436 // CHECK1-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP36]], i32 0, i32 3
 437 // CHECK1-NEXT:    [[TMP41:%.*]] = load i16, ptr [[AA]], align 2
 438 // CHECK1-NEXT:    store i16 [[TMP41]], ptr [[TMP40]], align 8
 439 // CHECK1-NEXT:    [[TMP42:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP32]])
 440 // CHECK1-NEXT:    [[TMP43:%.*]] = load i32, ptr [[A]], align 4
 441 // CHECK1-NEXT:    store i32 [[TMP43]], ptr [[A_CASTED]], align 4
 442 // CHECK1-NEXT:    [[TMP44:%.*]] = load i64, ptr [[A_CASTED]], align 8
 443 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105(i64 [[TMP44]]) #[[ATTR3:[0-9]+]]
 444 // CHECK1-NEXT:    [[TMP45:%.*]] = load i16, ptr [[AA]], align 2
 445 // CHECK1-NEXT:    store i16 [[TMP45]], ptr [[AA_CASTED4]], align 2
 446 // CHECK1-NEXT:    [[TMP46:%.*]] = load i64, ptr [[AA_CASTED4]], align 8
 447 // CHECK1-NEXT:    [[TMP47:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0
 448 // CHECK1-NEXT:    store i64 [[TMP46]], ptr [[TMP47]], align 8
 449 // CHECK1-NEXT:    [[TMP48:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0
 450 // CHECK1-NEXT:    store i64 [[TMP46]], ptr [[TMP48]], align 8
 451 // CHECK1-NEXT:    [[TMP49:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 0
 452 // CHECK1-NEXT:    store ptr null, ptr [[TMP49]], align 8
 453 // CHECK1-NEXT:    [[TMP50:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0
 454 // CHECK1-NEXT:    [[TMP51:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0
 455 // CHECK1-NEXT:    [[TMP52:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
 456 // CHECK1-NEXT:    store i32 2, ptr [[TMP52]], align 4
 457 // CHECK1-NEXT:    [[TMP53:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
 458 // CHECK1-NEXT:    store i32 1, ptr [[TMP53]], align 4
 459 // CHECK1-NEXT:    [[TMP54:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
 460 // CHECK1-NEXT:    store ptr [[TMP50]], ptr [[TMP54]], align 8
 461 // CHECK1-NEXT:    [[TMP55:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
 462 // CHECK1-NEXT:    store ptr [[TMP51]], ptr [[TMP55]], align 8
 463 // CHECK1-NEXT:    [[TMP56:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
 464 // CHECK1-NEXT:    store ptr @.offload_sizes.1, ptr [[TMP56]], align 8
 465 // CHECK1-NEXT:    [[TMP57:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
 466 // CHECK1-NEXT:    store ptr @.offload_maptypes.2, ptr [[TMP57]], align 8
 467 // CHECK1-NEXT:    [[TMP58:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
 468 // CHECK1-NEXT:    store ptr null, ptr [[TMP58]], align 8
 469 // CHECK1-NEXT:    [[TMP59:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
 470 // CHECK1-NEXT:    store ptr null, ptr [[TMP59]], align 8
 471 // CHECK1-NEXT:    [[TMP60:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
 472 // CHECK1-NEXT:    store i64 0, ptr [[TMP60]], align 8
 473 // CHECK1-NEXT:    [[TMP61:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
 474 // CHECK1-NEXT:    store i64 0, ptr [[TMP61]], align 8
 475 // CHECK1-NEXT:    [[TMP62:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
 476 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP62]], align 4
 477 // CHECK1-NEXT:    [[TMP63:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
 478 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP63]], align 4
 479 // CHECK1-NEXT:    [[TMP64:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
 480 // CHECK1-NEXT:    store i32 0, ptr [[TMP64]], align 4
 481 // CHECK1-NEXT:    [[TMP65:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.region_id, ptr [[KERNEL_ARGS]])
 482 // CHECK1-NEXT:    [[TMP66:%.*]] = icmp ne i32 [[TMP65]], 0
 483 // CHECK1-NEXT:    br i1 [[TMP66]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
 484 // CHECK1:       omp_offload.failed:
 485 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i64 [[TMP46]]) #[[ATTR3]]
 486 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
 487 // CHECK1:       omp_offload.cont:
 488 // CHECK1-NEXT:    [[TMP67:%.*]] = load i32, ptr [[A]], align 4
 489 // CHECK1-NEXT:    store i32 [[TMP67]], ptr [[A_CASTED8]], align 4
 490 // CHECK1-NEXT:    [[TMP68:%.*]] = load i64, ptr [[A_CASTED8]], align 8
 491 // CHECK1-NEXT:    [[TMP69:%.*]] = load i16, ptr [[AA]], align 2
 492 // CHECK1-NEXT:    store i16 [[TMP69]], ptr [[AA_CASTED9]], align 2
 493 // CHECK1-NEXT:    [[TMP70:%.*]] = load i64, ptr [[AA_CASTED9]], align 8
 494 // CHECK1-NEXT:    [[TMP71:%.*]] = load i32, ptr [[N_ADDR]], align 4
 495 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP71]], 10
 496 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
 497 // CHECK1:       omp_if.then:
 498 // CHECK1-NEXT:    [[TMP72:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
 499 // CHECK1-NEXT:    store i64 [[TMP68]], ptr [[TMP72]], align 8
 500 // CHECK1-NEXT:    [[TMP73:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
 501 // CHECK1-NEXT:    store i64 [[TMP68]], ptr [[TMP73]], align 8
 502 // CHECK1-NEXT:    [[TMP74:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 0
 503 // CHECK1-NEXT:    store ptr null, ptr [[TMP74]], align 8
 504 // CHECK1-NEXT:    [[TMP75:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 1
 505 // CHECK1-NEXT:    store i64 [[TMP70]], ptr [[TMP75]], align 8
 506 // CHECK1-NEXT:    [[TMP76:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 1
 507 // CHECK1-NEXT:    store i64 [[TMP70]], ptr [[TMP76]], align 8
 508 // CHECK1-NEXT:    [[TMP77:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 1
 509 // CHECK1-NEXT:    store ptr null, ptr [[TMP77]], align 8
 510 // CHECK1-NEXT:    [[TMP78:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
 511 // CHECK1-NEXT:    [[TMP79:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
 512 // CHECK1-NEXT:    [[TMP80:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 0
 513 // CHECK1-NEXT:    store i32 2, ptr [[TMP80]], align 4
 514 // CHECK1-NEXT:    [[TMP81:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 1
 515 // CHECK1-NEXT:    store i32 2, ptr [[TMP81]], align 4
 516 // CHECK1-NEXT:    [[TMP82:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 2
 517 // CHECK1-NEXT:    store ptr [[TMP78]], ptr [[TMP82]], align 8
 518 // CHECK1-NEXT:    [[TMP83:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 3
 519 // CHECK1-NEXT:    store ptr [[TMP79]], ptr [[TMP83]], align 8
 520 // CHECK1-NEXT:    [[TMP84:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 4
 521 // CHECK1-NEXT:    store ptr @.offload_sizes.3, ptr [[TMP84]], align 8
 522 // CHECK1-NEXT:    [[TMP85:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 5
 523 // CHECK1-NEXT:    store ptr @.offload_maptypes.4, ptr [[TMP85]], align 8
 524 // CHECK1-NEXT:    [[TMP86:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 6
 525 // CHECK1-NEXT:    store ptr null, ptr [[TMP86]], align 8
 526 // CHECK1-NEXT:    [[TMP87:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 7
 527 // CHECK1-NEXT:    store ptr null, ptr [[TMP87]], align 8
 528 // CHECK1-NEXT:    [[TMP88:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 8
 529 // CHECK1-NEXT:    store i64 0, ptr [[TMP88]], align 8
 530 // CHECK1-NEXT:    [[TMP89:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 9
 531 // CHECK1-NEXT:    store i64 0, ptr [[TMP89]], align 8
 532 // CHECK1-NEXT:    [[TMP90:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 10
 533 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP90]], align 4
 534 // CHECK1-NEXT:    [[TMP91:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 11
 535 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP91]], align 4
 536 // CHECK1-NEXT:    [[TMP92:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 12
 537 // CHECK1-NEXT:    store i32 0, ptr [[TMP92]], align 4
 538 // CHECK1-NEXT:    [[TMP93:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.region_id, ptr [[KERNEL_ARGS13]])
 539 // CHECK1-NEXT:    [[TMP94:%.*]] = icmp ne i32 [[TMP93]], 0
 540 // CHECK1-NEXT:    br i1 [[TMP94]], label [[OMP_OFFLOAD_FAILED14:%.*]], label [[OMP_OFFLOAD_CONT15:%.*]]
 541 // CHECK1:       omp_offload.failed14:
 542 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP68]], i64 [[TMP70]]) #[[ATTR3]]
 543 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT15]]
 544 // CHECK1:       omp_offload.cont15:
 545 // CHECK1-NEXT:    br label [[OMP_IF_END:%.*]]
 546 // CHECK1:       omp_if.else:
 547 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP68]], i64 [[TMP70]]) #[[ATTR3]]
 548 // CHECK1-NEXT:    br label [[OMP_IF_END]]
 549 // CHECK1:       omp_if.end:
 550 // CHECK1-NEXT:    [[TMP95:%.*]] = load i32, ptr [[A]], align 4
 551 // CHECK1-NEXT:    store i32 [[TMP95]], ptr [[A_CASTED16]], align 4
 552 // CHECK1-NEXT:    [[TMP96:%.*]] = load i64, ptr [[A_CASTED16]], align 8
 553 // CHECK1-NEXT:    [[TMP97:%.*]] = load i16, ptr [[AA]], align 2
 554 // CHECK1-NEXT:    store i16 [[TMP97]], ptr [[AA_CASTED17]], align 2
 555 // CHECK1-NEXT:    [[TMP98:%.*]] = load i64, ptr [[AA_CASTED17]], align 8
 556 // CHECK1-NEXT:    [[TMP99:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 0
 557 // CHECK1-NEXT:    store i64 [[TMP96]], ptr [[TMP99]], align 8
 558 // CHECK1-NEXT:    [[TMP100:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS19]], i32 0, i32 0
 559 // CHECK1-NEXT:    store i64 [[TMP96]], ptr [[TMP100]], align 8
 560 // CHECK1-NEXT:    [[TMP101:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS20]], i64 0, i64 0
 561 // CHECK1-NEXT:    store ptr null, ptr [[TMP101]], align 8
 562 // CHECK1-NEXT:    [[TMP102:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 1
 563 // CHECK1-NEXT:    store i64 [[TMP98]], ptr [[TMP102]], align 8
 564 // CHECK1-NEXT:    [[TMP103:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS19]], i32 0, i32 1
 565 // CHECK1-NEXT:    store i64 [[TMP98]], ptr [[TMP103]], align 8
 566 // CHECK1-NEXT:    [[TMP104:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS20]], i64 0, i64 1
 567 // CHECK1-NEXT:    store ptr null, ptr [[TMP104]], align 8
 568 // CHECK1-NEXT:    [[TMP105:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 0
 569 // CHECK1-NEXT:    [[TMP106:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS19]], i32 0, i32 0
 570 // CHECK1-NEXT:    [[TMP107:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 0
 571 // CHECK1-NEXT:    store i32 2, ptr [[TMP107]], align 4
 572 // CHECK1-NEXT:    [[TMP108:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 1
 573 // CHECK1-NEXT:    store i32 2, ptr [[TMP108]], align 4
 574 // CHECK1-NEXT:    [[TMP109:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 2
 575 // CHECK1-NEXT:    store ptr [[TMP105]], ptr [[TMP109]], align 8
 576 // CHECK1-NEXT:    [[TMP110:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 3
 577 // CHECK1-NEXT:    store ptr [[TMP106]], ptr [[TMP110]], align 8
 578 // CHECK1-NEXT:    [[TMP111:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 4
 579 // CHECK1-NEXT:    store ptr @.offload_sizes.5, ptr [[TMP111]], align 8
 580 // CHECK1-NEXT:    [[TMP112:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 5
 581 // CHECK1-NEXT:    store ptr @.offload_maptypes.6, ptr [[TMP112]], align 8
 582 // CHECK1-NEXT:    [[TMP113:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 6
 583 // CHECK1-NEXT:    store ptr null, ptr [[TMP113]], align 8
 584 // CHECK1-NEXT:    [[TMP114:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 7
 585 // CHECK1-NEXT:    store ptr null, ptr [[TMP114]], align 8
 586 // CHECK1-NEXT:    [[TMP115:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 8
 587 // CHECK1-NEXT:    store i64 0, ptr [[TMP115]], align 8
 588 // CHECK1-NEXT:    [[TMP116:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 9
 589 // CHECK1-NEXT:    store i64 0, ptr [[TMP116]], align 8
 590 // CHECK1-NEXT:    [[TMP117:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 10
 591 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP117]], align 4
 592 // CHECK1-NEXT:    [[TMP118:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 11
 593 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP118]], align 4
 594 // CHECK1-NEXT:    [[TMP119:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 12
 595 // CHECK1-NEXT:    store i32 0, ptr [[TMP119]], align 4
 596 // CHECK1-NEXT:    [[TMP120:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l124.region_id, ptr [[KERNEL_ARGS21]])
 597 // CHECK1-NEXT:    [[TMP121:%.*]] = icmp ne i32 [[TMP120]], 0
 598 // CHECK1-NEXT:    br i1 [[TMP121]], label [[OMP_OFFLOAD_FAILED22:%.*]], label [[OMP_OFFLOAD_CONT23:%.*]]
 599 // CHECK1:       omp_offload.failed22:
 600 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l124(i64 [[TMP96]], i64 [[TMP98]]) #[[ATTR3]]
 601 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT23]]
 602 // CHECK1:       omp_offload.cont23:
 603 // CHECK1-NEXT:    [[TMP122:%.*]] = load i32, ptr [[A]], align 4
 604 // CHECK1-NEXT:    store i32 [[TMP122]], ptr [[A_CASTED24]], align 4
 605 // CHECK1-NEXT:    [[TMP123:%.*]] = load i64, ptr [[A_CASTED24]], align 8
 606 // CHECK1-NEXT:    [[TMP124:%.*]] = load i32, ptr [[N_ADDR]], align 4
 607 // CHECK1-NEXT:    [[CMP25:%.*]] = icmp sgt i32 [[TMP124]], 20
 608 // CHECK1-NEXT:    br i1 [[CMP25]], label [[OMP_IF_THEN26:%.*]], label [[OMP_IF_ELSE33:%.*]]
 609 // CHECK1:       omp_if.then26:
 610 // CHECK1-NEXT:    [[TMP125:%.*]] = mul nuw i64 [[TMP2]], 4
 611 // CHECK1-NEXT:    [[TMP126:%.*]] = mul nuw i64 5, [[TMP5]]
 612 // CHECK1-NEXT:    [[TMP127:%.*]] = mul nuw i64 [[TMP126]], 8
 613 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes.7, i64 72, i1 false)
 614 // CHECK1-NEXT:    [[TMP128:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 0
 615 // CHECK1-NEXT:    store i64 [[TMP123]], ptr [[TMP128]], align 8
 616 // CHECK1-NEXT:    [[TMP129:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS28]], i32 0, i32 0
 617 // CHECK1-NEXT:    store i64 [[TMP123]], ptr [[TMP129]], align 8
 618 // CHECK1-NEXT:    [[TMP130:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS29]], i64 0, i64 0
 619 // CHECK1-NEXT:    store ptr null, ptr [[TMP130]], align 8
 620 // CHECK1-NEXT:    [[TMP131:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 1
 621 // CHECK1-NEXT:    store ptr [[B]], ptr [[TMP131]], align 8
 622 // CHECK1-NEXT:    [[TMP132:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS28]], i32 0, i32 1
 623 // CHECK1-NEXT:    store ptr [[B]], ptr [[TMP132]], align 8
 624 // CHECK1-NEXT:    [[TMP133:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS29]], i64 0, i64 1
 625 // CHECK1-NEXT:    store ptr null, ptr [[TMP133]], align 8
 626 // CHECK1-NEXT:    [[TMP134:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 2
 627 // CHECK1-NEXT:    store i64 [[TMP2]], ptr [[TMP134]], align 8
 628 // CHECK1-NEXT:    [[TMP135:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS28]], i32 0, i32 2
 629 // CHECK1-NEXT:    store i64 [[TMP2]], ptr [[TMP135]], align 8
 630 // CHECK1-NEXT:    [[TMP136:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS29]], i64 0, i64 2
 631 // CHECK1-NEXT:    store ptr null, ptr [[TMP136]], align 8
 632 // CHECK1-NEXT:    [[TMP137:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 3
 633 // CHECK1-NEXT:    store ptr [[VLA]], ptr [[TMP137]], align 8
 634 // CHECK1-NEXT:    [[TMP138:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS28]], i32 0, i32 3
 635 // CHECK1-NEXT:    store ptr [[VLA]], ptr [[TMP138]], align 8
 636 // CHECK1-NEXT:    [[TMP139:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 3
 637 // CHECK1-NEXT:    store i64 [[TMP125]], ptr [[TMP139]], align 8
 638 // CHECK1-NEXT:    [[TMP140:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS29]], i64 0, i64 3
 639 // CHECK1-NEXT:    store ptr null, ptr [[TMP140]], align 8
 640 // CHECK1-NEXT:    [[TMP141:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 4
 641 // CHECK1-NEXT:    store ptr [[C]], ptr [[TMP141]], align 8
 642 // CHECK1-NEXT:    [[TMP142:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS28]], i32 0, i32 4
 643 // CHECK1-NEXT:    store ptr [[C]], ptr [[TMP142]], align 8
 644 // CHECK1-NEXT:    [[TMP143:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS29]], i64 0, i64 4
 645 // CHECK1-NEXT:    store ptr null, ptr [[TMP143]], align 8
 646 // CHECK1-NEXT:    [[TMP144:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 5
 647 // CHECK1-NEXT:    store i64 5, ptr [[TMP144]], align 8
 648 // CHECK1-NEXT:    [[TMP145:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS28]], i32 0, i32 5
 649 // CHECK1-NEXT:    store i64 5, ptr [[TMP145]], align 8
 650 // CHECK1-NEXT:    [[TMP146:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS29]], i64 0, i64 5
 651 // CHECK1-NEXT:    store ptr null, ptr [[TMP146]], align 8
 652 // CHECK1-NEXT:    [[TMP147:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 6
 653 // CHECK1-NEXT:    store i64 [[TMP5]], ptr [[TMP147]], align 8
 654 // CHECK1-NEXT:    [[TMP148:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS28]], i32 0, i32 6
 655 // CHECK1-NEXT:    store i64 [[TMP5]], ptr [[TMP148]], align 8
 656 // CHECK1-NEXT:    [[TMP149:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS29]], i64 0, i64 6
 657 // CHECK1-NEXT:    store ptr null, ptr [[TMP149]], align 8
 658 // CHECK1-NEXT:    [[TMP150:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 7
 659 // CHECK1-NEXT:    store ptr [[VLA1]], ptr [[TMP150]], align 8
 660 // CHECK1-NEXT:    [[TMP151:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS28]], i32 0, i32 7
 661 // CHECK1-NEXT:    store ptr [[VLA1]], ptr [[TMP151]], align 8
 662 // CHECK1-NEXT:    [[TMP152:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 7
 663 // CHECK1-NEXT:    store i64 [[TMP127]], ptr [[TMP152]], align 8
 664 // CHECK1-NEXT:    [[TMP153:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS29]], i64 0, i64 7
 665 // CHECK1-NEXT:    store ptr null, ptr [[TMP153]], align 8
 666 // CHECK1-NEXT:    [[TMP154:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 8
 667 // CHECK1-NEXT:    store ptr [[D]], ptr [[TMP154]], align 8
 668 // CHECK1-NEXT:    [[TMP155:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS28]], i32 0, i32 8
 669 // CHECK1-NEXT:    store ptr [[D]], ptr [[TMP155]], align 8
 670 // CHECK1-NEXT:    [[TMP156:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS29]], i64 0, i64 8
 671 // CHECK1-NEXT:    store ptr null, ptr [[TMP156]], align 8
 672 // CHECK1-NEXT:    [[TMP157:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 0
 673 // CHECK1-NEXT:    [[TMP158:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS28]], i32 0, i32 0
 674 // CHECK1-NEXT:    [[TMP159:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0
 675 // CHECK1-NEXT:    [[TMP160:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 0
 676 // CHECK1-NEXT:    store i32 2, ptr [[TMP160]], align 4
 677 // CHECK1-NEXT:    [[TMP161:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 1
 678 // CHECK1-NEXT:    store i32 9, ptr [[TMP161]], align 4
 679 // CHECK1-NEXT:    [[TMP162:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 2
 680 // CHECK1-NEXT:    store ptr [[TMP157]], ptr [[TMP162]], align 8
 681 // CHECK1-NEXT:    [[TMP163:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 3
 682 // CHECK1-NEXT:    store ptr [[TMP158]], ptr [[TMP163]], align 8
 683 // CHECK1-NEXT:    [[TMP164:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 4
 684 // CHECK1-NEXT:    store ptr [[TMP159]], ptr [[TMP164]], align 8
 685 // CHECK1-NEXT:    [[TMP165:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 5
 686 // CHECK1-NEXT:    store ptr @.offload_maptypes.8, ptr [[TMP165]], align 8
 687 // CHECK1-NEXT:    [[TMP166:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 6
 688 // CHECK1-NEXT:    store ptr null, ptr [[TMP166]], align 8
 689 // CHECK1-NEXT:    [[TMP167:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 7
 690 // CHECK1-NEXT:    store ptr null, ptr [[TMP167]], align 8
 691 // CHECK1-NEXT:    [[TMP168:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 8
 692 // CHECK1-NEXT:    store i64 0, ptr [[TMP168]], align 8
 693 // CHECK1-NEXT:    [[TMP169:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 9
 694 // CHECK1-NEXT:    store i64 0, ptr [[TMP169]], align 8
 695 // CHECK1-NEXT:    [[TMP170:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 10
 696 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP170]], align 4
 697 // CHECK1-NEXT:    [[TMP171:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 11
 698 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP171]], align 4
 699 // CHECK1-NEXT:    [[TMP172:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 12
 700 // CHECK1-NEXT:    store i32 0, ptr [[TMP172]], align 4
 701 // CHECK1-NEXT:    [[TMP173:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l148.region_id, ptr [[KERNEL_ARGS30]])
 702 // CHECK1-NEXT:    [[TMP174:%.*]] = icmp ne i32 [[TMP173]], 0
 703 // CHECK1-NEXT:    br i1 [[TMP174]], label [[OMP_OFFLOAD_FAILED31:%.*]], label [[OMP_OFFLOAD_CONT32:%.*]]
 704 // CHECK1:       omp_offload.failed31:
 705 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l148(i64 [[TMP123]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]]) #[[ATTR3]]
 706 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT32]]
 707 // CHECK1:       omp_offload.cont32:
 708 // CHECK1-NEXT:    br label [[OMP_IF_END34:%.*]]
 709 // CHECK1:       omp_if.else33:
 710 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l148(i64 [[TMP123]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]]) #[[ATTR3]]
 711 // CHECK1-NEXT:    br label [[OMP_IF_END34]]
 712 // CHECK1:       omp_if.end34:
 713 // CHECK1-NEXT:    store i32 0, ptr [[NN]], align 4
 714 // CHECK1-NEXT:    [[TMP175:%.*]] = load i32, ptr [[NN]], align 4
 715 // CHECK1-NEXT:    store i32 [[TMP175]], ptr [[NN_CASTED]], align 4
 716 // CHECK1-NEXT:    [[TMP176:%.*]] = load i64, ptr [[NN_CASTED]], align 8
 717 // CHECK1-NEXT:    [[TMP177:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS35]], i32 0, i32 0
 718 // CHECK1-NEXT:    store i64 [[TMP176]], ptr [[TMP177]], align 8
 719 // CHECK1-NEXT:    [[TMP178:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS36]], i32 0, i32 0
 720 // CHECK1-NEXT:    store i64 [[TMP176]], ptr [[TMP178]], align 8
 721 // CHECK1-NEXT:    [[TMP179:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS37]], i64 0, i64 0
 722 // CHECK1-NEXT:    store ptr null, ptr [[TMP179]], align 8
 723 // CHECK1-NEXT:    [[TMP180:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS35]], i32 0, i32 0
 724 // CHECK1-NEXT:    [[TMP181:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS36]], i32 0, i32 0
 725 // CHECK1-NEXT:    [[TMP182:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 0
 726 // CHECK1-NEXT:    store i32 2, ptr [[TMP182]], align 4
 727 // CHECK1-NEXT:    [[TMP183:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 1
 728 // CHECK1-NEXT:    store i32 1, ptr [[TMP183]], align 4
 729 // CHECK1-NEXT:    [[TMP184:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 2
 730 // CHECK1-NEXT:    store ptr [[TMP180]], ptr [[TMP184]], align 8
 731 // CHECK1-NEXT:    [[TMP185:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 3
 732 // CHECK1-NEXT:    store ptr [[TMP181]], ptr [[TMP185]], align 8
 733 // CHECK1-NEXT:    [[TMP186:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 4
 734 // CHECK1-NEXT:    store ptr @.offload_sizes.9, ptr [[TMP186]], align 8
 735 // CHECK1-NEXT:    [[TMP187:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 5
 736 // CHECK1-NEXT:    store ptr @.offload_maptypes.10, ptr [[TMP187]], align 8
 737 // CHECK1-NEXT:    [[TMP188:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 6
 738 // CHECK1-NEXT:    store ptr null, ptr [[TMP188]], align 8
 739 // CHECK1-NEXT:    [[TMP189:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 7
 740 // CHECK1-NEXT:    store ptr null, ptr [[TMP189]], align 8
 741 // CHECK1-NEXT:    [[TMP190:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 8
 742 // CHECK1-NEXT:    store i64 0, ptr [[TMP190]], align 8
 743 // CHECK1-NEXT:    [[TMP191:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 9
 744 // CHECK1-NEXT:    store i64 0, ptr [[TMP191]], align 8
 745 // CHECK1-NEXT:    [[TMP192:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 10
 746 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP192]], align 4
 747 // CHECK1-NEXT:    [[TMP193:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 11
 748 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP193]], align 4
 749 // CHECK1-NEXT:    [[TMP194:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 12
 750 // CHECK1-NEXT:    store i32 0, ptr [[TMP194]], align 4
 751 // CHECK1-NEXT:    [[TMP195:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.region_id, ptr [[KERNEL_ARGS38]])
 752 // CHECK1-NEXT:    [[TMP196:%.*]] = icmp ne i32 [[TMP195]], 0
 753 // CHECK1-NEXT:    br i1 [[TMP196]], label [[OMP_OFFLOAD_FAILED39:%.*]], label [[OMP_OFFLOAD_CONT40:%.*]]
 754 // CHECK1:       omp_offload.failed39:
 755 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160(i64 [[TMP176]]) #[[ATTR3]]
 756 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT40]]
 757 // CHECK1:       omp_offload.cont40:
 758 // CHECK1-NEXT:    [[TMP197:%.*]] = load i32, ptr [[NN]], align 4
 759 // CHECK1-NEXT:    store i32 [[TMP197]], ptr [[NN_CASTED41]], align 4
 760 // CHECK1-NEXT:    [[TMP198:%.*]] = load i64, ptr [[NN_CASTED41]], align 8
 761 // CHECK1-NEXT:    [[TMP199:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS42]], i32 0, i32 0
 762 // CHECK1-NEXT:    store i64 [[TMP198]], ptr [[TMP199]], align 8
 763 // CHECK1-NEXT:    [[TMP200:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS43]], i32 0, i32 0
 764 // CHECK1-NEXT:    store i64 [[TMP198]], ptr [[TMP200]], align 8
 765 // CHECK1-NEXT:    [[TMP201:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS44]], i64 0, i64 0
 766 // CHECK1-NEXT:    store ptr null, ptr [[TMP201]], align 8
 767 // CHECK1-NEXT:    [[TMP202:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS42]], i32 0, i32 0
 768 // CHECK1-NEXT:    [[TMP203:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS43]], i32 0, i32 0
 769 // CHECK1-NEXT:    [[TMP204:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS45]], i32 0, i32 0
 770 // CHECK1-NEXT:    store i32 2, ptr [[TMP204]], align 4
 771 // CHECK1-NEXT:    [[TMP205:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS45]], i32 0, i32 1
 772 // CHECK1-NEXT:    store i32 1, ptr [[TMP205]], align 4
 773 // CHECK1-NEXT:    [[TMP206:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS45]], i32 0, i32 2
 774 // CHECK1-NEXT:    store ptr [[TMP202]], ptr [[TMP206]], align 8
 775 // CHECK1-NEXT:    [[TMP207:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS45]], i32 0, i32 3
 776 // CHECK1-NEXT:    store ptr [[TMP203]], ptr [[TMP207]], align 8
 777 // CHECK1-NEXT:    [[TMP208:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS45]], i32 0, i32 4
 778 // CHECK1-NEXT:    store ptr @.offload_sizes.11, ptr [[TMP208]], align 8
 779 // CHECK1-NEXT:    [[TMP209:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS45]], i32 0, i32 5
 780 // CHECK1-NEXT:    store ptr @.offload_maptypes.12, ptr [[TMP209]], align 8
 781 // CHECK1-NEXT:    [[TMP210:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS45]], i32 0, i32 6
 782 // CHECK1-NEXT:    store ptr null, ptr [[TMP210]], align 8
 783 // CHECK1-NEXT:    [[TMP211:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS45]], i32 0, i32 7
 784 // CHECK1-NEXT:    store ptr null, ptr [[TMP211]], align 8
 785 // CHECK1-NEXT:    [[TMP212:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS45]], i32 0, i32 8
 786 // CHECK1-NEXT:    store i64 0, ptr [[TMP212]], align 8
 787 // CHECK1-NEXT:    [[TMP213:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS45]], i32 0, i32 9
 788 // CHECK1-NEXT:    store i64 0, ptr [[TMP213]], align 8
 789 // CHECK1-NEXT:    [[TMP214:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS45]], i32 0, i32 10
 790 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP214]], align 4
 791 // CHECK1-NEXT:    [[TMP215:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS45]], i32 0, i32 11
 792 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP215]], align 4
 793 // CHECK1-NEXT:    [[TMP216:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS45]], i32 0, i32 12
 794 // CHECK1-NEXT:    store i32 0, ptr [[TMP216]], align 4
 795 // CHECK1-NEXT:    [[TMP217:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l163.region_id, ptr [[KERNEL_ARGS45]])
 796 // CHECK1-NEXT:    [[TMP218:%.*]] = icmp ne i32 [[TMP217]], 0
 797 // CHECK1-NEXT:    br i1 [[TMP218]], label [[OMP_OFFLOAD_FAILED46:%.*]], label [[OMP_OFFLOAD_CONT47:%.*]]
 798 // CHECK1:       omp_offload.failed46:
 799 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l163(i64 [[TMP198]]) #[[ATTR3]]
 800 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT47]]
 801 // CHECK1:       omp_offload.cont47:
 802 // CHECK1-NEXT:    [[TMP219:%.*]] = load i32, ptr [[A]], align 4
 803 // CHECK1-NEXT:    [[TMP220:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
 804 // CHECK1-NEXT:    call void @llvm.stackrestore.p0(ptr [[TMP220]])
 805 // CHECK1-NEXT:    ret i32 [[TMP219]]
 806 //
 807 //
 808 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101
 809 // CHECK1-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] {
 810 // CHECK1-NEXT:  entry:
 811 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
 812 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
 813 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8
 814 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
 815 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
 816 // CHECK1-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
 817 // CHECK1-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
 818 // CHECK1-NEXT:    store i64 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 8
 819 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
 820 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4
 821 // CHECK1-NEXT:    call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
 822 // CHECK1-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
 823 // CHECK1-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
 824 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8
 825 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.omp_outlined, i64 [[TMP4]])
 826 // CHECK1-NEXT:    ret void
 827 //
 828 //
 829 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.omp_outlined
 830 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {
 831 // CHECK1-NEXT:  entry:
 832 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 833 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 834 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
 835 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 836 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 837 // CHECK1-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
 838 // CHECK1-NEXT:    ret void
 839 //
 840 //
 841 // CHECK1-LABEL: define {{[^@]+}}@.omp_task_privates_map.
 842 // CHECK1-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]], ptr noalias noundef [[TMP3:%.*]], ptr noalias noundef [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] {
 843 // CHECK1-NEXT:  entry:
 844 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
 845 // CHECK1-NEXT:    [[DOTADDR1:%.*]] = alloca ptr, align 8
 846 // CHECK1-NEXT:    [[DOTADDR2:%.*]] = alloca ptr, align 8
 847 // CHECK1-NEXT:    [[DOTADDR3:%.*]] = alloca ptr, align 8
 848 // CHECK1-NEXT:    [[DOTADDR4:%.*]] = alloca ptr, align 8
 849 // CHECK1-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
 850 // CHECK1-NEXT:    store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
 851 // CHECK1-NEXT:    store ptr [[TMP2]], ptr [[DOTADDR2]], align 8
 852 // CHECK1-NEXT:    store ptr [[TMP3]], ptr [[DOTADDR3]], align 8
 853 // CHECK1-NEXT:    store ptr [[TMP4]], ptr [[DOTADDR4]], align 8
 854 // CHECK1-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[DOTADDR]], align 8
 855 // CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP5]], i32 0, i32 0
 856 // CHECK1-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[DOTADDR2]], align 8
 857 // CHECK1-NEXT:    store ptr [[TMP6]], ptr [[TMP7]], align 8
 858 // CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 1
 859 // CHECK1-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[DOTADDR3]], align 8
 860 // CHECK1-NEXT:    store ptr [[TMP8]], ptr [[TMP9]], align 8
 861 // CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 2
 862 // CHECK1-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[DOTADDR4]], align 8
 863 // CHECK1-NEXT:    store ptr [[TMP10]], ptr [[TMP11]], align 8
 864 // CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 3
 865 // CHECK1-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[DOTADDR1]], align 8
 866 // CHECK1-NEXT:    store ptr [[TMP12]], ptr [[TMP13]], align 8
 867 // CHECK1-NEXT:    ret void
 868 //
 869 //
 870 // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry.
 871 // CHECK1-SAME: (i32 noundef signext [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] {
 872 // CHECK1-NEXT:  entry:
 873 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
 874 // CHECK1-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8
 875 // CHECK1-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8
 876 // CHECK1-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8
 877 // CHECK1-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8
 878 // CHECK1-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8
 879 // CHECK1-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca ptr, align 8
 880 // CHECK1-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca ptr, align 8
 881 // CHECK1-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca ptr, align 8
 882 // CHECK1-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca ptr, align 8
 883 // CHECK1-NEXT:    [[KERNEL_ARGS_I:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
 884 // CHECK1-NEXT:    [[AA_CASTED_I:%.*]] = alloca i64, align 8
 885 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i64, align 8
 886 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR__CASTED4_I:%.*]] = alloca i64, align 8
 887 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 4
 888 // CHECK1-NEXT:    [[DOTADDR1:%.*]] = alloca ptr, align 8
 889 // CHECK1-NEXT:    store i32 [[TMP0]], ptr [[DOTADDR]], align 4
 890 // CHECK1-NEXT:    store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
 891 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4
 892 // CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8
 893 // CHECK1-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0
 894 // CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2
 895 // CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0
 896 // CHECK1-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8
 897 // CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 1
 898 // CHECK1-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]])
 899 // CHECK1-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])
 900 // CHECK1-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])
 901 // CHECK1-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]])
 902 // CHECK1-NEXT:    store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !25
 903 // CHECK1-NEXT:    store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias !25
 904 // CHECK1-NEXT:    store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias !25
 905 // CHECK1-NEXT:    store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !25
 906 // CHECK1-NEXT:    store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias !25
 907 // CHECK1-NEXT:    store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias !25
 908 // CHECK1-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias !25
 909 // CHECK1-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !25
 910 // CHECK1-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias !25
 911 // CHECK1-NEXT:    call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]
 912 // CHECK1-NEXT:    [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !25
 913 // CHECK1-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !25
 914 // CHECK1-NEXT:    [[TMP14:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !25
 915 // CHECK1-NEXT:    [[TMP15:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !25
 916 // CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP9]], i32 0, i32 1
 917 // CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP9]], i32 0, i32 2
 918 // CHECK1-NEXT:    [[TMP18:%.*]] = load i32, ptr [[TMP16]], align 4
 919 // CHECK1-NEXT:    [[TMP19:%.*]] = load i32, ptr [[TMP17]], align 4
 920 // CHECK1-NEXT:    [[TMP20:%.*]] = insertvalue [3 x i32] zeroinitializer, i32 [[TMP18]], 0
 921 // CHECK1-NEXT:    [[TMP21:%.*]] = insertvalue [3 x i32] zeroinitializer, i32 [[TMP19]], 0
 922 // CHECK1-NEXT:    store i32 2, ptr [[KERNEL_ARGS_I]], align 4, !noalias !25
 923 // CHECK1-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 1
 924 // CHECK1-NEXT:    store i32 3, ptr [[TMP22]], align 4, !noalias !25
 925 // CHECK1-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 2
 926 // CHECK1-NEXT:    store ptr [[TMP13]], ptr [[TMP23]], align 8, !noalias !25
 927 // CHECK1-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 3
 928 // CHECK1-NEXT:    store ptr [[TMP14]], ptr [[TMP24]], align 8, !noalias !25
 929 // CHECK1-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 4
 930 // CHECK1-NEXT:    store ptr [[TMP15]], ptr [[TMP25]], align 8, !noalias !25
 931 // CHECK1-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 5
 932 // CHECK1-NEXT:    store ptr @.offload_maptypes, ptr [[TMP26]], align 8, !noalias !25
 933 // CHECK1-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 6
 934 // CHECK1-NEXT:    store ptr null, ptr [[TMP27]], align 8, !noalias !25
 935 // CHECK1-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 7
 936 // CHECK1-NEXT:    store ptr null, ptr [[TMP28]], align 8, !noalias !25
 937 // CHECK1-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 8
 938 // CHECK1-NEXT:    store i64 0, ptr [[TMP29]], align 8, !noalias !25
 939 // CHECK1-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 9
 940 // CHECK1-NEXT:    store i64 1, ptr [[TMP30]], align 8, !noalias !25
 941 // CHECK1-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 10
 942 // CHECK1-NEXT:    store [3 x i32] [[TMP20]], ptr [[TMP31]], align 4, !noalias !25
 943 // CHECK1-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 11
 944 // CHECK1-NEXT:    store [3 x i32] [[TMP21]], ptr [[TMP32]], align 4, !noalias !25
 945 // CHECK1-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 12
 946 // CHECK1-NEXT:    store i32 0, ptr [[TMP33]], align 4, !noalias !25
 947 // CHECK1-NEXT:    [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 [[TMP18]], i32 [[TMP19]], ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.region_id, ptr [[KERNEL_ARGS_I]])
 948 // CHECK1-NEXT:    [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0
 949 // CHECK1-NEXT:    br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]]
 950 // CHECK1:       omp_offload.failed.i:
 951 // CHECK1-NEXT:    [[TMP36:%.*]] = load i16, ptr [[TMP12]], align 2
 952 // CHECK1-NEXT:    store i16 [[TMP36]], ptr [[AA_CASTED_I]], align 2, !noalias !25
 953 // CHECK1-NEXT:    [[TMP37:%.*]] = load i64, ptr [[AA_CASTED_I]], align 8, !noalias !25
 954 // CHECK1-NEXT:    [[TMP38:%.*]] = load i32, ptr [[TMP16]], align 4
 955 // CHECK1-NEXT:    store i32 [[TMP38]], ptr [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !25
 956 // CHECK1-NEXT:    [[TMP39:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED_I]], align 8, !noalias !25
 957 // CHECK1-NEXT:    [[TMP40:%.*]] = load i32, ptr [[TMP17]], align 4
 958 // CHECK1-NEXT:    store i32 [[TMP40]], ptr [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !25
 959 // CHECK1-NEXT:    [[TMP41:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED4_I]], align 8, !noalias !25
 960 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i64 [[TMP37]], i64 [[TMP39]], i64 [[TMP41]]) #[[ATTR3]]
 961 // CHECK1-NEXT:    br label [[DOTOMP_OUTLINED__EXIT]]
 962 // CHECK1:       .omp_outlined..exit:
 963 // CHECK1-NEXT:    ret i32 0
 964 //
 965 //
 966 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105
 967 // CHECK1-SAME: (i64 noundef [[A:%.*]]) #[[ATTR2]] {
 968 // CHECK1-NEXT:  entry:
 969 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
 970 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
 971 // CHECK1-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
 972 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
 973 // CHECK1-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 4
 974 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8
 975 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105.omp_outlined, i64 [[TMP1]])
 976 // CHECK1-NEXT:    ret void
 977 //
 978 //
 979 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105.omp_outlined
 980 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] {
 981 // CHECK1-NEXT:  entry:
 982 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 983 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 984 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
 985 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 986 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 987 // CHECK1-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
 988 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
 989 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
 990 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 4
 991 // CHECK1-NEXT:    ret void
 992 //
 993 //
 994 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
 995 // CHECK1-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR2]] {
 996 // CHECK1-NEXT:  entry:
 997 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
 998 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
 999 // CHECK1-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
1000 // CHECK1-NEXT:    [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2
1001 // CHECK1-NEXT:    store i16 [[TMP0]], ptr [[AA_CASTED]], align 2
1002 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[AA_CASTED]], align 8
1003 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined, i64 [[TMP1]])
1004 // CHECK1-NEXT:    ret void
1005 //
1006 //
1007 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined
1008 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {
1009 // CHECK1-NEXT:  entry:
1010 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1011 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1012 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
1013 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1014 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1015 // CHECK1-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
1016 // CHECK1-NEXT:    [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2
1017 // CHECK1-NEXT:    [[CONV:%.*]] = sext i16 [[TMP0]] to i32
1018 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV]], 1
1019 // CHECK1-NEXT:    [[CONV1:%.*]] = trunc i32 [[ADD]] to i16
1020 // CHECK1-NEXT:    store i16 [[CONV1]], ptr [[AA_ADDR]], align 2
1021 // CHECK1-NEXT:    ret void
1022 //
1023 //
1024 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118
1025 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {
1026 // CHECK1-NEXT:  entry:
1027 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1028 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
1029 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
1030 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
1031 // CHECK1-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
1032 // CHECK1-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
1033 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
1034 // CHECK1-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 4
1035 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8
1036 // CHECK1-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2
1037 // CHECK1-NEXT:    store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
1038 // CHECK1-NEXT:    [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8
1039 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined, i64 [[TMP1]], i64 [[TMP3]])
1040 // CHECK1-NEXT:    ret void
1041 //
1042 //
1043 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined
1044 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {
1045 // CHECK1-NEXT:  entry:
1046 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1047 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1048 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1049 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
1050 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1051 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1052 // CHECK1-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
1053 // CHECK1-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
1054 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
1055 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
1056 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 4
1057 // CHECK1-NEXT:    [[TMP1:%.*]] = load i16, ptr [[AA_ADDR]], align 2
1058 // CHECK1-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
1059 // CHECK1-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
1060 // CHECK1-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
1061 // CHECK1-NEXT:    store i16 [[CONV2]], ptr [[AA_ADDR]], align 2
1062 // CHECK1-NEXT:    ret void
1063 //
1064 //
1065 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l124
1066 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {
1067 // CHECK1-NEXT:  entry:
1068 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1069 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
1070 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
1071 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
1072 // CHECK1-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
1073 // CHECK1-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
1074 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
1075 // CHECK1-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 4
1076 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8
1077 // CHECK1-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2
1078 // CHECK1-NEXT:    store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
1079 // CHECK1-NEXT:    [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8
1080 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l124.omp_outlined, i64 [[TMP1]], i64 [[TMP3]])
1081 // CHECK1-NEXT:    ret void
1082 //
1083 //
1084 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l124.omp_outlined
1085 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {
1086 // CHECK1-NEXT:  entry:
1087 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1088 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1089 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1090 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
1091 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1092 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1093 // CHECK1-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
1094 // CHECK1-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
1095 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
1096 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
1097 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 4
1098 // CHECK1-NEXT:    [[TMP1:%.*]] = load i16, ptr [[AA_ADDR]], align 2
1099 // CHECK1-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
1100 // CHECK1-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
1101 // CHECK1-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
1102 // CHECK1-NEXT:    store i16 [[CONV2]], ptr [[AA_ADDR]], align 2
1103 // CHECK1-NEXT:    ret void
1104 //
1105 //
1106 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l148
1107 // CHECK1-SAME: (i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] {
1108 // CHECK1-NEXT:  entry:
1109 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1110 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
1111 // CHECK1-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
1112 // CHECK1-NEXT:    [[BN_ADDR:%.*]] = alloca ptr, align 8
1113 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
1114 // CHECK1-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
1115 // CHECK1-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
1116 // CHECK1-NEXT:    [[CN_ADDR:%.*]] = alloca ptr, align 8
1117 // CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
1118 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
1119 // CHECK1-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
1120 // CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
1121 // CHECK1-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
1122 // CHECK1-NEXT:    store ptr [[BN]], ptr [[BN_ADDR]], align 8
1123 // CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
1124 // CHECK1-NEXT:    store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
1125 // CHECK1-NEXT:    store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8
1126 // CHECK1-NEXT:    store ptr [[CN]], ptr [[CN_ADDR]], align 8
1127 // CHECK1-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
1128 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
1129 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
1130 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8
1131 // CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
1132 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
1133 // CHECK1-NEXT:    [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8
1134 // CHECK1-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8
1135 // CHECK1-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8
1136 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
1137 // CHECK1-NEXT:    store i32 [[TMP8]], ptr [[A_CASTED]], align 4
1138 // CHECK1-NEXT:    [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 8
1139 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l148.omp_outlined, i64 [[TMP9]], ptr [[TMP0]], i64 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]])
1140 // CHECK1-NEXT:    ret void
1141 //
1142 //
1143 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l148.omp_outlined
1144 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] {
1145 // CHECK1-NEXT:  entry:
1146 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1147 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1148 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1149 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
1150 // CHECK1-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
1151 // CHECK1-NEXT:    [[BN_ADDR:%.*]] = alloca ptr, align 8
1152 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
1153 // CHECK1-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
1154 // CHECK1-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
1155 // CHECK1-NEXT:    [[CN_ADDR:%.*]] = alloca ptr, align 8
1156 // CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
1157 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1158 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1159 // CHECK1-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
1160 // CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
1161 // CHECK1-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
1162 // CHECK1-NEXT:    store ptr [[BN]], ptr [[BN_ADDR]], align 8
1163 // CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
1164 // CHECK1-NEXT:    store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
1165 // CHECK1-NEXT:    store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8
1166 // CHECK1-NEXT:    store ptr [[CN]], ptr [[CN_ADDR]], align 8
1167 // CHECK1-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
1168 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
1169 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
1170 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8
1171 // CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
1172 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
1173 // CHECK1-NEXT:    [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8
1174 // CHECK1-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8
1175 // CHECK1-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8
1176 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
1177 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
1178 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 4
1179 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 2
1180 // CHECK1-NEXT:    [[TMP9:%.*]] = load float, ptr [[ARRAYIDX]], align 4
1181 // CHECK1-NEXT:    [[CONV:%.*]] = fpext float [[TMP9]] to double
1182 // CHECK1-NEXT:    [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00
1183 // CHECK1-NEXT:    [[CONV6:%.*]] = fptrunc double [[ADD5]] to float
1184 // CHECK1-NEXT:    store float [[CONV6]], ptr [[ARRAYIDX]], align 4
1185 // CHECK1-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 3
1186 // CHECK1-NEXT:    [[TMP10:%.*]] = load float, ptr [[ARRAYIDX7]], align 4
1187 // CHECK1-NEXT:    [[CONV8:%.*]] = fpext float [[TMP10]] to double
1188 // CHECK1-NEXT:    [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00
1189 // CHECK1-NEXT:    [[CONV10:%.*]] = fptrunc double [[ADD9]] to float
1190 // CHECK1-NEXT:    store float [[CONV10]], ptr [[ARRAYIDX7]], align 4
1191 // CHECK1-NEXT:    [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 1
1192 // CHECK1-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX11]], i64 0, i64 2
1193 // CHECK1-NEXT:    [[TMP11:%.*]] = load double, ptr [[ARRAYIDX12]], align 8
1194 // CHECK1-NEXT:    [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00
1195 // CHECK1-NEXT:    store double [[ADD13]], ptr [[ARRAYIDX12]], align 8
1196 // CHECK1-NEXT:    [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]]
1197 // CHECK1-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i64 [[TMP12]]
1198 // CHECK1-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX14]], i64 3
1199 // CHECK1-NEXT:    [[TMP13:%.*]] = load double, ptr [[ARRAYIDX15]], align 8
1200 // CHECK1-NEXT:    [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00
1201 // CHECK1-NEXT:    store double [[ADD16]], ptr [[ARRAYIDX15]], align 8
1202 // CHECK1-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0
1203 // CHECK1-NEXT:    [[TMP14:%.*]] = load i64, ptr [[X]], align 8
1204 // CHECK1-NEXT:    [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1
1205 // CHECK1-NEXT:    store i64 [[ADD17]], ptr [[X]], align 8
1206 // CHECK1-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1
1207 // CHECK1-NEXT:    [[TMP15:%.*]] = load i8, ptr [[Y]], align 8
1208 // CHECK1-NEXT:    [[CONV18:%.*]] = sext i8 [[TMP15]] to i32
1209 // CHECK1-NEXT:    [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1
1210 // CHECK1-NEXT:    [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8
1211 // CHECK1-NEXT:    store i8 [[CONV20]], ptr [[Y]], align 8
1212 // CHECK1-NEXT:    ret void
1213 //
1214 //
1215 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160
1216 // CHECK1-SAME: (i64 noundef [[NN:%.*]]) #[[ATTR2]] {
1217 // CHECK1-NEXT:  entry:
1218 // CHECK1-NEXT:    [[NN_ADDR:%.*]] = alloca i64, align 8
1219 // CHECK1-NEXT:    [[NN_CASTED:%.*]] = alloca i64, align 8
1220 // CHECK1-NEXT:    store i64 [[NN]], ptr [[NN_ADDR]], align 8
1221 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[NN_ADDR]], align 4
1222 // CHECK1-NEXT:    store i32 [[TMP0]], ptr [[NN_CASTED]], align 4
1223 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[NN_CASTED]], align 8
1224 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined, i64 [[TMP1]])
1225 // CHECK1-NEXT:    ret void
1226 //
1227 //
1228 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined
1229 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR2]] {
1230 // CHECK1-NEXT:  entry:
1231 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1232 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1233 // CHECK1-NEXT:    [[NN_ADDR:%.*]] = alloca i64, align 8
1234 // CHECK1-NEXT:    [[NN_CASTED:%.*]] = alloca i64, align 8
1235 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1236 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1237 // CHECK1-NEXT:    store i64 [[NN]], ptr [[NN_ADDR]], align 8
1238 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[NN_ADDR]], align 4
1239 // CHECK1-NEXT:    store i32 [[TMP0]], ptr [[NN_CASTED]], align 4
1240 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[NN_CASTED]], align 8
1241 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined.omp_outlined, i64 [[TMP1]])
1242 // CHECK1-NEXT:    ret void
1243 //
1244 //
1245 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined.omp_outlined
1246 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR2]] {
1247 // CHECK1-NEXT:  entry:
1248 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1249 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1250 // CHECK1-NEXT:    [[NN_ADDR:%.*]] = alloca i64, align 8
1251 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1252 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1253 // CHECK1-NEXT:    store i64 [[NN]], ptr [[NN_ADDR]], align 8
1254 // CHECK1-NEXT:    ret void
1255 //
1256 //
1257 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l163
1258 // CHECK1-SAME: (i64 noundef [[NN:%.*]]) #[[ATTR2]] {
1259 // CHECK1-NEXT:  entry:
1260 // CHECK1-NEXT:    [[NN_ADDR:%.*]] = alloca i64, align 8
1261 // CHECK1-NEXT:    [[NN_CASTED:%.*]] = alloca i64, align 8
1262 // CHECK1-NEXT:    store i64 [[NN]], ptr [[NN_ADDR]], align 8
1263 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[NN_ADDR]], align 4
1264 // CHECK1-NEXT:    store i32 [[TMP0]], ptr [[NN_CASTED]], align 4
1265 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[NN_CASTED]], align 8
1266 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l163.omp_outlined, i64 [[TMP1]])
1267 // CHECK1-NEXT:    ret void
1268 //
1269 //
1270 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l163.omp_outlined
1271 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR2]] {
1272 // CHECK1-NEXT:  entry:
1273 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1274 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1275 // CHECK1-NEXT:    [[NN_ADDR:%.*]] = alloca i64, align 8
1276 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1277 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1278 // CHECK1-NEXT:    store i64 [[NN]], ptr [[NN_ADDR]], align 8
1279 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l163.omp_outlined.omp_outlined, ptr [[NN_ADDR]])
1280 // CHECK1-NEXT:    ret void
1281 //
1282 //
1283 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l163.omp_outlined.omp_outlined
1284 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR2]] {
1285 // CHECK1-NEXT:  entry:
1286 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1287 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1288 // CHECK1-NEXT:    [[NN_ADDR:%.*]] = alloca ptr, align 8
1289 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1290 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1291 // CHECK1-NEXT:    store ptr [[NN]], ptr [[NN_ADDR]], align 8
1292 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[NN_ADDR]], align 8
1293 // CHECK1-NEXT:    ret void
1294 //
1295 //
1296 // CHECK1-LABEL: define {{[^@]+}}@_Z6bazzzziPi
1297 // CHECK1-SAME: (i32 noundef signext [[N:%.*]], ptr noundef [[F:%.*]]) #[[ATTR0]] {
1298 // CHECK1-NEXT:  entry:
1299 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
1300 // CHECK1-NEXT:    [[F_ADDR:%.*]] = alloca ptr, align 8
1301 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8
1302 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8
1303 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8
1304 // CHECK1-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1305 // CHECK1-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
1306 // CHECK1-NEXT:    store ptr [[F]], ptr [[F_ADDR]], align 8
1307 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
1308 // CHECK1-NEXT:    [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
1309 // CHECK1-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1310 // CHECK1-NEXT:    store i64 [[TMP1]], ptr [[TMP2]], align 8
1311 // CHECK1-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1312 // CHECK1-NEXT:    store i64 [[TMP1]], ptr [[TMP3]], align 8
1313 // CHECK1-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
1314 // CHECK1-NEXT:    store ptr null, ptr [[TMP4]], align 8
1315 // CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1316 // CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1317 // CHECK1-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
1318 // CHECK1-NEXT:    store i32 2, ptr [[TMP7]], align 4
1319 // CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
1320 // CHECK1-NEXT:    store i32 1, ptr [[TMP8]], align 4
1321 // CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
1322 // CHECK1-NEXT:    store ptr [[TMP5]], ptr [[TMP9]], align 8
1323 // CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
1324 // CHECK1-NEXT:    store ptr [[TMP6]], ptr [[TMP10]], align 8
1325 // CHECK1-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
1326 // CHECK1-NEXT:    store ptr @.offload_sizes.13, ptr [[TMP11]], align 8
1327 // CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
1328 // CHECK1-NEXT:    store ptr @.offload_maptypes.14, ptr [[TMP12]], align 8
1329 // CHECK1-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
1330 // CHECK1-NEXT:    store ptr null, ptr [[TMP13]], align 8
1331 // CHECK1-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
1332 // CHECK1-NEXT:    store ptr null, ptr [[TMP14]], align 8
1333 // CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
1334 // CHECK1-NEXT:    store i64 0, ptr [[TMP15]], align 8
1335 // CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
1336 // CHECK1-NEXT:    store i64 0, ptr [[TMP16]], align 8
1337 // CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
1338 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP17]], align 4
1339 // CHECK1-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
1340 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP18]], align 4
1341 // CHECK1-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
1342 // CHECK1-NEXT:    store i32 0, ptr [[TMP19]], align 4
1343 // CHECK1-NEXT:    [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l188.region_id, ptr [[KERNEL_ARGS]])
1344 // CHECK1-NEXT:    [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
1345 // CHECK1-NEXT:    br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1346 // CHECK1:       omp_offload.failed:
1347 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l188(i64 [[TMP1]]) #[[ATTR3]]
1348 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
1349 // CHECK1:       omp_offload.cont:
1350 // CHECK1-NEXT:    ret void
1351 //
1352 //
1353 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l188
1354 // CHECK1-SAME: (i64 noundef [[VLA:%.*]]) #[[ATTR2]] {
1355 // CHECK1-NEXT:  entry:
1356 // CHECK1-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
1357 // CHECK1-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
1358 // CHECK1-NEXT:    [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
1359 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l188.omp_outlined, i64 [[TMP0]])
1360 // CHECK1-NEXT:    ret void
1361 //
1362 //
1363 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l188.omp_outlined
1364 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]]) #[[ATTR2]] {
1365 // CHECK1-NEXT:  entry:
1366 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1367 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1368 // CHECK1-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
1369 // CHECK1-NEXT:    [[F:%.*]] = alloca ptr, align 8
1370 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1371 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1372 // CHECK1-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
1373 // CHECK1-NEXT:    [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
1374 // CHECK1-NEXT:    ret void
1375 //
1376 //
1377 // CHECK1-LABEL: define {{[^@]+}}@_Z3bari
1378 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
1379 // CHECK1-NEXT:  entry:
1380 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
1381 // CHECK1-NEXT:    [[A:%.*]] = alloca i32, align 4
1382 // CHECK1-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
1383 // CHECK1-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
1384 // CHECK1-NEXT:    store i32 0, ptr [[A]], align 4
1385 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
1386 // CHECK1-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]])
1387 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A]], align 4
1388 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
1389 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[A]], align 4
1390 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
1391 // CHECK1-NEXT:    [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(ptr noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]])
1392 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A]], align 4
1393 // CHECK1-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
1394 // CHECK1-NEXT:    store i32 [[ADD2]], ptr [[A]], align 4
1395 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
1396 // CHECK1-NEXT:    [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]])
1397 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[A]], align 4
1398 // CHECK1-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
1399 // CHECK1-NEXT:    store i32 [[ADD4]], ptr [[A]], align 4
1400 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4
1401 // CHECK1-NEXT:    [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]])
1402 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[A]], align 4
1403 // CHECK1-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
1404 // CHECK1-NEXT:    store i32 [[ADD6]], ptr [[A]], align 4
1405 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A]], align 4
1406 // CHECK1-NEXT:    ret i32 [[TMP8]]
1407 //
1408 //
1409 // CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
1410 // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
1411 // CHECK1-NEXT:  entry:
1412 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1413 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
1414 // CHECK1-NEXT:    [[B:%.*]] = alloca i32, align 4
1415 // CHECK1-NEXT:    [[SAVED_STACK:%.*]] = alloca ptr, align 8
1416 // CHECK1-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
1417 // CHECK1-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
1418 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 8
1419 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 8
1420 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 8
1421 // CHECK1-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8
1422 // CHECK1-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1423 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1424 // CHECK1-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
1425 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1426 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
1427 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
1428 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[B]], align 4
1429 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
1430 // CHECK1-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
1431 // CHECK1-NEXT:    [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()
1432 // CHECK1-NEXT:    store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8
1433 // CHECK1-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
1434 // CHECK1-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
1435 // CHECK1-NEXT:    store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8
1436 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[B]], align 4
1437 // CHECK1-NEXT:    store i32 [[TMP5]], ptr [[B_CASTED]], align 4
1438 // CHECK1-NEXT:    [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 8
1439 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 4
1440 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60
1441 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
1442 // CHECK1:       omp_if.then:
1443 // CHECK1-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0
1444 // CHECK1-NEXT:    [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]]
1445 // CHECK1-NEXT:    [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2
1446 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes.15, i64 40, i1 false)
1447 // CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1448 // CHECK1-NEXT:    store ptr [[THIS1]], ptr [[TMP10]], align 8
1449 // CHECK1-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1450 // CHECK1-NEXT:    store ptr [[A]], ptr [[TMP11]], align 8
1451 // CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
1452 // CHECK1-NEXT:    store ptr null, ptr [[TMP12]], align 8
1453 // CHECK1-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1454 // CHECK1-NEXT:    store i64 [[TMP6]], ptr [[TMP13]], align 8
1455 // CHECK1-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1456 // CHECK1-NEXT:    store i64 [[TMP6]], ptr [[TMP14]], align 8
1457 // CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
1458 // CHECK1-NEXT:    store ptr null, ptr [[TMP15]], align 8
1459 // CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1460 // CHECK1-NEXT:    store i64 2, ptr [[TMP16]], align 8
1461 // CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1462 // CHECK1-NEXT:    store i64 2, ptr [[TMP17]], align 8
1463 // CHECK1-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
1464 // CHECK1-NEXT:    store ptr null, ptr [[TMP18]], align 8
1465 // CHECK1-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1466 // CHECK1-NEXT:    store i64 [[TMP2]], ptr [[TMP19]], align 8
1467 // CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1468 // CHECK1-NEXT:    store i64 [[TMP2]], ptr [[TMP20]], align 8
1469 // CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
1470 // CHECK1-NEXT:    store ptr null, ptr [[TMP21]], align 8
1471 // CHECK1-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
1472 // CHECK1-NEXT:    store ptr [[VLA]], ptr [[TMP22]], align 8
1473 // CHECK1-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4
1474 // CHECK1-NEXT:    store ptr [[VLA]], ptr [[TMP23]], align 8
1475 // CHECK1-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 4
1476 // CHECK1-NEXT:    store i64 [[TMP9]], ptr [[TMP24]], align 8
1477 // CHECK1-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
1478 // CHECK1-NEXT:    store ptr null, ptr [[TMP25]], align 8
1479 // CHECK1-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1480 // CHECK1-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1481 // CHECK1-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0
1482 // CHECK1-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
1483 // CHECK1-NEXT:    store i32 2, ptr [[TMP29]], align 4
1484 // CHECK1-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
1485 // CHECK1-NEXT:    store i32 5, ptr [[TMP30]], align 4
1486 // CHECK1-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
1487 // CHECK1-NEXT:    store ptr [[TMP26]], ptr [[TMP31]], align 8
1488 // CHECK1-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
1489 // CHECK1-NEXT:    store ptr [[TMP27]], ptr [[TMP32]], align 8
1490 // CHECK1-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
1491 // CHECK1-NEXT:    store ptr [[TMP28]], ptr [[TMP33]], align 8
1492 // CHECK1-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
1493 // CHECK1-NEXT:    store ptr @.offload_maptypes.16, ptr [[TMP34]], align 8
1494 // CHECK1-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
1495 // CHECK1-NEXT:    store ptr null, ptr [[TMP35]], align 8
1496 // CHECK1-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
1497 // CHECK1-NEXT:    store ptr null, ptr [[TMP36]], align 8
1498 // CHECK1-NEXT:    [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
1499 // CHECK1-NEXT:    store i64 0, ptr [[TMP37]], align 8
1500 // CHECK1-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
1501 // CHECK1-NEXT:    store i64 0, ptr [[TMP38]], align 8
1502 // CHECK1-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
1503 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP39]], align 4
1504 // CHECK1-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
1505 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP40]], align 4
1506 // CHECK1-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
1507 // CHECK1-NEXT:    store i32 0, ptr [[TMP41]], align 4
1508 // CHECK1-NEXT:    [[TMP42:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l233.region_id, ptr [[KERNEL_ARGS]])
1509 // CHECK1-NEXT:    [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0
1510 // CHECK1-NEXT:    br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1511 // CHECK1:       omp_offload.failed:
1512 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l233(ptr [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], ptr [[VLA]]) #[[ATTR3]]
1513 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
1514 // CHECK1:       omp_offload.cont:
1515 // CHECK1-NEXT:    br label [[OMP_IF_END:%.*]]
1516 // CHECK1:       omp_if.else:
1517 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l233(ptr [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], ptr [[VLA]]) #[[ATTR3]]
1518 // CHECK1-NEXT:    br label [[OMP_IF_END]]
1519 // CHECK1:       omp_if.end:
1520 // CHECK1-NEXT:    [[TMP44:%.*]] = mul nsw i64 1, [[TMP2]]
1521 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP44]]
1522 // CHECK1-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1
1523 // CHECK1-NEXT:    [[TMP45:%.*]] = load i16, ptr [[ARRAYIDX2]], align 2
1524 // CHECK1-NEXT:    [[CONV:%.*]] = sext i16 [[TMP45]] to i32
1525 // CHECK1-NEXT:    [[TMP46:%.*]] = load i32, ptr [[B]], align 4
1526 // CHECK1-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP46]]
1527 // CHECK1-NEXT:    [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
1528 // CHECK1-NEXT:    call void @llvm.stackrestore.p0(ptr [[TMP47]])
1529 // CHECK1-NEXT:    ret i32 [[ADD3]]
1530 //
1531 //
1532 // CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici
1533 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
1534 // CHECK1-NEXT:  entry:
1535 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
1536 // CHECK1-NEXT:    [[A:%.*]] = alloca i32, align 4
1537 // CHECK1-NEXT:    [[AA:%.*]] = alloca i16, align 2
1538 // CHECK1-NEXT:    [[AAA:%.*]] = alloca i8, align 1
1539 // CHECK1-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
1540 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
1541 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
1542 // CHECK1-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
1543 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 8
1544 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 8
1545 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 8
1546 // CHECK1-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1547 // CHECK1-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
1548 // CHECK1-NEXT:    store i32 0, ptr [[A]], align 4
1549 // CHECK1-NEXT:    store i16 0, ptr [[AA]], align 2
1550 // CHECK1-NEXT:    store i8 0, ptr [[AAA]], align 1
1551 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A]], align 4
1552 // CHECK1-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 4
1553 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8
1554 // CHECK1-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA]], align 2
1555 // CHECK1-NEXT:    store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
1556 // CHECK1-NEXT:    [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8
1557 // CHECK1-NEXT:    [[TMP4:%.*]] = load i8, ptr [[AAA]], align 1
1558 // CHECK1-NEXT:    store i8 [[TMP4]], ptr [[AAA_CASTED]], align 1
1559 // CHECK1-NEXT:    [[TMP5:%.*]] = load i64, ptr [[AAA_CASTED]], align 8
1560 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4
1561 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50
1562 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
1563 // CHECK1:       omp_if.then:
1564 // CHECK1-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1565 // CHECK1-NEXT:    store i64 [[TMP1]], ptr [[TMP7]], align 8
1566 // CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1567 // CHECK1-NEXT:    store i64 [[TMP1]], ptr [[TMP8]], align 8
1568 // CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
1569 // CHECK1-NEXT:    store ptr null, ptr [[TMP9]], align 8
1570 // CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1571 // CHECK1-NEXT:    store i64 [[TMP3]], ptr [[TMP10]], align 8
1572 // CHECK1-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1573 // CHECK1-NEXT:    store i64 [[TMP3]], ptr [[TMP11]], align 8
1574 // CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
1575 // CHECK1-NEXT:    store ptr null, ptr [[TMP12]], align 8
1576 // CHECK1-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1577 // CHECK1-NEXT:    store i64 [[TMP5]], ptr [[TMP13]], align 8
1578 // CHECK1-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1579 // CHECK1-NEXT:    store i64 [[TMP5]], ptr [[TMP14]], align 8
1580 // CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
1581 // CHECK1-NEXT:    store ptr null, ptr [[TMP15]], align 8
1582 // CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1583 // CHECK1-NEXT:    store ptr [[B]], ptr [[TMP16]], align 8
1584 // CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1585 // CHECK1-NEXT:    store ptr [[B]], ptr [[TMP17]], align 8
1586 // CHECK1-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
1587 // CHECK1-NEXT:    store ptr null, ptr [[TMP18]], align 8
1588 // CHECK1-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1589 // CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1590 // CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
1591 // CHECK1-NEXT:    store i32 2, ptr [[TMP21]], align 4
1592 // CHECK1-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
1593 // CHECK1-NEXT:    store i32 4, ptr [[TMP22]], align 4
1594 // CHECK1-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
1595 // CHECK1-NEXT:    store ptr [[TMP19]], ptr [[TMP23]], align 8
1596 // CHECK1-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
1597 // CHECK1-NEXT:    store ptr [[TMP20]], ptr [[TMP24]], align 8
1598 // CHECK1-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
1599 // CHECK1-NEXT:    store ptr @.offload_sizes.17, ptr [[TMP25]], align 8
1600 // CHECK1-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
1601 // CHECK1-NEXT:    store ptr @.offload_maptypes.18, ptr [[TMP26]], align 8
1602 // CHECK1-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
1603 // CHECK1-NEXT:    store ptr null, ptr [[TMP27]], align 8
1604 // CHECK1-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
1605 // CHECK1-NEXT:    store ptr null, ptr [[TMP28]], align 8
1606 // CHECK1-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
1607 // CHECK1-NEXT:    store i64 0, ptr [[TMP29]], align 8
1608 // CHECK1-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
1609 // CHECK1-NEXT:    store i64 0, ptr [[TMP30]], align 8
1610 // CHECK1-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
1611 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP31]], align 4
1612 // CHECK1-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
1613 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP32]], align 4
1614 // CHECK1-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
1615 // CHECK1-NEXT:    store i32 0, ptr [[TMP33]], align 4
1616 // CHECK1-NEXT:    [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l215.region_id, ptr [[KERNEL_ARGS]])
1617 // CHECK1-NEXT:    [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0
1618 // CHECK1-NEXT:    br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1619 // CHECK1:       omp_offload.failed:
1620 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l215(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], ptr [[B]]) #[[ATTR3]]
1621 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
1622 // CHECK1:       omp_offload.cont:
1623 // CHECK1-NEXT:    br label [[OMP_IF_END:%.*]]
1624 // CHECK1:       omp_if.else:
1625 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l215(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], ptr [[B]]) #[[ATTR3]]
1626 // CHECK1-NEXT:    br label [[OMP_IF_END]]
1627 // CHECK1:       omp_if.end:
1628 // CHECK1-NEXT:    [[TMP36:%.*]] = load i32, ptr [[A]], align 4
1629 // CHECK1-NEXT:    ret i32 [[TMP36]]
1630 //
1631 //
1632 // CHECK1-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
1633 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
1634 // CHECK1-NEXT:  entry:
1635 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
1636 // CHECK1-NEXT:    [[A:%.*]] = alloca i32, align 4
1637 // CHECK1-NEXT:    [[AA:%.*]] = alloca i16, align 2
1638 // CHECK1-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
1639 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
1640 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
1641 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8
1642 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 8
1643 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 8
1644 // CHECK1-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1645 // CHECK1-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
1646 // CHECK1-NEXT:    store i32 0, ptr [[A]], align 4
1647 // CHECK1-NEXT:    store i16 0, ptr [[AA]], align 2
1648 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A]], align 4
1649 // CHECK1-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 4
1650 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8
1651 // CHECK1-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA]], align 2
1652 // CHECK1-NEXT:    store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
1653 // CHECK1-NEXT:    [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8
1654 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
1655 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
1656 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
1657 // CHECK1:       omp_if.then:
1658 // CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1659 // CHECK1-NEXT:    store i64 [[TMP1]], ptr [[TMP5]], align 8
1660 // CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1661 // CHECK1-NEXT:    store i64 [[TMP1]], ptr [[TMP6]], align 8
1662 // CHECK1-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
1663 // CHECK1-NEXT:    store ptr null, ptr [[TMP7]], align 8
1664 // CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1665 // CHECK1-NEXT:    store i64 [[TMP3]], ptr [[TMP8]], align 8
1666 // CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1667 // CHECK1-NEXT:    store i64 [[TMP3]], ptr [[TMP9]], align 8
1668 // CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
1669 // CHECK1-NEXT:    store ptr null, ptr [[TMP10]], align 8
1670 // CHECK1-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1671 // CHECK1-NEXT:    store ptr [[B]], ptr [[TMP11]], align 8
1672 // CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1673 // CHECK1-NEXT:    store ptr [[B]], ptr [[TMP12]], align 8
1674 // CHECK1-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
1675 // CHECK1-NEXT:    store ptr null, ptr [[TMP13]], align 8
1676 // CHECK1-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1677 // CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1678 // CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
1679 // CHECK1-NEXT:    store i32 2, ptr [[TMP16]], align 4
1680 // CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
1681 // CHECK1-NEXT:    store i32 3, ptr [[TMP17]], align 4
1682 // CHECK1-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
1683 // CHECK1-NEXT:    store ptr [[TMP14]], ptr [[TMP18]], align 8
1684 // CHECK1-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
1685 // CHECK1-NEXT:    store ptr [[TMP15]], ptr [[TMP19]], align 8
1686 // CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
1687 // CHECK1-NEXT:    store ptr @.offload_sizes.19, ptr [[TMP20]], align 8
1688 // CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
1689 // CHECK1-NEXT:    store ptr @.offload_maptypes.20, ptr [[TMP21]], align 8
1690 // CHECK1-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
1691 // CHECK1-NEXT:    store ptr null, ptr [[TMP22]], align 8
1692 // CHECK1-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
1693 // CHECK1-NEXT:    store ptr null, ptr [[TMP23]], align 8
1694 // CHECK1-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
1695 // CHECK1-NEXT:    store i64 0, ptr [[TMP24]], align 8
1696 // CHECK1-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
1697 // CHECK1-NEXT:    store i64 0, ptr [[TMP25]], align 8
1698 // CHECK1-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
1699 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP26]], align 4
1700 // CHECK1-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
1701 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP27]], align 4
1702 // CHECK1-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
1703 // CHECK1-NEXT:    store i32 0, ptr [[TMP28]], align 4
1704 // CHECK1-NEXT:    [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l198.region_id, ptr [[KERNEL_ARGS]])
1705 // CHECK1-NEXT:    [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
1706 // CHECK1-NEXT:    br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1707 // CHECK1:       omp_offload.failed:
1708 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l198(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR3]]
1709 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
1710 // CHECK1:       omp_offload.cont:
1711 // CHECK1-NEXT:    br label [[OMP_IF_END:%.*]]
1712 // CHECK1:       omp_if.else:
1713 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l198(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR3]]
1714 // CHECK1-NEXT:    br label [[OMP_IF_END]]
1715 // CHECK1:       omp_if.end:
1716 // CHECK1-NEXT:    [[TMP31:%.*]] = load i32, ptr [[A]], align 4
1717 // CHECK1-NEXT:    ret i32 [[TMP31]]
1718 //
1719 //
1720 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l233
1721 // CHECK1-SAME: (ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
1722 // CHECK1-NEXT:  entry:
1723 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1724 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
1725 // CHECK1-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
1726 // CHECK1-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
1727 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
1728 // CHECK1-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
1729 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1730 // CHECK1-NEXT:    store i64 [[B]], ptr [[B_ADDR]], align 8
1731 // CHECK1-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
1732 // CHECK1-NEXT:    store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
1733 // CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
1734 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1735 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
1736 // CHECK1-NEXT:    [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
1737 // CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
1738 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4
1739 // CHECK1-NEXT:    store i32 [[TMP4]], ptr [[B_CASTED]], align 4
1740 // CHECK1-NEXT:    [[TMP5:%.*]] = load i64, ptr [[B_CASTED]], align 8
1741 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l233.omp_outlined, ptr [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], ptr [[TMP3]])
1742 // CHECK1-NEXT:    ret void
1743 //
1744 //
1745 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l233.omp_outlined
1746 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
1747 // CHECK1-NEXT:  entry:
1748 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1749 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1750 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1751 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
1752 // CHECK1-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
1753 // CHECK1-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
1754 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
1755 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1756 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1757 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1758 // CHECK1-NEXT:    store i64 [[B]], ptr [[B_ADDR]], align 8
1759 // CHECK1-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
1760 // CHECK1-NEXT:    store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
1761 // CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
1762 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1763 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
1764 // CHECK1-NEXT:    [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
1765 // CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
1766 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4
1767 // CHECK1-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP4]] to double
1768 // CHECK1-NEXT:    [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
1769 // CHECK1-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0
1770 // CHECK1-NEXT:    store double [[ADD]], ptr [[A]], align 8
1771 // CHECK1-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0
1772 // CHECK1-NEXT:    [[TMP5:%.*]] = load double, ptr [[A3]], align 8
1773 // CHECK1-NEXT:    [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
1774 // CHECK1-NEXT:    store double [[INC]], ptr [[A3]], align 8
1775 // CHECK1-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
1776 // CHECK1-NEXT:    [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]]
1777 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i64 [[TMP6]]
1778 // CHECK1-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1
1779 // CHECK1-NEXT:    store i16 [[CONV4]], ptr [[ARRAYIDX5]], align 2
1780 // CHECK1-NEXT:    ret void
1781 //
1782 //
1783 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l215
1784 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
1785 // CHECK1-NEXT:  entry:
1786 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1787 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
1788 // CHECK1-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
1789 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
1790 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
1791 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
1792 // CHECK1-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
1793 // CHECK1-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
1794 // CHECK1-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
1795 // CHECK1-NEXT:    store i64 [[AAA]], ptr [[AAA_ADDR]], align 8
1796 // CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
1797 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
1798 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
1799 // CHECK1-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 4
1800 // CHECK1-NEXT:    [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8
1801 // CHECK1-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
1802 // CHECK1-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
1803 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8
1804 // CHECK1-NEXT:    [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 1
1805 // CHECK1-NEXT:    store i8 [[TMP5]], ptr [[AAA_CASTED]], align 1
1806 // CHECK1-NEXT:    [[TMP6:%.*]] = load i64, ptr [[AAA_CASTED]], align 8
1807 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l215.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], ptr [[TMP0]])
1808 // CHECK1-NEXT:    ret void
1809 //
1810 //
1811 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l215.omp_outlined
1812 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
1813 // CHECK1-NEXT:  entry:
1814 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1815 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1816 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1817 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
1818 // CHECK1-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
1819 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
1820 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1821 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1822 // CHECK1-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
1823 // CHECK1-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
1824 // CHECK1-NEXT:    store i64 [[AAA]], ptr [[AAA_ADDR]], align 8
1825 // CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
1826 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
1827 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
1828 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
1829 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 4
1830 // CHECK1-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2
1831 // CHECK1-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i32
1832 // CHECK1-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
1833 // CHECK1-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
1834 // CHECK1-NEXT:    store i16 [[CONV2]], ptr [[AA_ADDR]], align 2
1835 // CHECK1-NEXT:    [[TMP3:%.*]] = load i8, ptr [[AAA_ADDR]], align 1
1836 // CHECK1-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP3]] to i32
1837 // CHECK1-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
1838 // CHECK1-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8
1839 // CHECK1-NEXT:    store i8 [[CONV5]], ptr [[AAA_ADDR]], align 1
1840 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2
1841 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
1842 // CHECK1-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP4]], 1
1843 // CHECK1-NEXT:    store i32 [[ADD6]], ptr [[ARRAYIDX]], align 4
1844 // CHECK1-NEXT:    ret void
1845 //
1846 //
1847 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l198
1848 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
1849 // CHECK1-NEXT:  entry:
1850 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1851 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
1852 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
1853 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
1854 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
1855 // CHECK1-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
1856 // CHECK1-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
1857 // CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
1858 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
1859 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
1860 // CHECK1-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 4
1861 // CHECK1-NEXT:    [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8
1862 // CHECK1-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
1863 // CHECK1-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
1864 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8
1865 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l198.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], ptr [[TMP0]])
1866 // CHECK1-NEXT:    ret void
1867 //
1868 //
1869 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l198.omp_outlined
1870 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
1871 // CHECK1-NEXT:  entry:
1872 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1873 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1874 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1875 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
1876 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
1877 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1878 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1879 // CHECK1-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
1880 // CHECK1-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
1881 // CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
1882 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
1883 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
1884 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
1885 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 4
1886 // CHECK1-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2
1887 // CHECK1-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i32
1888 // CHECK1-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
1889 // CHECK1-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
1890 // CHECK1-NEXT:    store i16 [[CONV2]], ptr [[AA_ADDR]], align 2
1891 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2
1892 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
1893 // CHECK1-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1
1894 // CHECK1-NEXT:    store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4
1895 // CHECK1-NEXT:    ret void
1896 //
1897 //
1898 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
1899 // CHECK1-SAME: () #[[ATTR4]] {
1900 // CHECK1-NEXT:  entry:
1901 // CHECK1-NEXT:    call void @__tgt_register_requires(i64 1)
1902 // CHECK1-NEXT:    ret void
1903 //
1904 //
1905 // CHECK3-LABEL: define {{[^@]+}}@_Z3fooi
1906 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] {
1907 // CHECK3-NEXT:  entry:
1908 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
1909 // CHECK3-NEXT:    [[A:%.*]] = alloca i32, align 4
1910 // CHECK3-NEXT:    [[AA:%.*]] = alloca i16, align 2
1911 // CHECK3-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
1912 // CHECK3-NEXT:    [[SAVED_STACK:%.*]] = alloca ptr, align 4
1913 // CHECK3-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
1914 // CHECK3-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
1915 // CHECK3-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
1916 // CHECK3-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
1917 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
1918 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
1919 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
1920 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
1921 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR__CASTED3:%.*]] = alloca i32, align 4
1922 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 4
1923 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 4
1924 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 4
1925 // CHECK3-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4
1926 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
1927 // CHECK3-NEXT:    [[AA_CASTED4:%.*]] = alloca i32, align 4
1928 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [1 x ptr], align 4
1929 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS6:%.*]] = alloca [1 x ptr], align 4
1930 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [1 x ptr], align 4
1931 // CHECK3-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1932 // CHECK3-NEXT:    [[A_CASTED8:%.*]] = alloca i32, align 4
1933 // CHECK3-NEXT:    [[AA_CASTED9:%.*]] = alloca i32, align 4
1934 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [2 x ptr], align 4
1935 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS11:%.*]] = alloca [2 x ptr], align 4
1936 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [2 x ptr], align 4
1937 // CHECK3-NEXT:    [[KERNEL_ARGS13:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
1938 // CHECK3-NEXT:    [[A_CASTED16:%.*]] = alloca i32, align 4
1939 // CHECK3-NEXT:    [[AA_CASTED17:%.*]] = alloca i32, align 4
1940 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS18:%.*]] = alloca [2 x ptr], align 4
1941 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS19:%.*]] = alloca [2 x ptr], align 4
1942 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS20:%.*]] = alloca [2 x ptr], align 4
1943 // CHECK3-NEXT:    [[KERNEL_ARGS21:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
1944 // CHECK3-NEXT:    [[A_CASTED24:%.*]] = alloca i32, align 4
1945 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS27:%.*]] = alloca [9 x ptr], align 4
1946 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS28:%.*]] = alloca [9 x ptr], align 4
1947 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS29:%.*]] = alloca [9 x ptr], align 4
1948 // CHECK3-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 4
1949 // CHECK3-NEXT:    [[KERNEL_ARGS30:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
1950 // CHECK3-NEXT:    [[NN:%.*]] = alloca i32, align 4
1951 // CHECK3-NEXT:    [[NN_CASTED:%.*]] = alloca i32, align 4
1952 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS35:%.*]] = alloca [1 x ptr], align 4
1953 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS36:%.*]] = alloca [1 x ptr], align 4
1954 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS37:%.*]] = alloca [1 x ptr], align 4
1955 // CHECK3-NEXT:    [[KERNEL_ARGS38:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
1956 // CHECK3-NEXT:    [[NN_CASTED41:%.*]] = alloca i32, align 4
1957 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS42:%.*]] = alloca [1 x ptr], align 4
1958 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS43:%.*]] = alloca [1 x ptr], align 4
1959 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS44:%.*]] = alloca [1 x ptr], align 4
1960 // CHECK3-NEXT:    [[KERNEL_ARGS45:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
1961 // CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
1962 // CHECK3-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
1963 // CHECK3-NEXT:    store i32 0, ptr [[A]], align 4
1964 // CHECK3-NEXT:    store i16 0, ptr [[AA]], align 2
1965 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
1966 // CHECK3-NEXT:    [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
1967 // CHECK3-NEXT:    store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4
1968 // CHECK3-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4
1969 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4
1970 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4
1971 // CHECK3-NEXT:    [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]]
1972 // CHECK3-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8
1973 // CHECK3-NEXT:    store i32 [[TMP3]], ptr [[__VLA_EXPR1]], align 4
1974 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[A]], align 4
1975 // CHECK3-NEXT:    store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_]], align 4
1976 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[A]], align 4
1977 // CHECK3-NEXT:    store i32 [[TMP6]], ptr [[DOTCAPTURE_EXPR_2]], align 4
1978 // CHECK3-NEXT:    [[TMP7:%.*]] = load i16, ptr [[AA]], align 2
1979 // CHECK3-NEXT:    store i16 [[TMP7]], ptr [[AA_CASTED]], align 2
1980 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[AA_CASTED]], align 4
1981 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1982 // CHECK3-NEXT:    store i32 [[TMP9]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
1983 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
1984 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
1985 // CHECK3-NEXT:    store i32 [[TMP11]], ptr [[DOTCAPTURE_EXPR__CASTED3]], align 4
1986 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED3]], align 4
1987 // CHECK3-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1988 // CHECK3-NEXT:    store i32 [[TMP8]], ptr [[TMP13]], align 4
1989 // CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1990 // CHECK3-NEXT:    store i32 [[TMP8]], ptr [[TMP14]], align 4
1991 // CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
1992 // CHECK3-NEXT:    store ptr null, ptr [[TMP15]], align 4
1993 // CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1994 // CHECK3-NEXT:    store i32 [[TMP10]], ptr [[TMP16]], align 4
1995 // CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1996 // CHECK3-NEXT:    store i32 [[TMP10]], ptr [[TMP17]], align 4
1997 // CHECK3-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
1998 // CHECK3-NEXT:    store ptr null, ptr [[TMP18]], align 4
1999 // CHECK3-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
2000 // CHECK3-NEXT:    store i32 [[TMP12]], ptr [[TMP19]], align 4
2001 // CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
2002 // CHECK3-NEXT:    store i32 [[TMP12]], ptr [[TMP20]], align 4
2003 // CHECK3-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
2004 // CHECK3-NEXT:    store ptr null, ptr [[TMP21]], align 4
2005 // CHECK3-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2006 // CHECK3-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2007 // CHECK3-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0
2008 // CHECK3-NEXT:    [[TMP25:%.*]] = load i16, ptr [[AA]], align 2
2009 // CHECK3-NEXT:    store i16 [[TMP25]], ptr [[TMP24]], align 4
2010 // CHECK3-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 1
2011 // CHECK3-NEXT:    [[TMP27:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
2012 // CHECK3-NEXT:    store i32 [[TMP27]], ptr [[TMP26]], align 4
2013 // CHECK3-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 2
2014 // CHECK3-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
2015 // CHECK3-NEXT:    store i32 [[TMP29]], ptr [[TMP28]], align 4
2016 // CHECK3-NEXT:    [[TMP30:%.*]] = call ptr @__kmpc_omp_target_task_alloc(ptr @[[GLOB1]], i32 [[TMP0]], i32 1, i32 72, i32 12, ptr @.omp_task_entry., i64 -1)
2017 // CHECK3-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP30]], i32 0, i32 0
2018 // CHECK3-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP31]], i32 0, i32 0
2019 // CHECK3-NEXT:    [[TMP33:%.*]] = load ptr, ptr [[TMP32]], align 4
2020 // CHECK3-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP33]], ptr align 4 [[AGG_CAPTURED]], i32 12, i1 false)
2021 // CHECK3-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP30]], i32 0, i32 1
2022 // CHECK3-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP34]], i32 0, i32 0
2023 // CHECK3-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP35]], ptr align 4 @.offload_sizes, i32 24, i1 false)
2024 // CHECK3-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP34]], i32 0, i32 1
2025 // CHECK3-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP36]], ptr align 4 [[TMP22]], i32 12, i1 false)
2026 // CHECK3-NEXT:    [[TMP37:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP34]], i32 0, i32 2
2027 // CHECK3-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP37]], ptr align 4 [[TMP23]], i32 12, i1 false)
2028 // CHECK3-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP34]], i32 0, i32 3
2029 // CHECK3-NEXT:    [[TMP39:%.*]] = load i16, ptr [[AA]], align 2
2030 // CHECK3-NEXT:    store i16 [[TMP39]], ptr [[TMP38]], align 4
2031 // CHECK3-NEXT:    [[TMP40:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB1]], i32 [[TMP0]], ptr [[TMP30]])
2032 // CHECK3-NEXT:    [[TMP41:%.*]] = load i32, ptr [[A]], align 4
2033 // CHECK3-NEXT:    store i32 [[TMP41]], ptr [[A_CASTED]], align 4
2034 // CHECK3-NEXT:    [[TMP42:%.*]] = load i32, ptr [[A_CASTED]], align 4
2035 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105(i32 [[TMP42]]) #[[ATTR3:[0-9]+]]
2036 // CHECK3-NEXT:    [[TMP43:%.*]] = load i16, ptr [[AA]], align 2
2037 // CHECK3-NEXT:    store i16 [[TMP43]], ptr [[AA_CASTED4]], align 2
2038 // CHECK3-NEXT:    [[TMP44:%.*]] = load i32, ptr [[AA_CASTED4]], align 4
2039 // CHECK3-NEXT:    [[TMP45:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0
2040 // CHECK3-NEXT:    store i32 [[TMP44]], ptr [[TMP45]], align 4
2041 // CHECK3-NEXT:    [[TMP46:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0
2042 // CHECK3-NEXT:    store i32 [[TMP44]], ptr [[TMP46]], align 4
2043 // CHECK3-NEXT:    [[TMP47:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 0
2044 // CHECK3-NEXT:    store ptr null, ptr [[TMP47]], align 4
2045 // CHECK3-NEXT:    [[TMP48:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0
2046 // CHECK3-NEXT:    [[TMP49:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0
2047 // CHECK3-NEXT:    [[TMP50:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
2048 // CHECK3-NEXT:    store i32 2, ptr [[TMP50]], align 4
2049 // CHECK3-NEXT:    [[TMP51:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
2050 // CHECK3-NEXT:    store i32 1, ptr [[TMP51]], align 4
2051 // CHECK3-NEXT:    [[TMP52:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
2052 // CHECK3-NEXT:    store ptr [[TMP48]], ptr [[TMP52]], align 4
2053 // CHECK3-NEXT:    [[TMP53:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
2054 // CHECK3-NEXT:    store ptr [[TMP49]], ptr [[TMP53]], align 4
2055 // CHECK3-NEXT:    [[TMP54:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
2056 // CHECK3-NEXT:    store ptr @.offload_sizes.1, ptr [[TMP54]], align 4
2057 // CHECK3-NEXT:    [[TMP55:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
2058 // CHECK3-NEXT:    store ptr @.offload_maptypes.2, ptr [[TMP55]], align 4
2059 // CHECK3-NEXT:    [[TMP56:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
2060 // CHECK3-NEXT:    store ptr null, ptr [[TMP56]], align 4
2061 // CHECK3-NEXT:    [[TMP57:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
2062 // CHECK3-NEXT:    store ptr null, ptr [[TMP57]], align 4
2063 // CHECK3-NEXT:    [[TMP58:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
2064 // CHECK3-NEXT:    store i64 0, ptr [[TMP58]], align 8
2065 // CHECK3-NEXT:    [[TMP59:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
2066 // CHECK3-NEXT:    store i64 0, ptr [[TMP59]], align 8
2067 // CHECK3-NEXT:    [[TMP60:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
2068 // CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP60]], align 4
2069 // CHECK3-NEXT:    [[TMP61:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
2070 // CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP61]], align 4
2071 // CHECK3-NEXT:    [[TMP62:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
2072 // CHECK3-NEXT:    store i32 0, ptr [[TMP62]], align 4
2073 // CHECK3-NEXT:    [[TMP63:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.region_id, ptr [[KERNEL_ARGS]])
2074 // CHECK3-NEXT:    [[TMP64:%.*]] = icmp ne i32 [[TMP63]], 0
2075 // CHECK3-NEXT:    br i1 [[TMP64]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
2076 // CHECK3:       omp_offload.failed:
2077 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i32 [[TMP44]]) #[[ATTR3]]
2078 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]
2079 // CHECK3:       omp_offload.cont:
2080 // CHECK3-NEXT:    [[TMP65:%.*]] = load i32, ptr [[A]], align 4
2081 // CHECK3-NEXT:    store i32 [[TMP65]], ptr [[A_CASTED8]], align 4
2082 // CHECK3-NEXT:    [[TMP66:%.*]] = load i32, ptr [[A_CASTED8]], align 4
2083 // CHECK3-NEXT:    [[TMP67:%.*]] = load i16, ptr [[AA]], align 2
2084 // CHECK3-NEXT:    store i16 [[TMP67]], ptr [[AA_CASTED9]], align 2
2085 // CHECK3-NEXT:    [[TMP68:%.*]] = load i32, ptr [[AA_CASTED9]], align 4
2086 // CHECK3-NEXT:    [[TMP69:%.*]] = load i32, ptr [[N_ADDR]], align 4
2087 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP69]], 10
2088 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
2089 // CHECK3:       omp_if.then:
2090 // CHECK3-NEXT:    [[TMP70:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
2091 // CHECK3-NEXT:    store i32 [[TMP66]], ptr [[TMP70]], align 4
2092 // CHECK3-NEXT:    [[TMP71:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
2093 // CHECK3-NEXT:    store i32 [[TMP66]], ptr [[TMP71]], align 4
2094 // CHECK3-NEXT:    [[TMP72:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS12]], i32 0, i32 0
2095 // CHECK3-NEXT:    store ptr null, ptr [[TMP72]], align 4
2096 // CHECK3-NEXT:    [[TMP73:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 1
2097 // CHECK3-NEXT:    store i32 [[TMP68]], ptr [[TMP73]], align 4
2098 // CHECK3-NEXT:    [[TMP74:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 1
2099 // CHECK3-NEXT:    store i32 [[TMP68]], ptr [[TMP74]], align 4
2100 // CHECK3-NEXT:    [[TMP75:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS12]], i32 0, i32 1
2101 // CHECK3-NEXT:    store ptr null, ptr [[TMP75]], align 4
2102 // CHECK3-NEXT:    [[TMP76:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
2103 // CHECK3-NEXT:    [[TMP77:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
2104 // CHECK3-NEXT:    [[TMP78:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 0
2105 // CHECK3-NEXT:    store i32 2, ptr [[TMP78]], align 4
2106 // CHECK3-NEXT:    [[TMP79:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 1
2107 // CHECK3-NEXT:    store i32 2, ptr [[TMP79]], align 4
2108 // CHECK3-NEXT:    [[TMP80:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 2
2109 // CHECK3-NEXT:    store ptr [[TMP76]], ptr [[TMP80]], align 4
2110 // CHECK3-NEXT:    [[TMP81:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 3
2111 // CHECK3-NEXT:    store ptr [[TMP77]], ptr [[TMP81]], align 4
2112 // CHECK3-NEXT:    [[TMP82:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 4
2113 // CHECK3-NEXT:    store ptr @.offload_sizes.3, ptr [[TMP82]], align 4
2114 // CHECK3-NEXT:    [[TMP83:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 5
2115 // CHECK3-NEXT:    store ptr @.offload_maptypes.4, ptr [[TMP83]], align 4
2116 // CHECK3-NEXT:    [[TMP84:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 6
2117 // CHECK3-NEXT:    store ptr null, ptr [[TMP84]], align 4
2118 // CHECK3-NEXT:    [[TMP85:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 7
2119 // CHECK3-NEXT:    store ptr null, ptr [[TMP85]], align 4
2120 // CHECK3-NEXT:    [[TMP86:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 8
2121 // CHECK3-NEXT:    store i64 0, ptr [[TMP86]], align 8
2122 // CHECK3-NEXT:    [[TMP87:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 9
2123 // CHECK3-NEXT:    store i64 0, ptr [[TMP87]], align 8
2124 // CHECK3-NEXT:    [[TMP88:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 10
2125 // CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP88]], align 4
2126 // CHECK3-NEXT:    [[TMP89:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 11
2127 // CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP89]], align 4
2128 // CHECK3-NEXT:    [[TMP90:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS13]], i32 0, i32 12
2129 // CHECK3-NEXT:    store i32 0, ptr [[TMP90]], align 4
2130 // CHECK3-NEXT:    [[TMP91:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.region_id, ptr [[KERNEL_ARGS13]])
2131 // CHECK3-NEXT:    [[TMP92:%.*]] = icmp ne i32 [[TMP91]], 0
2132 // CHECK3-NEXT:    br i1 [[TMP92]], label [[OMP_OFFLOAD_FAILED14:%.*]], label [[OMP_OFFLOAD_CONT15:%.*]]
2133 // CHECK3:       omp_offload.failed14:
2134 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP66]], i32 [[TMP68]]) #[[ATTR3]]
2135 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT15]]
2136 // CHECK3:       omp_offload.cont15:
2137 // CHECK3-NEXT:    br label [[OMP_IF_END:%.*]]
2138 // CHECK3:       omp_if.else:
2139 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP66]], i32 [[TMP68]]) #[[ATTR3]]
2140 // CHECK3-NEXT:    br label [[OMP_IF_END]]
2141 // CHECK3:       omp_if.end:
2142 // CHECK3-NEXT:    [[TMP93:%.*]] = load i32, ptr [[A]], align 4
2143 // CHECK3-NEXT:    store i32 [[TMP93]], ptr [[A_CASTED16]], align 4
2144 // CHECK3-NEXT:    [[TMP94:%.*]] = load i32, ptr [[A_CASTED16]], align 4
2145 // CHECK3-NEXT:    [[TMP95:%.*]] = load i16, ptr [[AA]], align 2
2146 // CHECK3-NEXT:    store i16 [[TMP95]], ptr [[AA_CASTED17]], align 2
2147 // CHECK3-NEXT:    [[TMP96:%.*]] = load i32, ptr [[AA_CASTED17]], align 4
2148 // CHECK3-NEXT:    [[TMP97:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 0
2149 // CHECK3-NEXT:    store i32 [[TMP94]], ptr [[TMP97]], align 4
2150 // CHECK3-NEXT:    [[TMP98:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS19]], i32 0, i32 0
2151 // CHECK3-NEXT:    store i32 [[TMP94]], ptr [[TMP98]], align 4
2152 // CHECK3-NEXT:    [[TMP99:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS20]], i32 0, i32 0
2153 // CHECK3-NEXT:    store ptr null, ptr [[TMP99]], align 4
2154 // CHECK3-NEXT:    [[TMP100:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 1
2155 // CHECK3-NEXT:    store i32 [[TMP96]], ptr [[TMP100]], align 4
2156 // CHECK3-NEXT:    [[TMP101:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS19]], i32 0, i32 1
2157 // CHECK3-NEXT:    store i32 [[TMP96]], ptr [[TMP101]], align 4
2158 // CHECK3-NEXT:    [[TMP102:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS20]], i32 0, i32 1
2159 // CHECK3-NEXT:    store ptr null, ptr [[TMP102]], align 4
2160 // CHECK3-NEXT:    [[TMP103:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS18]], i32 0, i32 0
2161 // CHECK3-NEXT:    [[TMP104:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS19]], i32 0, i32 0
2162 // CHECK3-NEXT:    [[TMP105:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 0
2163 // CHECK3-NEXT:    store i32 2, ptr [[TMP105]], align 4
2164 // CHECK3-NEXT:    [[TMP106:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 1
2165 // CHECK3-NEXT:    store i32 2, ptr [[TMP106]], align 4
2166 // CHECK3-NEXT:    [[TMP107:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 2
2167 // CHECK3-NEXT:    store ptr [[TMP103]], ptr [[TMP107]], align 4
2168 // CHECK3-NEXT:    [[TMP108:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 3
2169 // CHECK3-NEXT:    store ptr [[TMP104]], ptr [[TMP108]], align 4
2170 // CHECK3-NEXT:    [[TMP109:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 4
2171 // CHECK3-NEXT:    store ptr @.offload_sizes.5, ptr [[TMP109]], align 4
2172 // CHECK3-NEXT:    [[TMP110:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 5
2173 // CHECK3-NEXT:    store ptr @.offload_maptypes.6, ptr [[TMP110]], align 4
2174 // CHECK3-NEXT:    [[TMP111:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 6
2175 // CHECK3-NEXT:    store ptr null, ptr [[TMP111]], align 4
2176 // CHECK3-NEXT:    [[TMP112:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 7
2177 // CHECK3-NEXT:    store ptr null, ptr [[TMP112]], align 4
2178 // CHECK3-NEXT:    [[TMP113:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 8
2179 // CHECK3-NEXT:    store i64 0, ptr [[TMP113]], align 8
2180 // CHECK3-NEXT:    [[TMP114:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 9
2181 // CHECK3-NEXT:    store i64 0, ptr [[TMP114]], align 8
2182 // CHECK3-NEXT:    [[TMP115:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 10
2183 // CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP115]], align 4
2184 // CHECK3-NEXT:    [[TMP116:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 11
2185 // CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP116]], align 4
2186 // CHECK3-NEXT:    [[TMP117:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS21]], i32 0, i32 12
2187 // CHECK3-NEXT:    store i32 0, ptr [[TMP117]], align 4
2188 // CHECK3-NEXT:    [[TMP118:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l124.region_id, ptr [[KERNEL_ARGS21]])
2189 // CHECK3-NEXT:    [[TMP119:%.*]] = icmp ne i32 [[TMP118]], 0
2190 // CHECK3-NEXT:    br i1 [[TMP119]], label [[OMP_OFFLOAD_FAILED22:%.*]], label [[OMP_OFFLOAD_CONT23:%.*]]
2191 // CHECK3:       omp_offload.failed22:
2192 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l124(i32 [[TMP94]], i32 [[TMP96]]) #[[ATTR3]]
2193 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT23]]
2194 // CHECK3:       omp_offload.cont23:
2195 // CHECK3-NEXT:    [[TMP120:%.*]] = load i32, ptr [[A]], align 4
2196 // CHECK3-NEXT:    store i32 [[TMP120]], ptr [[A_CASTED24]], align 4
2197 // CHECK3-NEXT:    [[TMP121:%.*]] = load i32, ptr [[A_CASTED24]], align 4
2198 // CHECK3-NEXT:    [[TMP122:%.*]] = load i32, ptr [[N_ADDR]], align 4
2199 // CHECK3-NEXT:    [[CMP25:%.*]] = icmp sgt i32 [[TMP122]], 20
2200 // CHECK3-NEXT:    br i1 [[CMP25]], label [[OMP_IF_THEN26:%.*]], label [[OMP_IF_ELSE33:%.*]]
2201 // CHECK3:       omp_if.then26:
2202 // CHECK3-NEXT:    [[TMP123:%.*]] = mul nuw i32 [[TMP1]], 4
2203 // CHECK3-NEXT:    [[TMP124:%.*]] = sext i32 [[TMP123]] to i64
2204 // CHECK3-NEXT:    [[TMP125:%.*]] = mul nuw i32 5, [[TMP3]]
2205 // CHECK3-NEXT:    [[TMP126:%.*]] = mul nuw i32 [[TMP125]], 8
2206 // CHECK3-NEXT:    [[TMP127:%.*]] = sext i32 [[TMP126]] to i64
2207 // CHECK3-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes.7, i32 72, i1 false)
2208 // CHECK3-NEXT:    [[TMP128:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 0
2209 // CHECK3-NEXT:    store i32 [[TMP121]], ptr [[TMP128]], align 4
2210 // CHECK3-NEXT:    [[TMP129:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS28]], i32 0, i32 0
2211 // CHECK3-NEXT:    store i32 [[TMP121]], ptr [[TMP129]], align 4
2212 // CHECK3-NEXT:    [[TMP130:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS29]], i32 0, i32 0
2213 // CHECK3-NEXT:    store ptr null, ptr [[TMP130]], align 4
2214 // CHECK3-NEXT:    [[TMP131:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 1
2215 // CHECK3-NEXT:    store ptr [[B]], ptr [[TMP131]], align 4
2216 // CHECK3-NEXT:    [[TMP132:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS28]], i32 0, i32 1
2217 // CHECK3-NEXT:    store ptr [[B]], ptr [[TMP132]], align 4
2218 // CHECK3-NEXT:    [[TMP133:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS29]], i32 0, i32 1
2219 // CHECK3-NEXT:    store ptr null, ptr [[TMP133]], align 4
2220 // CHECK3-NEXT:    [[TMP134:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 2
2221 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[TMP134]], align 4
2222 // CHECK3-NEXT:    [[TMP135:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS28]], i32 0, i32 2
2223 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[TMP135]], align 4
2224 // CHECK3-NEXT:    [[TMP136:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS29]], i32 0, i32 2
2225 // CHECK3-NEXT:    store ptr null, ptr [[TMP136]], align 4
2226 // CHECK3-NEXT:    [[TMP137:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 3
2227 // CHECK3-NEXT:    store ptr [[VLA]], ptr [[TMP137]], align 4
2228 // CHECK3-NEXT:    [[TMP138:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS28]], i32 0, i32 3
2229 // CHECK3-NEXT:    store ptr [[VLA]], ptr [[TMP138]], align 4
2230 // CHECK3-NEXT:    [[TMP139:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 3
2231 // CHECK3-NEXT:    store i64 [[TMP124]], ptr [[TMP139]], align 4
2232 // CHECK3-NEXT:    [[TMP140:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS29]], i32 0, i32 3
2233 // CHECK3-NEXT:    store ptr null, ptr [[TMP140]], align 4
2234 // CHECK3-NEXT:    [[TMP141:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 4
2235 // CHECK3-NEXT:    store ptr [[C]], ptr [[TMP141]], align 4
2236 // CHECK3-NEXT:    [[TMP142:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS28]], i32 0, i32 4
2237 // CHECK3-NEXT:    store ptr [[C]], ptr [[TMP142]], align 4
2238 // CHECK3-NEXT:    [[TMP143:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS29]], i32 0, i32 4
2239 // CHECK3-NEXT:    store ptr null, ptr [[TMP143]], align 4
2240 // CHECK3-NEXT:    [[TMP144:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 5
2241 // CHECK3-NEXT:    store i32 5, ptr [[TMP144]], align 4
2242 // CHECK3-NEXT:    [[TMP145:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS28]], i32 0, i32 5
2243 // CHECK3-NEXT:    store i32 5, ptr [[TMP145]], align 4
2244 // CHECK3-NEXT:    [[TMP146:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS29]], i32 0, i32 5
2245 // CHECK3-NEXT:    store ptr null, ptr [[TMP146]], align 4
2246 // CHECK3-NEXT:    [[TMP147:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 6
2247 // CHECK3-NEXT:    store i32 [[TMP3]], ptr [[TMP147]], align 4
2248 // CHECK3-NEXT:    [[TMP148:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS28]], i32 0, i32 6
2249 // CHECK3-NEXT:    store i32 [[TMP3]], ptr [[TMP148]], align 4
2250 // CHECK3-NEXT:    [[TMP149:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS29]], i32 0, i32 6
2251 // CHECK3-NEXT:    store ptr null, ptr [[TMP149]], align 4
2252 // CHECK3-NEXT:    [[TMP150:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 7
2253 // CHECK3-NEXT:    store ptr [[VLA1]], ptr [[TMP150]], align 4
2254 // CHECK3-NEXT:    [[TMP151:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS28]], i32 0, i32 7
2255 // CHECK3-NEXT:    store ptr [[VLA1]], ptr [[TMP151]], align 4
2256 // CHECK3-NEXT:    [[TMP152:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 7
2257 // CHECK3-NEXT:    store i64 [[TMP127]], ptr [[TMP152]], align 4
2258 // CHECK3-NEXT:    [[TMP153:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS29]], i32 0, i32 7
2259 // CHECK3-NEXT:    store ptr null, ptr [[TMP153]], align 4
2260 // CHECK3-NEXT:    [[TMP154:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 8
2261 // CHECK3-NEXT:    store ptr [[D]], ptr [[TMP154]], align 4
2262 // CHECK3-NEXT:    [[TMP155:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS28]], i32 0, i32 8
2263 // CHECK3-NEXT:    store ptr [[D]], ptr [[TMP155]], align 4
2264 // CHECK3-NEXT:    [[TMP156:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS29]], i32 0, i32 8
2265 // CHECK3-NEXT:    store ptr null, ptr [[TMP156]], align 4
2266 // CHECK3-NEXT:    [[TMP157:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 0
2267 // CHECK3-NEXT:    [[TMP158:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS28]], i32 0, i32 0
2268 // CHECK3-NEXT:    [[TMP159:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0
2269 // CHECK3-NEXT:    [[TMP160:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 0
2270 // CHECK3-NEXT:    store i32 2, ptr [[TMP160]], align 4
2271 // CHECK3-NEXT:    [[TMP161:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 1
2272 // CHECK3-NEXT:    store i32 9, ptr [[TMP161]], align 4
2273 // CHECK3-NEXT:    [[TMP162:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 2
2274 // CHECK3-NEXT:    store ptr [[TMP157]], ptr [[TMP162]], align 4
2275 // CHECK3-NEXT:    [[TMP163:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 3
2276 // CHECK3-NEXT:    store ptr [[TMP158]], ptr [[TMP163]], align 4
2277 // CHECK3-NEXT:    [[TMP164:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 4
2278 // CHECK3-NEXT:    store ptr [[TMP159]], ptr [[TMP164]], align 4
2279 // CHECK3-NEXT:    [[TMP165:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 5
2280 // CHECK3-NEXT:    store ptr @.offload_maptypes.8, ptr [[TMP165]], align 4
2281 // CHECK3-NEXT:    [[TMP166:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 6
2282 // CHECK3-NEXT:    store ptr null, ptr [[TMP166]], align 4
2283 // CHECK3-NEXT:    [[TMP167:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 7
2284 // CHECK3-NEXT:    store ptr null, ptr [[TMP167]], align 4
2285 // CHECK3-NEXT:    [[TMP168:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 8
2286 // CHECK3-NEXT:    store i64 0, ptr [[TMP168]], align 8
2287 // CHECK3-NEXT:    [[TMP169:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 9
2288 // CHECK3-NEXT:    store i64 0, ptr [[TMP169]], align 8
2289 // CHECK3-NEXT:    [[TMP170:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 10
2290 // CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP170]], align 4
2291 // CHECK3-NEXT:    [[TMP171:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 11
2292 // CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP171]], align 4
2293 // CHECK3-NEXT:    [[TMP172:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS30]], i32 0, i32 12
2294 // CHECK3-NEXT:    store i32 0, ptr [[TMP172]], align 4
2295 // CHECK3-NEXT:    [[TMP173:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l148.region_id, ptr [[KERNEL_ARGS30]])
2296 // CHECK3-NEXT:    [[TMP174:%.*]] = icmp ne i32 [[TMP173]], 0
2297 // CHECK3-NEXT:    br i1 [[TMP174]], label [[OMP_OFFLOAD_FAILED31:%.*]], label [[OMP_OFFLOAD_CONT32:%.*]]
2298 // CHECK3:       omp_offload.failed31:
2299 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l148(i32 [[TMP121]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]]) #[[ATTR3]]
2300 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT32]]
2301 // CHECK3:       omp_offload.cont32:
2302 // CHECK3-NEXT:    br label [[OMP_IF_END34:%.*]]
2303 // CHECK3:       omp_if.else33:
2304 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l148(i32 [[TMP121]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]]) #[[ATTR3]]
2305 // CHECK3-NEXT:    br label [[OMP_IF_END34]]
2306 // CHECK3:       omp_if.end34:
2307 // CHECK3-NEXT:    store i32 0, ptr [[NN]], align 4
2308 // CHECK3-NEXT:    [[TMP175:%.*]] = load i32, ptr [[NN]], align 4
2309 // CHECK3-NEXT:    store i32 [[TMP175]], ptr [[NN_CASTED]], align 4
2310 // CHECK3-NEXT:    [[TMP176:%.*]] = load i32, ptr [[NN_CASTED]], align 4
2311 // CHECK3-NEXT:    [[TMP177:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS35]], i32 0, i32 0
2312 // CHECK3-NEXT:    store i32 [[TMP176]], ptr [[TMP177]], align 4
2313 // CHECK3-NEXT:    [[TMP178:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS36]], i32 0, i32 0
2314 // CHECK3-NEXT:    store i32 [[TMP176]], ptr [[TMP178]], align 4
2315 // CHECK3-NEXT:    [[TMP179:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS37]], i32 0, i32 0
2316 // CHECK3-NEXT:    store ptr null, ptr [[TMP179]], align 4
2317 // CHECK3-NEXT:    [[TMP180:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS35]], i32 0, i32 0
2318 // CHECK3-NEXT:    [[TMP181:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS36]], i32 0, i32 0
2319 // CHECK3-NEXT:    [[TMP182:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 0
2320 // CHECK3-NEXT:    store i32 2, ptr [[TMP182]], align 4
2321 // CHECK3-NEXT:    [[TMP183:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 1
2322 // CHECK3-NEXT:    store i32 1, ptr [[TMP183]], align 4
2323 // CHECK3-NEXT:    [[TMP184:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 2
2324 // CHECK3-NEXT:    store ptr [[TMP180]], ptr [[TMP184]], align 4
2325 // CHECK3-NEXT:    [[TMP185:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 3
2326 // CHECK3-NEXT:    store ptr [[TMP181]], ptr [[TMP185]], align 4
2327 // CHECK3-NEXT:    [[TMP186:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 4
2328 // CHECK3-NEXT:    store ptr @.offload_sizes.9, ptr [[TMP186]], align 4
2329 // CHECK3-NEXT:    [[TMP187:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 5
2330 // CHECK3-NEXT:    store ptr @.offload_maptypes.10, ptr [[TMP187]], align 4
2331 // CHECK3-NEXT:    [[TMP188:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 6
2332 // CHECK3-NEXT:    store ptr null, ptr [[TMP188]], align 4
2333 // CHECK3-NEXT:    [[TMP189:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 7
2334 // CHECK3-NEXT:    store ptr null, ptr [[TMP189]], align 4
2335 // CHECK3-NEXT:    [[TMP190:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 8
2336 // CHECK3-NEXT:    store i64 0, ptr [[TMP190]], align 8
2337 // CHECK3-NEXT:    [[TMP191:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 9
2338 // CHECK3-NEXT:    store i64 0, ptr [[TMP191]], align 8
2339 // CHECK3-NEXT:    [[TMP192:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 10
2340 // CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP192]], align 4
2341 // CHECK3-NEXT:    [[TMP193:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 11
2342 // CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP193]], align 4
2343 // CHECK3-NEXT:    [[TMP194:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS38]], i32 0, i32 12
2344 // CHECK3-NEXT:    store i32 0, ptr [[TMP194]], align 4
2345 // CHECK3-NEXT:    [[TMP195:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.region_id, ptr [[KERNEL_ARGS38]])
2346 // CHECK3-NEXT:    [[TMP196:%.*]] = icmp ne i32 [[TMP195]], 0
2347 // CHECK3-NEXT:    br i1 [[TMP196]], label [[OMP_OFFLOAD_FAILED39:%.*]], label [[OMP_OFFLOAD_CONT40:%.*]]
2348 // CHECK3:       omp_offload.failed39:
2349 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160(i32 [[TMP176]]) #[[ATTR3]]
2350 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT40]]
2351 // CHECK3:       omp_offload.cont40:
2352 // CHECK3-NEXT:    [[TMP197:%.*]] = load i32, ptr [[NN]], align 4
2353 // CHECK3-NEXT:    store i32 [[TMP197]], ptr [[NN_CASTED41]], align 4
2354 // CHECK3-NEXT:    [[TMP198:%.*]] = load i32, ptr [[NN_CASTED41]], align 4
2355 // CHECK3-NEXT:    [[TMP199:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS42]], i32 0, i32 0
2356 // CHECK3-NEXT:    store i32 [[TMP198]], ptr [[TMP199]], align 4
2357 // CHECK3-NEXT:    [[TMP200:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS43]], i32 0, i32 0
2358 // CHECK3-NEXT:    store i32 [[TMP198]], ptr [[TMP200]], align 4
2359 // CHECK3-NEXT:    [[TMP201:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS44]], i32 0, i32 0
2360 // CHECK3-NEXT:    store ptr null, ptr [[TMP201]], align 4
2361 // CHECK3-NEXT:    [[TMP202:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS42]], i32 0, i32 0
2362 // CHECK3-NEXT:    [[TMP203:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS43]], i32 0, i32 0
2363 // CHECK3-NEXT:    [[TMP204:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS45]], i32 0, i32 0
2364 // CHECK3-NEXT:    store i32 2, ptr [[TMP204]], align 4
2365 // CHECK3-NEXT:    [[TMP205:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS45]], i32 0, i32 1
2366 // CHECK3-NEXT:    store i32 1, ptr [[TMP205]], align 4
2367 // CHECK3-NEXT:    [[TMP206:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS45]], i32 0, i32 2
2368 // CHECK3-NEXT:    store ptr [[TMP202]], ptr [[TMP206]], align 4
2369 // CHECK3-NEXT:    [[TMP207:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS45]], i32 0, i32 3
2370 // CHECK3-NEXT:    store ptr [[TMP203]], ptr [[TMP207]], align 4
2371 // CHECK3-NEXT:    [[TMP208:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS45]], i32 0, i32 4
2372 // CHECK3-NEXT:    store ptr @.offload_sizes.11, ptr [[TMP208]], align 4
2373 // CHECK3-NEXT:    [[TMP209:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS45]], i32 0, i32 5
2374 // CHECK3-NEXT:    store ptr @.offload_maptypes.12, ptr [[TMP209]], align 4
2375 // CHECK3-NEXT:    [[TMP210:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS45]], i32 0, i32 6
2376 // CHECK3-NEXT:    store ptr null, ptr [[TMP210]], align 4
2377 // CHECK3-NEXT:    [[TMP211:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS45]], i32 0, i32 7
2378 // CHECK3-NEXT:    store ptr null, ptr [[TMP211]], align 4
2379 // CHECK3-NEXT:    [[TMP212:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS45]], i32 0, i32 8
2380 // CHECK3-NEXT:    store i64 0, ptr [[TMP212]], align 8
2381 // CHECK3-NEXT:    [[TMP213:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS45]], i32 0, i32 9
2382 // CHECK3-NEXT:    store i64 0, ptr [[TMP213]], align 8
2383 // CHECK3-NEXT:    [[TMP214:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS45]], i32 0, i32 10
2384 // CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP214]], align 4
2385 // CHECK3-NEXT:    [[TMP215:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS45]], i32 0, i32 11
2386 // CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP215]], align 4
2387 // CHECK3-NEXT:    [[TMP216:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS45]], i32 0, i32 12
2388 // CHECK3-NEXT:    store i32 0, ptr [[TMP216]], align 4
2389 // CHECK3-NEXT:    [[TMP217:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l163.region_id, ptr [[KERNEL_ARGS45]])
2390 // CHECK3-NEXT:    [[TMP218:%.*]] = icmp ne i32 [[TMP217]], 0
2391 // CHECK3-NEXT:    br i1 [[TMP218]], label [[OMP_OFFLOAD_FAILED46:%.*]], label [[OMP_OFFLOAD_CONT47:%.*]]
2392 // CHECK3:       omp_offload.failed46:
2393 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l163(i32 [[TMP198]]) #[[ATTR3]]
2394 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT47]]
2395 // CHECK3:       omp_offload.cont47:
2396 // CHECK3-NEXT:    [[TMP219:%.*]] = load i32, ptr [[A]], align 4
2397 // CHECK3-NEXT:    [[TMP220:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
2398 // CHECK3-NEXT:    call void @llvm.stackrestore.p0(ptr [[TMP220]])
2399 // CHECK3-NEXT:    ret i32 [[TMP219]]
2400 //
2401 //
2402 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101
2403 // CHECK3-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] {
2404 // CHECK3-NEXT:  entry:
2405 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
2406 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
2407 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4
2408 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
2409 // CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
2410 // CHECK3-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
2411 // CHECK3-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
2412 // CHECK3-NEXT:    store i32 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4
2413 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
2414 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4
2415 // CHECK3-NEXT:    call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
2416 // CHECK3-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
2417 // CHECK3-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
2418 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4
2419 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.omp_outlined, i32 [[TMP4]])
2420 // CHECK3-NEXT:    ret void
2421 //
2422 //
2423 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.omp_outlined
2424 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {
2425 // CHECK3-NEXT:  entry:
2426 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
2427 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
2428 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
2429 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
2430 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
2431 // CHECK3-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
2432 // CHECK3-NEXT:    ret void
2433 //
2434 //
2435 // CHECK3-LABEL: define {{[^@]+}}@.omp_task_privates_map.
2436 // CHECK3-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]], ptr noalias noundef [[TMP3:%.*]], ptr noalias noundef [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] {
2437 // CHECK3-NEXT:  entry:
2438 // CHECK3-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 4
2439 // CHECK3-NEXT:    [[DOTADDR1:%.*]] = alloca ptr, align 4
2440 // CHECK3-NEXT:    [[DOTADDR2:%.*]] = alloca ptr, align 4
2441 // CHECK3-NEXT:    [[DOTADDR3:%.*]] = alloca ptr, align 4
2442 // CHECK3-NEXT:    [[DOTADDR4:%.*]] = alloca ptr, align 4
2443 // CHECK3-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 4
2444 // CHECK3-NEXT:    store ptr [[TMP1]], ptr [[DOTADDR1]], align 4
2445 // CHECK3-NEXT:    store ptr [[TMP2]], ptr [[DOTADDR2]], align 4
2446 // CHECK3-NEXT:    store ptr [[TMP3]], ptr [[DOTADDR3]], align 4
2447 // CHECK3-NEXT:    store ptr [[TMP4]], ptr [[DOTADDR4]], align 4
2448 // CHECK3-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[DOTADDR]], align 4
2449 // CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP5]], i32 0, i32 0
2450 // CHECK3-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[DOTADDR4]], align 4
2451 // CHECK3-NEXT:    store ptr [[TMP6]], ptr [[TMP7]], align 4
2452 // CHECK3-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 1
2453 // CHECK3-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[DOTADDR2]], align 4
2454 // CHECK3-NEXT:    store ptr [[TMP8]], ptr [[TMP9]], align 4
2455 // CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 2
2456 // CHECK3-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[DOTADDR3]], align 4
2457 // CHECK3-NEXT:    store ptr [[TMP10]], ptr [[TMP11]], align 4
2458 // CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 3
2459 // CHECK3-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[DOTADDR1]], align 4
2460 // CHECK3-NEXT:    store ptr [[TMP12]], ptr [[TMP13]], align 4
2461 // CHECK3-NEXT:    ret void
2462 //
2463 //
2464 // CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry.
2465 // CHECK3-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] {
2466 // CHECK3-NEXT:  entry:
2467 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
2468 // CHECK3-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 4
2469 // CHECK3-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 4
2470 // CHECK3-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 4
2471 // CHECK3-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 4
2472 // CHECK3-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 4
2473 // CHECK3-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca ptr, align 4
2474 // CHECK3-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca ptr, align 4
2475 // CHECK3-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca ptr, align 4
2476 // CHECK3-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca ptr, align 4
2477 // CHECK3-NEXT:    [[KERNEL_ARGS_I:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
2478 // CHECK3-NEXT:    [[AA_CASTED_I:%.*]] = alloca i32, align 4
2479 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i32, align 4
2480 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR__CASTED4_I:%.*]] = alloca i32, align 4
2481 // CHECK3-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 4
2482 // CHECK3-NEXT:    [[DOTADDR1:%.*]] = alloca ptr, align 4
2483 // CHECK3-NEXT:    store i32 [[TMP0]], ptr [[DOTADDR]], align 4
2484 // CHECK3-NEXT:    store ptr [[TMP1]], ptr [[DOTADDR1]], align 4
2485 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4
2486 // CHECK3-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 4
2487 // CHECK3-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0
2488 // CHECK3-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2
2489 // CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0
2490 // CHECK3-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 4
2491 // CHECK3-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 1
2492 // CHECK3-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])
2493 // CHECK3-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
2494 // CHECK3-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])
2495 // CHECK3-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]])
2496 // CHECK3-NEXT:    store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !26
2497 // CHECK3-NEXT:    store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 4, !noalias !26
2498 // CHECK3-NEXT:    store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 4, !noalias !26
2499 // CHECK3-NEXT:    store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !26
2500 // CHECK3-NEXT:    store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 4, !noalias !26
2501 // CHECK3-NEXT:    store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 4, !noalias !26
2502 // CHECK3-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 4, !noalias !26
2503 // CHECK3-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !26
2504 // CHECK3-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 4, !noalias !26
2505 // CHECK3-NEXT:    call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]
2506 // CHECK3-NEXT:    [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !26
2507 // CHECK3-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !26
2508 // CHECK3-NEXT:    [[TMP14:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !26
2509 // CHECK3-NEXT:    [[TMP15:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !26
2510 // CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP9]], i32 0, i32 1
2511 // CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP9]], i32 0, i32 2
2512 // CHECK3-NEXT:    [[TMP18:%.*]] = load i32, ptr [[TMP16]], align 4
2513 // CHECK3-NEXT:    [[TMP19:%.*]] = load i32, ptr [[TMP17]], align 4
2514 // CHECK3-NEXT:    [[TMP20:%.*]] = insertvalue [3 x i32] zeroinitializer, i32 [[TMP18]], 0
2515 // CHECK3-NEXT:    [[TMP21:%.*]] = insertvalue [3 x i32] zeroinitializer, i32 [[TMP19]], 0
2516 // CHECK3-NEXT:    store i32 2, ptr [[KERNEL_ARGS_I]], align 4, !noalias !26
2517 // CHECK3-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 1
2518 // CHECK3-NEXT:    store i32 3, ptr [[TMP22]], align 4, !noalias !26
2519 // CHECK3-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 2
2520 // CHECK3-NEXT:    store ptr [[TMP13]], ptr [[TMP23]], align 4, !noalias !26
2521 // CHECK3-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 3
2522 // CHECK3-NEXT:    store ptr [[TMP14]], ptr [[TMP24]], align 4, !noalias !26
2523 // CHECK3-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 4
2524 // CHECK3-NEXT:    store ptr [[TMP15]], ptr [[TMP25]], align 4, !noalias !26
2525 // CHECK3-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 5
2526 // CHECK3-NEXT:    store ptr @.offload_maptypes, ptr [[TMP26]], align 4, !noalias !26
2527 // CHECK3-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 6
2528 // CHECK3-NEXT:    store ptr null, ptr [[TMP27]], align 4, !noalias !26
2529 // CHECK3-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 7
2530 // CHECK3-NEXT:    store ptr null, ptr [[TMP28]], align 4, !noalias !26
2531 // CHECK3-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 8
2532 // CHECK3-NEXT:    store i64 0, ptr [[TMP29]], align 8, !noalias !26
2533 // CHECK3-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 9
2534 // CHECK3-NEXT:    store i64 1, ptr [[TMP30]], align 8, !noalias !26
2535 // CHECK3-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 10
2536 // CHECK3-NEXT:    store [3 x i32] [[TMP20]], ptr [[TMP31]], align 4, !noalias !26
2537 // CHECK3-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 11
2538 // CHECK3-NEXT:    store [3 x i32] [[TMP21]], ptr [[TMP32]], align 4, !noalias !26
2539 // CHECK3-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 12
2540 // CHECK3-NEXT:    store i32 0, ptr [[TMP33]], align 4, !noalias !26
2541 // CHECK3-NEXT:    [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 [[TMP18]], i32 [[TMP19]], ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.region_id, ptr [[KERNEL_ARGS_I]])
2542 // CHECK3-NEXT:    [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0
2543 // CHECK3-NEXT:    br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]]
2544 // CHECK3:       omp_offload.failed.i:
2545 // CHECK3-NEXT:    [[TMP36:%.*]] = load i16, ptr [[TMP12]], align 2
2546 // CHECK3-NEXT:    store i16 [[TMP36]], ptr [[AA_CASTED_I]], align 2, !noalias !26
2547 // CHECK3-NEXT:    [[TMP37:%.*]] = load i32, ptr [[AA_CASTED_I]], align 4, !noalias !26
2548 // CHECK3-NEXT:    [[TMP38:%.*]] = load i32, ptr [[TMP16]], align 4
2549 // CHECK3-NEXT:    store i32 [[TMP38]], ptr [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !26
2550 // CHECK3-NEXT:    [[TMP39:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !26
2551 // CHECK3-NEXT:    [[TMP40:%.*]] = load i32, ptr [[TMP17]], align 4
2552 // CHECK3-NEXT:    store i32 [[TMP40]], ptr [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !26
2553 // CHECK3-NEXT:    [[TMP41:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !26
2554 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i32 [[TMP37]], i32 [[TMP39]], i32 [[TMP41]]) #[[ATTR3]]
2555 // CHECK3-NEXT:    br label [[DOTOMP_OUTLINED__EXIT]]
2556 // CHECK3:       .omp_outlined..exit:
2557 // CHECK3-NEXT:    ret i32 0
2558 //
2559 //
2560 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105
2561 // CHECK3-SAME: (i32 noundef [[A:%.*]]) #[[ATTR2]] {
2562 // CHECK3-NEXT:  entry:
2563 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2564 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
2565 // CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
2566 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
2567 // CHECK3-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 4
2568 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4
2569 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105.omp_outlined, i32 [[TMP1]])
2570 // CHECK3-NEXT:    ret void
2571 //
2572 //
2573 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105.omp_outlined
2574 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] {
2575 // CHECK3-NEXT:  entry:
2576 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
2577 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
2578 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2579 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
2580 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
2581 // CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
2582 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
2583 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
2584 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 4
2585 // CHECK3-NEXT:    ret void
2586 //
2587 //
2588 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
2589 // CHECK3-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR2]] {
2590 // CHECK3-NEXT:  entry:
2591 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
2592 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
2593 // CHECK3-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
2594 // CHECK3-NEXT:    [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2
2595 // CHECK3-NEXT:    store i16 [[TMP0]], ptr [[AA_CASTED]], align 2
2596 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[AA_CASTED]], align 4
2597 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined, i32 [[TMP1]])
2598 // CHECK3-NEXT:    ret void
2599 //
2600 //
2601 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined
2602 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {
2603 // CHECK3-NEXT:  entry:
2604 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
2605 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
2606 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
2607 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
2608 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
2609 // CHECK3-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
2610 // CHECK3-NEXT:    [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2
2611 // CHECK3-NEXT:    [[CONV:%.*]] = sext i16 [[TMP0]] to i32
2612 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV]], 1
2613 // CHECK3-NEXT:    [[CONV1:%.*]] = trunc i32 [[ADD]] to i16
2614 // CHECK3-NEXT:    store i16 [[CONV1]], ptr [[AA_ADDR]], align 2
2615 // CHECK3-NEXT:    ret void
2616 //
2617 //
2618 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118
2619 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {
2620 // CHECK3-NEXT:  entry:
2621 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2622 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
2623 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
2624 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
2625 // CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
2626 // CHECK3-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
2627 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
2628 // CHECK3-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 4
2629 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4
2630 // CHECK3-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2
2631 // CHECK3-NEXT:    store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
2632 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4
2633 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined, i32 [[TMP1]], i32 [[TMP3]])
2634 // CHECK3-NEXT:    ret void
2635 //
2636 //
2637 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined
2638 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {
2639 // CHECK3-NEXT:  entry:
2640 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
2641 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
2642 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2643 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
2644 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
2645 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
2646 // CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
2647 // CHECK3-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
2648 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
2649 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
2650 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 4
2651 // CHECK3-NEXT:    [[TMP1:%.*]] = load i16, ptr [[AA_ADDR]], align 2
2652 // CHECK3-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
2653 // CHECK3-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
2654 // CHECK3-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
2655 // CHECK3-NEXT:    store i16 [[CONV2]], ptr [[AA_ADDR]], align 2
2656 // CHECK3-NEXT:    ret void
2657 //
2658 //
2659 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l124
2660 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {
2661 // CHECK3-NEXT:  entry:
2662 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2663 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
2664 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
2665 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
2666 // CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
2667 // CHECK3-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
2668 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
2669 // CHECK3-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 4
2670 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4
2671 // CHECK3-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2
2672 // CHECK3-NEXT:    store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
2673 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4
2674 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l124.omp_outlined, i32 [[TMP1]], i32 [[TMP3]])
2675 // CHECK3-NEXT:    ret void
2676 //
2677 //
2678 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l124.omp_outlined
2679 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {
2680 // CHECK3-NEXT:  entry:
2681 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
2682 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
2683 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2684 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
2685 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
2686 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
2687 // CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
2688 // CHECK3-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
2689 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
2690 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
2691 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 4
2692 // CHECK3-NEXT:    [[TMP1:%.*]] = load i16, ptr [[AA_ADDR]], align 2
2693 // CHECK3-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
2694 // CHECK3-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
2695 // CHECK3-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
2696 // CHECK3-NEXT:    store i16 [[CONV2]], ptr [[AA_ADDR]], align 2
2697 // CHECK3-NEXT:    ret void
2698 //
2699 //
2700 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l148
2701 // CHECK3-SAME: (i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] {
2702 // CHECK3-NEXT:  entry:
2703 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2704 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
2705 // CHECK3-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
2706 // CHECK3-NEXT:    [[BN_ADDR:%.*]] = alloca ptr, align 4
2707 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
2708 // CHECK3-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
2709 // CHECK3-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
2710 // CHECK3-NEXT:    [[CN_ADDR:%.*]] = alloca ptr, align 4
2711 // CHECK3-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4
2712 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
2713 // CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
2714 // CHECK3-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
2715 // CHECK3-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
2716 // CHECK3-NEXT:    store ptr [[BN]], ptr [[BN_ADDR]], align 4
2717 // CHECK3-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
2718 // CHECK3-NEXT:    store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
2719 // CHECK3-NEXT:    store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4
2720 // CHECK3-NEXT:    store ptr [[CN]], ptr [[CN_ADDR]], align 4
2721 // CHECK3-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4
2722 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
2723 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
2724 // CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4
2725 // CHECK3-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
2726 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
2727 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4
2728 // CHECK3-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4
2729 // CHECK3-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4
2730 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
2731 // CHECK3-NEXT:    store i32 [[TMP8]], ptr [[A_CASTED]], align 4
2732 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4
2733 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l148.omp_outlined, i32 [[TMP9]], ptr [[TMP0]], i32 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]])
2734 // CHECK3-NEXT:    ret void
2735 //
2736 //
2737 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l148.omp_outlined
2738 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] {
2739 // CHECK3-NEXT:  entry:
2740 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
2741 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
2742 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2743 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
2744 // CHECK3-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
2745 // CHECK3-NEXT:    [[BN_ADDR:%.*]] = alloca ptr, align 4
2746 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
2747 // CHECK3-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
2748 // CHECK3-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
2749 // CHECK3-NEXT:    [[CN_ADDR:%.*]] = alloca ptr, align 4
2750 // CHECK3-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4
2751 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
2752 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
2753 // CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
2754 // CHECK3-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
2755 // CHECK3-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
2756 // CHECK3-NEXT:    store ptr [[BN]], ptr [[BN_ADDR]], align 4
2757 // CHECK3-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
2758 // CHECK3-NEXT:    store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
2759 // CHECK3-NEXT:    store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4
2760 // CHECK3-NEXT:    store ptr [[CN]], ptr [[CN_ADDR]], align 4
2761 // CHECK3-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4
2762 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
2763 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
2764 // CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4
2765 // CHECK3-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
2766 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
2767 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4
2768 // CHECK3-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4
2769 // CHECK3-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4
2770 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
2771 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
2772 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 4
2773 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 2
2774 // CHECK3-NEXT:    [[TMP9:%.*]] = load float, ptr [[ARRAYIDX]], align 4
2775 // CHECK3-NEXT:    [[CONV:%.*]] = fpext float [[TMP9]] to double
2776 // CHECK3-NEXT:    [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00
2777 // CHECK3-NEXT:    [[CONV6:%.*]] = fptrunc double [[ADD5]] to float
2778 // CHECK3-NEXT:    store float [[CONV6]], ptr [[ARRAYIDX]], align 4
2779 // CHECK3-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i32 3
2780 // CHECK3-NEXT:    [[TMP10:%.*]] = load float, ptr [[ARRAYIDX7]], align 4
2781 // CHECK3-NEXT:    [[CONV8:%.*]] = fpext float [[TMP10]] to double
2782 // CHECK3-NEXT:    [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00
2783 // CHECK3-NEXT:    [[CONV10:%.*]] = fptrunc double [[ADD9]] to float
2784 // CHECK3-NEXT:    store float [[CONV10]], ptr [[ARRAYIDX7]], align 4
2785 // CHECK3-NEXT:    [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 1
2786 // CHECK3-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX11]], i32 0, i32 2
2787 // CHECK3-NEXT:    [[TMP11:%.*]] = load double, ptr [[ARRAYIDX12]], align 8
2788 // CHECK3-NEXT:    [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00
2789 // CHECK3-NEXT:    store double [[ADD13]], ptr [[ARRAYIDX12]], align 8
2790 // CHECK3-NEXT:    [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]]
2791 // CHECK3-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i32 [[TMP12]]
2792 // CHECK3-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX14]], i32 3
2793 // CHECK3-NEXT:    [[TMP13:%.*]] = load double, ptr [[ARRAYIDX15]], align 8
2794 // CHECK3-NEXT:    [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00
2795 // CHECK3-NEXT:    store double [[ADD16]], ptr [[ARRAYIDX15]], align 8
2796 // CHECK3-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0
2797 // CHECK3-NEXT:    [[TMP14:%.*]] = load i64, ptr [[X]], align 4
2798 // CHECK3-NEXT:    [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1
2799 // CHECK3-NEXT:    store i64 [[ADD17]], ptr [[X]], align 4
2800 // CHECK3-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1
2801 // CHECK3-NEXT:    [[TMP15:%.*]] = load i8, ptr [[Y]], align 4
2802 // CHECK3-NEXT:    [[CONV18:%.*]] = sext i8 [[TMP15]] to i32
2803 // CHECK3-NEXT:    [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1
2804 // CHECK3-NEXT:    [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8
2805 // CHECK3-NEXT:    store i8 [[CONV20]], ptr [[Y]], align 4
2806 // CHECK3-NEXT:    ret void
2807 //
2808 //
2809 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160
2810 // CHECK3-SAME: (i32 noundef [[NN:%.*]]) #[[ATTR2]] {
2811 // CHECK3-NEXT:  entry:
2812 // CHECK3-NEXT:    [[NN_ADDR:%.*]] = alloca i32, align 4
2813 // CHECK3-NEXT:    [[NN_CASTED:%.*]] = alloca i32, align 4
2814 // CHECK3-NEXT:    store i32 [[NN]], ptr [[NN_ADDR]], align 4
2815 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[NN_ADDR]], align 4
2816 // CHECK3-NEXT:    store i32 [[TMP0]], ptr [[NN_CASTED]], align 4
2817 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[NN_CASTED]], align 4
2818 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined, i32 [[TMP1]])
2819 // CHECK3-NEXT:    ret void
2820 //
2821 //
2822 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined
2823 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR2]] {
2824 // CHECK3-NEXT:  entry:
2825 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
2826 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
2827 // CHECK3-NEXT:    [[NN_ADDR:%.*]] = alloca i32, align 4
2828 // CHECK3-NEXT:    [[NN_CASTED:%.*]] = alloca i32, align 4
2829 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
2830 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
2831 // CHECK3-NEXT:    store i32 [[NN]], ptr [[NN_ADDR]], align 4
2832 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[NN_ADDR]], align 4
2833 // CHECK3-NEXT:    store i32 [[TMP0]], ptr [[NN_CASTED]], align 4
2834 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[NN_CASTED]], align 4
2835 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined.omp_outlined, i32 [[TMP1]])
2836 // CHECK3-NEXT:    ret void
2837 //
2838 //
2839 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined.omp_outlined
2840 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR2]] {
2841 // CHECK3-NEXT:  entry:
2842 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
2843 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
2844 // CHECK3-NEXT:    [[NN_ADDR:%.*]] = alloca i32, align 4
2845 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
2846 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
2847 // CHECK3-NEXT:    store i32 [[NN]], ptr [[NN_ADDR]], align 4
2848 // CHECK3-NEXT:    ret void
2849 //
2850 //
2851 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l163
2852 // CHECK3-SAME: (i32 noundef [[NN:%.*]]) #[[ATTR2]] {
2853 // CHECK3-NEXT:  entry:
2854 // CHECK3-NEXT:    [[NN_ADDR:%.*]] = alloca i32, align 4
2855 // CHECK3-NEXT:    [[NN_CASTED:%.*]] = alloca i32, align 4
2856 // CHECK3-NEXT:    store i32 [[NN]], ptr [[NN_ADDR]], align 4
2857 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[NN_ADDR]], align 4
2858 // CHECK3-NEXT:    store i32 [[TMP0]], ptr [[NN_CASTED]], align 4
2859 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[NN_CASTED]], align 4
2860 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l163.omp_outlined, i32 [[TMP1]])
2861 // CHECK3-NEXT:    ret void
2862 //
2863 //
2864 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l163.omp_outlined
2865 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR2]] {
2866 // CHECK3-NEXT:  entry:
2867 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
2868 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
2869 // CHECK3-NEXT:    [[NN_ADDR:%.*]] = alloca i32, align 4
2870 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
2871 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
2872 // CHECK3-NEXT:    store i32 [[NN]], ptr [[NN_ADDR]], align 4
2873 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l163.omp_outlined.omp_outlined, ptr [[NN_ADDR]])
2874 // CHECK3-NEXT:    ret void
2875 //
2876 //
2877 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l163.omp_outlined.omp_outlined
2878 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR2]] {
2879 // CHECK3-NEXT:  entry:
2880 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
2881 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
2882 // CHECK3-NEXT:    [[NN_ADDR:%.*]] = alloca ptr, align 4
2883 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
2884 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
2885 // CHECK3-NEXT:    store ptr [[NN]], ptr [[NN_ADDR]], align 4
2886 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[NN_ADDR]], align 4
2887 // CHECK3-NEXT:    ret void
2888 //
2889 //
2890 // CHECK3-LABEL: define {{[^@]+}}@_Z6bazzzziPi
2891 // CHECK3-SAME: (i32 noundef [[N:%.*]], ptr noundef [[F:%.*]]) #[[ATTR0]] {
2892 // CHECK3-NEXT:  entry:
2893 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
2894 // CHECK3-NEXT:    [[F_ADDR:%.*]] = alloca ptr, align 4
2895 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 4
2896 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 4
2897 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 4
2898 // CHECK3-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
2899 // CHECK3-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
2900 // CHECK3-NEXT:    store ptr [[F]], ptr [[F_ADDR]], align 4
2901 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
2902 // CHECK3-NEXT:    [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2903 // CHECK3-NEXT:    store i32 [[TMP0]], ptr [[TMP1]], align 4
2904 // CHECK3-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2905 // CHECK3-NEXT:    store i32 [[TMP0]], ptr [[TMP2]], align 4
2906 // CHECK3-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
2907 // CHECK3-NEXT:    store ptr null, ptr [[TMP3]], align 4
2908 // CHECK3-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2909 // CHECK3-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2910 // CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
2911 // CHECK3-NEXT:    store i32 2, ptr [[TMP6]], align 4
2912 // CHECK3-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
2913 // CHECK3-NEXT:    store i32 1, ptr [[TMP7]], align 4
2914 // CHECK3-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
2915 // CHECK3-NEXT:    store ptr [[TMP4]], ptr [[TMP8]], align 4
2916 // CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
2917 // CHECK3-NEXT:    store ptr [[TMP5]], ptr [[TMP9]], align 4
2918 // CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
2919 // CHECK3-NEXT:    store ptr @.offload_sizes.13, ptr [[TMP10]], align 4
2920 // CHECK3-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
2921 // CHECK3-NEXT:    store ptr @.offload_maptypes.14, ptr [[TMP11]], align 4
2922 // CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
2923 // CHECK3-NEXT:    store ptr null, ptr [[TMP12]], align 4
2924 // CHECK3-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
2925 // CHECK3-NEXT:    store ptr null, ptr [[TMP13]], align 4
2926 // CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
2927 // CHECK3-NEXT:    store i64 0, ptr [[TMP14]], align 8
2928 // CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
2929 // CHECK3-NEXT:    store i64 0, ptr [[TMP15]], align 8
2930 // CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
2931 // CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP16]], align 4
2932 // CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
2933 // CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP17]], align 4
2934 // CHECK3-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
2935 // CHECK3-NEXT:    store i32 0, ptr [[TMP18]], align 4
2936 // CHECK3-NEXT:    [[TMP19:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l188.region_id, ptr [[KERNEL_ARGS]])
2937 // CHECK3-NEXT:    [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0
2938 // CHECK3-NEXT:    br i1 [[TMP20]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
2939 // CHECK3:       omp_offload.failed:
2940 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l188(i32 [[TMP0]]) #[[ATTR3]]
2941 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]
2942 // CHECK3:       omp_offload.cont:
2943 // CHECK3-NEXT:    ret void
2944 //
2945 //
2946 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l188
2947 // CHECK3-SAME: (i32 noundef [[VLA:%.*]]) #[[ATTR2]] {
2948 // CHECK3-NEXT:  entry:
2949 // CHECK3-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
2950 // CHECK3-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
2951 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
2952 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l188.omp_outlined, i32 [[TMP0]])
2953 // CHECK3-NEXT:    ret void
2954 //
2955 //
2956 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l188.omp_outlined
2957 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[VLA:%.*]]) #[[ATTR2]] {
2958 // CHECK3-NEXT:  entry:
2959 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
2960 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
2961 // CHECK3-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
2962 // CHECK3-NEXT:    [[F:%.*]] = alloca ptr, align 4
2963 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
2964 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
2965 // CHECK3-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
2966 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
2967 // CHECK3-NEXT:    ret void
2968 //
2969 //
2970 // CHECK3-LABEL: define {{[^@]+}}@_Z3bari
2971 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
2972 // CHECK3-NEXT:  entry:
2973 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
2974 // CHECK3-NEXT:    [[A:%.*]] = alloca i32, align 4
2975 // CHECK3-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
2976 // CHECK3-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
2977 // CHECK3-NEXT:    store i32 0, ptr [[A]], align 4
2978 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
2979 // CHECK3-NEXT:    [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]])
2980 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A]], align 4
2981 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
2982 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[A]], align 4
2983 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
2984 // CHECK3-NEXT:    [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]])
2985 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A]], align 4
2986 // CHECK3-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
2987 // CHECK3-NEXT:    store i32 [[ADD2]], ptr [[A]], align 4
2988 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
2989 // CHECK3-NEXT:    [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]])
2990 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[A]], align 4
2991 // CHECK3-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
2992 // CHECK3-NEXT:    store i32 [[ADD4]], ptr [[A]], align 4
2993 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4
2994 // CHECK3-NEXT:    [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]])
2995 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[A]], align 4
2996 // CHECK3-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
2997 // CHECK3-NEXT:    store i32 [[ADD6]], ptr [[A]], align 4
2998 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A]], align 4
2999 // CHECK3-NEXT:    ret i32 [[TMP8]]
3000 //
3001 //
3002 // CHECK3-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
3003 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 {
3004 // CHECK3-NEXT:  entry:
3005 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
3006 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
3007 // CHECK3-NEXT:    [[B:%.*]] = alloca i32, align 4
3008 // CHECK3-NEXT:    [[SAVED_STACK:%.*]] = alloca ptr, align 4
3009 // CHECK3-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
3010 // CHECK3-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
3011 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 4
3012 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 4
3013 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 4
3014 // CHECK3-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4
3015 // CHECK3-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
3016 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
3017 // CHECK3-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
3018 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
3019 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
3020 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
3021 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[B]], align 4
3022 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
3023 // CHECK3-NEXT:    [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
3024 // CHECK3-NEXT:    store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4
3025 // CHECK3-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
3026 // CHECK3-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
3027 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4
3028 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[B]], align 4
3029 // CHECK3-NEXT:    store i32 [[TMP4]], ptr [[B_CASTED]], align 4
3030 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4
3031 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4
3032 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60
3033 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
3034 // CHECK3:       omp_if.then:
3035 // CHECK3-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0
3036 // CHECK3-NEXT:    [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]]
3037 // CHECK3-NEXT:    [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2
3038 // CHECK3-NEXT:    [[TMP9:%.*]] = sext i32 [[TMP8]] to i64
3039 // CHECK3-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes.15, i32 40, i1 false)
3040 // CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3041 // CHECK3-NEXT:    store ptr [[THIS1]], ptr [[TMP10]], align 4
3042 // CHECK3-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3043 // CHECK3-NEXT:    store ptr [[A]], ptr [[TMP11]], align 4
3044 // CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
3045 // CHECK3-NEXT:    store ptr null, ptr [[TMP12]], align 4
3046 // CHECK3-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
3047 // CHECK3-NEXT:    store i32 [[TMP5]], ptr [[TMP13]], align 4
3048 // CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
3049 // CHECK3-NEXT:    store i32 [[TMP5]], ptr [[TMP14]], align 4
3050 // CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
3051 // CHECK3-NEXT:    store ptr null, ptr [[TMP15]], align 4
3052 // CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
3053 // CHECK3-NEXT:    store i32 2, ptr [[TMP16]], align 4
3054 // CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
3055 // CHECK3-NEXT:    store i32 2, ptr [[TMP17]], align 4
3056 // CHECK3-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
3057 // CHECK3-NEXT:    store ptr null, ptr [[TMP18]], align 4
3058 // CHECK3-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
3059 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[TMP19]], align 4
3060 // CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
3061 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[TMP20]], align 4
3062 // CHECK3-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
3063 // CHECK3-NEXT:    store ptr null, ptr [[TMP21]], align 4
3064 // CHECK3-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
3065 // CHECK3-NEXT:    store ptr [[VLA]], ptr [[TMP22]], align 4
3066 // CHECK3-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4
3067 // CHECK3-NEXT:    store ptr [[VLA]], ptr [[TMP23]], align 4
3068 // CHECK3-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 4
3069 // CHECK3-NEXT:    store i64 [[TMP9]], ptr [[TMP24]], align 4
3070 // CHECK3-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
3071 // CHECK3-NEXT:    store ptr null, ptr [[TMP25]], align 4
3072 // CHECK3-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3073 // CHECK3-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3074 // CHECK3-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0
3075 // CHECK3-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
3076 // CHECK3-NEXT:    store i32 2, ptr [[TMP29]], align 4
3077 // CHECK3-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
3078 // CHECK3-NEXT:    store i32 5, ptr [[TMP30]], align 4
3079 // CHECK3-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
3080 // CHECK3-NEXT:    store ptr [[TMP26]], ptr [[TMP31]], align 4
3081 // CHECK3-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
3082 // CHECK3-NEXT:    store ptr [[TMP27]], ptr [[TMP32]], align 4
3083 // CHECK3-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
3084 // CHECK3-NEXT:    store ptr [[TMP28]], ptr [[TMP33]], align 4
3085 // CHECK3-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
3086 // CHECK3-NEXT:    store ptr @.offload_maptypes.16, ptr [[TMP34]], align 4
3087 // CHECK3-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
3088 // CHECK3-NEXT:    store ptr null, ptr [[TMP35]], align 4
3089 // CHECK3-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
3090 // CHECK3-NEXT:    store ptr null, ptr [[TMP36]], align 4
3091 // CHECK3-NEXT:    [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
3092 // CHECK3-NEXT:    store i64 0, ptr [[TMP37]], align 8
3093 // CHECK3-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
3094 // CHECK3-NEXT:    store i64 0, ptr [[TMP38]], align 8
3095 // CHECK3-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
3096 // CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP39]], align 4
3097 // CHECK3-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
3098 // CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP40]], align 4
3099 // CHECK3-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
3100 // CHECK3-NEXT:    store i32 0, ptr [[TMP41]], align 4
3101 // CHECK3-NEXT:    [[TMP42:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l233.region_id, ptr [[KERNEL_ARGS]])
3102 // CHECK3-NEXT:    [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0
3103 // CHECK3-NEXT:    br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
3104 // CHECK3:       omp_offload.failed:
3105 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l233(ptr [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], ptr [[VLA]]) #[[ATTR3]]
3106 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]
3107 // CHECK3:       omp_offload.cont:
3108 // CHECK3-NEXT:    br label [[OMP_IF_END:%.*]]
3109 // CHECK3:       omp_if.else:
3110 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l233(ptr [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], ptr [[VLA]]) #[[ATTR3]]
3111 // CHECK3-NEXT:    br label [[OMP_IF_END]]
3112 // CHECK3:       omp_if.end:
3113 // CHECK3-NEXT:    [[TMP44:%.*]] = mul nsw i32 1, [[TMP1]]
3114 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP44]]
3115 // CHECK3-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1
3116 // CHECK3-NEXT:    [[TMP45:%.*]] = load i16, ptr [[ARRAYIDX2]], align 2
3117 // CHECK3-NEXT:    [[CONV:%.*]] = sext i16 [[TMP45]] to i32
3118 // CHECK3-NEXT:    [[TMP46:%.*]] = load i32, ptr [[B]], align 4
3119 // CHECK3-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP46]]
3120 // CHECK3-NEXT:    [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
3121 // CHECK3-NEXT:    call void @llvm.stackrestore.p0(ptr [[TMP47]])
3122 // CHECK3-NEXT:    ret i32 [[ADD3]]
3123 //
3124 //
3125 // CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici
3126 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
3127 // CHECK3-NEXT:  entry:
3128 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
3129 // CHECK3-NEXT:    [[A:%.*]] = alloca i32, align 4
3130 // CHECK3-NEXT:    [[AA:%.*]] = alloca i16, align 2
3131 // CHECK3-NEXT:    [[AAA:%.*]] = alloca i8, align 1
3132 // CHECK3-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
3133 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
3134 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
3135 // CHECK3-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
3136 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 4
3137 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 4
3138 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 4
3139 // CHECK3-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
3140 // CHECK3-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
3141 // CHECK3-NEXT:    store i32 0, ptr [[A]], align 4
3142 // CHECK3-NEXT:    store i16 0, ptr [[AA]], align 2
3143 // CHECK3-NEXT:    store i8 0, ptr [[AAA]], align 1
3144 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A]], align 4
3145 // CHECK3-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 4
3146 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4
3147 // CHECK3-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA]], align 2
3148 // CHECK3-NEXT:    store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
3149 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4
3150 // CHECK3-NEXT:    [[TMP4:%.*]] = load i8, ptr [[AAA]], align 1
3151 // CHECK3-NEXT:    store i8 [[TMP4]], ptr [[AAA_CASTED]], align 1
3152 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[AAA_CASTED]], align 4
3153 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4
3154 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50
3155 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
3156 // CHECK3:       omp_if.then:
3157 // CHECK3-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3158 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[TMP7]], align 4
3159 // CHECK3-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3160 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[TMP8]], align 4
3161 // CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
3162 // CHECK3-NEXT:    store ptr null, ptr [[TMP9]], align 4
3163 // CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
3164 // CHECK3-NEXT:    store i32 [[TMP3]], ptr [[TMP10]], align 4
3165 // CHECK3-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
3166 // CHECK3-NEXT:    store i32 [[TMP3]], ptr [[TMP11]], align 4
3167 // CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
3168 // CHECK3-NEXT:    store ptr null, ptr [[TMP12]], align 4
3169 // CHECK3-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
3170 // CHECK3-NEXT:    store i32 [[TMP5]], ptr [[TMP13]], align 4
3171 // CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
3172 // CHECK3-NEXT:    store i32 [[TMP5]], ptr [[TMP14]], align 4
3173 // CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
3174 // CHECK3-NEXT:    store ptr null, ptr [[TMP15]], align 4
3175 // CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
3176 // CHECK3-NEXT:    store ptr [[B]], ptr [[TMP16]], align 4
3177 // CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
3178 // CHECK3-NEXT:    store ptr [[B]], ptr [[TMP17]], align 4
3179 // CHECK3-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
3180 // CHECK3-NEXT:    store ptr null, ptr [[TMP18]], align 4
3181 // CHECK3-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3182 // CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3183 // CHECK3-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
3184 // CHECK3-NEXT:    store i32 2, ptr [[TMP21]], align 4
3185 // CHECK3-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
3186 // CHECK3-NEXT:    store i32 4, ptr [[TMP22]], align 4
3187 // CHECK3-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
3188 // CHECK3-NEXT:    store ptr [[TMP19]], ptr [[TMP23]], align 4
3189 // CHECK3-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
3190 // CHECK3-NEXT:    store ptr [[TMP20]], ptr [[TMP24]], align 4
3191 // CHECK3-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
3192 // CHECK3-NEXT:    store ptr @.offload_sizes.17, ptr [[TMP25]], align 4
3193 // CHECK3-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
3194 // CHECK3-NEXT:    store ptr @.offload_maptypes.18, ptr [[TMP26]], align 4
3195 // CHECK3-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
3196 // CHECK3-NEXT:    store ptr null, ptr [[TMP27]], align 4
3197 // CHECK3-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
3198 // CHECK3-NEXT:    store ptr null, ptr [[TMP28]], align 4
3199 // CHECK3-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
3200 // CHECK3-NEXT:    store i64 0, ptr [[TMP29]], align 8
3201 // CHECK3-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
3202 // CHECK3-NEXT:    store i64 0, ptr [[TMP30]], align 8
3203 // CHECK3-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
3204 // CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP31]], align 4
3205 // CHECK3-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
3206 // CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP32]], align 4
3207 // CHECK3-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
3208 // CHECK3-NEXT:    store i32 0, ptr [[TMP33]], align 4
3209 // CHECK3-NEXT:    [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l215.region_id, ptr [[KERNEL_ARGS]])
3210 // CHECK3-NEXT:    [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0
3211 // CHECK3-NEXT:    br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
3212 // CHECK3:       omp_offload.failed:
3213 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l215(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], ptr [[B]]) #[[ATTR3]]
3214 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]
3215 // CHECK3:       omp_offload.cont:
3216 // CHECK3-NEXT:    br label [[OMP_IF_END:%.*]]
3217 // CHECK3:       omp_if.else:
3218 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l215(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], ptr [[B]]) #[[ATTR3]]
3219 // CHECK3-NEXT:    br label [[OMP_IF_END]]
3220 // CHECK3:       omp_if.end:
3221 // CHECK3-NEXT:    [[TMP36:%.*]] = load i32, ptr [[A]], align 4
3222 // CHECK3-NEXT:    ret i32 [[TMP36]]
3223 //
3224 //
3225 // CHECK3-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
3226 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat {
3227 // CHECK3-NEXT:  entry:
3228 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
3229 // CHECK3-NEXT:    [[A:%.*]] = alloca i32, align 4
3230 // CHECK3-NEXT:    [[AA:%.*]] = alloca i16, align 2
3231 // CHECK3-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
3232 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
3233 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
3234 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 4
3235 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 4
3236 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 4
3237 // CHECK3-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
3238 // CHECK3-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
3239 // CHECK3-NEXT:    store i32 0, ptr [[A]], align 4
3240 // CHECK3-NEXT:    store i16 0, ptr [[AA]], align 2
3241 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A]], align 4
3242 // CHECK3-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 4
3243 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4
3244 // CHECK3-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA]], align 2
3245 // CHECK3-NEXT:    store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
3246 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4
3247 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
3248 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
3249 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
3250 // CHECK3:       omp_if.then:
3251 // CHECK3-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3252 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[TMP5]], align 4
3253 // CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3254 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[TMP6]], align 4
3255 // CHECK3-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
3256 // CHECK3-NEXT:    store ptr null, ptr [[TMP7]], align 4
3257 // CHECK3-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
3258 // CHECK3-NEXT:    store i32 [[TMP3]], ptr [[TMP8]], align 4
3259 // CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
3260 // CHECK3-NEXT:    store i32 [[TMP3]], ptr [[TMP9]], align 4
3261 // CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
3262 // CHECK3-NEXT:    store ptr null, ptr [[TMP10]], align 4
3263 // CHECK3-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
3264 // CHECK3-NEXT:    store ptr [[B]], ptr [[TMP11]], align 4
3265 // CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
3266 // CHECK3-NEXT:    store ptr [[B]], ptr [[TMP12]], align 4
3267 // CHECK3-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
3268 // CHECK3-NEXT:    store ptr null, ptr [[TMP13]], align 4
3269 // CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3270 // CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3271 // CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
3272 // CHECK3-NEXT:    store i32 2, ptr [[TMP16]], align 4
3273 // CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
3274 // CHECK3-NEXT:    store i32 3, ptr [[TMP17]], align 4
3275 // CHECK3-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
3276 // CHECK3-NEXT:    store ptr [[TMP14]], ptr [[TMP18]], align 4
3277 // CHECK3-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
3278 // CHECK3-NEXT:    store ptr [[TMP15]], ptr [[TMP19]], align 4
3279 // CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
3280 // CHECK3-NEXT:    store ptr @.offload_sizes.19, ptr [[TMP20]], align 4
3281 // CHECK3-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
3282 // CHECK3-NEXT:    store ptr @.offload_maptypes.20, ptr [[TMP21]], align 4
3283 // CHECK3-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
3284 // CHECK3-NEXT:    store ptr null, ptr [[TMP22]], align 4
3285 // CHECK3-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
3286 // CHECK3-NEXT:    store ptr null, ptr [[TMP23]], align 4
3287 // CHECK3-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
3288 // CHECK3-NEXT:    store i64 0, ptr [[TMP24]], align 8
3289 // CHECK3-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
3290 // CHECK3-NEXT:    store i64 0, ptr [[TMP25]], align 8
3291 // CHECK3-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
3292 // CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP26]], align 4
3293 // CHECK3-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
3294 // CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP27]], align 4
3295 // CHECK3-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
3296 // CHECK3-NEXT:    store i32 0, ptr [[TMP28]], align 4
3297 // CHECK3-NEXT:    [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB1]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l198.region_id, ptr [[KERNEL_ARGS]])
3298 // CHECK3-NEXT:    [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
3299 // CHECK3-NEXT:    br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
3300 // CHECK3:       omp_offload.failed:
3301 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l198(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR3]]
3302 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]
3303 // CHECK3:       omp_offload.cont:
3304 // CHECK3-NEXT:    br label [[OMP_IF_END:%.*]]
3305 // CHECK3:       omp_if.else:
3306 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l198(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR3]]
3307 // CHECK3-NEXT:    br label [[OMP_IF_END]]
3308 // CHECK3:       omp_if.end:
3309 // CHECK3-NEXT:    [[TMP31:%.*]] = load i32, ptr [[A]], align 4
3310 // CHECK3-NEXT:    ret i32 [[TMP31]]
3311 //
3312 //
3313 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l233
3314 // CHECK3-SAME: (ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
3315 // CHECK3-NEXT:  entry:
3316 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
3317 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
3318 // CHECK3-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
3319 // CHECK3-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
3320 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
3321 // CHECK3-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
3322 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
3323 // CHECK3-NEXT:    store i32 [[B]], ptr [[B_ADDR]], align 4
3324 // CHECK3-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
3325 // CHECK3-NEXT:    store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
3326 // CHECK3-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
3327 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
3328 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
3329 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
3330 // CHECK3-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
3331 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4
3332 // CHECK3-NEXT:    store i32 [[TMP4]], ptr [[B_CASTED]], align 4
3333 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4
3334 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l233.omp_outlined, ptr [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], ptr [[TMP3]])
3335 // CHECK3-NEXT:    ret void
3336 //
3337 //
3338 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l233.omp_outlined
3339 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
3340 // CHECK3-NEXT:  entry:
3341 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
3342 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
3343 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
3344 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
3345 // CHECK3-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
3346 // CHECK3-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
3347 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
3348 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
3349 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
3350 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
3351 // CHECK3-NEXT:    store i32 [[B]], ptr [[B_ADDR]], align 4
3352 // CHECK3-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
3353 // CHECK3-NEXT:    store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
3354 // CHECK3-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
3355 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
3356 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
3357 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
3358 // CHECK3-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
3359 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4
3360 // CHECK3-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP4]] to double
3361 // CHECK3-NEXT:    [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
3362 // CHECK3-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0
3363 // CHECK3-NEXT:    store double [[ADD]], ptr [[A]], align 4
3364 // CHECK3-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0
3365 // CHECK3-NEXT:    [[TMP5:%.*]] = load double, ptr [[A3]], align 4
3366 // CHECK3-NEXT:    [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
3367 // CHECK3-NEXT:    store double [[INC]], ptr [[A3]], align 4
3368 // CHECK3-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
3369 // CHECK3-NEXT:    [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]]
3370 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i32 [[TMP6]]
3371 // CHECK3-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1
3372 // CHECK3-NEXT:    store i16 [[CONV4]], ptr [[ARRAYIDX5]], align 2
3373 // CHECK3-NEXT:    ret void
3374 //
3375 //
3376 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l215
3377 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
3378 // CHECK3-NEXT:  entry:
3379 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
3380 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
3381 // CHECK3-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
3382 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
3383 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
3384 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
3385 // CHECK3-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
3386 // CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
3387 // CHECK3-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
3388 // CHECK3-NEXT:    store i32 [[AAA]], ptr [[AAA_ADDR]], align 4
3389 // CHECK3-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
3390 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
3391 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
3392 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 4
3393 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4
3394 // CHECK3-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
3395 // CHECK3-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
3396 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4
3397 // CHECK3-NEXT:    [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 1
3398 // CHECK3-NEXT:    store i8 [[TMP5]], ptr [[AAA_CASTED]], align 1
3399 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[AAA_CASTED]], align 4
3400 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l215.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], ptr [[TMP0]])
3401 // CHECK3-NEXT:    ret void
3402 //
3403 //
3404 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l215.omp_outlined
3405 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
3406 // CHECK3-NEXT:  entry:
3407 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
3408 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
3409 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
3410 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
3411 // CHECK3-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
3412 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
3413 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
3414 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
3415 // CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
3416 // CHECK3-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
3417 // CHECK3-NEXT:    store i32 [[AAA]], ptr [[AAA_ADDR]], align 4
3418 // CHECK3-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
3419 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
3420 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
3421 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
3422 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 4
3423 // CHECK3-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2
3424 // CHECK3-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i32
3425 // CHECK3-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
3426 // CHECK3-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
3427 // CHECK3-NEXT:    store i16 [[CONV2]], ptr [[AA_ADDR]], align 2
3428 // CHECK3-NEXT:    [[TMP3:%.*]] = load i8, ptr [[AAA_ADDR]], align 1
3429 // CHECK3-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP3]] to i32
3430 // CHECK3-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
3431 // CHECK3-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8
3432 // CHECK3-NEXT:    store i8 [[CONV5]], ptr [[AAA_ADDR]], align 1
3433 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2
3434 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
3435 // CHECK3-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP4]], 1
3436 // CHECK3-NEXT:    store i32 [[ADD6]], ptr [[ARRAYIDX]], align 4
3437 // CHECK3-NEXT:    ret void
3438 //
3439 //
3440 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l198
3441 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
3442 // CHECK3-NEXT:  entry:
3443 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
3444 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
3445 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
3446 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
3447 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
3448 // CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
3449 // CHECK3-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
3450 // CHECK3-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
3451 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
3452 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
3453 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 4
3454 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4
3455 // CHECK3-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
3456 // CHECK3-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
3457 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4
3458 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l198.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], ptr [[TMP0]])
3459 // CHECK3-NEXT:    ret void
3460 //
3461 //
3462 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l198.omp_outlined
3463 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
3464 // CHECK3-NEXT:  entry:
3465 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
3466 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
3467 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
3468 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
3469 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
3470 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
3471 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
3472 // CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
3473 // CHECK3-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
3474 // CHECK3-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
3475 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
3476 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
3477 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
3478 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 4
3479 // CHECK3-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2
3480 // CHECK3-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i32
3481 // CHECK3-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
3482 // CHECK3-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
3483 // CHECK3-NEXT:    store i16 [[CONV2]], ptr [[AA_ADDR]], align 2
3484 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2
3485 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
3486 // CHECK3-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1
3487 // CHECK3-NEXT:    store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4
3488 // CHECK3-NEXT:    ret void
3489 //
3490 //
3491 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
3492 // CHECK3-SAME: () #[[ATTR4]] {
3493 // CHECK3-NEXT:  entry:
3494 // CHECK3-NEXT:    call void @__tgt_register_requires(i64 1)
3495 // CHECK3-NEXT:    ret void
3496 //
3497 //
3498 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101
3499 // CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] {
3500 // CHECK9-NEXT:  entry:
3501 // CHECK9-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
3502 // CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
3503 // CHECK9-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
3504 // CHECK9-NEXT:    [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8
3505 // CHECK9-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
3506 // CHECK9-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
3507 // CHECK9-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
3508 // CHECK9-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
3509 // CHECK9-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
3510 // CHECK9-NEXT:    store i64 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 8
3511 // CHECK9-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
3512 // CHECK9-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4
3513 // CHECK9-NEXT:    call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
3514 // CHECK9-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
3515 // CHECK9-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
3516 // CHECK9-NEXT:    [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8
3517 // CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.omp_outlined, i64 [[TMP4]])
3518 // CHECK9-NEXT:    ret void
3519 //
3520 //
3521 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.omp_outlined
3522 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {
3523 // CHECK9-NEXT:  entry:
3524 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
3525 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
3526 // CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
3527 // CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
3528 // CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
3529 // CHECK9-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
3530 // CHECK9-NEXT:    ret void
3531 //
3532 //
3533 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
3534 // CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {
3535 // CHECK9-NEXT:  entry:
3536 // CHECK9-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
3537 // CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
3538 // CHECK9-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
3539 // CHECK9-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
3540 // CHECK9-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
3541 // CHECK9-NEXT:    [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2
3542 // CHECK9-NEXT:    store i16 [[TMP0]], ptr [[AA_CASTED]], align 2
3543 // CHECK9-NEXT:    [[TMP1:%.*]] = load i64, ptr [[AA_CASTED]], align 8
3544 // CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined, i64 [[TMP1]])
3545 // CHECK9-NEXT:    ret void
3546 //
3547 //
3548 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined
3549 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {
3550 // CHECK9-NEXT:  entry:
3551 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
3552 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
3553 // CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
3554 // CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
3555 // CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
3556 // CHECK9-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
3557 // CHECK9-NEXT:    [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2
3558 // CHECK9-NEXT:    [[CONV:%.*]] = sext i16 [[TMP0]] to i32
3559 // CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV]], 1
3560 // CHECK9-NEXT:    [[CONV1:%.*]] = trunc i32 [[ADD]] to i16
3561 // CHECK9-NEXT:    store i16 [[CONV1]], ptr [[AA_ADDR]], align 2
3562 // CHECK9-NEXT:    ret void
3563 //
3564 //
3565 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118
3566 // CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {
3567 // CHECK9-NEXT:  entry:
3568 // CHECK9-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
3569 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
3570 // CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
3571 // CHECK9-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
3572 // CHECK9-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
3573 // CHECK9-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
3574 // CHECK9-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
3575 // CHECK9-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
3576 // CHECK9-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
3577 // CHECK9-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 4
3578 // CHECK9-NEXT:    [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8
3579 // CHECK9-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2
3580 // CHECK9-NEXT:    store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
3581 // CHECK9-NEXT:    [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8
3582 // CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined, i64 [[TMP1]], i64 [[TMP3]])
3583 // CHECK9-NEXT:    ret void
3584 //
3585 //
3586 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined
3587 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {
3588 // CHECK9-NEXT:  entry:
3589 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
3590 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
3591 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
3592 // CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
3593 // CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
3594 // CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
3595 // CHECK9-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
3596 // CHECK9-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
3597 // CHECK9-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
3598 // CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
3599 // CHECK9-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 4
3600 // CHECK9-NEXT:    [[TMP1:%.*]] = load i16, ptr [[AA_ADDR]], align 2
3601 // CHECK9-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
3602 // CHECK9-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
3603 // CHECK9-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
3604 // CHECK9-NEXT:    store i16 [[CONV2]], ptr [[AA_ADDR]], align 2
3605 // CHECK9-NEXT:    ret void
3606 //
3607 //
3608 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l124
3609 // CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {
3610 // CHECK9-NEXT:  entry:
3611 // CHECK9-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
3612 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
3613 // CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
3614 // CHECK9-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
3615 // CHECK9-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
3616 // CHECK9-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
3617 // CHECK9-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
3618 // CHECK9-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
3619 // CHECK9-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
3620 // CHECK9-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 4
3621 // CHECK9-NEXT:    [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8
3622 // CHECK9-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2
3623 // CHECK9-NEXT:    store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
3624 // CHECK9-NEXT:    [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8
3625 // CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l124.omp_outlined, i64 [[TMP1]], i64 [[TMP3]])
3626 // CHECK9-NEXT:    ret void
3627 //
3628 //
3629 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l124.omp_outlined
3630 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {
3631 // CHECK9-NEXT:  entry:
3632 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
3633 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
3634 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
3635 // CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
3636 // CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
3637 // CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
3638 // CHECK9-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
3639 // CHECK9-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
3640 // CHECK9-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
3641 // CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
3642 // CHECK9-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 4
3643 // CHECK9-NEXT:    [[TMP1:%.*]] = load i16, ptr [[AA_ADDR]], align 2
3644 // CHECK9-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
3645 // CHECK9-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
3646 // CHECK9-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
3647 // CHECK9-NEXT:    store i16 [[CONV2]], ptr [[AA_ADDR]], align 2
3648 // CHECK9-NEXT:    ret void
3649 //
3650 //
3651 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l148
3652 // CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] {
3653 // CHECK9-NEXT:  entry:
3654 // CHECK9-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
3655 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
3656 // CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
3657 // CHECK9-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
3658 // CHECK9-NEXT:    [[BN_ADDR:%.*]] = alloca ptr, align 8
3659 // CHECK9-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
3660 // CHECK9-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
3661 // CHECK9-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
3662 // CHECK9-NEXT:    [[CN_ADDR:%.*]] = alloca ptr, align 8
3663 // CHECK9-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
3664 // CHECK9-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
3665 // CHECK9-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
3666 // CHECK9-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
3667 // CHECK9-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
3668 // CHECK9-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
3669 // CHECK9-NEXT:    store ptr [[BN]], ptr [[BN_ADDR]], align 8
3670 // CHECK9-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
3671 // CHECK9-NEXT:    store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
3672 // CHECK9-NEXT:    store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8
3673 // CHECK9-NEXT:    store ptr [[CN]], ptr [[CN_ADDR]], align 8
3674 // CHECK9-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
3675 // CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
3676 // CHECK9-NEXT:    [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
3677 // CHECK9-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8
3678 // CHECK9-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
3679 // CHECK9-NEXT:    [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
3680 // CHECK9-NEXT:    [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8
3681 // CHECK9-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8
3682 // CHECK9-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8
3683 // CHECK9-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
3684 // CHECK9-NEXT:    store i32 [[TMP8]], ptr [[A_CASTED]], align 4
3685 // CHECK9-NEXT:    [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 8
3686 // CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l148.omp_outlined, i64 [[TMP9]], ptr [[TMP0]], i64 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]])
3687 // CHECK9-NEXT:    ret void
3688 //
3689 //
3690 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l148.omp_outlined
3691 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] {
3692 // CHECK9-NEXT:  entry:
3693 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
3694 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
3695 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
3696 // CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
3697 // CHECK9-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
3698 // CHECK9-NEXT:    [[BN_ADDR:%.*]] = alloca ptr, align 8
3699 // CHECK9-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
3700 // CHECK9-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
3701 // CHECK9-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
3702 // CHECK9-NEXT:    [[CN_ADDR:%.*]] = alloca ptr, align 8
3703 // CHECK9-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
3704 // CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
3705 // CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
3706 // CHECK9-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
3707 // CHECK9-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
3708 // CHECK9-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
3709 // CHECK9-NEXT:    store ptr [[BN]], ptr [[BN_ADDR]], align 8
3710 // CHECK9-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
3711 // CHECK9-NEXT:    store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
3712 // CHECK9-NEXT:    store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8
3713 // CHECK9-NEXT:    store ptr [[CN]], ptr [[CN_ADDR]], align 8
3714 // CHECK9-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
3715 // CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
3716 // CHECK9-NEXT:    [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
3717 // CHECK9-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8
3718 // CHECK9-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
3719 // CHECK9-NEXT:    [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
3720 // CHECK9-NEXT:    [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8
3721 // CHECK9-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8
3722 // CHECK9-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8
3723 // CHECK9-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
3724 // CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
3725 // CHECK9-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 4
3726 // CHECK9-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 2
3727 // CHECK9-NEXT:    [[TMP9:%.*]] = load float, ptr [[ARRAYIDX]], align 4
3728 // CHECK9-NEXT:    [[CONV:%.*]] = fpext float [[TMP9]] to double
3729 // CHECK9-NEXT:    [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00
3730 // CHECK9-NEXT:    [[CONV6:%.*]] = fptrunc double [[ADD5]] to float
3731 // CHECK9-NEXT:    store float [[CONV6]], ptr [[ARRAYIDX]], align 4
3732 // CHECK9-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 3
3733 // CHECK9-NEXT:    [[TMP10:%.*]] = load float, ptr [[ARRAYIDX7]], align 4
3734 // CHECK9-NEXT:    [[CONV8:%.*]] = fpext float [[TMP10]] to double
3735 // CHECK9-NEXT:    [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00
3736 // CHECK9-NEXT:    [[CONV10:%.*]] = fptrunc double [[ADD9]] to float
3737 // CHECK9-NEXT:    store float [[CONV10]], ptr [[ARRAYIDX7]], align 4
3738 // CHECK9-NEXT:    [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 1
3739 // CHECK9-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX11]], i64 0, i64 2
3740 // CHECK9-NEXT:    [[TMP11:%.*]] = load double, ptr [[ARRAYIDX12]], align 8
3741 // CHECK9-NEXT:    [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00
3742 // CHECK9-NEXT:    store double [[ADD13]], ptr [[ARRAYIDX12]], align 8
3743 // CHECK9-NEXT:    [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]]
3744 // CHECK9-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i64 [[TMP12]]
3745 // CHECK9-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX14]], i64 3
3746 // CHECK9-NEXT:    [[TMP13:%.*]] = load double, ptr [[ARRAYIDX15]], align 8
3747 // CHECK9-NEXT:    [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00
3748 // CHECK9-NEXT:    store double [[ADD16]], ptr [[ARRAYIDX15]], align 8
3749 // CHECK9-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0
3750 // CHECK9-NEXT:    [[TMP14:%.*]] = load i64, ptr [[X]], align 8
3751 // CHECK9-NEXT:    [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1
3752 // CHECK9-NEXT:    store i64 [[ADD17]], ptr [[X]], align 8
3753 // CHECK9-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1
3754 // CHECK9-NEXT:    [[TMP15:%.*]] = load i8, ptr [[Y]], align 8
3755 // CHECK9-NEXT:    [[CONV18:%.*]] = sext i8 [[TMP15]] to i32
3756 // CHECK9-NEXT:    [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1
3757 // CHECK9-NEXT:    [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8
3758 // CHECK9-NEXT:    store i8 [[CONV20]], ptr [[Y]], align 8
3759 // CHECK9-NEXT:    ret void
3760 //
3761 //
3762 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160
3763 // CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR0]] {
3764 // CHECK9-NEXT:  entry:
3765 // CHECK9-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
3766 // CHECK9-NEXT:    [[NN_ADDR:%.*]] = alloca i64, align 8
3767 // CHECK9-NEXT:    [[NN_CASTED:%.*]] = alloca i64, align 8
3768 // CHECK9-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
3769 // CHECK9-NEXT:    store i64 [[NN]], ptr [[NN_ADDR]], align 8
3770 // CHECK9-NEXT:    [[TMP0:%.*]] = load i32, ptr [[NN_ADDR]], align 4
3771 // CHECK9-NEXT:    store i32 [[TMP0]], ptr [[NN_CASTED]], align 4
3772 // CHECK9-NEXT:    [[TMP1:%.*]] = load i64, ptr [[NN_CASTED]], align 8
3773 // CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined, i64 [[TMP1]])
3774 // CHECK9-NEXT:    ret void
3775 //
3776 //
3777 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined
3778 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR0]] {
3779 // CHECK9-NEXT:  entry:
3780 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
3781 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
3782 // CHECK9-NEXT:    [[NN_ADDR:%.*]] = alloca i64, align 8
3783 // CHECK9-NEXT:    [[NN_CASTED:%.*]] = alloca i64, align 8
3784 // CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
3785 // CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
3786 // CHECK9-NEXT:    store i64 [[NN]], ptr [[NN_ADDR]], align 8
3787 // CHECK9-NEXT:    [[TMP0:%.*]] = load i32, ptr [[NN_ADDR]], align 4
3788 // CHECK9-NEXT:    store i32 [[TMP0]], ptr [[NN_CASTED]], align 4
3789 // CHECK9-NEXT:    [[TMP1:%.*]] = load i64, ptr [[NN_CASTED]], align 8
3790 // CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined.omp_outlined, i64 [[TMP1]])
3791 // CHECK9-NEXT:    ret void
3792 //
3793 //
3794 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined.omp_outlined
3795 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR0]] {
3796 // CHECK9-NEXT:  entry:
3797 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
3798 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
3799 // CHECK9-NEXT:    [[NN_ADDR:%.*]] = alloca i64, align 8
3800 // CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
3801 // CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
3802 // CHECK9-NEXT:    store i64 [[NN]], ptr [[NN_ADDR]], align 8
3803 // CHECK9-NEXT:    ret void
3804 //
3805 //
3806 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l163
3807 // CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR0]] {
3808 // CHECK9-NEXT:  entry:
3809 // CHECK9-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
3810 // CHECK9-NEXT:    [[NN_ADDR:%.*]] = alloca i64, align 8
3811 // CHECK9-NEXT:    [[NN_CASTED:%.*]] = alloca i64, align 8
3812 // CHECK9-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
3813 // CHECK9-NEXT:    store i64 [[NN]], ptr [[NN_ADDR]], align 8
3814 // CHECK9-NEXT:    [[TMP0:%.*]] = load i32, ptr [[NN_ADDR]], align 4
3815 // CHECK9-NEXT:    store i32 [[TMP0]], ptr [[NN_CASTED]], align 4
3816 // CHECK9-NEXT:    [[TMP1:%.*]] = load i64, ptr [[NN_CASTED]], align 8
3817 // CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l163.omp_outlined, i64 [[TMP1]])
3818 // CHECK9-NEXT:    ret void
3819 //
3820 //
3821 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l163.omp_outlined
3822 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR0]] {
3823 // CHECK9-NEXT:  entry:
3824 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
3825 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
3826 // CHECK9-NEXT:    [[NN_ADDR:%.*]] = alloca i64, align 8
3827 // CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
3828 // CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
3829 // CHECK9-NEXT:    store i64 [[NN]], ptr [[NN_ADDR]], align 8
3830 // CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l163.omp_outlined.omp_outlined, ptr [[NN_ADDR]])
3831 // CHECK9-NEXT:    ret void
3832 //
3833 //
3834 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l163.omp_outlined.omp_outlined
3835 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] {
3836 // CHECK9-NEXT:  entry:
3837 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
3838 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
3839 // CHECK9-NEXT:    [[NN_ADDR:%.*]] = alloca ptr, align 8
3840 // CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
3841 // CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
3842 // CHECK9-NEXT:    store ptr [[NN]], ptr [[NN_ADDR]], align 8
3843 // CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[NN_ADDR]], align 8
3844 // CHECK9-NEXT:    ret void
3845 //
3846 //
3847 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l188
3848 // CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[VLA:%.*]]) #[[ATTR0]] {
3849 // CHECK9-NEXT:  entry:
3850 // CHECK9-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
3851 // CHECK9-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
3852 // CHECK9-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
3853 // CHECK9-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
3854 // CHECK9-NEXT:    [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
3855 // CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l188.omp_outlined, i64 [[TMP0]])
3856 // CHECK9-NEXT:    ret void
3857 //
3858 //
3859 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l188.omp_outlined
3860 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]]) #[[ATTR0]] {
3861 // CHECK9-NEXT:  entry:
3862 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
3863 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
3864 // CHECK9-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
3865 // CHECK9-NEXT:    [[F:%.*]] = alloca ptr, align 8
3866 // CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
3867 // CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
3868 // CHECK9-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
3869 // CHECK9-NEXT:    [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
3870 // CHECK9-NEXT:    ret void
3871 //
3872 //
3873 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l215
3874 // CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
3875 // CHECK9-NEXT:  entry:
3876 // CHECK9-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
3877 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
3878 // CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
3879 // CHECK9-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
3880 // CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
3881 // CHECK9-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
3882 // CHECK9-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
3883 // CHECK9-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
3884 // CHECK9-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
3885 // CHECK9-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
3886 // CHECK9-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
3887 // CHECK9-NEXT:    store i64 [[AAA]], ptr [[AAA_ADDR]], align 8
3888 // CHECK9-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
3889 // CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
3890 // CHECK9-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
3891 // CHECK9-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 4
3892 // CHECK9-NEXT:    [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8
3893 // CHECK9-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
3894 // CHECK9-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
3895 // CHECK9-NEXT:    [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8
3896 // CHECK9-NEXT:    [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 1
3897 // CHECK9-NEXT:    store i8 [[TMP5]], ptr [[AAA_CASTED]], align 1
3898 // CHECK9-NEXT:    [[TMP6:%.*]] = load i64, ptr [[AAA_CASTED]], align 8
3899 // CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l215.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], ptr [[TMP0]])
3900 // CHECK9-NEXT:    ret void
3901 //
3902 //
3903 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l215.omp_outlined
3904 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
3905 // CHECK9-NEXT:  entry:
3906 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
3907 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
3908 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
3909 // CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
3910 // CHECK9-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
3911 // CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
3912 // CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
3913 // CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
3914 // CHECK9-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
3915 // CHECK9-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
3916 // CHECK9-NEXT:    store i64 [[AAA]], ptr [[AAA_ADDR]], align 8
3917 // CHECK9-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
3918 // CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
3919 // CHECK9-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
3920 // CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
3921 // CHECK9-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 4
3922 // CHECK9-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2
3923 // CHECK9-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i32
3924 // CHECK9-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
3925 // CHECK9-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
3926 // CHECK9-NEXT:    store i16 [[CONV2]], ptr [[AA_ADDR]], align 2
3927 // CHECK9-NEXT:    [[TMP3:%.*]] = load i8, ptr [[AAA_ADDR]], align 1
3928 // CHECK9-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP3]] to i32
3929 // CHECK9-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
3930 // CHECK9-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8
3931 // CHECK9-NEXT:    store i8 [[CONV5]], ptr [[AAA_ADDR]], align 1
3932 // CHECK9-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2
3933 // CHECK9-NEXT:    [[TMP4:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
3934 // CHECK9-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP4]], 1
3935 // CHECK9-NEXT:    store i32 [[ADD6]], ptr [[ARRAYIDX]], align 4
3936 // CHECK9-NEXT:    ret void
3937 //
3938 //
3939 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l233
3940 // CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
3941 // CHECK9-NEXT:  entry:
3942 // CHECK9-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
3943 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
3944 // CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
3945 // CHECK9-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
3946 // CHECK9-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
3947 // CHECK9-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
3948 // CHECK9-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
3949 // CHECK9-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
3950 // CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
3951 // CHECK9-NEXT:    store i64 [[B]], ptr [[B_ADDR]], align 8
3952 // CHECK9-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
3953 // CHECK9-NEXT:    store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
3954 // CHECK9-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
3955 // CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
3956 // CHECK9-NEXT:    [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
3957 // CHECK9-NEXT:    [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
3958 // CHECK9-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
3959 // CHECK9-NEXT:    [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4
3960 // CHECK9-NEXT:    store i32 [[TMP4]], ptr [[B_CASTED]], align 4
3961 // CHECK9-NEXT:    [[TMP5:%.*]] = load i64, ptr [[B_CASTED]], align 8
3962 // CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l233.omp_outlined, ptr [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], ptr [[TMP3]])
3963 // CHECK9-NEXT:    ret void
3964 //
3965 //
3966 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l233.omp_outlined
3967 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
3968 // CHECK9-NEXT:  entry:
3969 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
3970 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
3971 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
3972 // CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
3973 // CHECK9-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
3974 // CHECK9-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
3975 // CHECK9-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
3976 // CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
3977 // CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
3978 // CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
3979 // CHECK9-NEXT:    store i64 [[B]], ptr [[B_ADDR]], align 8
3980 // CHECK9-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
3981 // CHECK9-NEXT:    store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
3982 // CHECK9-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
3983 // CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
3984 // CHECK9-NEXT:    [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
3985 // CHECK9-NEXT:    [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
3986 // CHECK9-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
3987 // CHECK9-NEXT:    [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4
3988 // CHECK9-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP4]] to double
3989 // CHECK9-NEXT:    [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
3990 // CHECK9-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0
3991 // CHECK9-NEXT:    store double [[ADD]], ptr [[A]], align 8
3992 // CHECK9-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0
3993 // CHECK9-NEXT:    [[TMP5:%.*]] = load double, ptr [[A3]], align 8
3994 // CHECK9-NEXT:    [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
3995 // CHECK9-NEXT:    store double [[INC]], ptr [[A3]], align 8
3996 // CHECK9-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
3997 // CHECK9-NEXT:    [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]]
3998 // CHECK9-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i64 [[TMP6]]
3999 // CHECK9-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1
4000 // CHECK9-NEXT:    store i16 [[CONV4]], ptr [[ARRAYIDX5]], align 2
4001 // CHECK9-NEXT:    ret void
4002 //
4003 //
4004 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l198
4005 // CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
4006 // CHECK9-NEXT:  entry:
4007 // CHECK9-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
4008 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
4009 // CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
4010 // CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
4011 // CHECK9-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
4012 // CHECK9-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
4013 // CHECK9-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
4014 // CHECK9-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
4015 // CHECK9-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
4016 // CHECK9-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
4017 // CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
4018 // CHECK9-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
4019 // CHECK9-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 4
4020 // CHECK9-NEXT:    [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8
4021 // CHECK9-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
4022 // CHECK9-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
4023 // CHECK9-NEXT:    [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8
4024 // CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l198.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], ptr [[TMP0]])
4025 // CHECK9-NEXT:    ret void
4026 //
4027 //
4028 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l198.omp_outlined
4029 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
4030 // CHECK9-NEXT:  entry:
4031 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
4032 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
4033 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
4034 // CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
4035 // CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
4036 // CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
4037 // CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
4038 // CHECK9-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
4039 // CHECK9-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
4040 // CHECK9-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
4041 // CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
4042 // CHECK9-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
4043 // CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
4044 // CHECK9-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 4
4045 // CHECK9-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2
4046 // CHECK9-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i32
4047 // CHECK9-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
4048 // CHECK9-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
4049 // CHECK9-NEXT:    store i16 [[CONV2]], ptr [[AA_ADDR]], align 2
4050 // CHECK9-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2
4051 // CHECK9-NEXT:    [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
4052 // CHECK9-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1
4053 // CHECK9-NEXT:    store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4
4054 // CHECK9-NEXT:    ret void
4055 //
4056 //
4057 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101
4058 // CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] {
4059 // CHECK11-NEXT:  entry:
4060 // CHECK11-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
4061 // CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
4062 // CHECK11-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
4063 // CHECK11-NEXT:    [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4
4064 // CHECK11-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
4065 // CHECK11-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
4066 // CHECK11-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
4067 // CHECK11-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
4068 // CHECK11-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
4069 // CHECK11-NEXT:    store i32 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4
4070 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
4071 // CHECK11-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4
4072 // CHECK11-NEXT:    call void @__kmpc_push_num_teams(ptr @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
4073 // CHECK11-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
4074 // CHECK11-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
4075 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4
4076 // CHECK11-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.omp_outlined, i32 [[TMP4]])
4077 // CHECK11-NEXT:    ret void
4078 //
4079 //
4080 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.omp_outlined
4081 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {
4082 // CHECK11-NEXT:  entry:
4083 // CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
4084 // CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
4085 // CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
4086 // CHECK11-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
4087 // CHECK11-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
4088 // CHECK11-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
4089 // CHECK11-NEXT:    ret void
4090 //
4091 //
4092 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
4093 // CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {
4094 // CHECK11-NEXT:  entry:
4095 // CHECK11-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
4096 // CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
4097 // CHECK11-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
4098 // CHECK11-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
4099 // CHECK11-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
4100 // CHECK11-NEXT:    [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2
4101 // CHECK11-NEXT:    store i16 [[TMP0]], ptr [[AA_CASTED]], align 2
4102 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[AA_CASTED]], align 4
4103 // CHECK11-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined, i32 [[TMP1]])
4104 // CHECK11-NEXT:    ret void
4105 //
4106 //
4107 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined
4108 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {
4109 // CHECK11-NEXT:  entry:
4110 // CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
4111 // CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
4112 // CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
4113 // CHECK11-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
4114 // CHECK11-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
4115 // CHECK11-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
4116 // CHECK11-NEXT:    [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2
4117 // CHECK11-NEXT:    [[CONV:%.*]] = sext i16 [[TMP0]] to i32
4118 // CHECK11-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV]], 1
4119 // CHECK11-NEXT:    [[CONV1:%.*]] = trunc i32 [[ADD]] to i16
4120 // CHECK11-NEXT:    store i16 [[CONV1]], ptr [[AA_ADDR]], align 2
4121 // CHECK11-NEXT:    ret void
4122 //
4123 //
4124 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118
4125 // CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {
4126 // CHECK11-NEXT:  entry:
4127 // CHECK11-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
4128 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
4129 // CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
4130 // CHECK11-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
4131 // CHECK11-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
4132 // CHECK11-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
4133 // CHECK11-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
4134 // CHECK11-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
4135 // CHECK11-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
4136 // CHECK11-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 4
4137 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4
4138 // CHECK11-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2
4139 // CHECK11-NEXT:    store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
4140 // CHECK11-NEXT:    [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4
4141 // CHECK11-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined, i32 [[TMP1]], i32 [[TMP3]])
4142 // CHECK11-NEXT:    ret void
4143 //
4144 //
4145 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined
4146 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {
4147 // CHECK11-NEXT:  entry:
4148 // CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
4149 // CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
4150 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
4151 // CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
4152 // CHECK11-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
4153 // CHECK11-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
4154 // CHECK11-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
4155 // CHECK11-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
4156 // CHECK11-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
4157 // CHECK11-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
4158 // CHECK11-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 4
4159 // CHECK11-NEXT:    [[TMP1:%.*]] = load i16, ptr [[AA_ADDR]], align 2
4160 // CHECK11-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
4161 // CHECK11-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
4162 // CHECK11-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
4163 // CHECK11-NEXT:    store i16 [[CONV2]], ptr [[AA_ADDR]], align 2
4164 // CHECK11-NEXT:    ret void
4165 //
4166 //
4167 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l124
4168 // CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {
4169 // CHECK11-NEXT:  entry:
4170 // CHECK11-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
4171 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
4172 // CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
4173 // CHECK11-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
4174 // CHECK11-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
4175 // CHECK11-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
4176 // CHECK11-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
4177 // CHECK11-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
4178 // CHECK11-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
4179 // CHECK11-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 4
4180 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4
4181 // CHECK11-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2
4182 // CHECK11-NEXT:    store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
4183 // CHECK11-NEXT:    [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4
4184 // CHECK11-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l124.omp_outlined, i32 [[TMP1]], i32 [[TMP3]])
4185 // CHECK11-NEXT:    ret void
4186 //
4187 //
4188 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l124.omp_outlined
4189 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {
4190 // CHECK11-NEXT:  entry:
4191 // CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
4192 // CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
4193 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
4194 // CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
4195 // CHECK11-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
4196 // CHECK11-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
4197 // CHECK11-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
4198 // CHECK11-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
4199 // CHECK11-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
4200 // CHECK11-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
4201 // CHECK11-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 4
4202 // CHECK11-NEXT:    [[TMP1:%.*]] = load i16, ptr [[AA_ADDR]], align 2
4203 // CHECK11-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
4204 // CHECK11-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
4205 // CHECK11-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
4206 // CHECK11-NEXT:    store i16 [[CONV2]], ptr [[AA_ADDR]], align 2
4207 // CHECK11-NEXT:    ret void
4208 //
4209 //
4210 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l148
4211 // CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] {
4212 // CHECK11-NEXT:  entry:
4213 // CHECK11-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
4214 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
4215 // CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
4216 // CHECK11-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
4217 // CHECK11-NEXT:    [[BN_ADDR:%.*]] = alloca ptr, align 4
4218 // CHECK11-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
4219 // CHECK11-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
4220 // CHECK11-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
4221 // CHECK11-NEXT:    [[CN_ADDR:%.*]] = alloca ptr, align 4
4222 // CHECK11-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4
4223 // CHECK11-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
4224 // CHECK11-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
4225 // CHECK11-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
4226 // CHECK11-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
4227 // CHECK11-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
4228 // CHECK11-NEXT:    store ptr [[BN]], ptr [[BN_ADDR]], align 4
4229 // CHECK11-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
4230 // CHECK11-NEXT:    store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
4231 // CHECK11-NEXT:    store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4
4232 // CHECK11-NEXT:    store ptr [[CN]], ptr [[CN_ADDR]], align 4
4233 // CHECK11-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4
4234 // CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
4235 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
4236 // CHECK11-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4
4237 // CHECK11-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
4238 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
4239 // CHECK11-NEXT:    [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4
4240 // CHECK11-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4
4241 // CHECK11-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4
4242 // CHECK11-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
4243 // CHECK11-NEXT:    store i32 [[TMP8]], ptr [[A_CASTED]], align 4
4244 // CHECK11-NEXT:    [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4
4245 // CHECK11-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l148.omp_outlined, i32 [[TMP9]], ptr [[TMP0]], i32 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]])
4246 // CHECK11-NEXT:    ret void
4247 //
4248 //
4249 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l148.omp_outlined
4250 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] {
4251 // CHECK11-NEXT:  entry:
4252 // CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
4253 // CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
4254 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
4255 // CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
4256 // CHECK11-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
4257 // CHECK11-NEXT:    [[BN_ADDR:%.*]] = alloca ptr, align 4
4258 // CHECK11-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
4259 // CHECK11-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
4260 // CHECK11-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
4261 // CHECK11-NEXT:    [[CN_ADDR:%.*]] = alloca ptr, align 4
4262 // CHECK11-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4
4263 // CHECK11-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
4264 // CHECK11-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
4265 // CHECK11-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
4266 // CHECK11-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
4267 // CHECK11-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
4268 // CHECK11-NEXT:    store ptr [[BN]], ptr [[BN_ADDR]], align 4
4269 // CHECK11-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
4270 // CHECK11-NEXT:    store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
4271 // CHECK11-NEXT:    store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4
4272 // CHECK11-NEXT:    store ptr [[CN]], ptr [[CN_ADDR]], align 4
4273 // CHECK11-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4
4274 // CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
4275 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
4276 // CHECK11-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4
4277 // CHECK11-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
4278 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
4279 // CHECK11-NEXT:    [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4
4280 // CHECK11-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4
4281 // CHECK11-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4
4282 // CHECK11-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
4283 // CHECK11-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
4284 // CHECK11-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 4
4285 // CHECK11-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 2
4286 // CHECK11-NEXT:    [[TMP9:%.*]] = load float, ptr [[ARRAYIDX]], align 4
4287 // CHECK11-NEXT:    [[CONV:%.*]] = fpext float [[TMP9]] to double
4288 // CHECK11-NEXT:    [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00
4289 // CHECK11-NEXT:    [[CONV6:%.*]] = fptrunc double [[ADD5]] to float
4290 // CHECK11-NEXT:    store float [[CONV6]], ptr [[ARRAYIDX]], align 4
4291 // CHECK11-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i32 3
4292 // CHECK11-NEXT:    [[TMP10:%.*]] = load float, ptr [[ARRAYIDX7]], align 4
4293 // CHECK11-NEXT:    [[CONV8:%.*]] = fpext float [[TMP10]] to double
4294 // CHECK11-NEXT:    [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00
4295 // CHECK11-NEXT:    [[CONV10:%.*]] = fptrunc double [[ADD9]] to float
4296 // CHECK11-NEXT:    store float [[CONV10]], ptr [[ARRAYIDX7]], align 4
4297 // CHECK11-NEXT:    [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 1
4298 // CHECK11-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX11]], i32 0, i32 2
4299 // CHECK11-NEXT:    [[TMP11:%.*]] = load double, ptr [[ARRAYIDX12]], align 8
4300 // CHECK11-NEXT:    [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00
4301 // CHECK11-NEXT:    store double [[ADD13]], ptr [[ARRAYIDX12]], align 8
4302 // CHECK11-NEXT:    [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]]
4303 // CHECK11-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i32 [[TMP12]]
4304 // CHECK11-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX14]], i32 3
4305 // CHECK11-NEXT:    [[TMP13:%.*]] = load double, ptr [[ARRAYIDX15]], align 8
4306 // CHECK11-NEXT:    [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00
4307 // CHECK11-NEXT:    store double [[ADD16]], ptr [[ARRAYIDX15]], align 8
4308 // CHECK11-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0
4309 // CHECK11-NEXT:    [[TMP14:%.*]] = load i64, ptr [[X]], align 4
4310 // CHECK11-NEXT:    [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1
4311 // CHECK11-NEXT:    store i64 [[ADD17]], ptr [[X]], align 4
4312 // CHECK11-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1
4313 // CHECK11-NEXT:    [[TMP15:%.*]] = load i8, ptr [[Y]], align 4
4314 // CHECK11-NEXT:    [[CONV18:%.*]] = sext i8 [[TMP15]] to i32
4315 // CHECK11-NEXT:    [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1
4316 // CHECK11-NEXT:    [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8
4317 // CHECK11-NEXT:    store i8 [[CONV20]], ptr [[Y]], align 4
4318 // CHECK11-NEXT:    ret void
4319 //
4320 //
4321 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160
4322 // CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR0]] {
4323 // CHECK11-NEXT:  entry:
4324 // CHECK11-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
4325 // CHECK11-NEXT:    [[NN_ADDR:%.*]] = alloca i32, align 4
4326 // CHECK11-NEXT:    [[NN_CASTED:%.*]] = alloca i32, align 4
4327 // CHECK11-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
4328 // CHECK11-NEXT:    store i32 [[NN]], ptr [[NN_ADDR]], align 4
4329 // CHECK11-NEXT:    [[TMP0:%.*]] = load i32, ptr [[NN_ADDR]], align 4
4330 // CHECK11-NEXT:    store i32 [[TMP0]], ptr [[NN_CASTED]], align 4
4331 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[NN_CASTED]], align 4
4332 // CHECK11-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined, i32 [[TMP1]])
4333 // CHECK11-NEXT:    ret void
4334 //
4335 //
4336 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined
4337 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR0]] {
4338 // CHECK11-NEXT:  entry:
4339 // CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
4340 // CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
4341 // CHECK11-NEXT:    [[NN_ADDR:%.*]] = alloca i32, align 4
4342 // CHECK11-NEXT:    [[NN_CASTED:%.*]] = alloca i32, align 4
4343 // CHECK11-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
4344 // CHECK11-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
4345 // CHECK11-NEXT:    store i32 [[NN]], ptr [[NN_ADDR]], align 4
4346 // CHECK11-NEXT:    [[TMP0:%.*]] = load i32, ptr [[NN_ADDR]], align 4
4347 // CHECK11-NEXT:    store i32 [[TMP0]], ptr [[NN_CASTED]], align 4
4348 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[NN_CASTED]], align 4
4349 // CHECK11-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined.omp_outlined, i32 [[TMP1]])
4350 // CHECK11-NEXT:    ret void
4351 //
4352 //
4353 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.omp_outlined.omp_outlined
4354 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR0]] {
4355 // CHECK11-NEXT:  entry:
4356 // CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
4357 // CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
4358 // CHECK11-NEXT:    [[NN_ADDR:%.*]] = alloca i32, align 4
4359 // CHECK11-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
4360 // CHECK11-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
4361 // CHECK11-NEXT:    store i32 [[NN]], ptr [[NN_ADDR]], align 4
4362 // CHECK11-NEXT:    ret void
4363 //
4364 //
4365 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l163
4366 // CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR0]] {
4367 // CHECK11-NEXT:  entry:
4368 // CHECK11-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
4369 // CHECK11-NEXT:    [[NN_ADDR:%.*]] = alloca i32, align 4
4370 // CHECK11-NEXT:    [[NN_CASTED:%.*]] = alloca i32, align 4
4371 // CHECK11-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
4372 // CHECK11-NEXT:    store i32 [[NN]], ptr [[NN_ADDR]], align 4
4373 // CHECK11-NEXT:    [[TMP0:%.*]] = load i32, ptr [[NN_ADDR]], align 4
4374 // CHECK11-NEXT:    store i32 [[TMP0]], ptr [[NN_CASTED]], align 4
4375 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[NN_CASTED]], align 4
4376 // CHECK11-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l163.omp_outlined, i32 [[TMP1]])
4377 // CHECK11-NEXT:    ret void
4378 //
4379 //
4380 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l163.omp_outlined
4381 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR0]] {
4382 // CHECK11-NEXT:  entry:
4383 // CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
4384 // CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
4385 // CHECK11-NEXT:    [[NN_ADDR:%.*]] = alloca i32, align 4
4386 // CHECK11-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
4387 // CHECK11-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
4388 // CHECK11-NEXT:    store i32 [[NN]], ptr [[NN_ADDR]], align 4
4389 // CHECK11-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l163.omp_outlined.omp_outlined, ptr [[NN_ADDR]])
4390 // CHECK11-NEXT:    ret void
4391 //
4392 //
4393 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l163.omp_outlined.omp_outlined
4394 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] {
4395 // CHECK11-NEXT:  entry:
4396 // CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
4397 // CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
4398 // CHECK11-NEXT:    [[NN_ADDR:%.*]] = alloca ptr, align 4
4399 // CHECK11-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
4400 // CHECK11-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
4401 // CHECK11-NEXT:    store ptr [[NN]], ptr [[NN_ADDR]], align 4
4402 // CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[NN_ADDR]], align 4
4403 // CHECK11-NEXT:    ret void
4404 //
4405 //
4406 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l188
4407 // CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[VLA:%.*]]) #[[ATTR0]] {
4408 // CHECK11-NEXT:  entry:
4409 // CHECK11-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
4410 // CHECK11-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
4411 // CHECK11-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
4412 // CHECK11-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
4413 // CHECK11-NEXT:    [[TMP0:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
4414 // CHECK11-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l188.omp_outlined, i32 [[TMP0]])
4415 // CHECK11-NEXT:    ret void
4416 //
4417 //
4418 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l188.omp_outlined
4419 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[VLA:%.*]]) #[[ATTR0]] {
4420 // CHECK11-NEXT:  entry:
4421 // CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
4422 // CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
4423 // CHECK11-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
4424 // CHECK11-NEXT:    [[F:%.*]] = alloca ptr, align 4
4425 // CHECK11-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
4426 // CHECK11-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
4427 // CHECK11-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
4428 // CHECK11-NEXT:    [[TMP0:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
4429 // CHECK11-NEXT:    ret void
4430 //
4431 //
4432 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l215
4433 // CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
4434 // CHECK11-NEXT:  entry:
4435 // CHECK11-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
4436 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
4437 // CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
4438 // CHECK11-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
4439 // CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
4440 // CHECK11-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
4441 // CHECK11-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
4442 // CHECK11-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
4443 // CHECK11-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
4444 // CHECK11-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
4445 // CHECK11-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
4446 // CHECK11-NEXT:    store i32 [[AAA]], ptr [[AAA_ADDR]], align 4
4447 // CHECK11-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
4448 // CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
4449 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
4450 // CHECK11-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 4
4451 // CHECK11-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4
4452 // CHECK11-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
4453 // CHECK11-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
4454 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4
4455 // CHECK11-NEXT:    [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 1
4456 // CHECK11-NEXT:    store i8 [[TMP5]], ptr [[AAA_CASTED]], align 1
4457 // CHECK11-NEXT:    [[TMP6:%.*]] = load i32, ptr [[AAA_CASTED]], align 4
4458 // CHECK11-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l215.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], ptr [[TMP0]])
4459 // CHECK11-NEXT:    ret void
4460 //
4461 //
4462 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l215.omp_outlined
4463 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
4464 // CHECK11-NEXT:  entry:
4465 // CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
4466 // CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
4467 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
4468 // CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
4469 // CHECK11-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
4470 // CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
4471 // CHECK11-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
4472 // CHECK11-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
4473 // CHECK11-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
4474 // CHECK11-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
4475 // CHECK11-NEXT:    store i32 [[AAA]], ptr [[AAA_ADDR]], align 4
4476 // CHECK11-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
4477 // CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
4478 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
4479 // CHECK11-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
4480 // CHECK11-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 4
4481 // CHECK11-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2
4482 // CHECK11-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i32
4483 // CHECK11-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
4484 // CHECK11-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
4485 // CHECK11-NEXT:    store i16 [[CONV2]], ptr [[AA_ADDR]], align 2
4486 // CHECK11-NEXT:    [[TMP3:%.*]] = load i8, ptr [[AAA_ADDR]], align 1
4487 // CHECK11-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP3]] to i32
4488 // CHECK11-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
4489 // CHECK11-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8
4490 // CHECK11-NEXT:    store i8 [[CONV5]], ptr [[AAA_ADDR]], align 1
4491 // CHECK11-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2
4492 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
4493 // CHECK11-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP4]], 1
4494 // CHECK11-NEXT:    store i32 [[ADD6]], ptr [[ARRAYIDX]], align 4
4495 // CHECK11-NEXT:    ret void
4496 //
4497 //
4498 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l233
4499 // CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
4500 // CHECK11-NEXT:  entry:
4501 // CHECK11-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
4502 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
4503 // CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
4504 // CHECK11-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
4505 // CHECK11-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
4506 // CHECK11-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
4507 // CHECK11-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
4508 // CHECK11-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
4509 // CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
4510 // CHECK11-NEXT:    store i32 [[B]], ptr [[B_ADDR]], align 4
4511 // CHECK11-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
4512 // CHECK11-NEXT:    store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
4513 // CHECK11-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
4514 // CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
4515 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
4516 // CHECK11-NEXT:    [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
4517 // CHECK11-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
4518 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4
4519 // CHECK11-NEXT:    store i32 [[TMP4]], ptr [[B_CASTED]], align 4
4520 // CHECK11-NEXT:    [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4
4521 // CHECK11-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l233.omp_outlined, ptr [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], ptr [[TMP3]])
4522 // CHECK11-NEXT:    ret void
4523 //
4524 //
4525 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l233.omp_outlined
4526 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
4527 // CHECK11-NEXT:  entry:
4528 // CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
4529 // CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
4530 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
4531 // CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
4532 // CHECK11-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
4533 // CHECK11-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
4534 // CHECK11-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
4535 // CHECK11-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
4536 // CHECK11-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
4537 // CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
4538 // CHECK11-NEXT:    store i32 [[B]], ptr [[B_ADDR]], align 4
4539 // CHECK11-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
4540 // CHECK11-NEXT:    store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
4541 // CHECK11-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
4542 // CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
4543 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
4544 // CHECK11-NEXT:    [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
4545 // CHECK11-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
4546 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4
4547 // CHECK11-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP4]] to double
4548 // CHECK11-NEXT:    [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
4549 // CHECK11-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0
4550 // CHECK11-NEXT:    store double [[ADD]], ptr [[A]], align 4
4551 // CHECK11-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0
4552 // CHECK11-NEXT:    [[TMP5:%.*]] = load double, ptr [[A3]], align 4
4553 // CHECK11-NEXT:    [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
4554 // CHECK11-NEXT:    store double [[INC]], ptr [[A3]], align 4
4555 // CHECK11-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
4556 // CHECK11-NEXT:    [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]]
4557 // CHECK11-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i32 [[TMP6]]
4558 // CHECK11-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1
4559 // CHECK11-NEXT:    store i16 [[CONV4]], ptr [[ARRAYIDX5]], align 2
4560 // CHECK11-NEXT:    ret void
4561 //
4562 //
4563 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l198
4564 // CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
4565 // CHECK11-NEXT:  entry:
4566 // CHECK11-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
4567 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
4568 // CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
4569 // CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
4570 // CHECK11-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
4571 // CHECK11-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
4572 // CHECK11-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
4573 // CHECK11-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
4574 // CHECK11-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
4575 // CHECK11-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
4576 // CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
4577 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
4578 // CHECK11-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 4
4579 // CHECK11-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4
4580 // CHECK11-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
4581 // CHECK11-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
4582 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4
4583 // CHECK11-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB1]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l198.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], ptr [[TMP0]])
4584 // CHECK11-NEXT:    ret void
4585 //
4586 //
4587 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l198.omp_outlined
4588 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
4589 // CHECK11-NEXT:  entry:
4590 // CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
4591 // CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
4592 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
4593 // CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
4594 // CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
4595 // CHECK11-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
4596 // CHECK11-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
4597 // CHECK11-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
4598 // CHECK11-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
4599 // CHECK11-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
4600 // CHECK11-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
4601 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
4602 // CHECK11-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
4603 // CHECK11-NEXT:    store i32 [[ADD]], ptr [[A_ADDR]], align 4
4604 // CHECK11-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2
4605 // CHECK11-NEXT:    [[CONV:%.*]] = sext i16 [[TMP2]] to i32
4606 // CHECK11-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
4607 // CHECK11-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
4608 // CHECK11-NEXT:    store i16 [[CONV2]], ptr [[AA_ADDR]], align 2
4609 // CHECK11-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2
4610 // CHECK11-NEXT:    [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
4611 // CHECK11-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1
4612 // CHECK11-NEXT:    store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4
4613 // CHECK11-NEXT:    ret void
4614 //