Run DCE after a LoopFlatten test to reduce spurious output [nfc]
[llvm-project.git] / clang / test / OpenMP / target_teams_distribute_codegen.cpp
blobce489d3b4e2a37216ffa8e5e589df6e86396714f
1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
2 // Test host codegen.
3 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1
4 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
5 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1
6 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3
7 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
8 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3
10 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
11 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
12 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
13 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
14 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
15 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
17 // Test target codegen - host bc file has to be created first.
18 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
19 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9
20 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
21 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9
22 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
23 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11
24 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
25 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11
27 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
28 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
29 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
30 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
31 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
32 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
33 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
34 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
36 // Test host codegen.
37 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1
38 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
39 // RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1
40 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3
41 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
42 // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3
44 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
45 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
46 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
47 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
48 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
49 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
51 // Test target codegen - host bc file has to be created first.
52 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
53 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9
54 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
55 // RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9
56 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
57 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11
58 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
59 // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11
61 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
62 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
63 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
64 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
65 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
66 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
67 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
68 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
70 // expected-no-diagnostics
71 #ifndef HEADER
72 #define HEADER
77 // We have 8 target regions, but only 7 that actually will generate offloading
78 // code, only 6 will have mapped arguments, and only 4 have all-constant map
79 // sizes.
83 // Check target registration is registered as a Ctor.
86 template<typename tx, typename ty>
87 struct TT{
88 tx X;
89 ty Y;
92 int global;
94 int foo(int n) {
95 int a = 0;
96 short aa = 0;
97 float b[10];
98 float bn[n];
99 double c[5][10];
100 double cn[5][n];
101 TT<long long, char> d;
103 #pragma omp target teams distribute num_teams(a) thread_limit(a) firstprivate(aa) nowait
104 for (int i = 0; i < 10; ++i) {
107 #pragma omp target teams distribute if(target: 0)
108 for (int i = 0; i < 10; ++i) {
109 a += 1;
113 #pragma omp target teams distribute if(target: 1)
114 for (int i = 0; i < 10; ++i) {
115 aa += 1;
120 #pragma omp target teams distribute if(target: n>10)
121 for (int i = 0; i < 10; ++i) {
122 a += 1;
123 aa += 1;
126 // We capture 3 VLA sizes in this target region
132 // The names below are not necessarily consistent with the names used for the
133 // addresses above as some are repeated.
145 #pragma omp target teams distribute if(target: n>20) dist_schedule(static, n)
146 for (int i = 0; i < 10; ++i) {
147 a += 1;
148 b[2] += 1.0;
149 bn[3] += 1.0;
150 c[1][2] += 1.0;
151 cn[1][3] += 1.0;
152 d.X += 1;
153 d.Y += 1;
156 return a;
159 // Check that the offloading functions are emitted and that the arguments are
160 // correct and loaded correctly for the target regions in foo().
165 // Create stack storage and store argument in there.
167 // Create stack storage and store argument in there.
169 // Create stack storage and store argument in there.
171 // Create local storage for each capture.
175 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.
177 template<typename tx>
178 tx ftemplate(int n) {
179 tx a = 0;
180 short aa = 0;
181 tx b[10];
183 #pragma omp target teams distribute if(target: n>40)
184 for (int i = 0; i < 10; ++i) {
185 a += 1;
186 aa += 1;
187 b[2] += 1;
190 return a;
193 static
194 int fstatic(int n) {
195 int a = 0;
196 short aa = 0;
197 char aaa = 0;
198 int b[10];
200 #pragma omp target teams distribute if(target: n>50)
201 for (int i = a; i < n; ++i) {
202 a += 1;
203 aa += 1;
204 aaa += 1;
205 b[2] += 1;
208 return a;
211 struct S1 {
212 double a;
214 int r1(int n){
215 int b = n+1;
216 short int c[2][n];
218 #pragma omp target teams distribute if(target: n>60)
219 for (int i = 0; i < 10; ++i) {
220 this->a = (double)b + 1.5;
221 c[1][1] = ++a;
224 return c[1][1] + (int)b;
228 int bar(int n){
229 int a = 0;
231 a += foo(n);
233 S1 S;
234 a += S.r1(n);
236 a += fstatic(n);
238 a += ftemplate<int>(n);
240 return a;
245 // We capture 2 VLA sizes in this target region
248 // The names below are not necessarily consistent with the names used for the
249 // addresses above as some are repeated.
271 // Check that the offloading functions are emitted and that the arguments are
272 // correct and loaded correctly for the target regions of the callees of bar().
274 // Create local storage for each capture.
275 // Store captures in the context.
278 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.
281 // Create local storage for each capture.
282 // Store captures in the context.
287 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.
289 // Create local storage for each capture.
290 // Store captures in the context.
294 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.
296 #endif
297 // CHECK1-LABEL: define {{[^@]+}}@_Z3fooi
298 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
299 // CHECK1-NEXT: entry:
300 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
301 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4
302 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2
303 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x float], align 4
304 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8
305 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
306 // CHECK1-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8
307 // CHECK1-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8
308 // CHECK1-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
309 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
310 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
311 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
312 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
313 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED3:%.*]] = alloca i64, align 8
314 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8
315 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 8
316 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 8
317 // CHECK1-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4
318 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
319 // CHECK1-NEXT: [[AA_CASTED4:%.*]] = alloca i64, align 8
320 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [1 x ptr], align 8
321 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [1 x ptr], align 8
322 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [1 x ptr], align 8
323 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
324 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
325 // CHECK1-NEXT: [[A_CASTED8:%.*]] = alloca i64, align 8
326 // CHECK1-NEXT: [[AA_CASTED9:%.*]] = alloca i64, align 8
327 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [2 x ptr], align 8
328 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS11:%.*]] = alloca [2 x ptr], align 8
329 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [2 x ptr], align 8
330 // CHECK1-NEXT: [[_TMP13:%.*]] = alloca i32, align 4
331 // CHECK1-NEXT: [[KERNEL_ARGS14:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
332 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_17:%.*]] = alloca i32, align 4
333 // CHECK1-NEXT: [[A_CASTED18:%.*]] = alloca i64, align 8
334 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED19:%.*]] = alloca i64, align 8
335 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS22:%.*]] = alloca [10 x ptr], align 8
336 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS23:%.*]] = alloca [10 x ptr], align 8
337 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS24:%.*]] = alloca [10 x ptr], align 8
338 // CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8
339 // CHECK1-NEXT: [[_TMP25:%.*]] = alloca i32, align 4
340 // CHECK1-NEXT: [[KERNEL_ARGS26:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
341 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])
342 // CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
343 // CHECK1-NEXT: store i32 0, ptr [[A]], align 4
344 // CHECK1-NEXT: store i16 0, ptr [[AA]], align 2
345 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
346 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
347 // CHECK1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()
348 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8
349 // CHECK1-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4
350 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8
351 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
352 // CHECK1-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
353 // CHECK1-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]]
354 // CHECK1-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8
355 // CHECK1-NEXT: store i64 [[TMP5]], ptr [[__VLA_EXPR1]], align 8
356 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4
357 // CHECK1-NEXT: store i32 [[TMP7]], ptr [[DOTCAPTURE_EXPR_]], align 4
358 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4
359 // CHECK1-NEXT: store i32 [[TMP8]], ptr [[DOTCAPTURE_EXPR_2]], align 4
360 // CHECK1-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA]], align 2
361 // CHECK1-NEXT: store i16 [[TMP9]], ptr [[AA_CASTED]], align 2
362 // CHECK1-NEXT: [[TMP10:%.*]] = load i64, ptr [[AA_CASTED]], align 8
363 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
364 // CHECK1-NEXT: store i32 [[TMP11]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
365 // CHECK1-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8
366 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
367 // CHECK1-NEXT: store i32 [[TMP13]], ptr [[DOTCAPTURE_EXPR__CASTED3]], align 4
368 // CHECK1-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED3]], align 8
369 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
370 // CHECK1-NEXT: store i64 [[TMP10]], ptr [[TMP15]], align 8
371 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
372 // CHECK1-NEXT: store i64 [[TMP10]], ptr [[TMP16]], align 8
373 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
374 // CHECK1-NEXT: store ptr null, ptr [[TMP17]], align 8
375 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
376 // CHECK1-NEXT: store i64 [[TMP12]], ptr [[TMP18]], align 8
377 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
378 // CHECK1-NEXT: store i64 [[TMP12]], ptr [[TMP19]], align 8
379 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
380 // CHECK1-NEXT: store ptr null, ptr [[TMP20]], align 8
381 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
382 // CHECK1-NEXT: store i64 [[TMP14]], ptr [[TMP21]], align 8
383 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
384 // CHECK1-NEXT: store i64 [[TMP14]], ptr [[TMP22]], align 8
385 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
386 // CHECK1-NEXT: store ptr null, ptr [[TMP23]], align 8
387 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
388 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
389 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0
390 // CHECK1-NEXT: [[TMP27:%.*]] = load i16, ptr [[AA]], align 2
391 // CHECK1-NEXT: store i16 [[TMP27]], ptr [[TMP26]], align 4
392 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 1
393 // CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
394 // CHECK1-NEXT: store i32 [[TMP29]], ptr [[TMP28]], align 4
395 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 2
396 // CHECK1-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
397 // CHECK1-NEXT: store i32 [[TMP31]], ptr [[TMP30]], align 4
398 // CHECK1-NEXT: [[TMP32:%.*]] = call ptr @__kmpc_omp_target_task_alloc(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i64 120, i64 12, ptr @.omp_task_entry., i64 -1)
399 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP32]], i32 0, i32 0
400 // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP33]], i32 0, i32 0
401 // CHECK1-NEXT: [[TMP35:%.*]] = load ptr, ptr [[TMP34]], align 8
402 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP35]], ptr align 4 [[AGG_CAPTURED]], i64 12, i1 false)
403 // CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP32]], i32 0, i32 1
404 // CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP36]], i32 0, i32 0
405 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP37]], ptr align 8 [[TMP24]], i64 24, i1 false)
406 // CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP36]], i32 0, i32 1
407 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP38]], ptr align 8 [[TMP25]], i64 24, i1 false)
408 // CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP36]], i32 0, i32 2
409 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP39]], ptr align 8 @.offload_sizes, i64 24, i1 false)
410 // CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP36]], i32 0, i32 3
411 // CHECK1-NEXT: [[TMP41:%.*]] = load i16, ptr [[AA]], align 2
412 // CHECK1-NEXT: store i16 [[TMP41]], ptr [[TMP40]], align 8
413 // CHECK1-NEXT: [[TMP42:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB2]], i32 [[TMP0]], ptr [[TMP32]])
414 // CHECK1-NEXT: [[TMP43:%.*]] = load i32, ptr [[A]], align 4
415 // CHECK1-NEXT: store i32 [[TMP43]], ptr [[A_CASTED]], align 4
416 // CHECK1-NEXT: [[TMP44:%.*]] = load i64, ptr [[A_CASTED]], align 8
417 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107(i64 [[TMP44]]) #[[ATTR3:[0-9]+]]
418 // CHECK1-NEXT: [[TMP45:%.*]] = load i16, ptr [[AA]], align 2
419 // CHECK1-NEXT: store i16 [[TMP45]], ptr [[AA_CASTED4]], align 2
420 // CHECK1-NEXT: [[TMP46:%.*]] = load i64, ptr [[AA_CASTED4]], align 8
421 // CHECK1-NEXT: [[TMP47:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0
422 // CHECK1-NEXT: store i64 [[TMP46]], ptr [[TMP47]], align 8
423 // CHECK1-NEXT: [[TMP48:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0
424 // CHECK1-NEXT: store i64 [[TMP46]], ptr [[TMP48]], align 8
425 // CHECK1-NEXT: [[TMP49:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 0
426 // CHECK1-NEXT: store ptr null, ptr [[TMP49]], align 8
427 // CHECK1-NEXT: [[TMP50:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0
428 // CHECK1-NEXT: [[TMP51:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0
429 // CHECK1-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
430 // CHECK1-NEXT: store i32 2, ptr [[TMP52]], align 4
431 // CHECK1-NEXT: [[TMP53:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
432 // CHECK1-NEXT: store i32 1, ptr [[TMP53]], align 4
433 // CHECK1-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
434 // CHECK1-NEXT: store ptr [[TMP50]], ptr [[TMP54]], align 8
435 // CHECK1-NEXT: [[TMP55:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
436 // CHECK1-NEXT: store ptr [[TMP51]], ptr [[TMP55]], align 8
437 // CHECK1-NEXT: [[TMP56:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
438 // CHECK1-NEXT: store ptr @.offload_sizes.1, ptr [[TMP56]], align 8
439 // CHECK1-NEXT: [[TMP57:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
440 // CHECK1-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP57]], align 8
441 // CHECK1-NEXT: [[TMP58:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
442 // CHECK1-NEXT: store ptr null, ptr [[TMP58]], align 8
443 // CHECK1-NEXT: [[TMP59:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
444 // CHECK1-NEXT: store ptr null, ptr [[TMP59]], align 8
445 // CHECK1-NEXT: [[TMP60:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
446 // CHECK1-NEXT: store i64 10, ptr [[TMP60]], align 8
447 // CHECK1-NEXT: [[TMP61:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
448 // CHECK1-NEXT: store i64 0, ptr [[TMP61]], align 8
449 // CHECK1-NEXT: [[TMP62:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
450 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP62]], align 4
451 // CHECK1-NEXT: [[TMP63:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
452 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP63]], align 4
453 // CHECK1-NEXT: [[TMP64:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
454 // CHECK1-NEXT: store i32 0, ptr [[TMP64]], align 4
455 // CHECK1-NEXT: [[TMP65:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113.region_id, ptr [[KERNEL_ARGS]])
456 // CHECK1-NEXT: [[TMP66:%.*]] = icmp ne i32 [[TMP65]], 0
457 // CHECK1-NEXT: br i1 [[TMP66]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
458 // CHECK1: omp_offload.failed:
459 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113(i64 [[TMP46]]) #[[ATTR3]]
460 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
461 // CHECK1: omp_offload.cont:
462 // CHECK1-NEXT: [[TMP67:%.*]] = load i32, ptr [[A]], align 4
463 // CHECK1-NEXT: store i32 [[TMP67]], ptr [[A_CASTED8]], align 4
464 // CHECK1-NEXT: [[TMP68:%.*]] = load i64, ptr [[A_CASTED8]], align 8
465 // CHECK1-NEXT: [[TMP69:%.*]] = load i16, ptr [[AA]], align 2
466 // CHECK1-NEXT: store i16 [[TMP69]], ptr [[AA_CASTED9]], align 2
467 // CHECK1-NEXT: [[TMP70:%.*]] = load i64, ptr [[AA_CASTED9]], align 8
468 // CHECK1-NEXT: [[TMP71:%.*]] = load i32, ptr [[N_ADDR]], align 4
469 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP71]], 10
470 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
471 // CHECK1: omp_if.then:
472 // CHECK1-NEXT: [[TMP72:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
473 // CHECK1-NEXT: store i64 [[TMP68]], ptr [[TMP72]], align 8
474 // CHECK1-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
475 // CHECK1-NEXT: store i64 [[TMP68]], ptr [[TMP73]], align 8
476 // CHECK1-NEXT: [[TMP74:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 0
477 // CHECK1-NEXT: store ptr null, ptr [[TMP74]], align 8
478 // CHECK1-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 1
479 // CHECK1-NEXT: store i64 [[TMP70]], ptr [[TMP75]], align 8
480 // CHECK1-NEXT: [[TMP76:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 1
481 // CHECK1-NEXT: store i64 [[TMP70]], ptr [[TMP76]], align 8
482 // CHECK1-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 1
483 // CHECK1-NEXT: store ptr null, ptr [[TMP77]], align 8
484 // CHECK1-NEXT: [[TMP78:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
485 // CHECK1-NEXT: [[TMP79:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
486 // CHECK1-NEXT: [[TMP80:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 0
487 // CHECK1-NEXT: store i32 2, ptr [[TMP80]], align 4
488 // CHECK1-NEXT: [[TMP81:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 1
489 // CHECK1-NEXT: store i32 2, ptr [[TMP81]], align 4
490 // CHECK1-NEXT: [[TMP82:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 2
491 // CHECK1-NEXT: store ptr [[TMP78]], ptr [[TMP82]], align 8
492 // CHECK1-NEXT: [[TMP83:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 3
493 // CHECK1-NEXT: store ptr [[TMP79]], ptr [[TMP83]], align 8
494 // CHECK1-NEXT: [[TMP84:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 4
495 // CHECK1-NEXT: store ptr @.offload_sizes.3, ptr [[TMP84]], align 8
496 // CHECK1-NEXT: [[TMP85:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 5
497 // CHECK1-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP85]], align 8
498 // CHECK1-NEXT: [[TMP86:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 6
499 // CHECK1-NEXT: store ptr null, ptr [[TMP86]], align 8
500 // CHECK1-NEXT: [[TMP87:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 7
501 // CHECK1-NEXT: store ptr null, ptr [[TMP87]], align 8
502 // CHECK1-NEXT: [[TMP88:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 8
503 // CHECK1-NEXT: store i64 10, ptr [[TMP88]], align 8
504 // CHECK1-NEXT: [[TMP89:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 9
505 // CHECK1-NEXT: store i64 0, ptr [[TMP89]], align 8
506 // CHECK1-NEXT: [[TMP90:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 10
507 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP90]], align 4
508 // CHECK1-NEXT: [[TMP91:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 11
509 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP91]], align 4
510 // CHECK1-NEXT: [[TMP92:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 12
511 // CHECK1-NEXT: store i32 0, ptr [[TMP92]], align 4
512 // CHECK1-NEXT: [[TMP93:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120.region_id, ptr [[KERNEL_ARGS14]])
513 // CHECK1-NEXT: [[TMP94:%.*]] = icmp ne i32 [[TMP93]], 0
514 // CHECK1-NEXT: br i1 [[TMP94]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]]
515 // CHECK1: omp_offload.failed15:
516 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120(i64 [[TMP68]], i64 [[TMP70]]) #[[ATTR3]]
517 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT16]]
518 // CHECK1: omp_offload.cont16:
519 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]]
520 // CHECK1: omp_if.else:
521 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120(i64 [[TMP68]], i64 [[TMP70]]) #[[ATTR3]]
522 // CHECK1-NEXT: br label [[OMP_IF_END]]
523 // CHECK1: omp_if.end:
524 // CHECK1-NEXT: [[TMP95:%.*]] = load i32, ptr [[N_ADDR]], align 4
525 // CHECK1-NEXT: store i32 [[TMP95]], ptr [[DOTCAPTURE_EXPR_17]], align 4
526 // CHECK1-NEXT: [[TMP96:%.*]] = load i32, ptr [[A]], align 4
527 // CHECK1-NEXT: store i32 [[TMP96]], ptr [[A_CASTED18]], align 4
528 // CHECK1-NEXT: [[TMP97:%.*]] = load i64, ptr [[A_CASTED18]], align 8
529 // CHECK1-NEXT: [[TMP98:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
530 // CHECK1-NEXT: store i32 [[TMP98]], ptr [[DOTCAPTURE_EXPR__CASTED19]], align 4
531 // CHECK1-NEXT: [[TMP99:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED19]], align 8
532 // CHECK1-NEXT: [[TMP100:%.*]] = load i32, ptr [[N_ADDR]], align 4
533 // CHECK1-NEXT: [[CMP20:%.*]] = icmp sgt i32 [[TMP100]], 20
534 // CHECK1-NEXT: br i1 [[CMP20]], label [[OMP_IF_THEN21:%.*]], label [[OMP_IF_ELSE29:%.*]]
535 // CHECK1: omp_if.then21:
536 // CHECK1-NEXT: [[TMP101:%.*]] = mul nuw i64 [[TMP2]], 4
537 // CHECK1-NEXT: [[TMP102:%.*]] = mul nuw i64 5, [[TMP5]]
538 // CHECK1-NEXT: [[TMP103:%.*]] = mul nuw i64 [[TMP102]], 8
539 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes.5, i64 80, i1 false)
540 // CHECK1-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 0
541 // CHECK1-NEXT: store i64 [[TMP97]], ptr [[TMP104]], align 8
542 // CHECK1-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS23]], i32 0, i32 0
543 // CHECK1-NEXT: store i64 [[TMP97]], ptr [[TMP105]], align 8
544 // CHECK1-NEXT: [[TMP106:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 0
545 // CHECK1-NEXT: store ptr null, ptr [[TMP106]], align 8
546 // CHECK1-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 1
547 // CHECK1-NEXT: store ptr [[B]], ptr [[TMP107]], align 8
548 // CHECK1-NEXT: [[TMP108:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS23]], i32 0, i32 1
549 // CHECK1-NEXT: store ptr [[B]], ptr [[TMP108]], align 8
550 // CHECK1-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 1
551 // CHECK1-NEXT: store ptr null, ptr [[TMP109]], align 8
552 // CHECK1-NEXT: [[TMP110:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 2
553 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[TMP110]], align 8
554 // CHECK1-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS23]], i32 0, i32 2
555 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[TMP111]], align 8
556 // CHECK1-NEXT: [[TMP112:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 2
557 // CHECK1-NEXT: store ptr null, ptr [[TMP112]], align 8
558 // CHECK1-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 3
559 // CHECK1-NEXT: store ptr [[VLA]], ptr [[TMP113]], align 8
560 // CHECK1-NEXT: [[TMP114:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS23]], i32 0, i32 3
561 // CHECK1-NEXT: store ptr [[VLA]], ptr [[TMP114]], align 8
562 // CHECK1-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 3
563 // CHECK1-NEXT: store i64 [[TMP101]], ptr [[TMP115]], align 8
564 // CHECK1-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 3
565 // CHECK1-NEXT: store ptr null, ptr [[TMP116]], align 8
566 // CHECK1-NEXT: [[TMP117:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 4
567 // CHECK1-NEXT: store ptr [[C]], ptr [[TMP117]], align 8
568 // CHECK1-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS23]], i32 0, i32 4
569 // CHECK1-NEXT: store ptr [[C]], ptr [[TMP118]], align 8
570 // CHECK1-NEXT: [[TMP119:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 4
571 // CHECK1-NEXT: store ptr null, ptr [[TMP119]], align 8
572 // CHECK1-NEXT: [[TMP120:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 5
573 // CHECK1-NEXT: store i64 5, ptr [[TMP120]], align 8
574 // CHECK1-NEXT: [[TMP121:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS23]], i32 0, i32 5
575 // CHECK1-NEXT: store i64 5, ptr [[TMP121]], align 8
576 // CHECK1-NEXT: [[TMP122:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 5
577 // CHECK1-NEXT: store ptr null, ptr [[TMP122]], align 8
578 // CHECK1-NEXT: [[TMP123:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 6
579 // CHECK1-NEXT: store i64 [[TMP5]], ptr [[TMP123]], align 8
580 // CHECK1-NEXT: [[TMP124:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS23]], i32 0, i32 6
581 // CHECK1-NEXT: store i64 [[TMP5]], ptr [[TMP124]], align 8
582 // CHECK1-NEXT: [[TMP125:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 6
583 // CHECK1-NEXT: store ptr null, ptr [[TMP125]], align 8
584 // CHECK1-NEXT: [[TMP126:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 7
585 // CHECK1-NEXT: store ptr [[VLA1]], ptr [[TMP126]], align 8
586 // CHECK1-NEXT: [[TMP127:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS23]], i32 0, i32 7
587 // CHECK1-NEXT: store ptr [[VLA1]], ptr [[TMP127]], align 8
588 // CHECK1-NEXT: [[TMP128:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 7
589 // CHECK1-NEXT: store i64 [[TMP103]], ptr [[TMP128]], align 8
590 // CHECK1-NEXT: [[TMP129:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 7
591 // CHECK1-NEXT: store ptr null, ptr [[TMP129]], align 8
592 // CHECK1-NEXT: [[TMP130:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 8
593 // CHECK1-NEXT: store ptr [[D]], ptr [[TMP130]], align 8
594 // CHECK1-NEXT: [[TMP131:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS23]], i32 0, i32 8
595 // CHECK1-NEXT: store ptr [[D]], ptr [[TMP131]], align 8
596 // CHECK1-NEXT: [[TMP132:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 8
597 // CHECK1-NEXT: store ptr null, ptr [[TMP132]], align 8
598 // CHECK1-NEXT: [[TMP133:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 9
599 // CHECK1-NEXT: store i64 [[TMP99]], ptr [[TMP133]], align 8
600 // CHECK1-NEXT: [[TMP134:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS23]], i32 0, i32 9
601 // CHECK1-NEXT: store i64 [[TMP99]], ptr [[TMP134]], align 8
602 // CHECK1-NEXT: [[TMP135:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS24]], i64 0, i64 9
603 // CHECK1-NEXT: store ptr null, ptr [[TMP135]], align 8
604 // CHECK1-NEXT: [[TMP136:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 0
605 // CHECK1-NEXT: [[TMP137:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS23]], i32 0, i32 0
606 // CHECK1-NEXT: [[TMP138:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0
607 // CHECK1-NEXT: [[TMP139:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 0
608 // CHECK1-NEXT: store i32 2, ptr [[TMP139]], align 4
609 // CHECK1-NEXT: [[TMP140:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 1
610 // CHECK1-NEXT: store i32 10, ptr [[TMP140]], align 4
611 // CHECK1-NEXT: [[TMP141:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 2
612 // CHECK1-NEXT: store ptr [[TMP136]], ptr [[TMP141]], align 8
613 // CHECK1-NEXT: [[TMP142:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 3
614 // CHECK1-NEXT: store ptr [[TMP137]], ptr [[TMP142]], align 8
615 // CHECK1-NEXT: [[TMP143:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 4
616 // CHECK1-NEXT: store ptr [[TMP138]], ptr [[TMP143]], align 8
617 // CHECK1-NEXT: [[TMP144:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 5
618 // CHECK1-NEXT: store ptr @.offload_maptypes.6, ptr [[TMP144]], align 8
619 // CHECK1-NEXT: [[TMP145:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 6
620 // CHECK1-NEXT: store ptr null, ptr [[TMP145]], align 8
621 // CHECK1-NEXT: [[TMP146:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 7
622 // CHECK1-NEXT: store ptr null, ptr [[TMP146]], align 8
623 // CHECK1-NEXT: [[TMP147:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 8
624 // CHECK1-NEXT: store i64 10, ptr [[TMP147]], align 8
625 // CHECK1-NEXT: [[TMP148:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 9
626 // CHECK1-NEXT: store i64 0, ptr [[TMP148]], align 8
627 // CHECK1-NEXT: [[TMP149:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 10
628 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP149]], align 4
629 // CHECK1-NEXT: [[TMP150:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 11
630 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP150]], align 4
631 // CHECK1-NEXT: [[TMP151:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 12
632 // CHECK1-NEXT: store i32 0, ptr [[TMP151]], align 4
633 // CHECK1-NEXT: [[TMP152:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145.region_id, ptr [[KERNEL_ARGS26]])
634 // CHECK1-NEXT: [[TMP153:%.*]] = icmp ne i32 [[TMP152]], 0
635 // CHECK1-NEXT: br i1 [[TMP153]], label [[OMP_OFFLOAD_FAILED27:%.*]], label [[OMP_OFFLOAD_CONT28:%.*]]
636 // CHECK1: omp_offload.failed27:
637 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145(i64 [[TMP97]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]], i64 [[TMP99]]) #[[ATTR3]]
638 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT28]]
639 // CHECK1: omp_offload.cont28:
640 // CHECK1-NEXT: br label [[OMP_IF_END30:%.*]]
641 // CHECK1: omp_if.else29:
642 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145(i64 [[TMP97]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]], i64 [[TMP99]]) #[[ATTR3]]
643 // CHECK1-NEXT: br label [[OMP_IF_END30]]
644 // CHECK1: omp_if.end30:
645 // CHECK1-NEXT: [[TMP154:%.*]] = load i32, ptr [[A]], align 4
646 // CHECK1-NEXT: [[TMP155:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
647 // CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP155]])
648 // CHECK1-NEXT: ret i32 [[TMP154]]
651 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
652 // CHECK1-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] {
653 // CHECK1-NEXT: entry:
654 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
655 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
656 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8
657 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
658 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
659 // CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
660 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
661 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 8
662 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
663 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4
664 // CHECK1-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
665 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
666 // CHECK1-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
667 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8
668 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined, i64 [[TMP4]])
669 // CHECK1-NEXT: ret void
672 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined
673 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {
674 // CHECK1-NEXT: entry:
675 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
676 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
677 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
678 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
679 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
680 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
681 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
682 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
683 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
684 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
685 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
686 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
687 // CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
688 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
689 // CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
690 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
691 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
692 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
693 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
694 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
695 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
696 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
697 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
698 // CHECK1: cond.true:
699 // CHECK1-NEXT: br label [[COND_END:%.*]]
700 // CHECK1: cond.false:
701 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
702 // CHECK1-NEXT: br label [[COND_END]]
703 // CHECK1: cond.end:
704 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
705 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
706 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
707 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
708 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
709 // CHECK1: omp.inner.for.cond:
710 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
711 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
712 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
713 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
714 // CHECK1: omp.inner.for.body:
715 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
716 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
717 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
718 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4
719 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
720 // CHECK1: omp.body.continue:
721 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
722 // CHECK1: omp.inner.for.inc:
723 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
724 // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
725 // CHECK1-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4
726 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
727 // CHECK1: omp.inner.for.end:
728 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
729 // CHECK1: omp.loop.exit:
730 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
731 // CHECK1-NEXT: ret void
734 // CHECK1-LABEL: define {{[^@]+}}@.omp_task_privates_map.
735 // CHECK1-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]], ptr noalias noundef [[TMP3:%.*]], ptr noalias noundef [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] {
736 // CHECK1-NEXT: entry:
737 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8
738 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8
739 // CHECK1-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 8
740 // CHECK1-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8
741 // CHECK1-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8
742 // CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8
743 // CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
744 // CHECK1-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2]], align 8
745 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTADDR3]], align 8
746 // CHECK1-NEXT: store ptr [[TMP4]], ptr [[DOTADDR4]], align 8
747 // CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR]], align 8
748 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP5]], i32 0, i32 0
749 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTADDR2]], align 8
750 // CHECK1-NEXT: store ptr [[TMP6]], ptr [[TMP7]], align 8
751 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 1
752 // CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTADDR3]], align 8
753 // CHECK1-NEXT: store ptr [[TMP8]], ptr [[TMP9]], align 8
754 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 2
755 // CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTADDR4]], align 8
756 // CHECK1-NEXT: store ptr [[TMP10]], ptr [[TMP11]], align 8
757 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 3
758 // CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTADDR1]], align 8
759 // CHECK1-NEXT: store ptr [[TMP12]], ptr [[TMP13]], align 8
760 // CHECK1-NEXT: ret void
763 // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry.
764 // CHECK1-SAME: (i32 noundef signext [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] {
765 // CHECK1-NEXT: entry:
766 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
767 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8
768 // CHECK1-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8
769 // CHECK1-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8
770 // CHECK1-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8
771 // CHECK1-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8
772 // CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca ptr, align 8
773 // CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca ptr, align 8
774 // CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca ptr, align 8
775 // CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca ptr, align 8
776 // CHECK1-NEXT: [[KERNEL_ARGS_I:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
777 // CHECK1-NEXT: [[AA_CASTED_I:%.*]] = alloca i64, align 8
778 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i64, align 8
779 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED4_I:%.*]] = alloca i64, align 8
780 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4
781 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8
782 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4
783 // CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
784 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4
785 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8
786 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0
787 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2
788 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0
789 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8
790 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 1
791 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
792 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])
793 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])
794 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])
795 // CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !21
796 // CHECK1-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias !21
797 // CHECK1-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias !21
798 // CHECK1-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !21
799 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias !21
800 // CHECK1-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias !21
801 // CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias !21
802 // CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !21
803 // CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias !21
804 // CHECK1-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]
805 // CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !21
806 // CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !21
807 // CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !21
808 // CHECK1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !21
809 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP9]], i32 0, i32 1
810 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP9]], i32 0, i32 2
811 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP16]], align 4
812 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP17]], align 4
813 // CHECK1-NEXT: [[TMP20:%.*]] = insertvalue [3 x i32] zeroinitializer, i32 [[TMP18]], 0
814 // CHECK1-NEXT: [[TMP21:%.*]] = insertvalue [3 x i32] zeroinitializer, i32 [[TMP19]], 0
815 // CHECK1-NEXT: store i32 2, ptr [[KERNEL_ARGS_I]], align 4, !noalias !21
816 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 1
817 // CHECK1-NEXT: store i32 3, ptr [[TMP22]], align 4, !noalias !21
818 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 2
819 // CHECK1-NEXT: store ptr [[TMP13]], ptr [[TMP23]], align 8, !noalias !21
820 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 3
821 // CHECK1-NEXT: store ptr [[TMP14]], ptr [[TMP24]], align 8, !noalias !21
822 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 4
823 // CHECK1-NEXT: store ptr [[TMP15]], ptr [[TMP25]], align 8, !noalias !21
824 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 5
825 // CHECK1-NEXT: store ptr @.offload_maptypes, ptr [[TMP26]], align 8, !noalias !21
826 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 6
827 // CHECK1-NEXT: store ptr null, ptr [[TMP27]], align 8, !noalias !21
828 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 7
829 // CHECK1-NEXT: store ptr null, ptr [[TMP28]], align 8, !noalias !21
830 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 8
831 // CHECK1-NEXT: store i64 10, ptr [[TMP29]], align 8, !noalias !21
832 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 9
833 // CHECK1-NEXT: store i64 1, ptr [[TMP30]], align 8, !noalias !21
834 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 10
835 // CHECK1-NEXT: store [3 x i32] [[TMP20]], ptr [[TMP31]], align 4, !noalias !21
836 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 11
837 // CHECK1-NEXT: store [3 x i32] [[TMP21]], ptr [[TMP32]], align 4, !noalias !21
838 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 12
839 // CHECK1-NEXT: store i32 0, ptr [[TMP33]], align 4, !noalias !21
840 // CHECK1-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 [[TMP18]], i32 [[TMP19]], ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, ptr [[KERNEL_ARGS_I]])
841 // CHECK1-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0
842 // CHECK1-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]]
843 // CHECK1: omp_offload.failed.i:
844 // CHECK1-NEXT: [[TMP36:%.*]] = load i16, ptr [[TMP12]], align 2
845 // CHECK1-NEXT: store i16 [[TMP36]], ptr [[AA_CASTED_I]], align 2, !noalias !21
846 // CHECK1-NEXT: [[TMP37:%.*]] = load i64, ptr [[AA_CASTED_I]], align 8, !noalias !21
847 // CHECK1-NEXT: [[TMP38:%.*]] = load i32, ptr [[TMP16]], align 4
848 // CHECK1-NEXT: store i32 [[TMP38]], ptr [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !21
849 // CHECK1-NEXT: [[TMP39:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED_I]], align 8, !noalias !21
850 // CHECK1-NEXT: [[TMP40:%.*]] = load i32, ptr [[TMP17]], align 4
851 // CHECK1-NEXT: store i32 [[TMP40]], ptr [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !21
852 // CHECK1-NEXT: [[TMP41:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED4_I]], align 8, !noalias !21
853 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103(i64 [[TMP37]], i64 [[TMP39]], i64 [[TMP41]]) #[[ATTR3]]
854 // CHECK1-NEXT: br label [[DOTOMP_OUTLINED__EXIT]]
855 // CHECK1: .omp_outlined..exit:
856 // CHECK1-NEXT: ret i32 0
859 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107
860 // CHECK1-SAME: (i64 noundef [[A:%.*]]) #[[ATTR2]] {
861 // CHECK1-NEXT: entry:
862 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
863 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
864 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
865 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
866 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4
867 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8
868 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107.omp_outlined, i64 [[TMP1]])
869 // CHECK1-NEXT: ret void
872 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107.omp_outlined
873 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] {
874 // CHECK1-NEXT: entry:
875 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
876 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
877 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
878 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
879 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
880 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
881 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
882 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
883 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
884 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
885 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
886 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
887 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
888 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
889 // CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
890 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
891 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
892 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
893 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
894 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
895 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
896 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
897 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
898 // CHECK1: cond.true:
899 // CHECK1-NEXT: br label [[COND_END:%.*]]
900 // CHECK1: cond.false:
901 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
902 // CHECK1-NEXT: br label [[COND_END]]
903 // CHECK1: cond.end:
904 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
905 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
906 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
907 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
908 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
909 // CHECK1: omp.inner.for.cond:
910 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
911 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
912 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
913 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
914 // CHECK1: omp.inner.for.body:
915 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
916 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
917 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
918 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4
919 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
920 // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
921 // CHECK1-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4
922 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
923 // CHECK1: omp.body.continue:
924 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
925 // CHECK1: omp.inner.for.inc:
926 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
927 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
928 // CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4
929 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
930 // CHECK1: omp.inner.for.end:
931 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
932 // CHECK1: omp.loop.exit:
933 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
934 // CHECK1-NEXT: ret void
937 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113
938 // CHECK1-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR2]] {
939 // CHECK1-NEXT: entry:
940 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
941 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
942 // CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
943 // CHECK1-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2
944 // CHECK1-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2
945 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[AA_CASTED]], align 8
946 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113.omp_outlined, i64 [[TMP1]])
947 // CHECK1-NEXT: ret void
950 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113.omp_outlined
951 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {
952 // CHECK1-NEXT: entry:
953 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
954 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
955 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
956 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
957 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
958 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
959 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
960 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
961 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
962 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
963 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
964 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
965 // CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
966 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
967 // CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
968 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
969 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
970 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
971 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
972 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
973 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
974 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
975 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
976 // CHECK1: cond.true:
977 // CHECK1-NEXT: br label [[COND_END:%.*]]
978 // CHECK1: cond.false:
979 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
980 // CHECK1-NEXT: br label [[COND_END]]
981 // CHECK1: cond.end:
982 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
983 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
984 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
985 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
986 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
987 // CHECK1: omp.inner.for.cond:
988 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
989 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
990 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
991 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
992 // CHECK1: omp.inner.for.body:
993 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
994 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
995 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
996 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4
997 // CHECK1-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA_ADDR]], align 2
998 // CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP8]] to i32
999 // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
1000 // CHECK1-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
1001 // CHECK1-NEXT: store i16 [[CONV3]], ptr [[AA_ADDR]], align 2
1002 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1003 // CHECK1: omp.body.continue:
1004 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1005 // CHECK1: omp.inner.for.inc:
1006 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1007 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], 1
1008 // CHECK1-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4
1009 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
1010 // CHECK1: omp.inner.for.end:
1011 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1012 // CHECK1: omp.loop.exit:
1013 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
1014 // CHECK1-NEXT: ret void
1017 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120
1018 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {
1019 // CHECK1-NEXT: entry:
1020 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
1021 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
1022 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
1023 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
1024 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
1025 // CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
1026 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
1027 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4
1028 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8
1029 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2
1030 // CHECK1-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
1031 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8
1032 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120.omp_outlined, i64 [[TMP1]], i64 [[TMP3]])
1033 // CHECK1-NEXT: ret void
1036 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120.omp_outlined
1037 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {
1038 // CHECK1-NEXT: entry:
1039 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1040 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1041 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
1042 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
1043 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1044 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
1045 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1046 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1047 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1048 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1049 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
1050 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1051 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1052 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
1053 // CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
1054 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
1055 // CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
1056 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1057 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1058 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1059 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
1060 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
1061 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1062 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
1063 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1064 // CHECK1: cond.true:
1065 // CHECK1-NEXT: br label [[COND_END:%.*]]
1066 // CHECK1: cond.false:
1067 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1068 // CHECK1-NEXT: br label [[COND_END]]
1069 // CHECK1: cond.end:
1070 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
1071 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
1072 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1073 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
1074 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1075 // CHECK1: omp.inner.for.cond:
1076 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1077 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1078 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
1079 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1080 // CHECK1: omp.inner.for.body:
1081 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1082 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
1083 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1084 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4
1085 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
1086 // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
1087 // CHECK1-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4
1088 // CHECK1-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2
1089 // CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP9]] to i32
1090 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1
1091 // CHECK1-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
1092 // CHECK1-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2
1093 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1094 // CHECK1: omp.body.continue:
1095 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1096 // CHECK1: omp.inner.for.inc:
1097 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1098 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP10]], 1
1099 // CHECK1-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4
1100 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
1101 // CHECK1: omp.inner.for.end:
1102 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1103 // CHECK1: omp.loop.exit:
1104 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
1105 // CHECK1-NEXT: ret void
1108 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145
1109 // CHECK1-SAME: (i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
1110 // CHECK1-NEXT: entry:
1111 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
1112 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
1113 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
1114 // CHECK1-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 8
1115 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8
1116 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
1117 // CHECK1-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
1118 // CHECK1-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 8
1119 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8
1120 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
1121 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
1122 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
1123 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
1124 // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
1125 // CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
1126 // CHECK1-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 8
1127 // CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
1128 // CHECK1-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
1129 // CHECK1-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8
1130 // CHECK1-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8
1131 // CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
1132 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
1133 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
1134 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
1135 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8
1136 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
1137 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
1138 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8
1139 // CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8
1140 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8
1141 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
1142 // CHECK1-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4
1143 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 8
1144 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
1145 // CHECK1-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
1146 // CHECK1-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8
1147 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145.omp_outlined, i64 [[TMP9]], ptr [[TMP0]], i64 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i64 [[TMP11]])
1148 // CHECK1-NEXT: ret void
1151 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145.omp_outlined
1152 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
1153 // CHECK1-NEXT: entry:
1154 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1155 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1156 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
1157 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
1158 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
1159 // CHECK1-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 8
1160 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8
1161 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
1162 // CHECK1-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
1163 // CHECK1-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 8
1164 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8
1165 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
1166 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1167 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
1168 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1169 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1170 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1171 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1172 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
1173 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1174 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1175 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
1176 // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
1177 // CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
1178 // CHECK1-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 8
1179 // CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
1180 // CHECK1-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
1181 // CHECK1-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8
1182 // CHECK1-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8
1183 // CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
1184 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
1185 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
1186 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
1187 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8
1188 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
1189 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
1190 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8
1191 // CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8
1192 // CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8
1193 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
1194 // CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
1195 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1196 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1197 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
1198 // CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1199 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4
1200 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP10]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
1201 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
1202 // CHECK1: omp.dispatch.cond:
1203 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1204 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9
1205 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1206 // CHECK1: cond.true:
1207 // CHECK1-NEXT: br label [[COND_END:%.*]]
1208 // CHECK1: cond.false:
1209 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1210 // CHECK1-NEXT: br label [[COND_END]]
1211 // CHECK1: cond.end:
1212 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
1213 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
1214 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1215 // CHECK1-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4
1216 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1217 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1218 // CHECK1-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
1219 // CHECK1-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
1220 // CHECK1: omp.dispatch.body:
1221 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1222 // CHECK1: omp.inner.for.cond:
1223 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22:![0-9]+]]
1224 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP22]]
1225 // CHECK1-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
1226 // CHECK1-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1227 // CHECK1: omp.inner.for.body:
1228 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]]
1229 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
1230 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1231 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]]
1232 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP22]]
1233 // CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1
1234 // CHECK1-NEXT: store i32 [[ADD7]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP22]]
1235 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 2
1236 // CHECK1-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP22]]
1237 // CHECK1-NEXT: [[CONV:%.*]] = fpext float [[TMP20]] to double
1238 // CHECK1-NEXT: [[ADD8:%.*]] = fadd double [[CONV]], 1.000000e+00
1239 // CHECK1-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
1240 // CHECK1-NEXT: store float [[CONV9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP22]]
1241 // CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 3
1242 // CHECK1-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP22]]
1243 // CHECK1-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double
1244 // CHECK1-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
1245 // CHECK1-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
1246 // CHECK1-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP22]]
1247 // CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 1
1248 // CHECK1-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i64 0, i64 2
1249 // CHECK1-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP22]]
1250 // CHECK1-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
1251 // CHECK1-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP22]]
1252 // CHECK1-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]
1253 // CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i64 [[TMP23]]
1254 // CHECK1-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX17]], i64 3
1255 // CHECK1-NEXT: [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP22]]
1256 // CHECK1-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
1257 // CHECK1-NEXT: store double [[ADD19]], ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP22]]
1258 // CHECK1-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0
1259 // CHECK1-NEXT: [[TMP25:%.*]] = load i64, ptr [[X]], align 8, !llvm.access.group [[ACC_GRP22]]
1260 // CHECK1-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
1261 // CHECK1-NEXT: store i64 [[ADD20]], ptr [[X]], align 8, !llvm.access.group [[ACC_GRP22]]
1262 // CHECK1-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1
1263 // CHECK1-NEXT: [[TMP26:%.*]] = load i8, ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP22]]
1264 // CHECK1-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
1265 // CHECK1-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
1266 // CHECK1-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
1267 // CHECK1-NEXT: store i8 [[CONV23]], ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP22]]
1268 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1269 // CHECK1: omp.body.continue:
1270 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1271 // CHECK1: omp.inner.for.inc:
1272 // CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]]
1273 // CHECK1-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
1274 // CHECK1-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]]
1275 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
1276 // CHECK1: omp.inner.for.end:
1277 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
1278 // CHECK1: omp.dispatch.inc:
1279 // CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1280 // CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
1281 // CHECK1-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
1282 // CHECK1-NEXT: store i32 [[ADD25]], ptr [[DOTOMP_LB]], align 4
1283 // CHECK1-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1284 // CHECK1-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
1285 // CHECK1-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
1286 // CHECK1-NEXT: store i32 [[ADD26]], ptr [[DOTOMP_UB]], align 4
1287 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]]
1288 // CHECK1: omp.dispatch.end:
1289 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP10]])
1290 // CHECK1-NEXT: ret void
1293 // CHECK1-LABEL: define {{[^@]+}}@_Z3bari
1294 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
1295 // CHECK1-NEXT: entry:
1296 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
1297 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4
1298 // CHECK1-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
1299 // CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
1300 // CHECK1-NEXT: store i32 0, ptr [[A]], align 4
1301 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
1302 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]])
1303 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 4
1304 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
1305 // CHECK1-NEXT: store i32 [[ADD]], ptr [[A]], align 4
1306 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
1307 // CHECK1-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(ptr noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]])
1308 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 4
1309 // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
1310 // CHECK1-NEXT: store i32 [[ADD2]], ptr [[A]], align 4
1311 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
1312 // CHECK1-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]])
1313 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4
1314 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
1315 // CHECK1-NEXT: store i32 [[ADD4]], ptr [[A]], align 4
1316 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4
1317 // CHECK1-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]])
1318 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4
1319 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
1320 // CHECK1-NEXT: store i32 [[ADD6]], ptr [[A]], align 4
1321 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4
1322 // CHECK1-NEXT: ret i32 [[TMP8]]
1325 // CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
1326 // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
1327 // CHECK1-NEXT: entry:
1328 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
1329 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
1330 // CHECK1-NEXT: [[B:%.*]] = alloca i32, align 4
1331 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8
1332 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
1333 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
1334 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 8
1335 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 8
1336 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 8
1337 // CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8
1338 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
1339 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1340 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1341 // CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
1342 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1343 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
1344 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
1345 // CHECK1-NEXT: store i32 [[ADD]], ptr [[B]], align 4
1346 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
1347 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
1348 // CHECK1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()
1349 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8
1350 // CHECK1-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
1351 // CHECK1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
1352 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8
1353 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[B]], align 4
1354 // CHECK1-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 4
1355 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 8
1356 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 4
1357 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60
1358 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
1359 // CHECK1: omp_if.then:
1360 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0
1361 // CHECK1-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]]
1362 // CHECK1-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2
1363 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes.7, i64 40, i1 false)
1364 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1365 // CHECK1-NEXT: store ptr [[THIS1]], ptr [[TMP10]], align 8
1366 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1367 // CHECK1-NEXT: store ptr [[A]], ptr [[TMP11]], align 8
1368 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
1369 // CHECK1-NEXT: store ptr null, ptr [[TMP12]], align 8
1370 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1371 // CHECK1-NEXT: store i64 [[TMP6]], ptr [[TMP13]], align 8
1372 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1373 // CHECK1-NEXT: store i64 [[TMP6]], ptr [[TMP14]], align 8
1374 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
1375 // CHECK1-NEXT: store ptr null, ptr [[TMP15]], align 8
1376 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1377 // CHECK1-NEXT: store i64 2, ptr [[TMP16]], align 8
1378 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1379 // CHECK1-NEXT: store i64 2, ptr [[TMP17]], align 8
1380 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
1381 // CHECK1-NEXT: store ptr null, ptr [[TMP18]], align 8
1382 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1383 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[TMP19]], align 8
1384 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1385 // CHECK1-NEXT: store i64 [[TMP2]], ptr [[TMP20]], align 8
1386 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
1387 // CHECK1-NEXT: store ptr null, ptr [[TMP21]], align 8
1388 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
1389 // CHECK1-NEXT: store ptr [[VLA]], ptr [[TMP22]], align 8
1390 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4
1391 // CHECK1-NEXT: store ptr [[VLA]], ptr [[TMP23]], align 8
1392 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 4
1393 // CHECK1-NEXT: store i64 [[TMP9]], ptr [[TMP24]], align 8
1394 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
1395 // CHECK1-NEXT: store ptr null, ptr [[TMP25]], align 8
1396 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1397 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1398 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0
1399 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
1400 // CHECK1-NEXT: store i32 2, ptr [[TMP29]], align 4
1401 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
1402 // CHECK1-NEXT: store i32 5, ptr [[TMP30]], align 4
1403 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
1404 // CHECK1-NEXT: store ptr [[TMP26]], ptr [[TMP31]], align 8
1405 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
1406 // CHECK1-NEXT: store ptr [[TMP27]], ptr [[TMP32]], align 8
1407 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
1408 // CHECK1-NEXT: store ptr [[TMP28]], ptr [[TMP33]], align 8
1409 // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
1410 // CHECK1-NEXT: store ptr @.offload_maptypes.8, ptr [[TMP34]], align 8
1411 // CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
1412 // CHECK1-NEXT: store ptr null, ptr [[TMP35]], align 8
1413 // CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
1414 // CHECK1-NEXT: store ptr null, ptr [[TMP36]], align 8
1415 // CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
1416 // CHECK1-NEXT: store i64 10, ptr [[TMP37]], align 8
1417 // CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
1418 // CHECK1-NEXT: store i64 0, ptr [[TMP38]], align 8
1419 // CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
1420 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP39]], align 4
1421 // CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
1422 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP40]], align 4
1423 // CHECK1-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
1424 // CHECK1-NEXT: store i32 0, ptr [[TMP41]], align 4
1425 // CHECK1-NEXT: [[TMP42:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218.region_id, ptr [[KERNEL_ARGS]])
1426 // CHECK1-NEXT: [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0
1427 // CHECK1-NEXT: br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1428 // CHECK1: omp_offload.failed:
1429 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218(ptr [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], ptr [[VLA]]) #[[ATTR3]]
1430 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
1431 // CHECK1: omp_offload.cont:
1432 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]]
1433 // CHECK1: omp_if.else:
1434 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218(ptr [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], ptr [[VLA]]) #[[ATTR3]]
1435 // CHECK1-NEXT: br label [[OMP_IF_END]]
1436 // CHECK1: omp_if.end:
1437 // CHECK1-NEXT: [[TMP44:%.*]] = mul nsw i64 1, [[TMP2]]
1438 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP44]]
1439 // CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1
1440 // CHECK1-NEXT: [[TMP45:%.*]] = load i16, ptr [[ARRAYIDX2]], align 2
1441 // CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP45]] to i32
1442 // CHECK1-NEXT: [[TMP46:%.*]] = load i32, ptr [[B]], align 4
1443 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP46]]
1444 // CHECK1-NEXT: [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
1445 // CHECK1-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP47]])
1446 // CHECK1-NEXT: ret i32 [[ADD3]]
1449 // CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici
1450 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
1451 // CHECK1-NEXT: entry:
1452 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
1453 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4
1454 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2
1455 // CHECK1-NEXT: [[AAA:%.*]] = alloca i8, align 1
1456 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
1457 // CHECK1-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
1458 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
1459 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
1460 // CHECK1-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8
1461 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 8
1462 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 8
1463 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 8
1464 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
1465 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
1466 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
1467 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
1468 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1469 // CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
1470 // CHECK1-NEXT: store i32 0, ptr [[A]], align 4
1471 // CHECK1-NEXT: store i16 0, ptr [[AA]], align 2
1472 // CHECK1-NEXT: store i8 0, ptr [[AAA]], align 1
1473 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
1474 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[N_CASTED]], align 4
1475 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[N_CASTED]], align 8
1476 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4
1477 // CHECK1-NEXT: store i32 [[TMP2]], ptr [[A_CASTED]], align 4
1478 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[A_CASTED]], align 8
1479 // CHECK1-NEXT: [[TMP4:%.*]] = load i16, ptr [[AA]], align 2
1480 // CHECK1-NEXT: store i16 [[TMP4]], ptr [[AA_CASTED]], align 2
1481 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[AA_CASTED]], align 8
1482 // CHECK1-NEXT: [[TMP6:%.*]] = load i8, ptr [[AAA]], align 1
1483 // CHECK1-NEXT: store i8 [[TMP6]], ptr [[AAA_CASTED]], align 1
1484 // CHECK1-NEXT: [[TMP7:%.*]] = load i64, ptr [[AAA_CASTED]], align 8
1485 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[N_ADDR]], align 4
1486 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 50
1487 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
1488 // CHECK1: omp_if.then:
1489 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1490 // CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP9]], align 8
1491 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1492 // CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP10]], align 8
1493 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
1494 // CHECK1-NEXT: store ptr null, ptr [[TMP11]], align 8
1495 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1496 // CHECK1-NEXT: store i64 [[TMP3]], ptr [[TMP12]], align 8
1497 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1498 // CHECK1-NEXT: store i64 [[TMP3]], ptr [[TMP13]], align 8
1499 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
1500 // CHECK1-NEXT: store ptr null, ptr [[TMP14]], align 8
1501 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1502 // CHECK1-NEXT: store i64 [[TMP5]], ptr [[TMP15]], align 8
1503 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1504 // CHECK1-NEXT: store i64 [[TMP5]], ptr [[TMP16]], align 8
1505 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
1506 // CHECK1-NEXT: store ptr null, ptr [[TMP17]], align 8
1507 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1508 // CHECK1-NEXT: store i64 [[TMP7]], ptr [[TMP18]], align 8
1509 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1510 // CHECK1-NEXT: store i64 [[TMP7]], ptr [[TMP19]], align 8
1511 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
1512 // CHECK1-NEXT: store ptr null, ptr [[TMP20]], align 8
1513 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
1514 // CHECK1-NEXT: store ptr [[B]], ptr [[TMP21]], align 8
1515 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4
1516 // CHECK1-NEXT: store ptr [[B]], ptr [[TMP22]], align 8
1517 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
1518 // CHECK1-NEXT: store ptr null, ptr [[TMP23]], align 8
1519 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1520 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1521 // CHECK1-NEXT: [[TMP26:%.*]] = load i32, ptr [[A]], align 4
1522 // CHECK1-NEXT: store i32 [[TMP26]], ptr [[DOTCAPTURE_EXPR_]], align 4
1523 // CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[N_ADDR]], align 4
1524 // CHECK1-NEXT: store i32 [[TMP27]], ptr [[DOTCAPTURE_EXPR_1]], align 4
1525 // CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
1526 // CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1527 // CHECK1-NEXT: [[SUB:%.*]] = sub i32 [[TMP28]], [[TMP29]]
1528 // CHECK1-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1
1529 // CHECK1-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 1
1530 // CHECK1-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
1531 // CHECK1-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 1
1532 // CHECK1-NEXT: store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 4
1533 // CHECK1-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
1534 // CHECK1-NEXT: [[ADD5:%.*]] = add i32 [[TMP30]], 1
1535 // CHECK1-NEXT: [[TMP31:%.*]] = zext i32 [[ADD5]] to i64
1536 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
1537 // CHECK1-NEXT: store i32 2, ptr [[TMP32]], align 4
1538 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
1539 // CHECK1-NEXT: store i32 5, ptr [[TMP33]], align 4
1540 // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
1541 // CHECK1-NEXT: store ptr [[TMP24]], ptr [[TMP34]], align 8
1542 // CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
1543 // CHECK1-NEXT: store ptr [[TMP25]], ptr [[TMP35]], align 8
1544 // CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
1545 // CHECK1-NEXT: store ptr @.offload_sizes.9, ptr [[TMP36]], align 8
1546 // CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
1547 // CHECK1-NEXT: store ptr @.offload_maptypes.10, ptr [[TMP37]], align 8
1548 // CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
1549 // CHECK1-NEXT: store ptr null, ptr [[TMP38]], align 8
1550 // CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
1551 // CHECK1-NEXT: store ptr null, ptr [[TMP39]], align 8
1552 // CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
1553 // CHECK1-NEXT: store i64 [[TMP31]], ptr [[TMP40]], align 8
1554 // CHECK1-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
1555 // CHECK1-NEXT: store i64 0, ptr [[TMP41]], align 8
1556 // CHECK1-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
1557 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP42]], align 4
1558 // CHECK1-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
1559 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP43]], align 4
1560 // CHECK1-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
1561 // CHECK1-NEXT: store i32 0, ptr [[TMP44]], align 4
1562 // CHECK1-NEXT: [[TMP45:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200.region_id, ptr [[KERNEL_ARGS]])
1563 // CHECK1-NEXT: [[TMP46:%.*]] = icmp ne i32 [[TMP45]], 0
1564 // CHECK1-NEXT: br i1 [[TMP46]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1565 // CHECK1: omp_offload.failed:
1566 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], i64 [[TMP7]], ptr [[B]]) #[[ATTR3]]
1567 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
1568 // CHECK1: omp_offload.cont:
1569 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]]
1570 // CHECK1: omp_if.else:
1571 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], i64 [[TMP7]], ptr [[B]]) #[[ATTR3]]
1572 // CHECK1-NEXT: br label [[OMP_IF_END]]
1573 // CHECK1: omp_if.end:
1574 // CHECK1-NEXT: [[TMP47:%.*]] = load i32, ptr [[A]], align 4
1575 // CHECK1-NEXT: ret i32 [[TMP47]]
1578 // CHECK1-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
1579 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
1580 // CHECK1-NEXT: entry:
1581 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
1582 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4
1583 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2
1584 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
1585 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
1586 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
1587 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8
1588 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 8
1589 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 8
1590 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
1591 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1592 // CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
1593 // CHECK1-NEXT: store i32 0, ptr [[A]], align 4
1594 // CHECK1-NEXT: store i16 0, ptr [[AA]], align 2
1595 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4
1596 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4
1597 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8
1598 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA]], align 2
1599 // CHECK1-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
1600 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8
1601 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
1602 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
1603 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
1604 // CHECK1: omp_if.then:
1605 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1606 // CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP5]], align 8
1607 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1608 // CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP6]], align 8
1609 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
1610 // CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 8
1611 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1612 // CHECK1-NEXT: store i64 [[TMP3]], ptr [[TMP8]], align 8
1613 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1614 // CHECK1-NEXT: store i64 [[TMP3]], ptr [[TMP9]], align 8
1615 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
1616 // CHECK1-NEXT: store ptr null, ptr [[TMP10]], align 8
1617 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1618 // CHECK1-NEXT: store ptr [[B]], ptr [[TMP11]], align 8
1619 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1620 // CHECK1-NEXT: store ptr [[B]], ptr [[TMP12]], align 8
1621 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
1622 // CHECK1-NEXT: store ptr null, ptr [[TMP13]], align 8
1623 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1624 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1625 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
1626 // CHECK1-NEXT: store i32 2, ptr [[TMP16]], align 4
1627 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
1628 // CHECK1-NEXT: store i32 3, ptr [[TMP17]], align 4
1629 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
1630 // CHECK1-NEXT: store ptr [[TMP14]], ptr [[TMP18]], align 8
1631 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
1632 // CHECK1-NEXT: store ptr [[TMP15]], ptr [[TMP19]], align 8
1633 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
1634 // CHECK1-NEXT: store ptr @.offload_sizes.11, ptr [[TMP20]], align 8
1635 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
1636 // CHECK1-NEXT: store ptr @.offload_maptypes.12, ptr [[TMP21]], align 8
1637 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
1638 // CHECK1-NEXT: store ptr null, ptr [[TMP22]], align 8
1639 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
1640 // CHECK1-NEXT: store ptr null, ptr [[TMP23]], align 8
1641 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
1642 // CHECK1-NEXT: store i64 10, ptr [[TMP24]], align 8
1643 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
1644 // CHECK1-NEXT: store i64 0, ptr [[TMP25]], align 8
1645 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
1646 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP26]], align 4
1647 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
1648 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP27]], align 4
1649 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
1650 // CHECK1-NEXT: store i32 0, ptr [[TMP28]], align 4
1651 // CHECK1-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183.region_id, ptr [[KERNEL_ARGS]])
1652 // CHECK1-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
1653 // CHECK1-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1654 // CHECK1: omp_offload.failed:
1655 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR3]]
1656 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
1657 // CHECK1: omp_offload.cont:
1658 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]]
1659 // CHECK1: omp_if.else:
1660 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR3]]
1661 // CHECK1-NEXT: br label [[OMP_IF_END]]
1662 // CHECK1: omp_if.end:
1663 // CHECK1-NEXT: [[TMP31:%.*]] = load i32, ptr [[A]], align 4
1664 // CHECK1-NEXT: ret i32 [[TMP31]]
1667 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218
1668 // CHECK1-SAME: (ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
1669 // CHECK1-NEXT: entry:
1670 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
1671 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
1672 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
1673 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
1674 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8
1675 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
1676 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1677 // CHECK1-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8
1678 // CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
1679 // CHECK1-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
1680 // CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
1681 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1682 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
1683 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
1684 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
1685 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4
1686 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4
1687 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[B_CASTED]], align 8
1688 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218.omp_outlined, ptr [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], ptr [[TMP3]])
1689 // CHECK1-NEXT: ret void
1692 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218.omp_outlined
1693 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
1694 // CHECK1-NEXT: entry:
1695 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1696 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1697 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
1698 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
1699 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
1700 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
1701 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8
1702 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1703 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
1704 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1705 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1706 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1707 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1708 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
1709 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1710 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1711 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1712 // CHECK1-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8
1713 // CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
1714 // CHECK1-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
1715 // CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
1716 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1717 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
1718 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
1719 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
1720 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
1721 // CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
1722 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1723 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1724 // CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1725 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
1726 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
1727 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1728 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9
1729 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1730 // CHECK1: cond.true:
1731 // CHECK1-NEXT: br label [[COND_END:%.*]]
1732 // CHECK1: cond.false:
1733 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1734 // CHECK1-NEXT: br label [[COND_END]]
1735 // CHECK1: cond.end:
1736 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
1737 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
1738 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1739 // CHECK1-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4
1740 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1741 // CHECK1: omp.inner.for.cond:
1742 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1743 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1744 // CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
1745 // CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1746 // CHECK1: omp.inner.for.body:
1747 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1748 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
1749 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1750 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4
1751 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[B_ADDR]], align 4
1752 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double
1753 // CHECK1-NEXT: [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00
1754 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0
1755 // CHECK1-NEXT: store double [[ADD4]], ptr [[A]], align 8
1756 // CHECK1-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0
1757 // CHECK1-NEXT: [[TMP13:%.*]] = load double, ptr [[A5]], align 8
1758 // CHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
1759 // CHECK1-NEXT: store double [[INC]], ptr [[A5]], align 8
1760 // CHECK1-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16
1761 // CHECK1-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]]
1762 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i64 [[TMP14]]
1763 // CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1
1764 // CHECK1-NEXT: store i16 [[CONV6]], ptr [[ARRAYIDX7]], align 2
1765 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1766 // CHECK1: omp.body.continue:
1767 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1768 // CHECK1: omp.inner.for.inc:
1769 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1770 // CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1
1771 // CHECK1-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4
1772 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
1773 // CHECK1: omp.inner.for.end:
1774 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1775 // CHECK1: omp.loop.exit:
1776 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])
1777 // CHECK1-NEXT: ret void
1780 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200
1781 // CHECK1-SAME: (i64 noundef [[N:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
1782 // CHECK1-NEXT: entry:
1783 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
1784 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
1785 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
1786 // CHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
1787 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
1788 // CHECK1-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
1789 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
1790 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
1791 // CHECK1-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8
1792 // CHECK1-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
1793 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
1794 // CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
1795 // CHECK1-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8
1796 // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
1797 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
1798 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
1799 // CHECK1-NEXT: store i32 [[TMP1]], ptr [[N_CASTED]], align 4
1800 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[N_CASTED]], align 8
1801 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[A_ADDR]], align 4
1802 // CHECK1-NEXT: store i32 [[TMP3]], ptr [[A_CASTED]], align 4
1803 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[A_CASTED]], align 8
1804 // CHECK1-NEXT: [[TMP5:%.*]] = load i16, ptr [[AA_ADDR]], align 2
1805 // CHECK1-NEXT: store i16 [[TMP5]], ptr [[AA_CASTED]], align 2
1806 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[AA_CASTED]], align 8
1807 // CHECK1-NEXT: [[TMP7:%.*]] = load i8, ptr [[AAA_ADDR]], align 1
1808 // CHECK1-NEXT: store i8 [[TMP7]], ptr [[AAA_CASTED]], align 1
1809 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, ptr [[AAA_CASTED]], align 8
1810 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], ptr [[TMP0]])
1811 // CHECK1-NEXT: ret void
1814 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200.omp_outlined
1815 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
1816 // CHECK1-NEXT: entry:
1817 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1818 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1819 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
1820 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
1821 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
1822 // CHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
1823 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
1824 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1825 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
1826 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
1827 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
1828 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
1829 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
1830 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1831 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1832 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1833 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1834 // CHECK1-NEXT: [[I5:%.*]] = alloca i32, align 4
1835 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1836 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1837 // CHECK1-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
1838 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
1839 // CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
1840 // CHECK1-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8
1841 // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
1842 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
1843 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
1844 // CHECK1-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
1845 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
1846 // CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
1847 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
1848 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1849 // CHECK1-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
1850 // CHECK1-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1
1851 // CHECK1-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 1
1852 // CHECK1-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
1853 // CHECK1-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 1
1854 // CHECK1-NEXT: store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 4
1855 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1856 // CHECK1-NEXT: store i32 [[TMP5]], ptr [[I]], align 4
1857 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1858 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
1859 // CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
1860 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
1861 // CHECK1: omp.precond.then:
1862 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
1863 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
1864 // CHECK1-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_UB]], align 4
1865 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1866 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1867 // CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1868 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4
1869 // CHECK1-NEXT: call void @__kmpc_for_static_init_4u(ptr @[[GLOB1]], i32 [[TMP10]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
1870 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1871 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
1872 // CHECK1-NEXT: [[CMP6:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]]
1873 // CHECK1-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1874 // CHECK1: cond.true:
1875 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
1876 // CHECK1-NEXT: br label [[COND_END:%.*]]
1877 // CHECK1: cond.false:
1878 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1879 // CHECK1-NEXT: br label [[COND_END]]
1880 // CHECK1: cond.end:
1881 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ]
1882 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
1883 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1884 // CHECK1-NEXT: store i32 [[TMP15]], ptr [[DOTOMP_IV]], align 4
1885 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1886 // CHECK1: omp.inner.for.cond:
1887 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1888 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1889 // CHECK1-NEXT: [[ADD7:%.*]] = add i32 [[TMP17]], 1
1890 // CHECK1-NEXT: [[CMP8:%.*]] = icmp ult i32 [[TMP16]], [[ADD7]]
1891 // CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1892 // CHECK1: omp.inner.for.body:
1893 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1894 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1895 // CHECK1-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1
1896 // CHECK1-NEXT: [[ADD9:%.*]] = add i32 [[TMP18]], [[MUL]]
1897 // CHECK1-NEXT: store i32 [[ADD9]], ptr [[I5]], align 4
1898 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[A_ADDR]], align 4
1899 // CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP20]], 1
1900 // CHECK1-NEXT: store i32 [[ADD10]], ptr [[A_ADDR]], align 4
1901 // CHECK1-NEXT: [[TMP21:%.*]] = load i16, ptr [[AA_ADDR]], align 2
1902 // CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP21]] to i32
1903 // CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[CONV]], 1
1904 // CHECK1-NEXT: [[CONV12:%.*]] = trunc i32 [[ADD11]] to i16
1905 // CHECK1-NEXT: store i16 [[CONV12]], ptr [[AA_ADDR]], align 2
1906 // CHECK1-NEXT: [[TMP22:%.*]] = load i8, ptr [[AAA_ADDR]], align 1
1907 // CHECK1-NEXT: [[CONV13:%.*]] = sext i8 [[TMP22]] to i32
1908 // CHECK1-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV13]], 1
1909 // CHECK1-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i8
1910 // CHECK1-NEXT: store i8 [[CONV15]], ptr [[AAA_ADDR]], align 1
1911 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2
1912 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
1913 // CHECK1-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP23]], 1
1914 // CHECK1-NEXT: store i32 [[ADD16]], ptr [[ARRAYIDX]], align 4
1915 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1916 // CHECK1: omp.body.continue:
1917 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1918 // CHECK1: omp.inner.for.inc:
1919 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1920 // CHECK1-NEXT: [[ADD17:%.*]] = add i32 [[TMP24]], 1
1921 // CHECK1-NEXT: store i32 [[ADD17]], ptr [[DOTOMP_IV]], align 4
1922 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
1923 // CHECK1: omp.inner.for.end:
1924 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1925 // CHECK1: omp.loop.exit:
1926 // CHECK1-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1927 // CHECK1-NEXT: [[TMP26:%.*]] = load i32, ptr [[TMP25]], align 4
1928 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP26]])
1929 // CHECK1-NEXT: br label [[OMP_PRECOND_END]]
1930 // CHECK1: omp.precond.end:
1931 // CHECK1-NEXT: ret void
1934 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183
1935 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
1936 // CHECK1-NEXT: entry:
1937 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
1938 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
1939 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
1940 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
1941 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
1942 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
1943 // CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
1944 // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
1945 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
1946 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
1947 // CHECK1-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4
1948 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8
1949 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
1950 // CHECK1-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
1951 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8
1952 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], ptr [[TMP0]])
1953 // CHECK1-NEXT: ret void
1956 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183.omp_outlined
1957 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
1958 // CHECK1-NEXT: entry:
1959 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1960 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1961 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
1962 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
1963 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
1964 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1965 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
1966 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1967 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1968 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1969 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1970 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
1971 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1972 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1973 // CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
1974 // CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
1975 // CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
1976 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
1977 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
1978 // CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
1979 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1980 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1981 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1982 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
1983 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
1984 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1985 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
1986 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1987 // CHECK1: cond.true:
1988 // CHECK1-NEXT: br label [[COND_END:%.*]]
1989 // CHECK1: cond.false:
1990 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1991 // CHECK1-NEXT: br label [[COND_END]]
1992 // CHECK1: cond.end:
1993 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
1994 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
1995 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1996 // CHECK1-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
1997 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1998 // CHECK1: omp.inner.for.cond:
1999 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2000 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2001 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
2002 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2003 // CHECK1: omp.inner.for.body:
2004 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2005 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
2006 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2007 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4
2008 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4
2009 // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
2010 // CHECK1-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4
2011 // CHECK1-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2
2012 // CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i32
2013 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1
2014 // CHECK1-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
2015 // CHECK1-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2
2016 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2
2017 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
2018 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1
2019 // CHECK1-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4
2020 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2021 // CHECK1: omp.body.continue:
2022 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2023 // CHECK1: omp.inner.for.inc:
2024 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2025 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP12]], 1
2026 // CHECK1-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4
2027 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
2028 // CHECK1: omp.inner.for.end:
2029 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2030 // CHECK1: omp.loop.exit:
2031 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])
2032 // CHECK1-NEXT: ret void
2035 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
2036 // CHECK1-SAME: () #[[ATTR4]] {
2037 // CHECK1-NEXT: entry:
2038 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1)
2039 // CHECK1-NEXT: ret void
2042 // CHECK3-LABEL: define {{[^@]+}}@_Z3fooi
2043 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] {
2044 // CHECK3-NEXT: entry:
2045 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
2046 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4
2047 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2
2048 // CHECK3-NEXT: [[B:%.*]] = alloca [10 x float], align 4
2049 // CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4
2050 // CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
2051 // CHECK3-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8
2052 // CHECK3-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4
2053 // CHECK3-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
2054 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
2055 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
2056 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
2057 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
2058 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED3:%.*]] = alloca i32, align 4
2059 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 4
2060 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 4
2061 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 4
2062 // CHECK3-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4
2063 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
2064 // CHECK3-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 4
2065 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [1 x ptr], align 4
2066 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [1 x ptr], align 4
2067 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [1 x ptr], align 4
2068 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
2069 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
2070 // CHECK3-NEXT: [[A_CASTED8:%.*]] = alloca i32, align 4
2071 // CHECK3-NEXT: [[AA_CASTED9:%.*]] = alloca i32, align 4
2072 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [2 x ptr], align 4
2073 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS11:%.*]] = alloca [2 x ptr], align 4
2074 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [2 x ptr], align 4
2075 // CHECK3-NEXT: [[_TMP13:%.*]] = alloca i32, align 4
2076 // CHECK3-NEXT: [[KERNEL_ARGS14:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
2077 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_17:%.*]] = alloca i32, align 4
2078 // CHECK3-NEXT: [[A_CASTED18:%.*]] = alloca i32, align 4
2079 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED19:%.*]] = alloca i32, align 4
2080 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS22:%.*]] = alloca [10 x ptr], align 4
2081 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS23:%.*]] = alloca [10 x ptr], align 4
2082 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS24:%.*]] = alloca [10 x ptr], align 4
2083 // CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4
2084 // CHECK3-NEXT: [[_TMP25:%.*]] = alloca i32, align 4
2085 // CHECK3-NEXT: [[KERNEL_ARGS26:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
2086 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])
2087 // CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
2088 // CHECK3-NEXT: store i32 0, ptr [[A]], align 4
2089 // CHECK3-NEXT: store i16 0, ptr [[AA]], align 2
2090 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
2091 // CHECK3-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
2092 // CHECK3-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4
2093 // CHECK3-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4
2094 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4
2095 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4
2096 // CHECK3-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]]
2097 // CHECK3-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8
2098 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[__VLA_EXPR1]], align 4
2099 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4
2100 // CHECK3-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_]], align 4
2101 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[A]], align 4
2102 // CHECK3-NEXT: store i32 [[TMP6]], ptr [[DOTCAPTURE_EXPR_2]], align 4
2103 // CHECK3-NEXT: [[TMP7:%.*]] = load i16, ptr [[AA]], align 2
2104 // CHECK3-NEXT: store i16 [[TMP7]], ptr [[AA_CASTED]], align 2
2105 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[AA_CASTED]], align 4
2106 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
2107 // CHECK3-NEXT: store i32 [[TMP9]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
2108 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
2109 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
2110 // CHECK3-NEXT: store i32 [[TMP11]], ptr [[DOTCAPTURE_EXPR__CASTED3]], align 4
2111 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED3]], align 4
2112 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2113 // CHECK3-NEXT: store i32 [[TMP8]], ptr [[TMP13]], align 4
2114 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2115 // CHECK3-NEXT: store i32 [[TMP8]], ptr [[TMP14]], align 4
2116 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
2117 // CHECK3-NEXT: store ptr null, ptr [[TMP15]], align 4
2118 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
2119 // CHECK3-NEXT: store i32 [[TMP10]], ptr [[TMP16]], align 4
2120 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
2121 // CHECK3-NEXT: store i32 [[TMP10]], ptr [[TMP17]], align 4
2122 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
2123 // CHECK3-NEXT: store ptr null, ptr [[TMP18]], align 4
2124 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
2125 // CHECK3-NEXT: store i32 [[TMP12]], ptr [[TMP19]], align 4
2126 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
2127 // CHECK3-NEXT: store i32 [[TMP12]], ptr [[TMP20]], align 4
2128 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
2129 // CHECK3-NEXT: store ptr null, ptr [[TMP21]], align 4
2130 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2131 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2132 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0
2133 // CHECK3-NEXT: [[TMP25:%.*]] = load i16, ptr [[AA]], align 2
2134 // CHECK3-NEXT: store i16 [[TMP25]], ptr [[TMP24]], align 4
2135 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 1
2136 // CHECK3-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
2137 // CHECK3-NEXT: store i32 [[TMP27]], ptr [[TMP26]], align 4
2138 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 2
2139 // CHECK3-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
2140 // CHECK3-NEXT: store i32 [[TMP29]], ptr [[TMP28]], align 4
2141 // CHECK3-NEXT: [[TMP30:%.*]] = call ptr @__kmpc_omp_target_task_alloc(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 72, i32 12, ptr @.omp_task_entry., i64 -1)
2142 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP30]], i32 0, i32 0
2143 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP31]], i32 0, i32 0
2144 // CHECK3-NEXT: [[TMP33:%.*]] = load ptr, ptr [[TMP32]], align 4
2145 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP33]], ptr align 4 [[AGG_CAPTURED]], i32 12, i1 false)
2146 // CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP30]], i32 0, i32 1
2147 // CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP34]], i32 0, i32 0
2148 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP35]], ptr align 4 @.offload_sizes, i32 24, i1 false)
2149 // CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP34]], i32 0, i32 1
2150 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP36]], ptr align 4 [[TMP22]], i32 12, i1 false)
2151 // CHECK3-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP34]], i32 0, i32 2
2152 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP37]], ptr align 4 [[TMP23]], i32 12, i1 false)
2153 // CHECK3-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP34]], i32 0, i32 3
2154 // CHECK3-NEXT: [[TMP39:%.*]] = load i16, ptr [[AA]], align 2
2155 // CHECK3-NEXT: store i16 [[TMP39]], ptr [[TMP38]], align 4
2156 // CHECK3-NEXT: [[TMP40:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB2]], i32 [[TMP0]], ptr [[TMP30]])
2157 // CHECK3-NEXT: [[TMP41:%.*]] = load i32, ptr [[A]], align 4
2158 // CHECK3-NEXT: store i32 [[TMP41]], ptr [[A_CASTED]], align 4
2159 // CHECK3-NEXT: [[TMP42:%.*]] = load i32, ptr [[A_CASTED]], align 4
2160 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107(i32 [[TMP42]]) #[[ATTR3:[0-9]+]]
2161 // CHECK3-NEXT: [[TMP43:%.*]] = load i16, ptr [[AA]], align 2
2162 // CHECK3-NEXT: store i16 [[TMP43]], ptr [[AA_CASTED4]], align 2
2163 // CHECK3-NEXT: [[TMP44:%.*]] = load i32, ptr [[AA_CASTED4]], align 4
2164 // CHECK3-NEXT: [[TMP45:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0
2165 // CHECK3-NEXT: store i32 [[TMP44]], ptr [[TMP45]], align 4
2166 // CHECK3-NEXT: [[TMP46:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0
2167 // CHECK3-NEXT: store i32 [[TMP44]], ptr [[TMP46]], align 4
2168 // CHECK3-NEXT: [[TMP47:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 0
2169 // CHECK3-NEXT: store ptr null, ptr [[TMP47]], align 4
2170 // CHECK3-NEXT: [[TMP48:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0
2171 // CHECK3-NEXT: [[TMP49:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0
2172 // CHECK3-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
2173 // CHECK3-NEXT: store i32 2, ptr [[TMP50]], align 4
2174 // CHECK3-NEXT: [[TMP51:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
2175 // CHECK3-NEXT: store i32 1, ptr [[TMP51]], align 4
2176 // CHECK3-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
2177 // CHECK3-NEXT: store ptr [[TMP48]], ptr [[TMP52]], align 4
2178 // CHECK3-NEXT: [[TMP53:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
2179 // CHECK3-NEXT: store ptr [[TMP49]], ptr [[TMP53]], align 4
2180 // CHECK3-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
2181 // CHECK3-NEXT: store ptr @.offload_sizes.1, ptr [[TMP54]], align 4
2182 // CHECK3-NEXT: [[TMP55:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
2183 // CHECK3-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP55]], align 4
2184 // CHECK3-NEXT: [[TMP56:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
2185 // CHECK3-NEXT: store ptr null, ptr [[TMP56]], align 4
2186 // CHECK3-NEXT: [[TMP57:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
2187 // CHECK3-NEXT: store ptr null, ptr [[TMP57]], align 4
2188 // CHECK3-NEXT: [[TMP58:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
2189 // CHECK3-NEXT: store i64 10, ptr [[TMP58]], align 8
2190 // CHECK3-NEXT: [[TMP59:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
2191 // CHECK3-NEXT: store i64 0, ptr [[TMP59]], align 8
2192 // CHECK3-NEXT: [[TMP60:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
2193 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP60]], align 4
2194 // CHECK3-NEXT: [[TMP61:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
2195 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP61]], align 4
2196 // CHECK3-NEXT: [[TMP62:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
2197 // CHECK3-NEXT: store i32 0, ptr [[TMP62]], align 4
2198 // CHECK3-NEXT: [[TMP63:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113.region_id, ptr [[KERNEL_ARGS]])
2199 // CHECK3-NEXT: [[TMP64:%.*]] = icmp ne i32 [[TMP63]], 0
2200 // CHECK3-NEXT: br i1 [[TMP64]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
2201 // CHECK3: omp_offload.failed:
2202 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113(i32 [[TMP44]]) #[[ATTR3]]
2203 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
2204 // CHECK3: omp_offload.cont:
2205 // CHECK3-NEXT: [[TMP65:%.*]] = load i32, ptr [[A]], align 4
2206 // CHECK3-NEXT: store i32 [[TMP65]], ptr [[A_CASTED8]], align 4
2207 // CHECK3-NEXT: [[TMP66:%.*]] = load i32, ptr [[A_CASTED8]], align 4
2208 // CHECK3-NEXT: [[TMP67:%.*]] = load i16, ptr [[AA]], align 2
2209 // CHECK3-NEXT: store i16 [[TMP67]], ptr [[AA_CASTED9]], align 2
2210 // CHECK3-NEXT: [[TMP68:%.*]] = load i32, ptr [[AA_CASTED9]], align 4
2211 // CHECK3-NEXT: [[TMP69:%.*]] = load i32, ptr [[N_ADDR]], align 4
2212 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP69]], 10
2213 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
2214 // CHECK3: omp_if.then:
2215 // CHECK3-NEXT: [[TMP70:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
2216 // CHECK3-NEXT: store i32 [[TMP66]], ptr [[TMP70]], align 4
2217 // CHECK3-NEXT: [[TMP71:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
2218 // CHECK3-NEXT: store i32 [[TMP66]], ptr [[TMP71]], align 4
2219 // CHECK3-NEXT: [[TMP72:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS12]], i32 0, i32 0
2220 // CHECK3-NEXT: store ptr null, ptr [[TMP72]], align 4
2221 // CHECK3-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 1
2222 // CHECK3-NEXT: store i32 [[TMP68]], ptr [[TMP73]], align 4
2223 // CHECK3-NEXT: [[TMP74:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 1
2224 // CHECK3-NEXT: store i32 [[TMP68]], ptr [[TMP74]], align 4
2225 // CHECK3-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS12]], i32 0, i32 1
2226 // CHECK3-NEXT: store ptr null, ptr [[TMP75]], align 4
2227 // CHECK3-NEXT: [[TMP76:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
2228 // CHECK3-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
2229 // CHECK3-NEXT: [[TMP78:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 0
2230 // CHECK3-NEXT: store i32 2, ptr [[TMP78]], align 4
2231 // CHECK3-NEXT: [[TMP79:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 1
2232 // CHECK3-NEXT: store i32 2, ptr [[TMP79]], align 4
2233 // CHECK3-NEXT: [[TMP80:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 2
2234 // CHECK3-NEXT: store ptr [[TMP76]], ptr [[TMP80]], align 4
2235 // CHECK3-NEXT: [[TMP81:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 3
2236 // CHECK3-NEXT: store ptr [[TMP77]], ptr [[TMP81]], align 4
2237 // CHECK3-NEXT: [[TMP82:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 4
2238 // CHECK3-NEXT: store ptr @.offload_sizes.3, ptr [[TMP82]], align 4
2239 // CHECK3-NEXT: [[TMP83:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 5
2240 // CHECK3-NEXT: store ptr @.offload_maptypes.4, ptr [[TMP83]], align 4
2241 // CHECK3-NEXT: [[TMP84:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 6
2242 // CHECK3-NEXT: store ptr null, ptr [[TMP84]], align 4
2243 // CHECK3-NEXT: [[TMP85:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 7
2244 // CHECK3-NEXT: store ptr null, ptr [[TMP85]], align 4
2245 // CHECK3-NEXT: [[TMP86:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 8
2246 // CHECK3-NEXT: store i64 10, ptr [[TMP86]], align 8
2247 // CHECK3-NEXT: [[TMP87:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 9
2248 // CHECK3-NEXT: store i64 0, ptr [[TMP87]], align 8
2249 // CHECK3-NEXT: [[TMP88:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 10
2250 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP88]], align 4
2251 // CHECK3-NEXT: [[TMP89:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 11
2252 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP89]], align 4
2253 // CHECK3-NEXT: [[TMP90:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 12
2254 // CHECK3-NEXT: store i32 0, ptr [[TMP90]], align 4
2255 // CHECK3-NEXT: [[TMP91:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120.region_id, ptr [[KERNEL_ARGS14]])
2256 // CHECK3-NEXT: [[TMP92:%.*]] = icmp ne i32 [[TMP91]], 0
2257 // CHECK3-NEXT: br i1 [[TMP92]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]]
2258 // CHECK3: omp_offload.failed15:
2259 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120(i32 [[TMP66]], i32 [[TMP68]]) #[[ATTR3]]
2260 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT16]]
2261 // CHECK3: omp_offload.cont16:
2262 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]]
2263 // CHECK3: omp_if.else:
2264 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120(i32 [[TMP66]], i32 [[TMP68]]) #[[ATTR3]]
2265 // CHECK3-NEXT: br label [[OMP_IF_END]]
2266 // CHECK3: omp_if.end:
2267 // CHECK3-NEXT: [[TMP93:%.*]] = load i32, ptr [[N_ADDR]], align 4
2268 // CHECK3-NEXT: store i32 [[TMP93]], ptr [[DOTCAPTURE_EXPR_17]], align 4
2269 // CHECK3-NEXT: [[TMP94:%.*]] = load i32, ptr [[A]], align 4
2270 // CHECK3-NEXT: store i32 [[TMP94]], ptr [[A_CASTED18]], align 4
2271 // CHECK3-NEXT: [[TMP95:%.*]] = load i32, ptr [[A_CASTED18]], align 4
2272 // CHECK3-NEXT: [[TMP96:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_17]], align 4
2273 // CHECK3-NEXT: store i32 [[TMP96]], ptr [[DOTCAPTURE_EXPR__CASTED19]], align 4
2274 // CHECK3-NEXT: [[TMP97:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED19]], align 4
2275 // CHECK3-NEXT: [[TMP98:%.*]] = load i32, ptr [[N_ADDR]], align 4
2276 // CHECK3-NEXT: [[CMP20:%.*]] = icmp sgt i32 [[TMP98]], 20
2277 // CHECK3-NEXT: br i1 [[CMP20]], label [[OMP_IF_THEN21:%.*]], label [[OMP_IF_ELSE29:%.*]]
2278 // CHECK3: omp_if.then21:
2279 // CHECK3-NEXT: [[TMP99:%.*]] = mul nuw i32 [[TMP1]], 4
2280 // CHECK3-NEXT: [[TMP100:%.*]] = sext i32 [[TMP99]] to i64
2281 // CHECK3-NEXT: [[TMP101:%.*]] = mul nuw i32 5, [[TMP3]]
2282 // CHECK3-NEXT: [[TMP102:%.*]] = mul nuw i32 [[TMP101]], 8
2283 // CHECK3-NEXT: [[TMP103:%.*]] = sext i32 [[TMP102]] to i64
2284 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes.5, i32 80, i1 false)
2285 // CHECK3-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 0
2286 // CHECK3-NEXT: store i32 [[TMP95]], ptr [[TMP104]], align 4
2287 // CHECK3-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS23]], i32 0, i32 0
2288 // CHECK3-NEXT: store i32 [[TMP95]], ptr [[TMP105]], align 4
2289 // CHECK3-NEXT: [[TMP106:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS24]], i32 0, i32 0
2290 // CHECK3-NEXT: store ptr null, ptr [[TMP106]], align 4
2291 // CHECK3-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 1
2292 // CHECK3-NEXT: store ptr [[B]], ptr [[TMP107]], align 4
2293 // CHECK3-NEXT: [[TMP108:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS23]], i32 0, i32 1
2294 // CHECK3-NEXT: store ptr [[B]], ptr [[TMP108]], align 4
2295 // CHECK3-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS24]], i32 0, i32 1
2296 // CHECK3-NEXT: store ptr null, ptr [[TMP109]], align 4
2297 // CHECK3-NEXT: [[TMP110:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 2
2298 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP110]], align 4
2299 // CHECK3-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS23]], i32 0, i32 2
2300 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP111]], align 4
2301 // CHECK3-NEXT: [[TMP112:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS24]], i32 0, i32 2
2302 // CHECK3-NEXT: store ptr null, ptr [[TMP112]], align 4
2303 // CHECK3-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 3
2304 // CHECK3-NEXT: store ptr [[VLA]], ptr [[TMP113]], align 4
2305 // CHECK3-NEXT: [[TMP114:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS23]], i32 0, i32 3
2306 // CHECK3-NEXT: store ptr [[VLA]], ptr [[TMP114]], align 4
2307 // CHECK3-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 3
2308 // CHECK3-NEXT: store i64 [[TMP100]], ptr [[TMP115]], align 4
2309 // CHECK3-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS24]], i32 0, i32 3
2310 // CHECK3-NEXT: store ptr null, ptr [[TMP116]], align 4
2311 // CHECK3-NEXT: [[TMP117:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 4
2312 // CHECK3-NEXT: store ptr [[C]], ptr [[TMP117]], align 4
2313 // CHECK3-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS23]], i32 0, i32 4
2314 // CHECK3-NEXT: store ptr [[C]], ptr [[TMP118]], align 4
2315 // CHECK3-NEXT: [[TMP119:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS24]], i32 0, i32 4
2316 // CHECK3-NEXT: store ptr null, ptr [[TMP119]], align 4
2317 // CHECK3-NEXT: [[TMP120:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 5
2318 // CHECK3-NEXT: store i32 5, ptr [[TMP120]], align 4
2319 // CHECK3-NEXT: [[TMP121:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS23]], i32 0, i32 5
2320 // CHECK3-NEXT: store i32 5, ptr [[TMP121]], align 4
2321 // CHECK3-NEXT: [[TMP122:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS24]], i32 0, i32 5
2322 // CHECK3-NEXT: store ptr null, ptr [[TMP122]], align 4
2323 // CHECK3-NEXT: [[TMP123:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 6
2324 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP123]], align 4
2325 // CHECK3-NEXT: [[TMP124:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS23]], i32 0, i32 6
2326 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP124]], align 4
2327 // CHECK3-NEXT: [[TMP125:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS24]], i32 0, i32 6
2328 // CHECK3-NEXT: store ptr null, ptr [[TMP125]], align 4
2329 // CHECK3-NEXT: [[TMP126:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 7
2330 // CHECK3-NEXT: store ptr [[VLA1]], ptr [[TMP126]], align 4
2331 // CHECK3-NEXT: [[TMP127:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS23]], i32 0, i32 7
2332 // CHECK3-NEXT: store ptr [[VLA1]], ptr [[TMP127]], align 4
2333 // CHECK3-NEXT: [[TMP128:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 7
2334 // CHECK3-NEXT: store i64 [[TMP103]], ptr [[TMP128]], align 4
2335 // CHECK3-NEXT: [[TMP129:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS24]], i32 0, i32 7
2336 // CHECK3-NEXT: store ptr null, ptr [[TMP129]], align 4
2337 // CHECK3-NEXT: [[TMP130:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 8
2338 // CHECK3-NEXT: store ptr [[D]], ptr [[TMP130]], align 4
2339 // CHECK3-NEXT: [[TMP131:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS23]], i32 0, i32 8
2340 // CHECK3-NEXT: store ptr [[D]], ptr [[TMP131]], align 4
2341 // CHECK3-NEXT: [[TMP132:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS24]], i32 0, i32 8
2342 // CHECK3-NEXT: store ptr null, ptr [[TMP132]], align 4
2343 // CHECK3-NEXT: [[TMP133:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 9
2344 // CHECK3-NEXT: store i32 [[TMP97]], ptr [[TMP133]], align 4
2345 // CHECK3-NEXT: [[TMP134:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS23]], i32 0, i32 9
2346 // CHECK3-NEXT: store i32 [[TMP97]], ptr [[TMP134]], align 4
2347 // CHECK3-NEXT: [[TMP135:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS24]], i32 0, i32 9
2348 // CHECK3-NEXT: store ptr null, ptr [[TMP135]], align 4
2349 // CHECK3-NEXT: [[TMP136:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS22]], i32 0, i32 0
2350 // CHECK3-NEXT: [[TMP137:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS23]], i32 0, i32 0
2351 // CHECK3-NEXT: [[TMP138:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0
2352 // CHECK3-NEXT: [[TMP139:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 0
2353 // CHECK3-NEXT: store i32 2, ptr [[TMP139]], align 4
2354 // CHECK3-NEXT: [[TMP140:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 1
2355 // CHECK3-NEXT: store i32 10, ptr [[TMP140]], align 4
2356 // CHECK3-NEXT: [[TMP141:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 2
2357 // CHECK3-NEXT: store ptr [[TMP136]], ptr [[TMP141]], align 4
2358 // CHECK3-NEXT: [[TMP142:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 3
2359 // CHECK3-NEXT: store ptr [[TMP137]], ptr [[TMP142]], align 4
2360 // CHECK3-NEXT: [[TMP143:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 4
2361 // CHECK3-NEXT: store ptr [[TMP138]], ptr [[TMP143]], align 4
2362 // CHECK3-NEXT: [[TMP144:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 5
2363 // CHECK3-NEXT: store ptr @.offload_maptypes.6, ptr [[TMP144]], align 4
2364 // CHECK3-NEXT: [[TMP145:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 6
2365 // CHECK3-NEXT: store ptr null, ptr [[TMP145]], align 4
2366 // CHECK3-NEXT: [[TMP146:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 7
2367 // CHECK3-NEXT: store ptr null, ptr [[TMP146]], align 4
2368 // CHECK3-NEXT: [[TMP147:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 8
2369 // CHECK3-NEXT: store i64 10, ptr [[TMP147]], align 8
2370 // CHECK3-NEXT: [[TMP148:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 9
2371 // CHECK3-NEXT: store i64 0, ptr [[TMP148]], align 8
2372 // CHECK3-NEXT: [[TMP149:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 10
2373 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP149]], align 4
2374 // CHECK3-NEXT: [[TMP150:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 11
2375 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP150]], align 4
2376 // CHECK3-NEXT: [[TMP151:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS26]], i32 0, i32 12
2377 // CHECK3-NEXT: store i32 0, ptr [[TMP151]], align 4
2378 // CHECK3-NEXT: [[TMP152:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145.region_id, ptr [[KERNEL_ARGS26]])
2379 // CHECK3-NEXT: [[TMP153:%.*]] = icmp ne i32 [[TMP152]], 0
2380 // CHECK3-NEXT: br i1 [[TMP153]], label [[OMP_OFFLOAD_FAILED27:%.*]], label [[OMP_OFFLOAD_CONT28:%.*]]
2381 // CHECK3: omp_offload.failed27:
2382 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145(i32 [[TMP95]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]], i32 [[TMP97]]) #[[ATTR3]]
2383 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT28]]
2384 // CHECK3: omp_offload.cont28:
2385 // CHECK3-NEXT: br label [[OMP_IF_END30:%.*]]
2386 // CHECK3: omp_if.else29:
2387 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145(i32 [[TMP95]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]], i32 [[TMP97]]) #[[ATTR3]]
2388 // CHECK3-NEXT: br label [[OMP_IF_END30]]
2389 // CHECK3: omp_if.end30:
2390 // CHECK3-NEXT: [[TMP154:%.*]] = load i32, ptr [[A]], align 4
2391 // CHECK3-NEXT: [[TMP155:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
2392 // CHECK3-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP155]])
2393 // CHECK3-NEXT: ret i32 [[TMP154]]
2396 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
2397 // CHECK3-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] {
2398 // CHECK3-NEXT: entry:
2399 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
2400 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
2401 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4
2402 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
2403 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
2404 // CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
2405 // CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
2406 // CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4
2407 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
2408 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4
2409 // CHECK3-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
2410 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
2411 // CHECK3-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
2412 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4
2413 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined, i32 [[TMP4]])
2414 // CHECK3-NEXT: ret void
2417 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined
2418 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {
2419 // CHECK3-NEXT: entry:
2420 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
2421 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
2422 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
2423 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2424 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
2425 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
2426 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
2427 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2428 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2429 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
2430 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
2431 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
2432 // CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
2433 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
2434 // CHECK3-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
2435 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
2436 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2437 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
2438 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
2439 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
2440 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2441 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
2442 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2443 // CHECK3: cond.true:
2444 // CHECK3-NEXT: br label [[COND_END:%.*]]
2445 // CHECK3: cond.false:
2446 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2447 // CHECK3-NEXT: br label [[COND_END]]
2448 // CHECK3: cond.end:
2449 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
2450 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
2451 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
2452 // CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
2453 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2454 // CHECK3: omp.inner.for.cond:
2455 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2456 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2457 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
2458 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2459 // CHECK3: omp.inner.for.body:
2460 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2461 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
2462 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2463 // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4
2464 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2465 // CHECK3: omp.body.continue:
2466 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2467 // CHECK3: omp.inner.for.inc:
2468 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2469 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
2470 // CHECK3-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4
2471 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
2472 // CHECK3: omp.inner.for.end:
2473 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2474 // CHECK3: omp.loop.exit:
2475 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
2476 // CHECK3-NEXT: ret void
2479 // CHECK3-LABEL: define {{[^@]+}}@.omp_task_privates_map.
2480 // CHECK3-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]], ptr noalias noundef [[TMP3:%.*]], ptr noalias noundef [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] {
2481 // CHECK3-NEXT: entry:
2482 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4
2483 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4
2484 // CHECK3-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 4
2485 // CHECK3-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 4
2486 // CHECK3-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 4
2487 // CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4
2488 // CHECK3-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 4
2489 // CHECK3-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2]], align 4
2490 // CHECK3-NEXT: store ptr [[TMP3]], ptr [[DOTADDR3]], align 4
2491 // CHECK3-NEXT: store ptr [[TMP4]], ptr [[DOTADDR4]], align 4
2492 // CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR]], align 4
2493 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP5]], i32 0, i32 0
2494 // CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTADDR4]], align 4
2495 // CHECK3-NEXT: store ptr [[TMP6]], ptr [[TMP7]], align 4
2496 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 1
2497 // CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTADDR2]], align 4
2498 // CHECK3-NEXT: store ptr [[TMP8]], ptr [[TMP9]], align 4
2499 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 2
2500 // CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTADDR3]], align 4
2501 // CHECK3-NEXT: store ptr [[TMP10]], ptr [[TMP11]], align 4
2502 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 3
2503 // CHECK3-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTADDR1]], align 4
2504 // CHECK3-NEXT: store ptr [[TMP12]], ptr [[TMP13]], align 4
2505 // CHECK3-NEXT: ret void
2508 // CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry.
2509 // CHECK3-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] {
2510 // CHECK3-NEXT: entry:
2511 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
2512 // CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 4
2513 // CHECK3-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 4
2514 // CHECK3-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 4
2515 // CHECK3-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 4
2516 // CHECK3-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 4
2517 // CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca ptr, align 4
2518 // CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca ptr, align 4
2519 // CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca ptr, align 4
2520 // CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca ptr, align 4
2521 // CHECK3-NEXT: [[KERNEL_ARGS_I:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
2522 // CHECK3-NEXT: [[AA_CASTED_I:%.*]] = alloca i32, align 4
2523 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i32, align 4
2524 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED4_I:%.*]] = alloca i32, align 4
2525 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4
2526 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4
2527 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4
2528 // CHECK3-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 4
2529 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4
2530 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 4
2531 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0
2532 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2
2533 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0
2534 // CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 4
2535 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 1
2536 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META13:![0-9]+]])
2537 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]])
2538 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])
2539 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
2540 // CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !22
2541 // CHECK3-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 4, !noalias !22
2542 // CHECK3-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 4, !noalias !22
2543 // CHECK3-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !22
2544 // CHECK3-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 4, !noalias !22
2545 // CHECK3-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 4, !noalias !22
2546 // CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 4, !noalias !22
2547 // CHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !22
2548 // CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 4, !noalias !22
2549 // CHECK3-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]
2550 // CHECK3-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !22
2551 // CHECK3-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !22
2552 // CHECK3-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !22
2553 // CHECK3-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !22
2554 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP9]], i32 0, i32 1
2555 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP9]], i32 0, i32 2
2556 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP16]], align 4
2557 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP17]], align 4
2558 // CHECK3-NEXT: [[TMP20:%.*]] = insertvalue [3 x i32] zeroinitializer, i32 [[TMP18]], 0
2559 // CHECK3-NEXT: [[TMP21:%.*]] = insertvalue [3 x i32] zeroinitializer, i32 [[TMP19]], 0
2560 // CHECK3-NEXT: store i32 2, ptr [[KERNEL_ARGS_I]], align 4, !noalias !22
2561 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 1
2562 // CHECK3-NEXT: store i32 3, ptr [[TMP22]], align 4, !noalias !22
2563 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 2
2564 // CHECK3-NEXT: store ptr [[TMP13]], ptr [[TMP23]], align 4, !noalias !22
2565 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 3
2566 // CHECK3-NEXT: store ptr [[TMP14]], ptr [[TMP24]], align 4, !noalias !22
2567 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 4
2568 // CHECK3-NEXT: store ptr [[TMP15]], ptr [[TMP25]], align 4, !noalias !22
2569 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 5
2570 // CHECK3-NEXT: store ptr @.offload_maptypes, ptr [[TMP26]], align 4, !noalias !22
2571 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 6
2572 // CHECK3-NEXT: store ptr null, ptr [[TMP27]], align 4, !noalias !22
2573 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 7
2574 // CHECK3-NEXT: store ptr null, ptr [[TMP28]], align 4, !noalias !22
2575 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 8
2576 // CHECK3-NEXT: store i64 10, ptr [[TMP29]], align 8, !noalias !22
2577 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 9
2578 // CHECK3-NEXT: store i64 1, ptr [[TMP30]], align 8, !noalias !22
2579 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 10
2580 // CHECK3-NEXT: store [3 x i32] [[TMP20]], ptr [[TMP31]], align 4, !noalias !22
2581 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 11
2582 // CHECK3-NEXT: store [3 x i32] [[TMP21]], ptr [[TMP32]], align 4, !noalias !22
2583 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 12
2584 // CHECK3-NEXT: store i32 0, ptr [[TMP33]], align 4, !noalias !22
2585 // CHECK3-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 [[TMP18]], i32 [[TMP19]], ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, ptr [[KERNEL_ARGS_I]])
2586 // CHECK3-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0
2587 // CHECK3-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]]
2588 // CHECK3: omp_offload.failed.i:
2589 // CHECK3-NEXT: [[TMP36:%.*]] = load i16, ptr [[TMP12]], align 2
2590 // CHECK3-NEXT: store i16 [[TMP36]], ptr [[AA_CASTED_I]], align 2, !noalias !22
2591 // CHECK3-NEXT: [[TMP37:%.*]] = load i32, ptr [[AA_CASTED_I]], align 4, !noalias !22
2592 // CHECK3-NEXT: [[TMP38:%.*]] = load i32, ptr [[TMP16]], align 4
2593 // CHECK3-NEXT: store i32 [[TMP38]], ptr [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !22
2594 // CHECK3-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !22
2595 // CHECK3-NEXT: [[TMP40:%.*]] = load i32, ptr [[TMP17]], align 4
2596 // CHECK3-NEXT: store i32 [[TMP40]], ptr [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !22
2597 // CHECK3-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !22
2598 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103(i32 [[TMP37]], i32 [[TMP39]], i32 [[TMP41]]) #[[ATTR3]]
2599 // CHECK3-NEXT: br label [[DOTOMP_OUTLINED__EXIT]]
2600 // CHECK3: .omp_outlined..exit:
2601 // CHECK3-NEXT: ret i32 0
2604 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107
2605 // CHECK3-SAME: (i32 noundef [[A:%.*]]) #[[ATTR2]] {
2606 // CHECK3-NEXT: entry:
2607 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
2608 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
2609 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
2610 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
2611 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4
2612 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4
2613 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107.omp_outlined, i32 [[TMP1]])
2614 // CHECK3-NEXT: ret void
2617 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l107.omp_outlined
2618 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] {
2619 // CHECK3-NEXT: entry:
2620 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
2621 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
2622 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
2623 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2624 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
2625 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
2626 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
2627 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2628 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2629 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
2630 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
2631 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
2632 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
2633 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
2634 // CHECK3-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
2635 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
2636 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2637 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
2638 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
2639 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
2640 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2641 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
2642 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2643 // CHECK3: cond.true:
2644 // CHECK3-NEXT: br label [[COND_END:%.*]]
2645 // CHECK3: cond.false:
2646 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2647 // CHECK3-NEXT: br label [[COND_END]]
2648 // CHECK3: cond.end:
2649 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
2650 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
2651 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
2652 // CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
2653 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2654 // CHECK3: omp.inner.for.cond:
2655 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2656 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2657 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
2658 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2659 // CHECK3: omp.inner.for.body:
2660 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2661 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
2662 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2663 // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4
2664 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
2665 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
2666 // CHECK3-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4
2667 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2668 // CHECK3: omp.body.continue:
2669 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2670 // CHECK3: omp.inner.for.inc:
2671 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2672 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
2673 // CHECK3-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4
2674 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
2675 // CHECK3: omp.inner.for.end:
2676 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2677 // CHECK3: omp.loop.exit:
2678 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
2679 // CHECK3-NEXT: ret void
2682 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113
2683 // CHECK3-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR2]] {
2684 // CHECK3-NEXT: entry:
2685 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
2686 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
2687 // CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
2688 // CHECK3-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2
2689 // CHECK3-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2
2690 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[AA_CASTED]], align 4
2691 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113.omp_outlined, i32 [[TMP1]])
2692 // CHECK3-NEXT: ret void
2695 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113.omp_outlined
2696 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {
2697 // CHECK3-NEXT: entry:
2698 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
2699 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
2700 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
2701 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2702 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
2703 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
2704 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
2705 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2706 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2707 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
2708 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
2709 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
2710 // CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
2711 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
2712 // CHECK3-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
2713 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
2714 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2715 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
2716 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
2717 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
2718 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2719 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
2720 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2721 // CHECK3: cond.true:
2722 // CHECK3-NEXT: br label [[COND_END:%.*]]
2723 // CHECK3: cond.false:
2724 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2725 // CHECK3-NEXT: br label [[COND_END]]
2726 // CHECK3: cond.end:
2727 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
2728 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
2729 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
2730 // CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
2731 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2732 // CHECK3: omp.inner.for.cond:
2733 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2734 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2735 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
2736 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2737 // CHECK3: omp.inner.for.body:
2738 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2739 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
2740 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2741 // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4
2742 // CHECK3-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA_ADDR]], align 2
2743 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP8]] to i32
2744 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
2745 // CHECK3-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
2746 // CHECK3-NEXT: store i16 [[CONV3]], ptr [[AA_ADDR]], align 2
2747 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2748 // CHECK3: omp.body.continue:
2749 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2750 // CHECK3: omp.inner.for.inc:
2751 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2752 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], 1
2753 // CHECK3-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4
2754 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
2755 // CHECK3: omp.inner.for.end:
2756 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2757 // CHECK3: omp.loop.exit:
2758 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
2759 // CHECK3-NEXT: ret void
2762 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120
2763 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {
2764 // CHECK3-NEXT: entry:
2765 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
2766 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
2767 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
2768 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
2769 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
2770 // CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
2771 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
2772 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4
2773 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4
2774 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2
2775 // CHECK3-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
2776 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4
2777 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120.omp_outlined, i32 [[TMP1]], i32 [[TMP3]])
2778 // CHECK3-NEXT: ret void
2781 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120.omp_outlined
2782 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {
2783 // CHECK3-NEXT: entry:
2784 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
2785 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
2786 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
2787 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
2788 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2789 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
2790 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
2791 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
2792 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2793 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2794 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
2795 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
2796 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
2797 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
2798 // CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
2799 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
2800 // CHECK3-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
2801 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
2802 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2803 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
2804 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
2805 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
2806 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2807 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
2808 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2809 // CHECK3: cond.true:
2810 // CHECK3-NEXT: br label [[COND_END:%.*]]
2811 // CHECK3: cond.false:
2812 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2813 // CHECK3-NEXT: br label [[COND_END]]
2814 // CHECK3: cond.end:
2815 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
2816 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
2817 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
2818 // CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
2819 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2820 // CHECK3: omp.inner.for.cond:
2821 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2822 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2823 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
2824 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2825 // CHECK3: omp.inner.for.body:
2826 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2827 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
2828 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2829 // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4
2830 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
2831 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
2832 // CHECK3-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4
2833 // CHECK3-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2
2834 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP9]] to i32
2835 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1
2836 // CHECK3-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
2837 // CHECK3-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2
2838 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2839 // CHECK3: omp.body.continue:
2840 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2841 // CHECK3: omp.inner.for.inc:
2842 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2843 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP10]], 1
2844 // CHECK3-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4
2845 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
2846 // CHECK3: omp.inner.for.end:
2847 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2848 // CHECK3: omp.loop.exit:
2849 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
2850 // CHECK3-NEXT: ret void
2853 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145
2854 // CHECK3-SAME: (i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
2855 // CHECK3-NEXT: entry:
2856 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
2857 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
2858 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
2859 // CHECK3-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 4
2860 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4
2861 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
2862 // CHECK3-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
2863 // CHECK3-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 4
2864 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4
2865 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
2866 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
2867 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
2868 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
2869 // CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
2870 // CHECK3-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
2871 // CHECK3-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 4
2872 // CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4
2873 // CHECK3-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
2874 // CHECK3-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4
2875 // CHECK3-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4
2876 // CHECK3-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4
2877 // CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
2878 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
2879 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
2880 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4
2881 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
2882 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
2883 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4
2884 // CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4
2885 // CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4
2886 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
2887 // CHECK3-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4
2888 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4
2889 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
2890 // CHECK3-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
2891 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
2892 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145.omp_outlined, i32 [[TMP9]], ptr [[TMP0]], i32 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i32 [[TMP11]])
2893 // CHECK3-NEXT: ret void
2896 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145.omp_outlined
2897 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
2898 // CHECK3-NEXT: entry:
2899 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
2900 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
2901 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
2902 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
2903 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
2904 // CHECK3-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 4
2905 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4
2906 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
2907 // CHECK3-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
2908 // CHECK3-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 4
2909 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4
2910 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
2911 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2912 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
2913 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
2914 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
2915 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2916 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2917 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
2918 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
2919 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
2920 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
2921 // CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
2922 // CHECK3-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
2923 // CHECK3-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 4
2924 // CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4
2925 // CHECK3-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
2926 // CHECK3-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4
2927 // CHECK3-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4
2928 // CHECK3-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4
2929 // CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
2930 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
2931 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
2932 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4
2933 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
2934 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
2935 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4
2936 // CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4
2937 // CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4
2938 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
2939 // CHECK3-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
2940 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
2941 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2942 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
2943 // CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
2944 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4
2945 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP10]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
2946 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
2947 // CHECK3: omp.dispatch.cond:
2948 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2949 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9
2950 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2951 // CHECK3: cond.true:
2952 // CHECK3-NEXT: br label [[COND_END:%.*]]
2953 // CHECK3: cond.false:
2954 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2955 // CHECK3-NEXT: br label [[COND_END]]
2956 // CHECK3: cond.end:
2957 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
2958 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
2959 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
2960 // CHECK3-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4
2961 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2962 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2963 // CHECK3-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
2964 // CHECK3-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
2965 // CHECK3: omp.dispatch.body:
2966 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2967 // CHECK3: omp.inner.for.cond:
2968 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23:![0-9]+]]
2969 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP23]]
2970 // CHECK3-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
2971 // CHECK3-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2972 // CHECK3: omp.inner.for.body:
2973 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]]
2974 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
2975 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2976 // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP23]]
2977 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP23]]
2978 // CHECK3-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1
2979 // CHECK3-NEXT: store i32 [[ADD7]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP23]]
2980 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 2
2981 // CHECK3-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP23]]
2982 // CHECK3-NEXT: [[CONV:%.*]] = fpext float [[TMP20]] to double
2983 // CHECK3-NEXT: [[ADD8:%.*]] = fadd double [[CONV]], 1.000000e+00
2984 // CHECK3-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
2985 // CHECK3-NEXT: store float [[CONV9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP23]]
2986 // CHECK3-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i32 3
2987 // CHECK3-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP23]]
2988 // CHECK3-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double
2989 // CHECK3-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
2990 // CHECK3-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
2991 // CHECK3-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP23]]
2992 // CHECK3-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 1
2993 // CHECK3-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i32 0, i32 2
2994 // CHECK3-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP23]]
2995 // CHECK3-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
2996 // CHECK3-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP23]]
2997 // CHECK3-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]
2998 // CHECK3-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i32 [[TMP23]]
2999 // CHECK3-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX17]], i32 3
3000 // CHECK3-NEXT: [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP23]]
3001 // CHECK3-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
3002 // CHECK3-NEXT: store double [[ADD19]], ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP23]]
3003 // CHECK3-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0
3004 // CHECK3-NEXT: [[TMP25:%.*]] = load i64, ptr [[X]], align 4, !llvm.access.group [[ACC_GRP23]]
3005 // CHECK3-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
3006 // CHECK3-NEXT: store i64 [[ADD20]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP23]]
3007 // CHECK3-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1
3008 // CHECK3-NEXT: [[TMP26:%.*]] = load i8, ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP23]]
3009 // CHECK3-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
3010 // CHECK3-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
3011 // CHECK3-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
3012 // CHECK3-NEXT: store i8 [[CONV23]], ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP23]]
3013 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
3014 // CHECK3: omp.body.continue:
3015 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
3016 // CHECK3: omp.inner.for.inc:
3017 // CHECK3-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]]
3018 // CHECK3-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
3019 // CHECK3-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]]
3020 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]]
3021 // CHECK3: omp.inner.for.end:
3022 // CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
3023 // CHECK3: omp.dispatch.inc:
3024 // CHECK3-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
3025 // CHECK3-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
3026 // CHECK3-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
3027 // CHECK3-NEXT: store i32 [[ADD25]], ptr [[DOTOMP_LB]], align 4
3028 // CHECK3-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
3029 // CHECK3-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
3030 // CHECK3-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
3031 // CHECK3-NEXT: store i32 [[ADD26]], ptr [[DOTOMP_UB]], align 4
3032 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND]]
3033 // CHECK3: omp.dispatch.end:
3034 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP10]])
3035 // CHECK3-NEXT: ret void
3038 // CHECK3-LABEL: define {{[^@]+}}@_Z3bari
3039 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
3040 // CHECK3-NEXT: entry:
3041 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
3042 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4
3043 // CHECK3-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
3044 // CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
3045 // CHECK3-NEXT: store i32 0, ptr [[A]], align 4
3046 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
3047 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]])
3048 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 4
3049 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
3050 // CHECK3-NEXT: store i32 [[ADD]], ptr [[A]], align 4
3051 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
3052 // CHECK3-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]])
3053 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 4
3054 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
3055 // CHECK3-NEXT: store i32 [[ADD2]], ptr [[A]], align 4
3056 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
3057 // CHECK3-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]])
3058 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4
3059 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
3060 // CHECK3-NEXT: store i32 [[ADD4]], ptr [[A]], align 4
3061 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4
3062 // CHECK3-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]])
3063 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4
3064 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
3065 // CHECK3-NEXT: store i32 [[ADD6]], ptr [[A]], align 4
3066 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4
3067 // CHECK3-NEXT: ret i32 [[TMP8]]
3070 // CHECK3-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
3071 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 {
3072 // CHECK3-NEXT: entry:
3073 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
3074 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
3075 // CHECK3-NEXT: [[B:%.*]] = alloca i32, align 4
3076 // CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4
3077 // CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
3078 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
3079 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 4
3080 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 4
3081 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 4
3082 // CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4
3083 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
3084 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
3085 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
3086 // CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
3087 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
3088 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
3089 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
3090 // CHECK3-NEXT: store i32 [[ADD]], ptr [[B]], align 4
3091 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
3092 // CHECK3-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
3093 // CHECK3-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4
3094 // CHECK3-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
3095 // CHECK3-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
3096 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4
3097 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[B]], align 4
3098 // CHECK3-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4
3099 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4
3100 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4
3101 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60
3102 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
3103 // CHECK3: omp_if.then:
3104 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0
3105 // CHECK3-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]]
3106 // CHECK3-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2
3107 // CHECK3-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64
3108 // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes.7, i32 40, i1 false)
3109 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3110 // CHECK3-NEXT: store ptr [[THIS1]], ptr [[TMP10]], align 4
3111 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3112 // CHECK3-NEXT: store ptr [[A]], ptr [[TMP11]], align 4
3113 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
3114 // CHECK3-NEXT: store ptr null, ptr [[TMP12]], align 4
3115 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
3116 // CHECK3-NEXT: store i32 [[TMP5]], ptr [[TMP13]], align 4
3117 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
3118 // CHECK3-NEXT: store i32 [[TMP5]], ptr [[TMP14]], align 4
3119 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
3120 // CHECK3-NEXT: store ptr null, ptr [[TMP15]], align 4
3121 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
3122 // CHECK3-NEXT: store i32 2, ptr [[TMP16]], align 4
3123 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
3124 // CHECK3-NEXT: store i32 2, ptr [[TMP17]], align 4
3125 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
3126 // CHECK3-NEXT: store ptr null, ptr [[TMP18]], align 4
3127 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
3128 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP19]], align 4
3129 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
3130 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP20]], align 4
3131 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
3132 // CHECK3-NEXT: store ptr null, ptr [[TMP21]], align 4
3133 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
3134 // CHECK3-NEXT: store ptr [[VLA]], ptr [[TMP22]], align 4
3135 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4
3136 // CHECK3-NEXT: store ptr [[VLA]], ptr [[TMP23]], align 4
3137 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 4
3138 // CHECK3-NEXT: store i64 [[TMP9]], ptr [[TMP24]], align 4
3139 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
3140 // CHECK3-NEXT: store ptr null, ptr [[TMP25]], align 4
3141 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3142 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3143 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0
3144 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
3145 // CHECK3-NEXT: store i32 2, ptr [[TMP29]], align 4
3146 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
3147 // CHECK3-NEXT: store i32 5, ptr [[TMP30]], align 4
3148 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
3149 // CHECK3-NEXT: store ptr [[TMP26]], ptr [[TMP31]], align 4
3150 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
3151 // CHECK3-NEXT: store ptr [[TMP27]], ptr [[TMP32]], align 4
3152 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
3153 // CHECK3-NEXT: store ptr [[TMP28]], ptr [[TMP33]], align 4
3154 // CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
3155 // CHECK3-NEXT: store ptr @.offload_maptypes.8, ptr [[TMP34]], align 4
3156 // CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
3157 // CHECK3-NEXT: store ptr null, ptr [[TMP35]], align 4
3158 // CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
3159 // CHECK3-NEXT: store ptr null, ptr [[TMP36]], align 4
3160 // CHECK3-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
3161 // CHECK3-NEXT: store i64 10, ptr [[TMP37]], align 8
3162 // CHECK3-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
3163 // CHECK3-NEXT: store i64 0, ptr [[TMP38]], align 8
3164 // CHECK3-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
3165 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP39]], align 4
3166 // CHECK3-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
3167 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP40]], align 4
3168 // CHECK3-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
3169 // CHECK3-NEXT: store i32 0, ptr [[TMP41]], align 4
3170 // CHECK3-NEXT: [[TMP42:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218.region_id, ptr [[KERNEL_ARGS]])
3171 // CHECK3-NEXT: [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0
3172 // CHECK3-NEXT: br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
3173 // CHECK3: omp_offload.failed:
3174 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218(ptr [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], ptr [[VLA]]) #[[ATTR3]]
3175 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
3176 // CHECK3: omp_offload.cont:
3177 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]]
3178 // CHECK3: omp_if.else:
3179 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218(ptr [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], ptr [[VLA]]) #[[ATTR3]]
3180 // CHECK3-NEXT: br label [[OMP_IF_END]]
3181 // CHECK3: omp_if.end:
3182 // CHECK3-NEXT: [[TMP44:%.*]] = mul nsw i32 1, [[TMP1]]
3183 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP44]]
3184 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1
3185 // CHECK3-NEXT: [[TMP45:%.*]] = load i16, ptr [[ARRAYIDX2]], align 2
3186 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP45]] to i32
3187 // CHECK3-NEXT: [[TMP46:%.*]] = load i32, ptr [[B]], align 4
3188 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP46]]
3189 // CHECK3-NEXT: [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
3190 // CHECK3-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP47]])
3191 // CHECK3-NEXT: ret i32 [[ADD3]]
3194 // CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici
3195 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
3196 // CHECK3-NEXT: entry:
3197 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
3198 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4
3199 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2
3200 // CHECK3-NEXT: [[AAA:%.*]] = alloca i8, align 1
3201 // CHECK3-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
3202 // CHECK3-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4
3203 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
3204 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
3205 // CHECK3-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4
3206 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 4
3207 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 4
3208 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 4
3209 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
3210 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
3211 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
3212 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
3213 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
3214 // CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
3215 // CHECK3-NEXT: store i32 0, ptr [[A]], align 4
3216 // CHECK3-NEXT: store i16 0, ptr [[AA]], align 2
3217 // CHECK3-NEXT: store i8 0, ptr [[AAA]], align 1
3218 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
3219 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[N_CASTED]], align 4
3220 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_CASTED]], align 4
3221 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4
3222 // CHECK3-NEXT: store i32 [[TMP2]], ptr [[A_CASTED]], align 4
3223 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[A_CASTED]], align 4
3224 // CHECK3-NEXT: [[TMP4:%.*]] = load i16, ptr [[AA]], align 2
3225 // CHECK3-NEXT: store i16 [[TMP4]], ptr [[AA_CASTED]], align 2
3226 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[AA_CASTED]], align 4
3227 // CHECK3-NEXT: [[TMP6:%.*]] = load i8, ptr [[AAA]], align 1
3228 // CHECK3-NEXT: store i8 [[TMP6]], ptr [[AAA_CASTED]], align 1
3229 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[AAA_CASTED]], align 4
3230 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[N_ADDR]], align 4
3231 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 50
3232 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
3233 // CHECK3: omp_if.then:
3234 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3235 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP9]], align 4
3236 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3237 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP10]], align 4
3238 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
3239 // CHECK3-NEXT: store ptr null, ptr [[TMP11]], align 4
3240 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
3241 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP12]], align 4
3242 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
3243 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP13]], align 4
3244 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
3245 // CHECK3-NEXT: store ptr null, ptr [[TMP14]], align 4
3246 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
3247 // CHECK3-NEXT: store i32 [[TMP5]], ptr [[TMP15]], align 4
3248 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
3249 // CHECK3-NEXT: store i32 [[TMP5]], ptr [[TMP16]], align 4
3250 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
3251 // CHECK3-NEXT: store ptr null, ptr [[TMP17]], align 4
3252 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
3253 // CHECK3-NEXT: store i32 [[TMP7]], ptr [[TMP18]], align 4
3254 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
3255 // CHECK3-NEXT: store i32 [[TMP7]], ptr [[TMP19]], align 4
3256 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
3257 // CHECK3-NEXT: store ptr null, ptr [[TMP20]], align 4
3258 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
3259 // CHECK3-NEXT: store ptr [[B]], ptr [[TMP21]], align 4
3260 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4
3261 // CHECK3-NEXT: store ptr [[B]], ptr [[TMP22]], align 4
3262 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
3263 // CHECK3-NEXT: store ptr null, ptr [[TMP23]], align 4
3264 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3265 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3266 // CHECK3-NEXT: [[TMP26:%.*]] = load i32, ptr [[A]], align 4
3267 // CHECK3-NEXT: store i32 [[TMP26]], ptr [[DOTCAPTURE_EXPR_]], align 4
3268 // CHECK3-NEXT: [[TMP27:%.*]] = load i32, ptr [[N_ADDR]], align 4
3269 // CHECK3-NEXT: store i32 [[TMP27]], ptr [[DOTCAPTURE_EXPR_1]], align 4
3270 // CHECK3-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
3271 // CHECK3-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
3272 // CHECK3-NEXT: [[SUB:%.*]] = sub i32 [[TMP28]], [[TMP29]]
3273 // CHECK3-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1
3274 // CHECK3-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 1
3275 // CHECK3-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
3276 // CHECK3-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 1
3277 // CHECK3-NEXT: store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 4
3278 // CHECK3-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
3279 // CHECK3-NEXT: [[ADD5:%.*]] = add i32 [[TMP30]], 1
3280 // CHECK3-NEXT: [[TMP31:%.*]] = zext i32 [[ADD5]] to i64
3281 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
3282 // CHECK3-NEXT: store i32 2, ptr [[TMP32]], align 4
3283 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
3284 // CHECK3-NEXT: store i32 5, ptr [[TMP33]], align 4
3285 // CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
3286 // CHECK3-NEXT: store ptr [[TMP24]], ptr [[TMP34]], align 4
3287 // CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
3288 // CHECK3-NEXT: store ptr [[TMP25]], ptr [[TMP35]], align 4
3289 // CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
3290 // CHECK3-NEXT: store ptr @.offload_sizes.9, ptr [[TMP36]], align 4
3291 // CHECK3-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
3292 // CHECK3-NEXT: store ptr @.offload_maptypes.10, ptr [[TMP37]], align 4
3293 // CHECK3-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
3294 // CHECK3-NEXT: store ptr null, ptr [[TMP38]], align 4
3295 // CHECK3-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
3296 // CHECK3-NEXT: store ptr null, ptr [[TMP39]], align 4
3297 // CHECK3-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
3298 // CHECK3-NEXT: store i64 [[TMP31]], ptr [[TMP40]], align 8
3299 // CHECK3-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
3300 // CHECK3-NEXT: store i64 0, ptr [[TMP41]], align 8
3301 // CHECK3-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
3302 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP42]], align 4
3303 // CHECK3-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
3304 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP43]], align 4
3305 // CHECK3-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
3306 // CHECK3-NEXT: store i32 0, ptr [[TMP44]], align 4
3307 // CHECK3-NEXT: [[TMP45:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200.region_id, ptr [[KERNEL_ARGS]])
3308 // CHECK3-NEXT: [[TMP46:%.*]] = icmp ne i32 [[TMP45]], 0
3309 // CHECK3-NEXT: br i1 [[TMP46]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
3310 // CHECK3: omp_offload.failed:
3311 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], i32 [[TMP7]], ptr [[B]]) #[[ATTR3]]
3312 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
3313 // CHECK3: omp_offload.cont:
3314 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]]
3315 // CHECK3: omp_if.else:
3316 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], i32 [[TMP7]], ptr [[B]]) #[[ATTR3]]
3317 // CHECK3-NEXT: br label [[OMP_IF_END]]
3318 // CHECK3: omp_if.end:
3319 // CHECK3-NEXT: [[TMP47:%.*]] = load i32, ptr [[A]], align 4
3320 // CHECK3-NEXT: ret i32 [[TMP47]]
3323 // CHECK3-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
3324 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat {
3325 // CHECK3-NEXT: entry:
3326 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
3327 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4
3328 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2
3329 // CHECK3-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
3330 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
3331 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
3332 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 4
3333 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 4
3334 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 4
3335 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
3336 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
3337 // CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
3338 // CHECK3-NEXT: store i32 0, ptr [[A]], align 4
3339 // CHECK3-NEXT: store i16 0, ptr [[AA]], align 2
3340 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4
3341 // CHECK3-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4
3342 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4
3343 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA]], align 2
3344 // CHECK3-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
3345 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4
3346 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
3347 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
3348 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
3349 // CHECK3: omp_if.then:
3350 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3351 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP5]], align 4
3352 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3353 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP6]], align 4
3354 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
3355 // CHECK3-NEXT: store ptr null, ptr [[TMP7]], align 4
3356 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
3357 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP8]], align 4
3358 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
3359 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP9]], align 4
3360 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
3361 // CHECK3-NEXT: store ptr null, ptr [[TMP10]], align 4
3362 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
3363 // CHECK3-NEXT: store ptr [[B]], ptr [[TMP11]], align 4
3364 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
3365 // CHECK3-NEXT: store ptr [[B]], ptr [[TMP12]], align 4
3366 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
3367 // CHECK3-NEXT: store ptr null, ptr [[TMP13]], align 4
3368 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3369 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3370 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
3371 // CHECK3-NEXT: store i32 2, ptr [[TMP16]], align 4
3372 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
3373 // CHECK3-NEXT: store i32 3, ptr [[TMP17]], align 4
3374 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
3375 // CHECK3-NEXT: store ptr [[TMP14]], ptr [[TMP18]], align 4
3376 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
3377 // CHECK3-NEXT: store ptr [[TMP15]], ptr [[TMP19]], align 4
3378 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
3379 // CHECK3-NEXT: store ptr @.offload_sizes.11, ptr [[TMP20]], align 4
3380 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
3381 // CHECK3-NEXT: store ptr @.offload_maptypes.12, ptr [[TMP21]], align 4
3382 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
3383 // CHECK3-NEXT: store ptr null, ptr [[TMP22]], align 4
3384 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
3385 // CHECK3-NEXT: store ptr null, ptr [[TMP23]], align 4
3386 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
3387 // CHECK3-NEXT: store i64 10, ptr [[TMP24]], align 8
3388 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
3389 // CHECK3-NEXT: store i64 0, ptr [[TMP25]], align 8
3390 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
3391 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP26]], align 4
3392 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
3393 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP27]], align 4
3394 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
3395 // CHECK3-NEXT: store i32 0, ptr [[TMP28]], align 4
3396 // CHECK3-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183.region_id, ptr [[KERNEL_ARGS]])
3397 // CHECK3-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
3398 // CHECK3-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
3399 // CHECK3: omp_offload.failed:
3400 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR3]]
3401 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
3402 // CHECK3: omp_offload.cont:
3403 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]]
3404 // CHECK3: omp_if.else:
3405 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR3]]
3406 // CHECK3-NEXT: br label [[OMP_IF_END]]
3407 // CHECK3: omp_if.end:
3408 // CHECK3-NEXT: [[TMP31:%.*]] = load i32, ptr [[A]], align 4
3409 // CHECK3-NEXT: ret i32 [[TMP31]]
3412 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218
3413 // CHECK3-SAME: (ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
3414 // CHECK3-NEXT: entry:
3415 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
3416 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
3417 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
3418 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
3419 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4
3420 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
3421 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
3422 // CHECK3-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4
3423 // CHECK3-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
3424 // CHECK3-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
3425 // CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4
3426 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
3427 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
3428 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
3429 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
3430 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4
3431 // CHECK3-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4
3432 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4
3433 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218.omp_outlined, ptr [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], ptr [[TMP3]])
3434 // CHECK3-NEXT: ret void
3437 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218.omp_outlined
3438 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
3439 // CHECK3-NEXT: entry:
3440 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
3441 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
3442 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
3443 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
3444 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
3445 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
3446 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4
3447 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
3448 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
3449 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
3450 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
3451 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3452 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3453 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
3454 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
3455 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
3456 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
3457 // CHECK3-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4
3458 // CHECK3-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
3459 // CHECK3-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
3460 // CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4
3461 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
3462 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
3463 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
3464 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
3465 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
3466 // CHECK3-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
3467 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
3468 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
3469 // CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
3470 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
3471 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
3472 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
3473 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9
3474 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3475 // CHECK3: cond.true:
3476 // CHECK3-NEXT: br label [[COND_END:%.*]]
3477 // CHECK3: cond.false:
3478 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
3479 // CHECK3-NEXT: br label [[COND_END]]
3480 // CHECK3: cond.end:
3481 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
3482 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
3483 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
3484 // CHECK3-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4
3485 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
3486 // CHECK3: omp.inner.for.cond:
3487 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3488 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
3489 // CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
3490 // CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3491 // CHECK3: omp.inner.for.body:
3492 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3493 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
3494 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
3495 // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4
3496 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[B_ADDR]], align 4
3497 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double
3498 // CHECK3-NEXT: [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00
3499 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0
3500 // CHECK3-NEXT: store double [[ADD4]], ptr [[A]], align 4
3501 // CHECK3-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0
3502 // CHECK3-NEXT: [[TMP13:%.*]] = load double, ptr [[A5]], align 4
3503 // CHECK3-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
3504 // CHECK3-NEXT: store double [[INC]], ptr [[A5]], align 4
3505 // CHECK3-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16
3506 // CHECK3-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]]
3507 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i32 [[TMP14]]
3508 // CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1
3509 // CHECK3-NEXT: store i16 [[CONV6]], ptr [[ARRAYIDX7]], align 2
3510 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
3511 // CHECK3: omp.body.continue:
3512 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
3513 // CHECK3: omp.inner.for.inc:
3514 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3515 // CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1
3516 // CHECK3-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4
3517 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
3518 // CHECK3: omp.inner.for.end:
3519 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
3520 // CHECK3: omp.loop.exit:
3521 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])
3522 // CHECK3-NEXT: ret void
3525 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200
3526 // CHECK3-SAME: (i32 noundef [[N:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
3527 // CHECK3-NEXT: entry:
3528 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
3529 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
3530 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
3531 // CHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
3532 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
3533 // CHECK3-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4
3534 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
3535 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
3536 // CHECK3-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4
3537 // CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
3538 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
3539 // CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
3540 // CHECK3-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4
3541 // CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
3542 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
3543 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
3544 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[N_CASTED]], align 4
3545 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_CASTED]], align 4
3546 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[A_ADDR]], align 4
3547 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[A_CASTED]], align 4
3548 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_CASTED]], align 4
3549 // CHECK3-NEXT: [[TMP5:%.*]] = load i16, ptr [[AA_ADDR]], align 2
3550 // CHECK3-NEXT: store i16 [[TMP5]], ptr [[AA_CASTED]], align 2
3551 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[AA_CASTED]], align 4
3552 // CHECK3-NEXT: [[TMP7:%.*]] = load i8, ptr [[AAA_ADDR]], align 1
3553 // CHECK3-NEXT: store i8 [[TMP7]], ptr [[AAA_CASTED]], align 1
3554 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[AAA_CASTED]], align 4
3555 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], ptr [[TMP0]])
3556 // CHECK3-NEXT: ret void
3559 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200.omp_outlined
3560 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
3561 // CHECK3-NEXT: entry:
3562 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
3563 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
3564 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
3565 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
3566 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
3567 // CHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
3568 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
3569 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
3570 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
3571 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
3572 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
3573 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
3574 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
3575 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
3576 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
3577 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3578 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3579 // CHECK3-NEXT: [[I5:%.*]] = alloca i32, align 4
3580 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
3581 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
3582 // CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
3583 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
3584 // CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
3585 // CHECK3-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4
3586 // CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
3587 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
3588 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
3589 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
3590 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
3591 // CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
3592 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
3593 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
3594 // CHECK3-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
3595 // CHECK3-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1
3596 // CHECK3-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 1
3597 // CHECK3-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
3598 // CHECK3-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 1
3599 // CHECK3-NEXT: store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 4
3600 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
3601 // CHECK3-NEXT: store i32 [[TMP5]], ptr [[I]], align 4
3602 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
3603 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
3604 // CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
3605 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
3606 // CHECK3: omp.precond.then:
3607 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
3608 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
3609 // CHECK3-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_UB]], align 4
3610 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
3611 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
3612 // CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
3613 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4
3614 // CHECK3-NEXT: call void @__kmpc_for_static_init_4u(ptr @[[GLOB1]], i32 [[TMP10]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
3615 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
3616 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
3617 // CHECK3-NEXT: [[CMP6:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]]
3618 // CHECK3-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3619 // CHECK3: cond.true:
3620 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
3621 // CHECK3-NEXT: br label [[COND_END:%.*]]
3622 // CHECK3: cond.false:
3623 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
3624 // CHECK3-NEXT: br label [[COND_END]]
3625 // CHECK3: cond.end:
3626 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ]
3627 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
3628 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
3629 // CHECK3-NEXT: store i32 [[TMP15]], ptr [[DOTOMP_IV]], align 4
3630 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
3631 // CHECK3: omp.inner.for.cond:
3632 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3633 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
3634 // CHECK3-NEXT: [[ADD7:%.*]] = add i32 [[TMP17]], 1
3635 // CHECK3-NEXT: [[CMP8:%.*]] = icmp ult i32 [[TMP16]], [[ADD7]]
3636 // CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3637 // CHECK3: omp.inner.for.body:
3638 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
3639 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3640 // CHECK3-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1
3641 // CHECK3-NEXT: [[ADD9:%.*]] = add i32 [[TMP18]], [[MUL]]
3642 // CHECK3-NEXT: store i32 [[ADD9]], ptr [[I5]], align 4
3643 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[A_ADDR]], align 4
3644 // CHECK3-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP20]], 1
3645 // CHECK3-NEXT: store i32 [[ADD10]], ptr [[A_ADDR]], align 4
3646 // CHECK3-NEXT: [[TMP21:%.*]] = load i16, ptr [[AA_ADDR]], align 2
3647 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP21]] to i32
3648 // CHECK3-NEXT: [[ADD11:%.*]] = add nsw i32 [[CONV]], 1
3649 // CHECK3-NEXT: [[CONV12:%.*]] = trunc i32 [[ADD11]] to i16
3650 // CHECK3-NEXT: store i16 [[CONV12]], ptr [[AA_ADDR]], align 2
3651 // CHECK3-NEXT: [[TMP22:%.*]] = load i8, ptr [[AAA_ADDR]], align 1
3652 // CHECK3-NEXT: [[CONV13:%.*]] = sext i8 [[TMP22]] to i32
3653 // CHECK3-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV13]], 1
3654 // CHECK3-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i8
3655 // CHECK3-NEXT: store i8 [[CONV15]], ptr [[AAA_ADDR]], align 1
3656 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2
3657 // CHECK3-NEXT: [[TMP23:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
3658 // CHECK3-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP23]], 1
3659 // CHECK3-NEXT: store i32 [[ADD16]], ptr [[ARRAYIDX]], align 4
3660 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
3661 // CHECK3: omp.body.continue:
3662 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
3663 // CHECK3: omp.inner.for.inc:
3664 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3665 // CHECK3-NEXT: [[ADD17:%.*]] = add i32 [[TMP24]], 1
3666 // CHECK3-NEXT: store i32 [[ADD17]], ptr [[DOTOMP_IV]], align 4
3667 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
3668 // CHECK3: omp.inner.for.end:
3669 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
3670 // CHECK3: omp.loop.exit:
3671 // CHECK3-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
3672 // CHECK3-NEXT: [[TMP26:%.*]] = load i32, ptr [[TMP25]], align 4
3673 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP26]])
3674 // CHECK3-NEXT: br label [[OMP_PRECOND_END]]
3675 // CHECK3: omp.precond.end:
3676 // CHECK3-NEXT: ret void
3679 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183
3680 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
3681 // CHECK3-NEXT: entry:
3682 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
3683 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
3684 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
3685 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
3686 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
3687 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
3688 // CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
3689 // CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
3690 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
3691 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
3692 // CHECK3-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4
3693 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4
3694 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
3695 // CHECK3-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
3696 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4
3697 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], ptr [[TMP0]])
3698 // CHECK3-NEXT: ret void
3701 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183.omp_outlined
3702 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
3703 // CHECK3-NEXT: entry:
3704 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
3705 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
3706 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
3707 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
3708 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
3709 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
3710 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
3711 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
3712 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
3713 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3714 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3715 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
3716 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
3717 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
3718 // CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
3719 // CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
3720 // CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
3721 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
3722 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
3723 // CHECK3-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
3724 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
3725 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
3726 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
3727 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
3728 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
3729 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
3730 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
3731 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3732 // CHECK3: cond.true:
3733 // CHECK3-NEXT: br label [[COND_END:%.*]]
3734 // CHECK3: cond.false:
3735 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
3736 // CHECK3-NEXT: br label [[COND_END]]
3737 // CHECK3: cond.end:
3738 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
3739 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
3740 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
3741 // CHECK3-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
3742 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
3743 // CHECK3: omp.inner.for.cond:
3744 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3745 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
3746 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
3747 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3748 // CHECK3: omp.inner.for.body:
3749 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3750 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
3751 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
3752 // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4
3753 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4
3754 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
3755 // CHECK3-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4
3756 // CHECK3-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2
3757 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i32
3758 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1
3759 // CHECK3-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
3760 // CHECK3-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2
3761 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2
3762 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
3763 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1
3764 // CHECK3-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4
3765 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
3766 // CHECK3: omp.body.continue:
3767 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
3768 // CHECK3: omp.inner.for.inc:
3769 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3770 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP12]], 1
3771 // CHECK3-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4
3772 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
3773 // CHECK3: omp.inner.for.end:
3774 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
3775 // CHECK3: omp.loop.exit:
3776 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])
3777 // CHECK3-NEXT: ret void
3780 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
3781 // CHECK3-SAME: () #[[ATTR4]] {
3782 // CHECK3-NEXT: entry:
3783 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1)
3784 // CHECK3-NEXT: ret void
3787 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
3788 // CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] {
3789 // CHECK9-NEXT: entry:
3790 // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
3791 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
3792 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
3793 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8
3794 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
3795 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])
3796 // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
3797 // CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
3798 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
3799 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 8
3800 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
3801 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4
3802 // CHECK9-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
3803 // CHECK9-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
3804 // CHECK9-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
3805 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8
3806 // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined, i64 [[TMP4]])
3807 // CHECK9-NEXT: ret void
3810 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined
3811 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {
3812 // CHECK9-NEXT: entry:
3813 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
3814 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
3815 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
3816 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
3817 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
3818 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
3819 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
3820 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3821 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3822 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4
3823 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
3824 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
3825 // CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
3826 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
3827 // CHECK9-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
3828 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
3829 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
3830 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
3831 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
3832 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
3833 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
3834 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
3835 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3836 // CHECK9: cond.true:
3837 // CHECK9-NEXT: br label [[COND_END:%.*]]
3838 // CHECK9: cond.false:
3839 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
3840 // CHECK9-NEXT: br label [[COND_END]]
3841 // CHECK9: cond.end:
3842 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
3843 // CHECK9-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
3844 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
3845 // CHECK9-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
3846 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
3847 // CHECK9: omp.inner.for.cond:
3848 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3849 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
3850 // CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
3851 // CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3852 // CHECK9: omp.inner.for.body:
3853 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3854 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
3855 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
3856 // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4
3857 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
3858 // CHECK9: omp.body.continue:
3859 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
3860 // CHECK9: omp.inner.for.inc:
3861 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3862 // CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
3863 // CHECK9-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4
3864 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]]
3865 // CHECK9: omp.inner.for.end:
3866 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
3867 // CHECK9: omp.loop.exit:
3868 // CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
3869 // CHECK9-NEXT: ret void
3872 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113
3873 // CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {
3874 // CHECK9-NEXT: entry:
3875 // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
3876 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
3877 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
3878 // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
3879 // CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
3880 // CHECK9-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2
3881 // CHECK9-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2
3882 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[AA_CASTED]], align 8
3883 // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113.omp_outlined, i64 [[TMP1]])
3884 // CHECK9-NEXT: ret void
3887 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113.omp_outlined
3888 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {
3889 // CHECK9-NEXT: entry:
3890 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
3891 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
3892 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
3893 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
3894 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
3895 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
3896 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
3897 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3898 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3899 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4
3900 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
3901 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
3902 // CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
3903 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
3904 // CHECK9-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
3905 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
3906 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
3907 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
3908 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
3909 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
3910 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
3911 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
3912 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3913 // CHECK9: cond.true:
3914 // CHECK9-NEXT: br label [[COND_END:%.*]]
3915 // CHECK9: cond.false:
3916 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
3917 // CHECK9-NEXT: br label [[COND_END]]
3918 // CHECK9: cond.end:
3919 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
3920 // CHECK9-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
3921 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
3922 // CHECK9-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
3923 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
3924 // CHECK9: omp.inner.for.cond:
3925 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3926 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
3927 // CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
3928 // CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3929 // CHECK9: omp.inner.for.body:
3930 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3931 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
3932 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
3933 // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4
3934 // CHECK9-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA_ADDR]], align 2
3935 // CHECK9-NEXT: [[CONV:%.*]] = sext i16 [[TMP8]] to i32
3936 // CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
3937 // CHECK9-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
3938 // CHECK9-NEXT: store i16 [[CONV3]], ptr [[AA_ADDR]], align 2
3939 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
3940 // CHECK9: omp.body.continue:
3941 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
3942 // CHECK9: omp.inner.for.inc:
3943 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3944 // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], 1
3945 // CHECK9-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4
3946 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]]
3947 // CHECK9: omp.inner.for.end:
3948 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
3949 // CHECK9: omp.loop.exit:
3950 // CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
3951 // CHECK9-NEXT: ret void
3954 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120
3955 // CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {
3956 // CHECK9-NEXT: entry:
3957 // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
3958 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
3959 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
3960 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
3961 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
3962 // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
3963 // CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
3964 // CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
3965 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
3966 // CHECK9-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4
3967 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8
3968 // CHECK9-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2
3969 // CHECK9-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
3970 // CHECK9-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8
3971 // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120.omp_outlined, i64 [[TMP1]], i64 [[TMP3]])
3972 // CHECK9-NEXT: ret void
3975 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120.omp_outlined
3976 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {
3977 // CHECK9-NEXT: entry:
3978 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
3979 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
3980 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
3981 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
3982 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
3983 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
3984 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
3985 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
3986 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3987 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3988 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4
3989 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
3990 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
3991 // CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
3992 // CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
3993 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
3994 // CHECK9-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
3995 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
3996 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
3997 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
3998 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
3999 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
4000 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4001 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
4002 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4003 // CHECK9: cond.true:
4004 // CHECK9-NEXT: br label [[COND_END:%.*]]
4005 // CHECK9: cond.false:
4006 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4007 // CHECK9-NEXT: br label [[COND_END]]
4008 // CHECK9: cond.end:
4009 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
4010 // CHECK9-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
4011 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
4012 // CHECK9-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
4013 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
4014 // CHECK9: omp.inner.for.cond:
4015 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4016 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4017 // CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
4018 // CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4019 // CHECK9: omp.inner.for.body:
4020 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4021 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
4022 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
4023 // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4
4024 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
4025 // CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
4026 // CHECK9-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4
4027 // CHECK9-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2
4028 // CHECK9-NEXT: [[CONV:%.*]] = sext i16 [[TMP9]] to i32
4029 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1
4030 // CHECK9-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
4031 // CHECK9-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2
4032 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
4033 // CHECK9: omp.body.continue:
4034 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
4035 // CHECK9: omp.inner.for.inc:
4036 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4037 // CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP10]], 1
4038 // CHECK9-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4
4039 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]]
4040 // CHECK9: omp.inner.for.end:
4041 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
4042 // CHECK9: omp.loop.exit:
4043 // CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
4044 // CHECK9-NEXT: ret void
4047 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145
4048 // CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
4049 // CHECK9-NEXT: entry:
4050 // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
4051 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
4052 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
4053 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
4054 // CHECK9-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 8
4055 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8
4056 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
4057 // CHECK9-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
4058 // CHECK9-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 8
4059 // CHECK9-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8
4060 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
4061 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
4062 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
4063 // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
4064 // CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
4065 // CHECK9-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
4066 // CHECK9-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
4067 // CHECK9-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 8
4068 // CHECK9-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
4069 // CHECK9-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
4070 // CHECK9-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8
4071 // CHECK9-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8
4072 // CHECK9-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
4073 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
4074 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
4075 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
4076 // CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8
4077 // CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
4078 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
4079 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8
4080 // CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8
4081 // CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8
4082 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
4083 // CHECK9-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4
4084 // CHECK9-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 8
4085 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
4086 // CHECK9-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
4087 // CHECK9-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8
4088 // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145.omp_outlined, i64 [[TMP9]], ptr [[TMP0]], i64 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i64 [[TMP11]])
4089 // CHECK9-NEXT: ret void
4092 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145.omp_outlined
4093 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
4094 // CHECK9-NEXT: entry:
4095 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
4096 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
4097 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
4098 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
4099 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
4100 // CHECK9-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 8
4101 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8
4102 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
4103 // CHECK9-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
4104 // CHECK9-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 8
4105 // CHECK9-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8
4106 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
4107 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
4108 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
4109 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
4110 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
4111 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4112 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4113 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4
4114 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
4115 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
4116 // CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
4117 // CHECK9-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
4118 // CHECK9-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
4119 // CHECK9-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 8
4120 // CHECK9-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
4121 // CHECK9-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
4122 // CHECK9-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8
4123 // CHECK9-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8
4124 // CHECK9-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
4125 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
4126 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
4127 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
4128 // CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8
4129 // CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
4130 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
4131 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8
4132 // CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8
4133 // CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8
4134 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
4135 // CHECK9-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
4136 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
4137 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
4138 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
4139 // CHECK9-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
4140 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4
4141 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP10]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
4142 // CHECK9-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
4143 // CHECK9: omp.dispatch.cond:
4144 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4145 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9
4146 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4147 // CHECK9: cond.true:
4148 // CHECK9-NEXT: br label [[COND_END:%.*]]
4149 // CHECK9: cond.false:
4150 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4151 // CHECK9-NEXT: br label [[COND_END]]
4152 // CHECK9: cond.end:
4153 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
4154 // CHECK9-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
4155 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
4156 // CHECK9-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4
4157 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4158 // CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4159 // CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
4160 // CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
4161 // CHECK9: omp.dispatch.body:
4162 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
4163 // CHECK9: omp.inner.for.cond:
4164 // CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13:![0-9]+]]
4165 // CHECK9-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP13]]
4166 // CHECK9-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
4167 // CHECK9-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4168 // CHECK9: omp.inner.for.body:
4169 // CHECK9-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]]
4170 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
4171 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
4172 // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]]
4173 // CHECK9-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP13]]
4174 // CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1
4175 // CHECK9-NEXT: store i32 [[ADD7]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP13]]
4176 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 2
4177 // CHECK9-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP13]]
4178 // CHECK9-NEXT: [[CONV:%.*]] = fpext float [[TMP20]] to double
4179 // CHECK9-NEXT: [[ADD8:%.*]] = fadd double [[CONV]], 1.000000e+00
4180 // CHECK9-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
4181 // CHECK9-NEXT: store float [[CONV9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP13]]
4182 // CHECK9-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 3
4183 // CHECK9-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP13]]
4184 // CHECK9-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double
4185 // CHECK9-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
4186 // CHECK9-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
4187 // CHECK9-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP13]]
4188 // CHECK9-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 1
4189 // CHECK9-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i64 0, i64 2
4190 // CHECK9-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP13]]
4191 // CHECK9-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
4192 // CHECK9-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP13]]
4193 // CHECK9-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]
4194 // CHECK9-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i64 [[TMP23]]
4195 // CHECK9-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX17]], i64 3
4196 // CHECK9-NEXT: [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP13]]
4197 // CHECK9-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
4198 // CHECK9-NEXT: store double [[ADD19]], ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP13]]
4199 // CHECK9-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0
4200 // CHECK9-NEXT: [[TMP25:%.*]] = load i64, ptr [[X]], align 8, !llvm.access.group [[ACC_GRP13]]
4201 // CHECK9-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
4202 // CHECK9-NEXT: store i64 [[ADD20]], ptr [[X]], align 8, !llvm.access.group [[ACC_GRP13]]
4203 // CHECK9-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1
4204 // CHECK9-NEXT: [[TMP26:%.*]] = load i8, ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP13]]
4205 // CHECK9-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
4206 // CHECK9-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
4207 // CHECK9-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
4208 // CHECK9-NEXT: store i8 [[CONV23]], ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP13]]
4209 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
4210 // CHECK9: omp.body.continue:
4211 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
4212 // CHECK9: omp.inner.for.inc:
4213 // CHECK9-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]]
4214 // CHECK9-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
4215 // CHECK9-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]]
4216 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
4217 // CHECK9: omp.inner.for.end:
4218 // CHECK9-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
4219 // CHECK9: omp.dispatch.inc:
4220 // CHECK9-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
4221 // CHECK9-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
4222 // CHECK9-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
4223 // CHECK9-NEXT: store i32 [[ADD25]], ptr [[DOTOMP_LB]], align 4
4224 // CHECK9-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4225 // CHECK9-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
4226 // CHECK9-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
4227 // CHECK9-NEXT: store i32 [[ADD26]], ptr [[DOTOMP_UB]], align 4
4228 // CHECK9-NEXT: br label [[OMP_DISPATCH_COND]]
4229 // CHECK9: omp.dispatch.end:
4230 // CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP10]])
4231 // CHECK9-NEXT: ret void
4234 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200
4235 // CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[N:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
4236 // CHECK9-NEXT: entry:
4237 // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
4238 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
4239 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
4240 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
4241 // CHECK9-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
4242 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
4243 // CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
4244 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
4245 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
4246 // CHECK9-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8
4247 // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
4248 // CHECK9-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
4249 // CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
4250 // CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
4251 // CHECK9-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8
4252 // CHECK9-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
4253 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
4254 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
4255 // CHECK9-NEXT: store i32 [[TMP1]], ptr [[N_CASTED]], align 4
4256 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[N_CASTED]], align 8
4257 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[A_ADDR]], align 4
4258 // CHECK9-NEXT: store i32 [[TMP3]], ptr [[A_CASTED]], align 4
4259 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[A_CASTED]], align 8
4260 // CHECK9-NEXT: [[TMP5:%.*]] = load i16, ptr [[AA_ADDR]], align 2
4261 // CHECK9-NEXT: store i16 [[TMP5]], ptr [[AA_CASTED]], align 2
4262 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, ptr [[AA_CASTED]], align 8
4263 // CHECK9-NEXT: [[TMP7:%.*]] = load i8, ptr [[AAA_ADDR]], align 1
4264 // CHECK9-NEXT: store i8 [[TMP7]], ptr [[AAA_CASTED]], align 1
4265 // CHECK9-NEXT: [[TMP8:%.*]] = load i64, ptr [[AAA_CASTED]], align 8
4266 // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], ptr [[TMP0]])
4267 // CHECK9-NEXT: ret void
4270 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200.omp_outlined
4271 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
4272 // CHECK9-NEXT: entry:
4273 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
4274 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
4275 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
4276 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
4277 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
4278 // CHECK9-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
4279 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
4280 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
4281 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
4282 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
4283 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
4284 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
4285 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4
4286 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
4287 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
4288 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4289 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4290 // CHECK9-NEXT: [[I5:%.*]] = alloca i32, align 4
4291 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
4292 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
4293 // CHECK9-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
4294 // CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
4295 // CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
4296 // CHECK9-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8
4297 // CHECK9-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
4298 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
4299 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
4300 // CHECK9-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
4301 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
4302 // CHECK9-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
4303 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
4304 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
4305 // CHECK9-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
4306 // CHECK9-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1
4307 // CHECK9-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 1
4308 // CHECK9-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
4309 // CHECK9-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 1
4310 // CHECK9-NEXT: store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 4
4311 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
4312 // CHECK9-NEXT: store i32 [[TMP5]], ptr [[I]], align 4
4313 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
4314 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
4315 // CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
4316 // CHECK9-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
4317 // CHECK9: omp.precond.then:
4318 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
4319 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
4320 // CHECK9-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_UB]], align 4
4321 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
4322 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
4323 // CHECK9-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
4324 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4
4325 // CHECK9-NEXT: call void @__kmpc_for_static_init_4u(ptr @[[GLOB1]], i32 [[TMP10]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
4326 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4327 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
4328 // CHECK9-NEXT: [[CMP6:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]]
4329 // CHECK9-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4330 // CHECK9: cond.true:
4331 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
4332 // CHECK9-NEXT: br label [[COND_END:%.*]]
4333 // CHECK9: cond.false:
4334 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4335 // CHECK9-NEXT: br label [[COND_END]]
4336 // CHECK9: cond.end:
4337 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ]
4338 // CHECK9-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
4339 // CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
4340 // CHECK9-NEXT: store i32 [[TMP15]], ptr [[DOTOMP_IV]], align 4
4341 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
4342 // CHECK9: omp.inner.for.cond:
4343 // CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4344 // CHECK9-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4345 // CHECK9-NEXT: [[ADD7:%.*]] = add i32 [[TMP17]], 1
4346 // CHECK9-NEXT: [[CMP8:%.*]] = icmp ult i32 [[TMP16]], [[ADD7]]
4347 // CHECK9-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4348 // CHECK9: omp.inner.for.body:
4349 // CHECK9-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
4350 // CHECK9-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4351 // CHECK9-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1
4352 // CHECK9-NEXT: [[ADD9:%.*]] = add i32 [[TMP18]], [[MUL]]
4353 // CHECK9-NEXT: store i32 [[ADD9]], ptr [[I5]], align 4
4354 // CHECK9-NEXT: [[TMP20:%.*]] = load i32, ptr [[A_ADDR]], align 4
4355 // CHECK9-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP20]], 1
4356 // CHECK9-NEXT: store i32 [[ADD10]], ptr [[A_ADDR]], align 4
4357 // CHECK9-NEXT: [[TMP21:%.*]] = load i16, ptr [[AA_ADDR]], align 2
4358 // CHECK9-NEXT: [[CONV:%.*]] = sext i16 [[TMP21]] to i32
4359 // CHECK9-NEXT: [[ADD11:%.*]] = add nsw i32 [[CONV]], 1
4360 // CHECK9-NEXT: [[CONV12:%.*]] = trunc i32 [[ADD11]] to i16
4361 // CHECK9-NEXT: store i16 [[CONV12]], ptr [[AA_ADDR]], align 2
4362 // CHECK9-NEXT: [[TMP22:%.*]] = load i8, ptr [[AAA_ADDR]], align 1
4363 // CHECK9-NEXT: [[CONV13:%.*]] = sext i8 [[TMP22]] to i32
4364 // CHECK9-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV13]], 1
4365 // CHECK9-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i8
4366 // CHECK9-NEXT: store i8 [[CONV15]], ptr [[AAA_ADDR]], align 1
4367 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2
4368 // CHECK9-NEXT: [[TMP23:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
4369 // CHECK9-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP23]], 1
4370 // CHECK9-NEXT: store i32 [[ADD16]], ptr [[ARRAYIDX]], align 4
4371 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
4372 // CHECK9: omp.body.continue:
4373 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
4374 // CHECK9: omp.inner.for.inc:
4375 // CHECK9-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4376 // CHECK9-NEXT: [[ADD17:%.*]] = add i32 [[TMP24]], 1
4377 // CHECK9-NEXT: store i32 [[ADD17]], ptr [[DOTOMP_IV]], align 4
4378 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]]
4379 // CHECK9: omp.inner.for.end:
4380 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
4381 // CHECK9: omp.loop.exit:
4382 // CHECK9-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
4383 // CHECK9-NEXT: [[TMP26:%.*]] = load i32, ptr [[TMP25]], align 4
4384 // CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP26]])
4385 // CHECK9-NEXT: br label [[OMP_PRECOND_END]]
4386 // CHECK9: omp.precond.end:
4387 // CHECK9-NEXT: ret void
4390 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218
4391 // CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
4392 // CHECK9-NEXT: entry:
4393 // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
4394 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
4395 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
4396 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
4397 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
4398 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8
4399 // CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
4400 // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
4401 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
4402 // CHECK9-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8
4403 // CHECK9-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
4404 // CHECK9-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
4405 // CHECK9-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
4406 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
4407 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
4408 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
4409 // CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
4410 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4
4411 // CHECK9-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4
4412 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[B_CASTED]], align 8
4413 // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218.omp_outlined, ptr [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], ptr [[TMP3]])
4414 // CHECK9-NEXT: ret void
4417 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218.omp_outlined
4418 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
4419 // CHECK9-NEXT: entry:
4420 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
4421 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
4422 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
4423 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
4424 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
4425 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
4426 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8
4427 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
4428 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
4429 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
4430 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
4431 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4432 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4433 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4
4434 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
4435 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
4436 // CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
4437 // CHECK9-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8
4438 // CHECK9-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
4439 // CHECK9-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
4440 // CHECK9-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
4441 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
4442 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
4443 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
4444 // CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
4445 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
4446 // CHECK9-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
4447 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
4448 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
4449 // CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
4450 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
4451 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
4452 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4453 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9
4454 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4455 // CHECK9: cond.true:
4456 // CHECK9-NEXT: br label [[COND_END:%.*]]
4457 // CHECK9: cond.false:
4458 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4459 // CHECK9-NEXT: br label [[COND_END]]
4460 // CHECK9: cond.end:
4461 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
4462 // CHECK9-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
4463 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
4464 // CHECK9-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4
4465 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
4466 // CHECK9: omp.inner.for.cond:
4467 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4468 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4469 // CHECK9-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
4470 // CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4471 // CHECK9: omp.inner.for.body:
4472 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4473 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
4474 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
4475 // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4
4476 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[B_ADDR]], align 4
4477 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double
4478 // CHECK9-NEXT: [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00
4479 // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0
4480 // CHECK9-NEXT: store double [[ADD4]], ptr [[A]], align 8
4481 // CHECK9-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0
4482 // CHECK9-NEXT: [[TMP13:%.*]] = load double, ptr [[A5]], align 8
4483 // CHECK9-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
4484 // CHECK9-NEXT: store double [[INC]], ptr [[A5]], align 8
4485 // CHECK9-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16
4486 // CHECK9-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]]
4487 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i64 [[TMP14]]
4488 // CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1
4489 // CHECK9-NEXT: store i16 [[CONV6]], ptr [[ARRAYIDX7]], align 2
4490 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
4491 // CHECK9: omp.body.continue:
4492 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
4493 // CHECK9: omp.inner.for.inc:
4494 // CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4495 // CHECK9-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1
4496 // CHECK9-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4
4497 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]]
4498 // CHECK9: omp.inner.for.end:
4499 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
4500 // CHECK9: omp.loop.exit:
4501 // CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])
4502 // CHECK9-NEXT: ret void
4505 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183
4506 // CHECK9-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
4507 // CHECK9-NEXT: entry:
4508 // CHECK9-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
4509 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
4510 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
4511 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
4512 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
4513 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
4514 // CHECK9-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
4515 // CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
4516 // CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
4517 // CHECK9-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
4518 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
4519 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
4520 // CHECK9-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4
4521 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8
4522 // CHECK9-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
4523 // CHECK9-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
4524 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8
4525 // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], ptr [[TMP0]])
4526 // CHECK9-NEXT: ret void
4529 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183.omp_outlined
4530 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
4531 // CHECK9-NEXT: entry:
4532 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
4533 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
4534 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
4535 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
4536 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
4537 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
4538 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
4539 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
4540 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
4541 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4542 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4543 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4
4544 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
4545 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
4546 // CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
4547 // CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
4548 // CHECK9-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
4549 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
4550 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
4551 // CHECK9-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
4552 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
4553 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
4554 // CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
4555 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
4556 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
4557 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4558 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
4559 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4560 // CHECK9: cond.true:
4561 // CHECK9-NEXT: br label [[COND_END:%.*]]
4562 // CHECK9: cond.false:
4563 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4564 // CHECK9-NEXT: br label [[COND_END]]
4565 // CHECK9: cond.end:
4566 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
4567 // CHECK9-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
4568 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
4569 // CHECK9-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
4570 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
4571 // CHECK9: omp.inner.for.cond:
4572 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4573 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4574 // CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
4575 // CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4576 // CHECK9: omp.inner.for.body:
4577 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4578 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
4579 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
4580 // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4
4581 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4
4582 // CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
4583 // CHECK9-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4
4584 // CHECK9-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2
4585 // CHECK9-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i32
4586 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1
4587 // CHECK9-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
4588 // CHECK9-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2
4589 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2
4590 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
4591 // CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1
4592 // CHECK9-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4
4593 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
4594 // CHECK9: omp.body.continue:
4595 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
4596 // CHECK9: omp.inner.for.inc:
4597 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4598 // CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP12]], 1
4599 // CHECK9-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4
4600 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]]
4601 // CHECK9: omp.inner.for.end:
4602 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
4603 // CHECK9: omp.loop.exit:
4604 // CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])
4605 // CHECK9-NEXT: ret void
4608 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
4609 // CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] {
4610 // CHECK11-NEXT: entry:
4611 // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
4612 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
4613 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
4614 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4
4615 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
4616 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])
4617 // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
4618 // CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
4619 // CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
4620 // CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4
4621 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
4622 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4
4623 // CHECK11-NEXT: call void @__kmpc_push_num_teams(ptr @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
4624 // CHECK11-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
4625 // CHECK11-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
4626 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4
4627 // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined, i32 [[TMP4]])
4628 // CHECK11-NEXT: ret void
4631 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.omp_outlined
4632 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {
4633 // CHECK11-NEXT: entry:
4634 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
4635 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
4636 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
4637 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
4638 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4
4639 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
4640 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
4641 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4642 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4643 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4
4644 // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
4645 // CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
4646 // CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
4647 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
4648 // CHECK11-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
4649 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
4650 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
4651 // CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
4652 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
4653 // CHECK11-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
4654 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4655 // CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
4656 // CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4657 // CHECK11: cond.true:
4658 // CHECK11-NEXT: br label [[COND_END:%.*]]
4659 // CHECK11: cond.false:
4660 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4661 // CHECK11-NEXT: br label [[COND_END]]
4662 // CHECK11: cond.end:
4663 // CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
4664 // CHECK11-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
4665 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
4666 // CHECK11-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
4667 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
4668 // CHECK11: omp.inner.for.cond:
4669 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4670 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4671 // CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
4672 // CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4673 // CHECK11: omp.inner.for.body:
4674 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4675 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
4676 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
4677 // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4
4678 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
4679 // CHECK11: omp.body.continue:
4680 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
4681 // CHECK11: omp.inner.for.inc:
4682 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4683 // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
4684 // CHECK11-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4
4685 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]]
4686 // CHECK11: omp.inner.for.end:
4687 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
4688 // CHECK11: omp.loop.exit:
4689 // CHECK11-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
4690 // CHECK11-NEXT: ret void
4693 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113
4694 // CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {
4695 // CHECK11-NEXT: entry:
4696 // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
4697 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
4698 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
4699 // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
4700 // CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
4701 // CHECK11-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2
4702 // CHECK11-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2
4703 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[AA_CASTED]], align 4
4704 // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113.omp_outlined, i32 [[TMP1]])
4705 // CHECK11-NEXT: ret void
4708 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l113.omp_outlined
4709 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {
4710 // CHECK11-NEXT: entry:
4711 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
4712 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
4713 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
4714 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
4715 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4
4716 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
4717 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
4718 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4719 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4720 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4
4721 // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
4722 // CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
4723 // CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
4724 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
4725 // CHECK11-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
4726 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
4727 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
4728 // CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
4729 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
4730 // CHECK11-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
4731 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4732 // CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
4733 // CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4734 // CHECK11: cond.true:
4735 // CHECK11-NEXT: br label [[COND_END:%.*]]
4736 // CHECK11: cond.false:
4737 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4738 // CHECK11-NEXT: br label [[COND_END]]
4739 // CHECK11: cond.end:
4740 // CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
4741 // CHECK11-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
4742 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
4743 // CHECK11-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
4744 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
4745 // CHECK11: omp.inner.for.cond:
4746 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4747 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4748 // CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
4749 // CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4750 // CHECK11: omp.inner.for.body:
4751 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4752 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
4753 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
4754 // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4
4755 // CHECK11-NEXT: [[TMP8:%.*]] = load i16, ptr [[AA_ADDR]], align 2
4756 // CHECK11-NEXT: [[CONV:%.*]] = sext i16 [[TMP8]] to i32
4757 // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
4758 // CHECK11-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
4759 // CHECK11-NEXT: store i16 [[CONV3]], ptr [[AA_ADDR]], align 2
4760 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
4761 // CHECK11: omp.body.continue:
4762 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
4763 // CHECK11: omp.inner.for.inc:
4764 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4765 // CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], 1
4766 // CHECK11-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4
4767 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]]
4768 // CHECK11: omp.inner.for.end:
4769 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
4770 // CHECK11: omp.loop.exit:
4771 // CHECK11-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
4772 // CHECK11-NEXT: ret void
4775 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120
4776 // CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {
4777 // CHECK11-NEXT: entry:
4778 // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
4779 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
4780 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
4781 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
4782 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
4783 // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
4784 // CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
4785 // CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
4786 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
4787 // CHECK11-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4
4788 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4
4789 // CHECK11-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2
4790 // CHECK11-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
4791 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4
4792 // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120.omp_outlined, i32 [[TMP1]], i32 [[TMP3]])
4793 // CHECK11-NEXT: ret void
4796 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l120.omp_outlined
4797 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {
4798 // CHECK11-NEXT: entry:
4799 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
4800 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
4801 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
4802 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
4803 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
4804 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4
4805 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
4806 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
4807 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4808 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4809 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4
4810 // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
4811 // CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
4812 // CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
4813 // CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
4814 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
4815 // CHECK11-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
4816 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
4817 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
4818 // CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
4819 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
4820 // CHECK11-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
4821 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4822 // CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
4823 // CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4824 // CHECK11: cond.true:
4825 // CHECK11-NEXT: br label [[COND_END:%.*]]
4826 // CHECK11: cond.false:
4827 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4828 // CHECK11-NEXT: br label [[COND_END]]
4829 // CHECK11: cond.end:
4830 // CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
4831 // CHECK11-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
4832 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
4833 // CHECK11-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
4834 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
4835 // CHECK11: omp.inner.for.cond:
4836 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4837 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4838 // CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
4839 // CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4840 // CHECK11: omp.inner.for.body:
4841 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4842 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
4843 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
4844 // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4
4845 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
4846 // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
4847 // CHECK11-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4
4848 // CHECK11-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2
4849 // CHECK11-NEXT: [[CONV:%.*]] = sext i16 [[TMP9]] to i32
4850 // CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1
4851 // CHECK11-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
4852 // CHECK11-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2
4853 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
4854 // CHECK11: omp.body.continue:
4855 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
4856 // CHECK11: omp.inner.for.inc:
4857 // CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4858 // CHECK11-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP10]], 1
4859 // CHECK11-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4
4860 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]]
4861 // CHECK11: omp.inner.for.end:
4862 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
4863 // CHECK11: omp.loop.exit:
4864 // CHECK11-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
4865 // CHECK11-NEXT: ret void
4868 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145
4869 // CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
4870 // CHECK11-NEXT: entry:
4871 // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
4872 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
4873 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
4874 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
4875 // CHECK11-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 4
4876 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4
4877 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
4878 // CHECK11-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
4879 // CHECK11-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 4
4880 // CHECK11-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4
4881 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
4882 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
4883 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
4884 // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
4885 // CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
4886 // CHECK11-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
4887 // CHECK11-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
4888 // CHECK11-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 4
4889 // CHECK11-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4
4890 // CHECK11-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
4891 // CHECK11-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4
4892 // CHECK11-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4
4893 // CHECK11-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4
4894 // CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
4895 // CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
4896 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
4897 // CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4
4898 // CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
4899 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
4900 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4
4901 // CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4
4902 // CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4
4903 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
4904 // CHECK11-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4
4905 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4
4906 // CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
4907 // CHECK11-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
4908 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
4909 // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 10, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145.omp_outlined, i32 [[TMP9]], ptr [[TMP0]], i32 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i32 [[TMP11]])
4910 // CHECK11-NEXT: ret void
4913 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l145.omp_outlined
4914 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
4915 // CHECK11-NEXT: entry:
4916 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
4917 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
4918 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
4919 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
4920 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
4921 // CHECK11-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 4
4922 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4
4923 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
4924 // CHECK11-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
4925 // CHECK11-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 4
4926 // CHECK11-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4
4927 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
4928 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
4929 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4
4930 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
4931 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
4932 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4933 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4934 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4
4935 // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
4936 // CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
4937 // CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
4938 // CHECK11-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
4939 // CHECK11-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
4940 // CHECK11-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 4
4941 // CHECK11-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4
4942 // CHECK11-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
4943 // CHECK11-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4
4944 // CHECK11-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4
4945 // CHECK11-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4
4946 // CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
4947 // CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
4948 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
4949 // CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4
4950 // CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
4951 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
4952 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4
4953 // CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4
4954 // CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4
4955 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
4956 // CHECK11-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
4957 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
4958 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
4959 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
4960 // CHECK11-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
4961 // CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4
4962 // CHECK11-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP10]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
4963 // CHECK11-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
4964 // CHECK11: omp.dispatch.cond:
4965 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4966 // CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9
4967 // CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4968 // CHECK11: cond.true:
4969 // CHECK11-NEXT: br label [[COND_END:%.*]]
4970 // CHECK11: cond.false:
4971 // CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4972 // CHECK11-NEXT: br label [[COND_END]]
4973 // CHECK11: cond.end:
4974 // CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
4975 // CHECK11-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
4976 // CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
4977 // CHECK11-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4
4978 // CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4979 // CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4980 // CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
4981 // CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
4982 // CHECK11: omp.dispatch.body:
4983 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
4984 // CHECK11: omp.inner.for.cond:
4985 // CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14:![0-9]+]]
4986 // CHECK11-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP14]]
4987 // CHECK11-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
4988 // CHECK11-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4989 // CHECK11: omp.inner.for.body:
4990 // CHECK11-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]
4991 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
4992 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
4993 // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP14]]
4994 // CHECK11-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP14]]
4995 // CHECK11-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1
4996 // CHECK11-NEXT: store i32 [[ADD7]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP14]]
4997 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 2
4998 // CHECK11-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP14]]
4999 // CHECK11-NEXT: [[CONV:%.*]] = fpext float [[TMP20]] to double
5000 // CHECK11-NEXT: [[ADD8:%.*]] = fadd double [[CONV]], 1.000000e+00
5001 // CHECK11-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
5002 // CHECK11-NEXT: store float [[CONV9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP14]]
5003 // CHECK11-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i32 3
5004 // CHECK11-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP14]]
5005 // CHECK11-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double
5006 // CHECK11-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
5007 // CHECK11-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
5008 // CHECK11-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP14]]
5009 // CHECK11-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 1
5010 // CHECK11-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i32 0, i32 2
5011 // CHECK11-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP14]]
5012 // CHECK11-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
5013 // CHECK11-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP14]]
5014 // CHECK11-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]
5015 // CHECK11-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i32 [[TMP23]]
5016 // CHECK11-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX17]], i32 3
5017 // CHECK11-NEXT: [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP14]]
5018 // CHECK11-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
5019 // CHECK11-NEXT: store double [[ADD19]], ptr [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP14]]
5020 // CHECK11-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0
5021 // CHECK11-NEXT: [[TMP25:%.*]] = load i64, ptr [[X]], align 4, !llvm.access.group [[ACC_GRP14]]
5022 // CHECK11-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
5023 // CHECK11-NEXT: store i64 [[ADD20]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP14]]
5024 // CHECK11-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1
5025 // CHECK11-NEXT: [[TMP26:%.*]] = load i8, ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP14]]
5026 // CHECK11-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
5027 // CHECK11-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
5028 // CHECK11-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
5029 // CHECK11-NEXT: store i8 [[CONV23]], ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP14]]
5030 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
5031 // CHECK11: omp.body.continue:
5032 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
5033 // CHECK11: omp.inner.for.inc:
5034 // CHECK11-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]
5035 // CHECK11-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
5036 // CHECK11-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]
5037 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
5038 // CHECK11: omp.inner.for.end:
5039 // CHECK11-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
5040 // CHECK11: omp.dispatch.inc:
5041 // CHECK11-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
5042 // CHECK11-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
5043 // CHECK11-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
5044 // CHECK11-NEXT: store i32 [[ADD25]], ptr [[DOTOMP_LB]], align 4
5045 // CHECK11-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
5046 // CHECK11-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
5047 // CHECK11-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
5048 // CHECK11-NEXT: store i32 [[ADD26]], ptr [[DOTOMP_UB]], align 4
5049 // CHECK11-NEXT: br label [[OMP_DISPATCH_COND]]
5050 // CHECK11: omp.dispatch.end:
5051 // CHECK11-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP10]])
5052 // CHECK11-NEXT: ret void
5055 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200
5056 // CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[N:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
5057 // CHECK11-NEXT: entry:
5058 // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
5059 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
5060 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
5061 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
5062 // CHECK11-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
5063 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
5064 // CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4
5065 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
5066 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
5067 // CHECK11-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4
5068 // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
5069 // CHECK11-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
5070 // CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
5071 // CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
5072 // CHECK11-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4
5073 // CHECK11-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
5074 // CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
5075 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
5076 // CHECK11-NEXT: store i32 [[TMP1]], ptr [[N_CASTED]], align 4
5077 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_CASTED]], align 4
5078 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[A_ADDR]], align 4
5079 // CHECK11-NEXT: store i32 [[TMP3]], ptr [[A_CASTED]], align 4
5080 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_CASTED]], align 4
5081 // CHECK11-NEXT: [[TMP5:%.*]] = load i16, ptr [[AA_ADDR]], align 2
5082 // CHECK11-NEXT: store i16 [[TMP5]], ptr [[AA_CASTED]], align 2
5083 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[AA_CASTED]], align 4
5084 // CHECK11-NEXT: [[TMP7:%.*]] = load i8, ptr [[AAA_ADDR]], align 1
5085 // CHECK11-NEXT: store i8 [[TMP7]], ptr [[AAA_CASTED]], align 1
5086 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[AAA_CASTED]], align 4
5087 // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], ptr [[TMP0]])
5088 // CHECK11-NEXT: ret void
5091 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l200.omp_outlined
5092 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
5093 // CHECK11-NEXT: entry:
5094 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
5095 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
5096 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
5097 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
5098 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
5099 // CHECK11-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
5100 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
5101 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
5102 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4
5103 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
5104 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
5105 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
5106 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4
5107 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
5108 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
5109 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
5110 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
5111 // CHECK11-NEXT: [[I5:%.*]] = alloca i32, align 4
5112 // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
5113 // CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
5114 // CHECK11-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
5115 // CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
5116 // CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
5117 // CHECK11-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4
5118 // CHECK11-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
5119 // CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
5120 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
5121 // CHECK11-NEXT: store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
5122 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
5123 // CHECK11-NEXT: store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
5124 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
5125 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
5126 // CHECK11-NEXT: [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
5127 // CHECK11-NEXT: [[SUB3:%.*]] = sub i32 [[SUB]], 1
5128 // CHECK11-NEXT: [[ADD:%.*]] = add i32 [[SUB3]], 1
5129 // CHECK11-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1
5130 // CHECK11-NEXT: [[SUB4:%.*]] = sub i32 [[DIV]], 1
5131 // CHECK11-NEXT: store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 4
5132 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
5133 // CHECK11-NEXT: store i32 [[TMP5]], ptr [[I]], align 4
5134 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
5135 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
5136 // CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
5137 // CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
5138 // CHECK11: omp.precond.then:
5139 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
5140 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
5141 // CHECK11-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_UB]], align 4
5142 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
5143 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
5144 // CHECK11-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
5145 // CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4
5146 // CHECK11-NEXT: call void @__kmpc_for_static_init_4u(ptr @[[GLOB1]], i32 [[TMP10]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
5147 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
5148 // CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
5149 // CHECK11-NEXT: [[CMP6:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]]
5150 // CHECK11-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
5151 // CHECK11: cond.true:
5152 // CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
5153 // CHECK11-NEXT: br label [[COND_END:%.*]]
5154 // CHECK11: cond.false:
5155 // CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
5156 // CHECK11-NEXT: br label [[COND_END]]
5157 // CHECK11: cond.end:
5158 // CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ]
5159 // CHECK11-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
5160 // CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
5161 // CHECK11-NEXT: store i32 [[TMP15]], ptr [[DOTOMP_IV]], align 4
5162 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
5163 // CHECK11: omp.inner.for.cond:
5164 // CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
5165 // CHECK11-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
5166 // CHECK11-NEXT: [[ADD7:%.*]] = add i32 [[TMP17]], 1
5167 // CHECK11-NEXT: [[CMP8:%.*]] = icmp ult i32 [[TMP16]], [[ADD7]]
5168 // CHECK11-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5169 // CHECK11: omp.inner.for.body:
5170 // CHECK11-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
5171 // CHECK11-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
5172 // CHECK11-NEXT: [[MUL:%.*]] = mul i32 [[TMP19]], 1
5173 // CHECK11-NEXT: [[ADD9:%.*]] = add i32 [[TMP18]], [[MUL]]
5174 // CHECK11-NEXT: store i32 [[ADD9]], ptr [[I5]], align 4
5175 // CHECK11-NEXT: [[TMP20:%.*]] = load i32, ptr [[A_ADDR]], align 4
5176 // CHECK11-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP20]], 1
5177 // CHECK11-NEXT: store i32 [[ADD10]], ptr [[A_ADDR]], align 4
5178 // CHECK11-NEXT: [[TMP21:%.*]] = load i16, ptr [[AA_ADDR]], align 2
5179 // CHECK11-NEXT: [[CONV:%.*]] = sext i16 [[TMP21]] to i32
5180 // CHECK11-NEXT: [[ADD11:%.*]] = add nsw i32 [[CONV]], 1
5181 // CHECK11-NEXT: [[CONV12:%.*]] = trunc i32 [[ADD11]] to i16
5182 // CHECK11-NEXT: store i16 [[CONV12]], ptr [[AA_ADDR]], align 2
5183 // CHECK11-NEXT: [[TMP22:%.*]] = load i8, ptr [[AAA_ADDR]], align 1
5184 // CHECK11-NEXT: [[CONV13:%.*]] = sext i8 [[TMP22]] to i32
5185 // CHECK11-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV13]], 1
5186 // CHECK11-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i8
5187 // CHECK11-NEXT: store i8 [[CONV15]], ptr [[AAA_ADDR]], align 1
5188 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2
5189 // CHECK11-NEXT: [[TMP23:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
5190 // CHECK11-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP23]], 1
5191 // CHECK11-NEXT: store i32 [[ADD16]], ptr [[ARRAYIDX]], align 4
5192 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
5193 // CHECK11: omp.body.continue:
5194 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
5195 // CHECK11: omp.inner.for.inc:
5196 // CHECK11-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
5197 // CHECK11-NEXT: [[ADD17:%.*]] = add i32 [[TMP24]], 1
5198 // CHECK11-NEXT: store i32 [[ADD17]], ptr [[DOTOMP_IV]], align 4
5199 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]]
5200 // CHECK11: omp.inner.for.end:
5201 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
5202 // CHECK11: omp.loop.exit:
5203 // CHECK11-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
5204 // CHECK11-NEXT: [[TMP26:%.*]] = load i32, ptr [[TMP25]], align 4
5205 // CHECK11-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP26]])
5206 // CHECK11-NEXT: br label [[OMP_PRECOND_END]]
5207 // CHECK11: omp.precond.end:
5208 // CHECK11-NEXT: ret void
5211 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218
5212 // CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
5213 // CHECK11-NEXT: entry:
5214 // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
5215 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
5216 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
5217 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
5218 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
5219 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4
5220 // CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
5221 // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
5222 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
5223 // CHECK11-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4
5224 // CHECK11-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
5225 // CHECK11-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
5226 // CHECK11-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4
5227 // CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
5228 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
5229 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
5230 // CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
5231 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4
5232 // CHECK11-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4
5233 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4
5234 // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218.omp_outlined, ptr [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], ptr [[TMP3]])
5235 // CHECK11-NEXT: ret void
5238 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l218.omp_outlined
5239 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
5240 // CHECK11-NEXT: entry:
5241 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
5242 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
5243 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
5244 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
5245 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
5246 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
5247 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4
5248 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
5249 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4
5250 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
5251 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
5252 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
5253 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
5254 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4
5255 // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
5256 // CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
5257 // CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
5258 // CHECK11-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4
5259 // CHECK11-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
5260 // CHECK11-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
5261 // CHECK11-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4
5262 // CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
5263 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
5264 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
5265 // CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
5266 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
5267 // CHECK11-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
5268 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
5269 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
5270 // CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
5271 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
5272 // CHECK11-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
5273 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
5274 // CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9
5275 // CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
5276 // CHECK11: cond.true:
5277 // CHECK11-NEXT: br label [[COND_END:%.*]]
5278 // CHECK11: cond.false:
5279 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
5280 // CHECK11-NEXT: br label [[COND_END]]
5281 // CHECK11: cond.end:
5282 // CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
5283 // CHECK11-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
5284 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
5285 // CHECK11-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4
5286 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
5287 // CHECK11: omp.inner.for.cond:
5288 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
5289 // CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
5290 // CHECK11-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
5291 // CHECK11-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5292 // CHECK11: omp.inner.for.body:
5293 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
5294 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
5295 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
5296 // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4
5297 // CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[B_ADDR]], align 4
5298 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double
5299 // CHECK11-NEXT: [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00
5300 // CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0
5301 // CHECK11-NEXT: store double [[ADD4]], ptr [[A]], align 4
5302 // CHECK11-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0
5303 // CHECK11-NEXT: [[TMP13:%.*]] = load double, ptr [[A5]], align 4
5304 // CHECK11-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
5305 // CHECK11-NEXT: store double [[INC]], ptr [[A5]], align 4
5306 // CHECK11-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16
5307 // CHECK11-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]]
5308 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i32 [[TMP14]]
5309 // CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1
5310 // CHECK11-NEXT: store i16 [[CONV6]], ptr [[ARRAYIDX7]], align 2
5311 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
5312 // CHECK11: omp.body.continue:
5313 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
5314 // CHECK11: omp.inner.for.inc:
5315 // CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
5316 // CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1
5317 // CHECK11-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4
5318 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]]
5319 // CHECK11: omp.inner.for.end:
5320 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
5321 // CHECK11: omp.loop.exit:
5322 // CHECK11-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])
5323 // CHECK11-NEXT: ret void
5326 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183
5327 // CHECK11-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
5328 // CHECK11-NEXT: entry:
5329 // CHECK11-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
5330 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
5331 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
5332 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
5333 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
5334 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
5335 // CHECK11-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
5336 // CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
5337 // CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
5338 // CHECK11-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
5339 // CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
5340 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
5341 // CHECK11-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4
5342 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4
5343 // CHECK11-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
5344 // CHECK11-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
5345 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4
5346 // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], ptr [[TMP0]])
5347 // CHECK11-NEXT: ret void
5350 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l183.omp_outlined
5351 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
5352 // CHECK11-NEXT: entry:
5353 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
5354 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
5355 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
5356 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
5357 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
5358 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
5359 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4
5360 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
5361 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
5362 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
5363 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
5364 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4
5365 // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
5366 // CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
5367 // CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
5368 // CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
5369 // CHECK11-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
5370 // CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
5371 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
5372 // CHECK11-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
5373 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
5374 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
5375 // CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
5376 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
5377 // CHECK11-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
5378 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
5379 // CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
5380 // CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
5381 // CHECK11: cond.true:
5382 // CHECK11-NEXT: br label [[COND_END:%.*]]
5383 // CHECK11: cond.false:
5384 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
5385 // CHECK11-NEXT: br label [[COND_END]]
5386 // CHECK11: cond.end:
5387 // CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
5388 // CHECK11-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
5389 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
5390 // CHECK11-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
5391 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
5392 // CHECK11: omp.inner.for.cond:
5393 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
5394 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
5395 // CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
5396 // CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5397 // CHECK11: omp.inner.for.body:
5398 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
5399 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
5400 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
5401 // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4
5402 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4
5403 // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
5404 // CHECK11-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4
5405 // CHECK11-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2
5406 // CHECK11-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i32
5407 // CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1
5408 // CHECK11-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
5409 // CHECK11-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2
5410 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2
5411 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
5412 // CHECK11-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1
5413 // CHECK11-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4
5414 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
5415 // CHECK11: omp.body.continue:
5416 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
5417 // CHECK11: omp.inner.for.inc:
5418 // CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
5419 // CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP12]], 1
5420 // CHECK11-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4
5421 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]]
5422 // CHECK11: omp.inner.for.end:
5423 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
5424 // CHECK11: omp.loop.exit:
5425 // CHECK11-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])
5426 // CHECK11-NEXT: ret void