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Run DCE after a LoopFlatten test to reduce spurious output [nfc]
[llvm-project.git] / clang / test / OpenMP / target_teams_distribute_parallel_for_lastprivate_codegen.cpp
blob6142e9113660ed39b84302c19374435e719baa4e
1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
2 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1
3 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
4 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1
5 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3
6 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
7 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3
8
9 // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5
10 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
11 // RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK5
12 // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7
13 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
14 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK7
15
16 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
17 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
18 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
19 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
20 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
21 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
22
23 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
24 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
25 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
26 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
27 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
28 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
29
30 // expected-no-diagnostics
31 #ifndef HEADER
32 #define HEADER
33
34 template <class T>
35 struct S {
36 T f;
37 S(T a) : f(a) {}
38 S() : f() {}
39 operator T() { return T(); }
40 ~S() {}
41 };
42
43 template <typename T>
44 T tmain() {
45 S<T> test;
46 T t_var = T();
47 T vec[] = {1, 2};
48 S<T> s_arr[] = {1, 2};
49 S<T> &var = test;
50 #pragma omp target teams distribute parallel for lastprivate(t_var, vec, s_arr, s_arr, var, var)
51 for (int i = 0; i < 2; ++i) {
52 vec[i] = t_var;
53 s_arr[i] = var;
54 }
55 return T();
56 }
57
58 int main() {
59 static int svar;
60 volatile double g;
61 volatile double &g1 = g;
62
63 #ifdef LAMBDA
64 [&]() {
65 static float sfvar;
66
67 #pragma omp target teams distribute parallel for lastprivate(g, g1, svar, sfvar)
68 for (int i = 0; i < 2; ++i) {
69 // skip gbl and bound tid
70 // loop variables
71
72
73
74 g1 = 1;
75 svar = 3;
76 sfvar = 4.0;
77
78
79
80 // skip tid and prev variables
81 // loop variables
82
83
84
85
86
87
88
89 [&]() {
90 g = 2;
91 g1 = 2;
92 svar = 4;
93 sfvar = 8.0;
94
95 }();
96 }
97 }();
98 return 0;
99 #else
100 S<float> test;
101 int t_var = 0;
102 int vec[] = {1, 2};
103 S<float> s_arr[] = {1, 2};
104 S<float> &var = test;
105
106 #pragma omp target teams distribute parallel for lastprivate(t_var, vec, s_arr, s_arr, var, var, svar)
107 for (int i = 0; i < 2; ++i) {
108 vec[i] = t_var;
109 s_arr[i] = var;
110 }
111 int i;
112
113 return tmain<int>();
114 #endif
115 }
116
117
118 // skip loop variables
119
120 // copy from parameters to local address variables
121
122 // prepare lastprivate targets
123
124 // the distribute loop
125
126 // lastprivates
127
128
129
130 // gbl and bound tid vars, prev lb and ub vars
131
132 // skip loop variables
133
134 // copy from parameters to local address variables
135
136 // prepare lastprivate targets
137
138 // the distribute loop
139 // skip body: code generation routine is same as distribute parallel for lastprivate
140
141 // lastprivates
142
143
144 // template tmain
145
146
147 // skip alloca of global_tid and bound_tid
148 // skip loop variables
149
150 // copy from parameters to local address variables
151
152 // prepare lastprivate targets
153
154
155 // lastprivates
156
157
158 // skip alloca of global_tid and bound_tid, and prev lb and ub vars
159
160 // skip loop variables
161
162 // copy from parameters to local address variables
163
164 // prepare lastprivate targets
165
166 // skip body: code generation routine is same as distribute parallel for lastprivate
167
168 // lastprivates
169
170
171 #endif
172 // CHECK1-LABEL: define {{[^@]+}}@main
173 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
174 // CHECK1-NEXT: entry:
175 // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
176 // CHECK1-NEXT: [[G:%.*]] = alloca double, align 8
177 // CHECK1-NEXT: [[G1:%.*]] = alloca ptr, align 8
178 // CHECK1-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8
179 // CHECK1-NEXT: store i32 0, ptr [[RETVAL]], align 4
180 // CHECK1-NEXT: store ptr [[G]], ptr [[G1]], align 8
181 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0
182 // CHECK1-NEXT: store ptr [[G]], ptr [[TMP0]], align 8
183 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1
184 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[G1]], align 8
185 // CHECK1-NEXT: store ptr [[TMP2]], ptr [[TMP1]], align 8
186 // CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 8 dereferenceable(16) [[REF_TMP]])
187 // CHECK1-NEXT: ret i32 0
188 //
189 //
190 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67
191 // CHECK1-SAME: (i64 noundef [[G1:%.*]], i64 noundef [[SVAR:%.*]], i64 noundef [[SFVAR:%.*]], i64 noundef [[G:%.*]]) #[[ATTR2:[0-9]+]] {
192 // CHECK1-NEXT: entry:
193 // CHECK1-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8
194 // CHECK1-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8
195 // CHECK1-NEXT: [[SFVAR_ADDR:%.*]] = alloca i64, align 8
196 // CHECK1-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8
197 // CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8
198 // CHECK1-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8
199 // CHECK1-NEXT: [[SVAR_CASTED:%.*]] = alloca i64, align 8
200 // CHECK1-NEXT: [[SFVAR_CASTED:%.*]] = alloca i64, align 8
201 // CHECK1-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8
202 // CHECK1-NEXT: store i64 [[G1]], ptr [[G1_ADDR]], align 8
203 // CHECK1-NEXT: store i64 [[SVAR]], ptr [[SVAR_ADDR]], align 8
204 // CHECK1-NEXT: store i64 [[SFVAR]], ptr [[SFVAR_ADDR]], align 8
205 // CHECK1-NEXT: store i64 [[G]], ptr [[G_ADDR]], align 8
206 // CHECK1-NEXT: store ptr [[G1_ADDR]], ptr [[TMP]], align 8
207 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[TMP]], align 8
208 // CHECK1-NEXT: [[TMP1:%.*]] = load volatile double, ptr [[TMP0]], align 8
209 // CHECK1-NEXT: store double [[TMP1]], ptr [[G1_CASTED]], align 8
210 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[G1_CASTED]], align 8
211 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[SVAR_ADDR]], align 4
212 // CHECK1-NEXT: store i32 [[TMP3]], ptr [[SVAR_CASTED]], align 4
213 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[SVAR_CASTED]], align 8
214 // CHECK1-NEXT: [[TMP5:%.*]] = load float, ptr [[SFVAR_ADDR]], align 4
215 // CHECK1-NEXT: store float [[TMP5]], ptr [[SFVAR_CASTED]], align 4
216 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[SFVAR_CASTED]], align 8
217 // CHECK1-NEXT: [[TMP7:%.*]] = load double, ptr [[G_ADDR]], align 8
218 // CHECK1-NEXT: store double [[TMP7]], ptr [[G_CASTED]], align 8
219 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, ptr [[G_CASTED]], align 8
220 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]])
221 // CHECK1-NEXT: ret void
222 //
223 //
224 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67.omp_outlined
225 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SVAR:%.*]], i64 noundef [[SFVAR:%.*]], i64 noundef [[G:%.*]]) #[[ATTR2]] {
226 // CHECK1-NEXT: entry:
227 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
228 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
229 // CHECK1-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8
230 // CHECK1-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8
231 // CHECK1-NEXT: [[SFVAR_ADDR:%.*]] = alloca i64, align 8
232 // CHECK1-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8
233 // CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8
234 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
235 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
236 // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
237 // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
238 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
239 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
240 // CHECK1-NEXT: [[G2:%.*]] = alloca double, align 8
241 // CHECK1-NEXT: [[G13:%.*]] = alloca double, align 8
242 // CHECK1-NEXT: [[_TMP4:%.*]] = alloca ptr, align 8
243 // CHECK1-NEXT: [[SVAR5:%.*]] = alloca i32, align 4
244 // CHECK1-NEXT: [[SFVAR6:%.*]] = alloca float, align 4
245 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
246 // CHECK1-NEXT: [[G1_CASTED:%.*]] = alloca i64, align 8
247 // CHECK1-NEXT: [[SVAR_CASTED:%.*]] = alloca i64, align 8
248 // CHECK1-NEXT: [[SFVAR_CASTED:%.*]] = alloca i64, align 8
249 // CHECK1-NEXT: [[G_CASTED:%.*]] = alloca i64, align 8
250 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
251 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
252 // CHECK1-NEXT: store i64 [[G1]], ptr [[G1_ADDR]], align 8
253 // CHECK1-NEXT: store i64 [[SVAR]], ptr [[SVAR_ADDR]], align 8
254 // CHECK1-NEXT: store i64 [[SFVAR]], ptr [[SFVAR_ADDR]], align 8
255 // CHECK1-NEXT: store i64 [[G]], ptr [[G_ADDR]], align 8
256 // CHECK1-NEXT: store ptr [[G1_ADDR]], ptr [[TMP]], align 8
257 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
258 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4
259 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
260 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
261 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[TMP]], align 8
262 // CHECK1-NEXT: store ptr [[G13]], ptr [[_TMP4]], align 8
263 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
264 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
265 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
266 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
267 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 1
268 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
269 // CHECK1: cond.true:
270 // CHECK1-NEXT: br label [[COND_END:%.*]]
271 // CHECK1: cond.false:
272 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
273 // CHECK1-NEXT: br label [[COND_END]]
274 // CHECK1: cond.end:
275 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
276 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
277 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
278 // CHECK1-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
279 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
280 // CHECK1: omp.inner.for.cond:
281 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
282 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
283 // CHECK1-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
284 // CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
285 // CHECK1: omp.inner.for.body:
286 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
287 // CHECK1-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
288 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
289 // CHECK1-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
290 // CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP4]], align 8
291 // CHECK1-NEXT: [[TMP13:%.*]] = load volatile double, ptr [[TMP12]], align 8
292 // CHECK1-NEXT: store double [[TMP13]], ptr [[G1_CASTED]], align 8
293 // CHECK1-NEXT: [[TMP14:%.*]] = load i64, ptr [[G1_CASTED]], align 8
294 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[SVAR5]], align 4
295 // CHECK1-NEXT: store i32 [[TMP15]], ptr [[SVAR_CASTED]], align 4
296 // CHECK1-NEXT: [[TMP16:%.*]] = load i64, ptr [[SVAR_CASTED]], align 8
297 // CHECK1-NEXT: [[TMP17:%.*]] = load float, ptr [[SFVAR6]], align 4
298 // CHECK1-NEXT: store float [[TMP17]], ptr [[SFVAR_CASTED]], align 4
299 // CHECK1-NEXT: [[TMP18:%.*]] = load i64, ptr [[SFVAR_CASTED]], align 8
300 // CHECK1-NEXT: [[TMP19:%.*]] = load double, ptr [[G2]], align 8
301 // CHECK1-NEXT: store double [[TMP19]], ptr [[G_CASTED]], align 8
302 // CHECK1-NEXT: [[TMP20:%.*]] = load i64, ptr [[G_CASTED]], align 8
303 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67.omp_outlined.omp_outlined, i64 [[TMP9]], i64 [[TMP11]], i64 [[TMP14]], i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]])
304 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
305 // CHECK1: omp.inner.for.inc:
306 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
307 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
308 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]]
309 // CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
310 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
311 // CHECK1: omp.inner.for.end:
312 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
313 // CHECK1: omp.loop.exit:
314 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])
315 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
316 // CHECK1-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0
317 // CHECK1-NEXT: br i1 [[TMP24]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
318 // CHECK1: .omp.lastprivate.then:
319 // CHECK1-NEXT: [[TMP25:%.*]] = load double, ptr [[G2]], align 8
320 // CHECK1-NEXT: store volatile double [[TMP25]], ptr [[G_ADDR]], align 8
321 // CHECK1-NEXT: [[TMP26:%.*]] = load ptr, ptr [[_TMP4]], align 8
322 // CHECK1-NEXT: [[TMP27:%.*]] = load double, ptr [[TMP26]], align 8
323 // CHECK1-NEXT: store volatile double [[TMP27]], ptr [[TMP0]], align 8
324 // CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[SVAR5]], align 4
325 // CHECK1-NEXT: store i32 [[TMP28]], ptr [[SVAR_ADDR]], align 4
326 // CHECK1-NEXT: [[TMP29:%.*]] = load float, ptr [[SFVAR6]], align 4
327 // CHECK1-NEXT: store float [[TMP29]], ptr [[SFVAR_ADDR]], align 4
328 // CHECK1-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
329 // CHECK1: .omp.lastprivate.done:
330 // CHECK1-NEXT: ret void
331 //
332 //
333 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67.omp_outlined.omp_outlined
334 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SVAR:%.*]], i64 noundef [[SFVAR:%.*]], i64 noundef [[G:%.*]]) #[[ATTR2]] {
335 // CHECK1-NEXT: entry:
336 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
337 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
338 // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
339 // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
340 // CHECK1-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8
341 // CHECK1-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8
342 // CHECK1-NEXT: [[SFVAR_ADDR:%.*]] = alloca i64, align 8
343 // CHECK1-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8
344 // CHECK1-NEXT: [[TMP:%.*]] = alloca ptr, align 8
345 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
346 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
347 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
348 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
349 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
350 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
351 // CHECK1-NEXT: [[G3:%.*]] = alloca double, align 8
352 // CHECK1-NEXT: [[G14:%.*]] = alloca double, align 8
353 // CHECK1-NEXT: [[_TMP5:%.*]] = alloca ptr, align 8
354 // CHECK1-NEXT: [[SVAR6:%.*]] = alloca i32, align 4
355 // CHECK1-NEXT: [[SFVAR7:%.*]] = alloca float, align 4
356 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
357 // CHECK1-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8
358 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
359 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
360 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
361 // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
362 // CHECK1-NEXT: store i64 [[G1]], ptr [[G1_ADDR]], align 8
363 // CHECK1-NEXT: store i64 [[SVAR]], ptr [[SVAR_ADDR]], align 8
364 // CHECK1-NEXT: store i64 [[SFVAR]], ptr [[SFVAR_ADDR]], align 8
365 // CHECK1-NEXT: store i64 [[G]], ptr [[G_ADDR]], align 8
366 // CHECK1-NEXT: store ptr [[G1_ADDR]], ptr [[TMP]], align 8
367 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
368 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4
369 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
370 // CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
371 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
372 // CHECK1-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32
373 // CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
374 // CHECK1-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4
375 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
376 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
377 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8
378 // CHECK1-NEXT: store ptr [[G14]], ptr [[_TMP5]], align 8
379 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
380 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
381 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP4]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
382 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
383 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 1
384 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
385 // CHECK1: cond.true:
386 // CHECK1-NEXT: br label [[COND_END:%.*]]
387 // CHECK1: cond.false:
388 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
389 // CHECK1-NEXT: br label [[COND_END]]
390 // CHECK1: cond.end:
391 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]
392 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
393 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
394 // CHECK1-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
395 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
396 // CHECK1: omp.inner.for.cond:
397 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
398 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
399 // CHECK1-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
400 // CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
401 // CHECK1: omp.inner.for.body:
402 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
403 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
404 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
405 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4
406 // CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP5]], align 8
407 // CHECK1-NEXT: store volatile double 1.000000e+00, ptr [[TMP11]], align 8
408 // CHECK1-NEXT: store i32 3, ptr [[SVAR6]], align 4
409 // CHECK1-NEXT: store float 4.000000e+00, ptr [[SFVAR7]], align 4
410 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0
411 // CHECK1-NEXT: store ptr [[G3]], ptr [[TMP12]], align 8
412 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1
413 // CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[_TMP5]], align 8
414 // CHECK1-NEXT: store ptr [[TMP14]], ptr [[TMP13]], align 8
415 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2
416 // CHECK1-NEXT: store ptr [[SVAR6]], ptr [[TMP15]], align 8
417 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 3
418 // CHECK1-NEXT: store ptr [[SFVAR7]], ptr [[TMP16]], align 8
419 // CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(32) [[REF_TMP]])
420 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
421 // CHECK1: omp.body.continue:
422 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
423 // CHECK1: omp.inner.for.inc:
424 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
425 // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP17]], 1
426 // CHECK1-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4
427 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
428 // CHECK1: omp.inner.for.end:
429 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
430 // CHECK1: omp.loop.exit:
431 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP4]])
432 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
433 // CHECK1-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
434 // CHECK1-NEXT: br i1 [[TMP19]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
435 // CHECK1: .omp.lastprivate.then:
436 // CHECK1-NEXT: [[TMP20:%.*]] = load double, ptr [[G3]], align 8
437 // CHECK1-NEXT: store volatile double [[TMP20]], ptr [[G_ADDR]], align 8
438 // CHECK1-NEXT: [[TMP21:%.*]] = load ptr, ptr [[_TMP5]], align 8
439 // CHECK1-NEXT: [[TMP22:%.*]] = load double, ptr [[TMP21]], align 8
440 // CHECK1-NEXT: store volatile double [[TMP22]], ptr [[TMP2]], align 8
441 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[SVAR6]], align 4
442 // CHECK1-NEXT: store i32 [[TMP23]], ptr [[SVAR_ADDR]], align 4
443 // CHECK1-NEXT: [[TMP24:%.*]] = load float, ptr [[SFVAR7]], align 4
444 // CHECK1-NEXT: store float [[TMP24]], ptr [[SFVAR_ADDR]], align 4
445 // CHECK1-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
446 // CHECK1: .omp.lastprivate.done:
447 // CHECK1-NEXT: ret void
448 //
449 //
450 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
451 // CHECK1-SAME: () #[[ATTR4:[0-9]+]] {
452 // CHECK1-NEXT: entry:
453 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1)
454 // CHECK1-NEXT: ret void
455 //
456 //
457 // CHECK3-LABEL: define {{[^@]+}}@main
458 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] {
459 // CHECK3-NEXT: entry:
460 // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
461 // CHECK3-NEXT: [[G:%.*]] = alloca double, align 8
462 // CHECK3-NEXT: [[G1:%.*]] = alloca ptr, align 4
463 // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 4
464 // CHECK3-NEXT: store i32 0, ptr [[RETVAL]], align 4
465 // CHECK3-NEXT: store ptr [[G]], ptr [[G1]], align 4
466 // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0
467 // CHECK3-NEXT: store ptr [[G]], ptr [[TMP0]], align 4
468 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1
469 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[G1]], align 4
470 // CHECK3-NEXT: store ptr [[TMP2]], ptr [[TMP1]], align 4
471 // CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 4 dereferenceable(8) [[REF_TMP]])
472 // CHECK3-NEXT: ret i32 0
473 //
474 //
475 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67
476 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 noundef [[SVAR:%.*]], i32 noundef [[SFVAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[G:%.*]]) #[[ATTR2:[0-9]+]] {
477 // CHECK3-NEXT: entry:
478 // CHECK3-NEXT: [[G1_ADDR:%.*]] = alloca ptr, align 4
479 // CHECK3-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4
480 // CHECK3-NEXT: [[SFVAR_ADDR:%.*]] = alloca i32, align 4
481 // CHECK3-NEXT: [[G_ADDR:%.*]] = alloca ptr, align 4
482 // CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 4
483 // CHECK3-NEXT: [[SVAR_CASTED:%.*]] = alloca i32, align 4
484 // CHECK3-NEXT: [[SFVAR_CASTED:%.*]] = alloca i32, align 4
485 // CHECK3-NEXT: store ptr [[G1]], ptr [[G1_ADDR]], align 4
486 // CHECK3-NEXT: store i32 [[SVAR]], ptr [[SVAR_ADDR]], align 4
487 // CHECK3-NEXT: store i32 [[SFVAR]], ptr [[SFVAR_ADDR]], align 4
488 // CHECK3-NEXT: store ptr [[G]], ptr [[G_ADDR]], align 4
489 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G1_ADDR]], align 4
490 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G_ADDR]], align 4
491 // CHECK3-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 4
492 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 4
493 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[SVAR_ADDR]], align 4
494 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[SVAR_CASTED]], align 4
495 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[SVAR_CASTED]], align 4
496 // CHECK3-NEXT: [[TMP5:%.*]] = load float, ptr [[SFVAR_ADDR]], align 4
497 // CHECK3-NEXT: store float [[TMP5]], ptr [[SFVAR_CASTED]], align 4
498 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[SFVAR_CASTED]], align 4
499 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67.omp_outlined, ptr [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], ptr [[TMP1]])
500 // CHECK3-NEXT: ret void
501 //
502 //
503 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67.omp_outlined
504 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 noundef [[SVAR:%.*]], i32 noundef [[SFVAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[G:%.*]]) #[[ATTR2]] {
505 // CHECK3-NEXT: entry:
506 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
507 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
508 // CHECK3-NEXT: [[G1_ADDR:%.*]] = alloca ptr, align 4
509 // CHECK3-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4
510 // CHECK3-NEXT: [[SFVAR_ADDR:%.*]] = alloca i32, align 4
511 // CHECK3-NEXT: [[G_ADDR:%.*]] = alloca ptr, align 4
512 // CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 4
513 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
514 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
515 // CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
516 // CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
517 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
518 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
519 // CHECK3-NEXT: [[G2:%.*]] = alloca double, align 8
520 // CHECK3-NEXT: [[G13:%.*]] = alloca double, align 8
521 // CHECK3-NEXT: [[_TMP4:%.*]] = alloca ptr, align 4
522 // CHECK3-NEXT: [[SVAR5:%.*]] = alloca i32, align 4
523 // CHECK3-NEXT: [[SFVAR6:%.*]] = alloca float, align 4
524 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
525 // CHECK3-NEXT: [[SVAR_CASTED:%.*]] = alloca i32, align 4
526 // CHECK3-NEXT: [[SFVAR_CASTED:%.*]] = alloca i32, align 4
527 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
528 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
529 // CHECK3-NEXT: store ptr [[G1]], ptr [[G1_ADDR]], align 4
530 // CHECK3-NEXT: store i32 [[SVAR]], ptr [[SVAR_ADDR]], align 4
531 // CHECK3-NEXT: store i32 [[SFVAR]], ptr [[SFVAR_ADDR]], align 4
532 // CHECK3-NEXT: store ptr [[G]], ptr [[G_ADDR]], align 4
533 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G1_ADDR]], align 4
534 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G_ADDR]], align 4
535 // CHECK3-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 4
536 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
537 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4
538 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
539 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
540 // CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 4
541 // CHECK3-NEXT: store ptr [[G13]], ptr [[_TMP4]], align 4
542 // CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
543 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
544 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP4]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
545 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
546 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 1
547 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
548 // CHECK3: cond.true:
549 // CHECK3-NEXT: br label [[COND_END:%.*]]
550 // CHECK3: cond.false:
551 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
552 // CHECK3-NEXT: br label [[COND_END]]
553 // CHECK3: cond.end:
554 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ]
555 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
556 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
557 // CHECK3-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
558 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
559 // CHECK3: omp.inner.for.cond:
560 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
561 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
562 // CHECK3-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
563 // CHECK3-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
564 // CHECK3: omp.inner.for.body:
565 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
566 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
567 // CHECK3-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP4]], align 4
568 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[SVAR5]], align 4
569 // CHECK3-NEXT: store i32 [[TMP13]], ptr [[SVAR_CASTED]], align 4
570 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[SVAR_CASTED]], align 4
571 // CHECK3-NEXT: [[TMP15:%.*]] = load float, ptr [[SFVAR6]], align 4
572 // CHECK3-NEXT: store float [[TMP15]], ptr [[SFVAR_CASTED]], align 4
573 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[SFVAR_CASTED]], align 4
574 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67.omp_outlined.omp_outlined, i32 [[TMP10]], i32 [[TMP11]], ptr [[TMP12]], i32 [[TMP14]], i32 [[TMP16]], ptr [[G2]])
575 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
576 // CHECK3: omp.inner.for.inc:
577 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
578 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
579 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP17]], [[TMP18]]
580 // CHECK3-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
581 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
582 // CHECK3: omp.inner.for.end:
583 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
584 // CHECK3: omp.loop.exit:
585 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP4]])
586 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
587 // CHECK3-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0
588 // CHECK3-NEXT: br i1 [[TMP20]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
589 // CHECK3: .omp.lastprivate.then:
590 // CHECK3-NEXT: [[TMP21:%.*]] = load double, ptr [[G2]], align 8
591 // CHECK3-NEXT: store volatile double [[TMP21]], ptr [[TMP1]], align 8
592 // CHECK3-NEXT: [[TMP22:%.*]] = load ptr, ptr [[_TMP4]], align 4
593 // CHECK3-NEXT: [[TMP23:%.*]] = load double, ptr [[TMP22]], align 4
594 // CHECK3-NEXT: store volatile double [[TMP23]], ptr [[TMP2]], align 4
595 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, ptr [[SVAR5]], align 4
596 // CHECK3-NEXT: store i32 [[TMP24]], ptr [[SVAR_ADDR]], align 4
597 // CHECK3-NEXT: [[TMP25:%.*]] = load float, ptr [[SFVAR6]], align 4
598 // CHECK3-NEXT: store float [[TMP25]], ptr [[SFVAR_ADDR]], align 4
599 // CHECK3-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
600 // CHECK3: .omp.lastprivate.done:
601 // CHECK3-NEXT: ret void
602 //
603 //
604 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l67.omp_outlined.omp_outlined
605 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 noundef [[SVAR:%.*]], i32 noundef [[SFVAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[G:%.*]]) #[[ATTR2]] {
606 // CHECK3-NEXT: entry:
607 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
608 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
609 // CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
610 // CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
611 // CHECK3-NEXT: [[G1_ADDR:%.*]] = alloca ptr, align 4
612 // CHECK3-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4
613 // CHECK3-NEXT: [[SFVAR_ADDR:%.*]] = alloca i32, align 4
614 // CHECK3-NEXT: [[G_ADDR:%.*]] = alloca ptr, align 4
615 // CHECK3-NEXT: [[TMP:%.*]] = alloca ptr, align 4
616 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
617 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
618 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
619 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
620 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
621 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
622 // CHECK3-NEXT: [[G2:%.*]] = alloca double, align 8
623 // CHECK3-NEXT: [[G13:%.*]] = alloca double, align 8
624 // CHECK3-NEXT: [[_TMP4:%.*]] = alloca ptr, align 4
625 // CHECK3-NEXT: [[SVAR5:%.*]] = alloca i32, align 4
626 // CHECK3-NEXT: [[SFVAR6:%.*]] = alloca float, align 4
627 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
628 // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 4
629 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
630 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
631 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4
632 // CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
633 // CHECK3-NEXT: store ptr [[G1]], ptr [[G1_ADDR]], align 4
634 // CHECK3-NEXT: store i32 [[SVAR]], ptr [[SVAR_ADDR]], align 4
635 // CHECK3-NEXT: store i32 [[SFVAR]], ptr [[SFVAR_ADDR]], align 4
636 // CHECK3-NEXT: store ptr [[G]], ptr [[G_ADDR]], align 4
637 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[G1_ADDR]], align 4
638 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[G_ADDR]], align 4
639 // CHECK3-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 4
640 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
641 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4
642 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4
643 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
644 // CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTOMP_LB]], align 4
645 // CHECK3-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_UB]], align 4
646 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
647 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
648 // CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4
649 // CHECK3-NEXT: store ptr [[G13]], ptr [[_TMP4]], align 4
650 // CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
651 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
652 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP6]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
653 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
654 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 1
655 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
656 // CHECK3: cond.true:
657 // CHECK3-NEXT: br label [[COND_END:%.*]]
658 // CHECK3: cond.false:
659 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
660 // CHECK3-NEXT: br label [[COND_END]]
661 // CHECK3: cond.end:
662 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
663 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
664 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
665 // CHECK3-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4
666 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
667 // CHECK3: omp.inner.for.cond:
668 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
669 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
670 // CHECK3-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
671 // CHECK3-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
672 // CHECK3: omp.inner.for.body:
673 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
674 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
675 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
676 // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4
677 // CHECK3-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP4]], align 4
678 // CHECK3-NEXT: store volatile double 1.000000e+00, ptr [[TMP13]], align 4
679 // CHECK3-NEXT: store i32 3, ptr [[SVAR5]], align 4
680 // CHECK3-NEXT: store float 4.000000e+00, ptr [[SFVAR6]], align 4
681 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0
682 // CHECK3-NEXT: store ptr [[G2]], ptr [[TMP14]], align 4
683 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1
684 // CHECK3-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP4]], align 4
685 // CHECK3-NEXT: store ptr [[TMP16]], ptr [[TMP15]], align 4
686 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2
687 // CHECK3-NEXT: store ptr [[SVAR5]], ptr [[TMP17]], align 4
688 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 3
689 // CHECK3-NEXT: store ptr [[SFVAR6]], ptr [[TMP18]], align 4
690 // CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 4 dereferenceable(16) [[REF_TMP]])
691 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
692 // CHECK3: omp.body.continue:
693 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
694 // CHECK3: omp.inner.for.inc:
695 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
696 // CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP19]], 1
697 // CHECK3-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4
698 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
699 // CHECK3: omp.inner.for.end:
700 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
701 // CHECK3: omp.loop.exit:
702 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP6]])
703 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
704 // CHECK3-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
705 // CHECK3-NEXT: br i1 [[TMP21]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
706 // CHECK3: .omp.lastprivate.then:
707 // CHECK3-NEXT: [[TMP22:%.*]] = load double, ptr [[G2]], align 8
708 // CHECK3-NEXT: store volatile double [[TMP22]], ptr [[TMP1]], align 8
709 // CHECK3-NEXT: [[TMP23:%.*]] = load ptr, ptr [[_TMP4]], align 4
710 // CHECK3-NEXT: [[TMP24:%.*]] = load double, ptr [[TMP23]], align 4
711 // CHECK3-NEXT: store volatile double [[TMP24]], ptr [[TMP4]], align 4
712 // CHECK3-NEXT: [[TMP25:%.*]] = load i32, ptr [[SVAR5]], align 4
713 // CHECK3-NEXT: store i32 [[TMP25]], ptr [[SVAR_ADDR]], align 4
714 // CHECK3-NEXT: [[TMP26:%.*]] = load float, ptr [[SFVAR6]], align 4
715 // CHECK3-NEXT: store float [[TMP26]], ptr [[SFVAR_ADDR]], align 4
716 // CHECK3-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
717 // CHECK3: .omp.lastprivate.done:
718 // CHECK3-NEXT: ret void
719 //
720 //
721 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
722 // CHECK3-SAME: () #[[ATTR4:[0-9]+]] {
723 // CHECK3-NEXT: entry:
724 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1)
725 // CHECK3-NEXT: ret void
726 //
727 //
728 // CHECK5-LABEL: define {{[^@]+}}@main
729 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] {
730 // CHECK5-NEXT: entry:
731 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
732 // CHECK5-NEXT: [[G:%.*]] = alloca double, align 8
733 // CHECK5-NEXT: [[G1:%.*]] = alloca ptr, align 8
734 // CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4
735 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
736 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
737 // CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
738 // CHECK5-NEXT: [[VAR:%.*]] = alloca ptr, align 8
739 // CHECK5-NEXT: [[TMP:%.*]] = alloca ptr, align 8
740 // CHECK5-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
741 // CHECK5-NEXT: [[SVAR_CASTED:%.*]] = alloca i64, align 8
742 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 8
743 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 8
744 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 8
745 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
746 // CHECK5-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
747 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
748 // CHECK5-NEXT: store i32 0, ptr [[RETVAL]], align 4
749 // CHECK5-NEXT: store ptr [[G]], ptr [[G1]], align 8
750 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])
751 // CHECK5-NEXT: store i32 0, ptr [[T_VAR]], align 4
752 // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const.main.vec, i64 8, i1 false)
753 // CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 0
754 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00)
755 // CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYINIT_BEGIN]], i64 1
756 // CHECK5-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00)
757 // CHECK5-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8
758 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8
759 // CHECK5-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8
760 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4
761 // CHECK5-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4
762 // CHECK5-NEXT: [[TMP2:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8
763 // CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8
764 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr @_ZZ4mainE4svar, align 4
765 // CHECK5-NEXT: store i32 [[TMP4]], ptr [[SVAR_CASTED]], align 4
766 // CHECK5-NEXT: [[TMP5:%.*]] = load i64, ptr [[SVAR_CASTED]], align 8
767 // CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
768 // CHECK5-NEXT: store ptr [[VEC]], ptr [[TMP6]], align 8
769 // CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
770 // CHECK5-NEXT: store ptr [[VEC]], ptr [[TMP7]], align 8
771 // CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
772 // CHECK5-NEXT: store ptr null, ptr [[TMP8]], align 8
773 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
774 // CHECK5-NEXT: store i64 [[TMP2]], ptr [[TMP9]], align 8
775 // CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
776 // CHECK5-NEXT: store i64 [[TMP2]], ptr [[TMP10]], align 8
777 // CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
778 // CHECK5-NEXT: store ptr null, ptr [[TMP11]], align 8
779 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
780 // CHECK5-NEXT: store ptr [[S_ARR]], ptr [[TMP12]], align 8
781 // CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
782 // CHECK5-NEXT: store ptr [[S_ARR]], ptr [[TMP13]], align 8
783 // CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
784 // CHECK5-NEXT: store ptr null, ptr [[TMP14]], align 8
785 // CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
786 // CHECK5-NEXT: store ptr [[TMP3]], ptr [[TMP15]], align 8
787 // CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
788 // CHECK5-NEXT: store ptr [[TMP3]], ptr [[TMP16]], align 8
789 // CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
790 // CHECK5-NEXT: store ptr null, ptr [[TMP17]], align 8
791 // CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
792 // CHECK5-NEXT: store i64 [[TMP5]], ptr [[TMP18]], align 8
793 // CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4
794 // CHECK5-NEXT: store i64 [[TMP5]], ptr [[TMP19]], align 8
795 // CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
796 // CHECK5-NEXT: store ptr null, ptr [[TMP20]], align 8
797 // CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
798 // CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
799 // CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
800 // CHECK5-NEXT: store i32 2, ptr [[TMP23]], align 4
801 // CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
802 // CHECK5-NEXT: store i32 5, ptr [[TMP24]], align 4
803 // CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
804 // CHECK5-NEXT: store ptr [[TMP21]], ptr [[TMP25]], align 8
805 // CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
806 // CHECK5-NEXT: store ptr [[TMP22]], ptr [[TMP26]], align 8
807 // CHECK5-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
808 // CHECK5-NEXT: store ptr @.offload_sizes, ptr [[TMP27]], align 8
809 // CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
810 // CHECK5-NEXT: store ptr @.offload_maptypes, ptr [[TMP28]], align 8
811 // CHECK5-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
812 // CHECK5-NEXT: store ptr null, ptr [[TMP29]], align 8
813 // CHECK5-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
814 // CHECK5-NEXT: store ptr null, ptr [[TMP30]], align 8
815 // CHECK5-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
816 // CHECK5-NEXT: store i64 2, ptr [[TMP31]], align 8
817 // CHECK5-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
818 // CHECK5-NEXT: store i64 0, ptr [[TMP32]], align 8
819 // CHECK5-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
820 // CHECK5-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP33]], align 4
821 // CHECK5-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
822 // CHECK5-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP34]], align 4
823 // CHECK5-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
824 // CHECK5-NEXT: store i32 0, ptr [[TMP35]], align 4
825 // CHECK5-NEXT: [[TMP36:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106.region_id, ptr [[KERNEL_ARGS]])
826 // CHECK5-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0
827 // CHECK5-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
828 // CHECK5: omp_offload.failed:
829 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106(ptr [[VEC]], i64 [[TMP2]], ptr [[S_ARR]], ptr [[TMP3]], i64 [[TMP5]]) #[[ATTR4:[0-9]+]]
830 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]]
831 // CHECK5: omp_offload.cont:
832 // CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v()
833 // CHECK5-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
834 // CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
835 // CHECK5-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2
836 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
837 // CHECK5: arraydestroy.body:
838 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
839 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
840 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
841 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
842 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
843 // CHECK5: arraydestroy.done2:
844 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
845 // CHECK5-NEXT: [[TMP39:%.*]] = load i32, ptr [[RETVAL]], align 4
846 // CHECK5-NEXT: ret i32 [[TMP39]]
847 //
848 //
849 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
850 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
851 // CHECK5-NEXT: entry:
852 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
853 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
854 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
855 // CHECK5-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
856 // CHECK5-NEXT: ret void
857 //
858 //
859 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
860 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
861 // CHECK5-NEXT: entry:
862 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
863 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
864 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
865 // CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
866 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
867 // CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
868 // CHECK5-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
869 // CHECK5-NEXT: ret void
870 //
871 //
872 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106
873 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] {
874 // CHECK5-NEXT: entry:
875 // CHECK5-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8
876 // CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
877 // CHECK5-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8
878 // CHECK5-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8
879 // CHECK5-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8
880 // CHECK5-NEXT: [[TMP:%.*]] = alloca ptr, align 8
881 // CHECK5-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
882 // CHECK5-NEXT: [[SVAR_CASTED:%.*]] = alloca i64, align 8
883 // CHECK5-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8
884 // CHECK5-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
885 // CHECK5-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8
886 // CHECK5-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8
887 // CHECK5-NEXT: store i64 [[SVAR]], ptr [[SVAR_ADDR]], align 8
888 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8
889 // CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8
890 // CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8
891 // CHECK5-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8
892 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4
893 // CHECK5-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4
894 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8
895 // CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8
896 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[SVAR_ADDR]], align 4
897 // CHECK5-NEXT: store i32 [[TMP6]], ptr [[SVAR_CASTED]], align 4
898 // CHECK5-NEXT: [[TMP7:%.*]] = load i64, ptr [[SVAR_CASTED]], align 8
899 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106.omp_outlined, ptr [[TMP0]], i64 [[TMP4]], ptr [[TMP1]], ptr [[TMP5]], i64 [[TMP7]])
900 // CHECK5-NEXT: ret void
901 //
902 //
903 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106.omp_outlined
904 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SVAR:%.*]]) #[[ATTR3]] {
905 // CHECK5-NEXT: entry:
906 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
907 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
908 // CHECK5-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8
909 // CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
910 // CHECK5-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8
911 // CHECK5-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8
912 // CHECK5-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8
913 // CHECK5-NEXT: [[TMP:%.*]] = alloca ptr, align 8
914 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
915 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
916 // CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
917 // CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
918 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
919 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
920 // CHECK5-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4
921 // CHECK5-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4
922 // CHECK5-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4
923 // CHECK5-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4
924 // CHECK5-NEXT: [[_TMP6:%.*]] = alloca ptr, align 8
925 // CHECK5-NEXT: [[SVAR7:%.*]] = alloca i32, align 4
926 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
927 // CHECK5-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
928 // CHECK5-NEXT: [[SVAR_CASTED:%.*]] = alloca i64, align 8
929 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
930 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
931 // CHECK5-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8
932 // CHECK5-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
933 // CHECK5-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8
934 // CHECK5-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8
935 // CHECK5-NEXT: store i64 [[SVAR]], ptr [[SVAR_ADDR]], align 8
936 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8
937 // CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8
938 // CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8
939 // CHECK5-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8
940 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
941 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4
942 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
943 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
944 // CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0
945 // CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2
946 // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
947 // CHECK5: arrayctor.loop:
948 // CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
949 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
950 // CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1
951 // CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
952 // CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
953 // CHECK5: arrayctor.cont:
954 // CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8
955 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]])
956 // CHECK5-NEXT: store ptr [[VAR5]], ptr [[_TMP6]], align 8
957 // CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
958 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
959 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
960 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
961 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1
962 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
963 // CHECK5: cond.true:
964 // CHECK5-NEXT: br label [[COND_END:%.*]]
965 // CHECK5: cond.false:
966 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
967 // CHECK5-NEXT: br label [[COND_END]]
968 // CHECK5: cond.end:
969 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
970 // CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
971 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
972 // CHECK5-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4
973 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
974 // CHECK5: omp.inner.for.cond:
975 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
976 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
977 // CHECK5-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
978 // CHECK5-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
979 // CHECK5: omp.inner.for.cond.cleanup:
980 // CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
981 // CHECK5: omp.inner.for.body:
982 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
983 // CHECK5-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64
984 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
985 // CHECK5-NEXT: [[TMP14:%.*]] = zext i32 [[TMP13]] to i64
986 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR2]], align 4
987 // CHECK5-NEXT: store i32 [[TMP15]], ptr [[T_VAR_CASTED]], align 4
988 // CHECK5-NEXT: [[TMP16:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8
989 // CHECK5-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP6]], align 8
990 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, ptr [[SVAR7]], align 4
991 // CHECK5-NEXT: store i32 [[TMP18]], ptr [[SVAR_CASTED]], align 4
992 // CHECK5-NEXT: [[TMP19:%.*]] = load i64, ptr [[SVAR_CASTED]], align 8
993 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 7, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106.omp_outlined.omp_outlined, i64 [[TMP12]], i64 [[TMP14]], ptr [[VEC3]], i64 [[TMP16]], ptr [[S_ARR4]], ptr [[TMP17]], i64 [[TMP19]])
994 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
995 // CHECK5: omp.inner.for.inc:
996 // CHECK5-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
997 // CHECK5-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
998 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]
999 // CHECK5-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
1000 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]]
1001 // CHECK5: omp.inner.for.end:
1002 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1003 // CHECK5: omp.loop.exit:
1004 // CHECK5-NEXT: [[TMP22:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1005 // CHECK5-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP22]], align 4
1006 // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP23]])
1007 // CHECK5-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
1008 // CHECK5-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
1009 // CHECK5-NEXT: br i1 [[TMP25]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
1010 // CHECK5: .omp.lastprivate.then:
1011 // CHECK5-NEXT: [[TMP26:%.*]] = load i32, ptr [[T_VAR2]], align 4
1012 // CHECK5-NEXT: store i32 [[TMP26]], ptr [[T_VAR_ADDR]], align 4
1013 // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP0]], ptr align 4 [[VEC3]], i64 8, i1 false)
1014 // CHECK5-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP1]], i32 0, i32 0
1015 // CHECK5-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN9]], i64 2
1016 // CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN9]], [[TMP27]]
1017 // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE10:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
1018 // CHECK5: omp.arraycpy.body:
1019 // CHECK5-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[S_ARR4]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1020 // CHECK5-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN9]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1021 // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i64 4, i1 false)
1022 // CHECK5-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
1023 // CHECK5-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
1024 // CHECK5-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP27]]
1025 // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE10]], label [[OMP_ARRAYCPY_BODY]]
1026 // CHECK5: omp.arraycpy.done10:
1027 // CHECK5-NEXT: [[TMP28:%.*]] = load ptr, ptr [[_TMP6]], align 8
1028 // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP3]], ptr align 4 [[TMP28]], i64 4, i1 false)
1029 // CHECK5-NEXT: [[TMP29:%.*]] = load i32, ptr [[SVAR7]], align 4
1030 // CHECK5-NEXT: store i32 [[TMP29]], ptr [[SVAR_ADDR]], align 4
1031 // CHECK5-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
1032 // CHECK5: .omp.lastprivate.done:
1033 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]]
1034 // CHECK5-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0
1035 // CHECK5-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN11]], i64 2
1036 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1037 // CHECK5: arraydestroy.body:
1038 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP30]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1039 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1040 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
1041 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]]
1042 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]]
1043 // CHECK5: arraydestroy.done12:
1044 // CHECK5-NEXT: ret void
1045 //
1046 //
1047 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106.omp_outlined.omp_outlined
1048 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SVAR:%.*]]) #[[ATTR3]] {
1049 // CHECK5-NEXT: entry:
1050 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1051 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1052 // CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
1053 // CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
1054 // CHECK5-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8
1055 // CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
1056 // CHECK5-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8
1057 // CHECK5-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8
1058 // CHECK5-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8
1059 // CHECK5-NEXT: [[TMP:%.*]] = alloca ptr, align 8
1060 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1061 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
1062 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1063 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1064 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1065 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1066 // CHECK5-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4
1067 // CHECK5-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4
1068 // CHECK5-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4
1069 // CHECK5-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S:%.*]], align 4
1070 // CHECK5-NEXT: [[_TMP7:%.*]] = alloca ptr, align 8
1071 // CHECK5-NEXT: [[SVAR8:%.*]] = alloca i32, align 4
1072 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
1073 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1074 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1075 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
1076 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
1077 // CHECK5-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8
1078 // CHECK5-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
1079 // CHECK5-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8
1080 // CHECK5-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8
1081 // CHECK5-NEXT: store i64 [[SVAR]], ptr [[SVAR_ADDR]], align 8
1082 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8
1083 // CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8
1084 // CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8
1085 // CHECK5-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8
1086 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
1087 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4
1088 // CHECK5-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
1089 // CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP3]] to i32
1090 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
1091 // CHECK5-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP4]] to i32
1092 // CHECK5-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
1093 // CHECK5-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4
1094 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1095 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1096 // CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0
1097 // CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2
1098 // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
1099 // CHECK5: arrayctor.loop:
1100 // CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1101 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1102 // CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1
1103 // CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1104 // CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1105 // CHECK5: arrayctor.cont:
1106 // CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8
1107 // CHECK5-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]])
1108 // CHECK5-NEXT: store ptr [[VAR6]], ptr [[_TMP7]], align 8
1109 // CHECK5-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1110 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
1111 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP7]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
1112 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1113 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1
1114 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1115 // CHECK5: cond.true:
1116 // CHECK5-NEXT: br label [[COND_END:%.*]]
1117 // CHECK5: cond.false:
1118 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1119 // CHECK5-NEXT: br label [[COND_END]]
1120 // CHECK5: cond.end:
1121 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]
1122 // CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
1123 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1124 // CHECK5-NEXT: store i32 [[TMP10]], ptr [[DOTOMP_IV]], align 4
1125 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1126 // CHECK5: omp.inner.for.cond:
1127 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1128 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1129 // CHECK5-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]
1130 // CHECK5-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1131 // CHECK5: omp.inner.for.cond.cleanup:
1132 // CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
1133 // CHECK5: omp.inner.for.body:
1134 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1135 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1
1136 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1137 // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4
1138 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR3]], align 4
1139 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4
1140 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64
1141 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i64 0, i64 [[IDXPROM]]
1142 // CHECK5-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4
1143 // CHECK5-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP7]], align 8
1144 // CHECK5-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4
1145 // CHECK5-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP17]] to i64
1146 // CHECK5-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM10]]
1147 // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX11]], ptr align 4 [[TMP16]], i64 4, i1 false)
1148 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1149 // CHECK5: omp.body.continue:
1150 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1151 // CHECK5: omp.inner.for.inc:
1152 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1153 // CHECK5-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP18]], 1
1154 // CHECK5-NEXT: store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4
1155 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]]
1156 // CHECK5: omp.inner.for.end:
1157 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1158 // CHECK5: omp.loop.exit:
1159 // CHECK5-NEXT: [[TMP19:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1160 // CHECK5-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4
1161 // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP20]])
1162 // CHECK5-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
1163 // CHECK5-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
1164 // CHECK5-NEXT: br i1 [[TMP22]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
1165 // CHECK5: .omp.lastprivate.then:
1166 // CHECK5-NEXT: [[TMP23:%.*]] = load i32, ptr [[T_VAR3]], align 4
1167 // CHECK5-NEXT: store i32 [[TMP23]], ptr [[T_VAR_ADDR]], align 4
1168 // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP0]], ptr align 4 [[VEC4]], i64 8, i1 false)
1169 // CHECK5-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP1]], i32 0, i32 0
1170 // CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN13]], i64 2
1171 // CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN13]], [[TMP24]]
1172 // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE14:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
1173 // CHECK5: omp.arraycpy.body:
1174 // CHECK5-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[S_ARR5]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1175 // CHECK5-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN13]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1176 // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i64 4, i1 false)
1177 // CHECK5-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
1178 // CHECK5-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
1179 // CHECK5-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP24]]
1180 // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE14]], label [[OMP_ARRAYCPY_BODY]]
1181 // CHECK5: omp.arraycpy.done14:
1182 // CHECK5-NEXT: [[TMP25:%.*]] = load ptr, ptr [[_TMP7]], align 8
1183 // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP5]], ptr align 4 [[TMP25]], i64 4, i1 false)
1184 // CHECK5-NEXT: [[TMP26:%.*]] = load i32, ptr [[SVAR8]], align 4
1185 // CHECK5-NEXT: store i32 [[TMP26]], ptr [[SVAR_ADDR]], align 4
1186 // CHECK5-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
1187 // CHECK5: .omp.lastprivate.done:
1188 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]]
1189 // CHECK5-NEXT: [[ARRAY_BEGIN15:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 0
1190 // CHECK5-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN15]], i64 2
1191 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1192 // CHECK5: arraydestroy.body:
1193 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP27]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1194 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1195 // CHECK5-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
1196 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN15]]
1197 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY]]
1198 // CHECK5: arraydestroy.done16:
1199 // CHECK5-NEXT: ret void
1200 //
1201 //
1202 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
1203 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1204 // CHECK5-NEXT: entry:
1205 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
1206 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1207 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1208 // CHECK5-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
1209 // CHECK5-NEXT: ret void
1210 //
1211 //
1212 // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
1213 // CHECK5-SAME: () #[[ATTR5:[0-9]+]] comdat {
1214 // CHECK5-NEXT: entry:
1215 // CHECK5-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1216 // CHECK5-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1217 // CHECK5-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
1218 // CHECK5-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
1219 // CHECK5-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
1220 // CHECK5-NEXT: [[VAR:%.*]] = alloca ptr, align 8
1221 // CHECK5-NEXT: [[TMP:%.*]] = alloca ptr, align 8
1222 // CHECK5-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
1223 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 8
1224 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 8
1225 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 8
1226 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
1227 // CHECK5-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1228 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])
1229 // CHECK5-NEXT: store i32 0, ptr [[T_VAR]], align 4
1230 // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false)
1231 // CHECK5-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 0
1232 // CHECK5-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef signext 1)
1233 // CHECK5-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYINIT_BEGIN]], i64 1
1234 // CHECK5-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2)
1235 // CHECK5-NEXT: store ptr [[TEST]], ptr [[VAR]], align 8
1236 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8
1237 // CHECK5-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8
1238 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4
1239 // CHECK5-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4
1240 // CHECK5-NEXT: [[TMP2:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8
1241 // CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8
1242 // CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1243 // CHECK5-NEXT: store ptr [[VEC]], ptr [[TMP4]], align 8
1244 // CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1245 // CHECK5-NEXT: store ptr [[VEC]], ptr [[TMP5]], align 8
1246 // CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
1247 // CHECK5-NEXT: store ptr null, ptr [[TMP6]], align 8
1248 // CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1249 // CHECK5-NEXT: store i64 [[TMP2]], ptr [[TMP7]], align 8
1250 // CHECK5-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1251 // CHECK5-NEXT: store i64 [[TMP2]], ptr [[TMP8]], align 8
1252 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
1253 // CHECK5-NEXT: store ptr null, ptr [[TMP9]], align 8
1254 // CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1255 // CHECK5-NEXT: store ptr [[S_ARR]], ptr [[TMP10]], align 8
1256 // CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1257 // CHECK5-NEXT: store ptr [[S_ARR]], ptr [[TMP11]], align 8
1258 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
1259 // CHECK5-NEXT: store ptr null, ptr [[TMP12]], align 8
1260 // CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1261 // CHECK5-NEXT: store ptr [[TMP3]], ptr [[TMP13]], align 8
1262 // CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1263 // CHECK5-NEXT: store ptr [[TMP3]], ptr [[TMP14]], align 8
1264 // CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
1265 // CHECK5-NEXT: store ptr null, ptr [[TMP15]], align 8
1266 // CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1267 // CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1268 // CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
1269 // CHECK5-NEXT: store i32 2, ptr [[TMP18]], align 4
1270 // CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
1271 // CHECK5-NEXT: store i32 4, ptr [[TMP19]], align 4
1272 // CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
1273 // CHECK5-NEXT: store ptr [[TMP16]], ptr [[TMP20]], align 8
1274 // CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
1275 // CHECK5-NEXT: store ptr [[TMP17]], ptr [[TMP21]], align 8
1276 // CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
1277 // CHECK5-NEXT: store ptr @.offload_sizes.1, ptr [[TMP22]], align 8
1278 // CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
1279 // CHECK5-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP23]], align 8
1280 // CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
1281 // CHECK5-NEXT: store ptr null, ptr [[TMP24]], align 8
1282 // CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
1283 // CHECK5-NEXT: store ptr null, ptr [[TMP25]], align 8
1284 // CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
1285 // CHECK5-NEXT: store i64 2, ptr [[TMP26]], align 8
1286 // CHECK5-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
1287 // CHECK5-NEXT: store i64 0, ptr [[TMP27]], align 8
1288 // CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
1289 // CHECK5-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP28]], align 4
1290 // CHECK5-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
1291 // CHECK5-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP29]], align 4
1292 // CHECK5-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
1293 // CHECK5-NEXT: store i32 0, ptr [[TMP30]], align 4
1294 // CHECK5-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50.region_id, ptr [[KERNEL_ARGS]])
1295 // CHECK5-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0
1296 // CHECK5-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1297 // CHECK5: omp_offload.failed:
1298 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50(ptr [[VEC]], i64 [[TMP2]], ptr [[S_ARR]], ptr [[TMP3]]) #[[ATTR4]]
1299 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]]
1300 // CHECK5: omp_offload.cont:
1301 // CHECK5-NEXT: store i32 0, ptr [[RETVAL]], align 4
1302 // CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
1303 // CHECK5-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2
1304 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1305 // CHECK5: arraydestroy.body:
1306 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP33]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1307 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1308 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
1309 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
1310 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
1311 // CHECK5: arraydestroy.done2:
1312 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
1313 // CHECK5-NEXT: [[TMP34:%.*]] = load i32, ptr [[RETVAL]], align 4
1314 // CHECK5-NEXT: ret i32 [[TMP34]]
1315 //
1316 //
1317 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
1318 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1319 // CHECK5-NEXT: entry:
1320 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
1321 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1322 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1323 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
1324 // CHECK5-NEXT: store float 0.000000e+00, ptr [[F]], align 4
1325 // CHECK5-NEXT: ret void
1326 //
1327 //
1328 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
1329 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1330 // CHECK5-NEXT: entry:
1331 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
1332 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
1333 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1334 // CHECK5-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
1335 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1336 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
1337 // CHECK5-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
1338 // CHECK5-NEXT: store float [[TMP0]], ptr [[F]], align 4
1339 // CHECK5-NEXT: ret void
1340 //
1341 //
1342 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
1343 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1344 // CHECK5-NEXT: entry:
1345 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
1346 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1347 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1348 // CHECK5-NEXT: ret void
1349 //
1350 //
1351 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
1352 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1353 // CHECK5-NEXT: entry:
1354 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
1355 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1356 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1357 // CHECK5-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
1358 // CHECK5-NEXT: ret void
1359 //
1360 //
1361 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
1362 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1363 // CHECK5-NEXT: entry:
1364 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
1365 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
1366 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1367 // CHECK5-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
1368 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1369 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
1370 // CHECK5-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
1371 // CHECK5-NEXT: ret void
1372 //
1373 //
1374 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50
1375 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {
1376 // CHECK5-NEXT: entry:
1377 // CHECK5-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8
1378 // CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
1379 // CHECK5-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8
1380 // CHECK5-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8
1381 // CHECK5-NEXT: [[TMP:%.*]] = alloca ptr, align 8
1382 // CHECK5-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
1383 // CHECK5-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8
1384 // CHECK5-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
1385 // CHECK5-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8
1386 // CHECK5-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8
1387 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8
1388 // CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8
1389 // CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8
1390 // CHECK5-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8
1391 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4
1392 // CHECK5-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4
1393 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8
1394 // CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8
1395 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50.omp_outlined, ptr [[TMP0]], i64 [[TMP4]], ptr [[TMP1]], ptr [[TMP5]])
1396 // CHECK5-NEXT: ret void
1397 //
1398 //
1399 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50.omp_outlined
1400 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {
1401 // CHECK5-NEXT: entry:
1402 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1403 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1404 // CHECK5-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8
1405 // CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
1406 // CHECK5-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8
1407 // CHECK5-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8
1408 // CHECK5-NEXT: [[TMP:%.*]] = alloca ptr, align 8
1409 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1410 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
1411 // CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
1412 // CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
1413 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1414 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1415 // CHECK5-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4
1416 // CHECK5-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4
1417 // CHECK5-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4
1418 // CHECK5-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1419 // CHECK5-NEXT: [[_TMP6:%.*]] = alloca ptr, align 8
1420 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
1421 // CHECK5-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8
1422 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1423 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1424 // CHECK5-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8
1425 // CHECK5-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
1426 // CHECK5-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8
1427 // CHECK5-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8
1428 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8
1429 // CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8
1430 // CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8
1431 // CHECK5-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8
1432 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
1433 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4
1434 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1435 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1436 // CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0
1437 // CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2
1438 // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
1439 // CHECK5: arrayctor.loop:
1440 // CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1441 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1442 // CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i64 1
1443 // CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1444 // CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1445 // CHECK5: arrayctor.cont:
1446 // CHECK5-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8
1447 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]])
1448 // CHECK5-NEXT: store ptr [[VAR5]], ptr [[_TMP6]], align 8
1449 // CHECK5-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1450 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
1451 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
1452 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1453 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1
1454 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1455 // CHECK5: cond.true:
1456 // CHECK5-NEXT: br label [[COND_END:%.*]]
1457 // CHECK5: cond.false:
1458 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1459 // CHECK5-NEXT: br label [[COND_END]]
1460 // CHECK5: cond.end:
1461 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
1462 // CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
1463 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
1464 // CHECK5-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4
1465 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1466 // CHECK5: omp.inner.for.cond:
1467 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1468 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1469 // CHECK5-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
1470 // CHECK5-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1471 // CHECK5: omp.inner.for.cond.cleanup:
1472 // CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
1473 // CHECK5: omp.inner.for.body:
1474 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
1475 // CHECK5-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64
1476 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1477 // CHECK5-NEXT: [[TMP14:%.*]] = zext i32 [[TMP13]] to i64
1478 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR2]], align 4
1479 // CHECK5-NEXT: store i32 [[TMP15]], ptr [[T_VAR_CASTED]], align 4
1480 // CHECK5-NEXT: [[TMP16:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8
1481 // CHECK5-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP6]], align 8
1482 // CHECK5-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50.omp_outlined.omp_outlined, i64 [[TMP12]], i64 [[TMP14]], ptr [[VEC3]], i64 [[TMP16]], ptr [[S_ARR4]], ptr [[TMP17]])
1483 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1484 // CHECK5: omp.inner.for.inc:
1485 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1486 // CHECK5-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
1487 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
1488 // CHECK5-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
1489 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]]
1490 // CHECK5: omp.inner.for.end:
1491 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1492 // CHECK5: omp.loop.exit:
1493 // CHECK5-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1494 // CHECK5-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4
1495 // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP21]])
1496 // CHECK5-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
1497 // CHECK5-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
1498 // CHECK5-NEXT: br i1 [[TMP23]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
1499 // CHECK5: .omp.lastprivate.then:
1500 // CHECK5-NEXT: [[TMP24:%.*]] = load i32, ptr [[T_VAR2]], align 4
1501 // CHECK5-NEXT: store i32 [[TMP24]], ptr [[T_VAR_ADDR]], align 4
1502 // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP0]], ptr align 4 [[VEC3]], i64 8, i1 false)
1503 // CHECK5-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP1]], i32 0, i32 0
1504 // CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN8]], i64 2
1505 // CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN8]], [[TMP25]]
1506 // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE9:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
1507 // CHECK5: omp.arraycpy.body:
1508 // CHECK5-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[S_ARR4]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1509 // CHECK5-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN8]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1510 // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i64 4, i1 false)
1511 // CHECK5-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
1512 // CHECK5-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
1513 // CHECK5-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP25]]
1514 // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE9]], label [[OMP_ARRAYCPY_BODY]]
1515 // CHECK5: omp.arraycpy.done9:
1516 // CHECK5-NEXT: [[TMP26:%.*]] = load ptr, ptr [[_TMP6]], align 8
1517 // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP3]], ptr align 4 [[TMP26]], i64 4, i1 false)
1518 // CHECK5-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
1519 // CHECK5: .omp.lastprivate.done:
1520 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]]
1521 // CHECK5-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0
1522 // CHECK5-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN10]], i64 2
1523 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1524 // CHECK5: arraydestroy.body:
1525 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP27]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1526 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1527 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
1528 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]]
1529 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]]
1530 // CHECK5: arraydestroy.done11:
1531 // CHECK5-NEXT: ret void
1532 //
1533 //
1534 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50.omp_outlined.omp_outlined
1535 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {
1536 // CHECK5-NEXT: entry:
1537 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1538 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1539 // CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
1540 // CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
1541 // CHECK5-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 8
1542 // CHECK5-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8
1543 // CHECK5-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 8
1544 // CHECK5-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 8
1545 // CHECK5-NEXT: [[TMP:%.*]] = alloca ptr, align 8
1546 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1547 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
1548 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1549 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1550 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1551 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1552 // CHECK5-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4
1553 // CHECK5-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4
1554 // CHECK5-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4
1555 // CHECK5-NEXT: [[VAR6:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1556 // CHECK5-NEXT: [[_TMP7:%.*]] = alloca ptr, align 8
1557 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
1558 // CHECK5-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1559 // CHECK5-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1560 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
1561 // CHECK5-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
1562 // CHECK5-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 8
1563 // CHECK5-NEXT: store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
1564 // CHECK5-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8
1565 // CHECK5-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 8
1566 // CHECK5-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8
1567 // CHECK5-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8
1568 // CHECK5-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8
1569 // CHECK5-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 8
1570 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
1571 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4
1572 // CHECK5-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
1573 // CHECK5-NEXT: [[CONV:%.*]] = trunc i64 [[TMP3]] to i32
1574 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
1575 // CHECK5-NEXT: [[CONV2:%.*]] = trunc i64 [[TMP4]] to i32
1576 // CHECK5-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
1577 // CHECK5-NEXT: store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4
1578 // CHECK5-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1579 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1580 // CHECK5-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0
1581 // CHECK5-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2
1582 // CHECK5-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
1583 // CHECK5: arrayctor.loop:
1584 // CHECK5-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1585 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1586 // CHECK5-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i64 1
1587 // CHECK5-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1588 // CHECK5-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1589 // CHECK5: arrayctor.cont:
1590 // CHECK5-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8
1591 // CHECK5-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]])
1592 // CHECK5-NEXT: store ptr [[VAR6]], ptr [[_TMP7]], align 8
1593 // CHECK5-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1594 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
1595 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP7]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
1596 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1597 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1
1598 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1599 // CHECK5: cond.true:
1600 // CHECK5-NEXT: br label [[COND_END:%.*]]
1601 // CHECK5: cond.false:
1602 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1603 // CHECK5-NEXT: br label [[COND_END]]
1604 // CHECK5: cond.end:
1605 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]
1606 // CHECK5-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
1607 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1608 // CHECK5-NEXT: store i32 [[TMP10]], ptr [[DOTOMP_IV]], align 4
1609 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1610 // CHECK5: omp.inner.for.cond:
1611 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1612 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1613 // CHECK5-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]
1614 // CHECK5-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1615 // CHECK5: omp.inner.for.cond.cleanup:
1616 // CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
1617 // CHECK5: omp.inner.for.body:
1618 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1619 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1
1620 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1621 // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4
1622 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR3]], align 4
1623 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4
1624 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64
1625 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i64 0, i64 [[IDXPROM]]
1626 // CHECK5-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4
1627 // CHECK5-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP7]], align 8
1628 // CHECK5-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4
1629 // CHECK5-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP17]] to i64
1630 // CHECK5-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM9]]
1631 // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP16]], i64 4, i1 false)
1632 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1633 // CHECK5: omp.body.continue:
1634 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1635 // CHECK5: omp.inner.for.inc:
1636 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1637 // CHECK5-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP18]], 1
1638 // CHECK5-NEXT: store i32 [[ADD11]], ptr [[DOTOMP_IV]], align 4
1639 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]]
1640 // CHECK5: omp.inner.for.end:
1641 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1642 // CHECK5: omp.loop.exit:
1643 // CHECK5-NEXT: [[TMP19:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1644 // CHECK5-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4
1645 // CHECK5-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP20]])
1646 // CHECK5-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
1647 // CHECK5-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
1648 // CHECK5-NEXT: br i1 [[TMP22]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
1649 // CHECK5: .omp.lastprivate.then:
1650 // CHECK5-NEXT: [[TMP23:%.*]] = load i32, ptr [[T_VAR3]], align 4
1651 // CHECK5-NEXT: store i32 [[TMP23]], ptr [[T_VAR_ADDR]], align 4
1652 // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP0]], ptr align 4 [[VEC4]], i64 8, i1 false)
1653 // CHECK5-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP1]], i32 0, i32 0
1654 // CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i64 2
1655 // CHECK5-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN12]], [[TMP24]]
1656 // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE13:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
1657 // CHECK5: omp.arraycpy.body:
1658 // CHECK5-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[S_ARR5]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1659 // CHECK5-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN12]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1660 // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i64 4, i1 false)
1661 // CHECK5-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
1662 // CHECK5-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
1663 // CHECK5-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP24]]
1664 // CHECK5-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE13]], label [[OMP_ARRAYCPY_BODY]]
1665 // CHECK5: omp.arraycpy.done13:
1666 // CHECK5-NEXT: [[TMP25:%.*]] = load ptr, ptr [[_TMP7]], align 8
1667 // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP5]], ptr align 4 [[TMP25]], i64 4, i1 false)
1668 // CHECK5-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
1669 // CHECK5: .omp.lastprivate.done:
1670 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR4]]
1671 // CHECK5-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 0
1672 // CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN14]], i64 2
1673 // CHECK5-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1674 // CHECK5: arraydestroy.body:
1675 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP26]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1676 // CHECK5-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1677 // CHECK5-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
1678 // CHECK5-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]]
1679 // CHECK5-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]]
1680 // CHECK5: arraydestroy.done15:
1681 // CHECK5-NEXT: ret void
1682 //
1683 //
1684 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
1685 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1686 // CHECK5-NEXT: entry:
1687 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
1688 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1689 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1690 // CHECK5-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
1691 // CHECK5-NEXT: ret void
1692 //
1693 //
1694 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
1695 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1696 // CHECK5-NEXT: entry:
1697 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
1698 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1699 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1700 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
1701 // CHECK5-NEXT: store i32 0, ptr [[F]], align 4
1702 // CHECK5-NEXT: ret void
1703 //
1704 //
1705 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
1706 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1707 // CHECK5-NEXT: entry:
1708 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
1709 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
1710 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1711 // CHECK5-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
1712 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1713 // CHECK5-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
1714 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
1715 // CHECK5-NEXT: store i32 [[TMP0]], ptr [[F]], align 4
1716 // CHECK5-NEXT: ret void
1717 //
1718 //
1719 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
1720 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1721 // CHECK5-NEXT: entry:
1722 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
1723 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1724 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1725 // CHECK5-NEXT: ret void
1726 //
1727 //
1728 // CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
1729 // CHECK5-SAME: () #[[ATTR6:[0-9]+]] {
1730 // CHECK5-NEXT: entry:
1731 // CHECK5-NEXT: call void @__tgt_register_requires(i64 1)
1732 // CHECK5-NEXT: ret void
1733 //
1734 //
1735 // CHECK7-LABEL: define {{[^@]+}}@main
1736 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] {
1737 // CHECK7-NEXT: entry:
1738 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1739 // CHECK7-NEXT: [[G:%.*]] = alloca double, align 8
1740 // CHECK7-NEXT: [[G1:%.*]] = alloca ptr, align 4
1741 // CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4
1742 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
1743 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
1744 // CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
1745 // CHECK7-NEXT: [[VAR:%.*]] = alloca ptr, align 4
1746 // CHECK7-NEXT: [[TMP:%.*]] = alloca ptr, align 4
1747 // CHECK7-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
1748 // CHECK7-NEXT: [[SVAR_CASTED:%.*]] = alloca i32, align 4
1749 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 4
1750 // CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 4
1751 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 4
1752 // CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
1753 // CHECK7-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1754 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4
1755 // CHECK7-NEXT: store i32 0, ptr [[RETVAL]], align 4
1756 // CHECK7-NEXT: store ptr [[G]], ptr [[G1]], align 4
1757 // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])
1758 // CHECK7-NEXT: store i32 0, ptr [[T_VAR]], align 4
1759 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const.main.vec, i32 8, i1 false)
1760 // CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
1761 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float noundef 1.000000e+00)
1762 // CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYINIT_BEGIN]], i32 1
1763 // CHECK7-NEXT: call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float noundef 2.000000e+00)
1764 // CHECK7-NEXT: store ptr [[TEST]], ptr [[VAR]], align 4
1765 // CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4
1766 // CHECK7-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 4
1767 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4
1768 // CHECK7-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4
1769 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4
1770 // CHECK7-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4
1771 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr @_ZZ4mainE4svar, align 4
1772 // CHECK7-NEXT: store i32 [[TMP4]], ptr [[SVAR_CASTED]], align 4
1773 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[SVAR_CASTED]], align 4
1774 // CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1775 // CHECK7-NEXT: store ptr [[VEC]], ptr [[TMP6]], align 4
1776 // CHECK7-NEXT: [[TMP7:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1777 // CHECK7-NEXT: store ptr [[VEC]], ptr [[TMP7]], align 4
1778 // CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
1779 // CHECK7-NEXT: store ptr null, ptr [[TMP8]], align 4
1780 // CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1781 // CHECK7-NEXT: store i32 [[TMP2]], ptr [[TMP9]], align 4
1782 // CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1783 // CHECK7-NEXT: store i32 [[TMP2]], ptr [[TMP10]], align 4
1784 // CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
1785 // CHECK7-NEXT: store ptr null, ptr [[TMP11]], align 4
1786 // CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1787 // CHECK7-NEXT: store ptr [[S_ARR]], ptr [[TMP12]], align 4
1788 // CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1789 // CHECK7-NEXT: store ptr [[S_ARR]], ptr [[TMP13]], align 4
1790 // CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
1791 // CHECK7-NEXT: store ptr null, ptr [[TMP14]], align 4
1792 // CHECK7-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1793 // CHECK7-NEXT: store ptr [[TMP3]], ptr [[TMP15]], align 4
1794 // CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1795 // CHECK7-NEXT: store ptr [[TMP3]], ptr [[TMP16]], align 4
1796 // CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
1797 // CHECK7-NEXT: store ptr null, ptr [[TMP17]], align 4
1798 // CHECK7-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
1799 // CHECK7-NEXT: store i32 [[TMP5]], ptr [[TMP18]], align 4
1800 // CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4
1801 // CHECK7-NEXT: store i32 [[TMP5]], ptr [[TMP19]], align 4
1802 // CHECK7-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
1803 // CHECK7-NEXT: store ptr null, ptr [[TMP20]], align 4
1804 // CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1805 // CHECK7-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1806 // CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
1807 // CHECK7-NEXT: store i32 2, ptr [[TMP23]], align 4
1808 // CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
1809 // CHECK7-NEXT: store i32 5, ptr [[TMP24]], align 4
1810 // CHECK7-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
1811 // CHECK7-NEXT: store ptr [[TMP21]], ptr [[TMP25]], align 4
1812 // CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
1813 // CHECK7-NEXT: store ptr [[TMP22]], ptr [[TMP26]], align 4
1814 // CHECK7-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
1815 // CHECK7-NEXT: store ptr @.offload_sizes, ptr [[TMP27]], align 4
1816 // CHECK7-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
1817 // CHECK7-NEXT: store ptr @.offload_maptypes, ptr [[TMP28]], align 4
1818 // CHECK7-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
1819 // CHECK7-NEXT: store ptr null, ptr [[TMP29]], align 4
1820 // CHECK7-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
1821 // CHECK7-NEXT: store ptr null, ptr [[TMP30]], align 4
1822 // CHECK7-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
1823 // CHECK7-NEXT: store i64 2, ptr [[TMP31]], align 8
1824 // CHECK7-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
1825 // CHECK7-NEXT: store i64 0, ptr [[TMP32]], align 8
1826 // CHECK7-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
1827 // CHECK7-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP33]], align 4
1828 // CHECK7-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
1829 // CHECK7-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP34]], align 4
1830 // CHECK7-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
1831 // CHECK7-NEXT: store i32 0, ptr [[TMP35]], align 4
1832 // CHECK7-NEXT: [[TMP36:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106.region_id, ptr [[KERNEL_ARGS]])
1833 // CHECK7-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0
1834 // CHECK7-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1835 // CHECK7: omp_offload.failed:
1836 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106(ptr [[VEC]], i32 [[TMP2]], ptr [[S_ARR]], ptr [[TMP3]], i32 [[TMP5]]) #[[ATTR4:[0-9]+]]
1837 // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]]
1838 // CHECK7: omp_offload.cont:
1839 // CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()
1840 // CHECK7-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
1841 // CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
1842 // CHECK7-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2
1843 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
1844 // CHECK7: arraydestroy.body:
1845 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1846 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1847 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
1848 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
1849 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
1850 // CHECK7: arraydestroy.done2:
1851 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
1852 // CHECK7-NEXT: [[TMP39:%.*]] = load i32, ptr [[RETVAL]], align 4
1853 // CHECK7-NEXT: ret i32 [[TMP39]]
1854 //
1855 //
1856 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
1857 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
1858 // CHECK7-NEXT: entry:
1859 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
1860 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1861 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1862 // CHECK7-NEXT: call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
1863 // CHECK7-NEXT: ret void
1864 //
1865 //
1866 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
1867 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1868 // CHECK7-NEXT: entry:
1869 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
1870 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
1871 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1872 // CHECK7-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
1873 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1874 // CHECK7-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
1875 // CHECK7-NEXT: call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
1876 // CHECK7-NEXT: ret void
1877 //
1878 //
1879 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106
1880 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] {
1881 // CHECK7-NEXT: entry:
1882 // CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4
1883 // CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
1884 // CHECK7-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4
1885 // CHECK7-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4
1886 // CHECK7-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4
1887 // CHECK7-NEXT: [[TMP:%.*]] = alloca ptr, align 4
1888 // CHECK7-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
1889 // CHECK7-NEXT: [[SVAR_CASTED:%.*]] = alloca i32, align 4
1890 // CHECK7-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4
1891 // CHECK7-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4
1892 // CHECK7-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4
1893 // CHECK7-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4
1894 // CHECK7-NEXT: store i32 [[SVAR]], ptr [[SVAR_ADDR]], align 4
1895 // CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4
1896 // CHECK7-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4
1897 // CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4
1898 // CHECK7-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 4
1899 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4
1900 // CHECK7-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4
1901 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4
1902 // CHECK7-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4
1903 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[SVAR_ADDR]], align 4
1904 // CHECK7-NEXT: store i32 [[TMP6]], ptr [[SVAR_CASTED]], align 4
1905 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[SVAR_CASTED]], align 4
1906 // CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106.omp_outlined, ptr [[TMP0]], i32 [[TMP4]], ptr [[TMP1]], ptr [[TMP5]], i32 [[TMP7]])
1907 // CHECK7-NEXT: ret void
1908 //
1909 //
1910 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106.omp_outlined
1911 // CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SVAR:%.*]]) #[[ATTR3]] {
1912 // CHECK7-NEXT: entry:
1913 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
1914 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
1915 // CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4
1916 // CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
1917 // CHECK7-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4
1918 // CHECK7-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4
1919 // CHECK7-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4
1920 // CHECK7-NEXT: [[TMP:%.*]] = alloca ptr, align 4
1921 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1922 // CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
1923 // CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
1924 // CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
1925 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1926 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1927 // CHECK7-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4
1928 // CHECK7-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4
1929 // CHECK7-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4
1930 // CHECK7-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4
1931 // CHECK7-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4
1932 // CHECK7-NEXT: [[SVAR7:%.*]] = alloca i32, align 4
1933 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4
1934 // CHECK7-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
1935 // CHECK7-NEXT: [[SVAR_CASTED:%.*]] = alloca i32, align 4
1936 // CHECK7-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
1937 // CHECK7-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
1938 // CHECK7-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4
1939 // CHECK7-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4
1940 // CHECK7-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4
1941 // CHECK7-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4
1942 // CHECK7-NEXT: store i32 [[SVAR]], ptr [[SVAR_ADDR]], align 4
1943 // CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4
1944 // CHECK7-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4
1945 // CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4
1946 // CHECK7-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 4
1947 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
1948 // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4
1949 // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1950 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1951 // CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0
1952 // CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2
1953 // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
1954 // CHECK7: arrayctor.loop:
1955 // CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1956 // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1957 // CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i32 1
1958 // CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1959 // CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1960 // CHECK7: arrayctor.cont:
1961 // CHECK7-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4
1962 // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]])
1963 // CHECK7-NEXT: store ptr [[VAR5]], ptr [[_TMP6]], align 4
1964 // CHECK7-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
1965 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
1966 // CHECK7-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
1967 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1968 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1
1969 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1970 // CHECK7: cond.true:
1971 // CHECK7-NEXT: br label [[COND_END:%.*]]
1972 // CHECK7: cond.false:
1973 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1974 // CHECK7-NEXT: br label [[COND_END]]
1975 // CHECK7: cond.end:
1976 // CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
1977 // CHECK7-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
1978 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
1979 // CHECK7-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4
1980 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1981 // CHECK7: omp.inner.for.cond:
1982 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1983 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1984 // CHECK7-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
1985 // CHECK7-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1986 // CHECK7: omp.inner.for.cond.cleanup:
1987 // CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
1988 // CHECK7: omp.inner.for.body:
1989 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
1990 // CHECK7-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1991 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, ptr [[T_VAR2]], align 4
1992 // CHECK7-NEXT: store i32 [[TMP13]], ptr [[T_VAR_CASTED]], align 4
1993 // CHECK7-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4
1994 // CHECK7-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP6]], align 4
1995 // CHECK7-NEXT: [[TMP16:%.*]] = load i32, ptr [[SVAR7]], align 4
1996 // CHECK7-NEXT: store i32 [[TMP16]], ptr [[SVAR_CASTED]], align 4
1997 // CHECK7-NEXT: [[TMP17:%.*]] = load i32, ptr [[SVAR_CASTED]], align 4
1998 // CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 7, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106.omp_outlined.omp_outlined, i32 [[TMP11]], i32 [[TMP12]], ptr [[VEC3]], i32 [[TMP14]], ptr [[S_ARR4]], ptr [[TMP15]], i32 [[TMP17]])
1999 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2000 // CHECK7: omp.inner.for.inc:
2001 // CHECK7-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2002 // CHECK7-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
2003 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
2004 // CHECK7-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
2005 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]]
2006 // CHECK7: omp.inner.for.end:
2007 // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2008 // CHECK7: omp.loop.exit:
2009 // CHECK7-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
2010 // CHECK7-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4
2011 // CHECK7-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP21]])
2012 // CHECK7-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
2013 // CHECK7-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
2014 // CHECK7-NEXT: br i1 [[TMP23]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
2015 // CHECK7: .omp.lastprivate.then:
2016 // CHECK7-NEXT: [[TMP24:%.*]] = load i32, ptr [[T_VAR2]], align 4
2017 // CHECK7-NEXT: store i32 [[TMP24]], ptr [[T_VAR_ADDR]], align 4
2018 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP0]], ptr align 4 [[VEC3]], i32 8, i1 false)
2019 // CHECK7-NEXT: [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP1]], i32 0, i32 0
2020 // CHECK7-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN9]], i32 2
2021 // CHECK7-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN9]], [[TMP25]]
2022 // CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE10:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
2023 // CHECK7: omp.arraycpy.body:
2024 // CHECK7-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[S_ARR4]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2025 // CHECK7-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN9]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2026 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 4, i1 false)
2027 // CHECK7-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
2028 // CHECK7-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
2029 // CHECK7-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP25]]
2030 // CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE10]], label [[OMP_ARRAYCPY_BODY]]
2031 // CHECK7: omp.arraycpy.done10:
2032 // CHECK7-NEXT: [[TMP26:%.*]] = load ptr, ptr [[_TMP6]], align 4
2033 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP3]], ptr align 4 [[TMP26]], i32 4, i1 false)
2034 // CHECK7-NEXT: [[TMP27:%.*]] = load i32, ptr [[SVAR7]], align 4
2035 // CHECK7-NEXT: store i32 [[TMP27]], ptr [[SVAR_ADDR]], align 4
2036 // CHECK7-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
2037 // CHECK7: .omp.lastprivate.done:
2038 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]]
2039 // CHECK7-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0
2040 // CHECK7-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN11]], i32 2
2041 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2042 // CHECK7: arraydestroy.body:
2043 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP28]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2044 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2045 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
2046 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]]
2047 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]]
2048 // CHECK7: arraydestroy.done12:
2049 // CHECK7-NEXT: ret void
2050 //
2051 //
2052 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l106.omp_outlined.omp_outlined
2053 // CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SVAR:%.*]]) #[[ATTR3]] {
2054 // CHECK7-NEXT: entry:
2055 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
2056 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
2057 // CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
2058 // CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
2059 // CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4
2060 // CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
2061 // CHECK7-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4
2062 // CHECK7-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4
2063 // CHECK7-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4
2064 // CHECK7-NEXT: [[TMP:%.*]] = alloca ptr, align 4
2065 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2066 // CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
2067 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
2068 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
2069 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2070 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2071 // CHECK7-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4
2072 // CHECK7-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4
2073 // CHECK7-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S], align 4
2074 // CHECK7-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4
2075 // CHECK7-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4
2076 // CHECK7-NEXT: [[SVAR7:%.*]] = alloca i32, align 4
2077 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4
2078 // CHECK7-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
2079 // CHECK7-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
2080 // CHECK7-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4
2081 // CHECK7-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
2082 // CHECK7-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4
2083 // CHECK7-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4
2084 // CHECK7-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4
2085 // CHECK7-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4
2086 // CHECK7-NEXT: store i32 [[SVAR]], ptr [[SVAR_ADDR]], align 4
2087 // CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4
2088 // CHECK7-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4
2089 // CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4
2090 // CHECK7-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 4
2091 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
2092 // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4
2093 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4
2094 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
2095 // CHECK7-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_LB]], align 4
2096 // CHECK7-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4
2097 // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
2098 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2099 // CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0
2100 // CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2
2101 // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
2102 // CHECK7: arrayctor.loop:
2103 // CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
2104 // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
2105 // CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i32 1
2106 // CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
2107 // CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
2108 // CHECK7: arrayctor.cont:
2109 // CHECK7-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4
2110 // CHECK7-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]])
2111 // CHECK7-NEXT: store ptr [[VAR5]], ptr [[_TMP6]], align 4
2112 // CHECK7-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
2113 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
2114 // CHECK7-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP7]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
2115 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2116 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1
2117 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2118 // CHECK7: cond.true:
2119 // CHECK7-NEXT: br label [[COND_END:%.*]]
2120 // CHECK7: cond.false:
2121 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2122 // CHECK7-NEXT: br label [[COND_END]]
2123 // CHECK7: cond.end:
2124 // CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]
2125 // CHECK7-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
2126 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
2127 // CHECK7-NEXT: store i32 [[TMP10]], ptr [[DOTOMP_IV]], align 4
2128 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2129 // CHECK7: omp.inner.for.cond:
2130 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2131 // CHECK7-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2132 // CHECK7-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]
2133 // CHECK7-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2134 // CHECK7: omp.inner.for.cond.cleanup:
2135 // CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
2136 // CHECK7: omp.inner.for.body:
2137 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2138 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1
2139 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2140 // CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4
2141 // CHECK7-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR2]], align 4
2142 // CHECK7-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4
2143 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i32 0, i32 [[TMP15]]
2144 // CHECK7-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4
2145 // CHECK7-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP6]], align 4
2146 // CHECK7-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4
2147 // CHECK7-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 [[TMP17]]
2148 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP16]], i32 4, i1 false)
2149 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2150 // CHECK7: omp.body.continue:
2151 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2152 // CHECK7: omp.inner.for.inc:
2153 // CHECK7-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2154 // CHECK7-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP18]], 1
2155 // CHECK7-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4
2156 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]]
2157 // CHECK7: omp.inner.for.end:
2158 // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2159 // CHECK7: omp.loop.exit:
2160 // CHECK7-NEXT: [[TMP19:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
2161 // CHECK7-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4
2162 // CHECK7-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP20]])
2163 // CHECK7-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
2164 // CHECK7-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
2165 // CHECK7-NEXT: br i1 [[TMP22]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
2166 // CHECK7: .omp.lastprivate.then:
2167 // CHECK7-NEXT: [[TMP23:%.*]] = load i32, ptr [[T_VAR2]], align 4
2168 // CHECK7-NEXT: store i32 [[TMP23]], ptr [[T_VAR_ADDR]], align 4
2169 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP0]], ptr align 4 [[VEC3]], i32 8, i1 false)
2170 // CHECK7-NEXT: [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP1]], i32 0, i32 0
2171 // CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN11]], i32 2
2172 // CHECK7-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN11]], [[TMP24]]
2173 // CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE12:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
2174 // CHECK7: omp.arraycpy.body:
2175 // CHECK7-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[S_ARR4]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2176 // CHECK7-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN11]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2177 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 4, i1 false)
2178 // CHECK7-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
2179 // CHECK7-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
2180 // CHECK7-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP24]]
2181 // CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE12]], label [[OMP_ARRAYCPY_BODY]]
2182 // CHECK7: omp.arraycpy.done12:
2183 // CHECK7-NEXT: [[TMP25:%.*]] = load ptr, ptr [[_TMP6]], align 4
2184 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP5]], ptr align 4 [[TMP25]], i32 4, i1 false)
2185 // CHECK7-NEXT: [[TMP26:%.*]] = load i32, ptr [[SVAR7]], align 4
2186 // CHECK7-NEXT: store i32 [[TMP26]], ptr [[SVAR_ADDR]], align 4
2187 // CHECK7-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
2188 // CHECK7: .omp.lastprivate.done:
2189 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]]
2190 // CHECK7-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 0
2191 // CHECK7-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN13]], i32 2
2192 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2193 // CHECK7: arraydestroy.body:
2194 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP27]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2195 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2196 // CHECK7-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
2197 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]]
2198 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]]
2199 // CHECK7: arraydestroy.done14:
2200 // CHECK7-NEXT: ret void
2201 //
2202 //
2203 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
2204 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2205 // CHECK7-NEXT: entry:
2206 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
2207 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2208 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2209 // CHECK7-NEXT: call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
2210 // CHECK7-NEXT: ret void
2211 //
2212 //
2213 // CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
2214 // CHECK7-SAME: () #[[ATTR5:[0-9]+]] comdat {
2215 // CHECK7-NEXT: entry:
2216 // CHECK7-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
2217 // CHECK7-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
2218 // CHECK7-NEXT: [[T_VAR:%.*]] = alloca i32, align 4
2219 // CHECK7-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4
2220 // CHECK7-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
2221 // CHECK7-NEXT: [[VAR:%.*]] = alloca ptr, align 4
2222 // CHECK7-NEXT: [[TMP:%.*]] = alloca ptr, align 4
2223 // CHECK7-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
2224 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 4
2225 // CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 4
2226 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 4
2227 // CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
2228 // CHECK7-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
2229 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])
2230 // CHECK7-NEXT: store i32 0, ptr [[T_VAR]], align 4
2231 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false)
2232 // CHECK7-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
2233 // CHECK7-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef 1)
2234 // CHECK7-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYINIT_BEGIN]], i32 1
2235 // CHECK7-NEXT: call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)
2236 // CHECK7-NEXT: store ptr [[TEST]], ptr [[VAR]], align 4
2237 // CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4
2238 // CHECK7-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 4
2239 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4
2240 // CHECK7-NEXT: store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4
2241 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4
2242 // CHECK7-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4
2243 // CHECK7-NEXT: [[TMP4:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2244 // CHECK7-NEXT: store ptr [[VEC]], ptr [[TMP4]], align 4
2245 // CHECK7-NEXT: [[TMP5:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2246 // CHECK7-NEXT: store ptr [[VEC]], ptr [[TMP5]], align 4
2247 // CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
2248 // CHECK7-NEXT: store ptr null, ptr [[TMP6]], align 4
2249 // CHECK7-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
2250 // CHECK7-NEXT: store i32 [[TMP2]], ptr [[TMP7]], align 4
2251 // CHECK7-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
2252 // CHECK7-NEXT: store i32 [[TMP2]], ptr [[TMP8]], align 4
2253 // CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
2254 // CHECK7-NEXT: store ptr null, ptr [[TMP9]], align 4
2255 // CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
2256 // CHECK7-NEXT: store ptr [[S_ARR]], ptr [[TMP10]], align 4
2257 // CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
2258 // CHECK7-NEXT: store ptr [[S_ARR]], ptr [[TMP11]], align 4
2259 // CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
2260 // CHECK7-NEXT: store ptr null, ptr [[TMP12]], align 4
2261 // CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
2262 // CHECK7-NEXT: store ptr [[TMP3]], ptr [[TMP13]], align 4
2263 // CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
2264 // CHECK7-NEXT: store ptr [[TMP3]], ptr [[TMP14]], align 4
2265 // CHECK7-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
2266 // CHECK7-NEXT: store ptr null, ptr [[TMP15]], align 4
2267 // CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2268 // CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2269 // CHECK7-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
2270 // CHECK7-NEXT: store i32 2, ptr [[TMP18]], align 4
2271 // CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
2272 // CHECK7-NEXT: store i32 4, ptr [[TMP19]], align 4
2273 // CHECK7-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
2274 // CHECK7-NEXT: store ptr [[TMP16]], ptr [[TMP20]], align 4
2275 // CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
2276 // CHECK7-NEXT: store ptr [[TMP17]], ptr [[TMP21]], align 4
2277 // CHECK7-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
2278 // CHECK7-NEXT: store ptr @.offload_sizes.1, ptr [[TMP22]], align 4
2279 // CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
2280 // CHECK7-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP23]], align 4
2281 // CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
2282 // CHECK7-NEXT: store ptr null, ptr [[TMP24]], align 4
2283 // CHECK7-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
2284 // CHECK7-NEXT: store ptr null, ptr [[TMP25]], align 4
2285 // CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
2286 // CHECK7-NEXT: store i64 2, ptr [[TMP26]], align 8
2287 // CHECK7-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
2288 // CHECK7-NEXT: store i64 0, ptr [[TMP27]], align 8
2289 // CHECK7-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
2290 // CHECK7-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP28]], align 4
2291 // CHECK7-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
2292 // CHECK7-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP29]], align 4
2293 // CHECK7-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
2294 // CHECK7-NEXT: store i32 0, ptr [[TMP30]], align 4
2295 // CHECK7-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50.region_id, ptr [[KERNEL_ARGS]])
2296 // CHECK7-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0
2297 // CHECK7-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
2298 // CHECK7: omp_offload.failed:
2299 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50(ptr [[VEC]], i32 [[TMP2]], ptr [[S_ARR]], ptr [[TMP3]]) #[[ATTR4]]
2300 // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]]
2301 // CHECK7: omp_offload.cont:
2302 // CHECK7-NEXT: store i32 0, ptr [[RETVAL]], align 4
2303 // CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
2304 // CHECK7-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2
2305 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2306 // CHECK7: arraydestroy.body:
2307 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP33]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2308 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2309 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
2310 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
2311 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
2312 // CHECK7: arraydestroy.done2:
2313 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
2314 // CHECK7-NEXT: [[TMP34:%.*]] = load i32, ptr [[RETVAL]], align 4
2315 // CHECK7-NEXT: ret i32 [[TMP34]]
2316 //
2317 //
2318 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
2319 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2320 // CHECK7-NEXT: entry:
2321 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
2322 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2323 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2324 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
2325 // CHECK7-NEXT: store float 0.000000e+00, ptr [[F]], align 4
2326 // CHECK7-NEXT: ret void
2327 //
2328 //
2329 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
2330 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2331 // CHECK7-NEXT: entry:
2332 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
2333 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float, align 4
2334 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2335 // CHECK7-NEXT: store float [[A]], ptr [[A_ADDR]], align 4
2336 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2337 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
2338 // CHECK7-NEXT: [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
2339 // CHECK7-NEXT: store float [[TMP0]], ptr [[F]], align 4
2340 // CHECK7-NEXT: ret void
2341 //
2342 //
2343 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
2344 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2345 // CHECK7-NEXT: entry:
2346 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
2347 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2348 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2349 // CHECK7-NEXT: ret void
2350 //
2351 //
2352 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
2353 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2354 // CHECK7-NEXT: entry:
2355 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
2356 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2357 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2358 // CHECK7-NEXT: call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
2359 // CHECK7-NEXT: ret void
2360 //
2361 //
2362 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
2363 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2364 // CHECK7-NEXT: entry:
2365 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
2366 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
2367 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2368 // CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
2369 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2370 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
2371 // CHECK7-NEXT: call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])
2372 // CHECK7-NEXT: ret void
2373 //
2374 //
2375 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50
2376 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {
2377 // CHECK7-NEXT: entry:
2378 // CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4
2379 // CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
2380 // CHECK7-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4
2381 // CHECK7-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4
2382 // CHECK7-NEXT: [[TMP:%.*]] = alloca ptr, align 4
2383 // CHECK7-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
2384 // CHECK7-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4
2385 // CHECK7-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4
2386 // CHECK7-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4
2387 // CHECK7-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4
2388 // CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4
2389 // CHECK7-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4
2390 // CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4
2391 // CHECK7-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 4
2392 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4
2393 // CHECK7-NEXT: store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4
2394 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4
2395 // CHECK7-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4
2396 // CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50.omp_outlined, ptr [[TMP0]], i32 [[TMP4]], ptr [[TMP1]], ptr [[TMP5]])
2397 // CHECK7-NEXT: ret void
2398 //
2399 //
2400 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50.omp_outlined
2401 // CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {
2402 // CHECK7-NEXT: entry:
2403 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
2404 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
2405 // CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4
2406 // CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
2407 // CHECK7-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4
2408 // CHECK7-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4
2409 // CHECK7-NEXT: [[TMP:%.*]] = alloca ptr, align 4
2410 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2411 // CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
2412 // CHECK7-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
2413 // CHECK7-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
2414 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2415 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2416 // CHECK7-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4
2417 // CHECK7-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4
2418 // CHECK7-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4
2419 // CHECK7-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
2420 // CHECK7-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4
2421 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4
2422 // CHECK7-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4
2423 // CHECK7-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
2424 // CHECK7-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
2425 // CHECK7-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4
2426 // CHECK7-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4
2427 // CHECK7-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4
2428 // CHECK7-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4
2429 // CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4
2430 // CHECK7-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4
2431 // CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4
2432 // CHECK7-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 4
2433 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
2434 // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_COMB_UB]], align 4
2435 // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
2436 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2437 // CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0
2438 // CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2
2439 // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
2440 // CHECK7: arrayctor.loop:
2441 // CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
2442 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
2443 // CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i32 1
2444 // CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
2445 // CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
2446 // CHECK7: arrayctor.cont:
2447 // CHECK7-NEXT: [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4
2448 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]])
2449 // CHECK7-NEXT: store ptr [[VAR5]], ptr [[_TMP6]], align 4
2450 // CHECK7-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
2451 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
2452 // CHECK7-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
2453 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2454 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1
2455 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2456 // CHECK7: cond.true:
2457 // CHECK7-NEXT: br label [[COND_END:%.*]]
2458 // CHECK7: cond.false:
2459 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2460 // CHECK7-NEXT: br label [[COND_END]]
2461 // CHECK7: cond.end:
2462 // CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
2463 // CHECK7-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
2464 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
2465 // CHECK7-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4
2466 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2467 // CHECK7: omp.inner.for.cond:
2468 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2469 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2470 // CHECK7-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
2471 // CHECK7-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2472 // CHECK7: omp.inner.for.cond.cleanup:
2473 // CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
2474 // CHECK7: omp.inner.for.body:
2475 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
2476 // CHECK7-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2477 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, ptr [[T_VAR2]], align 4
2478 // CHECK7-NEXT: store i32 [[TMP13]], ptr [[T_VAR_CASTED]], align 4
2479 // CHECK7-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4
2480 // CHECK7-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP6]], align 4
2481 // CHECK7-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50.omp_outlined.omp_outlined, i32 [[TMP11]], i32 [[TMP12]], ptr [[VEC3]], i32 [[TMP14]], ptr [[S_ARR4]], ptr [[TMP15]])
2482 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2483 // CHECK7: omp.inner.for.inc:
2484 // CHECK7-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2485 // CHECK7-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
2486 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
2487 // CHECK7-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
2488 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]]
2489 // CHECK7: omp.inner.for.end:
2490 // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2491 // CHECK7: omp.loop.exit:
2492 // CHECK7-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
2493 // CHECK7-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4
2494 // CHECK7-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP19]])
2495 // CHECK7-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
2496 // CHECK7-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
2497 // CHECK7-NEXT: br i1 [[TMP21]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
2498 // CHECK7: .omp.lastprivate.then:
2499 // CHECK7-NEXT: [[TMP22:%.*]] = load i32, ptr [[T_VAR2]], align 4
2500 // CHECK7-NEXT: store i32 [[TMP22]], ptr [[T_VAR_ADDR]], align 4
2501 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP0]], ptr align 4 [[VEC3]], i32 8, i1 false)
2502 // CHECK7-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP1]], i32 0, i32 0
2503 // CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN8]], i32 2
2504 // CHECK7-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN8]], [[TMP23]]
2505 // CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE9:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
2506 // CHECK7: omp.arraycpy.body:
2507 // CHECK7-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[S_ARR4]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2508 // CHECK7-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN8]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2509 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 4, i1 false)
2510 // CHECK7-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
2511 // CHECK7-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
2512 // CHECK7-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP23]]
2513 // CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE9]], label [[OMP_ARRAYCPY_BODY]]
2514 // CHECK7: omp.arraycpy.done9:
2515 // CHECK7-NEXT: [[TMP24:%.*]] = load ptr, ptr [[_TMP6]], align 4
2516 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP3]], ptr align 4 [[TMP24]], i32 4, i1 false)
2517 // CHECK7-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
2518 // CHECK7: .omp.lastprivate.done:
2519 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]]
2520 // CHECK7-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0
2521 // CHECK7-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN10]], i32 2
2522 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2523 // CHECK7: arraydestroy.body:
2524 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP25]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2525 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2526 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
2527 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]]
2528 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]]
2529 // CHECK7: arraydestroy.done11:
2530 // CHECK7-NEXT: ret void
2531 //
2532 //
2533 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l50.omp_outlined.omp_outlined
2534 // CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] {
2535 // CHECK7-NEXT: entry:
2536 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
2537 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
2538 // CHECK7-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
2539 // CHECK7-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
2540 // CHECK7-NEXT: [[VEC_ADDR:%.*]] = alloca ptr, align 4
2541 // CHECK7-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4
2542 // CHECK7-NEXT: [[S_ARR_ADDR:%.*]] = alloca ptr, align 4
2543 // CHECK7-NEXT: [[VAR_ADDR:%.*]] = alloca ptr, align 4
2544 // CHECK7-NEXT: [[TMP:%.*]] = alloca ptr, align 4
2545 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
2546 // CHECK7-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
2547 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
2548 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
2549 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2550 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2551 // CHECK7-NEXT: [[T_VAR2:%.*]] = alloca i32, align 4
2552 // CHECK7-NEXT: [[VEC3:%.*]] = alloca [2 x i32], align 4
2553 // CHECK7-NEXT: [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4
2554 // CHECK7-NEXT: [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
2555 // CHECK7-NEXT: [[_TMP6:%.*]] = alloca ptr, align 4
2556 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4
2557 // CHECK7-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
2558 // CHECK7-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
2559 // CHECK7-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4
2560 // CHECK7-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
2561 // CHECK7-NEXT: store ptr [[VEC]], ptr [[VEC_ADDR]], align 4
2562 // CHECK7-NEXT: store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4
2563 // CHECK7-NEXT: store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4
2564 // CHECK7-NEXT: store ptr [[VAR]], ptr [[VAR_ADDR]], align 4
2565 // CHECK7-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4
2566 // CHECK7-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4
2567 // CHECK7-NEXT: [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4
2568 // CHECK7-NEXT: store ptr [[TMP2]], ptr [[TMP]], align 4
2569 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
2570 // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4
2571 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4
2572 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
2573 // CHECK7-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_LB]], align 4
2574 // CHECK7-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4
2575 // CHECK7-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
2576 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2577 // CHECK7-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0
2578 // CHECK7-NEXT: [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2
2579 // CHECK7-NEXT: br label [[ARRAYCTOR_LOOP:%.*]]
2580 // CHECK7: arrayctor.loop:
2581 // CHECK7-NEXT: [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
2582 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
2583 // CHECK7-NEXT: [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i32 1
2584 // CHECK7-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
2585 // CHECK7-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
2586 // CHECK7: arrayctor.cont:
2587 // CHECK7-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4
2588 // CHECK7-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]])
2589 // CHECK7-NEXT: store ptr [[VAR5]], ptr [[_TMP6]], align 4
2590 // CHECK7-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
2591 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
2592 // CHECK7-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP7]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
2593 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2594 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1
2595 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2596 // CHECK7: cond.true:
2597 // CHECK7-NEXT: br label [[COND_END:%.*]]
2598 // CHECK7: cond.false:
2599 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2600 // CHECK7-NEXT: br label [[COND_END]]
2601 // CHECK7: cond.end:
2602 // CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]
2603 // CHECK7-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
2604 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
2605 // CHECK7-NEXT: store i32 [[TMP10]], ptr [[DOTOMP_IV]], align 4
2606 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
2607 // CHECK7: omp.inner.for.cond:
2608 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2609 // CHECK7-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2610 // CHECK7-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]
2611 // CHECK7-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2612 // CHECK7: omp.inner.for.cond.cleanup:
2613 // CHECK7-NEXT: br label [[OMP_INNER_FOR_END:%.*]]
2614 // CHECK7: omp.inner.for.body:
2615 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2616 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1
2617 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2618 // CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4
2619 // CHECK7-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR2]], align 4
2620 // CHECK7-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4
2621 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i32 0, i32 [[TMP15]]
2622 // CHECK7-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4
2623 // CHECK7-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP6]], align 4
2624 // CHECK7-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4
2625 // CHECK7-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 [[TMP17]]
2626 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP16]], i32 4, i1 false)
2627 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
2628 // CHECK7: omp.body.continue:
2629 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
2630 // CHECK7: omp.inner.for.inc:
2631 // CHECK7-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2632 // CHECK7-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP18]], 1
2633 // CHECK7-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4
2634 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]]
2635 // CHECK7: omp.inner.for.end:
2636 // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
2637 // CHECK7: omp.loop.exit:
2638 // CHECK7-NEXT: [[TMP19:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
2639 // CHECK7-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4
2640 // CHECK7-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP20]])
2641 // CHECK7-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
2642 // CHECK7-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
2643 // CHECK7-NEXT: br i1 [[TMP22]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
2644 // CHECK7: .omp.lastprivate.then:
2645 // CHECK7-NEXT: [[TMP23:%.*]] = load i32, ptr [[T_VAR2]], align 4
2646 // CHECK7-NEXT: store i32 [[TMP23]], ptr [[T_VAR_ADDR]], align 4
2647 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP0]], ptr align 4 [[VEC3]], i32 8, i1 false)
2648 // CHECK7-NEXT: [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP1]], i32 0, i32 0
2649 // CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN10]], i32 2
2650 // CHECK7-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN10]], [[TMP24]]
2651 // CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE11:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
2652 // CHECK7: omp.arraycpy.body:
2653 // CHECK7-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[S_ARR4]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2654 // CHECK7-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN10]], [[DOTOMP_LASTPRIVATE_THEN]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2655 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr align 4 [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 4, i1 false)
2656 // CHECK7-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
2657 // CHECK7-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
2658 // CHECK7-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP24]]
2659 // CHECK7-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE11]], label [[OMP_ARRAYCPY_BODY]]
2660 // CHECK7: omp.arraycpy.done11:
2661 // CHECK7-NEXT: [[TMP25:%.*]] = load ptr, ptr [[_TMP6]], align 4
2662 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP5]], ptr align 4 [[TMP25]], i32 4, i1 false)
2663 // CHECK7-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
2664 // CHECK7: .omp.lastprivate.done:
2665 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR4]]
2666 // CHECK7-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0
2667 // CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i32 2
2668 // CHECK7-NEXT: br label [[ARRAYDESTROY_BODY:%.*]]
2669 // CHECK7: arraydestroy.body:
2670 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP26]], [[DOTOMP_LASTPRIVATE_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2671 // CHECK7-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2672 // CHECK7-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
2673 // CHECK7-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]]
2674 // CHECK7-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]]
2675 // CHECK7: arraydestroy.done13:
2676 // CHECK7-NEXT: ret void
2677 //
2678 //
2679 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
2680 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2681 // CHECK7-NEXT: entry:
2682 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
2683 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2684 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2685 // CHECK7-NEXT: call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
2686 // CHECK7-NEXT: ret void
2687 //
2688 //
2689 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
2690 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2691 // CHECK7-NEXT: entry:
2692 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
2693 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2694 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2695 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
2696 // CHECK7-NEXT: store i32 0, ptr [[F]], align 4
2697 // CHECK7-NEXT: ret void
2698 //
2699 //
2700 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
2701 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2702 // CHECK7-NEXT: entry:
2703 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
2704 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
2705 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2706 // CHECK7-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
2707 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2708 // CHECK7-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
2709 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
2710 // CHECK7-NEXT: store i32 [[TMP0]], ptr [[F]], align 4
2711 // CHECK7-NEXT: ret void
2712 //
2713 //
2714 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
2715 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2716 // CHECK7-NEXT: entry:
2717 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
2718 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2719 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2720 // CHECK7-NEXT: ret void
2721 //
2722 //
2723 // CHECK7-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
2724 // CHECK7-SAME: () #[[ATTR6:[0-9]+]] {
2725 // CHECK7-NEXT: entry:
2726 // CHECK7-NEXT: call void @__tgt_register_requires(i64 1)
2727 // CHECK7-NEXT: ret void
2728 //
LLVM monorepo