clang/test/OpenMP/target_teams_distribute_simd_codegen.cpp

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
   2 // Test host codegen.
   3 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck  %s --check-prefix=CHECK1
   4 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
   5 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck  %s --check-prefix=CHECK1
   6 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck  %s --check-prefix=CHECK3
   7 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
   8 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck  %s --check-prefix=CHECK3
   9 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck  %s --check-prefix=CHECK5
  10 // RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
  11 // RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck  %s --check-prefix=CHECK5
  12 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck  %s --check-prefix=CHECK7
  13 // RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
  14 // RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck  %s --check-prefix=CHECK7
  15
  16 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck  %s --check-prefix=CHECK9
  17 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
  18 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck  %s --check-prefix=CHECK9
  19 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck  %s --check-prefix=CHECK11
  20 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
  21 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck  %s --check-prefix=CHECK11
  22 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck  %s --check-prefix=CHECK13
  23 // RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
  24 // RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck  %s --check-prefix=CHECK13
  25 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck  %s --check-prefix=CHECK15
  26 // RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
  27 // RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck  %s --check-prefix=CHECK15
  28
  29 // Test target codegen - host bc file has to be created first.
  30 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
  31 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck  %s --check-prefix=CHECK17
  32 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
  33 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck  %s --check-prefix=CHECK17
  34 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
  35 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck  %s --check-prefix=CHECK19
  36 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
  37 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck  %s --check-prefix=CHECK19
  38 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
  39 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck  %s --check-prefix=CHECK21
  40 // RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
  41 // RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck  %s --check-prefix=CHECK21
  42 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
  43 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck  %s --check-prefix=CHECK23
  44 // RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
  45 // RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck  %s --check-prefix=CHECK23
  46
  47 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
  48 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck  %s --check-prefix=CHECK9
  49 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
  50 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck  %s --check-prefix=CHECK9
  51 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
  52 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck  %s --check-prefix=CHECK11
  53 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
  54 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck  %s --check-prefix=CHECK11
  55 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
  56 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck  %s --check-prefix=CHECK13
  57 // RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
  58 // RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck  %s --check-prefix=CHECK13
  59 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
  60 // RUN: %clang_cc1 -verify -Wno-vla -fopenmp-simd -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck  %s --check-prefix=CHECK15
  61 // RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
  62 // RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck  %s --check-prefix=CHECK15
  63 // expected-no-diagnostics
  64
  65 #ifndef HEADER
  66 #define HEADER
  67
  68
  69
  70
  71 // We have 8 target regions, but only 7 that actually will generate offloading
  72 // code, only 6 will have mapped arguments, and only 4 have all-constant map
  73 // sizes.
  74
  75
  76
  77 // Check target registration is registered as a Ctor.
  78
  79
  80 template<typename tx, typename ty>
  81 struct TT{
  82   tx X;
  83   ty Y;
  84 };
  85
  86 int global;
  87
  88 int foo(int n) {
  89   int a = 0;
  90   short aa = 0;
  91   float b[10];
  92   float bn[n];
  93   double c[5][10];
  94   double cn[5][n];
  95   TT<long long, char> d;
  96
  97   #pragma omp target teams distribute simd num_teams(a) thread_limit(a) firstprivate(aa) simdlen(16) nowait
  98   for (int i = 0; i < 10; ++i) {
  99   }
 100
 101 #ifdef OMP5
 102   #pragma omp target teams distribute simd if(target: 0) safelen(32) linear(a) if(simd: 1) nontemporal(a)
 103 #else
 104   #pragma omp target teams distribute simd if(target: 0) safelen(32) linear(a)
 105 #endif // OMP5
 106   for (a = 0; a < 10; ++a) {
 107     a += 1;
 108   }
 109
 110
 111   #pragma omp target teams distribute simd if(target: 1)
 112   for (int i = 0; i < 10; ++i) {
 113     aa += 1;
 114   }
 115
 116
 117
 118   #pragma omp target teams distribute simd if(target: n>10)
 119   for (int i = 0; i < 10; ++i) {
 120     a += 1;
 121     aa += 1;
 122   }
 123
 124   // We capture 3 VLA sizes in this target region
 125
 126
 127
 128
 129
 130   // The names below are not necessarily consistent with the names used for the
 131   // addresses above as some are repeated.
 132
 133
 134
 135
 136
 137
 138
 139
 140
 141
 142   #pragma omp target teams distribute simd if(target: n>20) aligned(b)
 143   for (int i = 0; i < 10; ++i) {
 144     a += 1;
 145     b[2] += 1.0;
 146     bn[3] += 1.0;
 147     c[1][2] += 1.0;
 148     cn[1][3] += 1.0;
 149     d.X += 1;
 150     d.Y += 1;
 151   }
 152
 153   return a;
 154 }
 155
 156 // Check that the offloading functions are emitted and that the arguments are
 157 // correct and loaded correctly for the target regions in foo().
 158
 159
 160
 161
 162 // Create stack storage and store argument in there.
 163
 164 // Create stack storage and store argument in there.
 165
 166 // Create stack storage and store argument in there.
 167
 168 // Create local storage for each capture.
 169
 170
 171
 172 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.
 173
 174 template<typename tx>
 175 tx ftemplate(int n) {
 176   tx a = 0;
 177   short aa = 0;
 178   tx b[10];
 179
 180   #pragma omp target teams distribute simd if(target: n>40)
 181   for (int i = 0; i < 10; ++i) {
 182     a += 1;
 183     aa += 1;
 184     b[2] += 1;
 185   }
 186
 187   return a;
 188 }
 189
 190 static
 191 int fstatic(int n) {
 192   int a = 0;
 193   short aa = 0;
 194   char aaa = 0;
 195   int b[10];
 196
 197   #pragma omp target teams distribute simd if(target: n>50)
 198   for (int i = a; i < n; ++i) {
 199     a += 1;
 200     aa += 1;
 201     aaa += 1;
 202     b[2] += 1;
 203   }
 204
 205   return a;
 206 }
 207
 208 struct S1 {
 209   double a;
 210
 211   int r1(int n){
 212     int b = n+1;
 213     short int c[2][n];
 214
 215     #pragma omp target teams distribute simd if(n>60)
 216     for (int i = 0; i < 10; ++i) {
 217       this->a = (double)b + 1.5;
 218       c[1][1] = ++a;
 219     }
 220
 221     return c[1][1] + (int)b;
 222   }
 223 };
 224
 225 int bar(int n){
 226   int a = 0;
 227
 228   a += foo(n);
 229
 230   S1 S;
 231   a += S.r1(n);
 232
 233   a += fstatic(n);
 234
 235   a += ftemplate<int>(n);
 236
 237   return a;
 238 }
 239
 240
 241
 242 // We capture 2 VLA sizes in this target region
 243
 244
 245 // The names below are not necessarily consistent with the names used for the
 246 // addresses above as some are repeated.
 247
 248
 249
 250
 251
 252
 253
 254
 255
 256
 257
 258
 259
 260
 261
 262
 263
 264
 265
 266
 267
 268
 269 // Check that the offloading functions are emitted and that the arguments are
 270 // correct and loaded correctly for the target regions of the callees of bar().
 271
 272 // Create local storage for each capture.
 273 // Store captures in the context.
 274
 275
 276 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.
 277
 278
 279 // Create local storage for each capture.
 280 // Store captures in the context.
 281
 282
 283
 284
 285 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.
 286
 287 // Create local storage for each capture.
 288 // Store captures in the context.
 289
 290
 291
 292 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.
 293
 294
 295 #endif
 296 // CHECK1-LABEL: define {{[^@]+}}@_Z3fooi
 297 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
 298 // CHECK1-NEXT:  entry:
 299 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
 300 // CHECK1-NEXT:    [[A:%.*]] = alloca i32, align 4
 301 // CHECK1-NEXT:    [[AA:%.*]] = alloca i16, align 2
 302 // CHECK1-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
 303 // CHECK1-NEXT:    [[SAVED_STACK:%.*]] = alloca ptr, align 8
 304 // CHECK1-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
 305 // CHECK1-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
 306 // CHECK1-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
 307 // CHECK1-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
 308 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
 309 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
 310 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
 311 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
 312 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR__CASTED3:%.*]] = alloca i64, align 8
 313 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8
 314 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 8
 315 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 8
 316 // CHECK1-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4
 317 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
 318 // CHECK1-NEXT:    [[AA_CASTED4:%.*]] = alloca i64, align 8
 319 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [1 x ptr], align 8
 320 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS6:%.*]] = alloca [1 x ptr], align 8
 321 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [1 x ptr], align 8
 322 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 323 // CHECK1-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
 324 // CHECK1-NEXT:    [[A_CASTED8:%.*]] = alloca i64, align 8
 325 // CHECK1-NEXT:    [[AA_CASTED9:%.*]] = alloca i64, align 8
 326 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [2 x ptr], align 8
 327 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS11:%.*]] = alloca [2 x ptr], align 8
 328 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [2 x ptr], align 8
 329 // CHECK1-NEXT:    [[_TMP13:%.*]] = alloca i32, align 4
 330 // CHECK1-NEXT:    [[KERNEL_ARGS14:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
 331 // CHECK1-NEXT:    [[A_CASTED17:%.*]] = alloca i64, align 8
 332 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [9 x ptr], align 8
 333 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS21:%.*]] = alloca [9 x ptr], align 8
 334 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [9 x ptr], align 8
 335 // CHECK1-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 8
 336 // CHECK1-NEXT:    [[_TMP23:%.*]] = alloca i32, align 4
 337 // CHECK1-NEXT:    [[KERNEL_ARGS24:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
 338 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])
 339 // CHECK1-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
 340 // CHECK1-NEXT:    store i32 0, ptr [[A]], align 4
 341 // CHECK1-NEXT:    store i16 0, ptr [[AA]], align 2
 342 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
 343 // CHECK1-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
 344 // CHECK1-NEXT:    [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()
 345 // CHECK1-NEXT:    store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8
 346 // CHECK1-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4
 347 // CHECK1-NEXT:    store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8
 348 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
 349 // CHECK1-NEXT:    [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
 350 // CHECK1-NEXT:    [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]]
 351 // CHECK1-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8
 352 // CHECK1-NEXT:    store i64 [[TMP5]], ptr [[__VLA_EXPR1]], align 8
 353 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[A]], align 4
 354 // CHECK1-NEXT:    store i32 [[TMP7]], ptr [[DOTCAPTURE_EXPR_]], align 4
 355 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A]], align 4
 356 // CHECK1-NEXT:    store i32 [[TMP8]], ptr [[DOTCAPTURE_EXPR_2]], align 4
 357 // CHECK1-NEXT:    [[TMP9:%.*]] = load i16, ptr [[AA]], align 2
 358 // CHECK1-NEXT:    store i16 [[TMP9]], ptr [[AA_CASTED]], align 2
 359 // CHECK1-NEXT:    [[TMP10:%.*]] = load i64, ptr [[AA_CASTED]], align 8
 360 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
 361 // CHECK1-NEXT:    store i32 [[TMP11]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
 362 // CHECK1-NEXT:    [[TMP12:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8
 363 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
 364 // CHECK1-NEXT:    store i32 [[TMP13]], ptr [[DOTCAPTURE_EXPR__CASTED3]], align 4
 365 // CHECK1-NEXT:    [[TMP14:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED3]], align 8
 366 // CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
 367 // CHECK1-NEXT:    store i64 [[TMP10]], ptr [[TMP15]], align 8
 368 // CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
 369 // CHECK1-NEXT:    store i64 [[TMP10]], ptr [[TMP16]], align 8
 370 // CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
 371 // CHECK1-NEXT:    store ptr null, ptr [[TMP17]], align 8
 372 // CHECK1-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
 373 // CHECK1-NEXT:    store i64 [[TMP12]], ptr [[TMP18]], align 8
 374 // CHECK1-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
 375 // CHECK1-NEXT:    store i64 [[TMP12]], ptr [[TMP19]], align 8
 376 // CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
 377 // CHECK1-NEXT:    store ptr null, ptr [[TMP20]], align 8
 378 // CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
 379 // CHECK1-NEXT:    store i64 [[TMP14]], ptr [[TMP21]], align 8
 380 // CHECK1-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
 381 // CHECK1-NEXT:    store i64 [[TMP14]], ptr [[TMP22]], align 8
 382 // CHECK1-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
 383 // CHECK1-NEXT:    store ptr null, ptr [[TMP23]], align 8
 384 // CHECK1-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
 385 // CHECK1-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
 386 // CHECK1-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0
 387 // CHECK1-NEXT:    [[TMP27:%.*]] = load i16, ptr [[AA]], align 2
 388 // CHECK1-NEXT:    store i16 [[TMP27]], ptr [[TMP26]], align 4
 389 // CHECK1-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 1
 390 // CHECK1-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
 391 // CHECK1-NEXT:    store i32 [[TMP29]], ptr [[TMP28]], align 4
 392 // CHECK1-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 2
 393 // CHECK1-NEXT:    [[TMP31:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
 394 // CHECK1-NEXT:    store i32 [[TMP31]], ptr [[TMP30]], align 4
 395 // CHECK1-NEXT:    [[TMP32:%.*]] = call ptr @__kmpc_omp_target_task_alloc(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i64 120, i64 12, ptr @.omp_task_entry., i64 -1)
 396 // CHECK1-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP32]], i32 0, i32 0
 397 // CHECK1-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP33]], i32 0, i32 0
 398 // CHECK1-NEXT:    [[TMP35:%.*]] = load ptr, ptr [[TMP34]], align 8
 399 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP35]], ptr align 4 [[AGG_CAPTURED]], i64 12, i1 false)
 400 // CHECK1-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP32]], i32 0, i32 1
 401 // CHECK1-NEXT:    [[TMP37:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP36]], i32 0, i32 0
 402 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP37]], ptr align 8 [[TMP24]], i64 24, i1 false)
 403 // CHECK1-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP36]], i32 0, i32 1
 404 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP38]], ptr align 8 [[TMP25]], i64 24, i1 false)
 405 // CHECK1-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP36]], i32 0, i32 2
 406 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP39]], ptr align 8 @.offload_sizes, i64 24, i1 false)
 407 // CHECK1-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP36]], i32 0, i32 3
 408 // CHECK1-NEXT:    [[TMP41:%.*]] = load i16, ptr [[AA]], align 2
 409 // CHECK1-NEXT:    store i16 [[TMP41]], ptr [[TMP40]], align 8
 410 // CHECK1-NEXT:    [[TMP42:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB2]], i32 [[TMP0]], ptr [[TMP32]])
 411 // CHECK1-NEXT:    [[TMP43:%.*]] = load i32, ptr [[A]], align 4
 412 // CHECK1-NEXT:    store i32 [[TMP43]], ptr [[A_CASTED]], align 4
 413 // CHECK1-NEXT:    [[TMP44:%.*]] = load i64, ptr [[A_CASTED]], align 8
 414 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104(i64 [[TMP44]]) #[[ATTR3:[0-9]+]]
 415 // CHECK1-NEXT:    [[TMP45:%.*]] = load i16, ptr [[AA]], align 2
 416 // CHECK1-NEXT:    store i16 [[TMP45]], ptr [[AA_CASTED4]], align 2
 417 // CHECK1-NEXT:    [[TMP46:%.*]] = load i64, ptr [[AA_CASTED4]], align 8
 418 // CHECK1-NEXT:    [[TMP47:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0
 419 // CHECK1-NEXT:    store i64 [[TMP46]], ptr [[TMP47]], align 8
 420 // CHECK1-NEXT:    [[TMP48:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0
 421 // CHECK1-NEXT:    store i64 [[TMP46]], ptr [[TMP48]], align 8
 422 // CHECK1-NEXT:    [[TMP49:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 0
 423 // CHECK1-NEXT:    store ptr null, ptr [[TMP49]], align 8
 424 // CHECK1-NEXT:    [[TMP50:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0
 425 // CHECK1-NEXT:    [[TMP51:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0
 426 // CHECK1-NEXT:    [[TMP52:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
 427 // CHECK1-NEXT:    store i32 2, ptr [[TMP52]], align 4
 428 // CHECK1-NEXT:    [[TMP53:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
 429 // CHECK1-NEXT:    store i32 1, ptr [[TMP53]], align 4
 430 // CHECK1-NEXT:    [[TMP54:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
 431 // CHECK1-NEXT:    store ptr [[TMP50]], ptr [[TMP54]], align 8
 432 // CHECK1-NEXT:    [[TMP55:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
 433 // CHECK1-NEXT:    store ptr [[TMP51]], ptr [[TMP55]], align 8
 434 // CHECK1-NEXT:    [[TMP56:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
 435 // CHECK1-NEXT:    store ptr @.offload_sizes.1, ptr [[TMP56]], align 8
 436 // CHECK1-NEXT:    [[TMP57:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
 437 // CHECK1-NEXT:    store ptr @.offload_maptypes.2, ptr [[TMP57]], align 8
 438 // CHECK1-NEXT:    [[TMP58:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
 439 // CHECK1-NEXT:    store ptr null, ptr [[TMP58]], align 8
 440 // CHECK1-NEXT:    [[TMP59:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
 441 // CHECK1-NEXT:    store ptr null, ptr [[TMP59]], align 8
 442 // CHECK1-NEXT:    [[TMP60:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
 443 // CHECK1-NEXT:    store i64 10, ptr [[TMP60]], align 8
 444 // CHECK1-NEXT:    [[TMP61:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
 445 // CHECK1-NEXT:    store i64 0, ptr [[TMP61]], align 8
 446 // CHECK1-NEXT:    [[TMP62:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
 447 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP62]], align 4
 448 // CHECK1-NEXT:    [[TMP63:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
 449 // CHECK1-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP63]], align 4
 450 // CHECK1-NEXT:    [[TMP64:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
 451 // CHECK1-NEXT:    store i32 0, ptr [[TMP64]], align 4
 452 // CHECK1-NEXT:    [[TMP65:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.region_id, ptr [[KERNEL_ARGS]])
 453 // CHECK1-NEXT:    [[TMP66:%.*]] = icmp ne i32 [[TMP65]], 0
 454 // CHECK1-NEXT:    br i1 [[TMP66]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
 455 // CHECK1:       omp_offload.failed:
 456 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i64 [[TMP46]]) #[[ATTR3]]
 457 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
 458 // CHECK1:       omp_offload.cont:
 459 // CHECK1-NEXT:    [[TMP67:%.*]] = load i32, ptr [[A]], align 4
 460 // CHECK1-NEXT:    store i32 [[TMP67]], ptr [[A_CASTED8]], align 4
 461 // CHECK1-NEXT:    [[TMP68:%.*]] = load i64, ptr [[A_CASTED8]], align 8
 462 // CHECK1-NEXT:    [[TMP69:%.*]] = load i16, ptr [[AA]], align 2
 463 // CHECK1-NEXT:    store i16 [[TMP69]], ptr [[AA_CASTED9]], align 2
 464 // CHECK1-NEXT:    [[TMP70:%.*]] = load i64, ptr [[AA_CASTED9]], align 8
 465 // CHECK1-NEXT:    [[TMP71:%.*]] = load i32, ptr [[N_ADDR]], align 4
 466 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP71]], 10
 467 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
 468 // CHECK1:       omp_if.then:
 469 // CHECK1-NEXT:    [[TMP72:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
 470 // CHECK1-NEXT:    store i64 [[TMP68]], ptr [[TMP72]], align 8
 471 // CHECK1-NEXT:    [[TMP73:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
 472 // CHECK1-NEXT:    store i64 [[TMP68]], ptr [[TMP73]], align 8
 473 // CHECK1-NEXT:    [[TMP74:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 0
 474 // CHECK1-NEXT:    store ptr null, ptr [[TMP74]], align 8
 475 // CHECK1-NEXT:    [[TMP75:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 1
 476 // CHECK1-NEXT:    store i64 [[TMP70]], ptr [[TMP75]], align 8
 477 // CHECK1-NEXT:    [[TMP76:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 1
 478 // CHECK1-NEXT:    store i64 [[TMP70]], ptr [[TMP76]], align 8
 479 // CHECK1-NEXT:    [[TMP77:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 1
 480 // CHECK1-NEXT:    store ptr null, ptr [[TMP77]], align 8
 481 // CHECK1-NEXT:    [[TMP78:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
 482 // CHECK1-NEXT:    [[TMP79:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
 483 // CHECK1-NEXT:    [[TMP80:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 0
 484 // CHECK1-NEXT:    store i32 2, ptr [[TMP80]], align 4
 485 // CHECK1-NEXT:    [[TMP81:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 1
 486 // CHECK1-NEXT:    store i32 2, ptr [[TMP81]], align 4
 487 // CHECK1-NEXT:    [[TMP82:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 2
 488 // CHECK1-NEXT:    store ptr [[TMP78]], ptr [[TMP82]], align 8
 489 // CHECK1-NEXT:    [[TMP83:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 3
 490 // CHECK1-NEXT:    store ptr [[TMP79]], ptr [[TMP83]], align 8
 491 // CHECK1-NEXT:    [[TMP84:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 4
 492 // CHECK1-NEXT:    store ptr @.offload_sizes.3, ptr [[TMP84]], align 8
 493 // CHECK1-NEXT:    [[TMP85:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 5
 494 // CHECK1-NEXT:    store ptr @.offload_maptypes.4, ptr [[TMP85]], align 8
 495 // CHECK1-NEXT:    [[TMP86:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 6
 496 // CHECK1-NEXT:    store ptr null, ptr [[TMP86]], align 8
 497 // CHECK1-NEXT:    [[TMP87:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 7
 498 // CHECK1-NEXT:    store ptr null, ptr [[TMP87]], align 8
 499 // CHECK1-NEXT:    [[TMP88:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 8
 500 // CHECK1-NEXT:    store i64 10, ptr [[TMP88]], align 8
 501 // CHECK1-NEXT:    [[TMP89:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 9
 502 // CHECK1-NEXT:    store i64 0, ptr [[TMP89]], align 8
 503 // CHECK1-NEXT:    [[TMP90:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 10
 504 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP90]], align 4
 505 // CHECK1-NEXT:    [[TMP91:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 11
 506 // CHECK1-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP91]], align 4
 507 // CHECK1-NEXT:    [[TMP92:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 12
 508 // CHECK1-NEXT:    store i32 0, ptr [[TMP92]], align 4
 509 // CHECK1-NEXT:    [[TMP93:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.region_id, ptr [[KERNEL_ARGS14]])
 510 // CHECK1-NEXT:    [[TMP94:%.*]] = icmp ne i32 [[TMP93]], 0
 511 // CHECK1-NEXT:    br i1 [[TMP94]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]]
 512 // CHECK1:       omp_offload.failed15:
 513 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP68]], i64 [[TMP70]]) #[[ATTR3]]
 514 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT16]]
 515 // CHECK1:       omp_offload.cont16:
 516 // CHECK1-NEXT:    br label [[OMP_IF_END:%.*]]
 517 // CHECK1:       omp_if.else:
 518 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP68]], i64 [[TMP70]]) #[[ATTR3]]
 519 // CHECK1-NEXT:    br label [[OMP_IF_END]]
 520 // CHECK1:       omp_if.end:
 521 // CHECK1-NEXT:    [[TMP95:%.*]] = load i32, ptr [[A]], align 4
 522 // CHECK1-NEXT:    store i32 [[TMP95]], ptr [[A_CASTED17]], align 4
 523 // CHECK1-NEXT:    [[TMP96:%.*]] = load i64, ptr [[A_CASTED17]], align 8
 524 // CHECK1-NEXT:    [[TMP97:%.*]] = load i32, ptr [[N_ADDR]], align 4
 525 // CHECK1-NEXT:    [[CMP18:%.*]] = icmp sgt i32 [[TMP97]], 20
 526 // CHECK1-NEXT:    br i1 [[CMP18]], label [[OMP_IF_THEN19:%.*]], label [[OMP_IF_ELSE27:%.*]]
 527 // CHECK1:       omp_if.then19:
 528 // CHECK1-NEXT:    [[TMP98:%.*]] = mul nuw i64 [[TMP2]], 4
 529 // CHECK1-NEXT:    [[TMP99:%.*]] = mul nuw i64 5, [[TMP5]]
 530 // CHECK1-NEXT:    [[TMP100:%.*]] = mul nuw i64 [[TMP99]], 8
 531 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes.5, i64 72, i1 false)
 532 // CHECK1-NEXT:    [[TMP101:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0
 533 // CHECK1-NEXT:    store i64 [[TMP96]], ptr [[TMP101]], align 8
 534 // CHECK1-NEXT:    [[TMP102:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 0
 535 // CHECK1-NEXT:    store i64 [[TMP96]], ptr [[TMP102]], align 8
 536 // CHECK1-NEXT:    [[TMP103:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 0
 537 // CHECK1-NEXT:    store ptr null, ptr [[TMP103]], align 8
 538 // CHECK1-NEXT:    [[TMP104:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1
 539 // CHECK1-NEXT:    store ptr [[B]], ptr [[TMP104]], align 8
 540 // CHECK1-NEXT:    [[TMP105:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 1
 541 // CHECK1-NEXT:    store ptr [[B]], ptr [[TMP105]], align 8
 542 // CHECK1-NEXT:    [[TMP106:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 1
 543 // CHECK1-NEXT:    store ptr null, ptr [[TMP106]], align 8
 544 // CHECK1-NEXT:    [[TMP107:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 2
 545 // CHECK1-NEXT:    store i64 [[TMP2]], ptr [[TMP107]], align 8
 546 // CHECK1-NEXT:    [[TMP108:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 2
 547 // CHECK1-NEXT:    store i64 [[TMP2]], ptr [[TMP108]], align 8
 548 // CHECK1-NEXT:    [[TMP109:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 2
 549 // CHECK1-NEXT:    store ptr null, ptr [[TMP109]], align 8
 550 // CHECK1-NEXT:    [[TMP110:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 3
 551 // CHECK1-NEXT:    store ptr [[VLA]], ptr [[TMP110]], align 8
 552 // CHECK1-NEXT:    [[TMP111:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 3
 553 // CHECK1-NEXT:    store ptr [[VLA]], ptr [[TMP111]], align 8
 554 // CHECK1-NEXT:    [[TMP112:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 3
 555 // CHECK1-NEXT:    store i64 [[TMP98]], ptr [[TMP112]], align 8
 556 // CHECK1-NEXT:    [[TMP113:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 3
 557 // CHECK1-NEXT:    store ptr null, ptr [[TMP113]], align 8
 558 // CHECK1-NEXT:    [[TMP114:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 4
 559 // CHECK1-NEXT:    store ptr [[C]], ptr [[TMP114]], align 8
 560 // CHECK1-NEXT:    [[TMP115:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 4
 561 // CHECK1-NEXT:    store ptr [[C]], ptr [[TMP115]], align 8
 562 // CHECK1-NEXT:    [[TMP116:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 4
 563 // CHECK1-NEXT:    store ptr null, ptr [[TMP116]], align 8
 564 // CHECK1-NEXT:    [[TMP117:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 5
 565 // CHECK1-NEXT:    store i64 5, ptr [[TMP117]], align 8
 566 // CHECK1-NEXT:    [[TMP118:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 5
 567 // CHECK1-NEXT:    store i64 5, ptr [[TMP118]], align 8
 568 // CHECK1-NEXT:    [[TMP119:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 5
 569 // CHECK1-NEXT:    store ptr null, ptr [[TMP119]], align 8
 570 // CHECK1-NEXT:    [[TMP120:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 6
 571 // CHECK1-NEXT:    store i64 [[TMP5]], ptr [[TMP120]], align 8
 572 // CHECK1-NEXT:    [[TMP121:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 6
 573 // CHECK1-NEXT:    store i64 [[TMP5]], ptr [[TMP121]], align 8
 574 // CHECK1-NEXT:    [[TMP122:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 6
 575 // CHECK1-NEXT:    store ptr null, ptr [[TMP122]], align 8
 576 // CHECK1-NEXT:    [[TMP123:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 7
 577 // CHECK1-NEXT:    store ptr [[VLA1]], ptr [[TMP123]], align 8
 578 // CHECK1-NEXT:    [[TMP124:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 7
 579 // CHECK1-NEXT:    store ptr [[VLA1]], ptr [[TMP124]], align 8
 580 // CHECK1-NEXT:    [[TMP125:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 7
 581 // CHECK1-NEXT:    store i64 [[TMP100]], ptr [[TMP125]], align 8
 582 // CHECK1-NEXT:    [[TMP126:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 7
 583 // CHECK1-NEXT:    store ptr null, ptr [[TMP126]], align 8
 584 // CHECK1-NEXT:    [[TMP127:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 8
 585 // CHECK1-NEXT:    store ptr [[D]], ptr [[TMP127]], align 8
 586 // CHECK1-NEXT:    [[TMP128:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 8
 587 // CHECK1-NEXT:    store ptr [[D]], ptr [[TMP128]], align 8
 588 // CHECK1-NEXT:    [[TMP129:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 8
 589 // CHECK1-NEXT:    store ptr null, ptr [[TMP129]], align 8
 590 // CHECK1-NEXT:    [[TMP130:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0
 591 // CHECK1-NEXT:    [[TMP131:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 0
 592 // CHECK1-NEXT:    [[TMP132:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0
 593 // CHECK1-NEXT:    [[TMP133:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 0
 594 // CHECK1-NEXT:    store i32 2, ptr [[TMP133]], align 4
 595 // CHECK1-NEXT:    [[TMP134:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 1
 596 // CHECK1-NEXT:    store i32 9, ptr [[TMP134]], align 4
 597 // CHECK1-NEXT:    [[TMP135:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 2
 598 // CHECK1-NEXT:    store ptr [[TMP130]], ptr [[TMP135]], align 8
 599 // CHECK1-NEXT:    [[TMP136:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 3
 600 // CHECK1-NEXT:    store ptr [[TMP131]], ptr [[TMP136]], align 8
 601 // CHECK1-NEXT:    [[TMP137:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 4
 602 // CHECK1-NEXT:    store ptr [[TMP132]], ptr [[TMP137]], align 8
 603 // CHECK1-NEXT:    [[TMP138:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 5
 604 // CHECK1-NEXT:    store ptr @.offload_maptypes.6, ptr [[TMP138]], align 8
 605 // CHECK1-NEXT:    [[TMP139:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 6
 606 // CHECK1-NEXT:    store ptr null, ptr [[TMP139]], align 8
 607 // CHECK1-NEXT:    [[TMP140:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 7
 608 // CHECK1-NEXT:    store ptr null, ptr [[TMP140]], align 8
 609 // CHECK1-NEXT:    [[TMP141:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 8
 610 // CHECK1-NEXT:    store i64 10, ptr [[TMP141]], align 8
 611 // CHECK1-NEXT:    [[TMP142:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 9
 612 // CHECK1-NEXT:    store i64 0, ptr [[TMP142]], align 8
 613 // CHECK1-NEXT:    [[TMP143:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 10
 614 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP143]], align 4
 615 // CHECK1-NEXT:    [[TMP144:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 11
 616 // CHECK1-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP144]], align 4
 617 // CHECK1-NEXT:    [[TMP145:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 12
 618 // CHECK1-NEXT:    store i32 0, ptr [[TMP145]], align 4
 619 // CHECK1-NEXT:    [[TMP146:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.region_id, ptr [[KERNEL_ARGS24]])
 620 // CHECK1-NEXT:    [[TMP147:%.*]] = icmp ne i32 [[TMP146]], 0
 621 // CHECK1-NEXT:    br i1 [[TMP147]], label [[OMP_OFFLOAD_FAILED25:%.*]], label [[OMP_OFFLOAD_CONT26:%.*]]
 622 // CHECK1:       omp_offload.failed25:
 623 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP96]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]]) #[[ATTR3]]
 624 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT26]]
 625 // CHECK1:       omp_offload.cont26:
 626 // CHECK1-NEXT:    br label [[OMP_IF_END28:%.*]]
 627 // CHECK1:       omp_if.else27:
 628 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP96]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]]) #[[ATTR3]]
 629 // CHECK1-NEXT:    br label [[OMP_IF_END28]]
 630 // CHECK1:       omp_if.end28:
 631 // CHECK1-NEXT:    [[TMP148:%.*]] = load i32, ptr [[A]], align 4
 632 // CHECK1-NEXT:    [[TMP149:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
 633 // CHECK1-NEXT:    call void @llvm.stackrestore.p0(ptr [[TMP149]])
 634 // CHECK1-NEXT:    ret i32 [[TMP148]]
 635 //
 636 //
 637 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97
 638 // CHECK1-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] {
 639 // CHECK1-NEXT:  entry:
 640 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
 641 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
 642 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8
 643 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
 644 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
 645 // CHECK1-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
 646 // CHECK1-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
 647 // CHECK1-NEXT:    store i64 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 8
 648 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
 649 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4
 650 // CHECK1-NEXT:    call void @__kmpc_push_num_teams(ptr @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
 651 // CHECK1-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
 652 // CHECK1-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
 653 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8
 654 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.omp_outlined, i64 [[TMP4]])
 655 // CHECK1-NEXT:    ret void
 656 //
 657 //
 658 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.omp_outlined
 659 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {
 660 // CHECK1-NEXT:  entry:
 661 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 662 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 663 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
 664 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 665 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 666 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
 667 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
 668 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 669 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 670 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
 671 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 672 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 673 // CHECK1-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
 674 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
 675 // CHECK1-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4
 676 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 677 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 678 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 679 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
 680 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
 681 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 682 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
 683 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 684 // CHECK1:       cond.true:
 685 // CHECK1-NEXT:    br label [[COND_END:%.*]]
 686 // CHECK1:       cond.false:
 687 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 688 // CHECK1-NEXT:    br label [[COND_END]]
 689 // CHECK1:       cond.end:
 690 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
 691 // CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
 692 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
 693 // CHECK1-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
 694 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 695 // CHECK1:       omp.inner.for.cond:
 696 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10:![0-9]+]]
 697 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP10]]
 698 // CHECK1-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
 699 // CHECK1-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 700 // CHECK1:       omp.inner.for.body:
 701 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]]
 702 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
 703 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
 704 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]]
 705 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 706 // CHECK1:       omp.body.continue:
 707 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 708 // CHECK1:       omp.inner.for.inc:
 709 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]]
 710 // CHECK1-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
 711 // CHECK1-NEXT:    store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]]
 712 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
 713 // CHECK1:       omp.inner.for.end:
 714 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
 715 // CHECK1:       omp.loop.exit:
 716 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
 717 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
 718 // CHECK1-NEXT:    [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
 719 // CHECK1-NEXT:    br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
 720 // CHECK1:       .omp.final.then:
 721 // CHECK1-NEXT:    store i32 10, ptr [[I]], align 4
 722 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
 723 // CHECK1:       .omp.final.done:
 724 // CHECK1-NEXT:    ret void
 725 //
 726 //
 727 // CHECK1-LABEL: define {{[^@]+}}@.omp_task_privates_map.
 728 // CHECK1-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]], ptr noalias noundef [[TMP3:%.*]], ptr noalias noundef [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] {
 729 // CHECK1-NEXT:  entry:
 730 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
 731 // CHECK1-NEXT:    [[DOTADDR1:%.*]] = alloca ptr, align 8
 732 // CHECK1-NEXT:    [[DOTADDR2:%.*]] = alloca ptr, align 8
 733 // CHECK1-NEXT:    [[DOTADDR3:%.*]] = alloca ptr, align 8
 734 // CHECK1-NEXT:    [[DOTADDR4:%.*]] = alloca ptr, align 8
 735 // CHECK1-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
 736 // CHECK1-NEXT:    store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
 737 // CHECK1-NEXT:    store ptr [[TMP2]], ptr [[DOTADDR2]], align 8
 738 // CHECK1-NEXT:    store ptr [[TMP3]], ptr [[DOTADDR3]], align 8
 739 // CHECK1-NEXT:    store ptr [[TMP4]], ptr [[DOTADDR4]], align 8
 740 // CHECK1-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[DOTADDR]], align 8
 741 // CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP5]], i32 0, i32 0
 742 // CHECK1-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[DOTADDR2]], align 8
 743 // CHECK1-NEXT:    store ptr [[TMP6]], ptr [[TMP7]], align 8
 744 // CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 1
 745 // CHECK1-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[DOTADDR3]], align 8
 746 // CHECK1-NEXT:    store ptr [[TMP8]], ptr [[TMP9]], align 8
 747 // CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 2
 748 // CHECK1-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[DOTADDR4]], align 8
 749 // CHECK1-NEXT:    store ptr [[TMP10]], ptr [[TMP11]], align 8
 750 // CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 3
 751 // CHECK1-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[DOTADDR1]], align 8
 752 // CHECK1-NEXT:    store ptr [[TMP12]], ptr [[TMP13]], align 8
 753 // CHECK1-NEXT:    ret void
 754 //
 755 //
 756 // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry.
 757 // CHECK1-SAME: (i32 noundef signext [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] {
 758 // CHECK1-NEXT:  entry:
 759 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
 760 // CHECK1-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8
 761 // CHECK1-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8
 762 // CHECK1-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8
 763 // CHECK1-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8
 764 // CHECK1-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8
 765 // CHECK1-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca ptr, align 8
 766 // CHECK1-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca ptr, align 8
 767 // CHECK1-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca ptr, align 8
 768 // CHECK1-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca ptr, align 8
 769 // CHECK1-NEXT:    [[KERNEL_ARGS_I:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
 770 // CHECK1-NEXT:    [[AA_CASTED_I:%.*]] = alloca i64, align 8
 771 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i64, align 8
 772 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR__CASTED4_I:%.*]] = alloca i64, align 8
 773 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 4
 774 // CHECK1-NEXT:    [[DOTADDR1:%.*]] = alloca ptr, align 8
 775 // CHECK1-NEXT:    store i32 [[TMP0]], ptr [[DOTADDR]], align 4
 776 // CHECK1-NEXT:    store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
 777 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4
 778 // CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8
 779 // CHECK1-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0
 780 // CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2
 781 // CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0
 782 // CHECK1-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8
 783 // CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 1
 784 // CHECK1-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])
 785 // CHECK1-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
 786 // CHECK1-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])
 787 // CHECK1-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]])
 788 // CHECK1-NEXT:    store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !26
 789 // CHECK1-NEXT:    store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias !26
 790 // CHECK1-NEXT:    store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias !26
 791 // CHECK1-NEXT:    store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !26
 792 // CHECK1-NEXT:    store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias !26
 793 // CHECK1-NEXT:    store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias !26
 794 // CHECK1-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias !26
 795 // CHECK1-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !26
 796 // CHECK1-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias !26
 797 // CHECK1-NEXT:    call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]
 798 // CHECK1-NEXT:    [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !26
 799 // CHECK1-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !26
 800 // CHECK1-NEXT:    [[TMP14:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !26
 801 // CHECK1-NEXT:    [[TMP15:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !26
 802 // CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP9]], i32 0, i32 1
 803 // CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP9]], i32 0, i32 2
 804 // CHECK1-NEXT:    [[TMP18:%.*]] = load i32, ptr [[TMP16]], align 4
 805 // CHECK1-NEXT:    [[TMP19:%.*]] = insertvalue [3 x i32] zeroinitializer, i32 [[TMP18]], 0
 806 // CHECK1-NEXT:    store i32 2, ptr [[KERNEL_ARGS_I]], align 4, !noalias !26
 807 // CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 1
 808 // CHECK1-NEXT:    store i32 3, ptr [[TMP20]], align 4, !noalias !26
 809 // CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 2
 810 // CHECK1-NEXT:    store ptr [[TMP13]], ptr [[TMP21]], align 8, !noalias !26
 811 // CHECK1-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 3
 812 // CHECK1-NEXT:    store ptr [[TMP14]], ptr [[TMP22]], align 8, !noalias !26
 813 // CHECK1-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 4
 814 // CHECK1-NEXT:    store ptr [[TMP15]], ptr [[TMP23]], align 8, !noalias !26
 815 // CHECK1-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 5
 816 // CHECK1-NEXT:    store ptr @.offload_maptypes, ptr [[TMP24]], align 8, !noalias !26
 817 // CHECK1-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 6
 818 // CHECK1-NEXT:    store ptr null, ptr [[TMP25]], align 8, !noalias !26
 819 // CHECK1-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 7
 820 // CHECK1-NEXT:    store ptr null, ptr [[TMP26]], align 8, !noalias !26
 821 // CHECK1-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 8
 822 // CHECK1-NEXT:    store i64 10, ptr [[TMP27]], align 8, !noalias !26
 823 // CHECK1-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 9
 824 // CHECK1-NEXT:    store i64 1, ptr [[TMP28]], align 8, !noalias !26
 825 // CHECK1-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 10
 826 // CHECK1-NEXT:    store [3 x i32] [[TMP19]], ptr [[TMP29]], align 4, !noalias !26
 827 // CHECK1-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 11
 828 // CHECK1-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP30]], align 4, !noalias !26
 829 // CHECK1-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 12
 830 // CHECK1-NEXT:    store i32 0, ptr [[TMP31]], align 4, !noalias !26
 831 // CHECK1-NEXT:    [[TMP32:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 [[TMP18]], i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.region_id, ptr [[KERNEL_ARGS_I]])
 832 // CHECK1-NEXT:    [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0
 833 // CHECK1-NEXT:    br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]]
 834 // CHECK1:       omp_offload.failed.i:
 835 // CHECK1-NEXT:    [[TMP34:%.*]] = load i16, ptr [[TMP12]], align 2
 836 // CHECK1-NEXT:    store i16 [[TMP34]], ptr [[AA_CASTED_I]], align 2, !noalias !26
 837 // CHECK1-NEXT:    [[TMP35:%.*]] = load i64, ptr [[AA_CASTED_I]], align 8, !noalias !26
 838 // CHECK1-NEXT:    [[TMP36:%.*]] = load i32, ptr [[TMP16]], align 4
 839 // CHECK1-NEXT:    store i32 [[TMP36]], ptr [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !26
 840 // CHECK1-NEXT:    [[TMP37:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED_I]], align 8, !noalias !26
 841 // CHECK1-NEXT:    [[TMP38:%.*]] = load i32, ptr [[TMP17]], align 4
 842 // CHECK1-NEXT:    store i32 [[TMP38]], ptr [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !26
 843 // CHECK1-NEXT:    [[TMP39:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED4_I]], align 8, !noalias !26
 844 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97(i64 [[TMP35]], i64 [[TMP37]], i64 [[TMP39]]) #[[ATTR3]]
 845 // CHECK1-NEXT:    br label [[DOTOMP_OUTLINED__EXIT]]
 846 // CHECK1:       .omp_outlined..exit:
 847 // CHECK1-NEXT:    ret i32 0
 848 //
 849 //
 850 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104
 851 // CHECK1-SAME: (i64 noundef [[A:%.*]]) #[[ATTR2]] {
 852 // CHECK1-NEXT:  entry:
 853 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
 854 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
 855 // CHECK1-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
 856 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
 857 // CHECK1-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 4
 858 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8
 859 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104.omp_outlined, i64 [[TMP1]])
 860 // CHECK1-NEXT:    ret void
 861 //
 862 //
 863 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104.omp_outlined
 864 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] {
 865 // CHECK1-NEXT:  entry:
 866 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 867 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 868 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
 869 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 870 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 871 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
 872 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
 873 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 874 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 875 // CHECK1-NEXT:    [[A1:%.*]] = alloca i32, align 4
 876 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 877 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 878 // CHECK1-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
 879 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
 880 // CHECK1-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4
 881 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 882 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 883 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 884 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
 885 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
 886 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 887 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
 888 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 889 // CHECK1:       cond.true:
 890 // CHECK1-NEXT:    br label [[COND_END:%.*]]
 891 // CHECK1:       cond.false:
 892 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 893 // CHECK1-NEXT:    br label [[COND_END]]
 894 // CHECK1:       cond.end:
 895 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
 896 // CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
 897 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
 898 // CHECK1-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
 899 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 900 // CHECK1:       omp.inner.for.cond:
 901 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 902 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 903 // CHECK1-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
 904 // CHECK1-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 905 // CHECK1:       omp.inner.for.body:
 906 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 907 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
 908 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
 909 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[A1]], align 4
 910 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A1]], align 4
 911 // CHECK1-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
 912 // CHECK1-NEXT:    store i32 [[ADD3]], ptr [[A1]], align 4
 913 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 914 // CHECK1:       omp.body.continue:
 915 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 916 // CHECK1:       omp.inner.for.inc:
 917 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 918 // CHECK1-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP9]], 1
 919 // CHECK1-NEXT:    store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4
 920 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]]
 921 // CHECK1:       omp.inner.for.end:
 922 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
 923 // CHECK1:       omp.loop.exit:
 924 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
 925 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
 926 // CHECK1-NEXT:    [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
 927 // CHECK1-NEXT:    br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
 928 // CHECK1:       .omp.final.then:
 929 // CHECK1-NEXT:    store i32 10, ptr [[A_ADDR]], align 4
 930 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
 931 // CHECK1:       .omp.final.done:
 932 // CHECK1-NEXT:    ret void
 933 //
 934 //
 935 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
 936 // CHECK1-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR2]] {
 937 // CHECK1-NEXT:  entry:
 938 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
 939 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
 940 // CHECK1-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
 941 // CHECK1-NEXT:    [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2
 942 // CHECK1-NEXT:    store i16 [[TMP0]], ptr [[AA_CASTED]], align 2
 943 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[AA_CASTED]], align 8
 944 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined, i64 [[TMP1]])
 945 // CHECK1-NEXT:    ret void
 946 //
 947 //
 948 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined
 949 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {
 950 // CHECK1-NEXT:  entry:
 951 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 952 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 953 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
 954 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 955 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 956 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
 957 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
 958 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 959 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 960 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
 961 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 962 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 963 // CHECK1-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
 964 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
 965 // CHECK1-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4
 966 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 967 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 968 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 969 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
 970 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
 971 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 972 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
 973 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 974 // CHECK1:       cond.true:
 975 // CHECK1-NEXT:    br label [[COND_END:%.*]]
 976 // CHECK1:       cond.false:
 977 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 978 // CHECK1-NEXT:    br label [[COND_END]]
 979 // CHECK1:       cond.end:
 980 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
 981 // CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
 982 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
 983 // CHECK1-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
 984 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 985 // CHECK1:       omp.inner.for.cond:
 986 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP29:![0-9]+]]
 987 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP29]]
 988 // CHECK1-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
 989 // CHECK1-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
 990 // CHECK1:       omp.inner.for.body:
 991 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP29]]
 992 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
 993 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
 994 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP29]]
 995 // CHECK1-NEXT:    [[TMP8:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP29]]
 996 // CHECK1-NEXT:    [[CONV:%.*]] = sext i16 [[TMP8]] to i32
 997 // CHECK1-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
 998 // CHECK1-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
 999 // CHECK1-NEXT:    store i16 [[CONV3]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP29]]
1000 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1001 // CHECK1:       omp.body.continue:
1002 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1003 // CHECK1:       omp.inner.for.inc:
1004 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP29]]
1005 // CHECK1-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP9]], 1
1006 // CHECK1-NEXT:    store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP29]]
1007 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]]
1008 // CHECK1:       omp.inner.for.end:
1009 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1010 // CHECK1:       omp.loop.exit:
1011 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
1012 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
1013 // CHECK1-NEXT:    [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
1014 // CHECK1-NEXT:    br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1015 // CHECK1:       .omp.final.then:
1016 // CHECK1-NEXT:    store i32 10, ptr [[I]], align 4
1017 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
1018 // CHECK1:       .omp.final.done:
1019 // CHECK1-NEXT:    ret void
1020 //
1021 //
1022 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118
1023 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {
1024 // CHECK1-NEXT:  entry:
1025 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1026 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
1027 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
1028 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
1029 // CHECK1-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
1030 // CHECK1-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
1031 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
1032 // CHECK1-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 4
1033 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8
1034 // CHECK1-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2
1035 // CHECK1-NEXT:    store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
1036 // CHECK1-NEXT:    [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8
1037 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined, i64 [[TMP1]], i64 [[TMP3]])
1038 // CHECK1-NEXT:    ret void
1039 //
1040 //
1041 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined
1042 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {
1043 // CHECK1-NEXT:  entry:
1044 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1045 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1046 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1047 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
1048 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1049 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1050 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1051 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1052 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1053 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1054 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
1055 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1056 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1057 // CHECK1-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
1058 // CHECK1-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
1059 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
1060 // CHECK1-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4
1061 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1062 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1063 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1064 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
1065 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
1066 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1067 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
1068 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1069 // CHECK1:       cond.true:
1070 // CHECK1-NEXT:    br label [[COND_END:%.*]]
1071 // CHECK1:       cond.false:
1072 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1073 // CHECK1-NEXT:    br label [[COND_END]]
1074 // CHECK1:       cond.end:
1075 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
1076 // CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
1077 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1078 // CHECK1-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
1079 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1080 // CHECK1:       omp.inner.for.cond:
1081 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32:![0-9]+]]
1082 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP32]]
1083 // CHECK1-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
1084 // CHECK1-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1085 // CHECK1:       omp.inner.for.body:
1086 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]]
1087 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
1088 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1089 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP32]]
1090 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP32]]
1091 // CHECK1-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
1092 // CHECK1-NEXT:    store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP32]]
1093 // CHECK1-NEXT:    [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP32]]
1094 // CHECK1-NEXT:    [[CONV:%.*]] = sext i16 [[TMP9]] to i32
1095 // CHECK1-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV]], 1
1096 // CHECK1-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
1097 // CHECK1-NEXT:    store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP32]]
1098 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1099 // CHECK1:       omp.body.continue:
1100 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1101 // CHECK1:       omp.inner.for.inc:
1102 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]]
1103 // CHECK1-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP10]], 1
1104 // CHECK1-NEXT:    store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]]
1105 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]]
1106 // CHECK1:       omp.inner.for.end:
1107 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1108 // CHECK1:       omp.loop.exit:
1109 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
1110 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
1111 // CHECK1-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
1112 // CHECK1-NEXT:    br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1113 // CHECK1:       .omp.final.then:
1114 // CHECK1-NEXT:    store i32 10, ptr [[I]], align 4
1115 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
1116 // CHECK1:       .omp.final.done:
1117 // CHECK1-NEXT:    ret void
1118 //
1119 //
1120 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142
1121 // CHECK1-SAME: (i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] {
1122 // CHECK1-NEXT:  entry:
1123 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1124 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
1125 // CHECK1-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
1126 // CHECK1-NEXT:    [[BN_ADDR:%.*]] = alloca ptr, align 8
1127 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
1128 // CHECK1-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
1129 // CHECK1-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
1130 // CHECK1-NEXT:    [[CN_ADDR:%.*]] = alloca ptr, align 8
1131 // CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
1132 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
1133 // CHECK1-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
1134 // CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
1135 // CHECK1-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
1136 // CHECK1-NEXT:    store ptr [[BN]], ptr [[BN_ADDR]], align 8
1137 // CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
1138 // CHECK1-NEXT:    store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
1139 // CHECK1-NEXT:    store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8
1140 // CHECK1-NEXT:    store ptr [[CN]], ptr [[CN_ADDR]], align 8
1141 // CHECK1-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
1142 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
1143 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
1144 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8
1145 // CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
1146 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
1147 // CHECK1-NEXT:    [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8
1148 // CHECK1-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8
1149 // CHECK1-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8
1150 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
1151 // CHECK1-NEXT:    store i32 [[TMP8]], ptr [[A_CASTED]], align 4
1152 // CHECK1-NEXT:    [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 8
1153 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.omp_outlined, i64 [[TMP9]], ptr [[TMP0]], i64 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]])
1154 // CHECK1-NEXT:    ret void
1155 //
1156 //
1157 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.omp_outlined
1158 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] {
1159 // CHECK1-NEXT:  entry:
1160 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1161 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1162 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1163 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
1164 // CHECK1-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
1165 // CHECK1-NEXT:    [[BN_ADDR:%.*]] = alloca ptr, align 8
1166 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
1167 // CHECK1-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
1168 // CHECK1-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
1169 // CHECK1-NEXT:    [[CN_ADDR:%.*]] = alloca ptr, align 8
1170 // CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
1171 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1172 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1173 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1174 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1175 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1176 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1177 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
1178 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1179 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1180 // CHECK1-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
1181 // CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
1182 // CHECK1-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
1183 // CHECK1-NEXT:    store ptr [[BN]], ptr [[BN_ADDR]], align 8
1184 // CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
1185 // CHECK1-NEXT:    store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
1186 // CHECK1-NEXT:    store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8
1187 // CHECK1-NEXT:    store ptr [[CN]], ptr [[CN_ADDR]], align 8
1188 // CHECK1-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
1189 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
1190 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
1191 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8
1192 // CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
1193 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
1194 // CHECK1-NEXT:    [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8
1195 // CHECK1-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8
1196 // CHECK1-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8
1197 // CHECK1-NEXT:    [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 0
1198 // CHECK1-NEXT:    call void @llvm.assume(i1 true) [ "align"(ptr [[ARRAYDECAY]], i64 16) ]
1199 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
1200 // CHECK1-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4
1201 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1202 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1203 // CHECK1-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1204 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
1205 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP9]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
1206 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1207 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 9
1208 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1209 // CHECK1:       cond.true:
1210 // CHECK1-NEXT:    br label [[COND_END:%.*]]
1211 // CHECK1:       cond.false:
1212 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1213 // CHECK1-NEXT:    br label [[COND_END]]
1214 // CHECK1:       cond.end:
1215 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
1216 // CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
1217 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1218 // CHECK1-NEXT:    store i32 [[TMP12]], ptr [[DOTOMP_IV]], align 4
1219 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1220 // CHECK1:       omp.inner.for.cond:
1221 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35:![0-9]+]]
1222 // CHECK1-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP35]]
1223 // CHECK1-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
1224 // CHECK1-NEXT:    br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1225 // CHECK1:       omp.inner.for.body:
1226 // CHECK1-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35]]
1227 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
1228 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1229 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP35]]
1230 // CHECK1-NEXT:    [[TMP16:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP35]]
1231 // CHECK1-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1
1232 // CHECK1-NEXT:    store i32 [[ADD6]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP35]]
1233 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 2
1234 // CHECK1-NEXT:    [[TMP17:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP35]]
1235 // CHECK1-NEXT:    [[CONV:%.*]] = fpext float [[TMP17]] to double
1236 // CHECK1-NEXT:    [[ADD7:%.*]] = fadd double [[CONV]], 1.000000e+00
1237 // CHECK1-NEXT:    [[CONV8:%.*]] = fptrunc double [[ADD7]] to float
1238 // CHECK1-NEXT:    store float [[CONV8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP35]]
1239 // CHECK1-NEXT:    [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 3
1240 // CHECK1-NEXT:    [[TMP18:%.*]] = load float, ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP35]]
1241 // CHECK1-NEXT:    [[CONV10:%.*]] = fpext float [[TMP18]] to double
1242 // CHECK1-NEXT:    [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00
1243 // CHECK1-NEXT:    [[CONV12:%.*]] = fptrunc double [[ADD11]] to float
1244 // CHECK1-NEXT:    store float [[CONV12]], ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP35]]
1245 // CHECK1-NEXT:    [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 1
1246 // CHECK1-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX13]], i64 0, i64 2
1247 // CHECK1-NEXT:    [[TMP19:%.*]] = load double, ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP35]]
1248 // CHECK1-NEXT:    [[ADD15:%.*]] = fadd double [[TMP19]], 1.000000e+00
1249 // CHECK1-NEXT:    store double [[ADD15]], ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP35]]
1250 // CHECK1-NEXT:    [[TMP20:%.*]] = mul nsw i64 1, [[TMP5]]
1251 // CHECK1-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i64 [[TMP20]]
1252 // CHECK1-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX16]], i64 3
1253 // CHECK1-NEXT:    [[TMP21:%.*]] = load double, ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP35]]
1254 // CHECK1-NEXT:    [[ADD18:%.*]] = fadd double [[TMP21]], 1.000000e+00
1255 // CHECK1-NEXT:    store double [[ADD18]], ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP35]]
1256 // CHECK1-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0
1257 // CHECK1-NEXT:    [[TMP22:%.*]] = load i64, ptr [[X]], align 8, !llvm.access.group [[ACC_GRP35]]
1258 // CHECK1-NEXT:    [[ADD19:%.*]] = add nsw i64 [[TMP22]], 1
1259 // CHECK1-NEXT:    store i64 [[ADD19]], ptr [[X]], align 8, !llvm.access.group [[ACC_GRP35]]
1260 // CHECK1-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1
1261 // CHECK1-NEXT:    [[TMP23:%.*]] = load i8, ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP35]]
1262 // CHECK1-NEXT:    [[CONV20:%.*]] = sext i8 [[TMP23]] to i32
1263 // CHECK1-NEXT:    [[ADD21:%.*]] = add nsw i32 [[CONV20]], 1
1264 // CHECK1-NEXT:    [[CONV22:%.*]] = trunc i32 [[ADD21]] to i8
1265 // CHECK1-NEXT:    store i8 [[CONV22]], ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP35]]
1266 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1267 // CHECK1:       omp.body.continue:
1268 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1269 // CHECK1:       omp.inner.for.inc:
1270 // CHECK1-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35]]
1271 // CHECK1-NEXT:    [[ADD23:%.*]] = add nsw i32 [[TMP24]], 1
1272 // CHECK1-NEXT:    store i32 [[ADD23]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35]]
1273 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP36:![0-9]+]]
1274 // CHECK1:       omp.inner.for.end:
1275 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1276 // CHECK1:       omp.loop.exit:
1277 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP9]])
1278 // CHECK1-NEXT:    [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
1279 // CHECK1-NEXT:    [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
1280 // CHECK1-NEXT:    br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1281 // CHECK1:       .omp.final.then:
1282 // CHECK1-NEXT:    store i32 10, ptr [[I]], align 4
1283 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
1284 // CHECK1:       .omp.final.done:
1285 // CHECK1-NEXT:    ret void
1286 //
1287 //
1288 // CHECK1-LABEL: define {{[^@]+}}@_Z3bari
1289 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
1290 // CHECK1-NEXT:  entry:
1291 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
1292 // CHECK1-NEXT:    [[A:%.*]] = alloca i32, align 4
1293 // CHECK1-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
1294 // CHECK1-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
1295 // CHECK1-NEXT:    store i32 0, ptr [[A]], align 4
1296 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
1297 // CHECK1-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]])
1298 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A]], align 4
1299 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
1300 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[A]], align 4
1301 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
1302 // CHECK1-NEXT:    [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(ptr noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]])
1303 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A]], align 4
1304 // CHECK1-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
1305 // CHECK1-NEXT:    store i32 [[ADD2]], ptr [[A]], align 4
1306 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
1307 // CHECK1-NEXT:    [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]])
1308 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[A]], align 4
1309 // CHECK1-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
1310 // CHECK1-NEXT:    store i32 [[ADD4]], ptr [[A]], align 4
1311 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4
1312 // CHECK1-NEXT:    [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]])
1313 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[A]], align 4
1314 // CHECK1-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
1315 // CHECK1-NEXT:    store i32 [[ADD6]], ptr [[A]], align 4
1316 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A]], align 4
1317 // CHECK1-NEXT:    ret i32 [[TMP8]]
1318 //
1319 //
1320 // CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
1321 // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
1322 // CHECK1-NEXT:  entry:
1323 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1324 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
1325 // CHECK1-NEXT:    [[B:%.*]] = alloca i32, align 4
1326 // CHECK1-NEXT:    [[SAVED_STACK:%.*]] = alloca ptr, align 8
1327 // CHECK1-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
1328 // CHECK1-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
1329 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 8
1330 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 8
1331 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 8
1332 // CHECK1-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8
1333 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1334 // CHECK1-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1335 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1336 // CHECK1-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
1337 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1338 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
1339 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
1340 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[B]], align 4
1341 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
1342 // CHECK1-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
1343 // CHECK1-NEXT:    [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()
1344 // CHECK1-NEXT:    store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8
1345 // CHECK1-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
1346 // CHECK1-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
1347 // CHECK1-NEXT:    store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8
1348 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[B]], align 4
1349 // CHECK1-NEXT:    store i32 [[TMP5]], ptr [[B_CASTED]], align 4
1350 // CHECK1-NEXT:    [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 8
1351 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 4
1352 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60
1353 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
1354 // CHECK1:       omp_if.then:
1355 // CHECK1-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0
1356 // CHECK1-NEXT:    [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]]
1357 // CHECK1-NEXT:    [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2
1358 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes.7, i64 40, i1 false)
1359 // CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1360 // CHECK1-NEXT:    store ptr [[THIS1]], ptr [[TMP10]], align 8
1361 // CHECK1-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1362 // CHECK1-NEXT:    store ptr [[A]], ptr [[TMP11]], align 8
1363 // CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
1364 // CHECK1-NEXT:    store ptr null, ptr [[TMP12]], align 8
1365 // CHECK1-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1366 // CHECK1-NEXT:    store i64 [[TMP6]], ptr [[TMP13]], align 8
1367 // CHECK1-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1368 // CHECK1-NEXT:    store i64 [[TMP6]], ptr [[TMP14]], align 8
1369 // CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
1370 // CHECK1-NEXT:    store ptr null, ptr [[TMP15]], align 8
1371 // CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1372 // CHECK1-NEXT:    store i64 2, ptr [[TMP16]], align 8
1373 // CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1374 // CHECK1-NEXT:    store i64 2, ptr [[TMP17]], align 8
1375 // CHECK1-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
1376 // CHECK1-NEXT:    store ptr null, ptr [[TMP18]], align 8
1377 // CHECK1-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1378 // CHECK1-NEXT:    store i64 [[TMP2]], ptr [[TMP19]], align 8
1379 // CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1380 // CHECK1-NEXT:    store i64 [[TMP2]], ptr [[TMP20]], align 8
1381 // CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
1382 // CHECK1-NEXT:    store ptr null, ptr [[TMP21]], align 8
1383 // CHECK1-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
1384 // CHECK1-NEXT:    store ptr [[VLA]], ptr [[TMP22]], align 8
1385 // CHECK1-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4
1386 // CHECK1-NEXT:    store ptr [[VLA]], ptr [[TMP23]], align 8
1387 // CHECK1-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 4
1388 // CHECK1-NEXT:    store i64 [[TMP9]], ptr [[TMP24]], align 8
1389 // CHECK1-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
1390 // CHECK1-NEXT:    store ptr null, ptr [[TMP25]], align 8
1391 // CHECK1-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1392 // CHECK1-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1393 // CHECK1-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0
1394 // CHECK1-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
1395 // CHECK1-NEXT:    store i32 2, ptr [[TMP29]], align 4
1396 // CHECK1-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
1397 // CHECK1-NEXT:    store i32 5, ptr [[TMP30]], align 4
1398 // CHECK1-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
1399 // CHECK1-NEXT:    store ptr [[TMP26]], ptr [[TMP31]], align 8
1400 // CHECK1-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
1401 // CHECK1-NEXT:    store ptr [[TMP27]], ptr [[TMP32]], align 8
1402 // CHECK1-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
1403 // CHECK1-NEXT:    store ptr [[TMP28]], ptr [[TMP33]], align 8
1404 // CHECK1-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
1405 // CHECK1-NEXT:    store ptr @.offload_maptypes.8, ptr [[TMP34]], align 8
1406 // CHECK1-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
1407 // CHECK1-NEXT:    store ptr null, ptr [[TMP35]], align 8
1408 // CHECK1-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
1409 // CHECK1-NEXT:    store ptr null, ptr [[TMP36]], align 8
1410 // CHECK1-NEXT:    [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
1411 // CHECK1-NEXT:    store i64 10, ptr [[TMP37]], align 8
1412 // CHECK1-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
1413 // CHECK1-NEXT:    store i64 0, ptr [[TMP38]], align 8
1414 // CHECK1-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
1415 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP39]], align 4
1416 // CHECK1-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
1417 // CHECK1-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP40]], align 4
1418 // CHECK1-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
1419 // CHECK1-NEXT:    store i32 0, ptr [[TMP41]], align 4
1420 // CHECK1-NEXT:    [[TMP42:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.region_id, ptr [[KERNEL_ARGS]])
1421 // CHECK1-NEXT:    [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0
1422 // CHECK1-NEXT:    br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1423 // CHECK1:       omp_offload.failed:
1424 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215(ptr [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], ptr [[VLA]]) #[[ATTR3]]
1425 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
1426 // CHECK1:       omp_offload.cont:
1427 // CHECK1-NEXT:    br label [[OMP_IF_END:%.*]]
1428 // CHECK1:       omp_if.else:
1429 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215(ptr [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], ptr [[VLA]]) #[[ATTR3]]
1430 // CHECK1-NEXT:    br label [[OMP_IF_END]]
1431 // CHECK1:       omp_if.end:
1432 // CHECK1-NEXT:    [[TMP44:%.*]] = mul nsw i64 1, [[TMP2]]
1433 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP44]]
1434 // CHECK1-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1
1435 // CHECK1-NEXT:    [[TMP45:%.*]] = load i16, ptr [[ARRAYIDX2]], align 2
1436 // CHECK1-NEXT:    [[CONV:%.*]] = sext i16 [[TMP45]] to i32
1437 // CHECK1-NEXT:    [[TMP46:%.*]] = load i32, ptr [[B]], align 4
1438 // CHECK1-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP46]]
1439 // CHECK1-NEXT:    [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
1440 // CHECK1-NEXT:    call void @llvm.stackrestore.p0(ptr [[TMP47]])
1441 // CHECK1-NEXT:    ret i32 [[ADD3]]
1442 //
1443 //
1444 // CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici
1445 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
1446 // CHECK1-NEXT:  entry:
1447 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
1448 // CHECK1-NEXT:    [[A:%.*]] = alloca i32, align 4
1449 // CHECK1-NEXT:    [[AA:%.*]] = alloca i16, align 2
1450 // CHECK1-NEXT:    [[AAA:%.*]] = alloca i8, align 1
1451 // CHECK1-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
1452 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
1453 // CHECK1-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8
1454 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
1455 // CHECK1-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
1456 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 8
1457 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 8
1458 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 8
1459 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1460 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
1461 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
1462 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
1463 // CHECK1-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1464 // CHECK1-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
1465 // CHECK1-NEXT:    store i32 0, ptr [[A]], align 4
1466 // CHECK1-NEXT:    store i16 0, ptr [[AA]], align 2
1467 // CHECK1-NEXT:    store i8 0, ptr [[AAA]], align 1
1468 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A]], align 4
1469 // CHECK1-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 4
1470 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8
1471 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
1472 // CHECK1-NEXT:    store i32 [[TMP2]], ptr [[N_CASTED]], align 4
1473 // CHECK1-NEXT:    [[TMP3:%.*]] = load i64, ptr [[N_CASTED]], align 8
1474 // CHECK1-NEXT:    [[TMP4:%.*]] = load i16, ptr [[AA]], align 2
1475 // CHECK1-NEXT:    store i16 [[TMP4]], ptr [[AA_CASTED]], align 2
1476 // CHECK1-NEXT:    [[TMP5:%.*]] = load i64, ptr [[AA_CASTED]], align 8
1477 // CHECK1-NEXT:    [[TMP6:%.*]] = load i8, ptr [[AAA]], align 1
1478 // CHECK1-NEXT:    store i8 [[TMP6]], ptr [[AAA_CASTED]], align 1
1479 // CHECK1-NEXT:    [[TMP7:%.*]] = load i64, ptr [[AAA_CASTED]], align 8
1480 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[N_ADDR]], align 4
1481 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 50
1482 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
1483 // CHECK1:       omp_if.then:
1484 // CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1485 // CHECK1-NEXT:    store i64 [[TMP1]], ptr [[TMP9]], align 8
1486 // CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1487 // CHECK1-NEXT:    store i64 [[TMP1]], ptr [[TMP10]], align 8
1488 // CHECK1-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
1489 // CHECK1-NEXT:    store ptr null, ptr [[TMP11]], align 8
1490 // CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1491 // CHECK1-NEXT:    store i64 [[TMP3]], ptr [[TMP12]], align 8
1492 // CHECK1-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1493 // CHECK1-NEXT:    store i64 [[TMP3]], ptr [[TMP13]], align 8
1494 // CHECK1-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
1495 // CHECK1-NEXT:    store ptr null, ptr [[TMP14]], align 8
1496 // CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1497 // CHECK1-NEXT:    store i64 [[TMP5]], ptr [[TMP15]], align 8
1498 // CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1499 // CHECK1-NEXT:    store i64 [[TMP5]], ptr [[TMP16]], align 8
1500 // CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
1501 // CHECK1-NEXT:    store ptr null, ptr [[TMP17]], align 8
1502 // CHECK1-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1503 // CHECK1-NEXT:    store i64 [[TMP7]], ptr [[TMP18]], align 8
1504 // CHECK1-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1505 // CHECK1-NEXT:    store i64 [[TMP7]], ptr [[TMP19]], align 8
1506 // CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
1507 // CHECK1-NEXT:    store ptr null, ptr [[TMP20]], align 8
1508 // CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
1509 // CHECK1-NEXT:    store ptr [[B]], ptr [[TMP21]], align 8
1510 // CHECK1-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4
1511 // CHECK1-NEXT:    store ptr [[B]], ptr [[TMP22]], align 8
1512 // CHECK1-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
1513 // CHECK1-NEXT:    store ptr null, ptr [[TMP23]], align 8
1514 // CHECK1-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1515 // CHECK1-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1516 // CHECK1-NEXT:    [[TMP26:%.*]] = load i32, ptr [[A]], align 4
1517 // CHECK1-NEXT:    store i32 [[TMP26]], ptr [[DOTCAPTURE_EXPR_]], align 4
1518 // CHECK1-NEXT:    [[TMP27:%.*]] = load i32, ptr [[N_ADDR]], align 4
1519 // CHECK1-NEXT:    store i32 [[TMP27]], ptr [[DOTCAPTURE_EXPR_1]], align 4
1520 // CHECK1-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
1521 // CHECK1-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1522 // CHECK1-NEXT:    [[SUB:%.*]] = sub i32 [[TMP28]], [[TMP29]]
1523 // CHECK1-NEXT:    [[SUB3:%.*]] = sub i32 [[SUB]], 1
1524 // CHECK1-NEXT:    [[ADD:%.*]] = add i32 [[SUB3]], 1
1525 // CHECK1-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
1526 // CHECK1-NEXT:    [[SUB4:%.*]] = sub i32 [[DIV]], 1
1527 // CHECK1-NEXT:    store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 4
1528 // CHECK1-NEXT:    [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
1529 // CHECK1-NEXT:    [[ADD5:%.*]] = add i32 [[TMP30]], 1
1530 // CHECK1-NEXT:    [[TMP31:%.*]] = zext i32 [[ADD5]] to i64
1531 // CHECK1-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
1532 // CHECK1-NEXT:    store i32 2, ptr [[TMP32]], align 4
1533 // CHECK1-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
1534 // CHECK1-NEXT:    store i32 5, ptr [[TMP33]], align 4
1535 // CHECK1-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
1536 // CHECK1-NEXT:    store ptr [[TMP24]], ptr [[TMP34]], align 8
1537 // CHECK1-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
1538 // CHECK1-NEXT:    store ptr [[TMP25]], ptr [[TMP35]], align 8
1539 // CHECK1-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
1540 // CHECK1-NEXT:    store ptr @.offload_sizes.9, ptr [[TMP36]], align 8
1541 // CHECK1-NEXT:    [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
1542 // CHECK1-NEXT:    store ptr @.offload_maptypes.10, ptr [[TMP37]], align 8
1543 // CHECK1-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
1544 // CHECK1-NEXT:    store ptr null, ptr [[TMP38]], align 8
1545 // CHECK1-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
1546 // CHECK1-NEXT:    store ptr null, ptr [[TMP39]], align 8
1547 // CHECK1-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
1548 // CHECK1-NEXT:    store i64 [[TMP31]], ptr [[TMP40]], align 8
1549 // CHECK1-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
1550 // CHECK1-NEXT:    store i64 0, ptr [[TMP41]], align 8
1551 // CHECK1-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
1552 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP42]], align 4
1553 // CHECK1-NEXT:    [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
1554 // CHECK1-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP43]], align 4
1555 // CHECK1-NEXT:    [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
1556 // CHECK1-NEXT:    store i32 0, ptr [[TMP44]], align 4
1557 // CHECK1-NEXT:    [[TMP45:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.region_id, ptr [[KERNEL_ARGS]])
1558 // CHECK1-NEXT:    [[TMP46:%.*]] = icmp ne i32 [[TMP45]], 0
1559 // CHECK1-NEXT:    br i1 [[TMP46]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1560 // CHECK1:       omp_offload.failed:
1561 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], i64 [[TMP7]], ptr [[B]]) #[[ATTR3]]
1562 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
1563 // CHECK1:       omp_offload.cont:
1564 // CHECK1-NEXT:    br label [[OMP_IF_END:%.*]]
1565 // CHECK1:       omp_if.else:
1566 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], i64 [[TMP7]], ptr [[B]]) #[[ATTR3]]
1567 // CHECK1-NEXT:    br label [[OMP_IF_END]]
1568 // CHECK1:       omp_if.end:
1569 // CHECK1-NEXT:    [[TMP47:%.*]] = load i32, ptr [[A]], align 4
1570 // CHECK1-NEXT:    ret i32 [[TMP47]]
1571 //
1572 //
1573 // CHECK1-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
1574 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
1575 // CHECK1-NEXT:  entry:
1576 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
1577 // CHECK1-NEXT:    [[A:%.*]] = alloca i32, align 4
1578 // CHECK1-NEXT:    [[AA:%.*]] = alloca i16, align 2
1579 // CHECK1-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
1580 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
1581 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
1582 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8
1583 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 8
1584 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 8
1585 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1586 // CHECK1-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1587 // CHECK1-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
1588 // CHECK1-NEXT:    store i32 0, ptr [[A]], align 4
1589 // CHECK1-NEXT:    store i16 0, ptr [[AA]], align 2
1590 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A]], align 4
1591 // CHECK1-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 4
1592 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8
1593 // CHECK1-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA]], align 2
1594 // CHECK1-NEXT:    store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
1595 // CHECK1-NEXT:    [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8
1596 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
1597 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
1598 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
1599 // CHECK1:       omp_if.then:
1600 // CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1601 // CHECK1-NEXT:    store i64 [[TMP1]], ptr [[TMP5]], align 8
1602 // CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1603 // CHECK1-NEXT:    store i64 [[TMP1]], ptr [[TMP6]], align 8
1604 // CHECK1-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
1605 // CHECK1-NEXT:    store ptr null, ptr [[TMP7]], align 8
1606 // CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1607 // CHECK1-NEXT:    store i64 [[TMP3]], ptr [[TMP8]], align 8
1608 // CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1609 // CHECK1-NEXT:    store i64 [[TMP3]], ptr [[TMP9]], align 8
1610 // CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
1611 // CHECK1-NEXT:    store ptr null, ptr [[TMP10]], align 8
1612 // CHECK1-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1613 // CHECK1-NEXT:    store ptr [[B]], ptr [[TMP11]], align 8
1614 // CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1615 // CHECK1-NEXT:    store ptr [[B]], ptr [[TMP12]], align 8
1616 // CHECK1-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
1617 // CHECK1-NEXT:    store ptr null, ptr [[TMP13]], align 8
1618 // CHECK1-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1619 // CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1620 // CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
1621 // CHECK1-NEXT:    store i32 2, ptr [[TMP16]], align 4
1622 // CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
1623 // CHECK1-NEXT:    store i32 3, ptr [[TMP17]], align 4
1624 // CHECK1-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
1625 // CHECK1-NEXT:    store ptr [[TMP14]], ptr [[TMP18]], align 8
1626 // CHECK1-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
1627 // CHECK1-NEXT:    store ptr [[TMP15]], ptr [[TMP19]], align 8
1628 // CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
1629 // CHECK1-NEXT:    store ptr @.offload_sizes.11, ptr [[TMP20]], align 8
1630 // CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
1631 // CHECK1-NEXT:    store ptr @.offload_maptypes.12, ptr [[TMP21]], align 8
1632 // CHECK1-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
1633 // CHECK1-NEXT:    store ptr null, ptr [[TMP22]], align 8
1634 // CHECK1-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
1635 // CHECK1-NEXT:    store ptr null, ptr [[TMP23]], align 8
1636 // CHECK1-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
1637 // CHECK1-NEXT:    store i64 10, ptr [[TMP24]], align 8
1638 // CHECK1-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
1639 // CHECK1-NEXT:    store i64 0, ptr [[TMP25]], align 8
1640 // CHECK1-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
1641 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP26]], align 4
1642 // CHECK1-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
1643 // CHECK1-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP27]], align 4
1644 // CHECK1-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
1645 // CHECK1-NEXT:    store i32 0, ptr [[TMP28]], align 4
1646 // CHECK1-NEXT:    [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.region_id, ptr [[KERNEL_ARGS]])
1647 // CHECK1-NEXT:    [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
1648 // CHECK1-NEXT:    br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1649 // CHECK1:       omp_offload.failed:
1650 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR3]]
1651 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
1652 // CHECK1:       omp_offload.cont:
1653 // CHECK1-NEXT:    br label [[OMP_IF_END:%.*]]
1654 // CHECK1:       omp_if.else:
1655 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR3]]
1656 // CHECK1-NEXT:    br label [[OMP_IF_END]]
1657 // CHECK1:       omp_if.end:
1658 // CHECK1-NEXT:    [[TMP31:%.*]] = load i32, ptr [[A]], align 4
1659 // CHECK1-NEXT:    ret i32 [[TMP31]]
1660 //
1661 //
1662 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215
1663 // CHECK1-SAME: (ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
1664 // CHECK1-NEXT:  entry:
1665 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1666 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
1667 // CHECK1-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
1668 // CHECK1-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
1669 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
1670 // CHECK1-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
1671 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1672 // CHECK1-NEXT:    store i64 [[B]], ptr [[B_ADDR]], align 8
1673 // CHECK1-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
1674 // CHECK1-NEXT:    store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
1675 // CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
1676 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1677 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
1678 // CHECK1-NEXT:    [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
1679 // CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
1680 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4
1681 // CHECK1-NEXT:    store i32 [[TMP4]], ptr [[B_CASTED]], align 4
1682 // CHECK1-NEXT:    [[TMP5:%.*]] = load i64, ptr [[B_CASTED]], align 8
1683 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.omp_outlined, ptr [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], ptr [[TMP3]])
1684 // CHECK1-NEXT:    ret void
1685 //
1686 //
1687 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.omp_outlined
1688 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
1689 // CHECK1-NEXT:  entry:
1690 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1691 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1692 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1693 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
1694 // CHECK1-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
1695 // CHECK1-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
1696 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
1697 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1698 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1699 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1700 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1701 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1702 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1703 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
1704 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1705 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1706 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1707 // CHECK1-NEXT:    store i64 [[B]], ptr [[B_ADDR]], align 8
1708 // CHECK1-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
1709 // CHECK1-NEXT:    store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
1710 // CHECK1-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
1711 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1712 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
1713 // CHECK1-NEXT:    [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
1714 // CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
1715 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
1716 // CHECK1-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4
1717 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1718 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1719 // CHECK1-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1720 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
1721 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
1722 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1723 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9
1724 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1725 // CHECK1:       cond.true:
1726 // CHECK1-NEXT:    br label [[COND_END:%.*]]
1727 // CHECK1:       cond.false:
1728 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1729 // CHECK1-NEXT:    br label [[COND_END]]
1730 // CHECK1:       cond.end:
1731 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
1732 // CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
1733 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1734 // CHECK1-NEXT:    store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4
1735 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1736 // CHECK1:       omp.inner.for.cond:
1737 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP38:![0-9]+]]
1738 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP38]]
1739 // CHECK1-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
1740 // CHECK1-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1741 // CHECK1:       omp.inner.for.body:
1742 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP38]]
1743 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
1744 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1745 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP38]]
1746 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP38]]
1747 // CHECK1-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP12]] to double
1748 // CHECK1-NEXT:    [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00
1749 // CHECK1-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0
1750 // CHECK1-NEXT:    store double [[ADD4]], ptr [[A]], align 8, !llvm.access.group [[ACC_GRP38]]
1751 // CHECK1-NEXT:    [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0
1752 // CHECK1-NEXT:    [[TMP13:%.*]] = load double, ptr [[A5]], align 8, !llvm.access.group [[ACC_GRP38]]
1753 // CHECK1-NEXT:    [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
1754 // CHECK1-NEXT:    store double [[INC]], ptr [[A5]], align 8, !llvm.access.group [[ACC_GRP38]]
1755 // CHECK1-NEXT:    [[CONV6:%.*]] = fptosi double [[INC]] to i16
1756 // CHECK1-NEXT:    [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]]
1757 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i64 [[TMP14]]
1758 // CHECK1-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1
1759 // CHECK1-NEXT:    store i16 [[CONV6]], ptr [[ARRAYIDX7]], align 2, !llvm.access.group [[ACC_GRP38]]
1760 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1761 // CHECK1:       omp.body.continue:
1762 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1763 // CHECK1:       omp.inner.for.inc:
1764 // CHECK1-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP38]]
1765 // CHECK1-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1
1766 // CHECK1-NEXT:    store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP38]]
1767 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP39:![0-9]+]]
1768 // CHECK1:       omp.inner.for.end:
1769 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1770 // CHECK1:       omp.loop.exit:
1771 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])
1772 // CHECK1-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
1773 // CHECK1-NEXT:    [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
1774 // CHECK1-NEXT:    br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1775 // CHECK1:       .omp.final.then:
1776 // CHECK1-NEXT:    store i32 10, ptr [[I]], align 4
1777 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
1778 // CHECK1:       .omp.final.done:
1779 // CHECK1-NEXT:    ret void
1780 //
1781 //
1782 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197
1783 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
1784 // CHECK1-NEXT:  entry:
1785 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1786 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
1787 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
1788 // CHECK1-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
1789 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
1790 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
1791 // CHECK1-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8
1792 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
1793 // CHECK1-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
1794 // CHECK1-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
1795 // CHECK1-NEXT:    store i64 [[N]], ptr [[N_ADDR]], align 8
1796 // CHECK1-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
1797 // CHECK1-NEXT:    store i64 [[AAA]], ptr [[AAA_ADDR]], align 8
1798 // CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
1799 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
1800 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
1801 // CHECK1-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 4
1802 // CHECK1-NEXT:    [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8
1803 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4
1804 // CHECK1-NEXT:    store i32 [[TMP3]], ptr [[N_CASTED]], align 4
1805 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8
1806 // CHECK1-NEXT:    [[TMP5:%.*]] = load i16, ptr [[AA_ADDR]], align 2
1807 // CHECK1-NEXT:    store i16 [[TMP5]], ptr [[AA_CASTED]], align 2
1808 // CHECK1-NEXT:    [[TMP6:%.*]] = load i64, ptr [[AA_CASTED]], align 8
1809 // CHECK1-NEXT:    [[TMP7:%.*]] = load i8, ptr [[AAA_ADDR]], align 1
1810 // CHECK1-NEXT:    store i8 [[TMP7]], ptr [[AAA_CASTED]], align 1
1811 // CHECK1-NEXT:    [[TMP8:%.*]] = load i64, ptr [[AAA_CASTED]], align 8
1812 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], ptr [[TMP0]])
1813 // CHECK1-NEXT:    ret void
1814 //
1815 //
1816 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.omp_outlined
1817 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
1818 // CHECK1-NEXT:  entry:
1819 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1820 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1821 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1822 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
1823 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
1824 // CHECK1-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
1825 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
1826 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1827 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1828 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
1829 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
1830 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
1831 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
1832 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1833 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1834 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1835 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1836 // CHECK1-NEXT:    [[I5:%.*]] = alloca i32, align 4
1837 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1838 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1839 // CHECK1-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
1840 // CHECK1-NEXT:    store i64 [[N]], ptr [[N_ADDR]], align 8
1841 // CHECK1-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
1842 // CHECK1-NEXT:    store i64 [[AAA]], ptr [[AAA_ADDR]], align 8
1843 // CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
1844 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
1845 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
1846 // CHECK1-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
1847 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
1848 // CHECK1-NEXT:    store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
1849 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
1850 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1851 // CHECK1-NEXT:    [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
1852 // CHECK1-NEXT:    [[SUB3:%.*]] = sub i32 [[SUB]], 1
1853 // CHECK1-NEXT:    [[ADD:%.*]] = add i32 [[SUB3]], 1
1854 // CHECK1-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
1855 // CHECK1-NEXT:    [[SUB4:%.*]] = sub i32 [[DIV]], 1
1856 // CHECK1-NEXT:    store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 4
1857 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1858 // CHECK1-NEXT:    store i32 [[TMP5]], ptr [[I]], align 4
1859 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1860 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
1861 // CHECK1-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
1862 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
1863 // CHECK1:       omp.precond.then:
1864 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
1865 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
1866 // CHECK1-NEXT:    store i32 [[TMP8]], ptr [[DOTOMP_UB]], align 4
1867 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1868 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1869 // CHECK1-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1870 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4
1871 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4u(ptr @[[GLOB1]], i32 [[TMP10]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
1872 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1873 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
1874 // CHECK1-NEXT:    [[CMP6:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]]
1875 // CHECK1-NEXT:    br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1876 // CHECK1:       cond.true:
1877 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
1878 // CHECK1-NEXT:    br label [[COND_END:%.*]]
1879 // CHECK1:       cond.false:
1880 // CHECK1-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1881 // CHECK1-NEXT:    br label [[COND_END]]
1882 // CHECK1:       cond.end:
1883 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ]
1884 // CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
1885 // CHECK1-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1886 // CHECK1-NEXT:    store i32 [[TMP15]], ptr [[DOTOMP_IV]], align 4
1887 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1888 // CHECK1:       omp.inner.for.cond:
1889 // CHECK1-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP41:![0-9]+]]
1890 // CHECK1-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP41]]
1891 // CHECK1-NEXT:    [[ADD7:%.*]] = add i32 [[TMP17]], 1
1892 // CHECK1-NEXT:    [[CMP8:%.*]] = icmp ult i32 [[TMP16]], [[ADD7]]
1893 // CHECK1-NEXT:    br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1894 // CHECK1:       omp.inner.for.body:
1895 // CHECK1-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group [[ACC_GRP41]]
1896 // CHECK1-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP41]]
1897 // CHECK1-NEXT:    [[MUL:%.*]] = mul i32 [[TMP19]], 1
1898 // CHECK1-NEXT:    [[ADD9:%.*]] = add i32 [[TMP18]], [[MUL]]
1899 // CHECK1-NEXT:    store i32 [[ADD9]], ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP41]]
1900 // CHECK1-NEXT:    [[TMP20:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP41]]
1901 // CHECK1-NEXT:    [[ADD10:%.*]] = add nsw i32 [[TMP20]], 1
1902 // CHECK1-NEXT:    store i32 [[ADD10]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP41]]
1903 // CHECK1-NEXT:    [[TMP21:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP41]]
1904 // CHECK1-NEXT:    [[CONV:%.*]] = sext i16 [[TMP21]] to i32
1905 // CHECK1-NEXT:    [[ADD11:%.*]] = add nsw i32 [[CONV]], 1
1906 // CHECK1-NEXT:    [[CONV12:%.*]] = trunc i32 [[ADD11]] to i16
1907 // CHECK1-NEXT:    store i16 [[CONV12]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP41]]
1908 // CHECK1-NEXT:    [[TMP22:%.*]] = load i8, ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP41]]
1909 // CHECK1-NEXT:    [[CONV13:%.*]] = sext i8 [[TMP22]] to i32
1910 // CHECK1-NEXT:    [[ADD14:%.*]] = add nsw i32 [[CONV13]], 1
1911 // CHECK1-NEXT:    [[CONV15:%.*]] = trunc i32 [[ADD14]] to i8
1912 // CHECK1-NEXT:    store i8 [[CONV15]], ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP41]]
1913 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2
1914 // CHECK1-NEXT:    [[TMP23:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP41]]
1915 // CHECK1-NEXT:    [[ADD16:%.*]] = add nsw i32 [[TMP23]], 1
1916 // CHECK1-NEXT:    store i32 [[ADD16]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP41]]
1917 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1918 // CHECK1:       omp.body.continue:
1919 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1920 // CHECK1:       omp.inner.for.inc:
1921 // CHECK1-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP41]]
1922 // CHECK1-NEXT:    [[ADD17:%.*]] = add i32 [[TMP24]], 1
1923 // CHECK1-NEXT:    store i32 [[ADD17]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP41]]
1924 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP42:![0-9]+]]
1925 // CHECK1:       omp.inner.for.end:
1926 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1927 // CHECK1:       omp.loop.exit:
1928 // CHECK1-NEXT:    [[TMP25:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1929 // CHECK1-NEXT:    [[TMP26:%.*]] = load i32, ptr [[TMP25]], align 4
1930 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP26]])
1931 // CHECK1-NEXT:    [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
1932 // CHECK1-NEXT:    [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
1933 // CHECK1-NEXT:    br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1934 // CHECK1:       .omp.final.then:
1935 // CHECK1-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1936 // CHECK1-NEXT:    [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
1937 // CHECK1-NEXT:    [[TMP31:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1938 // CHECK1-NEXT:    [[SUB18:%.*]] = sub i32 [[TMP30]], [[TMP31]]
1939 // CHECK1-NEXT:    [[SUB19:%.*]] = sub i32 [[SUB18]], 1
1940 // CHECK1-NEXT:    [[ADD20:%.*]] = add i32 [[SUB19]], 1
1941 // CHECK1-NEXT:    [[DIV21:%.*]] = udiv i32 [[ADD20]], 1
1942 // CHECK1-NEXT:    [[MUL22:%.*]] = mul i32 [[DIV21]], 1
1943 // CHECK1-NEXT:    [[ADD23:%.*]] = add i32 [[TMP29]], [[MUL22]]
1944 // CHECK1-NEXT:    store i32 [[ADD23]], ptr [[I5]], align 4
1945 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
1946 // CHECK1:       .omp.final.done:
1947 // CHECK1-NEXT:    br label [[OMP_PRECOND_END]]
1948 // CHECK1:       omp.precond.end:
1949 // CHECK1-NEXT:    ret void
1950 //
1951 //
1952 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180
1953 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
1954 // CHECK1-NEXT:  entry:
1955 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1956 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
1957 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
1958 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
1959 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
1960 // CHECK1-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
1961 // CHECK1-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
1962 // CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
1963 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
1964 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
1965 // CHECK1-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 4
1966 // CHECK1-NEXT:    [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8
1967 // CHECK1-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
1968 // CHECK1-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
1969 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8
1970 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], ptr [[TMP0]])
1971 // CHECK1-NEXT:    ret void
1972 //
1973 //
1974 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.omp_outlined
1975 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
1976 // CHECK1-NEXT:  entry:
1977 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1978 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1979 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1980 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
1981 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
1982 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1983 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1984 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1985 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1986 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1987 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1988 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
1989 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1990 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1991 // CHECK1-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
1992 // CHECK1-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
1993 // CHECK1-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
1994 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
1995 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
1996 // CHECK1-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4
1997 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1998 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1999 // CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
2000 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
2001 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
2002 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2003 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
2004 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2005 // CHECK1:       cond.true:
2006 // CHECK1-NEXT:    br label [[COND_END:%.*]]
2007 // CHECK1:       cond.false:
2008 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2009 // CHECK1-NEXT:    br label [[COND_END]]
2010 // CHECK1:       cond.end:
2011 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
2012 // CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
2013 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
2014 // CHECK1-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
2015 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2016 // CHECK1:       omp.inner.for.cond:
2017 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP44:![0-9]+]]
2018 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP44]]
2019 // CHECK1-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
2020 // CHECK1-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2021 // CHECK1:       omp.inner.for.body:
2022 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP44]]
2023 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
2024 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2025 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP44]]
2026 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP44]]
2027 // CHECK1-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
2028 // CHECK1-NEXT:    store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP44]]
2029 // CHECK1-NEXT:    [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP44]]
2030 // CHECK1-NEXT:    [[CONV:%.*]] = sext i16 [[TMP10]] to i32
2031 // CHECK1-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV]], 1
2032 // CHECK1-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
2033 // CHECK1-NEXT:    store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP44]]
2034 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2
2035 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP44]]
2036 // CHECK1-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1
2037 // CHECK1-NEXT:    store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP44]]
2038 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2039 // CHECK1:       omp.body.continue:
2040 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2041 // CHECK1:       omp.inner.for.inc:
2042 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP44]]
2043 // CHECK1-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP12]], 1
2044 // CHECK1-NEXT:    store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP44]]
2045 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP45:![0-9]+]]
2046 // CHECK1:       omp.inner.for.end:
2047 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2048 // CHECK1:       omp.loop.exit:
2049 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])
2050 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
2051 // CHECK1-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
2052 // CHECK1-NEXT:    br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2053 // CHECK1:       .omp.final.then:
2054 // CHECK1-NEXT:    store i32 10, ptr [[I]], align 4
2055 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
2056 // CHECK1:       .omp.final.done:
2057 // CHECK1-NEXT:    ret void
2058 //
2059 //
2060 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
2061 // CHECK1-SAME: () #[[ATTR4]] {
2062 // CHECK1-NEXT:  entry:
2063 // CHECK1-NEXT:    call void @__tgt_register_requires(i64 1)
2064 // CHECK1-NEXT:    ret void
2065 //
2066 //
2067 // CHECK3-LABEL: define {{[^@]+}}@_Z3fooi
2068 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] {
2069 // CHECK3-NEXT:  entry:
2070 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
2071 // CHECK3-NEXT:    [[A:%.*]] = alloca i32, align 4
2072 // CHECK3-NEXT:    [[AA:%.*]] = alloca i16, align 2
2073 // CHECK3-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
2074 // CHECK3-NEXT:    [[SAVED_STACK:%.*]] = alloca ptr, align 4
2075 // CHECK3-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
2076 // CHECK3-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
2077 // CHECK3-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
2078 // CHECK3-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
2079 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
2080 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
2081 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
2082 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
2083 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR__CASTED3:%.*]] = alloca i32, align 4
2084 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 4
2085 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 4
2086 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 4
2087 // CHECK3-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4
2088 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
2089 // CHECK3-NEXT:    [[AA_CASTED4:%.*]] = alloca i32, align 4
2090 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [1 x ptr], align 4
2091 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS6:%.*]] = alloca [1 x ptr], align 4
2092 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [1 x ptr], align 4
2093 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2094 // CHECK3-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
2095 // CHECK3-NEXT:    [[A_CASTED8:%.*]] = alloca i32, align 4
2096 // CHECK3-NEXT:    [[AA_CASTED9:%.*]] = alloca i32, align 4
2097 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [2 x ptr], align 4
2098 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS11:%.*]] = alloca [2 x ptr], align 4
2099 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [2 x ptr], align 4
2100 // CHECK3-NEXT:    [[_TMP13:%.*]] = alloca i32, align 4
2101 // CHECK3-NEXT:    [[KERNEL_ARGS14:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
2102 // CHECK3-NEXT:    [[A_CASTED17:%.*]] = alloca i32, align 4
2103 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [9 x ptr], align 4
2104 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS21:%.*]] = alloca [9 x ptr], align 4
2105 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [9 x ptr], align 4
2106 // CHECK3-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 4
2107 // CHECK3-NEXT:    [[_TMP23:%.*]] = alloca i32, align 4
2108 // CHECK3-NEXT:    [[KERNEL_ARGS24:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
2109 // CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])
2110 // CHECK3-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
2111 // CHECK3-NEXT:    store i32 0, ptr [[A]], align 4
2112 // CHECK3-NEXT:    store i16 0, ptr [[AA]], align 2
2113 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
2114 // CHECK3-NEXT:    [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
2115 // CHECK3-NEXT:    store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4
2116 // CHECK3-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4
2117 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4
2118 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4
2119 // CHECK3-NEXT:    [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]]
2120 // CHECK3-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8
2121 // CHECK3-NEXT:    store i32 [[TMP3]], ptr [[__VLA_EXPR1]], align 4
2122 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[A]], align 4
2123 // CHECK3-NEXT:    store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_]], align 4
2124 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[A]], align 4
2125 // CHECK3-NEXT:    store i32 [[TMP6]], ptr [[DOTCAPTURE_EXPR_2]], align 4
2126 // CHECK3-NEXT:    [[TMP7:%.*]] = load i16, ptr [[AA]], align 2
2127 // CHECK3-NEXT:    store i16 [[TMP7]], ptr [[AA_CASTED]], align 2
2128 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[AA_CASTED]], align 4
2129 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
2130 // CHECK3-NEXT:    store i32 [[TMP9]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
2131 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
2132 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
2133 // CHECK3-NEXT:    store i32 [[TMP11]], ptr [[DOTCAPTURE_EXPR__CASTED3]], align 4
2134 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED3]], align 4
2135 // CHECK3-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2136 // CHECK3-NEXT:    store i32 [[TMP8]], ptr [[TMP13]], align 4
2137 // CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2138 // CHECK3-NEXT:    store i32 [[TMP8]], ptr [[TMP14]], align 4
2139 // CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
2140 // CHECK3-NEXT:    store ptr null, ptr [[TMP15]], align 4
2141 // CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
2142 // CHECK3-NEXT:    store i32 [[TMP10]], ptr [[TMP16]], align 4
2143 // CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
2144 // CHECK3-NEXT:    store i32 [[TMP10]], ptr [[TMP17]], align 4
2145 // CHECK3-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
2146 // CHECK3-NEXT:    store ptr null, ptr [[TMP18]], align 4
2147 // CHECK3-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
2148 // CHECK3-NEXT:    store i32 [[TMP12]], ptr [[TMP19]], align 4
2149 // CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
2150 // CHECK3-NEXT:    store i32 [[TMP12]], ptr [[TMP20]], align 4
2151 // CHECK3-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
2152 // CHECK3-NEXT:    store ptr null, ptr [[TMP21]], align 4
2153 // CHECK3-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2154 // CHECK3-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2155 // CHECK3-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0
2156 // CHECK3-NEXT:    [[TMP25:%.*]] = load i16, ptr [[AA]], align 2
2157 // CHECK3-NEXT:    store i16 [[TMP25]], ptr [[TMP24]], align 4
2158 // CHECK3-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 1
2159 // CHECK3-NEXT:    [[TMP27:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
2160 // CHECK3-NEXT:    store i32 [[TMP27]], ptr [[TMP26]], align 4
2161 // CHECK3-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 2
2162 // CHECK3-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
2163 // CHECK3-NEXT:    store i32 [[TMP29]], ptr [[TMP28]], align 4
2164 // CHECK3-NEXT:    [[TMP30:%.*]] = call ptr @__kmpc_omp_target_task_alloc(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 72, i32 12, ptr @.omp_task_entry., i64 -1)
2165 // CHECK3-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP30]], i32 0, i32 0
2166 // CHECK3-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP31]], i32 0, i32 0
2167 // CHECK3-NEXT:    [[TMP33:%.*]] = load ptr, ptr [[TMP32]], align 4
2168 // CHECK3-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP33]], ptr align 4 [[AGG_CAPTURED]], i32 12, i1 false)
2169 // CHECK3-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP30]], i32 0, i32 1
2170 // CHECK3-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP34]], i32 0, i32 0
2171 // CHECK3-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP35]], ptr align 4 @.offload_sizes, i32 24, i1 false)
2172 // CHECK3-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP34]], i32 0, i32 1
2173 // CHECK3-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP36]], ptr align 4 [[TMP22]], i32 12, i1 false)
2174 // CHECK3-NEXT:    [[TMP37:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP34]], i32 0, i32 2
2175 // CHECK3-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP37]], ptr align 4 [[TMP23]], i32 12, i1 false)
2176 // CHECK3-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP34]], i32 0, i32 3
2177 // CHECK3-NEXT:    [[TMP39:%.*]] = load i16, ptr [[AA]], align 2
2178 // CHECK3-NEXT:    store i16 [[TMP39]], ptr [[TMP38]], align 4
2179 // CHECK3-NEXT:    [[TMP40:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB2]], i32 [[TMP0]], ptr [[TMP30]])
2180 // CHECK3-NEXT:    [[TMP41:%.*]] = load i32, ptr [[A]], align 4
2181 // CHECK3-NEXT:    store i32 [[TMP41]], ptr [[A_CASTED]], align 4
2182 // CHECK3-NEXT:    [[TMP42:%.*]] = load i32, ptr [[A_CASTED]], align 4
2183 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104(i32 [[TMP42]]) #[[ATTR3:[0-9]+]]
2184 // CHECK3-NEXT:    [[TMP43:%.*]] = load i16, ptr [[AA]], align 2
2185 // CHECK3-NEXT:    store i16 [[TMP43]], ptr [[AA_CASTED4]], align 2
2186 // CHECK3-NEXT:    [[TMP44:%.*]] = load i32, ptr [[AA_CASTED4]], align 4
2187 // CHECK3-NEXT:    [[TMP45:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0
2188 // CHECK3-NEXT:    store i32 [[TMP44]], ptr [[TMP45]], align 4
2189 // CHECK3-NEXT:    [[TMP46:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0
2190 // CHECK3-NEXT:    store i32 [[TMP44]], ptr [[TMP46]], align 4
2191 // CHECK3-NEXT:    [[TMP47:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 0
2192 // CHECK3-NEXT:    store ptr null, ptr [[TMP47]], align 4
2193 // CHECK3-NEXT:    [[TMP48:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0
2194 // CHECK3-NEXT:    [[TMP49:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0
2195 // CHECK3-NEXT:    [[TMP50:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
2196 // CHECK3-NEXT:    store i32 2, ptr [[TMP50]], align 4
2197 // CHECK3-NEXT:    [[TMP51:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
2198 // CHECK3-NEXT:    store i32 1, ptr [[TMP51]], align 4
2199 // CHECK3-NEXT:    [[TMP52:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
2200 // CHECK3-NEXT:    store ptr [[TMP48]], ptr [[TMP52]], align 4
2201 // CHECK3-NEXT:    [[TMP53:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
2202 // CHECK3-NEXT:    store ptr [[TMP49]], ptr [[TMP53]], align 4
2203 // CHECK3-NEXT:    [[TMP54:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
2204 // CHECK3-NEXT:    store ptr @.offload_sizes.1, ptr [[TMP54]], align 4
2205 // CHECK3-NEXT:    [[TMP55:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
2206 // CHECK3-NEXT:    store ptr @.offload_maptypes.2, ptr [[TMP55]], align 4
2207 // CHECK3-NEXT:    [[TMP56:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
2208 // CHECK3-NEXT:    store ptr null, ptr [[TMP56]], align 4
2209 // CHECK3-NEXT:    [[TMP57:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
2210 // CHECK3-NEXT:    store ptr null, ptr [[TMP57]], align 4
2211 // CHECK3-NEXT:    [[TMP58:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
2212 // CHECK3-NEXT:    store i64 10, ptr [[TMP58]], align 8
2213 // CHECK3-NEXT:    [[TMP59:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
2214 // CHECK3-NEXT:    store i64 0, ptr [[TMP59]], align 8
2215 // CHECK3-NEXT:    [[TMP60:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
2216 // CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP60]], align 4
2217 // CHECK3-NEXT:    [[TMP61:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
2218 // CHECK3-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP61]], align 4
2219 // CHECK3-NEXT:    [[TMP62:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
2220 // CHECK3-NEXT:    store i32 0, ptr [[TMP62]], align 4
2221 // CHECK3-NEXT:    [[TMP63:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.region_id, ptr [[KERNEL_ARGS]])
2222 // CHECK3-NEXT:    [[TMP64:%.*]] = icmp ne i32 [[TMP63]], 0
2223 // CHECK3-NEXT:    br i1 [[TMP64]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
2224 // CHECK3:       omp_offload.failed:
2225 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i32 [[TMP44]]) #[[ATTR3]]
2226 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]
2227 // CHECK3:       omp_offload.cont:
2228 // CHECK3-NEXT:    [[TMP65:%.*]] = load i32, ptr [[A]], align 4
2229 // CHECK3-NEXT:    store i32 [[TMP65]], ptr [[A_CASTED8]], align 4
2230 // CHECK3-NEXT:    [[TMP66:%.*]] = load i32, ptr [[A_CASTED8]], align 4
2231 // CHECK3-NEXT:    [[TMP67:%.*]] = load i16, ptr [[AA]], align 2
2232 // CHECK3-NEXT:    store i16 [[TMP67]], ptr [[AA_CASTED9]], align 2
2233 // CHECK3-NEXT:    [[TMP68:%.*]] = load i32, ptr [[AA_CASTED9]], align 4
2234 // CHECK3-NEXT:    [[TMP69:%.*]] = load i32, ptr [[N_ADDR]], align 4
2235 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP69]], 10
2236 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
2237 // CHECK3:       omp_if.then:
2238 // CHECK3-NEXT:    [[TMP70:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
2239 // CHECK3-NEXT:    store i32 [[TMP66]], ptr [[TMP70]], align 4
2240 // CHECK3-NEXT:    [[TMP71:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
2241 // CHECK3-NEXT:    store i32 [[TMP66]], ptr [[TMP71]], align 4
2242 // CHECK3-NEXT:    [[TMP72:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS12]], i32 0, i32 0
2243 // CHECK3-NEXT:    store ptr null, ptr [[TMP72]], align 4
2244 // CHECK3-NEXT:    [[TMP73:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 1
2245 // CHECK3-NEXT:    store i32 [[TMP68]], ptr [[TMP73]], align 4
2246 // CHECK3-NEXT:    [[TMP74:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 1
2247 // CHECK3-NEXT:    store i32 [[TMP68]], ptr [[TMP74]], align 4
2248 // CHECK3-NEXT:    [[TMP75:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS12]], i32 0, i32 1
2249 // CHECK3-NEXT:    store ptr null, ptr [[TMP75]], align 4
2250 // CHECK3-NEXT:    [[TMP76:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
2251 // CHECK3-NEXT:    [[TMP77:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
2252 // CHECK3-NEXT:    [[TMP78:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 0
2253 // CHECK3-NEXT:    store i32 2, ptr [[TMP78]], align 4
2254 // CHECK3-NEXT:    [[TMP79:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 1
2255 // CHECK3-NEXT:    store i32 2, ptr [[TMP79]], align 4
2256 // CHECK3-NEXT:    [[TMP80:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 2
2257 // CHECK3-NEXT:    store ptr [[TMP76]], ptr [[TMP80]], align 4
2258 // CHECK3-NEXT:    [[TMP81:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 3
2259 // CHECK3-NEXT:    store ptr [[TMP77]], ptr [[TMP81]], align 4
2260 // CHECK3-NEXT:    [[TMP82:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 4
2261 // CHECK3-NEXT:    store ptr @.offload_sizes.3, ptr [[TMP82]], align 4
2262 // CHECK3-NEXT:    [[TMP83:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 5
2263 // CHECK3-NEXT:    store ptr @.offload_maptypes.4, ptr [[TMP83]], align 4
2264 // CHECK3-NEXT:    [[TMP84:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 6
2265 // CHECK3-NEXT:    store ptr null, ptr [[TMP84]], align 4
2266 // CHECK3-NEXT:    [[TMP85:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 7
2267 // CHECK3-NEXT:    store ptr null, ptr [[TMP85]], align 4
2268 // CHECK3-NEXT:    [[TMP86:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 8
2269 // CHECK3-NEXT:    store i64 10, ptr [[TMP86]], align 8
2270 // CHECK3-NEXT:    [[TMP87:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 9
2271 // CHECK3-NEXT:    store i64 0, ptr [[TMP87]], align 8
2272 // CHECK3-NEXT:    [[TMP88:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 10
2273 // CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP88]], align 4
2274 // CHECK3-NEXT:    [[TMP89:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 11
2275 // CHECK3-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP89]], align 4
2276 // CHECK3-NEXT:    [[TMP90:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 12
2277 // CHECK3-NEXT:    store i32 0, ptr [[TMP90]], align 4
2278 // CHECK3-NEXT:    [[TMP91:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.region_id, ptr [[KERNEL_ARGS14]])
2279 // CHECK3-NEXT:    [[TMP92:%.*]] = icmp ne i32 [[TMP91]], 0
2280 // CHECK3-NEXT:    br i1 [[TMP92]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]]
2281 // CHECK3:       omp_offload.failed15:
2282 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP66]], i32 [[TMP68]]) #[[ATTR3]]
2283 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT16]]
2284 // CHECK3:       omp_offload.cont16:
2285 // CHECK3-NEXT:    br label [[OMP_IF_END:%.*]]
2286 // CHECK3:       omp_if.else:
2287 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP66]], i32 [[TMP68]]) #[[ATTR3]]
2288 // CHECK3-NEXT:    br label [[OMP_IF_END]]
2289 // CHECK3:       omp_if.end:
2290 // CHECK3-NEXT:    [[TMP93:%.*]] = load i32, ptr [[A]], align 4
2291 // CHECK3-NEXT:    store i32 [[TMP93]], ptr [[A_CASTED17]], align 4
2292 // CHECK3-NEXT:    [[TMP94:%.*]] = load i32, ptr [[A_CASTED17]], align 4
2293 // CHECK3-NEXT:    [[TMP95:%.*]] = load i32, ptr [[N_ADDR]], align 4
2294 // CHECK3-NEXT:    [[CMP18:%.*]] = icmp sgt i32 [[TMP95]], 20
2295 // CHECK3-NEXT:    br i1 [[CMP18]], label [[OMP_IF_THEN19:%.*]], label [[OMP_IF_ELSE27:%.*]]
2296 // CHECK3:       omp_if.then19:
2297 // CHECK3-NEXT:    [[TMP96:%.*]] = mul nuw i32 [[TMP1]], 4
2298 // CHECK3-NEXT:    [[TMP97:%.*]] = sext i32 [[TMP96]] to i64
2299 // CHECK3-NEXT:    [[TMP98:%.*]] = mul nuw i32 5, [[TMP3]]
2300 // CHECK3-NEXT:    [[TMP99:%.*]] = mul nuw i32 [[TMP98]], 8
2301 // CHECK3-NEXT:    [[TMP100:%.*]] = sext i32 [[TMP99]] to i64
2302 // CHECK3-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes.5, i32 72, i1 false)
2303 // CHECK3-NEXT:    [[TMP101:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0
2304 // CHECK3-NEXT:    store i32 [[TMP94]], ptr [[TMP101]], align 4
2305 // CHECK3-NEXT:    [[TMP102:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 0
2306 // CHECK3-NEXT:    store i32 [[TMP94]], ptr [[TMP102]], align 4
2307 // CHECK3-NEXT:    [[TMP103:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 0
2308 // CHECK3-NEXT:    store ptr null, ptr [[TMP103]], align 4
2309 // CHECK3-NEXT:    [[TMP104:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1
2310 // CHECK3-NEXT:    store ptr [[B]], ptr [[TMP104]], align 4
2311 // CHECK3-NEXT:    [[TMP105:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 1
2312 // CHECK3-NEXT:    store ptr [[B]], ptr [[TMP105]], align 4
2313 // CHECK3-NEXT:    [[TMP106:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 1
2314 // CHECK3-NEXT:    store ptr null, ptr [[TMP106]], align 4
2315 // CHECK3-NEXT:    [[TMP107:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 2
2316 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[TMP107]], align 4
2317 // CHECK3-NEXT:    [[TMP108:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 2
2318 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[TMP108]], align 4
2319 // CHECK3-NEXT:    [[TMP109:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 2
2320 // CHECK3-NEXT:    store ptr null, ptr [[TMP109]], align 4
2321 // CHECK3-NEXT:    [[TMP110:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 3
2322 // CHECK3-NEXT:    store ptr [[VLA]], ptr [[TMP110]], align 4
2323 // CHECK3-NEXT:    [[TMP111:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 3
2324 // CHECK3-NEXT:    store ptr [[VLA]], ptr [[TMP111]], align 4
2325 // CHECK3-NEXT:    [[TMP112:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 3
2326 // CHECK3-NEXT:    store i64 [[TMP97]], ptr [[TMP112]], align 4
2327 // CHECK3-NEXT:    [[TMP113:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 3
2328 // CHECK3-NEXT:    store ptr null, ptr [[TMP113]], align 4
2329 // CHECK3-NEXT:    [[TMP114:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 4
2330 // CHECK3-NEXT:    store ptr [[C]], ptr [[TMP114]], align 4
2331 // CHECK3-NEXT:    [[TMP115:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 4
2332 // CHECK3-NEXT:    store ptr [[C]], ptr [[TMP115]], align 4
2333 // CHECK3-NEXT:    [[TMP116:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 4
2334 // CHECK3-NEXT:    store ptr null, ptr [[TMP116]], align 4
2335 // CHECK3-NEXT:    [[TMP117:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 5
2336 // CHECK3-NEXT:    store i32 5, ptr [[TMP117]], align 4
2337 // CHECK3-NEXT:    [[TMP118:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 5
2338 // CHECK3-NEXT:    store i32 5, ptr [[TMP118]], align 4
2339 // CHECK3-NEXT:    [[TMP119:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 5
2340 // CHECK3-NEXT:    store ptr null, ptr [[TMP119]], align 4
2341 // CHECK3-NEXT:    [[TMP120:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 6
2342 // CHECK3-NEXT:    store i32 [[TMP3]], ptr [[TMP120]], align 4
2343 // CHECK3-NEXT:    [[TMP121:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 6
2344 // CHECK3-NEXT:    store i32 [[TMP3]], ptr [[TMP121]], align 4
2345 // CHECK3-NEXT:    [[TMP122:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 6
2346 // CHECK3-NEXT:    store ptr null, ptr [[TMP122]], align 4
2347 // CHECK3-NEXT:    [[TMP123:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 7
2348 // CHECK3-NEXT:    store ptr [[VLA1]], ptr [[TMP123]], align 4
2349 // CHECK3-NEXT:    [[TMP124:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 7
2350 // CHECK3-NEXT:    store ptr [[VLA1]], ptr [[TMP124]], align 4
2351 // CHECK3-NEXT:    [[TMP125:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 7
2352 // CHECK3-NEXT:    store i64 [[TMP100]], ptr [[TMP125]], align 4
2353 // CHECK3-NEXT:    [[TMP126:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 7
2354 // CHECK3-NEXT:    store ptr null, ptr [[TMP126]], align 4
2355 // CHECK3-NEXT:    [[TMP127:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 8
2356 // CHECK3-NEXT:    store ptr [[D]], ptr [[TMP127]], align 4
2357 // CHECK3-NEXT:    [[TMP128:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 8
2358 // CHECK3-NEXT:    store ptr [[D]], ptr [[TMP128]], align 4
2359 // CHECK3-NEXT:    [[TMP129:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 8
2360 // CHECK3-NEXT:    store ptr null, ptr [[TMP129]], align 4
2361 // CHECK3-NEXT:    [[TMP130:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0
2362 // CHECK3-NEXT:    [[TMP131:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 0
2363 // CHECK3-NEXT:    [[TMP132:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0
2364 // CHECK3-NEXT:    [[TMP133:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 0
2365 // CHECK3-NEXT:    store i32 2, ptr [[TMP133]], align 4
2366 // CHECK3-NEXT:    [[TMP134:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 1
2367 // CHECK3-NEXT:    store i32 9, ptr [[TMP134]], align 4
2368 // CHECK3-NEXT:    [[TMP135:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 2
2369 // CHECK3-NEXT:    store ptr [[TMP130]], ptr [[TMP135]], align 4
2370 // CHECK3-NEXT:    [[TMP136:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 3
2371 // CHECK3-NEXT:    store ptr [[TMP131]], ptr [[TMP136]], align 4
2372 // CHECK3-NEXT:    [[TMP137:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 4
2373 // CHECK3-NEXT:    store ptr [[TMP132]], ptr [[TMP137]], align 4
2374 // CHECK3-NEXT:    [[TMP138:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 5
2375 // CHECK3-NEXT:    store ptr @.offload_maptypes.6, ptr [[TMP138]], align 4
2376 // CHECK3-NEXT:    [[TMP139:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 6
2377 // CHECK3-NEXT:    store ptr null, ptr [[TMP139]], align 4
2378 // CHECK3-NEXT:    [[TMP140:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 7
2379 // CHECK3-NEXT:    store ptr null, ptr [[TMP140]], align 4
2380 // CHECK3-NEXT:    [[TMP141:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 8
2381 // CHECK3-NEXT:    store i64 10, ptr [[TMP141]], align 8
2382 // CHECK3-NEXT:    [[TMP142:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 9
2383 // CHECK3-NEXT:    store i64 0, ptr [[TMP142]], align 8
2384 // CHECK3-NEXT:    [[TMP143:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 10
2385 // CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP143]], align 4
2386 // CHECK3-NEXT:    [[TMP144:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 11
2387 // CHECK3-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP144]], align 4
2388 // CHECK3-NEXT:    [[TMP145:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 12
2389 // CHECK3-NEXT:    store i32 0, ptr [[TMP145]], align 4
2390 // CHECK3-NEXT:    [[TMP146:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.region_id, ptr [[KERNEL_ARGS24]])
2391 // CHECK3-NEXT:    [[TMP147:%.*]] = icmp ne i32 [[TMP146]], 0
2392 // CHECK3-NEXT:    br i1 [[TMP147]], label [[OMP_OFFLOAD_FAILED25:%.*]], label [[OMP_OFFLOAD_CONT26:%.*]]
2393 // CHECK3:       omp_offload.failed25:
2394 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP94]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]]) #[[ATTR3]]
2395 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT26]]
2396 // CHECK3:       omp_offload.cont26:
2397 // CHECK3-NEXT:    br label [[OMP_IF_END28:%.*]]
2398 // CHECK3:       omp_if.else27:
2399 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP94]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]]) #[[ATTR3]]
2400 // CHECK3-NEXT:    br label [[OMP_IF_END28]]
2401 // CHECK3:       omp_if.end28:
2402 // CHECK3-NEXT:    [[TMP148:%.*]] = load i32, ptr [[A]], align 4
2403 // CHECK3-NEXT:    [[TMP149:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
2404 // CHECK3-NEXT:    call void @llvm.stackrestore.p0(ptr [[TMP149]])
2405 // CHECK3-NEXT:    ret i32 [[TMP148]]
2406 //
2407 //
2408 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97
2409 // CHECK3-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] {
2410 // CHECK3-NEXT:  entry:
2411 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
2412 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
2413 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4
2414 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
2415 // CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
2416 // CHECK3-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
2417 // CHECK3-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
2418 // CHECK3-NEXT:    store i32 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4
2419 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
2420 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4
2421 // CHECK3-NEXT:    call void @__kmpc_push_num_teams(ptr @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
2422 // CHECK3-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
2423 // CHECK3-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
2424 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4
2425 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.omp_outlined, i32 [[TMP4]])
2426 // CHECK3-NEXT:    ret void
2427 //
2428 //
2429 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.omp_outlined
2430 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {
2431 // CHECK3-NEXT:  entry:
2432 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
2433 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
2434 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
2435 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2436 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2437 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2438 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2439 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2440 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2441 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
2442 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
2443 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
2444 // CHECK3-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
2445 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
2446 // CHECK3-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4
2447 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
2448 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2449 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
2450 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
2451 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
2452 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2453 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
2454 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2455 // CHECK3:       cond.true:
2456 // CHECK3-NEXT:    br label [[COND_END:%.*]]
2457 // CHECK3:       cond.false:
2458 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2459 // CHECK3-NEXT:    br label [[COND_END]]
2460 // CHECK3:       cond.end:
2461 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
2462 // CHECK3-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
2463 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
2464 // CHECK3-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
2465 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2466 // CHECK3:       omp.inner.for.cond:
2467 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11:![0-9]+]]
2468 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP11]]
2469 // CHECK3-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
2470 // CHECK3-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2471 // CHECK3:       omp.inner.for.body:
2472 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]
2473 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
2474 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2475 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]]
2476 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2477 // CHECK3:       omp.body.continue:
2478 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2479 // CHECK3:       omp.inner.for.inc:
2480 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]
2481 // CHECK3-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
2482 // CHECK3-NEXT:    store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]
2483 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
2484 // CHECK3:       omp.inner.for.end:
2485 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2486 // CHECK3:       omp.loop.exit:
2487 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
2488 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
2489 // CHECK3-NEXT:    [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
2490 // CHECK3-NEXT:    br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2491 // CHECK3:       .omp.final.then:
2492 // CHECK3-NEXT:    store i32 10, ptr [[I]], align 4
2493 // CHECK3-NEXT:    br label [[DOTOMP_FINAL_DONE]]
2494 // CHECK3:       .omp.final.done:
2495 // CHECK3-NEXT:    ret void
2496 //
2497 //
2498 // CHECK3-LABEL: define {{[^@]+}}@.omp_task_privates_map.
2499 // CHECK3-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]], ptr noalias noundef [[TMP3:%.*]], ptr noalias noundef [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] {
2500 // CHECK3-NEXT:  entry:
2501 // CHECK3-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 4
2502 // CHECK3-NEXT:    [[DOTADDR1:%.*]] = alloca ptr, align 4
2503 // CHECK3-NEXT:    [[DOTADDR2:%.*]] = alloca ptr, align 4
2504 // CHECK3-NEXT:    [[DOTADDR3:%.*]] = alloca ptr, align 4
2505 // CHECK3-NEXT:    [[DOTADDR4:%.*]] = alloca ptr, align 4
2506 // CHECK3-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 4
2507 // CHECK3-NEXT:    store ptr [[TMP1]], ptr [[DOTADDR1]], align 4
2508 // CHECK3-NEXT:    store ptr [[TMP2]], ptr [[DOTADDR2]], align 4
2509 // CHECK3-NEXT:    store ptr [[TMP3]], ptr [[DOTADDR3]], align 4
2510 // CHECK3-NEXT:    store ptr [[TMP4]], ptr [[DOTADDR4]], align 4
2511 // CHECK3-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[DOTADDR]], align 4
2512 // CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP5]], i32 0, i32 0
2513 // CHECK3-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[DOTADDR4]], align 4
2514 // CHECK3-NEXT:    store ptr [[TMP6]], ptr [[TMP7]], align 4
2515 // CHECK3-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 1
2516 // CHECK3-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[DOTADDR2]], align 4
2517 // CHECK3-NEXT:    store ptr [[TMP8]], ptr [[TMP9]], align 4
2518 // CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 2
2519 // CHECK3-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[DOTADDR3]], align 4
2520 // CHECK3-NEXT:    store ptr [[TMP10]], ptr [[TMP11]], align 4
2521 // CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 3
2522 // CHECK3-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[DOTADDR1]], align 4
2523 // CHECK3-NEXT:    store ptr [[TMP12]], ptr [[TMP13]], align 4
2524 // CHECK3-NEXT:    ret void
2525 //
2526 //
2527 // CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry.
2528 // CHECK3-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] {
2529 // CHECK3-NEXT:  entry:
2530 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
2531 // CHECK3-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 4
2532 // CHECK3-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 4
2533 // CHECK3-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 4
2534 // CHECK3-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 4
2535 // CHECK3-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 4
2536 // CHECK3-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca ptr, align 4
2537 // CHECK3-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca ptr, align 4
2538 // CHECK3-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca ptr, align 4
2539 // CHECK3-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca ptr, align 4
2540 // CHECK3-NEXT:    [[KERNEL_ARGS_I:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
2541 // CHECK3-NEXT:    [[AA_CASTED_I:%.*]] = alloca i32, align 4
2542 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i32, align 4
2543 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR__CASTED4_I:%.*]] = alloca i32, align 4
2544 // CHECK3-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 4
2545 // CHECK3-NEXT:    [[DOTADDR1:%.*]] = alloca ptr, align 4
2546 // CHECK3-NEXT:    store i32 [[TMP0]], ptr [[DOTADDR]], align 4
2547 // CHECK3-NEXT:    store ptr [[TMP1]], ptr [[DOTADDR1]], align 4
2548 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4
2549 // CHECK3-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 4
2550 // CHECK3-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0
2551 // CHECK3-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2
2552 // CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0
2553 // CHECK3-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 4
2554 // CHECK3-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 1
2555 // CHECK3-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])
2556 // CHECK3-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])
2557 // CHECK3-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]])
2558 // CHECK3-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META25:![0-9]+]])
2559 // CHECK3-NEXT:    store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !27
2560 // CHECK3-NEXT:    store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 4, !noalias !27
2561 // CHECK3-NEXT:    store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 4, !noalias !27
2562 // CHECK3-NEXT:    store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !27
2563 // CHECK3-NEXT:    store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 4, !noalias !27
2564 // CHECK3-NEXT:    store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 4, !noalias !27
2565 // CHECK3-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 4, !noalias !27
2566 // CHECK3-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !27
2567 // CHECK3-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 4, !noalias !27
2568 // CHECK3-NEXT:    call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]
2569 // CHECK3-NEXT:    [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !27
2570 // CHECK3-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !27
2571 // CHECK3-NEXT:    [[TMP14:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !27
2572 // CHECK3-NEXT:    [[TMP15:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !27
2573 // CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP9]], i32 0, i32 1
2574 // CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP9]], i32 0, i32 2
2575 // CHECK3-NEXT:    [[TMP18:%.*]] = load i32, ptr [[TMP16]], align 4
2576 // CHECK3-NEXT:    [[TMP19:%.*]] = insertvalue [3 x i32] zeroinitializer, i32 [[TMP18]], 0
2577 // CHECK3-NEXT:    store i32 2, ptr [[KERNEL_ARGS_I]], align 4, !noalias !27
2578 // CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 1
2579 // CHECK3-NEXT:    store i32 3, ptr [[TMP20]], align 4, !noalias !27
2580 // CHECK3-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 2
2581 // CHECK3-NEXT:    store ptr [[TMP13]], ptr [[TMP21]], align 4, !noalias !27
2582 // CHECK3-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 3
2583 // CHECK3-NEXT:    store ptr [[TMP14]], ptr [[TMP22]], align 4, !noalias !27
2584 // CHECK3-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 4
2585 // CHECK3-NEXT:    store ptr [[TMP15]], ptr [[TMP23]], align 4, !noalias !27
2586 // CHECK3-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 5
2587 // CHECK3-NEXT:    store ptr @.offload_maptypes, ptr [[TMP24]], align 4, !noalias !27
2588 // CHECK3-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 6
2589 // CHECK3-NEXT:    store ptr null, ptr [[TMP25]], align 4, !noalias !27
2590 // CHECK3-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 7
2591 // CHECK3-NEXT:    store ptr null, ptr [[TMP26]], align 4, !noalias !27
2592 // CHECK3-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 8
2593 // CHECK3-NEXT:    store i64 10, ptr [[TMP27]], align 8, !noalias !27
2594 // CHECK3-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 9
2595 // CHECK3-NEXT:    store i64 1, ptr [[TMP28]], align 8, !noalias !27
2596 // CHECK3-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 10
2597 // CHECK3-NEXT:    store [3 x i32] [[TMP19]], ptr [[TMP29]], align 4, !noalias !27
2598 // CHECK3-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 11
2599 // CHECK3-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP30]], align 4, !noalias !27
2600 // CHECK3-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 12
2601 // CHECK3-NEXT:    store i32 0, ptr [[TMP31]], align 4, !noalias !27
2602 // CHECK3-NEXT:    [[TMP32:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 [[TMP18]], i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.region_id, ptr [[KERNEL_ARGS_I]])
2603 // CHECK3-NEXT:    [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0
2604 // CHECK3-NEXT:    br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]]
2605 // CHECK3:       omp_offload.failed.i:
2606 // CHECK3-NEXT:    [[TMP34:%.*]] = load i16, ptr [[TMP12]], align 2
2607 // CHECK3-NEXT:    store i16 [[TMP34]], ptr [[AA_CASTED_I]], align 2, !noalias !27
2608 // CHECK3-NEXT:    [[TMP35:%.*]] = load i32, ptr [[AA_CASTED_I]], align 4, !noalias !27
2609 // CHECK3-NEXT:    [[TMP36:%.*]] = load i32, ptr [[TMP16]], align 4
2610 // CHECK3-NEXT:    store i32 [[TMP36]], ptr [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !27
2611 // CHECK3-NEXT:    [[TMP37:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !27
2612 // CHECK3-NEXT:    [[TMP38:%.*]] = load i32, ptr [[TMP17]], align 4
2613 // CHECK3-NEXT:    store i32 [[TMP38]], ptr [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !27
2614 // CHECK3-NEXT:    [[TMP39:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !27
2615 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97(i32 [[TMP35]], i32 [[TMP37]], i32 [[TMP39]]) #[[ATTR3]]
2616 // CHECK3-NEXT:    br label [[DOTOMP_OUTLINED__EXIT]]
2617 // CHECK3:       .omp_outlined..exit:
2618 // CHECK3-NEXT:    ret i32 0
2619 //
2620 //
2621 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104
2622 // CHECK3-SAME: (i32 noundef [[A:%.*]]) #[[ATTR2]] {
2623 // CHECK3-NEXT:  entry:
2624 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2625 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
2626 // CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
2627 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
2628 // CHECK3-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 4
2629 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4
2630 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104.omp_outlined, i32 [[TMP1]])
2631 // CHECK3-NEXT:    ret void
2632 //
2633 //
2634 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104.omp_outlined
2635 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] {
2636 // CHECK3-NEXT:  entry:
2637 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
2638 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
2639 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2640 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2641 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2642 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2643 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2644 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2645 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2646 // CHECK3-NEXT:    [[A1:%.*]] = alloca i32, align 4
2647 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
2648 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
2649 // CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
2650 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
2651 // CHECK3-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4
2652 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
2653 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2654 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
2655 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
2656 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
2657 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2658 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
2659 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2660 // CHECK3:       cond.true:
2661 // CHECK3-NEXT:    br label [[COND_END:%.*]]
2662 // CHECK3:       cond.false:
2663 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2664 // CHECK3-NEXT:    br label [[COND_END]]
2665 // CHECK3:       cond.end:
2666 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
2667 // CHECK3-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
2668 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
2669 // CHECK3-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
2670 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2671 // CHECK3:       omp.inner.for.cond:
2672 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2673 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2674 // CHECK3-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
2675 // CHECK3-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2676 // CHECK3:       omp.inner.for.body:
2677 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2678 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
2679 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2680 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[A1]], align 4
2681 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A1]], align 4
2682 // CHECK3-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
2683 // CHECK3-NEXT:    store i32 [[ADD3]], ptr [[A1]], align 4
2684 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2685 // CHECK3:       omp.body.continue:
2686 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2687 // CHECK3:       omp.inner.for.inc:
2688 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2689 // CHECK3-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP9]], 1
2690 // CHECK3-NEXT:    store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4
2691 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]
2692 // CHECK3:       omp.inner.for.end:
2693 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2694 // CHECK3:       omp.loop.exit:
2695 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
2696 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
2697 // CHECK3-NEXT:    [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
2698 // CHECK3-NEXT:    br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2699 // CHECK3:       .omp.final.then:
2700 // CHECK3-NEXT:    store i32 10, ptr [[A_ADDR]], align 4
2701 // CHECK3-NEXT:    br label [[DOTOMP_FINAL_DONE]]
2702 // CHECK3:       .omp.final.done:
2703 // CHECK3-NEXT:    ret void
2704 //
2705 //
2706 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
2707 // CHECK3-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR2]] {
2708 // CHECK3-NEXT:  entry:
2709 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
2710 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
2711 // CHECK3-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
2712 // CHECK3-NEXT:    [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2
2713 // CHECK3-NEXT:    store i16 [[TMP0]], ptr [[AA_CASTED]], align 2
2714 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[AA_CASTED]], align 4
2715 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined, i32 [[TMP1]])
2716 // CHECK3-NEXT:    ret void
2717 //
2718 //
2719 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined
2720 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {
2721 // CHECK3-NEXT:  entry:
2722 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
2723 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
2724 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
2725 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2726 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2727 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2728 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2729 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2730 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2731 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
2732 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
2733 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
2734 // CHECK3-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
2735 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
2736 // CHECK3-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4
2737 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
2738 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2739 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
2740 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
2741 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
2742 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2743 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
2744 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2745 // CHECK3:       cond.true:
2746 // CHECK3-NEXT:    br label [[COND_END:%.*]]
2747 // CHECK3:       cond.false:
2748 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2749 // CHECK3-NEXT:    br label [[COND_END]]
2750 // CHECK3:       cond.end:
2751 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
2752 // CHECK3-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
2753 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
2754 // CHECK3-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
2755 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2756 // CHECK3:       omp.inner.for.cond:
2757 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30:![0-9]+]]
2758 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP30]]
2759 // CHECK3-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
2760 // CHECK3-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2761 // CHECK3:       omp.inner.for.body:
2762 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30]]
2763 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
2764 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2765 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP30]]
2766 // CHECK3-NEXT:    [[TMP8:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP30]]
2767 // CHECK3-NEXT:    [[CONV:%.*]] = sext i16 [[TMP8]] to i32
2768 // CHECK3-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
2769 // CHECK3-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
2770 // CHECK3-NEXT:    store i16 [[CONV3]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP30]]
2771 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2772 // CHECK3:       omp.body.continue:
2773 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2774 // CHECK3:       omp.inner.for.inc:
2775 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30]]
2776 // CHECK3-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP9]], 1
2777 // CHECK3-NEXT:    store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30]]
2778 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]]
2779 // CHECK3:       omp.inner.for.end:
2780 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2781 // CHECK3:       omp.loop.exit:
2782 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
2783 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
2784 // CHECK3-NEXT:    [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
2785 // CHECK3-NEXT:    br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2786 // CHECK3:       .omp.final.then:
2787 // CHECK3-NEXT:    store i32 10, ptr [[I]], align 4
2788 // CHECK3-NEXT:    br label [[DOTOMP_FINAL_DONE]]
2789 // CHECK3:       .omp.final.done:
2790 // CHECK3-NEXT:    ret void
2791 //
2792 //
2793 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118
2794 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {
2795 // CHECK3-NEXT:  entry:
2796 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2797 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
2798 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
2799 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
2800 // CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
2801 // CHECK3-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
2802 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
2803 // CHECK3-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 4
2804 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4
2805 // CHECK3-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2
2806 // CHECK3-NEXT:    store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
2807 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4
2808 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined, i32 [[TMP1]], i32 [[TMP3]])
2809 // CHECK3-NEXT:    ret void
2810 //
2811 //
2812 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined
2813 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {
2814 // CHECK3-NEXT:  entry:
2815 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
2816 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
2817 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2818 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
2819 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2820 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2821 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2822 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2823 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2824 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2825 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
2826 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
2827 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
2828 // CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
2829 // CHECK3-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
2830 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
2831 // CHECK3-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4
2832 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
2833 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2834 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
2835 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
2836 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
2837 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2838 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
2839 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2840 // CHECK3:       cond.true:
2841 // CHECK3-NEXT:    br label [[COND_END:%.*]]
2842 // CHECK3:       cond.false:
2843 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2844 // CHECK3-NEXT:    br label [[COND_END]]
2845 // CHECK3:       cond.end:
2846 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
2847 // CHECK3-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
2848 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
2849 // CHECK3-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
2850 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2851 // CHECK3:       omp.inner.for.cond:
2852 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33:![0-9]+]]
2853 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP33]]
2854 // CHECK3-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
2855 // CHECK3-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2856 // CHECK3:       omp.inner.for.body:
2857 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]]
2858 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
2859 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2860 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP33]]
2861 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP33]]
2862 // CHECK3-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
2863 // CHECK3-NEXT:    store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP33]]
2864 // CHECK3-NEXT:    [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP33]]
2865 // CHECK3-NEXT:    [[CONV:%.*]] = sext i16 [[TMP9]] to i32
2866 // CHECK3-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV]], 1
2867 // CHECK3-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
2868 // CHECK3-NEXT:    store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP33]]
2869 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2870 // CHECK3:       omp.body.continue:
2871 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2872 // CHECK3:       omp.inner.for.inc:
2873 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]]
2874 // CHECK3-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP10]], 1
2875 // CHECK3-NEXT:    store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]]
2876 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]]
2877 // CHECK3:       omp.inner.for.end:
2878 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2879 // CHECK3:       omp.loop.exit:
2880 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
2881 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
2882 // CHECK3-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
2883 // CHECK3-NEXT:    br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2884 // CHECK3:       .omp.final.then:
2885 // CHECK3-NEXT:    store i32 10, ptr [[I]], align 4
2886 // CHECK3-NEXT:    br label [[DOTOMP_FINAL_DONE]]
2887 // CHECK3:       .omp.final.done:
2888 // CHECK3-NEXT:    ret void
2889 //
2890 //
2891 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142
2892 // CHECK3-SAME: (i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] {
2893 // CHECK3-NEXT:  entry:
2894 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2895 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
2896 // CHECK3-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
2897 // CHECK3-NEXT:    [[BN_ADDR:%.*]] = alloca ptr, align 4
2898 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
2899 // CHECK3-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
2900 // CHECK3-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
2901 // CHECK3-NEXT:    [[CN_ADDR:%.*]] = alloca ptr, align 4
2902 // CHECK3-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4
2903 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
2904 // CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
2905 // CHECK3-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
2906 // CHECK3-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
2907 // CHECK3-NEXT:    store ptr [[BN]], ptr [[BN_ADDR]], align 4
2908 // CHECK3-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
2909 // CHECK3-NEXT:    store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
2910 // CHECK3-NEXT:    store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4
2911 // CHECK3-NEXT:    store ptr [[CN]], ptr [[CN_ADDR]], align 4
2912 // CHECK3-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4
2913 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
2914 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
2915 // CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4
2916 // CHECK3-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
2917 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
2918 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4
2919 // CHECK3-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4
2920 // CHECK3-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4
2921 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
2922 // CHECK3-NEXT:    store i32 [[TMP8]], ptr [[A_CASTED]], align 4
2923 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4
2924 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.omp_outlined, i32 [[TMP9]], ptr [[TMP0]], i32 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]])
2925 // CHECK3-NEXT:    ret void
2926 //
2927 //
2928 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.omp_outlined
2929 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] {
2930 // CHECK3-NEXT:  entry:
2931 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
2932 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
2933 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2934 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
2935 // CHECK3-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
2936 // CHECK3-NEXT:    [[BN_ADDR:%.*]] = alloca ptr, align 4
2937 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
2938 // CHECK3-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
2939 // CHECK3-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
2940 // CHECK3-NEXT:    [[CN_ADDR:%.*]] = alloca ptr, align 4
2941 // CHECK3-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4
2942 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2943 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2944 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2945 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2946 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2947 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2948 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
2949 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
2950 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
2951 // CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
2952 // CHECK3-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
2953 // CHECK3-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
2954 // CHECK3-NEXT:    store ptr [[BN]], ptr [[BN_ADDR]], align 4
2955 // CHECK3-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
2956 // CHECK3-NEXT:    store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
2957 // CHECK3-NEXT:    store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4
2958 // CHECK3-NEXT:    store ptr [[CN]], ptr [[CN_ADDR]], align 4
2959 // CHECK3-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4
2960 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
2961 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
2962 // CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4
2963 // CHECK3-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
2964 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
2965 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4
2966 // CHECK3-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4
2967 // CHECK3-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4
2968 // CHECK3-NEXT:    [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 0
2969 // CHECK3-NEXT:    call void @llvm.assume(i1 true) [ "align"(ptr [[ARRAYDECAY]], i32 16) ]
2970 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
2971 // CHECK3-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4
2972 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
2973 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2974 // CHECK3-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
2975 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
2976 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP9]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
2977 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2978 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 9
2979 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2980 // CHECK3:       cond.true:
2981 // CHECK3-NEXT:    br label [[COND_END:%.*]]
2982 // CHECK3:       cond.false:
2983 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2984 // CHECK3-NEXT:    br label [[COND_END]]
2985 // CHECK3:       cond.end:
2986 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
2987 // CHECK3-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
2988 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
2989 // CHECK3-NEXT:    store i32 [[TMP12]], ptr [[DOTOMP_IV]], align 4
2990 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2991 // CHECK3:       omp.inner.for.cond:
2992 // CHECK3-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36:![0-9]+]]
2993 // CHECK3-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP36]]
2994 // CHECK3-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
2995 // CHECK3-NEXT:    br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2996 // CHECK3:       omp.inner.for.body:
2997 // CHECK3-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]]
2998 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
2999 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
3000 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP36]]
3001 // CHECK3-NEXT:    [[TMP16:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP36]]
3002 // CHECK3-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1
3003 // CHECK3-NEXT:    store i32 [[ADD6]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP36]]
3004 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 2
3005 // CHECK3-NEXT:    [[TMP17:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP36]]
3006 // CHECK3-NEXT:    [[CONV:%.*]] = fpext float [[TMP17]] to double
3007 // CHECK3-NEXT:    [[ADD7:%.*]] = fadd double [[CONV]], 1.000000e+00
3008 // CHECK3-NEXT:    [[CONV8:%.*]] = fptrunc double [[ADD7]] to float
3009 // CHECK3-NEXT:    store float [[CONV8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP36]]
3010 // CHECK3-NEXT:    [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i32 3
3011 // CHECK3-NEXT:    [[TMP18:%.*]] = load float, ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP36]]
3012 // CHECK3-NEXT:    [[CONV10:%.*]] = fpext float [[TMP18]] to double
3013 // CHECK3-NEXT:    [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00
3014 // CHECK3-NEXT:    [[CONV12:%.*]] = fptrunc double [[ADD11]] to float
3015 // CHECK3-NEXT:    store float [[CONV12]], ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP36]]
3016 // CHECK3-NEXT:    [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 1
3017 // CHECK3-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX13]], i32 0, i32 2
3018 // CHECK3-NEXT:    [[TMP19:%.*]] = load double, ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP36]]
3019 // CHECK3-NEXT:    [[ADD15:%.*]] = fadd double [[TMP19]], 1.000000e+00
3020 // CHECK3-NEXT:    store double [[ADD15]], ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP36]]
3021 // CHECK3-NEXT:    [[TMP20:%.*]] = mul nsw i32 1, [[TMP5]]
3022 // CHECK3-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i32 [[TMP20]]
3023 // CHECK3-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX16]], i32 3
3024 // CHECK3-NEXT:    [[TMP21:%.*]] = load double, ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP36]]
3025 // CHECK3-NEXT:    [[ADD18:%.*]] = fadd double [[TMP21]], 1.000000e+00
3026 // CHECK3-NEXT:    store double [[ADD18]], ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP36]]
3027 // CHECK3-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0
3028 // CHECK3-NEXT:    [[TMP22:%.*]] = load i64, ptr [[X]], align 4, !llvm.access.group [[ACC_GRP36]]
3029 // CHECK3-NEXT:    [[ADD19:%.*]] = add nsw i64 [[TMP22]], 1
3030 // CHECK3-NEXT:    store i64 [[ADD19]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP36]]
3031 // CHECK3-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1
3032 // CHECK3-NEXT:    [[TMP23:%.*]] = load i8, ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP36]]
3033 // CHECK3-NEXT:    [[CONV20:%.*]] = sext i8 [[TMP23]] to i32
3034 // CHECK3-NEXT:    [[ADD21:%.*]] = add nsw i32 [[CONV20]], 1
3035 // CHECK3-NEXT:    [[CONV22:%.*]] = trunc i32 [[ADD21]] to i8
3036 // CHECK3-NEXT:    store i8 [[CONV22]], ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP36]]
3037 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
3038 // CHECK3:       omp.body.continue:
3039 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
3040 // CHECK3:       omp.inner.for.inc:
3041 // CHECK3-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]]
3042 // CHECK3-NEXT:    [[ADD23:%.*]] = add nsw i32 [[TMP24]], 1
3043 // CHECK3-NEXT:    store i32 [[ADD23]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]]
3044 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]]
3045 // CHECK3:       omp.inner.for.end:
3046 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
3047 // CHECK3:       omp.loop.exit:
3048 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP9]])
3049 // CHECK3-NEXT:    [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
3050 // CHECK3-NEXT:    [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
3051 // CHECK3-NEXT:    br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
3052 // CHECK3:       .omp.final.then:
3053 // CHECK3-NEXT:    store i32 10, ptr [[I]], align 4
3054 // CHECK3-NEXT:    br label [[DOTOMP_FINAL_DONE]]
3055 // CHECK3:       .omp.final.done:
3056 // CHECK3-NEXT:    ret void
3057 //
3058 //
3059 // CHECK3-LABEL: define {{[^@]+}}@_Z3bari
3060 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
3061 // CHECK3-NEXT:  entry:
3062 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
3063 // CHECK3-NEXT:    [[A:%.*]] = alloca i32, align 4
3064 // CHECK3-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
3065 // CHECK3-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
3066 // CHECK3-NEXT:    store i32 0, ptr [[A]], align 4
3067 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
3068 // CHECK3-NEXT:    [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]])
3069 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A]], align 4
3070 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
3071 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[A]], align 4
3072 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
3073 // CHECK3-NEXT:    [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]])
3074 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A]], align 4
3075 // CHECK3-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
3076 // CHECK3-NEXT:    store i32 [[ADD2]], ptr [[A]], align 4
3077 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
3078 // CHECK3-NEXT:    [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]])
3079 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[A]], align 4
3080 // CHECK3-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
3081 // CHECK3-NEXT:    store i32 [[ADD4]], ptr [[A]], align 4
3082 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4
3083 // CHECK3-NEXT:    [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]])
3084 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[A]], align 4
3085 // CHECK3-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
3086 // CHECK3-NEXT:    store i32 [[ADD6]], ptr [[A]], align 4
3087 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A]], align 4
3088 // CHECK3-NEXT:    ret i32 [[TMP8]]
3089 //
3090 //
3091 // CHECK3-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
3092 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 {
3093 // CHECK3-NEXT:  entry:
3094 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
3095 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
3096 // CHECK3-NEXT:    [[B:%.*]] = alloca i32, align 4
3097 // CHECK3-NEXT:    [[SAVED_STACK:%.*]] = alloca ptr, align 4
3098 // CHECK3-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
3099 // CHECK3-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
3100 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 4
3101 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 4
3102 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 4
3103 // CHECK3-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4
3104 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
3105 // CHECK3-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
3106 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
3107 // CHECK3-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
3108 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
3109 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
3110 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
3111 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[B]], align 4
3112 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
3113 // CHECK3-NEXT:    [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
3114 // CHECK3-NEXT:    store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4
3115 // CHECK3-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
3116 // CHECK3-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
3117 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4
3118 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[B]], align 4
3119 // CHECK3-NEXT:    store i32 [[TMP4]], ptr [[B_CASTED]], align 4
3120 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4
3121 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4
3122 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60
3123 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
3124 // CHECK3:       omp_if.then:
3125 // CHECK3-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0
3126 // CHECK3-NEXT:    [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]]
3127 // CHECK3-NEXT:    [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2
3128 // CHECK3-NEXT:    [[TMP9:%.*]] = sext i32 [[TMP8]] to i64
3129 // CHECK3-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes.7, i32 40, i1 false)
3130 // CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3131 // CHECK3-NEXT:    store ptr [[THIS1]], ptr [[TMP10]], align 4
3132 // CHECK3-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3133 // CHECK3-NEXT:    store ptr [[A]], ptr [[TMP11]], align 4
3134 // CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
3135 // CHECK3-NEXT:    store ptr null, ptr [[TMP12]], align 4
3136 // CHECK3-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
3137 // CHECK3-NEXT:    store i32 [[TMP5]], ptr [[TMP13]], align 4
3138 // CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
3139 // CHECK3-NEXT:    store i32 [[TMP5]], ptr [[TMP14]], align 4
3140 // CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
3141 // CHECK3-NEXT:    store ptr null, ptr [[TMP15]], align 4
3142 // CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
3143 // CHECK3-NEXT:    store i32 2, ptr [[TMP16]], align 4
3144 // CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
3145 // CHECK3-NEXT:    store i32 2, ptr [[TMP17]], align 4
3146 // CHECK3-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
3147 // CHECK3-NEXT:    store ptr null, ptr [[TMP18]], align 4
3148 // CHECK3-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
3149 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[TMP19]], align 4
3150 // CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
3151 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[TMP20]], align 4
3152 // CHECK3-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
3153 // CHECK3-NEXT:    store ptr null, ptr [[TMP21]], align 4
3154 // CHECK3-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
3155 // CHECK3-NEXT:    store ptr [[VLA]], ptr [[TMP22]], align 4
3156 // CHECK3-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4
3157 // CHECK3-NEXT:    store ptr [[VLA]], ptr [[TMP23]], align 4
3158 // CHECK3-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 4
3159 // CHECK3-NEXT:    store i64 [[TMP9]], ptr [[TMP24]], align 4
3160 // CHECK3-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
3161 // CHECK3-NEXT:    store ptr null, ptr [[TMP25]], align 4
3162 // CHECK3-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3163 // CHECK3-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3164 // CHECK3-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0
3165 // CHECK3-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
3166 // CHECK3-NEXT:    store i32 2, ptr [[TMP29]], align 4
3167 // CHECK3-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
3168 // CHECK3-NEXT:    store i32 5, ptr [[TMP30]], align 4
3169 // CHECK3-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
3170 // CHECK3-NEXT:    store ptr [[TMP26]], ptr [[TMP31]], align 4
3171 // CHECK3-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
3172 // CHECK3-NEXT:    store ptr [[TMP27]], ptr [[TMP32]], align 4
3173 // CHECK3-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
3174 // CHECK3-NEXT:    store ptr [[TMP28]], ptr [[TMP33]], align 4
3175 // CHECK3-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
3176 // CHECK3-NEXT:    store ptr @.offload_maptypes.8, ptr [[TMP34]], align 4
3177 // CHECK3-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
3178 // CHECK3-NEXT:    store ptr null, ptr [[TMP35]], align 4
3179 // CHECK3-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
3180 // CHECK3-NEXT:    store ptr null, ptr [[TMP36]], align 4
3181 // CHECK3-NEXT:    [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
3182 // CHECK3-NEXT:    store i64 10, ptr [[TMP37]], align 8
3183 // CHECK3-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
3184 // CHECK3-NEXT:    store i64 0, ptr [[TMP38]], align 8
3185 // CHECK3-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
3186 // CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP39]], align 4
3187 // CHECK3-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
3188 // CHECK3-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP40]], align 4
3189 // CHECK3-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
3190 // CHECK3-NEXT:    store i32 0, ptr [[TMP41]], align 4
3191 // CHECK3-NEXT:    [[TMP42:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.region_id, ptr [[KERNEL_ARGS]])
3192 // CHECK3-NEXT:    [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0
3193 // CHECK3-NEXT:    br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
3194 // CHECK3:       omp_offload.failed:
3195 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215(ptr [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], ptr [[VLA]]) #[[ATTR3]]
3196 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]
3197 // CHECK3:       omp_offload.cont:
3198 // CHECK3-NEXT:    br label [[OMP_IF_END:%.*]]
3199 // CHECK3:       omp_if.else:
3200 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215(ptr [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], ptr [[VLA]]) #[[ATTR3]]
3201 // CHECK3-NEXT:    br label [[OMP_IF_END]]
3202 // CHECK3:       omp_if.end:
3203 // CHECK3-NEXT:    [[TMP44:%.*]] = mul nsw i32 1, [[TMP1]]
3204 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP44]]
3205 // CHECK3-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1
3206 // CHECK3-NEXT:    [[TMP45:%.*]] = load i16, ptr [[ARRAYIDX2]], align 2
3207 // CHECK3-NEXT:    [[CONV:%.*]] = sext i16 [[TMP45]] to i32
3208 // CHECK3-NEXT:    [[TMP46:%.*]] = load i32, ptr [[B]], align 4
3209 // CHECK3-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP46]]
3210 // CHECK3-NEXT:    [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
3211 // CHECK3-NEXT:    call void @llvm.stackrestore.p0(ptr [[TMP47]])
3212 // CHECK3-NEXT:    ret i32 [[ADD3]]
3213 //
3214 //
3215 // CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici
3216 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
3217 // CHECK3-NEXT:  entry:
3218 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
3219 // CHECK3-NEXT:    [[A:%.*]] = alloca i32, align 4
3220 // CHECK3-NEXT:    [[AA:%.*]] = alloca i16, align 2
3221 // CHECK3-NEXT:    [[AAA:%.*]] = alloca i8, align 1
3222 // CHECK3-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
3223 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
3224 // CHECK3-NEXT:    [[N_CASTED:%.*]] = alloca i32, align 4
3225 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
3226 // CHECK3-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
3227 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 4
3228 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 4
3229 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 4
3230 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
3231 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
3232 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
3233 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
3234 // CHECK3-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
3235 // CHECK3-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
3236 // CHECK3-NEXT:    store i32 0, ptr [[A]], align 4
3237 // CHECK3-NEXT:    store i16 0, ptr [[AA]], align 2
3238 // CHECK3-NEXT:    store i8 0, ptr [[AAA]], align 1
3239 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A]], align 4
3240 // CHECK3-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 4
3241 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4
3242 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
3243 // CHECK3-NEXT:    store i32 [[TMP2]], ptr [[N_CASTED]], align 4
3244 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[N_CASTED]], align 4
3245 // CHECK3-NEXT:    [[TMP4:%.*]] = load i16, ptr [[AA]], align 2
3246 // CHECK3-NEXT:    store i16 [[TMP4]], ptr [[AA_CASTED]], align 2
3247 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[AA_CASTED]], align 4
3248 // CHECK3-NEXT:    [[TMP6:%.*]] = load i8, ptr [[AAA]], align 1
3249 // CHECK3-NEXT:    store i8 [[TMP6]], ptr [[AAA_CASTED]], align 1
3250 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[AAA_CASTED]], align 4
3251 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[N_ADDR]], align 4
3252 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 50
3253 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
3254 // CHECK3:       omp_if.then:
3255 // CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3256 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[TMP9]], align 4
3257 // CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3258 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[TMP10]], align 4
3259 // CHECK3-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
3260 // CHECK3-NEXT:    store ptr null, ptr [[TMP11]], align 4
3261 // CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
3262 // CHECK3-NEXT:    store i32 [[TMP3]], ptr [[TMP12]], align 4
3263 // CHECK3-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
3264 // CHECK3-NEXT:    store i32 [[TMP3]], ptr [[TMP13]], align 4
3265 // CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
3266 // CHECK3-NEXT:    store ptr null, ptr [[TMP14]], align 4
3267 // CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
3268 // CHECK3-NEXT:    store i32 [[TMP5]], ptr [[TMP15]], align 4
3269 // CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
3270 // CHECK3-NEXT:    store i32 [[TMP5]], ptr [[TMP16]], align 4
3271 // CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
3272 // CHECK3-NEXT:    store ptr null, ptr [[TMP17]], align 4
3273 // CHECK3-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
3274 // CHECK3-NEXT:    store i32 [[TMP7]], ptr [[TMP18]], align 4
3275 // CHECK3-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
3276 // CHECK3-NEXT:    store i32 [[TMP7]], ptr [[TMP19]], align 4
3277 // CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
3278 // CHECK3-NEXT:    store ptr null, ptr [[TMP20]], align 4
3279 // CHECK3-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
3280 // CHECK3-NEXT:    store ptr [[B]], ptr [[TMP21]], align 4
3281 // CHECK3-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4
3282 // CHECK3-NEXT:    store ptr [[B]], ptr [[TMP22]], align 4
3283 // CHECK3-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
3284 // CHECK3-NEXT:    store ptr null, ptr [[TMP23]], align 4
3285 // CHECK3-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3286 // CHECK3-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3287 // CHECK3-NEXT:    [[TMP26:%.*]] = load i32, ptr [[A]], align 4
3288 // CHECK3-NEXT:    store i32 [[TMP26]], ptr [[DOTCAPTURE_EXPR_]], align 4
3289 // CHECK3-NEXT:    [[TMP27:%.*]] = load i32, ptr [[N_ADDR]], align 4
3290 // CHECK3-NEXT:    store i32 [[TMP27]], ptr [[DOTCAPTURE_EXPR_1]], align 4
3291 // CHECK3-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
3292 // CHECK3-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
3293 // CHECK3-NEXT:    [[SUB:%.*]] = sub i32 [[TMP28]], [[TMP29]]
3294 // CHECK3-NEXT:    [[SUB3:%.*]] = sub i32 [[SUB]], 1
3295 // CHECK3-NEXT:    [[ADD:%.*]] = add i32 [[SUB3]], 1
3296 // CHECK3-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
3297 // CHECK3-NEXT:    [[SUB4:%.*]] = sub i32 [[DIV]], 1
3298 // CHECK3-NEXT:    store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 4
3299 // CHECK3-NEXT:    [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
3300 // CHECK3-NEXT:    [[ADD5:%.*]] = add i32 [[TMP30]], 1
3301 // CHECK3-NEXT:    [[TMP31:%.*]] = zext i32 [[ADD5]] to i64
3302 // CHECK3-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
3303 // CHECK3-NEXT:    store i32 2, ptr [[TMP32]], align 4
3304 // CHECK3-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
3305 // CHECK3-NEXT:    store i32 5, ptr [[TMP33]], align 4
3306 // CHECK3-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
3307 // CHECK3-NEXT:    store ptr [[TMP24]], ptr [[TMP34]], align 4
3308 // CHECK3-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
3309 // CHECK3-NEXT:    store ptr [[TMP25]], ptr [[TMP35]], align 4
3310 // CHECK3-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
3311 // CHECK3-NEXT:    store ptr @.offload_sizes.9, ptr [[TMP36]], align 4
3312 // CHECK3-NEXT:    [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
3313 // CHECK3-NEXT:    store ptr @.offload_maptypes.10, ptr [[TMP37]], align 4
3314 // CHECK3-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
3315 // CHECK3-NEXT:    store ptr null, ptr [[TMP38]], align 4
3316 // CHECK3-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
3317 // CHECK3-NEXT:    store ptr null, ptr [[TMP39]], align 4
3318 // CHECK3-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
3319 // CHECK3-NEXT:    store i64 [[TMP31]], ptr [[TMP40]], align 8
3320 // CHECK3-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
3321 // CHECK3-NEXT:    store i64 0, ptr [[TMP41]], align 8
3322 // CHECK3-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
3323 // CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP42]], align 4
3324 // CHECK3-NEXT:    [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
3325 // CHECK3-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP43]], align 4
3326 // CHECK3-NEXT:    [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
3327 // CHECK3-NEXT:    store i32 0, ptr [[TMP44]], align 4
3328 // CHECK3-NEXT:    [[TMP45:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.region_id, ptr [[KERNEL_ARGS]])
3329 // CHECK3-NEXT:    [[TMP46:%.*]] = icmp ne i32 [[TMP45]], 0
3330 // CHECK3-NEXT:    br i1 [[TMP46]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
3331 // CHECK3:       omp_offload.failed:
3332 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], i32 [[TMP7]], ptr [[B]]) #[[ATTR3]]
3333 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]
3334 // CHECK3:       omp_offload.cont:
3335 // CHECK3-NEXT:    br label [[OMP_IF_END:%.*]]
3336 // CHECK3:       omp_if.else:
3337 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], i32 [[TMP7]], ptr [[B]]) #[[ATTR3]]
3338 // CHECK3-NEXT:    br label [[OMP_IF_END]]
3339 // CHECK3:       omp_if.end:
3340 // CHECK3-NEXT:    [[TMP47:%.*]] = load i32, ptr [[A]], align 4
3341 // CHECK3-NEXT:    ret i32 [[TMP47]]
3342 //
3343 //
3344 // CHECK3-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
3345 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat {
3346 // CHECK3-NEXT:  entry:
3347 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
3348 // CHECK3-NEXT:    [[A:%.*]] = alloca i32, align 4
3349 // CHECK3-NEXT:    [[AA:%.*]] = alloca i16, align 2
3350 // CHECK3-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
3351 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
3352 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
3353 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 4
3354 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 4
3355 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 4
3356 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
3357 // CHECK3-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
3358 // CHECK3-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
3359 // CHECK3-NEXT:    store i32 0, ptr [[A]], align 4
3360 // CHECK3-NEXT:    store i16 0, ptr [[AA]], align 2
3361 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A]], align 4
3362 // CHECK3-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 4
3363 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4
3364 // CHECK3-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA]], align 2
3365 // CHECK3-NEXT:    store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
3366 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4
3367 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
3368 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
3369 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
3370 // CHECK3:       omp_if.then:
3371 // CHECK3-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3372 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[TMP5]], align 4
3373 // CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3374 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[TMP6]], align 4
3375 // CHECK3-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
3376 // CHECK3-NEXT:    store ptr null, ptr [[TMP7]], align 4
3377 // CHECK3-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
3378 // CHECK3-NEXT:    store i32 [[TMP3]], ptr [[TMP8]], align 4
3379 // CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
3380 // CHECK3-NEXT:    store i32 [[TMP3]], ptr [[TMP9]], align 4
3381 // CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
3382 // CHECK3-NEXT:    store ptr null, ptr [[TMP10]], align 4
3383 // CHECK3-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
3384 // CHECK3-NEXT:    store ptr [[B]], ptr [[TMP11]], align 4
3385 // CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
3386 // CHECK3-NEXT:    store ptr [[B]], ptr [[TMP12]], align 4
3387 // CHECK3-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
3388 // CHECK3-NEXT:    store ptr null, ptr [[TMP13]], align 4
3389 // CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3390 // CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3391 // CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
3392 // CHECK3-NEXT:    store i32 2, ptr [[TMP16]], align 4
3393 // CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
3394 // CHECK3-NEXT:    store i32 3, ptr [[TMP17]], align 4
3395 // CHECK3-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
3396 // CHECK3-NEXT:    store ptr [[TMP14]], ptr [[TMP18]], align 4
3397 // CHECK3-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
3398 // CHECK3-NEXT:    store ptr [[TMP15]], ptr [[TMP19]], align 4
3399 // CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
3400 // CHECK3-NEXT:    store ptr @.offload_sizes.11, ptr [[TMP20]], align 4
3401 // CHECK3-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
3402 // CHECK3-NEXT:    store ptr @.offload_maptypes.12, ptr [[TMP21]], align 4
3403 // CHECK3-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
3404 // CHECK3-NEXT:    store ptr null, ptr [[TMP22]], align 4
3405 // CHECK3-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
3406 // CHECK3-NEXT:    store ptr null, ptr [[TMP23]], align 4
3407 // CHECK3-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
3408 // CHECK3-NEXT:    store i64 10, ptr [[TMP24]], align 8
3409 // CHECK3-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
3410 // CHECK3-NEXT:    store i64 0, ptr [[TMP25]], align 8
3411 // CHECK3-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
3412 // CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP26]], align 4
3413 // CHECK3-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
3414 // CHECK3-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP27]], align 4
3415 // CHECK3-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
3416 // CHECK3-NEXT:    store i32 0, ptr [[TMP28]], align 4
3417 // CHECK3-NEXT:    [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.region_id, ptr [[KERNEL_ARGS]])
3418 // CHECK3-NEXT:    [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
3419 // CHECK3-NEXT:    br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
3420 // CHECK3:       omp_offload.failed:
3421 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR3]]
3422 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]
3423 // CHECK3:       omp_offload.cont:
3424 // CHECK3-NEXT:    br label [[OMP_IF_END:%.*]]
3425 // CHECK3:       omp_if.else:
3426 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR3]]
3427 // CHECK3-NEXT:    br label [[OMP_IF_END]]
3428 // CHECK3:       omp_if.end:
3429 // CHECK3-NEXT:    [[TMP31:%.*]] = load i32, ptr [[A]], align 4
3430 // CHECK3-NEXT:    ret i32 [[TMP31]]
3431 //
3432 //
3433 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215
3434 // CHECK3-SAME: (ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
3435 // CHECK3-NEXT:  entry:
3436 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
3437 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
3438 // CHECK3-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
3439 // CHECK3-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
3440 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
3441 // CHECK3-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
3442 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
3443 // CHECK3-NEXT:    store i32 [[B]], ptr [[B_ADDR]], align 4
3444 // CHECK3-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
3445 // CHECK3-NEXT:    store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
3446 // CHECK3-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
3447 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
3448 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
3449 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
3450 // CHECK3-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
3451 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4
3452 // CHECK3-NEXT:    store i32 [[TMP4]], ptr [[B_CASTED]], align 4
3453 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4
3454 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.omp_outlined, ptr [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], ptr [[TMP3]])
3455 // CHECK3-NEXT:    ret void
3456 //
3457 //
3458 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.omp_outlined
3459 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
3460 // CHECK3-NEXT:  entry:
3461 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
3462 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
3463 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
3464 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
3465 // CHECK3-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
3466 // CHECK3-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
3467 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
3468 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
3469 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
3470 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
3471 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
3472 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3473 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3474 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
3475 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
3476 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
3477 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
3478 // CHECK3-NEXT:    store i32 [[B]], ptr [[B_ADDR]], align 4
3479 // CHECK3-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
3480 // CHECK3-NEXT:    store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
3481 // CHECK3-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
3482 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
3483 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
3484 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
3485 // CHECK3-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
3486 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
3487 // CHECK3-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4
3488 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
3489 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
3490 // CHECK3-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
3491 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
3492 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
3493 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
3494 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9
3495 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3496 // CHECK3:       cond.true:
3497 // CHECK3-NEXT:    br label [[COND_END:%.*]]
3498 // CHECK3:       cond.false:
3499 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
3500 // CHECK3-NEXT:    br label [[COND_END]]
3501 // CHECK3:       cond.end:
3502 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
3503 // CHECK3-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
3504 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
3505 // CHECK3-NEXT:    store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4
3506 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
3507 // CHECK3:       omp.inner.for.cond:
3508 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39:![0-9]+]]
3509 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP39]]
3510 // CHECK3-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
3511 // CHECK3-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3512 // CHECK3:       omp.inner.for.body:
3513 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]]
3514 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
3515 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
3516 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP39]]
3517 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP39]]
3518 // CHECK3-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP12]] to double
3519 // CHECK3-NEXT:    [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00
3520 // CHECK3-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0
3521 // CHECK3-NEXT:    store double [[ADD4]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP39]]
3522 // CHECK3-NEXT:    [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0
3523 // CHECK3-NEXT:    [[TMP13:%.*]] = load double, ptr [[A5]], align 4, !llvm.access.group [[ACC_GRP39]]
3524 // CHECK3-NEXT:    [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
3525 // CHECK3-NEXT:    store double [[INC]], ptr [[A5]], align 4, !llvm.access.group [[ACC_GRP39]]
3526 // CHECK3-NEXT:    [[CONV6:%.*]] = fptosi double [[INC]] to i16
3527 // CHECK3-NEXT:    [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]]
3528 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i32 [[TMP14]]
3529 // CHECK3-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1
3530 // CHECK3-NEXT:    store i16 [[CONV6]], ptr [[ARRAYIDX7]], align 2, !llvm.access.group [[ACC_GRP39]]
3531 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
3532 // CHECK3:       omp.body.continue:
3533 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
3534 // CHECK3:       omp.inner.for.inc:
3535 // CHECK3-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]]
3536 // CHECK3-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1
3537 // CHECK3-NEXT:    store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]]
3538 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]]
3539 // CHECK3:       omp.inner.for.end:
3540 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
3541 // CHECK3:       omp.loop.exit:
3542 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])
3543 // CHECK3-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
3544 // CHECK3-NEXT:    [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
3545 // CHECK3-NEXT:    br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
3546 // CHECK3:       .omp.final.then:
3547 // CHECK3-NEXT:    store i32 10, ptr [[I]], align 4
3548 // CHECK3-NEXT:    br label [[DOTOMP_FINAL_DONE]]
3549 // CHECK3:       .omp.final.done:
3550 // CHECK3-NEXT:    ret void
3551 //
3552 //
3553 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197
3554 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
3555 // CHECK3-NEXT:  entry:
3556 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
3557 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
3558 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
3559 // CHECK3-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
3560 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
3561 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
3562 // CHECK3-NEXT:    [[N_CASTED:%.*]] = alloca i32, align 4
3563 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
3564 // CHECK3-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
3565 // CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
3566 // CHECK3-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
3567 // CHECK3-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
3568 // CHECK3-NEXT:    store i32 [[AAA]], ptr [[AAA_ADDR]], align 4
3569 // CHECK3-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
3570 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
3571 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
3572 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 4
3573 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4
3574 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4
3575 // CHECK3-NEXT:    store i32 [[TMP3]], ptr [[N_CASTED]], align 4
3576 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N_CASTED]], align 4
3577 // CHECK3-NEXT:    [[TMP5:%.*]] = load i16, ptr [[AA_ADDR]], align 2
3578 // CHECK3-NEXT:    store i16 [[TMP5]], ptr [[AA_CASTED]], align 2
3579 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[AA_CASTED]], align 4
3580 // CHECK3-NEXT:    [[TMP7:%.*]] = load i8, ptr [[AAA_ADDR]], align 1
3581 // CHECK3-NEXT:    store i8 [[TMP7]], ptr [[AAA_CASTED]], align 1
3582 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[AAA_CASTED]], align 4
3583 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], ptr [[TMP0]])
3584 // CHECK3-NEXT:    ret void
3585 //
3586 //
3587 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.omp_outlined
3588 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
3589 // CHECK3-NEXT:  entry:
3590 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
3591 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
3592 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
3593 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
3594 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
3595 // CHECK3-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
3596 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
3597 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
3598 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
3599 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
3600 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
3601 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
3602 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
3603 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
3604 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
3605 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3606 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3607 // CHECK3-NEXT:    [[I5:%.*]] = alloca i32, align 4
3608 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
3609 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
3610 // CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
3611 // CHECK3-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
3612 // CHECK3-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
3613 // CHECK3-NEXT:    store i32 [[AAA]], ptr [[AAA_ADDR]], align 4
3614 // CHECK3-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
3615 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
3616 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
3617 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
3618 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
3619 // CHECK3-NEXT:    store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
3620 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
3621 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
3622 // CHECK3-NEXT:    [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
3623 // CHECK3-NEXT:    [[SUB3:%.*]] = sub i32 [[SUB]], 1
3624 // CHECK3-NEXT:    [[ADD:%.*]] = add i32 [[SUB3]], 1
3625 // CHECK3-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
3626 // CHECK3-NEXT:    [[SUB4:%.*]] = sub i32 [[DIV]], 1
3627 // CHECK3-NEXT:    store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 4
3628 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
3629 // CHECK3-NEXT:    store i32 [[TMP5]], ptr [[I]], align 4
3630 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
3631 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
3632 // CHECK3-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
3633 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
3634 // CHECK3:       omp.precond.then:
3635 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
3636 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
3637 // CHECK3-NEXT:    store i32 [[TMP8]], ptr [[DOTOMP_UB]], align 4
3638 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
3639 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
3640 // CHECK3-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
3641 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4
3642 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4u(ptr @[[GLOB1]], i32 [[TMP10]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
3643 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
3644 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
3645 // CHECK3-NEXT:    [[CMP6:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]]
3646 // CHECK3-NEXT:    br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3647 // CHECK3:       cond.true:
3648 // CHECK3-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
3649 // CHECK3-NEXT:    br label [[COND_END:%.*]]
3650 // CHECK3:       cond.false:
3651 // CHECK3-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
3652 // CHECK3-NEXT:    br label [[COND_END]]
3653 // CHECK3:       cond.end:
3654 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ]
3655 // CHECK3-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
3656 // CHECK3-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
3657 // CHECK3-NEXT:    store i32 [[TMP15]], ptr [[DOTOMP_IV]], align 4
3658 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
3659 // CHECK3:       omp.inner.for.cond:
3660 // CHECK3-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP42:![0-9]+]]
3661 // CHECK3-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP42]]
3662 // CHECK3-NEXT:    [[ADD7:%.*]] = add i32 [[TMP17]], 1
3663 // CHECK3-NEXT:    [[CMP8:%.*]] = icmp ult i32 [[TMP16]], [[ADD7]]
3664 // CHECK3-NEXT:    br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3665 // CHECK3:       omp.inner.for.body:
3666 // CHECK3-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group [[ACC_GRP42]]
3667 // CHECK3-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP42]]
3668 // CHECK3-NEXT:    [[MUL:%.*]] = mul i32 [[TMP19]], 1
3669 // CHECK3-NEXT:    [[ADD9:%.*]] = add i32 [[TMP18]], [[MUL]]
3670 // CHECK3-NEXT:    store i32 [[ADD9]], ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP42]]
3671 // CHECK3-NEXT:    [[TMP20:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP42]]
3672 // CHECK3-NEXT:    [[ADD10:%.*]] = add nsw i32 [[TMP20]], 1
3673 // CHECK3-NEXT:    store i32 [[ADD10]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP42]]
3674 // CHECK3-NEXT:    [[TMP21:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP42]]
3675 // CHECK3-NEXT:    [[CONV:%.*]] = sext i16 [[TMP21]] to i32
3676 // CHECK3-NEXT:    [[ADD11:%.*]] = add nsw i32 [[CONV]], 1
3677 // CHECK3-NEXT:    [[CONV12:%.*]] = trunc i32 [[ADD11]] to i16
3678 // CHECK3-NEXT:    store i16 [[CONV12]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP42]]
3679 // CHECK3-NEXT:    [[TMP22:%.*]] = load i8, ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP42]]
3680 // CHECK3-NEXT:    [[CONV13:%.*]] = sext i8 [[TMP22]] to i32
3681 // CHECK3-NEXT:    [[ADD14:%.*]] = add nsw i32 [[CONV13]], 1
3682 // CHECK3-NEXT:    [[CONV15:%.*]] = trunc i32 [[ADD14]] to i8
3683 // CHECK3-NEXT:    store i8 [[CONV15]], ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP42]]
3684 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2
3685 // CHECK3-NEXT:    [[TMP23:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP42]]
3686 // CHECK3-NEXT:    [[ADD16:%.*]] = add nsw i32 [[TMP23]], 1
3687 // CHECK3-NEXT:    store i32 [[ADD16]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP42]]
3688 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
3689 // CHECK3:       omp.body.continue:
3690 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
3691 // CHECK3:       omp.inner.for.inc:
3692 // CHECK3-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP42]]
3693 // CHECK3-NEXT:    [[ADD17:%.*]] = add i32 [[TMP24]], 1
3694 // CHECK3-NEXT:    store i32 [[ADD17]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP42]]
3695 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP43:![0-9]+]]
3696 // CHECK3:       omp.inner.for.end:
3697 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
3698 // CHECK3:       omp.loop.exit:
3699 // CHECK3-NEXT:    [[TMP25:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
3700 // CHECK3-NEXT:    [[TMP26:%.*]] = load i32, ptr [[TMP25]], align 4
3701 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP26]])
3702 // CHECK3-NEXT:    [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
3703 // CHECK3-NEXT:    [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
3704 // CHECK3-NEXT:    br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
3705 // CHECK3:       .omp.final.then:
3706 // CHECK3-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
3707 // CHECK3-NEXT:    [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
3708 // CHECK3-NEXT:    [[TMP31:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
3709 // CHECK3-NEXT:    [[SUB18:%.*]] = sub i32 [[TMP30]], [[TMP31]]
3710 // CHECK3-NEXT:    [[SUB19:%.*]] = sub i32 [[SUB18]], 1
3711 // CHECK3-NEXT:    [[ADD20:%.*]] = add i32 [[SUB19]], 1
3712 // CHECK3-NEXT:    [[DIV21:%.*]] = udiv i32 [[ADD20]], 1
3713 // CHECK3-NEXT:    [[MUL22:%.*]] = mul i32 [[DIV21]], 1
3714 // CHECK3-NEXT:    [[ADD23:%.*]] = add i32 [[TMP29]], [[MUL22]]
3715 // CHECK3-NEXT:    store i32 [[ADD23]], ptr [[I5]], align 4
3716 // CHECK3-NEXT:    br label [[DOTOMP_FINAL_DONE]]
3717 // CHECK3:       .omp.final.done:
3718 // CHECK3-NEXT:    br label [[OMP_PRECOND_END]]
3719 // CHECK3:       omp.precond.end:
3720 // CHECK3-NEXT:    ret void
3721 //
3722 //
3723 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180
3724 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
3725 // CHECK3-NEXT:  entry:
3726 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
3727 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
3728 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
3729 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
3730 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
3731 // CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
3732 // CHECK3-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
3733 // CHECK3-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
3734 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
3735 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
3736 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 4
3737 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4
3738 // CHECK3-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
3739 // CHECK3-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
3740 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4
3741 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], ptr [[TMP0]])
3742 // CHECK3-NEXT:    ret void
3743 //
3744 //
3745 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.omp_outlined
3746 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
3747 // CHECK3-NEXT:  entry:
3748 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
3749 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
3750 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
3751 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
3752 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
3753 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
3754 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
3755 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
3756 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
3757 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3758 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3759 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
3760 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
3761 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
3762 // CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
3763 // CHECK3-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
3764 // CHECK3-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
3765 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
3766 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
3767 // CHECK3-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4
3768 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
3769 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
3770 // CHECK3-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
3771 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
3772 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
3773 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
3774 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
3775 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3776 // CHECK3:       cond.true:
3777 // CHECK3-NEXT:    br label [[COND_END:%.*]]
3778 // CHECK3:       cond.false:
3779 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
3780 // CHECK3-NEXT:    br label [[COND_END]]
3781 // CHECK3:       cond.end:
3782 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
3783 // CHECK3-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
3784 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
3785 // CHECK3-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
3786 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
3787 // CHECK3:       omp.inner.for.cond:
3788 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45:![0-9]+]]
3789 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP45]]
3790 // CHECK3-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
3791 // CHECK3-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3792 // CHECK3:       omp.inner.for.body:
3793 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]]
3794 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
3795 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
3796 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP45]]
3797 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP45]]
3798 // CHECK3-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
3799 // CHECK3-NEXT:    store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP45]]
3800 // CHECK3-NEXT:    [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP45]]
3801 // CHECK3-NEXT:    [[CONV:%.*]] = sext i16 [[TMP10]] to i32
3802 // CHECK3-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV]], 1
3803 // CHECK3-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
3804 // CHECK3-NEXT:    store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP45]]
3805 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2
3806 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP45]]
3807 // CHECK3-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1
3808 // CHECK3-NEXT:    store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP45]]
3809 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
3810 // CHECK3:       omp.body.continue:
3811 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
3812 // CHECK3:       omp.inner.for.inc:
3813 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]]
3814 // CHECK3-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP12]], 1
3815 // CHECK3-NEXT:    store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]]
3816 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]]
3817 // CHECK3:       omp.inner.for.end:
3818 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
3819 // CHECK3:       omp.loop.exit:
3820 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])
3821 // CHECK3-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
3822 // CHECK3-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
3823 // CHECK3-NEXT:    br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
3824 // CHECK3:       .omp.final.then:
3825 // CHECK3-NEXT:    store i32 10, ptr [[I]], align 4
3826 // CHECK3-NEXT:    br label [[DOTOMP_FINAL_DONE]]
3827 // CHECK3:       .omp.final.done:
3828 // CHECK3-NEXT:    ret void
3829 //
3830 //
3831 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
3832 // CHECK3-SAME: () #[[ATTR4]] {
3833 // CHECK3-NEXT:  entry:
3834 // CHECK3-NEXT:    call void @__tgt_register_requires(i64 1)
3835 // CHECK3-NEXT:    ret void
3836 //
3837 //
3838 // CHECK5-LABEL: define {{[^@]+}}@_Z3fooi
3839 // CHECK5-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
3840 // CHECK5-NEXT:  entry:
3841 // CHECK5-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
3842 // CHECK5-NEXT:    [[A:%.*]] = alloca i32, align 4
3843 // CHECK5-NEXT:    [[AA:%.*]] = alloca i16, align 2
3844 // CHECK5-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
3845 // CHECK5-NEXT:    [[SAVED_STACK:%.*]] = alloca ptr, align 8
3846 // CHECK5-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
3847 // CHECK5-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
3848 // CHECK5-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
3849 // CHECK5-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
3850 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
3851 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
3852 // CHECK5-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
3853 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
3854 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR__CASTED3:%.*]] = alloca i64, align 8
3855 // CHECK5-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8
3856 // CHECK5-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 8
3857 // CHECK5-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 8
3858 // CHECK5-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4
3859 // CHECK5-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
3860 // CHECK5-NEXT:    [[AA_CASTED4:%.*]] = alloca i64, align 8
3861 // CHECK5-NEXT:    [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [1 x ptr], align 8
3862 // CHECK5-NEXT:    [[DOTOFFLOAD_PTRS6:%.*]] = alloca [1 x ptr], align 8
3863 // CHECK5-NEXT:    [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [1 x ptr], align 8
3864 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4
3865 // CHECK5-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
3866 // CHECK5-NEXT:    [[A_CASTED8:%.*]] = alloca i64, align 8
3867 // CHECK5-NEXT:    [[AA_CASTED9:%.*]] = alloca i64, align 8
3868 // CHECK5-NEXT:    [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [2 x ptr], align 8
3869 // CHECK5-NEXT:    [[DOTOFFLOAD_PTRS11:%.*]] = alloca [2 x ptr], align 8
3870 // CHECK5-NEXT:    [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [2 x ptr], align 8
3871 // CHECK5-NEXT:    [[_TMP13:%.*]] = alloca i32, align 4
3872 // CHECK5-NEXT:    [[KERNEL_ARGS14:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
3873 // CHECK5-NEXT:    [[A_CASTED17:%.*]] = alloca i64, align 8
3874 // CHECK5-NEXT:    [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [9 x ptr], align 8
3875 // CHECK5-NEXT:    [[DOTOFFLOAD_PTRS21:%.*]] = alloca [9 x ptr], align 8
3876 // CHECK5-NEXT:    [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [9 x ptr], align 8
3877 // CHECK5-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 8
3878 // CHECK5-NEXT:    [[_TMP23:%.*]] = alloca i32, align 4
3879 // CHECK5-NEXT:    [[KERNEL_ARGS24:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
3880 // CHECK5-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])
3881 // CHECK5-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
3882 // CHECK5-NEXT:    store i32 0, ptr [[A]], align 4
3883 // CHECK5-NEXT:    store i16 0, ptr [[AA]], align 2
3884 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
3885 // CHECK5-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
3886 // CHECK5-NEXT:    [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()
3887 // CHECK5-NEXT:    store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8
3888 // CHECK5-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4
3889 // CHECK5-NEXT:    store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8
3890 // CHECK5-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
3891 // CHECK5-NEXT:    [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
3892 // CHECK5-NEXT:    [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]]
3893 // CHECK5-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8
3894 // CHECK5-NEXT:    store i64 [[TMP5]], ptr [[__VLA_EXPR1]], align 8
3895 // CHECK5-NEXT:    [[TMP7:%.*]] = load i32, ptr [[A]], align 4
3896 // CHECK5-NEXT:    store i32 [[TMP7]], ptr [[DOTCAPTURE_EXPR_]], align 4
3897 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A]], align 4
3898 // CHECK5-NEXT:    store i32 [[TMP8]], ptr [[DOTCAPTURE_EXPR_2]], align 4
3899 // CHECK5-NEXT:    [[TMP9:%.*]] = load i16, ptr [[AA]], align 2
3900 // CHECK5-NEXT:    store i16 [[TMP9]], ptr [[AA_CASTED]], align 2
3901 // CHECK5-NEXT:    [[TMP10:%.*]] = load i64, ptr [[AA_CASTED]], align 8
3902 // CHECK5-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
3903 // CHECK5-NEXT:    store i32 [[TMP11]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
3904 // CHECK5-NEXT:    [[TMP12:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8
3905 // CHECK5-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
3906 // CHECK5-NEXT:    store i32 [[TMP13]], ptr [[DOTCAPTURE_EXPR__CASTED3]], align 4
3907 // CHECK5-NEXT:    [[TMP14:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED3]], align 8
3908 // CHECK5-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3909 // CHECK5-NEXT:    store i64 [[TMP10]], ptr [[TMP15]], align 8
3910 // CHECK5-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3911 // CHECK5-NEXT:    store i64 [[TMP10]], ptr [[TMP16]], align 8
3912 // CHECK5-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
3913 // CHECK5-NEXT:    store ptr null, ptr [[TMP17]], align 8
3914 // CHECK5-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
3915 // CHECK5-NEXT:    store i64 [[TMP12]], ptr [[TMP18]], align 8
3916 // CHECK5-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
3917 // CHECK5-NEXT:    store i64 [[TMP12]], ptr [[TMP19]], align 8
3918 // CHECK5-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
3919 // CHECK5-NEXT:    store ptr null, ptr [[TMP20]], align 8
3920 // CHECK5-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
3921 // CHECK5-NEXT:    store i64 [[TMP14]], ptr [[TMP21]], align 8
3922 // CHECK5-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
3923 // CHECK5-NEXT:    store i64 [[TMP14]], ptr [[TMP22]], align 8
3924 // CHECK5-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
3925 // CHECK5-NEXT:    store ptr null, ptr [[TMP23]], align 8
3926 // CHECK5-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3927 // CHECK5-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3928 // CHECK5-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0
3929 // CHECK5-NEXT:    [[TMP27:%.*]] = load i16, ptr [[AA]], align 2
3930 // CHECK5-NEXT:    store i16 [[TMP27]], ptr [[TMP26]], align 4
3931 // CHECK5-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 1
3932 // CHECK5-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
3933 // CHECK5-NEXT:    store i32 [[TMP29]], ptr [[TMP28]], align 4
3934 // CHECK5-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 2
3935 // CHECK5-NEXT:    [[TMP31:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
3936 // CHECK5-NEXT:    store i32 [[TMP31]], ptr [[TMP30]], align 4
3937 // CHECK5-NEXT:    [[TMP32:%.*]] = call ptr @__kmpc_omp_target_task_alloc(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i64 120, i64 12, ptr @.omp_task_entry., i64 -1)
3938 // CHECK5-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP32]], i32 0, i32 0
3939 // CHECK5-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP33]], i32 0, i32 0
3940 // CHECK5-NEXT:    [[TMP35:%.*]] = load ptr, ptr [[TMP34]], align 8
3941 // CHECK5-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP35]], ptr align 4 [[AGG_CAPTURED]], i64 12, i1 false)
3942 // CHECK5-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP32]], i32 0, i32 1
3943 // CHECK5-NEXT:    [[TMP37:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP36]], i32 0, i32 0
3944 // CHECK5-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP37]], ptr align 8 [[TMP24]], i64 24, i1 false)
3945 // CHECK5-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP36]], i32 0, i32 1
3946 // CHECK5-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP38]], ptr align 8 [[TMP25]], i64 24, i1 false)
3947 // CHECK5-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP36]], i32 0, i32 2
3948 // CHECK5-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP39]], ptr align 8 @.offload_sizes, i64 24, i1 false)
3949 // CHECK5-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP36]], i32 0, i32 3
3950 // CHECK5-NEXT:    [[TMP41:%.*]] = load i16, ptr [[AA]], align 2
3951 // CHECK5-NEXT:    store i16 [[TMP41]], ptr [[TMP40]], align 8
3952 // CHECK5-NEXT:    [[TMP42:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB2]], i32 [[TMP0]], ptr [[TMP32]])
3953 // CHECK5-NEXT:    [[TMP43:%.*]] = load i32, ptr [[A]], align 4
3954 // CHECK5-NEXT:    store i32 [[TMP43]], ptr [[A_CASTED]], align 4
3955 // CHECK5-NEXT:    [[TMP44:%.*]] = load i64, ptr [[A_CASTED]], align 8
3956 // CHECK5-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l102(i64 [[TMP44]]) #[[ATTR3:[0-9]+]]
3957 // CHECK5-NEXT:    [[TMP45:%.*]] = load i16, ptr [[AA]], align 2
3958 // CHECK5-NEXT:    store i16 [[TMP45]], ptr [[AA_CASTED4]], align 2
3959 // CHECK5-NEXT:    [[TMP46:%.*]] = load i64, ptr [[AA_CASTED4]], align 8
3960 // CHECK5-NEXT:    [[TMP47:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0
3961 // CHECK5-NEXT:    store i64 [[TMP46]], ptr [[TMP47]], align 8
3962 // CHECK5-NEXT:    [[TMP48:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0
3963 // CHECK5-NEXT:    store i64 [[TMP46]], ptr [[TMP48]], align 8
3964 // CHECK5-NEXT:    [[TMP49:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 0
3965 // CHECK5-NEXT:    store ptr null, ptr [[TMP49]], align 8
3966 // CHECK5-NEXT:    [[TMP50:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0
3967 // CHECK5-NEXT:    [[TMP51:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0
3968 // CHECK5-NEXT:    [[TMP52:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
3969 // CHECK5-NEXT:    store i32 2, ptr [[TMP52]], align 4
3970 // CHECK5-NEXT:    [[TMP53:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
3971 // CHECK5-NEXT:    store i32 1, ptr [[TMP53]], align 4
3972 // CHECK5-NEXT:    [[TMP54:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
3973 // CHECK5-NEXT:    store ptr [[TMP50]], ptr [[TMP54]], align 8
3974 // CHECK5-NEXT:    [[TMP55:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
3975 // CHECK5-NEXT:    store ptr [[TMP51]], ptr [[TMP55]], align 8
3976 // CHECK5-NEXT:    [[TMP56:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
3977 // CHECK5-NEXT:    store ptr @.offload_sizes.1, ptr [[TMP56]], align 8
3978 // CHECK5-NEXT:    [[TMP57:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
3979 // CHECK5-NEXT:    store ptr @.offload_maptypes.2, ptr [[TMP57]], align 8
3980 // CHECK5-NEXT:    [[TMP58:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
3981 // CHECK5-NEXT:    store ptr null, ptr [[TMP58]], align 8
3982 // CHECK5-NEXT:    [[TMP59:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
3983 // CHECK5-NEXT:    store ptr null, ptr [[TMP59]], align 8
3984 // CHECK5-NEXT:    [[TMP60:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
3985 // CHECK5-NEXT:    store i64 10, ptr [[TMP60]], align 8
3986 // CHECK5-NEXT:    [[TMP61:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
3987 // CHECK5-NEXT:    store i64 0, ptr [[TMP61]], align 8
3988 // CHECK5-NEXT:    [[TMP62:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
3989 // CHECK5-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP62]], align 4
3990 // CHECK5-NEXT:    [[TMP63:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
3991 // CHECK5-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP63]], align 4
3992 // CHECK5-NEXT:    [[TMP64:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
3993 // CHECK5-NEXT:    store i32 0, ptr [[TMP64]], align 4
3994 // CHECK5-NEXT:    [[TMP65:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.region_id, ptr [[KERNEL_ARGS]])
3995 // CHECK5-NEXT:    [[TMP66:%.*]] = icmp ne i32 [[TMP65]], 0
3996 // CHECK5-NEXT:    br i1 [[TMP66]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
3997 // CHECK5:       omp_offload.failed:
3998 // CHECK5-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i64 [[TMP46]]) #[[ATTR3]]
3999 // CHECK5-NEXT:    br label [[OMP_OFFLOAD_CONT]]
4000 // CHECK5:       omp_offload.cont:
4001 // CHECK5-NEXT:    [[TMP67:%.*]] = load i32, ptr [[A]], align 4
4002 // CHECK5-NEXT:    store i32 [[TMP67]], ptr [[A_CASTED8]], align 4
4003 // CHECK5-NEXT:    [[TMP68:%.*]] = load i64, ptr [[A_CASTED8]], align 8
4004 // CHECK5-NEXT:    [[TMP69:%.*]] = load i16, ptr [[AA]], align 2
4005 // CHECK5-NEXT:    store i16 [[TMP69]], ptr [[AA_CASTED9]], align 2
4006 // CHECK5-NEXT:    [[TMP70:%.*]] = load i64, ptr [[AA_CASTED9]], align 8
4007 // CHECK5-NEXT:    [[TMP71:%.*]] = load i32, ptr [[N_ADDR]], align 4
4008 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP71]], 10
4009 // CHECK5-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
4010 // CHECK5:       omp_if.then:
4011 // CHECK5-NEXT:    [[TMP72:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
4012 // CHECK5-NEXT:    store i64 [[TMP68]], ptr [[TMP72]], align 8
4013 // CHECK5-NEXT:    [[TMP73:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
4014 // CHECK5-NEXT:    store i64 [[TMP68]], ptr [[TMP73]], align 8
4015 // CHECK5-NEXT:    [[TMP74:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 0
4016 // CHECK5-NEXT:    store ptr null, ptr [[TMP74]], align 8
4017 // CHECK5-NEXT:    [[TMP75:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 1
4018 // CHECK5-NEXT:    store i64 [[TMP70]], ptr [[TMP75]], align 8
4019 // CHECK5-NEXT:    [[TMP76:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 1
4020 // CHECK5-NEXT:    store i64 [[TMP70]], ptr [[TMP76]], align 8
4021 // CHECK5-NEXT:    [[TMP77:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 1
4022 // CHECK5-NEXT:    store ptr null, ptr [[TMP77]], align 8
4023 // CHECK5-NEXT:    [[TMP78:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
4024 // CHECK5-NEXT:    [[TMP79:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
4025 // CHECK5-NEXT:    [[TMP80:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 0
4026 // CHECK5-NEXT:    store i32 2, ptr [[TMP80]], align 4
4027 // CHECK5-NEXT:    [[TMP81:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 1
4028 // CHECK5-NEXT:    store i32 2, ptr [[TMP81]], align 4
4029 // CHECK5-NEXT:    [[TMP82:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 2
4030 // CHECK5-NEXT:    store ptr [[TMP78]], ptr [[TMP82]], align 8
4031 // CHECK5-NEXT:    [[TMP83:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 3
4032 // CHECK5-NEXT:    store ptr [[TMP79]], ptr [[TMP83]], align 8
4033 // CHECK5-NEXT:    [[TMP84:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 4
4034 // CHECK5-NEXT:    store ptr @.offload_sizes.3, ptr [[TMP84]], align 8
4035 // CHECK5-NEXT:    [[TMP85:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 5
4036 // CHECK5-NEXT:    store ptr @.offload_maptypes.4, ptr [[TMP85]], align 8
4037 // CHECK5-NEXT:    [[TMP86:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 6
4038 // CHECK5-NEXT:    store ptr null, ptr [[TMP86]], align 8
4039 // CHECK5-NEXT:    [[TMP87:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 7
4040 // CHECK5-NEXT:    store ptr null, ptr [[TMP87]], align 8
4041 // CHECK5-NEXT:    [[TMP88:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 8
4042 // CHECK5-NEXT:    store i64 10, ptr [[TMP88]], align 8
4043 // CHECK5-NEXT:    [[TMP89:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 9
4044 // CHECK5-NEXT:    store i64 0, ptr [[TMP89]], align 8
4045 // CHECK5-NEXT:    [[TMP90:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 10
4046 // CHECK5-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP90]], align 4
4047 // CHECK5-NEXT:    [[TMP91:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 11
4048 // CHECK5-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP91]], align 4
4049 // CHECK5-NEXT:    [[TMP92:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 12
4050 // CHECK5-NEXT:    store i32 0, ptr [[TMP92]], align 4
4051 // CHECK5-NEXT:    [[TMP93:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.region_id, ptr [[KERNEL_ARGS14]])
4052 // CHECK5-NEXT:    [[TMP94:%.*]] = icmp ne i32 [[TMP93]], 0
4053 // CHECK5-NEXT:    br i1 [[TMP94]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]]
4054 // CHECK5:       omp_offload.failed15:
4055 // CHECK5-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP68]], i64 [[TMP70]]) #[[ATTR3]]
4056 // CHECK5-NEXT:    br label [[OMP_OFFLOAD_CONT16]]
4057 // CHECK5:       omp_offload.cont16:
4058 // CHECK5-NEXT:    br label [[OMP_IF_END:%.*]]
4059 // CHECK5:       omp_if.else:
4060 // CHECK5-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP68]], i64 [[TMP70]]) #[[ATTR3]]
4061 // CHECK5-NEXT:    br label [[OMP_IF_END]]
4062 // CHECK5:       omp_if.end:
4063 // CHECK5-NEXT:    [[TMP95:%.*]] = load i32, ptr [[A]], align 4
4064 // CHECK5-NEXT:    store i32 [[TMP95]], ptr [[A_CASTED17]], align 4
4065 // CHECK5-NEXT:    [[TMP96:%.*]] = load i64, ptr [[A_CASTED17]], align 8
4066 // CHECK5-NEXT:    [[TMP97:%.*]] = load i32, ptr [[N_ADDR]], align 4
4067 // CHECK5-NEXT:    [[CMP18:%.*]] = icmp sgt i32 [[TMP97]], 20
4068 // CHECK5-NEXT:    br i1 [[CMP18]], label [[OMP_IF_THEN19:%.*]], label [[OMP_IF_ELSE27:%.*]]
4069 // CHECK5:       omp_if.then19:
4070 // CHECK5-NEXT:    [[TMP98:%.*]] = mul nuw i64 [[TMP2]], 4
4071 // CHECK5-NEXT:    [[TMP99:%.*]] = mul nuw i64 5, [[TMP5]]
4072 // CHECK5-NEXT:    [[TMP100:%.*]] = mul nuw i64 [[TMP99]], 8
4073 // CHECK5-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes.5, i64 72, i1 false)
4074 // CHECK5-NEXT:    [[TMP101:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0
4075 // CHECK5-NEXT:    store i64 [[TMP96]], ptr [[TMP101]], align 8
4076 // CHECK5-NEXT:    [[TMP102:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 0
4077 // CHECK5-NEXT:    store i64 [[TMP96]], ptr [[TMP102]], align 8
4078 // CHECK5-NEXT:    [[TMP103:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 0
4079 // CHECK5-NEXT:    store ptr null, ptr [[TMP103]], align 8
4080 // CHECK5-NEXT:    [[TMP104:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1
4081 // CHECK5-NEXT:    store ptr [[B]], ptr [[TMP104]], align 8
4082 // CHECK5-NEXT:    [[TMP105:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 1
4083 // CHECK5-NEXT:    store ptr [[B]], ptr [[TMP105]], align 8
4084 // CHECK5-NEXT:    [[TMP106:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 1
4085 // CHECK5-NEXT:    store ptr null, ptr [[TMP106]], align 8
4086 // CHECK5-NEXT:    [[TMP107:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 2
4087 // CHECK5-NEXT:    store i64 [[TMP2]], ptr [[TMP107]], align 8
4088 // CHECK5-NEXT:    [[TMP108:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 2
4089 // CHECK5-NEXT:    store i64 [[TMP2]], ptr [[TMP108]], align 8
4090 // CHECK5-NEXT:    [[TMP109:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 2
4091 // CHECK5-NEXT:    store ptr null, ptr [[TMP109]], align 8
4092 // CHECK5-NEXT:    [[TMP110:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 3
4093 // CHECK5-NEXT:    store ptr [[VLA]], ptr [[TMP110]], align 8
4094 // CHECK5-NEXT:    [[TMP111:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 3
4095 // CHECK5-NEXT:    store ptr [[VLA]], ptr [[TMP111]], align 8
4096 // CHECK5-NEXT:    [[TMP112:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 3
4097 // CHECK5-NEXT:    store i64 [[TMP98]], ptr [[TMP112]], align 8
4098 // CHECK5-NEXT:    [[TMP113:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 3
4099 // CHECK5-NEXT:    store ptr null, ptr [[TMP113]], align 8
4100 // CHECK5-NEXT:    [[TMP114:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 4
4101 // CHECK5-NEXT:    store ptr [[C]], ptr [[TMP114]], align 8
4102 // CHECK5-NEXT:    [[TMP115:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 4
4103 // CHECK5-NEXT:    store ptr [[C]], ptr [[TMP115]], align 8
4104 // CHECK5-NEXT:    [[TMP116:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 4
4105 // CHECK5-NEXT:    store ptr null, ptr [[TMP116]], align 8
4106 // CHECK5-NEXT:    [[TMP117:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 5
4107 // CHECK5-NEXT:    store i64 5, ptr [[TMP117]], align 8
4108 // CHECK5-NEXT:    [[TMP118:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 5
4109 // CHECK5-NEXT:    store i64 5, ptr [[TMP118]], align 8
4110 // CHECK5-NEXT:    [[TMP119:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 5
4111 // CHECK5-NEXT:    store ptr null, ptr [[TMP119]], align 8
4112 // CHECK5-NEXT:    [[TMP120:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 6
4113 // CHECK5-NEXT:    store i64 [[TMP5]], ptr [[TMP120]], align 8
4114 // CHECK5-NEXT:    [[TMP121:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 6
4115 // CHECK5-NEXT:    store i64 [[TMP5]], ptr [[TMP121]], align 8
4116 // CHECK5-NEXT:    [[TMP122:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 6
4117 // CHECK5-NEXT:    store ptr null, ptr [[TMP122]], align 8
4118 // CHECK5-NEXT:    [[TMP123:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 7
4119 // CHECK5-NEXT:    store ptr [[VLA1]], ptr [[TMP123]], align 8
4120 // CHECK5-NEXT:    [[TMP124:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 7
4121 // CHECK5-NEXT:    store ptr [[VLA1]], ptr [[TMP124]], align 8
4122 // CHECK5-NEXT:    [[TMP125:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 7
4123 // CHECK5-NEXT:    store i64 [[TMP100]], ptr [[TMP125]], align 8
4124 // CHECK5-NEXT:    [[TMP126:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 7
4125 // CHECK5-NEXT:    store ptr null, ptr [[TMP126]], align 8
4126 // CHECK5-NEXT:    [[TMP127:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 8
4127 // CHECK5-NEXT:    store ptr [[D]], ptr [[TMP127]], align 8
4128 // CHECK5-NEXT:    [[TMP128:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 8
4129 // CHECK5-NEXT:    store ptr [[D]], ptr [[TMP128]], align 8
4130 // CHECK5-NEXT:    [[TMP129:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 8
4131 // CHECK5-NEXT:    store ptr null, ptr [[TMP129]], align 8
4132 // CHECK5-NEXT:    [[TMP130:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0
4133 // CHECK5-NEXT:    [[TMP131:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 0
4134 // CHECK5-NEXT:    [[TMP132:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0
4135 // CHECK5-NEXT:    [[TMP133:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 0
4136 // CHECK5-NEXT:    store i32 2, ptr [[TMP133]], align 4
4137 // CHECK5-NEXT:    [[TMP134:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 1
4138 // CHECK5-NEXT:    store i32 9, ptr [[TMP134]], align 4
4139 // CHECK5-NEXT:    [[TMP135:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 2
4140 // CHECK5-NEXT:    store ptr [[TMP130]], ptr [[TMP135]], align 8
4141 // CHECK5-NEXT:    [[TMP136:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 3
4142 // CHECK5-NEXT:    store ptr [[TMP131]], ptr [[TMP136]], align 8
4143 // CHECK5-NEXT:    [[TMP137:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 4
4144 // CHECK5-NEXT:    store ptr [[TMP132]], ptr [[TMP137]], align 8
4145 // CHECK5-NEXT:    [[TMP138:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 5
4146 // CHECK5-NEXT:    store ptr @.offload_maptypes.6, ptr [[TMP138]], align 8
4147 // CHECK5-NEXT:    [[TMP139:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 6
4148 // CHECK5-NEXT:    store ptr null, ptr [[TMP139]], align 8
4149 // CHECK5-NEXT:    [[TMP140:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 7
4150 // CHECK5-NEXT:    store ptr null, ptr [[TMP140]], align 8
4151 // CHECK5-NEXT:    [[TMP141:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 8
4152 // CHECK5-NEXT:    store i64 10, ptr [[TMP141]], align 8
4153 // CHECK5-NEXT:    [[TMP142:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 9
4154 // CHECK5-NEXT:    store i64 0, ptr [[TMP142]], align 8
4155 // CHECK5-NEXT:    [[TMP143:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 10
4156 // CHECK5-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP143]], align 4
4157 // CHECK5-NEXT:    [[TMP144:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 11
4158 // CHECK5-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP144]], align 4
4159 // CHECK5-NEXT:    [[TMP145:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 12
4160 // CHECK5-NEXT:    store i32 0, ptr [[TMP145]], align 4
4161 // CHECK5-NEXT:    [[TMP146:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.region_id, ptr [[KERNEL_ARGS24]])
4162 // CHECK5-NEXT:    [[TMP147:%.*]] = icmp ne i32 [[TMP146]], 0
4163 // CHECK5-NEXT:    br i1 [[TMP147]], label [[OMP_OFFLOAD_FAILED25:%.*]], label [[OMP_OFFLOAD_CONT26:%.*]]
4164 // CHECK5:       omp_offload.failed25:
4165 // CHECK5-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP96]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]]) #[[ATTR3]]
4166 // CHECK5-NEXT:    br label [[OMP_OFFLOAD_CONT26]]
4167 // CHECK5:       omp_offload.cont26:
4168 // CHECK5-NEXT:    br label [[OMP_IF_END28:%.*]]
4169 // CHECK5:       omp_if.else27:
4170 // CHECK5-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP96]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]]) #[[ATTR3]]
4171 // CHECK5-NEXT:    br label [[OMP_IF_END28]]
4172 // CHECK5:       omp_if.end28:
4173 // CHECK5-NEXT:    [[TMP148:%.*]] = load i32, ptr [[A]], align 4
4174 // CHECK5-NEXT:    [[TMP149:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
4175 // CHECK5-NEXT:    call void @llvm.stackrestore.p0(ptr [[TMP149]])
4176 // CHECK5-NEXT:    ret i32 [[TMP148]]
4177 //
4178 //
4179 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97
4180 // CHECK5-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] {
4181 // CHECK5-NEXT:  entry:
4182 // CHECK5-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
4183 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
4184 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8
4185 // CHECK5-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
4186 // CHECK5-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
4187 // CHECK5-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
4188 // CHECK5-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
4189 // CHECK5-NEXT:    store i64 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 8
4190 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
4191 // CHECK5-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4
4192 // CHECK5-NEXT:    call void @__kmpc_push_num_teams(ptr @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
4193 // CHECK5-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
4194 // CHECK5-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
4195 // CHECK5-NEXT:    [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8
4196 // CHECK5-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.omp_outlined, i64 [[TMP4]])
4197 // CHECK5-NEXT:    ret void
4198 //
4199 //
4200 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.omp_outlined
4201 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {
4202 // CHECK5-NEXT:  entry:
4203 // CHECK5-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
4204 // CHECK5-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
4205 // CHECK5-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
4206 // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
4207 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4
4208 // CHECK5-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
4209 // CHECK5-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
4210 // CHECK5-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4211 // CHECK5-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4212 // CHECK5-NEXT:    [[I:%.*]] = alloca i32, align 4
4213 // CHECK5-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
4214 // CHECK5-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
4215 // CHECK5-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
4216 // CHECK5-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
4217 // CHECK5-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4
4218 // CHECK5-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
4219 // CHECK5-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
4220 // CHECK5-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
4221 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
4222 // CHECK5-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
4223 // CHECK5-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4224 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
4225 // CHECK5-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4226 // CHECK5:       cond.true:
4227 // CHECK5-NEXT:    br label [[COND_END:%.*]]
4228 // CHECK5:       cond.false:
4229 // CHECK5-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4230 // CHECK5-NEXT:    br label [[COND_END]]
4231 // CHECK5:       cond.end:
4232 // CHECK5-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
4233 // CHECK5-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
4234 // CHECK5-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
4235 // CHECK5-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
4236 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
4237 // CHECK5:       omp.inner.for.cond:
4238 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10:![0-9]+]]
4239 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP10]]
4240 // CHECK5-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
4241 // CHECK5-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4242 // CHECK5:       omp.inner.for.body:
4243 // CHECK5-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]]
4244 // CHECK5-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
4245 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
4246 // CHECK5-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]]
4247 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
4248 // CHECK5:       omp.body.continue:
4249 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4250 // CHECK5:       omp.inner.for.inc:
4251 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]]
4252 // CHECK5-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
4253 // CHECK5-NEXT:    store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]]
4254 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
4255 // CHECK5:       omp.inner.for.end:
4256 // CHECK5-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
4257 // CHECK5:       omp.loop.exit:
4258 // CHECK5-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
4259 // CHECK5-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
4260 // CHECK5-NEXT:    [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
4261 // CHECK5-NEXT:    br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
4262 // CHECK5:       .omp.final.then:
4263 // CHECK5-NEXT:    store i32 10, ptr [[I]], align 4
4264 // CHECK5-NEXT:    br label [[DOTOMP_FINAL_DONE]]
4265 // CHECK5:       .omp.final.done:
4266 // CHECK5-NEXT:    ret void
4267 //
4268 //
4269 // CHECK5-LABEL: define {{[^@]+}}@.omp_task_privates_map.
4270 // CHECK5-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]], ptr noalias noundef [[TMP3:%.*]], ptr noalias noundef [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] {
4271 // CHECK5-NEXT:  entry:
4272 // CHECK5-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
4273 // CHECK5-NEXT:    [[DOTADDR1:%.*]] = alloca ptr, align 8
4274 // CHECK5-NEXT:    [[DOTADDR2:%.*]] = alloca ptr, align 8
4275 // CHECK5-NEXT:    [[DOTADDR3:%.*]] = alloca ptr, align 8
4276 // CHECK5-NEXT:    [[DOTADDR4:%.*]] = alloca ptr, align 8
4277 // CHECK5-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
4278 // CHECK5-NEXT:    store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
4279 // CHECK5-NEXT:    store ptr [[TMP2]], ptr [[DOTADDR2]], align 8
4280 // CHECK5-NEXT:    store ptr [[TMP3]], ptr [[DOTADDR3]], align 8
4281 // CHECK5-NEXT:    store ptr [[TMP4]], ptr [[DOTADDR4]], align 8
4282 // CHECK5-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[DOTADDR]], align 8
4283 // CHECK5-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP5]], i32 0, i32 0
4284 // CHECK5-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[DOTADDR2]], align 8
4285 // CHECK5-NEXT:    store ptr [[TMP6]], ptr [[TMP7]], align 8
4286 // CHECK5-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 1
4287 // CHECK5-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[DOTADDR3]], align 8
4288 // CHECK5-NEXT:    store ptr [[TMP8]], ptr [[TMP9]], align 8
4289 // CHECK5-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 2
4290 // CHECK5-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[DOTADDR4]], align 8
4291 // CHECK5-NEXT:    store ptr [[TMP10]], ptr [[TMP11]], align 8
4292 // CHECK5-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 3
4293 // CHECK5-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[DOTADDR1]], align 8
4294 // CHECK5-NEXT:    store ptr [[TMP12]], ptr [[TMP13]], align 8
4295 // CHECK5-NEXT:    ret void
4296 //
4297 //
4298 // CHECK5-LABEL: define {{[^@]+}}@.omp_task_entry.
4299 // CHECK5-SAME: (i32 noundef signext [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] {
4300 // CHECK5-NEXT:  entry:
4301 // CHECK5-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
4302 // CHECK5-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8
4303 // CHECK5-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8
4304 // CHECK5-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8
4305 // CHECK5-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8
4306 // CHECK5-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8
4307 // CHECK5-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca ptr, align 8
4308 // CHECK5-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca ptr, align 8
4309 // CHECK5-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca ptr, align 8
4310 // CHECK5-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca ptr, align 8
4311 // CHECK5-NEXT:    [[KERNEL_ARGS_I:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
4312 // CHECK5-NEXT:    [[AA_CASTED_I:%.*]] = alloca i64, align 8
4313 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i64, align 8
4314 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR__CASTED4_I:%.*]] = alloca i64, align 8
4315 // CHECK5-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 4
4316 // CHECK5-NEXT:    [[DOTADDR1:%.*]] = alloca ptr, align 8
4317 // CHECK5-NEXT:    store i32 [[TMP0]], ptr [[DOTADDR]], align 4
4318 // CHECK5-NEXT:    store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
4319 // CHECK5-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4
4320 // CHECK5-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8
4321 // CHECK5-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0
4322 // CHECK5-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2
4323 // CHECK5-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0
4324 // CHECK5-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8
4325 // CHECK5-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 1
4326 // CHECK5-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])
4327 // CHECK5-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
4328 // CHECK5-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])
4329 // CHECK5-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]])
4330 // CHECK5-NEXT:    store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !26
4331 // CHECK5-NEXT:    store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias !26
4332 // CHECK5-NEXT:    store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias !26
4333 // CHECK5-NEXT:    store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !26
4334 // CHECK5-NEXT:    store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias !26
4335 // CHECK5-NEXT:    store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias !26
4336 // CHECK5-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias !26
4337 // CHECK5-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !26
4338 // CHECK5-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias !26
4339 // CHECK5-NEXT:    call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]
4340 // CHECK5-NEXT:    [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !26
4341 // CHECK5-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !26
4342 // CHECK5-NEXT:    [[TMP14:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !26
4343 // CHECK5-NEXT:    [[TMP15:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !26
4344 // CHECK5-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP9]], i32 0, i32 1
4345 // CHECK5-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP9]], i32 0, i32 2
4346 // CHECK5-NEXT:    [[TMP18:%.*]] = load i32, ptr [[TMP16]], align 4
4347 // CHECK5-NEXT:    [[TMP19:%.*]] = insertvalue [3 x i32] zeroinitializer, i32 [[TMP18]], 0
4348 // CHECK5-NEXT:    store i32 2, ptr [[KERNEL_ARGS_I]], align 4, !noalias !26
4349 // CHECK5-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 1
4350 // CHECK5-NEXT:    store i32 3, ptr [[TMP20]], align 4, !noalias !26
4351 // CHECK5-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 2
4352 // CHECK5-NEXT:    store ptr [[TMP13]], ptr [[TMP21]], align 8, !noalias !26
4353 // CHECK5-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 3
4354 // CHECK5-NEXT:    store ptr [[TMP14]], ptr [[TMP22]], align 8, !noalias !26
4355 // CHECK5-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 4
4356 // CHECK5-NEXT:    store ptr [[TMP15]], ptr [[TMP23]], align 8, !noalias !26
4357 // CHECK5-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 5
4358 // CHECK5-NEXT:    store ptr @.offload_maptypes, ptr [[TMP24]], align 8, !noalias !26
4359 // CHECK5-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 6
4360 // CHECK5-NEXT:    store ptr null, ptr [[TMP25]], align 8, !noalias !26
4361 // CHECK5-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 7
4362 // CHECK5-NEXT:    store ptr null, ptr [[TMP26]], align 8, !noalias !26
4363 // CHECK5-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 8
4364 // CHECK5-NEXT:    store i64 10, ptr [[TMP27]], align 8, !noalias !26
4365 // CHECK5-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 9
4366 // CHECK5-NEXT:    store i64 1, ptr [[TMP28]], align 8, !noalias !26
4367 // CHECK5-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 10
4368 // CHECK5-NEXT:    store [3 x i32] [[TMP19]], ptr [[TMP29]], align 4, !noalias !26
4369 // CHECK5-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 11
4370 // CHECK5-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP30]], align 4, !noalias !26
4371 // CHECK5-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 12
4372 // CHECK5-NEXT:    store i32 0, ptr [[TMP31]], align 4, !noalias !26
4373 // CHECK5-NEXT:    [[TMP32:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 [[TMP18]], i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.region_id, ptr [[KERNEL_ARGS_I]])
4374 // CHECK5-NEXT:    [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0
4375 // CHECK5-NEXT:    br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]]
4376 // CHECK5:       omp_offload.failed.i:
4377 // CHECK5-NEXT:    [[TMP34:%.*]] = load i16, ptr [[TMP12]], align 2
4378 // CHECK5-NEXT:    store i16 [[TMP34]], ptr [[AA_CASTED_I]], align 2, !noalias !26
4379 // CHECK5-NEXT:    [[TMP35:%.*]] = load i64, ptr [[AA_CASTED_I]], align 8, !noalias !26
4380 // CHECK5-NEXT:    [[TMP36:%.*]] = load i32, ptr [[TMP16]], align 4
4381 // CHECK5-NEXT:    store i32 [[TMP36]], ptr [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !26
4382 // CHECK5-NEXT:    [[TMP37:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED_I]], align 8, !noalias !26
4383 // CHECK5-NEXT:    [[TMP38:%.*]] = load i32, ptr [[TMP17]], align 4
4384 // CHECK5-NEXT:    store i32 [[TMP38]], ptr [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !26
4385 // CHECK5-NEXT:    [[TMP39:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED4_I]], align 8, !noalias !26
4386 // CHECK5-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97(i64 [[TMP35]], i64 [[TMP37]], i64 [[TMP39]]) #[[ATTR3]]
4387 // CHECK5-NEXT:    br label [[DOTOMP_OUTLINED__EXIT]]
4388 // CHECK5:       .omp_outlined..exit:
4389 // CHECK5-NEXT:    ret i32 0
4390 //
4391 //
4392 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l102
4393 // CHECK5-SAME: (i64 noundef [[A:%.*]]) #[[ATTR2]] {
4394 // CHECK5-NEXT:  entry:
4395 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
4396 // CHECK5-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
4397 // CHECK5-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
4398 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
4399 // CHECK5-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 4
4400 // CHECK5-NEXT:    [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8
4401 // CHECK5-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l102.omp_outlined, i64 [[TMP1]])
4402 // CHECK5-NEXT:    ret void
4403 //
4404 //
4405 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l102.omp_outlined
4406 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] {
4407 // CHECK5-NEXT:  entry:
4408 // CHECK5-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
4409 // CHECK5-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
4410 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
4411 // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
4412 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4
4413 // CHECK5-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
4414 // CHECK5-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
4415 // CHECK5-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4416 // CHECK5-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4417 // CHECK5-NEXT:    [[A1:%.*]] = alloca i32, align 4
4418 // CHECK5-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
4419 // CHECK5-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
4420 // CHECK5-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
4421 // CHECK5-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
4422 // CHECK5-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4
4423 // CHECK5-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
4424 // CHECK5-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
4425 // CHECK5-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
4426 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
4427 // CHECK5-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
4428 // CHECK5-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4429 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
4430 // CHECK5-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4431 // CHECK5:       cond.true:
4432 // CHECK5-NEXT:    br label [[COND_END:%.*]]
4433 // CHECK5:       cond.false:
4434 // CHECK5-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4435 // CHECK5-NEXT:    br label [[COND_END]]
4436 // CHECK5:       cond.end:
4437 // CHECK5-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
4438 // CHECK5-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
4439 // CHECK5-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
4440 // CHECK5-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
4441 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
4442 // CHECK5:       omp.inner.for.cond:
4443 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4444 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4445 // CHECK5-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
4446 // CHECK5-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4447 // CHECK5:       omp.inner.for.body:
4448 // CHECK5-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4449 // CHECK5-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
4450 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
4451 // CHECK5-NEXT:    store i32 [[ADD]], ptr [[A1]], align 4, !nontemporal !27
4452 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A1]], align 4, !nontemporal !27
4453 // CHECK5-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
4454 // CHECK5-NEXT:    store i32 [[ADD3]], ptr [[A1]], align 4, !nontemporal !27
4455 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
4456 // CHECK5:       omp.body.continue:
4457 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4458 // CHECK5:       omp.inner.for.inc:
4459 // CHECK5-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
4460 // CHECK5-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP9]], 1
4461 // CHECK5-NEXT:    store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4
4462 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]
4463 // CHECK5:       omp.inner.for.end:
4464 // CHECK5-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
4465 // CHECK5:       omp.loop.exit:
4466 // CHECK5-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
4467 // CHECK5-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
4468 // CHECK5-NEXT:    [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
4469 // CHECK5-NEXT:    br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
4470 // CHECK5:       .omp.final.then:
4471 // CHECK5-NEXT:    store i32 10, ptr [[A_ADDR]], align 4
4472 // CHECK5-NEXT:    br label [[DOTOMP_FINAL_DONE]]
4473 // CHECK5:       .omp.final.done:
4474 // CHECK5-NEXT:    ret void
4475 //
4476 //
4477 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
4478 // CHECK5-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR2]] {
4479 // CHECK5-NEXT:  entry:
4480 // CHECK5-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
4481 // CHECK5-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
4482 // CHECK5-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
4483 // CHECK5-NEXT:    [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2
4484 // CHECK5-NEXT:    store i16 [[TMP0]], ptr [[AA_CASTED]], align 2
4485 // CHECK5-NEXT:    [[TMP1:%.*]] = load i64, ptr [[AA_CASTED]], align 8
4486 // CHECK5-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined, i64 [[TMP1]])
4487 // CHECK5-NEXT:    ret void
4488 //
4489 //
4490 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined
4491 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {
4492 // CHECK5-NEXT:  entry:
4493 // CHECK5-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
4494 // CHECK5-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
4495 // CHECK5-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
4496 // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
4497 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4
4498 // CHECK5-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
4499 // CHECK5-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
4500 // CHECK5-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4501 // CHECK5-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4502 // CHECK5-NEXT:    [[I:%.*]] = alloca i32, align 4
4503 // CHECK5-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
4504 // CHECK5-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
4505 // CHECK5-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
4506 // CHECK5-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
4507 // CHECK5-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4
4508 // CHECK5-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
4509 // CHECK5-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
4510 // CHECK5-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
4511 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
4512 // CHECK5-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
4513 // CHECK5-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4514 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
4515 // CHECK5-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4516 // CHECK5:       cond.true:
4517 // CHECK5-NEXT:    br label [[COND_END:%.*]]
4518 // CHECK5:       cond.false:
4519 // CHECK5-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4520 // CHECK5-NEXT:    br label [[COND_END]]
4521 // CHECK5:       cond.end:
4522 // CHECK5-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
4523 // CHECK5-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
4524 // CHECK5-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
4525 // CHECK5-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
4526 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
4527 // CHECK5:       omp.inner.for.cond:
4528 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30:![0-9]+]]
4529 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP30]]
4530 // CHECK5-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
4531 // CHECK5-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4532 // CHECK5:       omp.inner.for.body:
4533 // CHECK5-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30]]
4534 // CHECK5-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
4535 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
4536 // CHECK5-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP30]]
4537 // CHECK5-NEXT:    [[TMP8:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP30]]
4538 // CHECK5-NEXT:    [[CONV:%.*]] = sext i16 [[TMP8]] to i32
4539 // CHECK5-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
4540 // CHECK5-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
4541 // CHECK5-NEXT:    store i16 [[CONV3]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP30]]
4542 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
4543 // CHECK5:       omp.body.continue:
4544 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4545 // CHECK5:       omp.inner.for.inc:
4546 // CHECK5-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30]]
4547 // CHECK5-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP9]], 1
4548 // CHECK5-NEXT:    store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30]]
4549 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]]
4550 // CHECK5:       omp.inner.for.end:
4551 // CHECK5-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
4552 // CHECK5:       omp.loop.exit:
4553 // CHECK5-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
4554 // CHECK5-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
4555 // CHECK5-NEXT:    [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
4556 // CHECK5-NEXT:    br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
4557 // CHECK5:       .omp.final.then:
4558 // CHECK5-NEXT:    store i32 10, ptr [[I]], align 4
4559 // CHECK5-NEXT:    br label [[DOTOMP_FINAL_DONE]]
4560 // CHECK5:       .omp.final.done:
4561 // CHECK5-NEXT:    ret void
4562 //
4563 //
4564 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118
4565 // CHECK5-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {
4566 // CHECK5-NEXT:  entry:
4567 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
4568 // CHECK5-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
4569 // CHECK5-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
4570 // CHECK5-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
4571 // CHECK5-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
4572 // CHECK5-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
4573 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
4574 // CHECK5-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 4
4575 // CHECK5-NEXT:    [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8
4576 // CHECK5-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2
4577 // CHECK5-NEXT:    store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
4578 // CHECK5-NEXT:    [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8
4579 // CHECK5-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined, i64 [[TMP1]], i64 [[TMP3]])
4580 // CHECK5-NEXT:    ret void
4581 //
4582 //
4583 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined
4584 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {
4585 // CHECK5-NEXT:  entry:
4586 // CHECK5-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
4587 // CHECK5-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
4588 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
4589 // CHECK5-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
4590 // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
4591 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4
4592 // CHECK5-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
4593 // CHECK5-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
4594 // CHECK5-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4595 // CHECK5-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4596 // CHECK5-NEXT:    [[I:%.*]] = alloca i32, align 4
4597 // CHECK5-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
4598 // CHECK5-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
4599 // CHECK5-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
4600 // CHECK5-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
4601 // CHECK5-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
4602 // CHECK5-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4
4603 // CHECK5-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
4604 // CHECK5-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
4605 // CHECK5-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
4606 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
4607 // CHECK5-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
4608 // CHECK5-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4609 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
4610 // CHECK5-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4611 // CHECK5:       cond.true:
4612 // CHECK5-NEXT:    br label [[COND_END:%.*]]
4613 // CHECK5:       cond.false:
4614 // CHECK5-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4615 // CHECK5-NEXT:    br label [[COND_END]]
4616 // CHECK5:       cond.end:
4617 // CHECK5-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
4618 // CHECK5-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
4619 // CHECK5-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
4620 // CHECK5-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
4621 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
4622 // CHECK5:       omp.inner.for.cond:
4623 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33:![0-9]+]]
4624 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP33]]
4625 // CHECK5-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
4626 // CHECK5-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4627 // CHECK5:       omp.inner.for.body:
4628 // CHECK5-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]]
4629 // CHECK5-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
4630 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
4631 // CHECK5-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP33]]
4632 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP33]]
4633 // CHECK5-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
4634 // CHECK5-NEXT:    store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP33]]
4635 // CHECK5-NEXT:    [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP33]]
4636 // CHECK5-NEXT:    [[CONV:%.*]] = sext i16 [[TMP9]] to i32
4637 // CHECK5-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV]], 1
4638 // CHECK5-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
4639 // CHECK5-NEXT:    store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP33]]
4640 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
4641 // CHECK5:       omp.body.continue:
4642 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4643 // CHECK5:       omp.inner.for.inc:
4644 // CHECK5-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]]
4645 // CHECK5-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP10]], 1
4646 // CHECK5-NEXT:    store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]]
4647 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]]
4648 // CHECK5:       omp.inner.for.end:
4649 // CHECK5-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
4650 // CHECK5:       omp.loop.exit:
4651 // CHECK5-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
4652 // CHECK5-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
4653 // CHECK5-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
4654 // CHECK5-NEXT:    br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
4655 // CHECK5:       .omp.final.then:
4656 // CHECK5-NEXT:    store i32 10, ptr [[I]], align 4
4657 // CHECK5-NEXT:    br label [[DOTOMP_FINAL_DONE]]
4658 // CHECK5:       .omp.final.done:
4659 // CHECK5-NEXT:    ret void
4660 //
4661 //
4662 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142
4663 // CHECK5-SAME: (i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] {
4664 // CHECK5-NEXT:  entry:
4665 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
4666 // CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
4667 // CHECK5-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
4668 // CHECK5-NEXT:    [[BN_ADDR:%.*]] = alloca ptr, align 8
4669 // CHECK5-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
4670 // CHECK5-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
4671 // CHECK5-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
4672 // CHECK5-NEXT:    [[CN_ADDR:%.*]] = alloca ptr, align 8
4673 // CHECK5-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
4674 // CHECK5-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
4675 // CHECK5-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
4676 // CHECK5-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
4677 // CHECK5-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
4678 // CHECK5-NEXT:    store ptr [[BN]], ptr [[BN_ADDR]], align 8
4679 // CHECK5-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
4680 // CHECK5-NEXT:    store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
4681 // CHECK5-NEXT:    store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8
4682 // CHECK5-NEXT:    store ptr [[CN]], ptr [[CN_ADDR]], align 8
4683 // CHECK5-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
4684 // CHECK5-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
4685 // CHECK5-NEXT:    [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
4686 // CHECK5-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8
4687 // CHECK5-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
4688 // CHECK5-NEXT:    [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
4689 // CHECK5-NEXT:    [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8
4690 // CHECK5-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8
4691 // CHECK5-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8
4692 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
4693 // CHECK5-NEXT:    store i32 [[TMP8]], ptr [[A_CASTED]], align 4
4694 // CHECK5-NEXT:    [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 8
4695 // CHECK5-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.omp_outlined, i64 [[TMP9]], ptr [[TMP0]], i64 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]])
4696 // CHECK5-NEXT:    ret void
4697 //
4698 //
4699 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.omp_outlined
4700 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] {
4701 // CHECK5-NEXT:  entry:
4702 // CHECK5-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
4703 // CHECK5-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
4704 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
4705 // CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
4706 // CHECK5-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
4707 // CHECK5-NEXT:    [[BN_ADDR:%.*]] = alloca ptr, align 8
4708 // CHECK5-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
4709 // CHECK5-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
4710 // CHECK5-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
4711 // CHECK5-NEXT:    [[CN_ADDR:%.*]] = alloca ptr, align 8
4712 // CHECK5-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
4713 // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
4714 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4
4715 // CHECK5-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
4716 // CHECK5-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
4717 // CHECK5-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
4718 // CHECK5-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
4719 // CHECK5-NEXT:    [[I:%.*]] = alloca i32, align 4
4720 // CHECK5-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
4721 // CHECK5-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
4722 // CHECK5-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
4723 // CHECK5-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
4724 // CHECK5-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
4725 // CHECK5-NEXT:    store ptr [[BN]], ptr [[BN_ADDR]], align 8
4726 // CHECK5-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
4727 // CHECK5-NEXT:    store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
4728 // CHECK5-NEXT:    store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8
4729 // CHECK5-NEXT:    store ptr [[CN]], ptr [[CN_ADDR]], align 8
4730 // CHECK5-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
4731 // CHECK5-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
4732 // CHECK5-NEXT:    [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
4733 // CHECK5-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8
4734 // CHECK5-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
4735 // CHECK5-NEXT:    [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
4736 // CHECK5-NEXT:    [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8
4737 // CHECK5-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8
4738 // CHECK5-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8
4739 // CHECK5-NEXT:    [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 0
4740 // CHECK5-NEXT:    call void @llvm.assume(i1 true) [ "align"(ptr [[ARRAYDECAY]], i64 16) ]
4741 // CHECK5-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
4742 // CHECK5-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4
4743 // CHECK5-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
4744 // CHECK5-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
4745 // CHECK5-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
4746 // CHECK5-NEXT:    [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
4747 // CHECK5-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP9]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
4748 // CHECK5-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4749 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 9
4750 // CHECK5-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
4751 // CHECK5:       cond.true:
4752 // CHECK5-NEXT:    br label [[COND_END:%.*]]
4753 // CHECK5:       cond.false:
4754 // CHECK5-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
4755 // CHECK5-NEXT:    br label [[COND_END]]
4756 // CHECK5:       cond.end:
4757 // CHECK5-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
4758 // CHECK5-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
4759 // CHECK5-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
4760 // CHECK5-NEXT:    store i32 [[TMP12]], ptr [[DOTOMP_IV]], align 4
4761 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
4762 // CHECK5:       omp.inner.for.cond:
4763 // CHECK5-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36:![0-9]+]]
4764 // CHECK5-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP36]]
4765 // CHECK5-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
4766 // CHECK5-NEXT:    br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
4767 // CHECK5:       omp.inner.for.body:
4768 // CHECK5-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]]
4769 // CHECK5-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
4770 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
4771 // CHECK5-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP36]]
4772 // CHECK5-NEXT:    [[TMP16:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP36]]
4773 // CHECK5-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1
4774 // CHECK5-NEXT:    store i32 [[ADD6]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP36]]
4775 // CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 2
4776 // CHECK5-NEXT:    [[TMP17:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP36]]
4777 // CHECK5-NEXT:    [[CONV:%.*]] = fpext float [[TMP17]] to double
4778 // CHECK5-NEXT:    [[ADD7:%.*]] = fadd double [[CONV]], 1.000000e+00
4779 // CHECK5-NEXT:    [[CONV8:%.*]] = fptrunc double [[ADD7]] to float
4780 // CHECK5-NEXT:    store float [[CONV8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP36]]
4781 // CHECK5-NEXT:    [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 3
4782 // CHECK5-NEXT:    [[TMP18:%.*]] = load float, ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP36]]
4783 // CHECK5-NEXT:    [[CONV10:%.*]] = fpext float [[TMP18]] to double
4784 // CHECK5-NEXT:    [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00
4785 // CHECK5-NEXT:    [[CONV12:%.*]] = fptrunc double [[ADD11]] to float
4786 // CHECK5-NEXT:    store float [[CONV12]], ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP36]]
4787 // CHECK5-NEXT:    [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 1
4788 // CHECK5-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX13]], i64 0, i64 2
4789 // CHECK5-NEXT:    [[TMP19:%.*]] = load double, ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP36]]
4790 // CHECK5-NEXT:    [[ADD15:%.*]] = fadd double [[TMP19]], 1.000000e+00
4791 // CHECK5-NEXT:    store double [[ADD15]], ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP36]]
4792 // CHECK5-NEXT:    [[TMP20:%.*]] = mul nsw i64 1, [[TMP5]]
4793 // CHECK5-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i64 [[TMP20]]
4794 // CHECK5-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX16]], i64 3
4795 // CHECK5-NEXT:    [[TMP21:%.*]] = load double, ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP36]]
4796 // CHECK5-NEXT:    [[ADD18:%.*]] = fadd double [[TMP21]], 1.000000e+00
4797 // CHECK5-NEXT:    store double [[ADD18]], ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP36]]
4798 // CHECK5-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0
4799 // CHECK5-NEXT:    [[TMP22:%.*]] = load i64, ptr [[X]], align 8, !llvm.access.group [[ACC_GRP36]]
4800 // CHECK5-NEXT:    [[ADD19:%.*]] = add nsw i64 [[TMP22]], 1
4801 // CHECK5-NEXT:    store i64 [[ADD19]], ptr [[X]], align 8, !llvm.access.group [[ACC_GRP36]]
4802 // CHECK5-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1
4803 // CHECK5-NEXT:    [[TMP23:%.*]] = load i8, ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP36]]
4804 // CHECK5-NEXT:    [[CONV20:%.*]] = sext i8 [[TMP23]] to i32
4805 // CHECK5-NEXT:    [[ADD21:%.*]] = add nsw i32 [[CONV20]], 1
4806 // CHECK5-NEXT:    [[CONV22:%.*]] = trunc i32 [[ADD21]] to i8
4807 // CHECK5-NEXT:    store i8 [[CONV22]], ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP36]]
4808 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
4809 // CHECK5:       omp.body.continue:
4810 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
4811 // CHECK5:       omp.inner.for.inc:
4812 // CHECK5-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]]
4813 // CHECK5-NEXT:    [[ADD23:%.*]] = add nsw i32 [[TMP24]], 1
4814 // CHECK5-NEXT:    store i32 [[ADD23]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]]
4815 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]]
4816 // CHECK5:       omp.inner.for.end:
4817 // CHECK5-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
4818 // CHECK5:       omp.loop.exit:
4819 // CHECK5-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP9]])
4820 // CHECK5-NEXT:    [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
4821 // CHECK5-NEXT:    [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
4822 // CHECK5-NEXT:    br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
4823 // CHECK5:       .omp.final.then:
4824 // CHECK5-NEXT:    store i32 10, ptr [[I]], align 4
4825 // CHECK5-NEXT:    br label [[DOTOMP_FINAL_DONE]]
4826 // CHECK5:       .omp.final.done:
4827 // CHECK5-NEXT:    ret void
4828 //
4829 //
4830 // CHECK5-LABEL: define {{[^@]+}}@_Z3bari
4831 // CHECK5-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
4832 // CHECK5-NEXT:  entry:
4833 // CHECK5-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
4834 // CHECK5-NEXT:    [[A:%.*]] = alloca i32, align 4
4835 // CHECK5-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
4836 // CHECK5-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
4837 // CHECK5-NEXT:    store i32 0, ptr [[A]], align 4
4838 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
4839 // CHECK5-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]])
4840 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A]], align 4
4841 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
4842 // CHECK5-NEXT:    store i32 [[ADD]], ptr [[A]], align 4
4843 // CHECK5-NEXT:    [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
4844 // CHECK5-NEXT:    [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(ptr noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]])
4845 // CHECK5-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A]], align 4
4846 // CHECK5-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
4847 // CHECK5-NEXT:    store i32 [[ADD2]], ptr [[A]], align 4
4848 // CHECK5-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
4849 // CHECK5-NEXT:    [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]])
4850 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, ptr [[A]], align 4
4851 // CHECK5-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
4852 // CHECK5-NEXT:    store i32 [[ADD4]], ptr [[A]], align 4
4853 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4
4854 // CHECK5-NEXT:    [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]])
4855 // CHECK5-NEXT:    [[TMP7:%.*]] = load i32, ptr [[A]], align 4
4856 // CHECK5-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
4857 // CHECK5-NEXT:    store i32 [[ADD6]], ptr [[A]], align 4
4858 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A]], align 4
4859 // CHECK5-NEXT:    ret i32 [[TMP8]]
4860 //
4861 //
4862 // CHECK5-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
4863 // CHECK5-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
4864 // CHECK5-NEXT:  entry:
4865 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
4866 // CHECK5-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
4867 // CHECK5-NEXT:    [[B:%.*]] = alloca i32, align 4
4868 // CHECK5-NEXT:    [[SAVED_STACK:%.*]] = alloca ptr, align 8
4869 // CHECK5-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
4870 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
4871 // CHECK5-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
4872 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
4873 // CHECK5-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [6 x ptr], align 8
4874 // CHECK5-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [6 x ptr], align 8
4875 // CHECK5-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [6 x ptr], align 8
4876 // CHECK5-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [6 x i64], align 8
4877 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4
4878 // CHECK5-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
4879 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
4880 // CHECK5-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
4881 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
4882 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
4883 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
4884 // CHECK5-NEXT:    store i32 [[ADD]], ptr [[B]], align 4
4885 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
4886 // CHECK5-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
4887 // CHECK5-NEXT:    [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()
4888 // CHECK5-NEXT:    store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8
4889 // CHECK5-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
4890 // CHECK5-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
4891 // CHECK5-NEXT:    store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8
4892 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 4
4893 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 60
4894 // CHECK5-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
4895 // CHECK5-NEXT:    store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR_]], align 1
4896 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, ptr [[B]], align 4
4897 // CHECK5-NEXT:    store i32 [[TMP6]], ptr [[B_CASTED]], align 4
4898 // CHECK5-NEXT:    [[TMP7:%.*]] = load i64, ptr [[B_CASTED]], align 8
4899 // CHECK5-NEXT:    [[TMP8:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
4900 // CHECK5-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP8]] to i1
4901 // CHECK5-NEXT:    [[FROMBOOL2:%.*]] = zext i1 [[TOBOOL]] to i8
4902 // CHECK5-NEXT:    store i8 [[FROMBOOL2]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1
4903 // CHECK5-NEXT:    [[TMP9:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8
4904 // CHECK5-NEXT:    [[TMP10:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
4905 // CHECK5-NEXT:    [[TOBOOL3:%.*]] = trunc i8 [[TMP10]] to i1
4906 // CHECK5-NEXT:    br i1 [[TOBOOL3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
4907 // CHECK5:       omp_if.then:
4908 // CHECK5-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0
4909 // CHECK5-NEXT:    [[TMP11:%.*]] = mul nuw i64 2, [[TMP2]]
4910 // CHECK5-NEXT:    [[TMP12:%.*]] = mul nuw i64 [[TMP11]], 2
4911 // CHECK5-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes.7, i64 48, i1 false)
4912 // CHECK5-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
4913 // CHECK5-NEXT:    store ptr [[THIS1]], ptr [[TMP13]], align 8
4914 // CHECK5-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
4915 // CHECK5-NEXT:    store ptr [[A]], ptr [[TMP14]], align 8
4916 // CHECK5-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
4917 // CHECK5-NEXT:    store ptr null, ptr [[TMP15]], align 8
4918 // CHECK5-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
4919 // CHECK5-NEXT:    store i64 [[TMP7]], ptr [[TMP16]], align 8
4920 // CHECK5-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
4921 // CHECK5-NEXT:    store i64 [[TMP7]], ptr [[TMP17]], align 8
4922 // CHECK5-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
4923 // CHECK5-NEXT:    store ptr null, ptr [[TMP18]], align 8
4924 // CHECK5-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
4925 // CHECK5-NEXT:    store i64 2, ptr [[TMP19]], align 8
4926 // CHECK5-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
4927 // CHECK5-NEXT:    store i64 2, ptr [[TMP20]], align 8
4928 // CHECK5-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
4929 // CHECK5-NEXT:    store ptr null, ptr [[TMP21]], align 8
4930 // CHECK5-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
4931 // CHECK5-NEXT:    store i64 [[TMP2]], ptr [[TMP22]], align 8
4932 // CHECK5-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
4933 // CHECK5-NEXT:    store i64 [[TMP2]], ptr [[TMP23]], align 8
4934 // CHECK5-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
4935 // CHECK5-NEXT:    store ptr null, ptr [[TMP24]], align 8
4936 // CHECK5-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
4937 // CHECK5-NEXT:    store ptr [[VLA]], ptr [[TMP25]], align 8
4938 // CHECK5-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4
4939 // CHECK5-NEXT:    store ptr [[VLA]], ptr [[TMP26]], align 8
4940 // CHECK5-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [6 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 4
4941 // CHECK5-NEXT:    store i64 [[TMP12]], ptr [[TMP27]], align 8
4942 // CHECK5-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
4943 // CHECK5-NEXT:    store ptr null, ptr [[TMP28]], align 8
4944 // CHECK5-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5
4945 // CHECK5-NEXT:    store i64 [[TMP9]], ptr [[TMP29]], align 8
4946 // CHECK5-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 5
4947 // CHECK5-NEXT:    store i64 [[TMP9]], ptr [[TMP30]], align 8
4948 // CHECK5-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 5
4949 // CHECK5-NEXT:    store ptr null, ptr [[TMP31]], align 8
4950 // CHECK5-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
4951 // CHECK5-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
4952 // CHECK5-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [6 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0
4953 // CHECK5-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
4954 // CHECK5-NEXT:    store i32 2, ptr [[TMP35]], align 4
4955 // CHECK5-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
4956 // CHECK5-NEXT:    store i32 6, ptr [[TMP36]], align 4
4957 // CHECK5-NEXT:    [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
4958 // CHECK5-NEXT:    store ptr [[TMP32]], ptr [[TMP37]], align 8
4959 // CHECK5-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
4960 // CHECK5-NEXT:    store ptr [[TMP33]], ptr [[TMP38]], align 8
4961 // CHECK5-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
4962 // CHECK5-NEXT:    store ptr [[TMP34]], ptr [[TMP39]], align 8
4963 // CHECK5-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
4964 // CHECK5-NEXT:    store ptr @.offload_maptypes.8, ptr [[TMP40]], align 8
4965 // CHECK5-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
4966 // CHECK5-NEXT:    store ptr null, ptr [[TMP41]], align 8
4967 // CHECK5-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
4968 // CHECK5-NEXT:    store ptr null, ptr [[TMP42]], align 8
4969 // CHECK5-NEXT:    [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
4970 // CHECK5-NEXT:    store i64 10, ptr [[TMP43]], align 8
4971 // CHECK5-NEXT:    [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
4972 // CHECK5-NEXT:    store i64 0, ptr [[TMP44]], align 8
4973 // CHECK5-NEXT:    [[TMP45:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
4974 // CHECK5-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP45]], align 4
4975 // CHECK5-NEXT:    [[TMP46:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
4976 // CHECK5-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP46]], align 4
4977 // CHECK5-NEXT:    [[TMP47:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
4978 // CHECK5-NEXT:    store i32 0, ptr [[TMP47]], align 4
4979 // CHECK5-NEXT:    [[TMP48:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.region_id, ptr [[KERNEL_ARGS]])
4980 // CHECK5-NEXT:    [[TMP49:%.*]] = icmp ne i32 [[TMP48]], 0
4981 // CHECK5-NEXT:    br i1 [[TMP49]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
4982 // CHECK5:       omp_offload.failed:
4983 // CHECK5-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215(ptr [[THIS1]], i64 [[TMP7]], i64 2, i64 [[TMP2]], ptr [[VLA]], i64 [[TMP9]]) #[[ATTR3]]
4984 // CHECK5-NEXT:    br label [[OMP_OFFLOAD_CONT]]
4985 // CHECK5:       omp_offload.cont:
4986 // CHECK5-NEXT:    br label [[OMP_IF_END:%.*]]
4987 // CHECK5:       omp_if.else:
4988 // CHECK5-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215(ptr [[THIS1]], i64 [[TMP7]], i64 2, i64 [[TMP2]], ptr [[VLA]], i64 [[TMP9]]) #[[ATTR3]]
4989 // CHECK5-NEXT:    br label [[OMP_IF_END]]
4990 // CHECK5:       omp_if.end:
4991 // CHECK5-NEXT:    [[TMP50:%.*]] = mul nsw i64 1, [[TMP2]]
4992 // CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP50]]
4993 // CHECK5-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1
4994 // CHECK5-NEXT:    [[TMP51:%.*]] = load i16, ptr [[ARRAYIDX4]], align 2
4995 // CHECK5-NEXT:    [[CONV:%.*]] = sext i16 [[TMP51]] to i32
4996 // CHECK5-NEXT:    [[TMP52:%.*]] = load i32, ptr [[B]], align 4
4997 // CHECK5-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV]], [[TMP52]]
4998 // CHECK5-NEXT:    [[TMP53:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
4999 // CHECK5-NEXT:    call void @llvm.stackrestore.p0(ptr [[TMP53]])
5000 // CHECK5-NEXT:    ret i32 [[ADD5]]
5001 //
5002 //
5003 // CHECK5-LABEL: define {{[^@]+}}@_ZL7fstatici
5004 // CHECK5-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
5005 // CHECK5-NEXT:  entry:
5006 // CHECK5-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
5007 // CHECK5-NEXT:    [[A:%.*]] = alloca i32, align 4
5008 // CHECK5-NEXT:    [[AA:%.*]] = alloca i16, align 2
5009 // CHECK5-NEXT:    [[AAA:%.*]] = alloca i8, align 1
5010 // CHECK5-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
5011 // CHECK5-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
5012 // CHECK5-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8
5013 // CHECK5-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
5014 // CHECK5-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
5015 // CHECK5-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 8
5016 // CHECK5-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 8
5017 // CHECK5-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 8
5018 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4
5019 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
5020 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
5021 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
5022 // CHECK5-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
5023 // CHECK5-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
5024 // CHECK5-NEXT:    store i32 0, ptr [[A]], align 4
5025 // CHECK5-NEXT:    store i16 0, ptr [[AA]], align 2
5026 // CHECK5-NEXT:    store i8 0, ptr [[AAA]], align 1
5027 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A]], align 4
5028 // CHECK5-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 4
5029 // CHECK5-NEXT:    [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8
5030 // CHECK5-NEXT:    [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
5031 // CHECK5-NEXT:    store i32 [[TMP2]], ptr [[N_CASTED]], align 4
5032 // CHECK5-NEXT:    [[TMP3:%.*]] = load i64, ptr [[N_CASTED]], align 8
5033 // CHECK5-NEXT:    [[TMP4:%.*]] = load i16, ptr [[AA]], align 2
5034 // CHECK5-NEXT:    store i16 [[TMP4]], ptr [[AA_CASTED]], align 2
5035 // CHECK5-NEXT:    [[TMP5:%.*]] = load i64, ptr [[AA_CASTED]], align 8
5036 // CHECK5-NEXT:    [[TMP6:%.*]] = load i8, ptr [[AAA]], align 1
5037 // CHECK5-NEXT:    store i8 [[TMP6]], ptr [[AAA_CASTED]], align 1
5038 // CHECK5-NEXT:    [[TMP7:%.*]] = load i64, ptr [[AAA_CASTED]], align 8
5039 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, ptr [[N_ADDR]], align 4
5040 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 50
5041 // CHECK5-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
5042 // CHECK5:       omp_if.then:
5043 // CHECK5-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
5044 // CHECK5-NEXT:    store i64 [[TMP1]], ptr [[TMP9]], align 8
5045 // CHECK5-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
5046 // CHECK5-NEXT:    store i64 [[TMP1]], ptr [[TMP10]], align 8
5047 // CHECK5-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
5048 // CHECK5-NEXT:    store ptr null, ptr [[TMP11]], align 8
5049 // CHECK5-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
5050 // CHECK5-NEXT:    store i64 [[TMP3]], ptr [[TMP12]], align 8
5051 // CHECK5-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
5052 // CHECK5-NEXT:    store i64 [[TMP3]], ptr [[TMP13]], align 8
5053 // CHECK5-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
5054 // CHECK5-NEXT:    store ptr null, ptr [[TMP14]], align 8
5055 // CHECK5-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
5056 // CHECK5-NEXT:    store i64 [[TMP5]], ptr [[TMP15]], align 8
5057 // CHECK5-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
5058 // CHECK5-NEXT:    store i64 [[TMP5]], ptr [[TMP16]], align 8
5059 // CHECK5-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
5060 // CHECK5-NEXT:    store ptr null, ptr [[TMP17]], align 8
5061 // CHECK5-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
5062 // CHECK5-NEXT:    store i64 [[TMP7]], ptr [[TMP18]], align 8
5063 // CHECK5-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
5064 // CHECK5-NEXT:    store i64 [[TMP7]], ptr [[TMP19]], align 8
5065 // CHECK5-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
5066 // CHECK5-NEXT:    store ptr null, ptr [[TMP20]], align 8
5067 // CHECK5-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
5068 // CHECK5-NEXT:    store ptr [[B]], ptr [[TMP21]], align 8
5069 // CHECK5-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4
5070 // CHECK5-NEXT:    store ptr [[B]], ptr [[TMP22]], align 8
5071 // CHECK5-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
5072 // CHECK5-NEXT:    store ptr null, ptr [[TMP23]], align 8
5073 // CHECK5-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
5074 // CHECK5-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
5075 // CHECK5-NEXT:    [[TMP26:%.*]] = load i32, ptr [[A]], align 4
5076 // CHECK5-NEXT:    store i32 [[TMP26]], ptr [[DOTCAPTURE_EXPR_]], align 4
5077 // CHECK5-NEXT:    [[TMP27:%.*]] = load i32, ptr [[N_ADDR]], align 4
5078 // CHECK5-NEXT:    store i32 [[TMP27]], ptr [[DOTCAPTURE_EXPR_1]], align 4
5079 // CHECK5-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
5080 // CHECK5-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
5081 // CHECK5-NEXT:    [[SUB:%.*]] = sub i32 [[TMP28]], [[TMP29]]
5082 // CHECK5-NEXT:    [[SUB3:%.*]] = sub i32 [[SUB]], 1
5083 // CHECK5-NEXT:    [[ADD:%.*]] = add i32 [[SUB3]], 1
5084 // CHECK5-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
5085 // CHECK5-NEXT:    [[SUB4:%.*]] = sub i32 [[DIV]], 1
5086 // CHECK5-NEXT:    store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 4
5087 // CHECK5-NEXT:    [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
5088 // CHECK5-NEXT:    [[ADD5:%.*]] = add i32 [[TMP30]], 1
5089 // CHECK5-NEXT:    [[TMP31:%.*]] = zext i32 [[ADD5]] to i64
5090 // CHECK5-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
5091 // CHECK5-NEXT:    store i32 2, ptr [[TMP32]], align 4
5092 // CHECK5-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
5093 // CHECK5-NEXT:    store i32 5, ptr [[TMP33]], align 4
5094 // CHECK5-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
5095 // CHECK5-NEXT:    store ptr [[TMP24]], ptr [[TMP34]], align 8
5096 // CHECK5-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
5097 // CHECK5-NEXT:    store ptr [[TMP25]], ptr [[TMP35]], align 8
5098 // CHECK5-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
5099 // CHECK5-NEXT:    store ptr @.offload_sizes.9, ptr [[TMP36]], align 8
5100 // CHECK5-NEXT:    [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
5101 // CHECK5-NEXT:    store ptr @.offload_maptypes.10, ptr [[TMP37]], align 8
5102 // CHECK5-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
5103 // CHECK5-NEXT:    store ptr null, ptr [[TMP38]], align 8
5104 // CHECK5-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
5105 // CHECK5-NEXT:    store ptr null, ptr [[TMP39]], align 8
5106 // CHECK5-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
5107 // CHECK5-NEXT:    store i64 [[TMP31]], ptr [[TMP40]], align 8
5108 // CHECK5-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
5109 // CHECK5-NEXT:    store i64 0, ptr [[TMP41]], align 8
5110 // CHECK5-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
5111 // CHECK5-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP42]], align 4
5112 // CHECK5-NEXT:    [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
5113 // CHECK5-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP43]], align 4
5114 // CHECK5-NEXT:    [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
5115 // CHECK5-NEXT:    store i32 0, ptr [[TMP44]], align 4
5116 // CHECK5-NEXT:    [[TMP45:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.region_id, ptr [[KERNEL_ARGS]])
5117 // CHECK5-NEXT:    [[TMP46:%.*]] = icmp ne i32 [[TMP45]], 0
5118 // CHECK5-NEXT:    br i1 [[TMP46]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
5119 // CHECK5:       omp_offload.failed:
5120 // CHECK5-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], i64 [[TMP7]], ptr [[B]]) #[[ATTR3]]
5121 // CHECK5-NEXT:    br label [[OMP_OFFLOAD_CONT]]
5122 // CHECK5:       omp_offload.cont:
5123 // CHECK5-NEXT:    br label [[OMP_IF_END:%.*]]
5124 // CHECK5:       omp_if.else:
5125 // CHECK5-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], i64 [[TMP7]], ptr [[B]]) #[[ATTR3]]
5126 // CHECK5-NEXT:    br label [[OMP_IF_END]]
5127 // CHECK5:       omp_if.end:
5128 // CHECK5-NEXT:    [[TMP47:%.*]] = load i32, ptr [[A]], align 4
5129 // CHECK5-NEXT:    ret i32 [[TMP47]]
5130 //
5131 //
5132 // CHECK5-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
5133 // CHECK5-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
5134 // CHECK5-NEXT:  entry:
5135 // CHECK5-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
5136 // CHECK5-NEXT:    [[A:%.*]] = alloca i32, align 4
5137 // CHECK5-NEXT:    [[AA:%.*]] = alloca i16, align 2
5138 // CHECK5-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
5139 // CHECK5-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
5140 // CHECK5-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
5141 // CHECK5-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8
5142 // CHECK5-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 8
5143 // CHECK5-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 8
5144 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4
5145 // CHECK5-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
5146 // CHECK5-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
5147 // CHECK5-NEXT:    store i32 0, ptr [[A]], align 4
5148 // CHECK5-NEXT:    store i16 0, ptr [[AA]], align 2
5149 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A]], align 4
5150 // CHECK5-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 4
5151 // CHECK5-NEXT:    [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8
5152 // CHECK5-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA]], align 2
5153 // CHECK5-NEXT:    store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
5154 // CHECK5-NEXT:    [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8
5155 // CHECK5-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
5156 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
5157 // CHECK5-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
5158 // CHECK5:       omp_if.then:
5159 // CHECK5-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
5160 // CHECK5-NEXT:    store i64 [[TMP1]], ptr [[TMP5]], align 8
5161 // CHECK5-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
5162 // CHECK5-NEXT:    store i64 [[TMP1]], ptr [[TMP6]], align 8
5163 // CHECK5-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
5164 // CHECK5-NEXT:    store ptr null, ptr [[TMP7]], align 8
5165 // CHECK5-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
5166 // CHECK5-NEXT:    store i64 [[TMP3]], ptr [[TMP8]], align 8
5167 // CHECK5-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
5168 // CHECK5-NEXT:    store i64 [[TMP3]], ptr [[TMP9]], align 8
5169 // CHECK5-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
5170 // CHECK5-NEXT:    store ptr null, ptr [[TMP10]], align 8
5171 // CHECK5-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
5172 // CHECK5-NEXT:    store ptr [[B]], ptr [[TMP11]], align 8
5173 // CHECK5-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
5174 // CHECK5-NEXT:    store ptr [[B]], ptr [[TMP12]], align 8
5175 // CHECK5-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
5176 // CHECK5-NEXT:    store ptr null, ptr [[TMP13]], align 8
5177 // CHECK5-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
5178 // CHECK5-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
5179 // CHECK5-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
5180 // CHECK5-NEXT:    store i32 2, ptr [[TMP16]], align 4
5181 // CHECK5-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
5182 // CHECK5-NEXT:    store i32 3, ptr [[TMP17]], align 4
5183 // CHECK5-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
5184 // CHECK5-NEXT:    store ptr [[TMP14]], ptr [[TMP18]], align 8
5185 // CHECK5-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
5186 // CHECK5-NEXT:    store ptr [[TMP15]], ptr [[TMP19]], align 8
5187 // CHECK5-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
5188 // CHECK5-NEXT:    store ptr @.offload_sizes.11, ptr [[TMP20]], align 8
5189 // CHECK5-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
5190 // CHECK5-NEXT:    store ptr @.offload_maptypes.12, ptr [[TMP21]], align 8
5191 // CHECK5-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
5192 // CHECK5-NEXT:    store ptr null, ptr [[TMP22]], align 8
5193 // CHECK5-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
5194 // CHECK5-NEXT:    store ptr null, ptr [[TMP23]], align 8
5195 // CHECK5-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
5196 // CHECK5-NEXT:    store i64 10, ptr [[TMP24]], align 8
5197 // CHECK5-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
5198 // CHECK5-NEXT:    store i64 0, ptr [[TMP25]], align 8
5199 // CHECK5-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
5200 // CHECK5-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP26]], align 4
5201 // CHECK5-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
5202 // CHECK5-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP27]], align 4
5203 // CHECK5-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
5204 // CHECK5-NEXT:    store i32 0, ptr [[TMP28]], align 4
5205 // CHECK5-NEXT:    [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.region_id, ptr [[KERNEL_ARGS]])
5206 // CHECK5-NEXT:    [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
5207 // CHECK5-NEXT:    br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
5208 // CHECK5:       omp_offload.failed:
5209 // CHECK5-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR3]]
5210 // CHECK5-NEXT:    br label [[OMP_OFFLOAD_CONT]]
5211 // CHECK5:       omp_offload.cont:
5212 // CHECK5-NEXT:    br label [[OMP_IF_END:%.*]]
5213 // CHECK5:       omp_if.else:
5214 // CHECK5-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR3]]
5215 // CHECK5-NEXT:    br label [[OMP_IF_END]]
5216 // CHECK5:       omp_if.end:
5217 // CHECK5-NEXT:    [[TMP31:%.*]] = load i32, ptr [[A]], align 4
5218 // CHECK5-NEXT:    ret i32 [[TMP31]]
5219 //
5220 //
5221 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215
5222 // CHECK5-SAME: (ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
5223 // CHECK5-NEXT:  entry:
5224 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
5225 // CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
5226 // CHECK5-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
5227 // CHECK5-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
5228 // CHECK5-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
5229 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
5230 // CHECK5-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
5231 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
5232 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
5233 // CHECK5-NEXT:    store i64 [[B]], ptr [[B_ADDR]], align 8
5234 // CHECK5-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
5235 // CHECK5-NEXT:    store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
5236 // CHECK5-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
5237 // CHECK5-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
5238 // CHECK5-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
5239 // CHECK5-NEXT:    [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
5240 // CHECK5-NEXT:    [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
5241 // CHECK5-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
5242 // CHECK5-NEXT:    [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4
5243 // CHECK5-NEXT:    store i32 [[TMP4]], ptr [[B_CASTED]], align 4
5244 // CHECK5-NEXT:    [[TMP5:%.*]] = load i64, ptr [[B_CASTED]], align 8
5245 // CHECK5-NEXT:    [[TMP6:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1
5246 // CHECK5-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1
5247 // CHECK5-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
5248 // CHECK5-NEXT:    store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1
5249 // CHECK5-NEXT:    [[TMP7:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8
5250 // CHECK5-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.omp_outlined, ptr [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], ptr [[TMP3]], i64 [[TMP7]])
5251 // CHECK5-NEXT:    ret void
5252 //
5253 //
5254 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.omp_outlined
5255 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
5256 // CHECK5-NEXT:  entry:
5257 // CHECK5-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
5258 // CHECK5-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
5259 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
5260 // CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
5261 // CHECK5-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
5262 // CHECK5-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
5263 // CHECK5-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
5264 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
5265 // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
5266 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4
5267 // CHECK5-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
5268 // CHECK5-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
5269 // CHECK5-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
5270 // CHECK5-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
5271 // CHECK5-NEXT:    [[I:%.*]] = alloca i32, align 4
5272 // CHECK5-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
5273 // CHECK5-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
5274 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
5275 // CHECK5-NEXT:    store i64 [[B]], ptr [[B_ADDR]], align 8
5276 // CHECK5-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
5277 // CHECK5-NEXT:    store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
5278 // CHECK5-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
5279 // CHECK5-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
5280 // CHECK5-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
5281 // CHECK5-NEXT:    [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
5282 // CHECK5-NEXT:    [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
5283 // CHECK5-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
5284 // CHECK5-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
5285 // CHECK5-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4
5286 // CHECK5-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
5287 // CHECK5-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
5288 // CHECK5-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
5289 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
5290 // CHECK5-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
5291 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
5292 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9
5293 // CHECK5-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
5294 // CHECK5:       cond.true:
5295 // CHECK5-NEXT:    br label [[COND_END:%.*]]
5296 // CHECK5:       cond.false:
5297 // CHECK5-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
5298 // CHECK5-NEXT:    br label [[COND_END]]
5299 // CHECK5:       cond.end:
5300 // CHECK5-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
5301 // CHECK5-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
5302 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
5303 // CHECK5-NEXT:    store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4
5304 // CHECK5-NEXT:    [[TMP9:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1
5305 // CHECK5-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP9]] to i1
5306 // CHECK5-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
5307 // CHECK5:       omp_if.then:
5308 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
5309 // CHECK5:       omp.inner.for.cond:
5310 // CHECK5-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39:![0-9]+]]
5311 // CHECK5-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP39]]
5312 // CHECK5-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
5313 // CHECK5-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5314 // CHECK5:       omp.inner.for.body:
5315 // CHECK5-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]]
5316 // CHECK5-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
5317 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
5318 // CHECK5-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP39]]
5319 // CHECK5-NEXT:    [[TMP13:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP39]]
5320 // CHECK5-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP13]] to double
5321 // CHECK5-NEXT:    [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00
5322 // CHECK5-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0
5323 // CHECK5-NEXT:    store double [[ADD4]], ptr [[A]], align 8, !llvm.access.group [[ACC_GRP39]]
5324 // CHECK5-NEXT:    [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0
5325 // CHECK5-NEXT:    [[TMP14:%.*]] = load double, ptr [[A5]], align 8, !llvm.access.group [[ACC_GRP39]]
5326 // CHECK5-NEXT:    [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00
5327 // CHECK5-NEXT:    store double [[INC]], ptr [[A5]], align 8, !llvm.access.group [[ACC_GRP39]]
5328 // CHECK5-NEXT:    [[CONV6:%.*]] = fptosi double [[INC]] to i16
5329 // CHECK5-NEXT:    [[TMP15:%.*]] = mul nsw i64 1, [[TMP2]]
5330 // CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i64 [[TMP15]]
5331 // CHECK5-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1
5332 // CHECK5-NEXT:    store i16 [[CONV6]], ptr [[ARRAYIDX7]], align 2, !llvm.access.group [[ACC_GRP39]]
5333 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
5334 // CHECK5:       omp.body.continue:
5335 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
5336 // CHECK5:       omp.inner.for.inc:
5337 // CHECK5-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]]
5338 // CHECK5-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP16]], 1
5339 // CHECK5-NEXT:    store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP39]]
5340 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]]
5341 // CHECK5:       omp.inner.for.end:
5342 // CHECK5-NEXT:    br label [[OMP_IF_END:%.*]]
5343 // CHECK5:       omp_if.else:
5344 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND9:%.*]]
5345 // CHECK5:       omp.inner.for.cond9:
5346 // CHECK5-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
5347 // CHECK5-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
5348 // CHECK5-NEXT:    [[CMP10:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]
5349 // CHECK5-NEXT:    br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END25:%.*]]
5350 // CHECK5:       omp.inner.for.body11:
5351 // CHECK5-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
5352 // CHECK5-NEXT:    [[MUL12:%.*]] = mul nsw i32 [[TMP19]], 1
5353 // CHECK5-NEXT:    [[ADD13:%.*]] = add nsw i32 0, [[MUL12]]
5354 // CHECK5-NEXT:    store i32 [[ADD13]], ptr [[I]], align 4
5355 // CHECK5-NEXT:    [[TMP20:%.*]] = load i32, ptr [[B_ADDR]], align 4
5356 // CHECK5-NEXT:    [[CONV14:%.*]] = sitofp i32 [[TMP20]] to double
5357 // CHECK5-NEXT:    [[ADD15:%.*]] = fadd double [[CONV14]], 1.500000e+00
5358 // CHECK5-NEXT:    [[A16:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0
5359 // CHECK5-NEXT:    store double [[ADD15]], ptr [[A16]], align 8
5360 // CHECK5-NEXT:    [[A17:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0
5361 // CHECK5-NEXT:    [[TMP21:%.*]] = load double, ptr [[A17]], align 8
5362 // CHECK5-NEXT:    [[INC18:%.*]] = fadd double [[TMP21]], 1.000000e+00
5363 // CHECK5-NEXT:    store double [[INC18]], ptr [[A17]], align 8
5364 // CHECK5-NEXT:    [[CONV19:%.*]] = fptosi double [[INC18]] to i16
5365 // CHECK5-NEXT:    [[TMP22:%.*]] = mul nsw i64 1, [[TMP2]]
5366 // CHECK5-NEXT:    [[ARRAYIDX20:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i64 [[TMP22]]
5367 // CHECK5-NEXT:    [[ARRAYIDX21:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX20]], i64 1
5368 // CHECK5-NEXT:    store i16 [[CONV19]], ptr [[ARRAYIDX21]], align 2
5369 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE22:%.*]]
5370 // CHECK5:       omp.body.continue22:
5371 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC23:%.*]]
5372 // CHECK5:       omp.inner.for.inc23:
5373 // CHECK5-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
5374 // CHECK5-NEXT:    [[ADD24:%.*]] = add nsw i32 [[TMP23]], 1
5375 // CHECK5-NEXT:    store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4
5376 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP42:![0-9]+]]
5377 // CHECK5:       omp.inner.for.end25:
5378 // CHECK5-NEXT:    br label [[OMP_IF_END]]
5379 // CHECK5:       omp_if.end:
5380 // CHECK5-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
5381 // CHECK5:       omp.loop.exit:
5382 // CHECK5-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])
5383 // CHECK5-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
5384 // CHECK5-NEXT:    [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
5385 // CHECK5-NEXT:    br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
5386 // CHECK5:       .omp.final.then:
5387 // CHECK5-NEXT:    store i32 10, ptr [[I]], align 4
5388 // CHECK5-NEXT:    br label [[DOTOMP_FINAL_DONE]]
5389 // CHECK5:       .omp.final.done:
5390 // CHECK5-NEXT:    ret void
5391 //
5392 //
5393 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197
5394 // CHECK5-SAME: (i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
5395 // CHECK5-NEXT:  entry:
5396 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
5397 // CHECK5-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
5398 // CHECK5-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
5399 // CHECK5-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
5400 // CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
5401 // CHECK5-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
5402 // CHECK5-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8
5403 // CHECK5-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
5404 // CHECK5-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
5405 // CHECK5-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
5406 // CHECK5-NEXT:    store i64 [[N]], ptr [[N_ADDR]], align 8
5407 // CHECK5-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
5408 // CHECK5-NEXT:    store i64 [[AAA]], ptr [[AAA_ADDR]], align 8
5409 // CHECK5-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
5410 // CHECK5-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
5411 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
5412 // CHECK5-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 4
5413 // CHECK5-NEXT:    [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8
5414 // CHECK5-NEXT:    [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4
5415 // CHECK5-NEXT:    store i32 [[TMP3]], ptr [[N_CASTED]], align 4
5416 // CHECK5-NEXT:    [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8
5417 // CHECK5-NEXT:    [[TMP5:%.*]] = load i16, ptr [[AA_ADDR]], align 2
5418 // CHECK5-NEXT:    store i16 [[TMP5]], ptr [[AA_CASTED]], align 2
5419 // CHECK5-NEXT:    [[TMP6:%.*]] = load i64, ptr [[AA_CASTED]], align 8
5420 // CHECK5-NEXT:    [[TMP7:%.*]] = load i8, ptr [[AAA_ADDR]], align 1
5421 // CHECK5-NEXT:    store i8 [[TMP7]], ptr [[AAA_CASTED]], align 1
5422 // CHECK5-NEXT:    [[TMP8:%.*]] = load i64, ptr [[AAA_CASTED]], align 8
5423 // CHECK5-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], ptr [[TMP0]])
5424 // CHECK5-NEXT:    ret void
5425 //
5426 //
5427 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.omp_outlined
5428 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
5429 // CHECK5-NEXT:  entry:
5430 // CHECK5-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
5431 // CHECK5-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
5432 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
5433 // CHECK5-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
5434 // CHECK5-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
5435 // CHECK5-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
5436 // CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
5437 // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
5438 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4
5439 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
5440 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
5441 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
5442 // CHECK5-NEXT:    [[I:%.*]] = alloca i32, align 4
5443 // CHECK5-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
5444 // CHECK5-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
5445 // CHECK5-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
5446 // CHECK5-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
5447 // CHECK5-NEXT:    [[I5:%.*]] = alloca i32, align 4
5448 // CHECK5-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
5449 // CHECK5-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
5450 // CHECK5-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
5451 // CHECK5-NEXT:    store i64 [[N]], ptr [[N_ADDR]], align 8
5452 // CHECK5-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
5453 // CHECK5-NEXT:    store i64 [[AAA]], ptr [[AAA_ADDR]], align 8
5454 // CHECK5-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
5455 // CHECK5-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
5456 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
5457 // CHECK5-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
5458 // CHECK5-NEXT:    [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
5459 // CHECK5-NEXT:    store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
5460 // CHECK5-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
5461 // CHECK5-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
5462 // CHECK5-NEXT:    [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
5463 // CHECK5-NEXT:    [[SUB3:%.*]] = sub i32 [[SUB]], 1
5464 // CHECK5-NEXT:    [[ADD:%.*]] = add i32 [[SUB3]], 1
5465 // CHECK5-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
5466 // CHECK5-NEXT:    [[SUB4:%.*]] = sub i32 [[DIV]], 1
5467 // CHECK5-NEXT:    store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 4
5468 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
5469 // CHECK5-NEXT:    store i32 [[TMP5]], ptr [[I]], align 4
5470 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
5471 // CHECK5-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
5472 // CHECK5-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
5473 // CHECK5-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
5474 // CHECK5:       omp.precond.then:
5475 // CHECK5-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
5476 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
5477 // CHECK5-NEXT:    store i32 [[TMP8]], ptr [[DOTOMP_UB]], align 4
5478 // CHECK5-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
5479 // CHECK5-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
5480 // CHECK5-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
5481 // CHECK5-NEXT:    [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4
5482 // CHECK5-NEXT:    call void @__kmpc_for_static_init_4u(ptr @[[GLOB1]], i32 [[TMP10]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
5483 // CHECK5-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
5484 // CHECK5-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
5485 // CHECK5-NEXT:    [[CMP6:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]]
5486 // CHECK5-NEXT:    br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
5487 // CHECK5:       cond.true:
5488 // CHECK5-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
5489 // CHECK5-NEXT:    br label [[COND_END:%.*]]
5490 // CHECK5:       cond.false:
5491 // CHECK5-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
5492 // CHECK5-NEXT:    br label [[COND_END]]
5493 // CHECK5:       cond.end:
5494 // CHECK5-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ]
5495 // CHECK5-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
5496 // CHECK5-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
5497 // CHECK5-NEXT:    store i32 [[TMP15]], ptr [[DOTOMP_IV]], align 4
5498 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
5499 // CHECK5:       omp.inner.for.cond:
5500 // CHECK5-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP44:![0-9]+]]
5501 // CHECK5-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP44]]
5502 // CHECK5-NEXT:    [[ADD7:%.*]] = add i32 [[TMP17]], 1
5503 // CHECK5-NEXT:    [[CMP8:%.*]] = icmp ult i32 [[TMP16]], [[ADD7]]
5504 // CHECK5-NEXT:    br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5505 // CHECK5:       omp.inner.for.body:
5506 // CHECK5-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group [[ACC_GRP44]]
5507 // CHECK5-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP44]]
5508 // CHECK5-NEXT:    [[MUL:%.*]] = mul i32 [[TMP19]], 1
5509 // CHECK5-NEXT:    [[ADD9:%.*]] = add i32 [[TMP18]], [[MUL]]
5510 // CHECK5-NEXT:    store i32 [[ADD9]], ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP44]]
5511 // CHECK5-NEXT:    [[TMP20:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP44]]
5512 // CHECK5-NEXT:    [[ADD10:%.*]] = add nsw i32 [[TMP20]], 1
5513 // CHECK5-NEXT:    store i32 [[ADD10]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP44]]
5514 // CHECK5-NEXT:    [[TMP21:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP44]]
5515 // CHECK5-NEXT:    [[CONV:%.*]] = sext i16 [[TMP21]] to i32
5516 // CHECK5-NEXT:    [[ADD11:%.*]] = add nsw i32 [[CONV]], 1
5517 // CHECK5-NEXT:    [[CONV12:%.*]] = trunc i32 [[ADD11]] to i16
5518 // CHECK5-NEXT:    store i16 [[CONV12]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP44]]
5519 // CHECK5-NEXT:    [[TMP22:%.*]] = load i8, ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP44]]
5520 // CHECK5-NEXT:    [[CONV13:%.*]] = sext i8 [[TMP22]] to i32
5521 // CHECK5-NEXT:    [[ADD14:%.*]] = add nsw i32 [[CONV13]], 1
5522 // CHECK5-NEXT:    [[CONV15:%.*]] = trunc i32 [[ADD14]] to i8
5523 // CHECK5-NEXT:    store i8 [[CONV15]], ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP44]]
5524 // CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2
5525 // CHECK5-NEXT:    [[TMP23:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP44]]
5526 // CHECK5-NEXT:    [[ADD16:%.*]] = add nsw i32 [[TMP23]], 1
5527 // CHECK5-NEXT:    store i32 [[ADD16]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP44]]
5528 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
5529 // CHECK5:       omp.body.continue:
5530 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
5531 // CHECK5:       omp.inner.for.inc:
5532 // CHECK5-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP44]]
5533 // CHECK5-NEXT:    [[ADD17:%.*]] = add i32 [[TMP24]], 1
5534 // CHECK5-NEXT:    store i32 [[ADD17]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP44]]
5535 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP45:![0-9]+]]
5536 // CHECK5:       omp.inner.for.end:
5537 // CHECK5-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
5538 // CHECK5:       omp.loop.exit:
5539 // CHECK5-NEXT:    [[TMP25:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
5540 // CHECK5-NEXT:    [[TMP26:%.*]] = load i32, ptr [[TMP25]], align 4
5541 // CHECK5-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP26]])
5542 // CHECK5-NEXT:    [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
5543 // CHECK5-NEXT:    [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
5544 // CHECK5-NEXT:    br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
5545 // CHECK5:       .omp.final.then:
5546 // CHECK5-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
5547 // CHECK5-NEXT:    [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
5548 // CHECK5-NEXT:    [[TMP31:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
5549 // CHECK5-NEXT:    [[SUB18:%.*]] = sub i32 [[TMP30]], [[TMP31]]
5550 // CHECK5-NEXT:    [[SUB19:%.*]] = sub i32 [[SUB18]], 1
5551 // CHECK5-NEXT:    [[ADD20:%.*]] = add i32 [[SUB19]], 1
5552 // CHECK5-NEXT:    [[DIV21:%.*]] = udiv i32 [[ADD20]], 1
5553 // CHECK5-NEXT:    [[MUL22:%.*]] = mul i32 [[DIV21]], 1
5554 // CHECK5-NEXT:    [[ADD23:%.*]] = add i32 [[TMP29]], [[MUL22]]
5555 // CHECK5-NEXT:    store i32 [[ADD23]], ptr [[I5]], align 4
5556 // CHECK5-NEXT:    br label [[DOTOMP_FINAL_DONE]]
5557 // CHECK5:       .omp.final.done:
5558 // CHECK5-NEXT:    br label [[OMP_PRECOND_END]]
5559 // CHECK5:       omp.precond.end:
5560 // CHECK5-NEXT:    ret void
5561 //
5562 //
5563 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180
5564 // CHECK5-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
5565 // CHECK5-NEXT:  entry:
5566 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
5567 // CHECK5-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
5568 // CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
5569 // CHECK5-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
5570 // CHECK5-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
5571 // CHECK5-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
5572 // CHECK5-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
5573 // CHECK5-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
5574 // CHECK5-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
5575 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
5576 // CHECK5-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 4
5577 // CHECK5-NEXT:    [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8
5578 // CHECK5-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
5579 // CHECK5-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
5580 // CHECK5-NEXT:    [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8
5581 // CHECK5-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], ptr [[TMP0]])
5582 // CHECK5-NEXT:    ret void
5583 //
5584 //
5585 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.omp_outlined
5586 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
5587 // CHECK5-NEXT:  entry:
5588 // CHECK5-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
5589 // CHECK5-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
5590 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
5591 // CHECK5-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
5592 // CHECK5-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
5593 // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
5594 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4
5595 // CHECK5-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
5596 // CHECK5-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
5597 // CHECK5-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
5598 // CHECK5-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
5599 // CHECK5-NEXT:    [[I:%.*]] = alloca i32, align 4
5600 // CHECK5-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
5601 // CHECK5-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
5602 // CHECK5-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
5603 // CHECK5-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
5604 // CHECK5-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
5605 // CHECK5-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
5606 // CHECK5-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
5607 // CHECK5-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4
5608 // CHECK5-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
5609 // CHECK5-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
5610 // CHECK5-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
5611 // CHECK5-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
5612 // CHECK5-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
5613 // CHECK5-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
5614 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
5615 // CHECK5-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
5616 // CHECK5:       cond.true:
5617 // CHECK5-NEXT:    br label [[COND_END:%.*]]
5618 // CHECK5:       cond.false:
5619 // CHECK5-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
5620 // CHECK5-NEXT:    br label [[COND_END]]
5621 // CHECK5:       cond.end:
5622 // CHECK5-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
5623 // CHECK5-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
5624 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
5625 // CHECK5-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
5626 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
5627 // CHECK5:       omp.inner.for.cond:
5628 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP47:![0-9]+]]
5629 // CHECK5-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP47]]
5630 // CHECK5-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
5631 // CHECK5-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
5632 // CHECK5:       omp.inner.for.body:
5633 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP47]]
5634 // CHECK5-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
5635 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
5636 // CHECK5-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP47]]
5637 // CHECK5-NEXT:    [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP47]]
5638 // CHECK5-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
5639 // CHECK5-NEXT:    store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP47]]
5640 // CHECK5-NEXT:    [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP47]]
5641 // CHECK5-NEXT:    [[CONV:%.*]] = sext i16 [[TMP10]] to i32
5642 // CHECK5-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV]], 1
5643 // CHECK5-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
5644 // CHECK5-NEXT:    store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP47]]
5645 // CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2
5646 // CHECK5-NEXT:    [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP47]]
5647 // CHECK5-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1
5648 // CHECK5-NEXT:    store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP47]]
5649 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
5650 // CHECK5:       omp.body.continue:
5651 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
5652 // CHECK5:       omp.inner.for.inc:
5653 // CHECK5-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP47]]
5654 // CHECK5-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP12]], 1
5655 // CHECK5-NEXT:    store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP47]]
5656 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP48:![0-9]+]]
5657 // CHECK5:       omp.inner.for.end:
5658 // CHECK5-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
5659 // CHECK5:       omp.loop.exit:
5660 // CHECK5-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])
5661 // CHECK5-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
5662 // CHECK5-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
5663 // CHECK5-NEXT:    br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
5664 // CHECK5:       .omp.final.then:
5665 // CHECK5-NEXT:    store i32 10, ptr [[I]], align 4
5666 // CHECK5-NEXT:    br label [[DOTOMP_FINAL_DONE]]
5667 // CHECK5:       .omp.final.done:
5668 // CHECK5-NEXT:    ret void
5669 //
5670 //
5671 // CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
5672 // CHECK5-SAME: () #[[ATTR4]] {
5673 // CHECK5-NEXT:  entry:
5674 // CHECK5-NEXT:    call void @__tgt_register_requires(i64 1)
5675 // CHECK5-NEXT:    ret void
5676 //
5677 //
5678 // CHECK7-LABEL: define {{[^@]+}}@_Z3fooi
5679 // CHECK7-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] {
5680 // CHECK7-NEXT:  entry:
5681 // CHECK7-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
5682 // CHECK7-NEXT:    [[A:%.*]] = alloca i32, align 4
5683 // CHECK7-NEXT:    [[AA:%.*]] = alloca i16, align 2
5684 // CHECK7-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
5685 // CHECK7-NEXT:    [[SAVED_STACK:%.*]] = alloca ptr, align 4
5686 // CHECK7-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
5687 // CHECK7-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
5688 // CHECK7-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
5689 // CHECK7-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
5690 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
5691 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
5692 // CHECK7-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
5693 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
5694 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR__CASTED3:%.*]] = alloca i32, align 4
5695 // CHECK7-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 4
5696 // CHECK7-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 4
5697 // CHECK7-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 4
5698 // CHECK7-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4
5699 // CHECK7-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
5700 // CHECK7-NEXT:    [[AA_CASTED4:%.*]] = alloca i32, align 4
5701 // CHECK7-NEXT:    [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [1 x ptr], align 4
5702 // CHECK7-NEXT:    [[DOTOFFLOAD_PTRS6:%.*]] = alloca [1 x ptr], align 4
5703 // CHECK7-NEXT:    [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [1 x ptr], align 4
5704 // CHECK7-NEXT:    [[TMP:%.*]] = alloca i32, align 4
5705 // CHECK7-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
5706 // CHECK7-NEXT:    [[A_CASTED8:%.*]] = alloca i32, align 4
5707 // CHECK7-NEXT:    [[AA_CASTED9:%.*]] = alloca i32, align 4
5708 // CHECK7-NEXT:    [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [2 x ptr], align 4
5709 // CHECK7-NEXT:    [[DOTOFFLOAD_PTRS11:%.*]] = alloca [2 x ptr], align 4
5710 // CHECK7-NEXT:    [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [2 x ptr], align 4
5711 // CHECK7-NEXT:    [[_TMP13:%.*]] = alloca i32, align 4
5712 // CHECK7-NEXT:    [[KERNEL_ARGS14:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
5713 // CHECK7-NEXT:    [[A_CASTED17:%.*]] = alloca i32, align 4
5714 // CHECK7-NEXT:    [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [9 x ptr], align 4
5715 // CHECK7-NEXT:    [[DOTOFFLOAD_PTRS21:%.*]] = alloca [9 x ptr], align 4
5716 // CHECK7-NEXT:    [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [9 x ptr], align 4
5717 // CHECK7-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 4
5718 // CHECK7-NEXT:    [[_TMP23:%.*]] = alloca i32, align 4
5719 // CHECK7-NEXT:    [[KERNEL_ARGS24:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
5720 // CHECK7-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])
5721 // CHECK7-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
5722 // CHECK7-NEXT:    store i32 0, ptr [[A]], align 4
5723 // CHECK7-NEXT:    store i16 0, ptr [[AA]], align 2
5724 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
5725 // CHECK7-NEXT:    [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
5726 // CHECK7-NEXT:    store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4
5727 // CHECK7-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4
5728 // CHECK7-NEXT:    store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4
5729 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4
5730 // CHECK7-NEXT:    [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]]
5731 // CHECK7-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8
5732 // CHECK7-NEXT:    store i32 [[TMP3]], ptr [[__VLA_EXPR1]], align 4
5733 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, ptr [[A]], align 4
5734 // CHECK7-NEXT:    store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_]], align 4
5735 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, ptr [[A]], align 4
5736 // CHECK7-NEXT:    store i32 [[TMP6]], ptr [[DOTCAPTURE_EXPR_2]], align 4
5737 // CHECK7-NEXT:    [[TMP7:%.*]] = load i16, ptr [[AA]], align 2
5738 // CHECK7-NEXT:    store i16 [[TMP7]], ptr [[AA_CASTED]], align 2
5739 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, ptr [[AA_CASTED]], align 4
5740 // CHECK7-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
5741 // CHECK7-NEXT:    store i32 [[TMP9]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
5742 // CHECK7-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
5743 // CHECK7-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
5744 // CHECK7-NEXT:    store i32 [[TMP11]], ptr [[DOTCAPTURE_EXPR__CASTED3]], align 4
5745 // CHECK7-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED3]], align 4
5746 // CHECK7-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
5747 // CHECK7-NEXT:    store i32 [[TMP8]], ptr [[TMP13]], align 4
5748 // CHECK7-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
5749 // CHECK7-NEXT:    store i32 [[TMP8]], ptr [[TMP14]], align 4
5750 // CHECK7-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
5751 // CHECK7-NEXT:    store ptr null, ptr [[TMP15]], align 4
5752 // CHECK7-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
5753 // CHECK7-NEXT:    store i32 [[TMP10]], ptr [[TMP16]], align 4
5754 // CHECK7-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
5755 // CHECK7-NEXT:    store i32 [[TMP10]], ptr [[TMP17]], align 4
5756 // CHECK7-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
5757 // CHECK7-NEXT:    store ptr null, ptr [[TMP18]], align 4
5758 // CHECK7-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
5759 // CHECK7-NEXT:    store i32 [[TMP12]], ptr [[TMP19]], align 4
5760 // CHECK7-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
5761 // CHECK7-NEXT:    store i32 [[TMP12]], ptr [[TMP20]], align 4
5762 // CHECK7-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
5763 // CHECK7-NEXT:    store ptr null, ptr [[TMP21]], align 4
5764 // CHECK7-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
5765 // CHECK7-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
5766 // CHECK7-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0
5767 // CHECK7-NEXT:    [[TMP25:%.*]] = load i16, ptr [[AA]], align 2
5768 // CHECK7-NEXT:    store i16 [[TMP25]], ptr [[TMP24]], align 4
5769 // CHECK7-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 1
5770 // CHECK7-NEXT:    [[TMP27:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
5771 // CHECK7-NEXT:    store i32 [[TMP27]], ptr [[TMP26]], align 4
5772 // CHECK7-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 2
5773 // CHECK7-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
5774 // CHECK7-NEXT:    store i32 [[TMP29]], ptr [[TMP28]], align 4
5775 // CHECK7-NEXT:    [[TMP30:%.*]] = call ptr @__kmpc_omp_target_task_alloc(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 72, i32 12, ptr @.omp_task_entry., i64 -1)
5776 // CHECK7-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP30]], i32 0, i32 0
5777 // CHECK7-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP31]], i32 0, i32 0
5778 // CHECK7-NEXT:    [[TMP33:%.*]] = load ptr, ptr [[TMP32]], align 4
5779 // CHECK7-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP33]], ptr align 4 [[AGG_CAPTURED]], i32 12, i1 false)
5780 // CHECK7-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP30]], i32 0, i32 1
5781 // CHECK7-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP34]], i32 0, i32 0
5782 // CHECK7-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP35]], ptr align 4 @.offload_sizes, i32 24, i1 false)
5783 // CHECK7-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP34]], i32 0, i32 1
5784 // CHECK7-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP36]], ptr align 4 [[TMP22]], i32 12, i1 false)
5785 // CHECK7-NEXT:    [[TMP37:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP34]], i32 0, i32 2
5786 // CHECK7-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP37]], ptr align 4 [[TMP23]], i32 12, i1 false)
5787 // CHECK7-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP34]], i32 0, i32 3
5788 // CHECK7-NEXT:    [[TMP39:%.*]] = load i16, ptr [[AA]], align 2
5789 // CHECK7-NEXT:    store i16 [[TMP39]], ptr [[TMP38]], align 4
5790 // CHECK7-NEXT:    [[TMP40:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB2]], i32 [[TMP0]], ptr [[TMP30]])
5791 // CHECK7-NEXT:    [[TMP41:%.*]] = load i32, ptr [[A]], align 4
5792 // CHECK7-NEXT:    store i32 [[TMP41]], ptr [[A_CASTED]], align 4
5793 // CHECK7-NEXT:    [[TMP42:%.*]] = load i32, ptr [[A_CASTED]], align 4
5794 // CHECK7-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l102(i32 [[TMP42]]) #[[ATTR3:[0-9]+]]
5795 // CHECK7-NEXT:    [[TMP43:%.*]] = load i16, ptr [[AA]], align 2
5796 // CHECK7-NEXT:    store i16 [[TMP43]], ptr [[AA_CASTED4]], align 2
5797 // CHECK7-NEXT:    [[TMP44:%.*]] = load i32, ptr [[AA_CASTED4]], align 4
5798 // CHECK7-NEXT:    [[TMP45:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0
5799 // CHECK7-NEXT:    store i32 [[TMP44]], ptr [[TMP45]], align 4
5800 // CHECK7-NEXT:    [[TMP46:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0
5801 // CHECK7-NEXT:    store i32 [[TMP44]], ptr [[TMP46]], align 4
5802 // CHECK7-NEXT:    [[TMP47:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 0
5803 // CHECK7-NEXT:    store ptr null, ptr [[TMP47]], align 4
5804 // CHECK7-NEXT:    [[TMP48:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0
5805 // CHECK7-NEXT:    [[TMP49:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0
5806 // CHECK7-NEXT:    [[TMP50:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
5807 // CHECK7-NEXT:    store i32 2, ptr [[TMP50]], align 4
5808 // CHECK7-NEXT:    [[TMP51:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
5809 // CHECK7-NEXT:    store i32 1, ptr [[TMP51]], align 4
5810 // CHECK7-NEXT:    [[TMP52:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
5811 // CHECK7-NEXT:    store ptr [[TMP48]], ptr [[TMP52]], align 4
5812 // CHECK7-NEXT:    [[TMP53:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
5813 // CHECK7-NEXT:    store ptr [[TMP49]], ptr [[TMP53]], align 4
5814 // CHECK7-NEXT:    [[TMP54:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
5815 // CHECK7-NEXT:    store ptr @.offload_sizes.1, ptr [[TMP54]], align 4
5816 // CHECK7-NEXT:    [[TMP55:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
5817 // CHECK7-NEXT:    store ptr @.offload_maptypes.2, ptr [[TMP55]], align 4
5818 // CHECK7-NEXT:    [[TMP56:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
5819 // CHECK7-NEXT:    store ptr null, ptr [[TMP56]], align 4
5820 // CHECK7-NEXT:    [[TMP57:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
5821 // CHECK7-NEXT:    store ptr null, ptr [[TMP57]], align 4
5822 // CHECK7-NEXT:    [[TMP58:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
5823 // CHECK7-NEXT:    store i64 10, ptr [[TMP58]], align 8
5824 // CHECK7-NEXT:    [[TMP59:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
5825 // CHECK7-NEXT:    store i64 0, ptr [[TMP59]], align 8
5826 // CHECK7-NEXT:    [[TMP60:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
5827 // CHECK7-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP60]], align 4
5828 // CHECK7-NEXT:    [[TMP61:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
5829 // CHECK7-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP61]], align 4
5830 // CHECK7-NEXT:    [[TMP62:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
5831 // CHECK7-NEXT:    store i32 0, ptr [[TMP62]], align 4
5832 // CHECK7-NEXT:    [[TMP63:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.region_id, ptr [[KERNEL_ARGS]])
5833 // CHECK7-NEXT:    [[TMP64:%.*]] = icmp ne i32 [[TMP63]], 0
5834 // CHECK7-NEXT:    br i1 [[TMP64]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
5835 // CHECK7:       omp_offload.failed:
5836 // CHECK7-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i32 [[TMP44]]) #[[ATTR3]]
5837 // CHECK7-NEXT:    br label [[OMP_OFFLOAD_CONT]]
5838 // CHECK7:       omp_offload.cont:
5839 // CHECK7-NEXT:    [[TMP65:%.*]] = load i32, ptr [[A]], align 4
5840 // CHECK7-NEXT:    store i32 [[TMP65]], ptr [[A_CASTED8]], align 4
5841 // CHECK7-NEXT:    [[TMP66:%.*]] = load i32, ptr [[A_CASTED8]], align 4
5842 // CHECK7-NEXT:    [[TMP67:%.*]] = load i16, ptr [[AA]], align 2
5843 // CHECK7-NEXT:    store i16 [[TMP67]], ptr [[AA_CASTED9]], align 2
5844 // CHECK7-NEXT:    [[TMP68:%.*]] = load i32, ptr [[AA_CASTED9]], align 4
5845 // CHECK7-NEXT:    [[TMP69:%.*]] = load i32, ptr [[N_ADDR]], align 4
5846 // CHECK7-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP69]], 10
5847 // CHECK7-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
5848 // CHECK7:       omp_if.then:
5849 // CHECK7-NEXT:    [[TMP70:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
5850 // CHECK7-NEXT:    store i32 [[TMP66]], ptr [[TMP70]], align 4
5851 // CHECK7-NEXT:    [[TMP71:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
5852 // CHECK7-NEXT:    store i32 [[TMP66]], ptr [[TMP71]], align 4
5853 // CHECK7-NEXT:    [[TMP72:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS12]], i32 0, i32 0
5854 // CHECK7-NEXT:    store ptr null, ptr [[TMP72]], align 4
5855 // CHECK7-NEXT:    [[TMP73:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 1
5856 // CHECK7-NEXT:    store i32 [[TMP68]], ptr [[TMP73]], align 4
5857 // CHECK7-NEXT:    [[TMP74:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 1
5858 // CHECK7-NEXT:    store i32 [[TMP68]], ptr [[TMP74]], align 4
5859 // CHECK7-NEXT:    [[TMP75:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS12]], i32 0, i32 1
5860 // CHECK7-NEXT:    store ptr null, ptr [[TMP75]], align 4
5861 // CHECK7-NEXT:    [[TMP76:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0
5862 // CHECK7-NEXT:    [[TMP77:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS11]], i32 0, i32 0
5863 // CHECK7-NEXT:    [[TMP78:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 0
5864 // CHECK7-NEXT:    store i32 2, ptr [[TMP78]], align 4
5865 // CHECK7-NEXT:    [[TMP79:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 1
5866 // CHECK7-NEXT:    store i32 2, ptr [[TMP79]], align 4
5867 // CHECK7-NEXT:    [[TMP80:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 2
5868 // CHECK7-NEXT:    store ptr [[TMP76]], ptr [[TMP80]], align 4
5869 // CHECK7-NEXT:    [[TMP81:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 3
5870 // CHECK7-NEXT:    store ptr [[TMP77]], ptr [[TMP81]], align 4
5871 // CHECK7-NEXT:    [[TMP82:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 4
5872 // CHECK7-NEXT:    store ptr @.offload_sizes.3, ptr [[TMP82]], align 4
5873 // CHECK7-NEXT:    [[TMP83:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 5
5874 // CHECK7-NEXT:    store ptr @.offload_maptypes.4, ptr [[TMP83]], align 4
5875 // CHECK7-NEXT:    [[TMP84:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 6
5876 // CHECK7-NEXT:    store ptr null, ptr [[TMP84]], align 4
5877 // CHECK7-NEXT:    [[TMP85:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 7
5878 // CHECK7-NEXT:    store ptr null, ptr [[TMP85]], align 4
5879 // CHECK7-NEXT:    [[TMP86:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 8
5880 // CHECK7-NEXT:    store i64 10, ptr [[TMP86]], align 8
5881 // CHECK7-NEXT:    [[TMP87:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 9
5882 // CHECK7-NEXT:    store i64 0, ptr [[TMP87]], align 8
5883 // CHECK7-NEXT:    [[TMP88:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 10
5884 // CHECK7-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP88]], align 4
5885 // CHECK7-NEXT:    [[TMP89:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 11
5886 // CHECK7-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP89]], align 4
5887 // CHECK7-NEXT:    [[TMP90:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS14]], i32 0, i32 12
5888 // CHECK7-NEXT:    store i32 0, ptr [[TMP90]], align 4
5889 // CHECK7-NEXT:    [[TMP91:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.region_id, ptr [[KERNEL_ARGS14]])
5890 // CHECK7-NEXT:    [[TMP92:%.*]] = icmp ne i32 [[TMP91]], 0
5891 // CHECK7-NEXT:    br i1 [[TMP92]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]]
5892 // CHECK7:       omp_offload.failed15:
5893 // CHECK7-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP66]], i32 [[TMP68]]) #[[ATTR3]]
5894 // CHECK7-NEXT:    br label [[OMP_OFFLOAD_CONT16]]
5895 // CHECK7:       omp_offload.cont16:
5896 // CHECK7-NEXT:    br label [[OMP_IF_END:%.*]]
5897 // CHECK7:       omp_if.else:
5898 // CHECK7-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP66]], i32 [[TMP68]]) #[[ATTR3]]
5899 // CHECK7-NEXT:    br label [[OMP_IF_END]]
5900 // CHECK7:       omp_if.end:
5901 // CHECK7-NEXT:    [[TMP93:%.*]] = load i32, ptr [[A]], align 4
5902 // CHECK7-NEXT:    store i32 [[TMP93]], ptr [[A_CASTED17]], align 4
5903 // CHECK7-NEXT:    [[TMP94:%.*]] = load i32, ptr [[A_CASTED17]], align 4
5904 // CHECK7-NEXT:    [[TMP95:%.*]] = load i32, ptr [[N_ADDR]], align 4
5905 // CHECK7-NEXT:    [[CMP18:%.*]] = icmp sgt i32 [[TMP95]], 20
5906 // CHECK7-NEXT:    br i1 [[CMP18]], label [[OMP_IF_THEN19:%.*]], label [[OMP_IF_ELSE27:%.*]]
5907 // CHECK7:       omp_if.then19:
5908 // CHECK7-NEXT:    [[TMP96:%.*]] = mul nuw i32 [[TMP1]], 4
5909 // CHECK7-NEXT:    [[TMP97:%.*]] = sext i32 [[TMP96]] to i64
5910 // CHECK7-NEXT:    [[TMP98:%.*]] = mul nuw i32 5, [[TMP3]]
5911 // CHECK7-NEXT:    [[TMP99:%.*]] = mul nuw i32 [[TMP98]], 8
5912 // CHECK7-NEXT:    [[TMP100:%.*]] = sext i32 [[TMP99]] to i64
5913 // CHECK7-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes.5, i32 72, i1 false)
5914 // CHECK7-NEXT:    [[TMP101:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0
5915 // CHECK7-NEXT:    store i32 [[TMP94]], ptr [[TMP101]], align 4
5916 // CHECK7-NEXT:    [[TMP102:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 0
5917 // CHECK7-NEXT:    store i32 [[TMP94]], ptr [[TMP102]], align 4
5918 // CHECK7-NEXT:    [[TMP103:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 0
5919 // CHECK7-NEXT:    store ptr null, ptr [[TMP103]], align 4
5920 // CHECK7-NEXT:    [[TMP104:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1
5921 // CHECK7-NEXT:    store ptr [[B]], ptr [[TMP104]], align 4
5922 // CHECK7-NEXT:    [[TMP105:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 1
5923 // CHECK7-NEXT:    store ptr [[B]], ptr [[TMP105]], align 4
5924 // CHECK7-NEXT:    [[TMP106:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 1
5925 // CHECK7-NEXT:    store ptr null, ptr [[TMP106]], align 4
5926 // CHECK7-NEXT:    [[TMP107:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 2
5927 // CHECK7-NEXT:    store i32 [[TMP1]], ptr [[TMP107]], align 4
5928 // CHECK7-NEXT:    [[TMP108:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 2
5929 // CHECK7-NEXT:    store i32 [[TMP1]], ptr [[TMP108]], align 4
5930 // CHECK7-NEXT:    [[TMP109:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 2
5931 // CHECK7-NEXT:    store ptr null, ptr [[TMP109]], align 4
5932 // CHECK7-NEXT:    [[TMP110:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 3
5933 // CHECK7-NEXT:    store ptr [[VLA]], ptr [[TMP110]], align 4
5934 // CHECK7-NEXT:    [[TMP111:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 3
5935 // CHECK7-NEXT:    store ptr [[VLA]], ptr [[TMP111]], align 4
5936 // CHECK7-NEXT:    [[TMP112:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 3
5937 // CHECK7-NEXT:    store i64 [[TMP97]], ptr [[TMP112]], align 4
5938 // CHECK7-NEXT:    [[TMP113:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 3
5939 // CHECK7-NEXT:    store ptr null, ptr [[TMP113]], align 4
5940 // CHECK7-NEXT:    [[TMP114:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 4
5941 // CHECK7-NEXT:    store ptr [[C]], ptr [[TMP114]], align 4
5942 // CHECK7-NEXT:    [[TMP115:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 4
5943 // CHECK7-NEXT:    store ptr [[C]], ptr [[TMP115]], align 4
5944 // CHECK7-NEXT:    [[TMP116:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 4
5945 // CHECK7-NEXT:    store ptr null, ptr [[TMP116]], align 4
5946 // CHECK7-NEXT:    [[TMP117:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 5
5947 // CHECK7-NEXT:    store i32 5, ptr [[TMP117]], align 4
5948 // CHECK7-NEXT:    [[TMP118:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 5
5949 // CHECK7-NEXT:    store i32 5, ptr [[TMP118]], align 4
5950 // CHECK7-NEXT:    [[TMP119:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 5
5951 // CHECK7-NEXT:    store ptr null, ptr [[TMP119]], align 4
5952 // CHECK7-NEXT:    [[TMP120:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 6
5953 // CHECK7-NEXT:    store i32 [[TMP3]], ptr [[TMP120]], align 4
5954 // CHECK7-NEXT:    [[TMP121:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 6
5955 // CHECK7-NEXT:    store i32 [[TMP3]], ptr [[TMP121]], align 4
5956 // CHECK7-NEXT:    [[TMP122:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 6
5957 // CHECK7-NEXT:    store ptr null, ptr [[TMP122]], align 4
5958 // CHECK7-NEXT:    [[TMP123:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 7
5959 // CHECK7-NEXT:    store ptr [[VLA1]], ptr [[TMP123]], align 4
5960 // CHECK7-NEXT:    [[TMP124:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 7
5961 // CHECK7-NEXT:    store ptr [[VLA1]], ptr [[TMP124]], align 4
5962 // CHECK7-NEXT:    [[TMP125:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 7
5963 // CHECK7-NEXT:    store i64 [[TMP100]], ptr [[TMP125]], align 4
5964 // CHECK7-NEXT:    [[TMP126:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 7
5965 // CHECK7-NEXT:    store ptr null, ptr [[TMP126]], align 4
5966 // CHECK7-NEXT:    [[TMP127:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 8
5967 // CHECK7-NEXT:    store ptr [[D]], ptr [[TMP127]], align 4
5968 // CHECK7-NEXT:    [[TMP128:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 8
5969 // CHECK7-NEXT:    store ptr [[D]], ptr [[TMP128]], align 4
5970 // CHECK7-NEXT:    [[TMP129:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 8
5971 // CHECK7-NEXT:    store ptr null, ptr [[TMP129]], align 4
5972 // CHECK7-NEXT:    [[TMP130:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0
5973 // CHECK7-NEXT:    [[TMP131:%.*]] = getelementptr inbounds [9 x ptr], ptr [[DOTOFFLOAD_PTRS21]], i32 0, i32 0
5974 // CHECK7-NEXT:    [[TMP132:%.*]] = getelementptr inbounds [9 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0
5975 // CHECK7-NEXT:    [[TMP133:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 0
5976 // CHECK7-NEXT:    store i32 2, ptr [[TMP133]], align 4
5977 // CHECK7-NEXT:    [[TMP134:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 1
5978 // CHECK7-NEXT:    store i32 9, ptr [[TMP134]], align 4
5979 // CHECK7-NEXT:    [[TMP135:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 2
5980 // CHECK7-NEXT:    store ptr [[TMP130]], ptr [[TMP135]], align 4
5981 // CHECK7-NEXT:    [[TMP136:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 3
5982 // CHECK7-NEXT:    store ptr [[TMP131]], ptr [[TMP136]], align 4
5983 // CHECK7-NEXT:    [[TMP137:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 4
5984 // CHECK7-NEXT:    store ptr [[TMP132]], ptr [[TMP137]], align 4
5985 // CHECK7-NEXT:    [[TMP138:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 5
5986 // CHECK7-NEXT:    store ptr @.offload_maptypes.6, ptr [[TMP138]], align 4
5987 // CHECK7-NEXT:    [[TMP139:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 6
5988 // CHECK7-NEXT:    store ptr null, ptr [[TMP139]], align 4
5989 // CHECK7-NEXT:    [[TMP140:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 7
5990 // CHECK7-NEXT:    store ptr null, ptr [[TMP140]], align 4
5991 // CHECK7-NEXT:    [[TMP141:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 8
5992 // CHECK7-NEXT:    store i64 10, ptr [[TMP141]], align 8
5993 // CHECK7-NEXT:    [[TMP142:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 9
5994 // CHECK7-NEXT:    store i64 0, ptr [[TMP142]], align 8
5995 // CHECK7-NEXT:    [[TMP143:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 10
5996 // CHECK7-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP143]], align 4
5997 // CHECK7-NEXT:    [[TMP144:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 11
5998 // CHECK7-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP144]], align 4
5999 // CHECK7-NEXT:    [[TMP145:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS24]], i32 0, i32 12
6000 // CHECK7-NEXT:    store i32 0, ptr [[TMP145]], align 4
6001 // CHECK7-NEXT:    [[TMP146:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.region_id, ptr [[KERNEL_ARGS24]])
6002 // CHECK7-NEXT:    [[TMP147:%.*]] = icmp ne i32 [[TMP146]], 0
6003 // CHECK7-NEXT:    br i1 [[TMP147]], label [[OMP_OFFLOAD_FAILED25:%.*]], label [[OMP_OFFLOAD_CONT26:%.*]]
6004 // CHECK7:       omp_offload.failed25:
6005 // CHECK7-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP94]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]]) #[[ATTR3]]
6006 // CHECK7-NEXT:    br label [[OMP_OFFLOAD_CONT26]]
6007 // CHECK7:       omp_offload.cont26:
6008 // CHECK7-NEXT:    br label [[OMP_IF_END28:%.*]]
6009 // CHECK7:       omp_if.else27:
6010 // CHECK7-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP94]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]]) #[[ATTR3]]
6011 // CHECK7-NEXT:    br label [[OMP_IF_END28]]
6012 // CHECK7:       omp_if.end28:
6013 // CHECK7-NEXT:    [[TMP148:%.*]] = load i32, ptr [[A]], align 4
6014 // CHECK7-NEXT:    [[TMP149:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
6015 // CHECK7-NEXT:    call void @llvm.stackrestore.p0(ptr [[TMP149]])
6016 // CHECK7-NEXT:    ret i32 [[TMP148]]
6017 //
6018 //
6019 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97
6020 // CHECK7-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] {
6021 // CHECK7-NEXT:  entry:
6022 // CHECK7-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
6023 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
6024 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4
6025 // CHECK7-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
6026 // CHECK7-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2]])
6027 // CHECK7-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
6028 // CHECK7-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
6029 // CHECK7-NEXT:    store i32 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4
6030 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
6031 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4
6032 // CHECK7-NEXT:    call void @__kmpc_push_num_teams(ptr @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
6033 // CHECK7-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
6034 // CHECK7-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
6035 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4
6036 // CHECK7-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.omp_outlined, i32 [[TMP4]])
6037 // CHECK7-NEXT:    ret void
6038 //
6039 //
6040 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.omp_outlined
6041 // CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {
6042 // CHECK7-NEXT:  entry:
6043 // CHECK7-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
6044 // CHECK7-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
6045 // CHECK7-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
6046 // CHECK7-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
6047 // CHECK7-NEXT:    [[TMP:%.*]] = alloca i32, align 4
6048 // CHECK7-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
6049 // CHECK7-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
6050 // CHECK7-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
6051 // CHECK7-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
6052 // CHECK7-NEXT:    [[I:%.*]] = alloca i32, align 4
6053 // CHECK7-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
6054 // CHECK7-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
6055 // CHECK7-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
6056 // CHECK7-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
6057 // CHECK7-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4
6058 // CHECK7-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
6059 // CHECK7-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
6060 // CHECK7-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
6061 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
6062 // CHECK7-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
6063 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
6064 // CHECK7-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
6065 // CHECK7-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
6066 // CHECK7:       cond.true:
6067 // CHECK7-NEXT:    br label [[COND_END:%.*]]
6068 // CHECK7:       cond.false:
6069 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
6070 // CHECK7-NEXT:    br label [[COND_END]]
6071 // CHECK7:       cond.end:
6072 // CHECK7-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
6073 // CHECK7-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
6074 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
6075 // CHECK7-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
6076 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
6077 // CHECK7:       omp.inner.for.cond:
6078 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11:![0-9]+]]
6079 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP11]]
6080 // CHECK7-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
6081 // CHECK7-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
6082 // CHECK7:       omp.inner.for.body:
6083 // CHECK7-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]
6084 // CHECK7-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
6085 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
6086 // CHECK7-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]]
6087 // CHECK7-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
6088 // CHECK7:       omp.body.continue:
6089 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
6090 // CHECK7:       omp.inner.for.inc:
6091 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]
6092 // CHECK7-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
6093 // CHECK7-NEXT:    store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]
6094 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
6095 // CHECK7:       omp.inner.for.end:
6096 // CHECK7-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
6097 // CHECK7:       omp.loop.exit:
6098 // CHECK7-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
6099 // CHECK7-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
6100 // CHECK7-NEXT:    [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
6101 // CHECK7-NEXT:    br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
6102 // CHECK7:       .omp.final.then:
6103 // CHECK7-NEXT:    store i32 10, ptr [[I]], align 4
6104 // CHECK7-NEXT:    br label [[DOTOMP_FINAL_DONE]]
6105 // CHECK7:       .omp.final.done:
6106 // CHECK7-NEXT:    ret void
6107 //
6108 //
6109 // CHECK7-LABEL: define {{[^@]+}}@.omp_task_privates_map.
6110 // CHECK7-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]], ptr noalias noundef [[TMP3:%.*]], ptr noalias noundef [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] {
6111 // CHECK7-NEXT:  entry:
6112 // CHECK7-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 4
6113 // CHECK7-NEXT:    [[DOTADDR1:%.*]] = alloca ptr, align 4
6114 // CHECK7-NEXT:    [[DOTADDR2:%.*]] = alloca ptr, align 4
6115 // CHECK7-NEXT:    [[DOTADDR3:%.*]] = alloca ptr, align 4
6116 // CHECK7-NEXT:    [[DOTADDR4:%.*]] = alloca ptr, align 4
6117 // CHECK7-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 4
6118 // CHECK7-NEXT:    store ptr [[TMP1]], ptr [[DOTADDR1]], align 4
6119 // CHECK7-NEXT:    store ptr [[TMP2]], ptr [[DOTADDR2]], align 4
6120 // CHECK7-NEXT:    store ptr [[TMP3]], ptr [[DOTADDR3]], align 4
6121 // CHECK7-NEXT:    store ptr [[TMP4]], ptr [[DOTADDR4]], align 4
6122 // CHECK7-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[DOTADDR]], align 4
6123 // CHECK7-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP5]], i32 0, i32 0
6124 // CHECK7-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[DOTADDR4]], align 4
6125 // CHECK7-NEXT:    store ptr [[TMP6]], ptr [[TMP7]], align 4
6126 // CHECK7-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 1
6127 // CHECK7-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[DOTADDR2]], align 4
6128 // CHECK7-NEXT:    store ptr [[TMP8]], ptr [[TMP9]], align 4
6129 // CHECK7-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 2
6130 // CHECK7-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[DOTADDR3]], align 4
6131 // CHECK7-NEXT:    store ptr [[TMP10]], ptr [[TMP11]], align 4
6132 // CHECK7-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 3
6133 // CHECK7-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[DOTADDR1]], align 4
6134 // CHECK7-NEXT:    store ptr [[TMP12]], ptr [[TMP13]], align 4
6135 // CHECK7-NEXT:    ret void
6136 //
6137 //
6138 // CHECK7-LABEL: define {{[^@]+}}@.omp_task_entry.
6139 // CHECK7-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] {
6140 // CHECK7-NEXT:  entry:
6141 // CHECK7-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
6142 // CHECK7-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 4
6143 // CHECK7-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 4
6144 // CHECK7-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 4
6145 // CHECK7-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 4
6146 // CHECK7-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 4
6147 // CHECK7-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca ptr, align 4
6148 // CHECK7-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca ptr, align 4
6149 // CHECK7-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca ptr, align 4
6150 // CHECK7-NEXT:    [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca ptr, align 4
6151 // CHECK7-NEXT:    [[KERNEL_ARGS_I:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
6152 // CHECK7-NEXT:    [[AA_CASTED_I:%.*]] = alloca i32, align 4
6153 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i32, align 4
6154 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR__CASTED4_I:%.*]] = alloca i32, align 4
6155 // CHECK7-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 4
6156 // CHECK7-NEXT:    [[DOTADDR1:%.*]] = alloca ptr, align 4
6157 // CHECK7-NEXT:    store i32 [[TMP0]], ptr [[DOTADDR]], align 4
6158 // CHECK7-NEXT:    store ptr [[TMP1]], ptr [[DOTADDR1]], align 4
6159 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4
6160 // CHECK7-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 4
6161 // CHECK7-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0
6162 // CHECK7-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2
6163 // CHECK7-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0
6164 // CHECK7-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 4
6165 // CHECK7-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 1
6166 // CHECK7-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])
6167 // CHECK7-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])
6168 // CHECK7-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]])
6169 // CHECK7-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META25:![0-9]+]])
6170 // CHECK7-NEXT:    store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !27
6171 // CHECK7-NEXT:    store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 4, !noalias !27
6172 // CHECK7-NEXT:    store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 4, !noalias !27
6173 // CHECK7-NEXT:    store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !27
6174 // CHECK7-NEXT:    store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 4, !noalias !27
6175 // CHECK7-NEXT:    store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 4, !noalias !27
6176 // CHECK7-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 4, !noalias !27
6177 // CHECK7-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !27
6178 // CHECK7-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 4, !noalias !27
6179 // CHECK7-NEXT:    call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]]
6180 // CHECK7-NEXT:    [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !27
6181 // CHECK7-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !27
6182 // CHECK7-NEXT:    [[TMP14:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !27
6183 // CHECK7-NEXT:    [[TMP15:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !27
6184 // CHECK7-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP9]], i32 0, i32 1
6185 // CHECK7-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP9]], i32 0, i32 2
6186 // CHECK7-NEXT:    [[TMP18:%.*]] = load i32, ptr [[TMP16]], align 4
6187 // CHECK7-NEXT:    [[TMP19:%.*]] = insertvalue [3 x i32] zeroinitializer, i32 [[TMP18]], 0
6188 // CHECK7-NEXT:    store i32 2, ptr [[KERNEL_ARGS_I]], align 4, !noalias !27
6189 // CHECK7-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 1
6190 // CHECK7-NEXT:    store i32 3, ptr [[TMP20]], align 4, !noalias !27
6191 // CHECK7-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 2
6192 // CHECK7-NEXT:    store ptr [[TMP13]], ptr [[TMP21]], align 4, !noalias !27
6193 // CHECK7-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 3
6194 // CHECK7-NEXT:    store ptr [[TMP14]], ptr [[TMP22]], align 4, !noalias !27
6195 // CHECK7-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 4
6196 // CHECK7-NEXT:    store ptr [[TMP15]], ptr [[TMP23]], align 4, !noalias !27
6197 // CHECK7-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 5
6198 // CHECK7-NEXT:    store ptr @.offload_maptypes, ptr [[TMP24]], align 4, !noalias !27
6199 // CHECK7-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 6
6200 // CHECK7-NEXT:    store ptr null, ptr [[TMP25]], align 4, !noalias !27
6201 // CHECK7-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 7
6202 // CHECK7-NEXT:    store ptr null, ptr [[TMP26]], align 4, !noalias !27
6203 // CHECK7-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 8
6204 // CHECK7-NEXT:    store i64 10, ptr [[TMP27]], align 8, !noalias !27
6205 // CHECK7-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 9
6206 // CHECK7-NEXT:    store i64 1, ptr [[TMP28]], align 8, !noalias !27
6207 // CHECK7-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 10
6208 // CHECK7-NEXT:    store [3 x i32] [[TMP19]], ptr [[TMP29]], align 4, !noalias !27
6209 // CHECK7-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 11
6210 // CHECK7-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP30]], align 4, !noalias !27
6211 // CHECK7-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 12
6212 // CHECK7-NEXT:    store i32 0, ptr [[TMP31]], align 4, !noalias !27
6213 // CHECK7-NEXT:    [[TMP32:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 [[TMP18]], i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.region_id, ptr [[KERNEL_ARGS_I]])
6214 // CHECK7-NEXT:    [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0
6215 // CHECK7-NEXT:    br i1 [[TMP33]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__EXIT:%.*]]
6216 // CHECK7:       omp_offload.failed.i:
6217 // CHECK7-NEXT:    [[TMP34:%.*]] = load i16, ptr [[TMP12]], align 2
6218 // CHECK7-NEXT:    store i16 [[TMP34]], ptr [[AA_CASTED_I]], align 2, !noalias !27
6219 // CHECK7-NEXT:    [[TMP35:%.*]] = load i32, ptr [[AA_CASTED_I]], align 4, !noalias !27
6220 // CHECK7-NEXT:    [[TMP36:%.*]] = load i32, ptr [[TMP16]], align 4
6221 // CHECK7-NEXT:    store i32 [[TMP36]], ptr [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !27
6222 // CHECK7-NEXT:    [[TMP37:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !27
6223 // CHECK7-NEXT:    [[TMP38:%.*]] = load i32, ptr [[TMP17]], align 4
6224 // CHECK7-NEXT:    store i32 [[TMP38]], ptr [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !27
6225 // CHECK7-NEXT:    [[TMP39:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !27
6226 // CHECK7-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97(i32 [[TMP35]], i32 [[TMP37]], i32 [[TMP39]]) #[[ATTR3]]
6227 // CHECK7-NEXT:    br label [[DOTOMP_OUTLINED__EXIT]]
6228 // CHECK7:       .omp_outlined..exit:
6229 // CHECK7-NEXT:    ret i32 0
6230 //
6231 //
6232 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l102
6233 // CHECK7-SAME: (i32 noundef [[A:%.*]]) #[[ATTR2]] {
6234 // CHECK7-NEXT:  entry:
6235 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
6236 // CHECK7-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
6237 // CHECK7-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
6238 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
6239 // CHECK7-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 4
6240 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4
6241 // CHECK7-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l102.omp_outlined, i32 [[TMP1]])
6242 // CHECK7-NEXT:    ret void
6243 //
6244 //
6245 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l102.omp_outlined
6246 // CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] {
6247 // CHECK7-NEXT:  entry:
6248 // CHECK7-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
6249 // CHECK7-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
6250 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
6251 // CHECK7-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
6252 // CHECK7-NEXT:    [[TMP:%.*]] = alloca i32, align 4
6253 // CHECK7-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
6254 // CHECK7-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
6255 // CHECK7-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
6256 // CHECK7-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
6257 // CHECK7-NEXT:    [[A1:%.*]] = alloca i32, align 4
6258 // CHECK7-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
6259 // CHECK7-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
6260 // CHECK7-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
6261 // CHECK7-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
6262 // CHECK7-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4
6263 // CHECK7-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
6264 // CHECK7-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
6265 // CHECK7-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
6266 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
6267 // CHECK7-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
6268 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
6269 // CHECK7-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
6270 // CHECK7-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
6271 // CHECK7:       cond.true:
6272 // CHECK7-NEXT:    br label [[COND_END:%.*]]
6273 // CHECK7:       cond.false:
6274 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
6275 // CHECK7-NEXT:    br label [[COND_END]]
6276 // CHECK7:       cond.end:
6277 // CHECK7-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
6278 // CHECK7-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
6279 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
6280 // CHECK7-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
6281 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
6282 // CHECK7:       omp.inner.for.cond:
6283 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
6284 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
6285 // CHECK7-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
6286 // CHECK7-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
6287 // CHECK7:       omp.inner.for.body:
6288 // CHECK7-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
6289 // CHECK7-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
6290 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
6291 // CHECK7-NEXT:    store i32 [[ADD]], ptr [[A1]], align 4, !nontemporal !28
6292 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A1]], align 4, !nontemporal !28
6293 // CHECK7-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1
6294 // CHECK7-NEXT:    store i32 [[ADD3]], ptr [[A1]], align 4, !nontemporal !28
6295 // CHECK7-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
6296 // CHECK7:       omp.body.continue:
6297 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
6298 // CHECK7:       omp.inner.for.inc:
6299 // CHECK7-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
6300 // CHECK7-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP9]], 1
6301 // CHECK7-NEXT:    store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4
6302 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]]
6303 // CHECK7:       omp.inner.for.end:
6304 // CHECK7-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
6305 // CHECK7:       omp.loop.exit:
6306 // CHECK7-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
6307 // CHECK7-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
6308 // CHECK7-NEXT:    [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
6309 // CHECK7-NEXT:    br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
6310 // CHECK7:       .omp.final.then:
6311 // CHECK7-NEXT:    store i32 10, ptr [[A_ADDR]], align 4
6312 // CHECK7-NEXT:    br label [[DOTOMP_FINAL_DONE]]
6313 // CHECK7:       .omp.final.done:
6314 // CHECK7-NEXT:    ret void
6315 //
6316 //
6317 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
6318 // CHECK7-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR2]] {
6319 // CHECK7-NEXT:  entry:
6320 // CHECK7-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
6321 // CHECK7-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
6322 // CHECK7-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
6323 // CHECK7-NEXT:    [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2
6324 // CHECK7-NEXT:    store i16 [[TMP0]], ptr [[AA_CASTED]], align 2
6325 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, ptr [[AA_CASTED]], align 4
6326 // CHECK7-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined, i32 [[TMP1]])
6327 // CHECK7-NEXT:    ret void
6328 //
6329 //
6330 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined
6331 // CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {
6332 // CHECK7-NEXT:  entry:
6333 // CHECK7-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
6334 // CHECK7-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
6335 // CHECK7-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
6336 // CHECK7-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
6337 // CHECK7-NEXT:    [[TMP:%.*]] = alloca i32, align 4
6338 // CHECK7-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
6339 // CHECK7-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
6340 // CHECK7-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
6341 // CHECK7-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
6342 // CHECK7-NEXT:    [[I:%.*]] = alloca i32, align 4
6343 // CHECK7-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
6344 // CHECK7-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
6345 // CHECK7-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
6346 // CHECK7-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
6347 // CHECK7-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4
6348 // CHECK7-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
6349 // CHECK7-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
6350 // CHECK7-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
6351 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
6352 // CHECK7-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
6353 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
6354 // CHECK7-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
6355 // CHECK7-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
6356 // CHECK7:       cond.true:
6357 // CHECK7-NEXT:    br label [[COND_END:%.*]]
6358 // CHECK7:       cond.false:
6359 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
6360 // CHECK7-NEXT:    br label [[COND_END]]
6361 // CHECK7:       cond.end:
6362 // CHECK7-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
6363 // CHECK7-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
6364 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
6365 // CHECK7-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
6366 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
6367 // CHECK7:       omp.inner.for.cond:
6368 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31:![0-9]+]]
6369 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP31]]
6370 // CHECK7-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
6371 // CHECK7-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
6372 // CHECK7:       omp.inner.for.body:
6373 // CHECK7-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31]]
6374 // CHECK7-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
6375 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
6376 // CHECK7-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP31]]
6377 // CHECK7-NEXT:    [[TMP8:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP31]]
6378 // CHECK7-NEXT:    [[CONV:%.*]] = sext i16 [[TMP8]] to i32
6379 // CHECK7-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
6380 // CHECK7-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
6381 // CHECK7-NEXT:    store i16 [[CONV3]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP31]]
6382 // CHECK7-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
6383 // CHECK7:       omp.body.continue:
6384 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
6385 // CHECK7:       omp.inner.for.inc:
6386 // CHECK7-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31]]
6387 // CHECK7-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP9]], 1
6388 // CHECK7-NEXT:    store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31]]
6389 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP32:![0-9]+]]
6390 // CHECK7:       omp.inner.for.end:
6391 // CHECK7-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
6392 // CHECK7:       omp.loop.exit:
6393 // CHECK7-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
6394 // CHECK7-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
6395 // CHECK7-NEXT:    [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
6396 // CHECK7-NEXT:    br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
6397 // CHECK7:       .omp.final.then:
6398 // CHECK7-NEXT:    store i32 10, ptr [[I]], align 4
6399 // CHECK7-NEXT:    br label [[DOTOMP_FINAL_DONE]]
6400 // CHECK7:       .omp.final.done:
6401 // CHECK7-NEXT:    ret void
6402 //
6403 //
6404 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118
6405 // CHECK7-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {
6406 // CHECK7-NEXT:  entry:
6407 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
6408 // CHECK7-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
6409 // CHECK7-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
6410 // CHECK7-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
6411 // CHECK7-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
6412 // CHECK7-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
6413 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
6414 // CHECK7-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 4
6415 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4
6416 // CHECK7-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2
6417 // CHECK7-NEXT:    store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
6418 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4
6419 // CHECK7-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined, i32 [[TMP1]], i32 [[TMP3]])
6420 // CHECK7-NEXT:    ret void
6421 //
6422 //
6423 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined
6424 // CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {
6425 // CHECK7-NEXT:  entry:
6426 // CHECK7-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
6427 // CHECK7-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
6428 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
6429 // CHECK7-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
6430 // CHECK7-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
6431 // CHECK7-NEXT:    [[TMP:%.*]] = alloca i32, align 4
6432 // CHECK7-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
6433 // CHECK7-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
6434 // CHECK7-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
6435 // CHECK7-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
6436 // CHECK7-NEXT:    [[I:%.*]] = alloca i32, align 4
6437 // CHECK7-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
6438 // CHECK7-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
6439 // CHECK7-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
6440 // CHECK7-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
6441 // CHECK7-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
6442 // CHECK7-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4
6443 // CHECK7-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
6444 // CHECK7-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
6445 // CHECK7-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
6446 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
6447 // CHECK7-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
6448 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
6449 // CHECK7-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
6450 // CHECK7-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
6451 // CHECK7:       cond.true:
6452 // CHECK7-NEXT:    br label [[COND_END:%.*]]
6453 // CHECK7:       cond.false:
6454 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
6455 // CHECK7-NEXT:    br label [[COND_END]]
6456 // CHECK7:       cond.end:
6457 // CHECK7-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
6458 // CHECK7-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
6459 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
6460 // CHECK7-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
6461 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
6462 // CHECK7:       omp.inner.for.cond:
6463 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP34:![0-9]+]]
6464 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP34]]
6465 // CHECK7-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
6466 // CHECK7-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
6467 // CHECK7:       omp.inner.for.body:
6468 // CHECK7-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP34]]
6469 // CHECK7-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
6470 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
6471 // CHECK7-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP34]]
6472 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP34]]
6473 // CHECK7-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
6474 // CHECK7-NEXT:    store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP34]]
6475 // CHECK7-NEXT:    [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP34]]
6476 // CHECK7-NEXT:    [[CONV:%.*]] = sext i16 [[TMP9]] to i32
6477 // CHECK7-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV]], 1
6478 // CHECK7-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
6479 // CHECK7-NEXT:    store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP34]]
6480 // CHECK7-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
6481 // CHECK7:       omp.body.continue:
6482 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
6483 // CHECK7:       omp.inner.for.inc:
6484 // CHECK7-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP34]]
6485 // CHECK7-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP10]], 1
6486 // CHECK7-NEXT:    store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP34]]
6487 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP35:![0-9]+]]
6488 // CHECK7:       omp.inner.for.end:
6489 // CHECK7-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
6490 // CHECK7:       omp.loop.exit:
6491 // CHECK7-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
6492 // CHECK7-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
6493 // CHECK7-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
6494 // CHECK7-NEXT:    br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
6495 // CHECK7:       .omp.final.then:
6496 // CHECK7-NEXT:    store i32 10, ptr [[I]], align 4
6497 // CHECK7-NEXT:    br label [[DOTOMP_FINAL_DONE]]
6498 // CHECK7:       .omp.final.done:
6499 // CHECK7-NEXT:    ret void
6500 //
6501 //
6502 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142
6503 // CHECK7-SAME: (i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] {
6504 // CHECK7-NEXT:  entry:
6505 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
6506 // CHECK7-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
6507 // CHECK7-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
6508 // CHECK7-NEXT:    [[BN_ADDR:%.*]] = alloca ptr, align 4
6509 // CHECK7-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
6510 // CHECK7-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
6511 // CHECK7-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
6512 // CHECK7-NEXT:    [[CN_ADDR:%.*]] = alloca ptr, align 4
6513 // CHECK7-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4
6514 // CHECK7-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
6515 // CHECK7-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
6516 // CHECK7-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
6517 // CHECK7-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
6518 // CHECK7-NEXT:    store ptr [[BN]], ptr [[BN_ADDR]], align 4
6519 // CHECK7-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
6520 // CHECK7-NEXT:    store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
6521 // CHECK7-NEXT:    store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4
6522 // CHECK7-NEXT:    store ptr [[CN]], ptr [[CN_ADDR]], align 4
6523 // CHECK7-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4
6524 // CHECK7-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
6525 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
6526 // CHECK7-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4
6527 // CHECK7-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
6528 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
6529 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4
6530 // CHECK7-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4
6531 // CHECK7-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4
6532 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
6533 // CHECK7-NEXT:    store i32 [[TMP8]], ptr [[A_CASTED]], align 4
6534 // CHECK7-NEXT:    [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4
6535 // CHECK7-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.omp_outlined, i32 [[TMP9]], ptr [[TMP0]], i32 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]])
6536 // CHECK7-NEXT:    ret void
6537 //
6538 //
6539 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.omp_outlined
6540 // CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] {
6541 // CHECK7-NEXT:  entry:
6542 // CHECK7-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
6543 // CHECK7-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
6544 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
6545 // CHECK7-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
6546 // CHECK7-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
6547 // CHECK7-NEXT:    [[BN_ADDR:%.*]] = alloca ptr, align 4
6548 // CHECK7-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
6549 // CHECK7-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
6550 // CHECK7-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
6551 // CHECK7-NEXT:    [[CN_ADDR:%.*]] = alloca ptr, align 4
6552 // CHECK7-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4
6553 // CHECK7-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
6554 // CHECK7-NEXT:    [[TMP:%.*]] = alloca i32, align 4
6555 // CHECK7-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
6556 // CHECK7-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
6557 // CHECK7-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
6558 // CHECK7-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
6559 // CHECK7-NEXT:    [[I:%.*]] = alloca i32, align 4
6560 // CHECK7-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
6561 // CHECK7-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
6562 // CHECK7-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
6563 // CHECK7-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
6564 // CHECK7-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
6565 // CHECK7-NEXT:    store ptr [[BN]], ptr [[BN_ADDR]], align 4
6566 // CHECK7-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
6567 // CHECK7-NEXT:    store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
6568 // CHECK7-NEXT:    store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4
6569 // CHECK7-NEXT:    store ptr [[CN]], ptr [[CN_ADDR]], align 4
6570 // CHECK7-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4
6571 // CHECK7-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
6572 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
6573 // CHECK7-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4
6574 // CHECK7-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
6575 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
6576 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4
6577 // CHECK7-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4
6578 // CHECK7-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4
6579 // CHECK7-NEXT:    [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 0
6580 // CHECK7-NEXT:    call void @llvm.assume(i1 true) [ "align"(ptr [[ARRAYDECAY]], i32 16) ]
6581 // CHECK7-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
6582 // CHECK7-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4
6583 // CHECK7-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
6584 // CHECK7-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
6585 // CHECK7-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
6586 // CHECK7-NEXT:    [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
6587 // CHECK7-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP9]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
6588 // CHECK7-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
6589 // CHECK7-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 9
6590 // CHECK7-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
6591 // CHECK7:       cond.true:
6592 // CHECK7-NEXT:    br label [[COND_END:%.*]]
6593 // CHECK7:       cond.false:
6594 // CHECK7-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
6595 // CHECK7-NEXT:    br label [[COND_END]]
6596 // CHECK7:       cond.end:
6597 // CHECK7-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
6598 // CHECK7-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
6599 // CHECK7-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
6600 // CHECK7-NEXT:    store i32 [[TMP12]], ptr [[DOTOMP_IV]], align 4
6601 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
6602 // CHECK7:       omp.inner.for.cond:
6603 // CHECK7-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP37:![0-9]+]]
6604 // CHECK7-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP37]]
6605 // CHECK7-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
6606 // CHECK7-NEXT:    br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
6607 // CHECK7:       omp.inner.for.body:
6608 // CHECK7-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP37]]
6609 // CHECK7-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
6610 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
6611 // CHECK7-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP37]]
6612 // CHECK7-NEXT:    [[TMP16:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP37]]
6613 // CHECK7-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1
6614 // CHECK7-NEXT:    store i32 [[ADD6]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP37]]
6615 // CHECK7-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 2
6616 // CHECK7-NEXT:    [[TMP17:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP37]]
6617 // CHECK7-NEXT:    [[CONV:%.*]] = fpext float [[TMP17]] to double
6618 // CHECK7-NEXT:    [[ADD7:%.*]] = fadd double [[CONV]], 1.000000e+00
6619 // CHECK7-NEXT:    [[CONV8:%.*]] = fptrunc double [[ADD7]] to float
6620 // CHECK7-NEXT:    store float [[CONV8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP37]]
6621 // CHECK7-NEXT:    [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i32 3
6622 // CHECK7-NEXT:    [[TMP18:%.*]] = load float, ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP37]]
6623 // CHECK7-NEXT:    [[CONV10:%.*]] = fpext float [[TMP18]] to double
6624 // CHECK7-NEXT:    [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00
6625 // CHECK7-NEXT:    [[CONV12:%.*]] = fptrunc double [[ADD11]] to float
6626 // CHECK7-NEXT:    store float [[CONV12]], ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP37]]
6627 // CHECK7-NEXT:    [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 1
6628 // CHECK7-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX13]], i32 0, i32 2
6629 // CHECK7-NEXT:    [[TMP19:%.*]] = load double, ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP37]]
6630 // CHECK7-NEXT:    [[ADD15:%.*]] = fadd double [[TMP19]], 1.000000e+00
6631 // CHECK7-NEXT:    store double [[ADD15]], ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP37]]
6632 // CHECK7-NEXT:    [[TMP20:%.*]] = mul nsw i32 1, [[TMP5]]
6633 // CHECK7-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i32 [[TMP20]]
6634 // CHECK7-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX16]], i32 3
6635 // CHECK7-NEXT:    [[TMP21:%.*]] = load double, ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP37]]
6636 // CHECK7-NEXT:    [[ADD18:%.*]] = fadd double [[TMP21]], 1.000000e+00
6637 // CHECK7-NEXT:    store double [[ADD18]], ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP37]]
6638 // CHECK7-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0
6639 // CHECK7-NEXT:    [[TMP22:%.*]] = load i64, ptr [[X]], align 4, !llvm.access.group [[ACC_GRP37]]
6640 // CHECK7-NEXT:    [[ADD19:%.*]] = add nsw i64 [[TMP22]], 1
6641 // CHECK7-NEXT:    store i64 [[ADD19]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP37]]
6642 // CHECK7-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1
6643 // CHECK7-NEXT:    [[TMP23:%.*]] = load i8, ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP37]]
6644 // CHECK7-NEXT:    [[CONV20:%.*]] = sext i8 [[TMP23]] to i32
6645 // CHECK7-NEXT:    [[ADD21:%.*]] = add nsw i32 [[CONV20]], 1
6646 // CHECK7-NEXT:    [[CONV22:%.*]] = trunc i32 [[ADD21]] to i8
6647 // CHECK7-NEXT:    store i8 [[CONV22]], ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP37]]
6648 // CHECK7-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
6649 // CHECK7:       omp.body.continue:
6650 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
6651 // CHECK7:       omp.inner.for.inc:
6652 // CHECK7-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP37]]
6653 // CHECK7-NEXT:    [[ADD23:%.*]] = add nsw i32 [[TMP24]], 1
6654 // CHECK7-NEXT:    store i32 [[ADD23]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP37]]
6655 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP38:![0-9]+]]
6656 // CHECK7:       omp.inner.for.end:
6657 // CHECK7-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
6658 // CHECK7:       omp.loop.exit:
6659 // CHECK7-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP9]])
6660 // CHECK7-NEXT:    [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
6661 // CHECK7-NEXT:    [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
6662 // CHECK7-NEXT:    br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
6663 // CHECK7:       .omp.final.then:
6664 // CHECK7-NEXT:    store i32 10, ptr [[I]], align 4
6665 // CHECK7-NEXT:    br label [[DOTOMP_FINAL_DONE]]
6666 // CHECK7:       .omp.final.done:
6667 // CHECK7-NEXT:    ret void
6668 //
6669 //
6670 // CHECK7-LABEL: define {{[^@]+}}@_Z3bari
6671 // CHECK7-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
6672 // CHECK7-NEXT:  entry:
6673 // CHECK7-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
6674 // CHECK7-NEXT:    [[A:%.*]] = alloca i32, align 4
6675 // CHECK7-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
6676 // CHECK7-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
6677 // CHECK7-NEXT:    store i32 0, ptr [[A]], align 4
6678 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
6679 // CHECK7-NEXT:    [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]])
6680 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A]], align 4
6681 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
6682 // CHECK7-NEXT:    store i32 [[ADD]], ptr [[A]], align 4
6683 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
6684 // CHECK7-NEXT:    [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]])
6685 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A]], align 4
6686 // CHECK7-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
6687 // CHECK7-NEXT:    store i32 [[ADD2]], ptr [[A]], align 4
6688 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
6689 // CHECK7-NEXT:    [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]])
6690 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, ptr [[A]], align 4
6691 // CHECK7-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
6692 // CHECK7-NEXT:    store i32 [[ADD4]], ptr [[A]], align 4
6693 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4
6694 // CHECK7-NEXT:    [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]])
6695 // CHECK7-NEXT:    [[TMP7:%.*]] = load i32, ptr [[A]], align 4
6696 // CHECK7-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
6697 // CHECK7-NEXT:    store i32 [[ADD6]], ptr [[A]], align 4
6698 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A]], align 4
6699 // CHECK7-NEXT:    ret i32 [[TMP8]]
6700 //
6701 //
6702 // CHECK7-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
6703 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 {
6704 // CHECK7-NEXT:  entry:
6705 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
6706 // CHECK7-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
6707 // CHECK7-NEXT:    [[B:%.*]] = alloca i32, align 4
6708 // CHECK7-NEXT:    [[SAVED_STACK:%.*]] = alloca ptr, align 4
6709 // CHECK7-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
6710 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
6711 // CHECK7-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
6712 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
6713 // CHECK7-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [6 x ptr], align 4
6714 // CHECK7-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [6 x ptr], align 4
6715 // CHECK7-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [6 x ptr], align 4
6716 // CHECK7-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [6 x i64], align 4
6717 // CHECK7-NEXT:    [[TMP:%.*]] = alloca i32, align 4
6718 // CHECK7-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
6719 // CHECK7-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
6720 // CHECK7-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
6721 // CHECK7-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
6722 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
6723 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
6724 // CHECK7-NEXT:    store i32 [[ADD]], ptr [[B]], align 4
6725 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
6726 // CHECK7-NEXT:    [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
6727 // CHECK7-NEXT:    store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4
6728 // CHECK7-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
6729 // CHECK7-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
6730 // CHECK7-NEXT:    store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4
6731 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
6732 // CHECK7-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 60
6733 // CHECK7-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
6734 // CHECK7-NEXT:    store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR_]], align 1
6735 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, ptr [[B]], align 4
6736 // CHECK7-NEXT:    store i32 [[TMP5]], ptr [[B_CASTED]], align 4
6737 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, ptr [[B_CASTED]], align 4
6738 // CHECK7-NEXT:    [[TMP7:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
6739 // CHECK7-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1
6740 // CHECK7-NEXT:    [[FROMBOOL2:%.*]] = zext i1 [[TOBOOL]] to i8
6741 // CHECK7-NEXT:    store i8 [[FROMBOOL2]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1
6742 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
6743 // CHECK7-NEXT:    [[TMP9:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
6744 // CHECK7-NEXT:    [[TOBOOL3:%.*]] = trunc i8 [[TMP9]] to i1
6745 // CHECK7-NEXT:    br i1 [[TOBOOL3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
6746 // CHECK7:       omp_if.then:
6747 // CHECK7-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0
6748 // CHECK7-NEXT:    [[TMP10:%.*]] = mul nuw i32 2, [[TMP1]]
6749 // CHECK7-NEXT:    [[TMP11:%.*]] = mul nuw i32 [[TMP10]], 2
6750 // CHECK7-NEXT:    [[TMP12:%.*]] = sext i32 [[TMP11]] to i64
6751 // CHECK7-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes.7, i32 48, i1 false)
6752 // CHECK7-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
6753 // CHECK7-NEXT:    store ptr [[THIS1]], ptr [[TMP13]], align 4
6754 // CHECK7-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
6755 // CHECK7-NEXT:    store ptr [[A]], ptr [[TMP14]], align 4
6756 // CHECK7-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
6757 // CHECK7-NEXT:    store ptr null, ptr [[TMP15]], align 4
6758 // CHECK7-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
6759 // CHECK7-NEXT:    store i32 [[TMP6]], ptr [[TMP16]], align 4
6760 // CHECK7-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
6761 // CHECK7-NEXT:    store i32 [[TMP6]], ptr [[TMP17]], align 4
6762 // CHECK7-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
6763 // CHECK7-NEXT:    store ptr null, ptr [[TMP18]], align 4
6764 // CHECK7-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
6765 // CHECK7-NEXT:    store i32 2, ptr [[TMP19]], align 4
6766 // CHECK7-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
6767 // CHECK7-NEXT:    store i32 2, ptr [[TMP20]], align 4
6768 // CHECK7-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
6769 // CHECK7-NEXT:    store ptr null, ptr [[TMP21]], align 4
6770 // CHECK7-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
6771 // CHECK7-NEXT:    store i32 [[TMP1]], ptr [[TMP22]], align 4
6772 // CHECK7-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
6773 // CHECK7-NEXT:    store i32 [[TMP1]], ptr [[TMP23]], align 4
6774 // CHECK7-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
6775 // CHECK7-NEXT:    store ptr null, ptr [[TMP24]], align 4
6776 // CHECK7-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
6777 // CHECK7-NEXT:    store ptr [[VLA]], ptr [[TMP25]], align 4
6778 // CHECK7-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4
6779 // CHECK7-NEXT:    store ptr [[VLA]], ptr [[TMP26]], align 4
6780 // CHECK7-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [6 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 4
6781 // CHECK7-NEXT:    store i64 [[TMP12]], ptr [[TMP27]], align 4
6782 // CHECK7-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
6783 // CHECK7-NEXT:    store ptr null, ptr [[TMP28]], align 4
6784 // CHECK7-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5
6785 // CHECK7-NEXT:    store i32 [[TMP8]], ptr [[TMP29]], align 4
6786 // CHECK7-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 5
6787 // CHECK7-NEXT:    store i32 [[TMP8]], ptr [[TMP30]], align 4
6788 // CHECK7-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 5
6789 // CHECK7-NEXT:    store ptr null, ptr [[TMP31]], align 4
6790 // CHECK7-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
6791 // CHECK7-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [6 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
6792 // CHECK7-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [6 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0
6793 // CHECK7-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
6794 // CHECK7-NEXT:    store i32 2, ptr [[TMP35]], align 4
6795 // CHECK7-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
6796 // CHECK7-NEXT:    store i32 6, ptr [[TMP36]], align 4
6797 // CHECK7-NEXT:    [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
6798 // CHECK7-NEXT:    store ptr [[TMP32]], ptr [[TMP37]], align 4
6799 // CHECK7-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
6800 // CHECK7-NEXT:    store ptr [[TMP33]], ptr [[TMP38]], align 4
6801 // CHECK7-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
6802 // CHECK7-NEXT:    store ptr [[TMP34]], ptr [[TMP39]], align 4
6803 // CHECK7-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
6804 // CHECK7-NEXT:    store ptr @.offload_maptypes.8, ptr [[TMP40]], align 4
6805 // CHECK7-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
6806 // CHECK7-NEXT:    store ptr null, ptr [[TMP41]], align 4
6807 // CHECK7-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
6808 // CHECK7-NEXT:    store ptr null, ptr [[TMP42]], align 4
6809 // CHECK7-NEXT:    [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
6810 // CHECK7-NEXT:    store i64 10, ptr [[TMP43]], align 8
6811 // CHECK7-NEXT:    [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
6812 // CHECK7-NEXT:    store i64 0, ptr [[TMP44]], align 8
6813 // CHECK7-NEXT:    [[TMP45:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
6814 // CHECK7-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP45]], align 4
6815 // CHECK7-NEXT:    [[TMP46:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
6816 // CHECK7-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP46]], align 4
6817 // CHECK7-NEXT:    [[TMP47:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
6818 // CHECK7-NEXT:    store i32 0, ptr [[TMP47]], align 4
6819 // CHECK7-NEXT:    [[TMP48:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.region_id, ptr [[KERNEL_ARGS]])
6820 // CHECK7-NEXT:    [[TMP49:%.*]] = icmp ne i32 [[TMP48]], 0
6821 // CHECK7-NEXT:    br i1 [[TMP49]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
6822 // CHECK7:       omp_offload.failed:
6823 // CHECK7-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215(ptr [[THIS1]], i32 [[TMP6]], i32 2, i32 [[TMP1]], ptr [[VLA]], i32 [[TMP8]]) #[[ATTR3]]
6824 // CHECK7-NEXT:    br label [[OMP_OFFLOAD_CONT]]
6825 // CHECK7:       omp_offload.cont:
6826 // CHECK7-NEXT:    br label [[OMP_IF_END:%.*]]
6827 // CHECK7:       omp_if.else:
6828 // CHECK7-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215(ptr [[THIS1]], i32 [[TMP6]], i32 2, i32 [[TMP1]], ptr [[VLA]], i32 [[TMP8]]) #[[ATTR3]]
6829 // CHECK7-NEXT:    br label [[OMP_IF_END]]
6830 // CHECK7:       omp_if.end:
6831 // CHECK7-NEXT:    [[TMP50:%.*]] = mul nsw i32 1, [[TMP1]]
6832 // CHECK7-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP50]]
6833 // CHECK7-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1
6834 // CHECK7-NEXT:    [[TMP51:%.*]] = load i16, ptr [[ARRAYIDX4]], align 2
6835 // CHECK7-NEXT:    [[CONV:%.*]] = sext i16 [[TMP51]] to i32
6836 // CHECK7-NEXT:    [[TMP52:%.*]] = load i32, ptr [[B]], align 4
6837 // CHECK7-NEXT:    [[ADD5:%.*]] = add nsw i32 [[CONV]], [[TMP52]]
6838 // CHECK7-NEXT:    [[TMP53:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
6839 // CHECK7-NEXT:    call void @llvm.stackrestore.p0(ptr [[TMP53]])
6840 // CHECK7-NEXT:    ret i32 [[ADD5]]
6841 //
6842 //
6843 // CHECK7-LABEL: define {{[^@]+}}@_ZL7fstatici
6844 // CHECK7-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
6845 // CHECK7-NEXT:  entry:
6846 // CHECK7-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
6847 // CHECK7-NEXT:    [[A:%.*]] = alloca i32, align 4
6848 // CHECK7-NEXT:    [[AA:%.*]] = alloca i16, align 2
6849 // CHECK7-NEXT:    [[AAA:%.*]] = alloca i8, align 1
6850 // CHECK7-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
6851 // CHECK7-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
6852 // CHECK7-NEXT:    [[N_CASTED:%.*]] = alloca i32, align 4
6853 // CHECK7-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
6854 // CHECK7-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
6855 // CHECK7-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 4
6856 // CHECK7-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 4
6857 // CHECK7-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 4
6858 // CHECK7-NEXT:    [[TMP:%.*]] = alloca i32, align 4
6859 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
6860 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
6861 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
6862 // CHECK7-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
6863 // CHECK7-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
6864 // CHECK7-NEXT:    store i32 0, ptr [[A]], align 4
6865 // CHECK7-NEXT:    store i16 0, ptr [[AA]], align 2
6866 // CHECK7-NEXT:    store i8 0, ptr [[AAA]], align 1
6867 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A]], align 4
6868 // CHECK7-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 4
6869 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4
6870 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
6871 // CHECK7-NEXT:    store i32 [[TMP2]], ptr [[N_CASTED]], align 4
6872 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, ptr [[N_CASTED]], align 4
6873 // CHECK7-NEXT:    [[TMP4:%.*]] = load i16, ptr [[AA]], align 2
6874 // CHECK7-NEXT:    store i16 [[TMP4]], ptr [[AA_CASTED]], align 2
6875 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, ptr [[AA_CASTED]], align 4
6876 // CHECK7-NEXT:    [[TMP6:%.*]] = load i8, ptr [[AAA]], align 1
6877 // CHECK7-NEXT:    store i8 [[TMP6]], ptr [[AAA_CASTED]], align 1
6878 // CHECK7-NEXT:    [[TMP7:%.*]] = load i32, ptr [[AAA_CASTED]], align 4
6879 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, ptr [[N_ADDR]], align 4
6880 // CHECK7-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 50
6881 // CHECK7-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
6882 // CHECK7:       omp_if.then:
6883 // CHECK7-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
6884 // CHECK7-NEXT:    store i32 [[TMP1]], ptr [[TMP9]], align 4
6885 // CHECK7-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
6886 // CHECK7-NEXT:    store i32 [[TMP1]], ptr [[TMP10]], align 4
6887 // CHECK7-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
6888 // CHECK7-NEXT:    store ptr null, ptr [[TMP11]], align 4
6889 // CHECK7-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
6890 // CHECK7-NEXT:    store i32 [[TMP3]], ptr [[TMP12]], align 4
6891 // CHECK7-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
6892 // CHECK7-NEXT:    store i32 [[TMP3]], ptr [[TMP13]], align 4
6893 // CHECK7-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
6894 // CHECK7-NEXT:    store ptr null, ptr [[TMP14]], align 4
6895 // CHECK7-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
6896 // CHECK7-NEXT:    store i32 [[TMP5]], ptr [[TMP15]], align 4
6897 // CHECK7-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
6898 // CHECK7-NEXT:    store i32 [[TMP5]], ptr [[TMP16]], align 4
6899 // CHECK7-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
6900 // CHECK7-NEXT:    store ptr null, ptr [[TMP17]], align 4
6901 // CHECK7-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
6902 // CHECK7-NEXT:    store i32 [[TMP7]], ptr [[TMP18]], align 4
6903 // CHECK7-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
6904 // CHECK7-NEXT:    store i32 [[TMP7]], ptr [[TMP19]], align 4
6905 // CHECK7-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
6906 // CHECK7-NEXT:    store ptr null, ptr [[TMP20]], align 4
6907 // CHECK7-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
6908 // CHECK7-NEXT:    store ptr [[B]], ptr [[TMP21]], align 4
6909 // CHECK7-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4
6910 // CHECK7-NEXT:    store ptr [[B]], ptr [[TMP22]], align 4
6911 // CHECK7-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
6912 // CHECK7-NEXT:    store ptr null, ptr [[TMP23]], align 4
6913 // CHECK7-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
6914 // CHECK7-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
6915 // CHECK7-NEXT:    [[TMP26:%.*]] = load i32, ptr [[A]], align 4
6916 // CHECK7-NEXT:    store i32 [[TMP26]], ptr [[DOTCAPTURE_EXPR_]], align 4
6917 // CHECK7-NEXT:    [[TMP27:%.*]] = load i32, ptr [[N_ADDR]], align 4
6918 // CHECK7-NEXT:    store i32 [[TMP27]], ptr [[DOTCAPTURE_EXPR_1]], align 4
6919 // CHECK7-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
6920 // CHECK7-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
6921 // CHECK7-NEXT:    [[SUB:%.*]] = sub i32 [[TMP28]], [[TMP29]]
6922 // CHECK7-NEXT:    [[SUB3:%.*]] = sub i32 [[SUB]], 1
6923 // CHECK7-NEXT:    [[ADD:%.*]] = add i32 [[SUB3]], 1
6924 // CHECK7-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
6925 // CHECK7-NEXT:    [[SUB4:%.*]] = sub i32 [[DIV]], 1
6926 // CHECK7-NEXT:    store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 4
6927 // CHECK7-NEXT:    [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
6928 // CHECK7-NEXT:    [[ADD5:%.*]] = add i32 [[TMP30]], 1
6929 // CHECK7-NEXT:    [[TMP31:%.*]] = zext i32 [[ADD5]] to i64
6930 // CHECK7-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
6931 // CHECK7-NEXT:    store i32 2, ptr [[TMP32]], align 4
6932 // CHECK7-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
6933 // CHECK7-NEXT:    store i32 5, ptr [[TMP33]], align 4
6934 // CHECK7-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
6935 // CHECK7-NEXT:    store ptr [[TMP24]], ptr [[TMP34]], align 4
6936 // CHECK7-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
6937 // CHECK7-NEXT:    store ptr [[TMP25]], ptr [[TMP35]], align 4
6938 // CHECK7-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
6939 // CHECK7-NEXT:    store ptr @.offload_sizes.9, ptr [[TMP36]], align 4
6940 // CHECK7-NEXT:    [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
6941 // CHECK7-NEXT:    store ptr @.offload_maptypes.10, ptr [[TMP37]], align 4
6942 // CHECK7-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
6943 // CHECK7-NEXT:    store ptr null, ptr [[TMP38]], align 4
6944 // CHECK7-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
6945 // CHECK7-NEXT:    store ptr null, ptr [[TMP39]], align 4
6946 // CHECK7-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
6947 // CHECK7-NEXT:    store i64 [[TMP31]], ptr [[TMP40]], align 8
6948 // CHECK7-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
6949 // CHECK7-NEXT:    store i64 0, ptr [[TMP41]], align 8
6950 // CHECK7-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
6951 // CHECK7-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP42]], align 4
6952 // CHECK7-NEXT:    [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
6953 // CHECK7-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP43]], align 4
6954 // CHECK7-NEXT:    [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
6955 // CHECK7-NEXT:    store i32 0, ptr [[TMP44]], align 4
6956 // CHECK7-NEXT:    [[TMP45:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.region_id, ptr [[KERNEL_ARGS]])
6957 // CHECK7-NEXT:    [[TMP46:%.*]] = icmp ne i32 [[TMP45]], 0
6958 // CHECK7-NEXT:    br i1 [[TMP46]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
6959 // CHECK7:       omp_offload.failed:
6960 // CHECK7-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], i32 [[TMP7]], ptr [[B]]) #[[ATTR3]]
6961 // CHECK7-NEXT:    br label [[OMP_OFFLOAD_CONT]]
6962 // CHECK7:       omp_offload.cont:
6963 // CHECK7-NEXT:    br label [[OMP_IF_END:%.*]]
6964 // CHECK7:       omp_if.else:
6965 // CHECK7-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], i32 [[TMP7]], ptr [[B]]) #[[ATTR3]]
6966 // CHECK7-NEXT:    br label [[OMP_IF_END]]
6967 // CHECK7:       omp_if.end:
6968 // CHECK7-NEXT:    [[TMP47:%.*]] = load i32, ptr [[A]], align 4
6969 // CHECK7-NEXT:    ret i32 [[TMP47]]
6970 //
6971 //
6972 // CHECK7-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
6973 // CHECK7-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat {
6974 // CHECK7-NEXT:  entry:
6975 // CHECK7-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
6976 // CHECK7-NEXT:    [[A:%.*]] = alloca i32, align 4
6977 // CHECK7-NEXT:    [[AA:%.*]] = alloca i16, align 2
6978 // CHECK7-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
6979 // CHECK7-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
6980 // CHECK7-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
6981 // CHECK7-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 4
6982 // CHECK7-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 4
6983 // CHECK7-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 4
6984 // CHECK7-NEXT:    [[TMP:%.*]] = alloca i32, align 4
6985 // CHECK7-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
6986 // CHECK7-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
6987 // CHECK7-NEXT:    store i32 0, ptr [[A]], align 4
6988 // CHECK7-NEXT:    store i16 0, ptr [[AA]], align 2
6989 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A]], align 4
6990 // CHECK7-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 4
6991 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4
6992 // CHECK7-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA]], align 2
6993 // CHECK7-NEXT:    store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
6994 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4
6995 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
6996 // CHECK7-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
6997 // CHECK7-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
6998 // CHECK7:       omp_if.then:
6999 // CHECK7-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
7000 // CHECK7-NEXT:    store i32 [[TMP1]], ptr [[TMP5]], align 4
7001 // CHECK7-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
7002 // CHECK7-NEXT:    store i32 [[TMP1]], ptr [[TMP6]], align 4
7003 // CHECK7-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
7004 // CHECK7-NEXT:    store ptr null, ptr [[TMP7]], align 4
7005 // CHECK7-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
7006 // CHECK7-NEXT:    store i32 [[TMP3]], ptr [[TMP8]], align 4
7007 // CHECK7-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
7008 // CHECK7-NEXT:    store i32 [[TMP3]], ptr [[TMP9]], align 4
7009 // CHECK7-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
7010 // CHECK7-NEXT:    store ptr null, ptr [[TMP10]], align 4
7011 // CHECK7-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
7012 // CHECK7-NEXT:    store ptr [[B]], ptr [[TMP11]], align 4
7013 // CHECK7-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
7014 // CHECK7-NEXT:    store ptr [[B]], ptr [[TMP12]], align 4
7015 // CHECK7-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
7016 // CHECK7-NEXT:    store ptr null, ptr [[TMP13]], align 4
7017 // CHECK7-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
7018 // CHECK7-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
7019 // CHECK7-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
7020 // CHECK7-NEXT:    store i32 2, ptr [[TMP16]], align 4
7021 // CHECK7-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
7022 // CHECK7-NEXT:    store i32 3, ptr [[TMP17]], align 4
7023 // CHECK7-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
7024 // CHECK7-NEXT:    store ptr [[TMP14]], ptr [[TMP18]], align 4
7025 // CHECK7-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
7026 // CHECK7-NEXT:    store ptr [[TMP15]], ptr [[TMP19]], align 4
7027 // CHECK7-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
7028 // CHECK7-NEXT:    store ptr @.offload_sizes.11, ptr [[TMP20]], align 4
7029 // CHECK7-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
7030 // CHECK7-NEXT:    store ptr @.offload_maptypes.12, ptr [[TMP21]], align 4
7031 // CHECK7-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
7032 // CHECK7-NEXT:    store ptr null, ptr [[TMP22]], align 4
7033 // CHECK7-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
7034 // CHECK7-NEXT:    store ptr null, ptr [[TMP23]], align 4
7035 // CHECK7-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
7036 // CHECK7-NEXT:    store i64 10, ptr [[TMP24]], align 8
7037 // CHECK7-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
7038 // CHECK7-NEXT:    store i64 0, ptr [[TMP25]], align 8
7039 // CHECK7-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
7040 // CHECK7-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP26]], align 4
7041 // CHECK7-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
7042 // CHECK7-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP27]], align 4
7043 // CHECK7-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
7044 // CHECK7-NEXT:    store i32 0, ptr [[TMP28]], align 4
7045 // CHECK7-NEXT:    [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.region_id, ptr [[KERNEL_ARGS]])
7046 // CHECK7-NEXT:    [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
7047 // CHECK7-NEXT:    br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
7048 // CHECK7:       omp_offload.failed:
7049 // CHECK7-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR3]]
7050 // CHECK7-NEXT:    br label [[OMP_OFFLOAD_CONT]]
7051 // CHECK7:       omp_offload.cont:
7052 // CHECK7-NEXT:    br label [[OMP_IF_END:%.*]]
7053 // CHECK7:       omp_if.else:
7054 // CHECK7-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR3]]
7055 // CHECK7-NEXT:    br label [[OMP_IF_END]]
7056 // CHECK7:       omp_if.end:
7057 // CHECK7-NEXT:    [[TMP31:%.*]] = load i32, ptr [[A]], align 4
7058 // CHECK7-NEXT:    ret i32 [[TMP31]]
7059 //
7060 //
7061 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215
7062 // CHECK7-SAME: (ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
7063 // CHECK7-NEXT:  entry:
7064 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
7065 // CHECK7-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
7066 // CHECK7-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
7067 // CHECK7-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
7068 // CHECK7-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
7069 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
7070 // CHECK7-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
7071 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
7072 // CHECK7-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
7073 // CHECK7-NEXT:    store i32 [[B]], ptr [[B_ADDR]], align 4
7074 // CHECK7-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
7075 // CHECK7-NEXT:    store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
7076 // CHECK7-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
7077 // CHECK7-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
7078 // CHECK7-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
7079 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
7080 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
7081 // CHECK7-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
7082 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4
7083 // CHECK7-NEXT:    store i32 [[TMP4]], ptr [[B_CASTED]], align 4
7084 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4
7085 // CHECK7-NEXT:    [[TMP6:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1
7086 // CHECK7-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1
7087 // CHECK7-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
7088 // CHECK7-NEXT:    store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1
7089 // CHECK7-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
7090 // CHECK7-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.omp_outlined, ptr [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], ptr [[TMP3]], i32 [[TMP7]])
7091 // CHECK7-NEXT:    ret void
7092 //
7093 //
7094 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.omp_outlined
7095 // CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
7096 // CHECK7-NEXT:  entry:
7097 // CHECK7-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
7098 // CHECK7-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
7099 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
7100 // CHECK7-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
7101 // CHECK7-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
7102 // CHECK7-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
7103 // CHECK7-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
7104 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
7105 // CHECK7-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
7106 // CHECK7-NEXT:    [[TMP:%.*]] = alloca i32, align 4
7107 // CHECK7-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
7108 // CHECK7-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
7109 // CHECK7-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
7110 // CHECK7-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
7111 // CHECK7-NEXT:    [[I:%.*]] = alloca i32, align 4
7112 // CHECK7-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
7113 // CHECK7-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
7114 // CHECK7-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
7115 // CHECK7-NEXT:    store i32 [[B]], ptr [[B_ADDR]], align 4
7116 // CHECK7-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
7117 // CHECK7-NEXT:    store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
7118 // CHECK7-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
7119 // CHECK7-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
7120 // CHECK7-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
7121 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
7122 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
7123 // CHECK7-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
7124 // CHECK7-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
7125 // CHECK7-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4
7126 // CHECK7-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
7127 // CHECK7-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
7128 // CHECK7-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
7129 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
7130 // CHECK7-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
7131 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
7132 // CHECK7-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9
7133 // CHECK7-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
7134 // CHECK7:       cond.true:
7135 // CHECK7-NEXT:    br label [[COND_END:%.*]]
7136 // CHECK7:       cond.false:
7137 // CHECK7-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
7138 // CHECK7-NEXT:    br label [[COND_END]]
7139 // CHECK7:       cond.end:
7140 // CHECK7-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
7141 // CHECK7-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
7142 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
7143 // CHECK7-NEXT:    store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4
7144 // CHECK7-NEXT:    [[TMP9:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1
7145 // CHECK7-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP9]] to i1
7146 // CHECK7-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
7147 // CHECK7:       omp_if.then:
7148 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
7149 // CHECK7:       omp.inner.for.cond:
7150 // CHECK7-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP40:![0-9]+]]
7151 // CHECK7-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP40]]
7152 // CHECK7-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
7153 // CHECK7-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
7154 // CHECK7:       omp.inner.for.body:
7155 // CHECK7-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP40]]
7156 // CHECK7-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
7157 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
7158 // CHECK7-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP40]]
7159 // CHECK7-NEXT:    [[TMP13:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP40]]
7160 // CHECK7-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP13]] to double
7161 // CHECK7-NEXT:    [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00
7162 // CHECK7-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0
7163 // CHECK7-NEXT:    store double [[ADD4]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP40]]
7164 // CHECK7-NEXT:    [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0
7165 // CHECK7-NEXT:    [[TMP14:%.*]] = load double, ptr [[A5]], align 4, !llvm.access.group [[ACC_GRP40]]
7166 // CHECK7-NEXT:    [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00
7167 // CHECK7-NEXT:    store double [[INC]], ptr [[A5]], align 4, !llvm.access.group [[ACC_GRP40]]
7168 // CHECK7-NEXT:    [[CONV6:%.*]] = fptosi double [[INC]] to i16
7169 // CHECK7-NEXT:    [[TMP15:%.*]] = mul nsw i32 1, [[TMP2]]
7170 // CHECK7-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i32 [[TMP15]]
7171 // CHECK7-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1
7172 // CHECK7-NEXT:    store i16 [[CONV6]], ptr [[ARRAYIDX7]], align 2, !llvm.access.group [[ACC_GRP40]]
7173 // CHECK7-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
7174 // CHECK7:       omp.body.continue:
7175 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
7176 // CHECK7:       omp.inner.for.inc:
7177 // CHECK7-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP40]]
7178 // CHECK7-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP16]], 1
7179 // CHECK7-NEXT:    store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP40]]
7180 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP41:![0-9]+]]
7181 // CHECK7:       omp.inner.for.end:
7182 // CHECK7-NEXT:    br label [[OMP_IF_END:%.*]]
7183 // CHECK7:       omp_if.else:
7184 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND9:%.*]]
7185 // CHECK7:       omp.inner.for.cond9:
7186 // CHECK7-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
7187 // CHECK7-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
7188 // CHECK7-NEXT:    [[CMP10:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]
7189 // CHECK7-NEXT:    br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END25:%.*]]
7190 // CHECK7:       omp.inner.for.body11:
7191 // CHECK7-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
7192 // CHECK7-NEXT:    [[MUL12:%.*]] = mul nsw i32 [[TMP19]], 1
7193 // CHECK7-NEXT:    [[ADD13:%.*]] = add nsw i32 0, [[MUL12]]
7194 // CHECK7-NEXT:    store i32 [[ADD13]], ptr [[I]], align 4
7195 // CHECK7-NEXT:    [[TMP20:%.*]] = load i32, ptr [[B_ADDR]], align 4
7196 // CHECK7-NEXT:    [[CONV14:%.*]] = sitofp i32 [[TMP20]] to double
7197 // CHECK7-NEXT:    [[ADD15:%.*]] = fadd double [[CONV14]], 1.500000e+00
7198 // CHECK7-NEXT:    [[A16:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0
7199 // CHECK7-NEXT:    store double [[ADD15]], ptr [[A16]], align 4
7200 // CHECK7-NEXT:    [[A17:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0
7201 // CHECK7-NEXT:    [[TMP21:%.*]] = load double, ptr [[A17]], align 4
7202 // CHECK7-NEXT:    [[INC18:%.*]] = fadd double [[TMP21]], 1.000000e+00
7203 // CHECK7-NEXT:    store double [[INC18]], ptr [[A17]], align 4
7204 // CHECK7-NEXT:    [[CONV19:%.*]] = fptosi double [[INC18]] to i16
7205 // CHECK7-NEXT:    [[TMP22:%.*]] = mul nsw i32 1, [[TMP2]]
7206 // CHECK7-NEXT:    [[ARRAYIDX20:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i32 [[TMP22]]
7207 // CHECK7-NEXT:    [[ARRAYIDX21:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX20]], i32 1
7208 // CHECK7-NEXT:    store i16 [[CONV19]], ptr [[ARRAYIDX21]], align 2
7209 // CHECK7-NEXT:    br label [[OMP_BODY_CONTINUE22:%.*]]
7210 // CHECK7:       omp.body.continue22:
7211 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_INC23:%.*]]
7212 // CHECK7:       omp.inner.for.inc23:
7213 // CHECK7-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
7214 // CHECK7-NEXT:    [[ADD24:%.*]] = add nsw i32 [[TMP23]], 1
7215 // CHECK7-NEXT:    store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4
7216 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP43:![0-9]+]]
7217 // CHECK7:       omp.inner.for.end25:
7218 // CHECK7-NEXT:    br label [[OMP_IF_END]]
7219 // CHECK7:       omp_if.end:
7220 // CHECK7-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
7221 // CHECK7:       omp.loop.exit:
7222 // CHECK7-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])
7223 // CHECK7-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
7224 // CHECK7-NEXT:    [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
7225 // CHECK7-NEXT:    br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
7226 // CHECK7:       .omp.final.then:
7227 // CHECK7-NEXT:    store i32 10, ptr [[I]], align 4
7228 // CHECK7-NEXT:    br label [[DOTOMP_FINAL_DONE]]
7229 // CHECK7:       .omp.final.done:
7230 // CHECK7-NEXT:    ret void
7231 //
7232 //
7233 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197
7234 // CHECK7-SAME: (i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
7235 // CHECK7-NEXT:  entry:
7236 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
7237 // CHECK7-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7238 // CHECK7-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
7239 // CHECK7-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
7240 // CHECK7-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
7241 // CHECK7-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
7242 // CHECK7-NEXT:    [[N_CASTED:%.*]] = alloca i32, align 4
7243 // CHECK7-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
7244 // CHECK7-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
7245 // CHECK7-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
7246 // CHECK7-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
7247 // CHECK7-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
7248 // CHECK7-NEXT:    store i32 [[AAA]], ptr [[AAA_ADDR]], align 4
7249 // CHECK7-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
7250 // CHECK7-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
7251 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
7252 // CHECK7-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 4
7253 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4
7254 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4
7255 // CHECK7-NEXT:    store i32 [[TMP3]], ptr [[N_CASTED]], align 4
7256 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N_CASTED]], align 4
7257 // CHECK7-NEXT:    [[TMP5:%.*]] = load i16, ptr [[AA_ADDR]], align 2
7258 // CHECK7-NEXT:    store i16 [[TMP5]], ptr [[AA_CASTED]], align 2
7259 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, ptr [[AA_CASTED]], align 4
7260 // CHECK7-NEXT:    [[TMP7:%.*]] = load i8, ptr [[AAA_ADDR]], align 1
7261 // CHECK7-NEXT:    store i8 [[TMP7]], ptr [[AAA_CASTED]], align 1
7262 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, ptr [[AAA_CASTED]], align 4
7263 // CHECK7-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], ptr [[TMP0]])
7264 // CHECK7-NEXT:    ret void
7265 //
7266 //
7267 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.omp_outlined
7268 // CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
7269 // CHECK7-NEXT:  entry:
7270 // CHECK7-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
7271 // CHECK7-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
7272 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
7273 // CHECK7-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7274 // CHECK7-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
7275 // CHECK7-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
7276 // CHECK7-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
7277 // CHECK7-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
7278 // CHECK7-NEXT:    [[TMP:%.*]] = alloca i32, align 4
7279 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
7280 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
7281 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
7282 // CHECK7-NEXT:    [[I:%.*]] = alloca i32, align 4
7283 // CHECK7-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
7284 // CHECK7-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
7285 // CHECK7-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
7286 // CHECK7-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
7287 // CHECK7-NEXT:    [[I5:%.*]] = alloca i32, align 4
7288 // CHECK7-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
7289 // CHECK7-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
7290 // CHECK7-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
7291 // CHECK7-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
7292 // CHECK7-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
7293 // CHECK7-NEXT:    store i32 [[AAA]], ptr [[AAA_ADDR]], align 4
7294 // CHECK7-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
7295 // CHECK7-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
7296 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
7297 // CHECK7-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
7298 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
7299 // CHECK7-NEXT:    store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
7300 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
7301 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
7302 // CHECK7-NEXT:    [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
7303 // CHECK7-NEXT:    [[SUB3:%.*]] = sub i32 [[SUB]], 1
7304 // CHECK7-NEXT:    [[ADD:%.*]] = add i32 [[SUB3]], 1
7305 // CHECK7-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
7306 // CHECK7-NEXT:    [[SUB4:%.*]] = sub i32 [[DIV]], 1
7307 // CHECK7-NEXT:    store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 4
7308 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
7309 // CHECK7-NEXT:    store i32 [[TMP5]], ptr [[I]], align 4
7310 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
7311 // CHECK7-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
7312 // CHECK7-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
7313 // CHECK7-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
7314 // CHECK7:       omp.precond.then:
7315 // CHECK7-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
7316 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
7317 // CHECK7-NEXT:    store i32 [[TMP8]], ptr [[DOTOMP_UB]], align 4
7318 // CHECK7-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
7319 // CHECK7-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
7320 // CHECK7-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
7321 // CHECK7-NEXT:    [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4
7322 // CHECK7-NEXT:    call void @__kmpc_for_static_init_4u(ptr @[[GLOB1]], i32 [[TMP10]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
7323 // CHECK7-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
7324 // CHECK7-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
7325 // CHECK7-NEXT:    [[CMP6:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]]
7326 // CHECK7-NEXT:    br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
7327 // CHECK7:       cond.true:
7328 // CHECK7-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
7329 // CHECK7-NEXT:    br label [[COND_END:%.*]]
7330 // CHECK7:       cond.false:
7331 // CHECK7-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
7332 // CHECK7-NEXT:    br label [[COND_END]]
7333 // CHECK7:       cond.end:
7334 // CHECK7-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ]
7335 // CHECK7-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
7336 // CHECK7-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
7337 // CHECK7-NEXT:    store i32 [[TMP15]], ptr [[DOTOMP_IV]], align 4
7338 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
7339 // CHECK7:       omp.inner.for.cond:
7340 // CHECK7-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45:![0-9]+]]
7341 // CHECK7-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP45]]
7342 // CHECK7-NEXT:    [[ADD7:%.*]] = add i32 [[TMP17]], 1
7343 // CHECK7-NEXT:    [[CMP8:%.*]] = icmp ult i32 [[TMP16]], [[ADD7]]
7344 // CHECK7-NEXT:    br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
7345 // CHECK7:       omp.inner.for.body:
7346 // CHECK7-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group [[ACC_GRP45]]
7347 // CHECK7-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]]
7348 // CHECK7-NEXT:    [[MUL:%.*]] = mul i32 [[TMP19]], 1
7349 // CHECK7-NEXT:    [[ADD9:%.*]] = add i32 [[TMP18]], [[MUL]]
7350 // CHECK7-NEXT:    store i32 [[ADD9]], ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP45]]
7351 // CHECK7-NEXT:    [[TMP20:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP45]]
7352 // CHECK7-NEXT:    [[ADD10:%.*]] = add nsw i32 [[TMP20]], 1
7353 // CHECK7-NEXT:    store i32 [[ADD10]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP45]]
7354 // CHECK7-NEXT:    [[TMP21:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP45]]
7355 // CHECK7-NEXT:    [[CONV:%.*]] = sext i16 [[TMP21]] to i32
7356 // CHECK7-NEXT:    [[ADD11:%.*]] = add nsw i32 [[CONV]], 1
7357 // CHECK7-NEXT:    [[CONV12:%.*]] = trunc i32 [[ADD11]] to i16
7358 // CHECK7-NEXT:    store i16 [[CONV12]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP45]]
7359 // CHECK7-NEXT:    [[TMP22:%.*]] = load i8, ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP45]]
7360 // CHECK7-NEXT:    [[CONV13:%.*]] = sext i8 [[TMP22]] to i32
7361 // CHECK7-NEXT:    [[ADD14:%.*]] = add nsw i32 [[CONV13]], 1
7362 // CHECK7-NEXT:    [[CONV15:%.*]] = trunc i32 [[ADD14]] to i8
7363 // CHECK7-NEXT:    store i8 [[CONV15]], ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP45]]
7364 // CHECK7-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2
7365 // CHECK7-NEXT:    [[TMP23:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP45]]
7366 // CHECK7-NEXT:    [[ADD16:%.*]] = add nsw i32 [[TMP23]], 1
7367 // CHECK7-NEXT:    store i32 [[ADD16]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP45]]
7368 // CHECK7-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
7369 // CHECK7:       omp.body.continue:
7370 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
7371 // CHECK7:       omp.inner.for.inc:
7372 // CHECK7-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]]
7373 // CHECK7-NEXT:    [[ADD17:%.*]] = add i32 [[TMP24]], 1
7374 // CHECK7-NEXT:    store i32 [[ADD17]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP45]]
7375 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]]
7376 // CHECK7:       omp.inner.for.end:
7377 // CHECK7-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
7378 // CHECK7:       omp.loop.exit:
7379 // CHECK7-NEXT:    [[TMP25:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
7380 // CHECK7-NEXT:    [[TMP26:%.*]] = load i32, ptr [[TMP25]], align 4
7381 // CHECK7-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP26]])
7382 // CHECK7-NEXT:    [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
7383 // CHECK7-NEXT:    [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
7384 // CHECK7-NEXT:    br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
7385 // CHECK7:       .omp.final.then:
7386 // CHECK7-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
7387 // CHECK7-NEXT:    [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
7388 // CHECK7-NEXT:    [[TMP31:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
7389 // CHECK7-NEXT:    [[SUB18:%.*]] = sub i32 [[TMP30]], [[TMP31]]
7390 // CHECK7-NEXT:    [[SUB19:%.*]] = sub i32 [[SUB18]], 1
7391 // CHECK7-NEXT:    [[ADD20:%.*]] = add i32 [[SUB19]], 1
7392 // CHECK7-NEXT:    [[DIV21:%.*]] = udiv i32 [[ADD20]], 1
7393 // CHECK7-NEXT:    [[MUL22:%.*]] = mul i32 [[DIV21]], 1
7394 // CHECK7-NEXT:    [[ADD23:%.*]] = add i32 [[TMP29]], [[MUL22]]
7395 // CHECK7-NEXT:    store i32 [[ADD23]], ptr [[I5]], align 4
7396 // CHECK7-NEXT:    br label [[DOTOMP_FINAL_DONE]]
7397 // CHECK7:       .omp.final.done:
7398 // CHECK7-NEXT:    br label [[OMP_PRECOND_END]]
7399 // CHECK7:       omp.precond.end:
7400 // CHECK7-NEXT:    ret void
7401 //
7402 //
7403 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180
7404 // CHECK7-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
7405 // CHECK7-NEXT:  entry:
7406 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
7407 // CHECK7-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
7408 // CHECK7-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
7409 // CHECK7-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
7410 // CHECK7-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
7411 // CHECK7-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
7412 // CHECK7-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
7413 // CHECK7-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
7414 // CHECK7-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
7415 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
7416 // CHECK7-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 4
7417 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4
7418 // CHECK7-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
7419 // CHECK7-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
7420 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4
7421 // CHECK7-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], ptr [[TMP0]])
7422 // CHECK7-NEXT:    ret void
7423 //
7424 //
7425 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.omp_outlined
7426 // CHECK7-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
7427 // CHECK7-NEXT:  entry:
7428 // CHECK7-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
7429 // CHECK7-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
7430 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
7431 // CHECK7-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
7432 // CHECK7-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
7433 // CHECK7-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
7434 // CHECK7-NEXT:    [[TMP:%.*]] = alloca i32, align 4
7435 // CHECK7-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
7436 // CHECK7-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
7437 // CHECK7-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
7438 // CHECK7-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
7439 // CHECK7-NEXT:    [[I:%.*]] = alloca i32, align 4
7440 // CHECK7-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
7441 // CHECK7-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
7442 // CHECK7-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
7443 // CHECK7-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
7444 // CHECK7-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
7445 // CHECK7-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
7446 // CHECK7-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
7447 // CHECK7-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4
7448 // CHECK7-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
7449 // CHECK7-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
7450 // CHECK7-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
7451 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
7452 // CHECK7-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
7453 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
7454 // CHECK7-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
7455 // CHECK7-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
7456 // CHECK7:       cond.true:
7457 // CHECK7-NEXT:    br label [[COND_END:%.*]]
7458 // CHECK7:       cond.false:
7459 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
7460 // CHECK7-NEXT:    br label [[COND_END]]
7461 // CHECK7:       cond.end:
7462 // CHECK7-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
7463 // CHECK7-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
7464 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
7465 // CHECK7-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
7466 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
7467 // CHECK7:       omp.inner.for.cond:
7468 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP48:![0-9]+]]
7469 // CHECK7-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP48]]
7470 // CHECK7-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
7471 // CHECK7-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
7472 // CHECK7:       omp.inner.for.body:
7473 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP48]]
7474 // CHECK7-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
7475 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
7476 // CHECK7-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP48]]
7477 // CHECK7-NEXT:    [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP48]]
7478 // CHECK7-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
7479 // CHECK7-NEXT:    store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP48]]
7480 // CHECK7-NEXT:    [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP48]]
7481 // CHECK7-NEXT:    [[CONV:%.*]] = sext i16 [[TMP10]] to i32
7482 // CHECK7-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV]], 1
7483 // CHECK7-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
7484 // CHECK7-NEXT:    store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP48]]
7485 // CHECK7-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2
7486 // CHECK7-NEXT:    [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP48]]
7487 // CHECK7-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1
7488 // CHECK7-NEXT:    store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP48]]
7489 // CHECK7-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
7490 // CHECK7:       omp.body.continue:
7491 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
7492 // CHECK7:       omp.inner.for.inc:
7493 // CHECK7-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP48]]
7494 // CHECK7-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP12]], 1
7495 // CHECK7-NEXT:    store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP48]]
7496 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP49:![0-9]+]]
7497 // CHECK7:       omp.inner.for.end:
7498 // CHECK7-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
7499 // CHECK7:       omp.loop.exit:
7500 // CHECK7-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])
7501 // CHECK7-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
7502 // CHECK7-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
7503 // CHECK7-NEXT:    br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
7504 // CHECK7:       .omp.final.then:
7505 // CHECK7-NEXT:    store i32 10, ptr [[I]], align 4
7506 // CHECK7-NEXT:    br label [[DOTOMP_FINAL_DONE]]
7507 // CHECK7:       .omp.final.done:
7508 // CHECK7-NEXT:    ret void
7509 //
7510 //
7511 // CHECK7-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
7512 // CHECK7-SAME: () #[[ATTR4]] {
7513 // CHECK7-NEXT:  entry:
7514 // CHECK7-NEXT:    call void @__tgt_register_requires(i64 1)
7515 // CHECK7-NEXT:    ret void
7516 //
7517 //
7518 // CHECK9-LABEL: define {{[^@]+}}@_Z3fooi
7519 // CHECK9-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
7520 // CHECK9-NEXT:  entry:
7521 // CHECK9-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7522 // CHECK9-NEXT:    [[A:%.*]] = alloca i32, align 4
7523 // CHECK9-NEXT:    [[AA:%.*]] = alloca i16, align 2
7524 // CHECK9-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
7525 // CHECK9-NEXT:    [[SAVED_STACK:%.*]] = alloca ptr, align 8
7526 // CHECK9-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
7527 // CHECK9-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
7528 // CHECK9-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
7529 // CHECK9-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
7530 // CHECK9-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
7531 // CHECK9-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
7532 // CHECK9-NEXT:    [[TMP:%.*]] = alloca i32, align 4
7533 // CHECK9-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
7534 // CHECK9-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
7535 // CHECK9-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
7536 // CHECK9-NEXT:    [[I:%.*]] = alloca i32, align 4
7537 // CHECK9-NEXT:    [[_TMP4:%.*]] = alloca i32, align 4
7538 // CHECK9-NEXT:    [[DOTOMP_LB5:%.*]] = alloca i32, align 4
7539 // CHECK9-NEXT:    [[DOTOMP_UB6:%.*]] = alloca i32, align 4
7540 // CHECK9-NEXT:    [[DOTOMP_IV7:%.*]] = alloca i32, align 4
7541 // CHECK9-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i32, align 4
7542 // CHECK9-NEXT:    [[A8:%.*]] = alloca i32, align 4
7543 // CHECK9-NEXT:    [[A9:%.*]] = alloca i32, align 4
7544 // CHECK9-NEXT:    [[_TMP20:%.*]] = alloca i32, align 4
7545 // CHECK9-NEXT:    [[DOTOMP_LB21:%.*]] = alloca i32, align 4
7546 // CHECK9-NEXT:    [[DOTOMP_UB22:%.*]] = alloca i32, align 4
7547 // CHECK9-NEXT:    [[DOTOMP_IV23:%.*]] = alloca i32, align 4
7548 // CHECK9-NEXT:    [[I24:%.*]] = alloca i32, align 4
7549 // CHECK9-NEXT:    [[_TMP36:%.*]] = alloca i32, align 4
7550 // CHECK9-NEXT:    [[DOTOMP_LB37:%.*]] = alloca i32, align 4
7551 // CHECK9-NEXT:    [[DOTOMP_UB38:%.*]] = alloca i32, align 4
7552 // CHECK9-NEXT:    [[DOTOMP_IV39:%.*]] = alloca i32, align 4
7553 // CHECK9-NEXT:    [[I40:%.*]] = alloca i32, align 4
7554 // CHECK9-NEXT:    [[_TMP54:%.*]] = alloca i32, align 4
7555 // CHECK9-NEXT:    [[DOTOMP_LB55:%.*]] = alloca i32, align 4
7556 // CHECK9-NEXT:    [[DOTOMP_UB56:%.*]] = alloca i32, align 4
7557 // CHECK9-NEXT:    [[DOTOMP_IV57:%.*]] = alloca i32, align 4
7558 // CHECK9-NEXT:    [[I58:%.*]] = alloca i32, align 4
7559 // CHECK9-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
7560 // CHECK9-NEXT:    store i32 0, ptr [[A]], align 4
7561 // CHECK9-NEXT:    store i16 0, ptr [[AA]], align 2
7562 // CHECK9-NEXT:    [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
7563 // CHECK9-NEXT:    [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
7564 // CHECK9-NEXT:    [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
7565 // CHECK9-NEXT:    store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
7566 // CHECK9-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
7567 // CHECK9-NEXT:    store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
7568 // CHECK9-NEXT:    [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4
7569 // CHECK9-NEXT:    [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
7570 // CHECK9-NEXT:    [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]
7571 // CHECK9-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8
7572 // CHECK9-NEXT:    store i64 [[TMP4]], ptr [[__VLA_EXPR1]], align 8
7573 // CHECK9-NEXT:    [[TMP6:%.*]] = load i32, ptr [[A]], align 4
7574 // CHECK9-NEXT:    store i32 [[TMP6]], ptr [[DOTCAPTURE_EXPR_]], align 4
7575 // CHECK9-NEXT:    [[TMP7:%.*]] = load i32, ptr [[A]], align 4
7576 // CHECK9-NEXT:    store i32 [[TMP7]], ptr [[DOTCAPTURE_EXPR_2]], align 4
7577 // CHECK9-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
7578 // CHECK9-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4
7579 // CHECK9-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
7580 // CHECK9-NEXT:    store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4
7581 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
7582 // CHECK9:       omp.inner.for.cond:
7583 // CHECK9-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]]
7584 // CHECK9-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP2]]
7585 // CHECK9-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
7586 // CHECK9-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
7587 // CHECK9:       omp.inner.for.body:
7588 // CHECK9-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
7589 // CHECK9-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
7590 // CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
7591 // CHECK9-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]
7592 // CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
7593 // CHECK9:       omp.body.continue:
7594 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
7595 // CHECK9:       omp.inner.for.inc:
7596 // CHECK9-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
7597 // CHECK9-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
7598 // CHECK9-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
7599 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
7600 // CHECK9:       omp.inner.for.end:
7601 // CHECK9-NEXT:    store i32 10, ptr [[I]], align 4
7602 // CHECK9-NEXT:    store i32 0, ptr [[DOTOMP_LB5]], align 4
7603 // CHECK9-NEXT:    store i32 9, ptr [[DOTOMP_UB6]], align 4
7604 // CHECK9-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB5]], align 4
7605 // CHECK9-NEXT:    store i32 [[TMP13]], ptr [[DOTOMP_IV7]], align 4
7606 // CHECK9-NEXT:    [[TMP14:%.*]] = load i32, ptr [[A]], align 4
7607 // CHECK9-NEXT:    store i32 [[TMP14]], ptr [[DOTLINEAR_START]], align 4
7608 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND10:%.*]]
7609 // CHECK9:       omp.inner.for.cond10:
7610 // CHECK9-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV7]], align 4
7611 // CHECK9-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_UB6]], align 4
7612 // CHECK9-NEXT:    [[CMP11:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
7613 // CHECK9-NEXT:    br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY12:%.*]], label [[OMP_INNER_FOR_END19:%.*]]
7614 // CHECK9:       omp.inner.for.body12:
7615 // CHECK9-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV7]], align 4
7616 // CHECK9-NEXT:    [[MUL13:%.*]] = mul nsw i32 [[TMP17]], 1
7617 // CHECK9-NEXT:    [[ADD14:%.*]] = add nsw i32 0, [[MUL13]]
7618 // CHECK9-NEXT:    store i32 [[ADD14]], ptr [[A8]], align 4
7619 // CHECK9-NEXT:    [[TMP18:%.*]] = load i32, ptr [[A8]], align 4
7620 // CHECK9-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP18]], 1
7621 // CHECK9-NEXT:    store i32 [[ADD15]], ptr [[A8]], align 4
7622 // CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE16:%.*]]
7623 // CHECK9:       omp.body.continue16:
7624 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC17:%.*]]
7625 // CHECK9:       omp.inner.for.inc17:
7626 // CHECK9-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV7]], align 4
7627 // CHECK9-NEXT:    [[ADD18:%.*]] = add nsw i32 [[TMP19]], 1
7628 // CHECK9-NEXT:    store i32 [[ADD18]], ptr [[DOTOMP_IV7]], align 4
7629 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP7:![0-9]+]]
7630 // CHECK9:       omp.inner.for.end19:
7631 // CHECK9-NEXT:    store i32 10, ptr [[A]], align 4
7632 // CHECK9-NEXT:    store i32 0, ptr [[DOTOMP_LB21]], align 4
7633 // CHECK9-NEXT:    store i32 9, ptr [[DOTOMP_UB22]], align 4
7634 // CHECK9-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTOMP_LB21]], align 4
7635 // CHECK9-NEXT:    store i32 [[TMP20]], ptr [[DOTOMP_IV23]], align 4
7636 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND25:%.*]]
7637 // CHECK9:       omp.inner.for.cond25:
7638 // CHECK9-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IV23]], align 4, !llvm.access.group [[ACC_GRP9:![0-9]+]]
7639 // CHECK9-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTOMP_UB22]], align 4, !llvm.access.group [[ACC_GRP9]]
7640 // CHECK9-NEXT:    [[CMP26:%.*]] = icmp sle i32 [[TMP21]], [[TMP22]]
7641 // CHECK9-NEXT:    br i1 [[CMP26]], label [[OMP_INNER_FOR_BODY27:%.*]], label [[OMP_INNER_FOR_END35:%.*]]
7642 // CHECK9:       omp.inner.for.body27:
7643 // CHECK9-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV23]], align 4, !llvm.access.group [[ACC_GRP9]]
7644 // CHECK9-NEXT:    [[MUL28:%.*]] = mul nsw i32 [[TMP23]], 1
7645 // CHECK9-NEXT:    [[ADD29:%.*]] = add nsw i32 0, [[MUL28]]
7646 // CHECK9-NEXT:    store i32 [[ADD29]], ptr [[I24]], align 4, !llvm.access.group [[ACC_GRP9]]
7647 // CHECK9-NEXT:    [[TMP24:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP9]]
7648 // CHECK9-NEXT:    [[CONV:%.*]] = sext i16 [[TMP24]] to i32
7649 // CHECK9-NEXT:    [[ADD30:%.*]] = add nsw i32 [[CONV]], 1
7650 // CHECK9-NEXT:    [[CONV31:%.*]] = trunc i32 [[ADD30]] to i16
7651 // CHECK9-NEXT:    store i16 [[CONV31]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP9]]
7652 // CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE32:%.*]]
7653 // CHECK9:       omp.body.continue32:
7654 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC33:%.*]]
7655 // CHECK9:       omp.inner.for.inc33:
7656 // CHECK9-NEXT:    [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV23]], align 4, !llvm.access.group [[ACC_GRP9]]
7657 // CHECK9-NEXT:    [[ADD34:%.*]] = add nsw i32 [[TMP25]], 1
7658 // CHECK9-NEXT:    store i32 [[ADD34]], ptr [[DOTOMP_IV23]], align 4, !llvm.access.group [[ACC_GRP9]]
7659 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND25]], !llvm.loop [[LOOP10:![0-9]+]]
7660 // CHECK9:       omp.inner.for.end35:
7661 // CHECK9-NEXT:    store i32 10, ptr [[I24]], align 4
7662 // CHECK9-NEXT:    store i32 0, ptr [[DOTOMP_LB37]], align 4
7663 // CHECK9-NEXT:    store i32 9, ptr [[DOTOMP_UB38]], align 4
7664 // CHECK9-NEXT:    [[TMP26:%.*]] = load i32, ptr [[DOTOMP_LB37]], align 4
7665 // CHECK9-NEXT:    store i32 [[TMP26]], ptr [[DOTOMP_IV39]], align 4
7666 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND41:%.*]]
7667 // CHECK9:       omp.inner.for.cond41:
7668 // CHECK9-NEXT:    [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV39]], align 4, !llvm.access.group [[ACC_GRP12:![0-9]+]]
7669 // CHECK9-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTOMP_UB38]], align 4, !llvm.access.group [[ACC_GRP12]]
7670 // CHECK9-NEXT:    [[CMP42:%.*]] = icmp sle i32 [[TMP27]], [[TMP28]]
7671 // CHECK9-NEXT:    br i1 [[CMP42]], label [[OMP_INNER_FOR_BODY43:%.*]], label [[OMP_INNER_FOR_END53:%.*]]
7672 // CHECK9:       omp.inner.for.body43:
7673 // CHECK9-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IV39]], align 4, !llvm.access.group [[ACC_GRP12]]
7674 // CHECK9-NEXT:    [[MUL44:%.*]] = mul nsw i32 [[TMP29]], 1
7675 // CHECK9-NEXT:    [[ADD45:%.*]] = add nsw i32 0, [[MUL44]]
7676 // CHECK9-NEXT:    store i32 [[ADD45]], ptr [[I40]], align 4, !llvm.access.group [[ACC_GRP12]]
7677 // CHECK9-NEXT:    [[TMP30:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP12]]
7678 // CHECK9-NEXT:    [[ADD46:%.*]] = add nsw i32 [[TMP30]], 1
7679 // CHECK9-NEXT:    store i32 [[ADD46]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP12]]
7680 // CHECK9-NEXT:    [[TMP31:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP12]]
7681 // CHECK9-NEXT:    [[CONV47:%.*]] = sext i16 [[TMP31]] to i32
7682 // CHECK9-NEXT:    [[ADD48:%.*]] = add nsw i32 [[CONV47]], 1
7683 // CHECK9-NEXT:    [[CONV49:%.*]] = trunc i32 [[ADD48]] to i16
7684 // CHECK9-NEXT:    store i16 [[CONV49]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP12]]
7685 // CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE50:%.*]]
7686 // CHECK9:       omp.body.continue50:
7687 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC51:%.*]]
7688 // CHECK9:       omp.inner.for.inc51:
7689 // CHECK9-NEXT:    [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IV39]], align 4, !llvm.access.group [[ACC_GRP12]]
7690 // CHECK9-NEXT:    [[ADD52:%.*]] = add nsw i32 [[TMP32]], 1
7691 // CHECK9-NEXT:    store i32 [[ADD52]], ptr [[DOTOMP_IV39]], align 4, !llvm.access.group [[ACC_GRP12]]
7692 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND41]], !llvm.loop [[LOOP13:![0-9]+]]
7693 // CHECK9:       omp.inner.for.end53:
7694 // CHECK9-NEXT:    store i32 10, ptr [[I40]], align 4
7695 // CHECK9-NEXT:    store i32 0, ptr [[DOTOMP_LB55]], align 4
7696 // CHECK9-NEXT:    store i32 9, ptr [[DOTOMP_UB56]], align 4
7697 // CHECK9-NEXT:    [[TMP33:%.*]] = load i32, ptr [[DOTOMP_LB55]], align 4
7698 // CHECK9-NEXT:    store i32 [[TMP33]], ptr [[DOTOMP_IV57]], align 4
7699 // CHECK9-NEXT:    [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], ptr [[B]], i64 0, i64 0
7700 // CHECK9-NEXT:    call void @llvm.assume(i1 true) [ "align"(ptr [[ARRAYDECAY]], i64 16) ]
7701 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND59:%.*]]
7702 // CHECK9:       omp.inner.for.cond59:
7703 // CHECK9-NEXT:    [[TMP34:%.*]] = load i32, ptr [[DOTOMP_IV57]], align 4, !llvm.access.group [[ACC_GRP15:![0-9]+]]
7704 // CHECK9-NEXT:    [[TMP35:%.*]] = load i32, ptr [[DOTOMP_UB56]], align 4, !llvm.access.group [[ACC_GRP15]]
7705 // CHECK9-NEXT:    [[CMP60:%.*]] = icmp sle i32 [[TMP34]], [[TMP35]]
7706 // CHECK9-NEXT:    br i1 [[CMP60]], label [[OMP_INNER_FOR_BODY61:%.*]], label [[OMP_INNER_FOR_END85:%.*]]
7707 // CHECK9:       omp.inner.for.body61:
7708 // CHECK9-NEXT:    [[TMP36:%.*]] = load i32, ptr [[DOTOMP_IV57]], align 4, !llvm.access.group [[ACC_GRP15]]
7709 // CHECK9-NEXT:    [[MUL62:%.*]] = mul nsw i32 [[TMP36]], 1
7710 // CHECK9-NEXT:    [[ADD63:%.*]] = add nsw i32 0, [[MUL62]]
7711 // CHECK9-NEXT:    store i32 [[ADD63]], ptr [[I58]], align 4, !llvm.access.group [[ACC_GRP15]]
7712 // CHECK9-NEXT:    [[TMP37:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP15]]
7713 // CHECK9-NEXT:    [[ADD64:%.*]] = add nsw i32 [[TMP37]], 1
7714 // CHECK9-NEXT:    store i32 [[ADD64]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP15]]
7715 // CHECK9-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B]], i64 0, i64 2
7716 // CHECK9-NEXT:    [[TMP38:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP15]]
7717 // CHECK9-NEXT:    [[CONV65:%.*]] = fpext float [[TMP38]] to double
7718 // CHECK9-NEXT:    [[ADD66:%.*]] = fadd double [[CONV65]], 1.000000e+00
7719 // CHECK9-NEXT:    [[CONV67:%.*]] = fptrunc double [[ADD66]] to float
7720 // CHECK9-NEXT:    store float [[CONV67]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP15]]
7721 // CHECK9-NEXT:    [[ARRAYIDX68:%.*]] = getelementptr inbounds float, ptr [[VLA]], i64 3
7722 // CHECK9-NEXT:    [[TMP39:%.*]] = load float, ptr [[ARRAYIDX68]], align 4, !llvm.access.group [[ACC_GRP15]]
7723 // CHECK9-NEXT:    [[CONV69:%.*]] = fpext float [[TMP39]] to double
7724 // CHECK9-NEXT:    [[ADD70:%.*]] = fadd double [[CONV69]], 1.000000e+00
7725 // CHECK9-NEXT:    [[CONV71:%.*]] = fptrunc double [[ADD70]] to float
7726 // CHECK9-NEXT:    store float [[CONV71]], ptr [[ARRAYIDX68]], align 4, !llvm.access.group [[ACC_GRP15]]
7727 // CHECK9-NEXT:    [[ARRAYIDX72:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C]], i64 0, i64 1
7728 // CHECK9-NEXT:    [[ARRAYIDX73:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX72]], i64 0, i64 2
7729 // CHECK9-NEXT:    [[TMP40:%.*]] = load double, ptr [[ARRAYIDX73]], align 8, !llvm.access.group [[ACC_GRP15]]
7730 // CHECK9-NEXT:    [[ADD74:%.*]] = fadd double [[TMP40]], 1.000000e+00
7731 // CHECK9-NEXT:    store double [[ADD74]], ptr [[ARRAYIDX73]], align 8, !llvm.access.group [[ACC_GRP15]]
7732 // CHECK9-NEXT:    [[TMP41:%.*]] = mul nsw i64 1, [[TMP4]]
7733 // CHECK9-NEXT:    [[ARRAYIDX75:%.*]] = getelementptr inbounds double, ptr [[VLA1]], i64 [[TMP41]]
7734 // CHECK9-NEXT:    [[ARRAYIDX76:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX75]], i64 3
7735 // CHECK9-NEXT:    [[TMP42:%.*]] = load double, ptr [[ARRAYIDX76]], align 8, !llvm.access.group [[ACC_GRP15]]
7736 // CHECK9-NEXT:    [[ADD77:%.*]] = fadd double [[TMP42]], 1.000000e+00
7737 // CHECK9-NEXT:    store double [[ADD77]], ptr [[ARRAYIDX76]], align 8, !llvm.access.group [[ACC_GRP15]]
7738 // CHECK9-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D]], i32 0, i32 0
7739 // CHECK9-NEXT:    [[TMP43:%.*]] = load i64, ptr [[X]], align 8, !llvm.access.group [[ACC_GRP15]]
7740 // CHECK9-NEXT:    [[ADD78:%.*]] = add nsw i64 [[TMP43]], 1
7741 // CHECK9-NEXT:    store i64 [[ADD78]], ptr [[X]], align 8, !llvm.access.group [[ACC_GRP15]]
7742 // CHECK9-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D]], i32 0, i32 1
7743 // CHECK9-NEXT:    [[TMP44:%.*]] = load i8, ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP15]]
7744 // CHECK9-NEXT:    [[CONV79:%.*]] = sext i8 [[TMP44]] to i32
7745 // CHECK9-NEXT:    [[ADD80:%.*]] = add nsw i32 [[CONV79]], 1
7746 // CHECK9-NEXT:    [[CONV81:%.*]] = trunc i32 [[ADD80]] to i8
7747 // CHECK9-NEXT:    store i8 [[CONV81]], ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP15]]
7748 // CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE82:%.*]]
7749 // CHECK9:       omp.body.continue82:
7750 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC83:%.*]]
7751 // CHECK9:       omp.inner.for.inc83:
7752 // CHECK9-NEXT:    [[TMP45:%.*]] = load i32, ptr [[DOTOMP_IV57]], align 4, !llvm.access.group [[ACC_GRP15]]
7753 // CHECK9-NEXT:    [[ADD84:%.*]] = add nsw i32 [[TMP45]], 1
7754 // CHECK9-NEXT:    store i32 [[ADD84]], ptr [[DOTOMP_IV57]], align 4, !llvm.access.group [[ACC_GRP15]]
7755 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND59]], !llvm.loop [[LOOP16:![0-9]+]]
7756 // CHECK9:       omp.inner.for.end85:
7757 // CHECK9-NEXT:    store i32 10, ptr [[I58]], align 4
7758 // CHECK9-NEXT:    [[TMP46:%.*]] = load i32, ptr [[A]], align 4
7759 // CHECK9-NEXT:    [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
7760 // CHECK9-NEXT:    call void @llvm.stackrestore.p0(ptr [[TMP47]])
7761 // CHECK9-NEXT:    ret i32 [[TMP46]]
7762 //
7763 //
7764 // CHECK9-LABEL: define {{[^@]+}}@_Z3bari
7765 // CHECK9-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
7766 // CHECK9-NEXT:  entry:
7767 // CHECK9-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7768 // CHECK9-NEXT:    [[A:%.*]] = alloca i32, align 4
7769 // CHECK9-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
7770 // CHECK9-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
7771 // CHECK9-NEXT:    store i32 0, ptr [[A]], align 4
7772 // CHECK9-NEXT:    [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
7773 // CHECK9-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]])
7774 // CHECK9-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A]], align 4
7775 // CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
7776 // CHECK9-NEXT:    store i32 [[ADD]], ptr [[A]], align 4
7777 // CHECK9-NEXT:    [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
7778 // CHECK9-NEXT:    [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(ptr noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]])
7779 // CHECK9-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A]], align 4
7780 // CHECK9-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
7781 // CHECK9-NEXT:    store i32 [[ADD2]], ptr [[A]], align 4
7782 // CHECK9-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
7783 // CHECK9-NEXT:    [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]])
7784 // CHECK9-NEXT:    [[TMP5:%.*]] = load i32, ptr [[A]], align 4
7785 // CHECK9-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
7786 // CHECK9-NEXT:    store i32 [[ADD4]], ptr [[A]], align 4
7787 // CHECK9-NEXT:    [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4
7788 // CHECK9-NEXT:    [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]])
7789 // CHECK9-NEXT:    [[TMP7:%.*]] = load i32, ptr [[A]], align 4
7790 // CHECK9-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
7791 // CHECK9-NEXT:    store i32 [[ADD6]], ptr [[A]], align 4
7792 // CHECK9-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A]], align 4
7793 // CHECK9-NEXT:    ret i32 [[TMP8]]
7794 //
7795 //
7796 // CHECK9-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
7797 // CHECK9-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
7798 // CHECK9-NEXT:  entry:
7799 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
7800 // CHECK9-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7801 // CHECK9-NEXT:    [[B:%.*]] = alloca i32, align 4
7802 // CHECK9-NEXT:    [[SAVED_STACK:%.*]] = alloca ptr, align 8
7803 // CHECK9-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
7804 // CHECK9-NEXT:    [[TMP:%.*]] = alloca i32, align 4
7805 // CHECK9-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
7806 // CHECK9-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
7807 // CHECK9-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
7808 // CHECK9-NEXT:    [[I:%.*]] = alloca i32, align 4
7809 // CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
7810 // CHECK9-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
7811 // CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
7812 // CHECK9-NEXT:    [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
7813 // CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
7814 // CHECK9-NEXT:    store i32 [[ADD]], ptr [[B]], align 4
7815 // CHECK9-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
7816 // CHECK9-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
7817 // CHECK9-NEXT:    [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()
7818 // CHECK9-NEXT:    store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8
7819 // CHECK9-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
7820 // CHECK9-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
7821 // CHECK9-NEXT:    store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8
7822 // CHECK9-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
7823 // CHECK9-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4
7824 // CHECK9-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
7825 // CHECK9-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
7826 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
7827 // CHECK9:       omp.inner.for.cond:
7828 // CHECK9-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18:![0-9]+]]
7829 // CHECK9-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP18]]
7830 // CHECK9-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
7831 // CHECK9-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
7832 // CHECK9:       omp.inner.for.body:
7833 // CHECK9-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]]
7834 // CHECK9-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
7835 // CHECK9-NEXT:    [[ADD2:%.*]] = add nsw i32 0, [[MUL]]
7836 // CHECK9-NEXT:    store i32 [[ADD2]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]]
7837 // CHECK9-NEXT:    [[TMP9:%.*]] = load i32, ptr [[B]], align 4, !llvm.access.group [[ACC_GRP18]]
7838 // CHECK9-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP9]] to double
7839 // CHECK9-NEXT:    [[ADD3:%.*]] = fadd double [[CONV]], 1.500000e+00
7840 // CHECK9-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0
7841 // CHECK9-NEXT:    store double [[ADD3]], ptr [[A]], align 8, !llvm.access.group [[ACC_GRP18]]
7842 // CHECK9-NEXT:    [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[THIS1]], i32 0, i32 0
7843 // CHECK9-NEXT:    [[TMP10:%.*]] = load double, ptr [[A4]], align 8, !llvm.access.group [[ACC_GRP18]]
7844 // CHECK9-NEXT:    [[INC:%.*]] = fadd double [[TMP10]], 1.000000e+00
7845 // CHECK9-NEXT:    store double [[INC]], ptr [[A4]], align 8, !llvm.access.group [[ACC_GRP18]]
7846 // CHECK9-NEXT:    [[CONV5:%.*]] = fptosi double [[INC]] to i16
7847 // CHECK9-NEXT:    [[TMP11:%.*]] = mul nsw i64 1, [[TMP2]]
7848 // CHECK9-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP11]]
7849 // CHECK9-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1
7850 // CHECK9-NEXT:    store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2, !llvm.access.group [[ACC_GRP18]]
7851 // CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
7852 // CHECK9:       omp.body.continue:
7853 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
7854 // CHECK9:       omp.inner.for.inc:
7855 // CHECK9-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]]
7856 // CHECK9-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP12]], 1
7857 // CHECK9-NEXT:    store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]]
7858 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
7859 // CHECK9:       omp.inner.for.end:
7860 // CHECK9-NEXT:    store i32 10, ptr [[I]], align 4
7861 // CHECK9-NEXT:    [[TMP13:%.*]] = mul nsw i64 1, [[TMP2]]
7862 // CHECK9-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP13]]
7863 // CHECK9-NEXT:    [[ARRAYIDX9:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX8]], i64 1
7864 // CHECK9-NEXT:    [[TMP14:%.*]] = load i16, ptr [[ARRAYIDX9]], align 2
7865 // CHECK9-NEXT:    [[CONV10:%.*]] = sext i16 [[TMP14]] to i32
7866 // CHECK9-NEXT:    [[TMP15:%.*]] = load i32, ptr [[B]], align 4
7867 // CHECK9-NEXT:    [[ADD11:%.*]] = add nsw i32 [[CONV10]], [[TMP15]]
7868 // CHECK9-NEXT:    [[TMP16:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
7869 // CHECK9-NEXT:    call void @llvm.stackrestore.p0(ptr [[TMP16]])
7870 // CHECK9-NEXT:    ret i32 [[ADD11]]
7871 //
7872 //
7873 // CHECK9-LABEL: define {{[^@]+}}@_ZL7fstatici
7874 // CHECK9-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
7875 // CHECK9-NEXT:  entry:
7876 // CHECK9-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7877 // CHECK9-NEXT:    [[A:%.*]] = alloca i32, align 4
7878 // CHECK9-NEXT:    [[AA:%.*]] = alloca i16, align 2
7879 // CHECK9-NEXT:    [[AAA:%.*]] = alloca i8, align 1
7880 // CHECK9-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
7881 // CHECK9-NEXT:    [[TMP:%.*]] = alloca i32, align 4
7882 // CHECK9-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
7883 // CHECK9-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
7884 // CHECK9-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
7885 // CHECK9-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
7886 // CHECK9-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
7887 // CHECK9-NEXT:    [[I:%.*]] = alloca i32, align 4
7888 // CHECK9-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
7889 // CHECK9-NEXT:    [[I5:%.*]] = alloca i32, align 4
7890 // CHECK9-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
7891 // CHECK9-NEXT:    store i32 0, ptr [[A]], align 4
7892 // CHECK9-NEXT:    store i16 0, ptr [[AA]], align 2
7893 // CHECK9-NEXT:    store i8 0, ptr [[AAA]], align 1
7894 // CHECK9-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A]], align 4
7895 // CHECK9-NEXT:    store i32 [[TMP0]], ptr [[DOTCAPTURE_EXPR_]], align 4
7896 // CHECK9-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
7897 // CHECK9-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_1]], align 4
7898 // CHECK9-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
7899 // CHECK9-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
7900 // CHECK9-NEXT:    [[SUB:%.*]] = sub i32 [[TMP2]], [[TMP3]]
7901 // CHECK9-NEXT:    [[SUB3:%.*]] = sub i32 [[SUB]], 1
7902 // CHECK9-NEXT:    [[ADD:%.*]] = add i32 [[SUB3]], 1
7903 // CHECK9-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
7904 // CHECK9-NEXT:    [[SUB4:%.*]] = sub i32 [[DIV]], 1
7905 // CHECK9-NEXT:    store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 4
7906 // CHECK9-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
7907 // CHECK9-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
7908 // CHECK9-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4
7909 // CHECK9-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
7910 // CHECK9-NEXT:    store i32 [[TMP5]], ptr [[I]], align 4
7911 // CHECK9-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
7912 // CHECK9-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
7913 // CHECK9-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
7914 // CHECK9-NEXT:    br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]
7915 // CHECK9:       simd.if.then:
7916 // CHECK9-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
7917 // CHECK9-NEXT:    store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4
7918 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
7919 // CHECK9:       omp.inner.for.cond:
7920 // CHECK9-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21:![0-9]+]]
7921 // CHECK9-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP21]]
7922 // CHECK9-NEXT:    [[ADD6:%.*]] = add i32 [[TMP10]], 1
7923 // CHECK9-NEXT:    [[CMP7:%.*]] = icmp ult i32 [[TMP9]], [[ADD6]]
7924 // CHECK9-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
7925 // CHECK9:       omp.inner.for.body:
7926 // CHECK9-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group [[ACC_GRP21]]
7927 // CHECK9-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]]
7928 // CHECK9-NEXT:    [[MUL:%.*]] = mul i32 [[TMP12]], 1
7929 // CHECK9-NEXT:    [[ADD8:%.*]] = add i32 [[TMP11]], [[MUL]]
7930 // CHECK9-NEXT:    store i32 [[ADD8]], ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP21]]
7931 // CHECK9-NEXT:    [[TMP13:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP21]]
7932 // CHECK9-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1
7933 // CHECK9-NEXT:    store i32 [[ADD9]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP21]]
7934 // CHECK9-NEXT:    [[TMP14:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP21]]
7935 // CHECK9-NEXT:    [[CONV:%.*]] = sext i16 [[TMP14]] to i32
7936 // CHECK9-NEXT:    [[ADD10:%.*]] = add nsw i32 [[CONV]], 1
7937 // CHECK9-NEXT:    [[CONV11:%.*]] = trunc i32 [[ADD10]] to i16
7938 // CHECK9-NEXT:    store i16 [[CONV11]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP21]]
7939 // CHECK9-NEXT:    [[TMP15:%.*]] = load i8, ptr [[AAA]], align 1, !llvm.access.group [[ACC_GRP21]]
7940 // CHECK9-NEXT:    [[CONV12:%.*]] = sext i8 [[TMP15]] to i32
7941 // CHECK9-NEXT:    [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
7942 // CHECK9-NEXT:    [[CONV14:%.*]] = trunc i32 [[ADD13]] to i8
7943 // CHECK9-NEXT:    store i8 [[CONV14]], ptr [[AAA]], align 1, !llvm.access.group [[ACC_GRP21]]
7944 // CHECK9-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i64 0, i64 2
7945 // CHECK9-NEXT:    [[TMP16:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP21]]
7946 // CHECK9-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1
7947 // CHECK9-NEXT:    store i32 [[ADD15]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP21]]
7948 // CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
7949 // CHECK9:       omp.body.continue:
7950 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
7951 // CHECK9:       omp.inner.for.inc:
7952 // CHECK9-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]]
7953 // CHECK9-NEXT:    [[ADD16:%.*]] = add i32 [[TMP17]], 1
7954 // CHECK9-NEXT:    store i32 [[ADD16]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]]
7955 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
7956 // CHECK9:       omp.inner.for.end:
7957 // CHECK9-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
7958 // CHECK9-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
7959 // CHECK9-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
7960 // CHECK9-NEXT:    [[SUB17:%.*]] = sub i32 [[TMP19]], [[TMP20]]
7961 // CHECK9-NEXT:    [[SUB18:%.*]] = sub i32 [[SUB17]], 1
7962 // CHECK9-NEXT:    [[ADD19:%.*]] = add i32 [[SUB18]], 1
7963 // CHECK9-NEXT:    [[DIV20:%.*]] = udiv i32 [[ADD19]], 1
7964 // CHECK9-NEXT:    [[MUL21:%.*]] = mul i32 [[DIV20]], 1
7965 // CHECK9-NEXT:    [[ADD22:%.*]] = add i32 [[TMP18]], [[MUL21]]
7966 // CHECK9-NEXT:    store i32 [[ADD22]], ptr [[I5]], align 4
7967 // CHECK9-NEXT:    br label [[SIMD_IF_END]]
7968 // CHECK9:       simd.if.end:
7969 // CHECK9-NEXT:    [[TMP21:%.*]] = load i32, ptr [[A]], align 4
7970 // CHECK9-NEXT:    ret i32 [[TMP21]]
7971 //
7972 //
7973 // CHECK9-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
7974 // CHECK9-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
7975 // CHECK9-NEXT:  entry:
7976 // CHECK9-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7977 // CHECK9-NEXT:    [[A:%.*]] = alloca i32, align 4
7978 // CHECK9-NEXT:    [[AA:%.*]] = alloca i16, align 2
7979 // CHECK9-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
7980 // CHECK9-NEXT:    [[TMP:%.*]] = alloca i32, align 4
7981 // CHECK9-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
7982 // CHECK9-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
7983 // CHECK9-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
7984 // CHECK9-NEXT:    [[I:%.*]] = alloca i32, align 4
7985 // CHECK9-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
7986 // CHECK9-NEXT:    store i32 0, ptr [[A]], align 4
7987 // CHECK9-NEXT:    store i16 0, ptr [[AA]], align 2
7988 // CHECK9-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
7989 // CHECK9-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4
7990 // CHECK9-NEXT:    [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
7991 // CHECK9-NEXT:    store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4
7992 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
7993 // CHECK9:       omp.inner.for.cond:
7994 // CHECK9-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24:![0-9]+]]
7995 // CHECK9-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP24]]
7996 // CHECK9-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
7997 // CHECK9-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
7998 // CHECK9:       omp.inner.for.body:
7999 // CHECK9-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]]
8000 // CHECK9-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
8001 // CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
8002 // CHECK9-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP24]]
8003 // CHECK9-NEXT:    [[TMP4:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP24]]
8004 // CHECK9-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
8005 // CHECK9-NEXT:    store i32 [[ADD1]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP24]]
8006 // CHECK9-NEXT:    [[TMP5:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP24]]
8007 // CHECK9-NEXT:    [[CONV:%.*]] = sext i16 [[TMP5]] to i32
8008 // CHECK9-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
8009 // CHECK9-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
8010 // CHECK9-NEXT:    store i16 [[CONV3]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP24]]
8011 // CHECK9-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i64 0, i64 2
8012 // CHECK9-NEXT:    [[TMP6:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP24]]
8013 // CHECK9-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1
8014 // CHECK9-NEXT:    store i32 [[ADD4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP24]]
8015 // CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
8016 // CHECK9:       omp.body.continue:
8017 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
8018 // CHECK9:       omp.inner.for.inc:
8019 // CHECK9-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]]
8020 // CHECK9-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP7]], 1
8021 // CHECK9-NEXT:    store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]]
8022 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
8023 // CHECK9:       omp.inner.for.end:
8024 // CHECK9-NEXT:    store i32 10, ptr [[I]], align 4
8025 // CHECK9-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A]], align 4
8026 // CHECK9-NEXT:    ret i32 [[TMP8]]
8027 //
8028 //
8029 // CHECK11-LABEL: define {{[^@]+}}@_Z3fooi
8030 // CHECK11-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] {
8031 // CHECK11-NEXT:  entry:
8032 // CHECK11-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
8033 // CHECK11-NEXT:    [[A:%.*]] = alloca i32, align 4
8034 // CHECK11-NEXT:    [[AA:%.*]] = alloca i16, align 2
8035 // CHECK11-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
8036 // CHECK11-NEXT:    [[SAVED_STACK:%.*]] = alloca ptr, align 4
8037 // CHECK11-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
8038 // CHECK11-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
8039 // CHECK11-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
8040 // CHECK11-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
8041 // CHECK11-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
8042 // CHECK11-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
8043 // CHECK11-NEXT:    [[TMP:%.*]] = alloca i32, align 4
8044 // CHECK11-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
8045 // CHECK11-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
8046 // CHECK11-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
8047 // CHECK11-NEXT:    [[I:%.*]] = alloca i32, align 4
8048 // CHECK11-NEXT:    [[_TMP4:%.*]] = alloca i32, align 4
8049 // CHECK11-NEXT:    [[DOTOMP_LB5:%.*]] = alloca i32, align 4
8050 // CHECK11-NEXT:    [[DOTOMP_UB6:%.*]] = alloca i32, align 4
8051 // CHECK11-NEXT:    [[DOTOMP_IV7:%.*]] = alloca i32, align 4
8052 // CHECK11-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i32, align 4
8053 // CHECK11-NEXT:    [[A8:%.*]] = alloca i32, align 4
8054 // CHECK11-NEXT:    [[A9:%.*]] = alloca i32, align 4
8055 // CHECK11-NEXT:    [[_TMP20:%.*]] = alloca i32, align 4
8056 // CHECK11-NEXT:    [[DOTOMP_LB21:%.*]] = alloca i32, align 4
8057 // CHECK11-NEXT:    [[DOTOMP_UB22:%.*]] = alloca i32, align 4
8058 // CHECK11-NEXT:    [[DOTOMP_IV23:%.*]] = alloca i32, align 4
8059 // CHECK11-NEXT:    [[I24:%.*]] = alloca i32, align 4
8060 // CHECK11-NEXT:    [[_TMP36:%.*]] = alloca i32, align 4
8061 // CHECK11-NEXT:    [[DOTOMP_LB37:%.*]] = alloca i32, align 4
8062 // CHECK11-NEXT:    [[DOTOMP_UB38:%.*]] = alloca i32, align 4
8063 // CHECK11-NEXT:    [[DOTOMP_IV39:%.*]] = alloca i32, align 4
8064 // CHECK11-NEXT:    [[I40:%.*]] = alloca i32, align 4
8065 // CHECK11-NEXT:    [[_TMP54:%.*]] = alloca i32, align 4
8066 // CHECK11-NEXT:    [[DOTOMP_LB55:%.*]] = alloca i32, align 4
8067 // CHECK11-NEXT:    [[DOTOMP_UB56:%.*]] = alloca i32, align 4
8068 // CHECK11-NEXT:    [[DOTOMP_IV57:%.*]] = alloca i32, align 4
8069 // CHECK11-NEXT:    [[I58:%.*]] = alloca i32, align 4
8070 // CHECK11-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
8071 // CHECK11-NEXT:    store i32 0, ptr [[A]], align 4
8072 // CHECK11-NEXT:    store i16 0, ptr [[AA]], align 2
8073 // CHECK11-NEXT:    [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
8074 // CHECK11-NEXT:    [[TMP1:%.*]] = call ptr @llvm.stacksave.p0()
8075 // CHECK11-NEXT:    store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4
8076 // CHECK11-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4
8077 // CHECK11-NEXT:    store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4
8078 // CHECK11-NEXT:    [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
8079 // CHECK11-NEXT:    [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]
8080 // CHECK11-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8
8081 // CHECK11-NEXT:    store i32 [[TMP2]], ptr [[__VLA_EXPR1]], align 4
8082 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, ptr [[A]], align 4
8083 // CHECK11-NEXT:    store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 4
8084 // CHECK11-NEXT:    [[TMP5:%.*]] = load i32, ptr [[A]], align 4
8085 // CHECK11-NEXT:    store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_2]], align 4
8086 // CHECK11-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
8087 // CHECK11-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4
8088 // CHECK11-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
8089 // CHECK11-NEXT:    store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4
8090 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
8091 // CHECK11:       omp.inner.for.cond:
8092 // CHECK11-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3:![0-9]+]]
8093 // CHECK11-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP3]]
8094 // CHECK11-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
8095 // CHECK11-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
8096 // CHECK11:       omp.inner.for.body:
8097 // CHECK11-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]
8098 // CHECK11-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
8099 // CHECK11-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
8100 // CHECK11-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]]
8101 // CHECK11-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
8102 // CHECK11:       omp.body.continue:
8103 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
8104 // CHECK11:       omp.inner.for.inc:
8105 // CHECK11-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]
8106 // CHECK11-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
8107 // CHECK11-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]
8108 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
8109 // CHECK11:       omp.inner.for.end:
8110 // CHECK11-NEXT:    store i32 10, ptr [[I]], align 4
8111 // CHECK11-NEXT:    store i32 0, ptr [[DOTOMP_LB5]], align 4
8112 // CHECK11-NEXT:    store i32 9, ptr [[DOTOMP_UB6]], align 4
8113 // CHECK11-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_LB5]], align 4
8114 // CHECK11-NEXT:    store i32 [[TMP11]], ptr [[DOTOMP_IV7]], align 4
8115 // CHECK11-NEXT:    [[TMP12:%.*]] = load i32, ptr [[A]], align 4
8116 // CHECK11-NEXT:    store i32 [[TMP12]], ptr [[DOTLINEAR_START]], align 4
8117 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND10:%.*]]
8118 // CHECK11:       omp.inner.for.cond10:
8119 // CHECK11-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV7]], align 4
8120 // CHECK11-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB6]], align 4
8121 // CHECK11-NEXT:    [[CMP11:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
8122 // CHECK11-NEXT:    br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY12:%.*]], label [[OMP_INNER_FOR_END19:%.*]]
8123 // CHECK11:       omp.inner.for.body12:
8124 // CHECK11-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV7]], align 4
8125 // CHECK11-NEXT:    [[MUL13:%.*]] = mul nsw i32 [[TMP15]], 1
8126 // CHECK11-NEXT:    [[ADD14:%.*]] = add nsw i32 0, [[MUL13]]
8127 // CHECK11-NEXT:    store i32 [[ADD14]], ptr [[A8]], align 4
8128 // CHECK11-NEXT:    [[TMP16:%.*]] = load i32, ptr [[A8]], align 4
8129 // CHECK11-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1
8130 // CHECK11-NEXT:    store i32 [[ADD15]], ptr [[A8]], align 4
8131 // CHECK11-NEXT:    br label [[OMP_BODY_CONTINUE16:%.*]]
8132 // CHECK11:       omp.body.continue16:
8133 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_INC17:%.*]]
8134 // CHECK11:       omp.inner.for.inc17:
8135 // CHECK11-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV7]], align 4
8136 // CHECK11-NEXT:    [[ADD18:%.*]] = add nsw i32 [[TMP17]], 1
8137 // CHECK11-NEXT:    store i32 [[ADD18]], ptr [[DOTOMP_IV7]], align 4
8138 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP8:![0-9]+]]
8139 // CHECK11:       omp.inner.for.end19:
8140 // CHECK11-NEXT:    store i32 10, ptr [[A]], align 4
8141 // CHECK11-NEXT:    store i32 0, ptr [[DOTOMP_LB21]], align 4
8142 // CHECK11-NEXT:    store i32 9, ptr [[DOTOMP_UB22]], align 4
8143 // CHECK11-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_LB21]], align 4
8144 // CHECK11-NEXT:    store i32 [[TMP18]], ptr [[DOTOMP_IV23]], align 4
8145 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND25:%.*]]
8146 // CHECK11:       omp.inner.for.cond25:
8147 // CHECK11-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV23]], align 4, !llvm.access.group [[ACC_GRP10:![0-9]+]]
8148 // CHECK11-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTOMP_UB22]], align 4, !llvm.access.group [[ACC_GRP10]]
8149 // CHECK11-NEXT:    [[CMP26:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]]
8150 // CHECK11-NEXT:    br i1 [[CMP26]], label [[OMP_INNER_FOR_BODY27:%.*]], label [[OMP_INNER_FOR_END35:%.*]]
8151 // CHECK11:       omp.inner.for.body27:
8152 // CHECK11-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IV23]], align 4, !llvm.access.group [[ACC_GRP10]]
8153 // CHECK11-NEXT:    [[MUL28:%.*]] = mul nsw i32 [[TMP21]], 1
8154 // CHECK11-NEXT:    [[ADD29:%.*]] = add nsw i32 0, [[MUL28]]
8155 // CHECK11-NEXT:    store i32 [[ADD29]], ptr [[I24]], align 4, !llvm.access.group [[ACC_GRP10]]
8156 // CHECK11-NEXT:    [[TMP22:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP10]]
8157 // CHECK11-NEXT:    [[CONV:%.*]] = sext i16 [[TMP22]] to i32
8158 // CHECK11-NEXT:    [[ADD30:%.*]] = add nsw i32 [[CONV]], 1
8159 // CHECK11-NEXT:    [[CONV31:%.*]] = trunc i32 [[ADD30]] to i16
8160 // CHECK11-NEXT:    store i16 [[CONV31]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP10]]
8161 // CHECK11-NEXT:    br label [[OMP_BODY_CONTINUE32:%.*]]
8162 // CHECK11:       omp.body.continue32:
8163 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_INC33:%.*]]
8164 // CHECK11:       omp.inner.for.inc33:
8165 // CHECK11-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV23]], align 4, !llvm.access.group [[ACC_GRP10]]
8166 // CHECK11-NEXT:    [[ADD34:%.*]] = add nsw i32 [[TMP23]], 1
8167 // CHECK11-NEXT:    store i32 [[ADD34]], ptr [[DOTOMP_IV23]], align 4, !llvm.access.group [[ACC_GRP10]]
8168 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND25]], !llvm.loop [[LOOP11:![0-9]+]]
8169 // CHECK11:       omp.inner.for.end35:
8170 // CHECK11-NEXT:    store i32 10, ptr [[I24]], align 4
8171 // CHECK11-NEXT:    store i32 0, ptr [[DOTOMP_LB37]], align 4
8172 // CHECK11-NEXT:    store i32 9, ptr [[DOTOMP_UB38]], align 4
8173 // CHECK11-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTOMP_LB37]], align 4
8174 // CHECK11-NEXT:    store i32 [[TMP24]], ptr [[DOTOMP_IV39]], align 4
8175 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND41:%.*]]
8176 // CHECK11:       omp.inner.for.cond41:
8177 // CHECK11-NEXT:    [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV39]], align 4, !llvm.access.group [[ACC_GRP13:![0-9]+]]
8178 // CHECK11-NEXT:    [[TMP26:%.*]] = load i32, ptr [[DOTOMP_UB38]], align 4, !llvm.access.group [[ACC_GRP13]]
8179 // CHECK11-NEXT:    [[CMP42:%.*]] = icmp sle i32 [[TMP25]], [[TMP26]]
8180 // CHECK11-NEXT:    br i1 [[CMP42]], label [[OMP_INNER_FOR_BODY43:%.*]], label [[OMP_INNER_FOR_END53:%.*]]
8181 // CHECK11:       omp.inner.for.body43:
8182 // CHECK11-NEXT:    [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV39]], align 4, !llvm.access.group [[ACC_GRP13]]
8183 // CHECK11-NEXT:    [[MUL44:%.*]] = mul nsw i32 [[TMP27]], 1
8184 // CHECK11-NEXT:    [[ADD45:%.*]] = add nsw i32 0, [[MUL44]]
8185 // CHECK11-NEXT:    store i32 [[ADD45]], ptr [[I40]], align 4, !llvm.access.group [[ACC_GRP13]]
8186 // CHECK11-NEXT:    [[TMP28:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP13]]
8187 // CHECK11-NEXT:    [[ADD46:%.*]] = add nsw i32 [[TMP28]], 1
8188 // CHECK11-NEXT:    store i32 [[ADD46]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP13]]
8189 // CHECK11-NEXT:    [[TMP29:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP13]]
8190 // CHECK11-NEXT:    [[CONV47:%.*]] = sext i16 [[TMP29]] to i32
8191 // CHECK11-NEXT:    [[ADD48:%.*]] = add nsw i32 [[CONV47]], 1
8192 // CHECK11-NEXT:    [[CONV49:%.*]] = trunc i32 [[ADD48]] to i16
8193 // CHECK11-NEXT:    store i16 [[CONV49]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP13]]
8194 // CHECK11-NEXT:    br label [[OMP_BODY_CONTINUE50:%.*]]
8195 // CHECK11:       omp.body.continue50:
8196 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_INC51:%.*]]
8197 // CHECK11:       omp.inner.for.inc51:
8198 // CHECK11-NEXT:    [[TMP30:%.*]] = load i32, ptr [[DOTOMP_IV39]], align 4, !llvm.access.group [[ACC_GRP13]]
8199 // CHECK11-NEXT:    [[ADD52:%.*]] = add nsw i32 [[TMP30]], 1
8200 // CHECK11-NEXT:    store i32 [[ADD52]], ptr [[DOTOMP_IV39]], align 4, !llvm.access.group [[ACC_GRP13]]
8201 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND41]], !llvm.loop [[LOOP14:![0-9]+]]
8202 // CHECK11:       omp.inner.for.end53:
8203 // CHECK11-NEXT:    store i32 10, ptr [[I40]], align 4
8204 // CHECK11-NEXT:    store i32 0, ptr [[DOTOMP_LB55]], align 4
8205 // CHECK11-NEXT:    store i32 9, ptr [[DOTOMP_UB56]], align 4
8206 // CHECK11-NEXT:    [[TMP31:%.*]] = load i32, ptr [[DOTOMP_LB55]], align 4
8207 // CHECK11-NEXT:    store i32 [[TMP31]], ptr [[DOTOMP_IV57]], align 4
8208 // CHECK11-NEXT:    [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], ptr [[B]], i32 0, i32 0
8209 // CHECK11-NEXT:    call void @llvm.assume(i1 true) [ "align"(ptr [[ARRAYDECAY]], i32 16) ]
8210 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND59:%.*]]
8211 // CHECK11:       omp.inner.for.cond59:
8212 // CHECK11-NEXT:    [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IV57]], align 4, !llvm.access.group [[ACC_GRP16:![0-9]+]]
8213 // CHECK11-NEXT:    [[TMP33:%.*]] = load i32, ptr [[DOTOMP_UB56]], align 4, !llvm.access.group [[ACC_GRP16]]
8214 // CHECK11-NEXT:    [[CMP60:%.*]] = icmp sle i32 [[TMP32]], [[TMP33]]
8215 // CHECK11-NEXT:    br i1 [[CMP60]], label [[OMP_INNER_FOR_BODY61:%.*]], label [[OMP_INNER_FOR_END85:%.*]]
8216 // CHECK11:       omp.inner.for.body61:
8217 // CHECK11-NEXT:    [[TMP34:%.*]] = load i32, ptr [[DOTOMP_IV57]], align 4, !llvm.access.group [[ACC_GRP16]]
8218 // CHECK11-NEXT:    [[MUL62:%.*]] = mul nsw i32 [[TMP34]], 1
8219 // CHECK11-NEXT:    [[ADD63:%.*]] = add nsw i32 0, [[MUL62]]
8220 // CHECK11-NEXT:    store i32 [[ADD63]], ptr [[I58]], align 4, !llvm.access.group [[ACC_GRP16]]
8221 // CHECK11-NEXT:    [[TMP35:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP16]]
8222 // CHECK11-NEXT:    [[ADD64:%.*]] = add nsw i32 [[TMP35]], 1
8223 // CHECK11-NEXT:    store i32 [[ADD64]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP16]]
8224 // CHECK11-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B]], i32 0, i32 2
8225 // CHECK11-NEXT:    [[TMP36:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP16]]
8226 // CHECK11-NEXT:    [[CONV65:%.*]] = fpext float [[TMP36]] to double
8227 // CHECK11-NEXT:    [[ADD66:%.*]] = fadd double [[CONV65]], 1.000000e+00
8228 // CHECK11-NEXT:    [[CONV67:%.*]] = fptrunc double [[ADD66]] to float
8229 // CHECK11-NEXT:    store float [[CONV67]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP16]]
8230 // CHECK11-NEXT:    [[ARRAYIDX68:%.*]] = getelementptr inbounds float, ptr [[VLA]], i32 3
8231 // CHECK11-NEXT:    [[TMP37:%.*]] = load float, ptr [[ARRAYIDX68]], align 4, !llvm.access.group [[ACC_GRP16]]
8232 // CHECK11-NEXT:    [[CONV69:%.*]] = fpext float [[TMP37]] to double
8233 // CHECK11-NEXT:    [[ADD70:%.*]] = fadd double [[CONV69]], 1.000000e+00
8234 // CHECK11-NEXT:    [[CONV71:%.*]] = fptrunc double [[ADD70]] to float
8235 // CHECK11-NEXT:    store float [[CONV71]], ptr [[ARRAYIDX68]], align 4, !llvm.access.group [[ACC_GRP16]]
8236 // CHECK11-NEXT:    [[ARRAYIDX72:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C]], i32 0, i32 1
8237 // CHECK11-NEXT:    [[ARRAYIDX73:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX72]], i32 0, i32 2
8238 // CHECK11-NEXT:    [[TMP38:%.*]] = load double, ptr [[ARRAYIDX73]], align 8, !llvm.access.group [[ACC_GRP16]]
8239 // CHECK11-NEXT:    [[ADD74:%.*]] = fadd double [[TMP38]], 1.000000e+00
8240 // CHECK11-NEXT:    store double [[ADD74]], ptr [[ARRAYIDX73]], align 8, !llvm.access.group [[ACC_GRP16]]
8241 // CHECK11-NEXT:    [[TMP39:%.*]] = mul nsw i32 1, [[TMP2]]
8242 // CHECK11-NEXT:    [[ARRAYIDX75:%.*]] = getelementptr inbounds double, ptr [[VLA1]], i32 [[TMP39]]
8243 // CHECK11-NEXT:    [[ARRAYIDX76:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX75]], i32 3
8244 // CHECK11-NEXT:    [[TMP40:%.*]] = load double, ptr [[ARRAYIDX76]], align 8, !llvm.access.group [[ACC_GRP16]]
8245 // CHECK11-NEXT:    [[ADD77:%.*]] = fadd double [[TMP40]], 1.000000e+00
8246 // CHECK11-NEXT:    store double [[ADD77]], ptr [[ARRAYIDX76]], align 8, !llvm.access.group [[ACC_GRP16]]
8247 // CHECK11-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D]], i32 0, i32 0
8248 // CHECK11-NEXT:    [[TMP41:%.*]] = load i64, ptr [[X]], align 4, !llvm.access.group [[ACC_GRP16]]
8249 // CHECK11-NEXT:    [[ADD78:%.*]] = add nsw i64 [[TMP41]], 1
8250 // CHECK11-NEXT:    store i64 [[ADD78]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP16]]
8251 // CHECK11-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D]], i32 0, i32 1
8252 // CHECK11-NEXT:    [[TMP42:%.*]] = load i8, ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP16]]
8253 // CHECK11-NEXT:    [[CONV79:%.*]] = sext i8 [[TMP42]] to i32
8254 // CHECK11-NEXT:    [[ADD80:%.*]] = add nsw i32 [[CONV79]], 1
8255 // CHECK11-NEXT:    [[CONV81:%.*]] = trunc i32 [[ADD80]] to i8
8256 // CHECK11-NEXT:    store i8 [[CONV81]], ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP16]]
8257 // CHECK11-NEXT:    br label [[OMP_BODY_CONTINUE82:%.*]]
8258 // CHECK11:       omp.body.continue82:
8259 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_INC83:%.*]]
8260 // CHECK11:       omp.inner.for.inc83:
8261 // CHECK11-NEXT:    [[TMP43:%.*]] = load i32, ptr [[DOTOMP_IV57]], align 4, !llvm.access.group [[ACC_GRP16]]
8262 // CHECK11-NEXT:    [[ADD84:%.*]] = add nsw i32 [[TMP43]], 1
8263 // CHECK11-NEXT:    store i32 [[ADD84]], ptr [[DOTOMP_IV57]], align 4, !llvm.access.group [[ACC_GRP16]]
8264 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND59]], !llvm.loop [[LOOP17:![0-9]+]]
8265 // CHECK11:       omp.inner.for.end85:
8266 // CHECK11-NEXT:    store i32 10, ptr [[I58]], align 4
8267 // CHECK11-NEXT:    [[TMP44:%.*]] = load i32, ptr [[A]], align 4
8268 // CHECK11-NEXT:    [[TMP45:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
8269 // CHECK11-NEXT:    call void @llvm.stackrestore.p0(ptr [[TMP45]])
8270 // CHECK11-NEXT:    ret i32 [[TMP44]]
8271 //
8272 //
8273 // CHECK11-LABEL: define {{[^@]+}}@_Z3bari
8274 // CHECK11-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
8275 // CHECK11-NEXT:  entry:
8276 // CHECK11-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
8277 // CHECK11-NEXT:    [[A:%.*]] = alloca i32, align 4
8278 // CHECK11-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
8279 // CHECK11-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
8280 // CHECK11-NEXT:    store i32 0, ptr [[A]], align 4
8281 // CHECK11-NEXT:    [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
8282 // CHECK11-NEXT:    [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]])
8283 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A]], align 4
8284 // CHECK11-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
8285 // CHECK11-NEXT:    store i32 [[ADD]], ptr [[A]], align 4
8286 // CHECK11-NEXT:    [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
8287 // CHECK11-NEXT:    [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]])
8288 // CHECK11-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A]], align 4
8289 // CHECK11-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
8290 // CHECK11-NEXT:    store i32 [[ADD2]], ptr [[A]], align 4
8291 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
8292 // CHECK11-NEXT:    [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]])
8293 // CHECK11-NEXT:    [[TMP5:%.*]] = load i32, ptr [[A]], align 4
8294 // CHECK11-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
8295 // CHECK11-NEXT:    store i32 [[ADD4]], ptr [[A]], align 4
8296 // CHECK11-NEXT:    [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4
8297 // CHECK11-NEXT:    [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]])
8298 // CHECK11-NEXT:    [[TMP7:%.*]] = load i32, ptr [[A]], align 4
8299 // CHECK11-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
8300 // CHECK11-NEXT:    store i32 [[ADD6]], ptr [[A]], align 4
8301 // CHECK11-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A]], align 4
8302 // CHECK11-NEXT:    ret i32 [[TMP8]]
8303 //
8304 //
8305 // CHECK11-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
8306 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 {
8307 // CHECK11-NEXT:  entry:
8308 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
8309 // CHECK11-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
8310 // CHECK11-NEXT:    [[B:%.*]] = alloca i32, align 4
8311 // CHECK11-NEXT:    [[SAVED_STACK:%.*]] = alloca ptr, align 4
8312 // CHECK11-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
8313 // CHECK11-NEXT:    [[TMP:%.*]] = alloca i32, align 4
8314 // CHECK11-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
8315 // CHECK11-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
8316 // CHECK11-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
8317 // CHECK11-NEXT:    [[I:%.*]] = alloca i32, align 4
8318 // CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
8319 // CHECK11-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
8320 // CHECK11-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
8321 // CHECK11-NEXT:    [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
8322 // CHECK11-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
8323 // CHECK11-NEXT:    store i32 [[ADD]], ptr [[B]], align 4
8324 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
8325 // CHECK11-NEXT:    [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
8326 // CHECK11-NEXT:    store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4
8327 // CHECK11-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
8328 // CHECK11-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
8329 // CHECK11-NEXT:    store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4
8330 // CHECK11-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
8331 // CHECK11-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4
8332 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
8333 // CHECK11-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
8334 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
8335 // CHECK11:       omp.inner.for.cond:
8336 // CHECK11-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19:![0-9]+]]
8337 // CHECK11-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP19]]
8338 // CHECK11-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
8339 // CHECK11-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
8340 // CHECK11:       omp.inner.for.body:
8341 // CHECK11-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]]
8342 // CHECK11-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
8343 // CHECK11-NEXT:    [[ADD2:%.*]] = add nsw i32 0, [[MUL]]
8344 // CHECK11-NEXT:    store i32 [[ADD2]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]]
8345 // CHECK11-NEXT:    [[TMP8:%.*]] = load i32, ptr [[B]], align 4, !llvm.access.group [[ACC_GRP19]]
8346 // CHECK11-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP8]] to double
8347 // CHECK11-NEXT:    [[ADD3:%.*]] = fadd double [[CONV]], 1.500000e+00
8348 // CHECK11-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0
8349 // CHECK11-NEXT:    store double [[ADD3]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP19]]
8350 // CHECK11-NEXT:    [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[THIS1]], i32 0, i32 0
8351 // CHECK11-NEXT:    [[TMP9:%.*]] = load double, ptr [[A4]], align 4, !llvm.access.group [[ACC_GRP19]]
8352 // CHECK11-NEXT:    [[INC:%.*]] = fadd double [[TMP9]], 1.000000e+00
8353 // CHECK11-NEXT:    store double [[INC]], ptr [[A4]], align 4, !llvm.access.group [[ACC_GRP19]]
8354 // CHECK11-NEXT:    [[CONV5:%.*]] = fptosi double [[INC]] to i16
8355 // CHECK11-NEXT:    [[TMP10:%.*]] = mul nsw i32 1, [[TMP1]]
8356 // CHECK11-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP10]]
8357 // CHECK11-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1
8358 // CHECK11-NEXT:    store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2, !llvm.access.group [[ACC_GRP19]]
8359 // CHECK11-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
8360 // CHECK11:       omp.body.continue:
8361 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
8362 // CHECK11:       omp.inner.for.inc:
8363 // CHECK11-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]]
8364 // CHECK11-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1
8365 // CHECK11-NEXT:    store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]]
8366 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
8367 // CHECK11:       omp.inner.for.end:
8368 // CHECK11-NEXT:    store i32 10, ptr [[I]], align 4
8369 // CHECK11-NEXT:    [[TMP12:%.*]] = mul nsw i32 1, [[TMP1]]
8370 // CHECK11-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP12]]
8371 // CHECK11-NEXT:    [[ARRAYIDX9:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX8]], i32 1
8372 // CHECK11-NEXT:    [[TMP13:%.*]] = load i16, ptr [[ARRAYIDX9]], align 2
8373 // CHECK11-NEXT:    [[CONV10:%.*]] = sext i16 [[TMP13]] to i32
8374 // CHECK11-NEXT:    [[TMP14:%.*]] = load i32, ptr [[B]], align 4
8375 // CHECK11-NEXT:    [[ADD11:%.*]] = add nsw i32 [[CONV10]], [[TMP14]]
8376 // CHECK11-NEXT:    [[TMP15:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
8377 // CHECK11-NEXT:    call void @llvm.stackrestore.p0(ptr [[TMP15]])
8378 // CHECK11-NEXT:    ret i32 [[ADD11]]
8379 //
8380 //
8381 // CHECK11-LABEL: define {{[^@]+}}@_ZL7fstatici
8382 // CHECK11-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
8383 // CHECK11-NEXT:  entry:
8384 // CHECK11-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
8385 // CHECK11-NEXT:    [[A:%.*]] = alloca i32, align 4
8386 // CHECK11-NEXT:    [[AA:%.*]] = alloca i16, align 2
8387 // CHECK11-NEXT:    [[AAA:%.*]] = alloca i8, align 1
8388 // CHECK11-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
8389 // CHECK11-NEXT:    [[TMP:%.*]] = alloca i32, align 4
8390 // CHECK11-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
8391 // CHECK11-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
8392 // CHECK11-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
8393 // CHECK11-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
8394 // CHECK11-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
8395 // CHECK11-NEXT:    [[I:%.*]] = alloca i32, align 4
8396 // CHECK11-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
8397 // CHECK11-NEXT:    [[I5:%.*]] = alloca i32, align 4
8398 // CHECK11-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
8399 // CHECK11-NEXT:    store i32 0, ptr [[A]], align 4
8400 // CHECK11-NEXT:    store i16 0, ptr [[AA]], align 2
8401 // CHECK11-NEXT:    store i8 0, ptr [[AAA]], align 1
8402 // CHECK11-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A]], align 4
8403 // CHECK11-NEXT:    store i32 [[TMP0]], ptr [[DOTCAPTURE_EXPR_]], align 4
8404 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
8405 // CHECK11-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_1]], align 4
8406 // CHECK11-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
8407 // CHECK11-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
8408 // CHECK11-NEXT:    [[SUB:%.*]] = sub i32 [[TMP2]], [[TMP3]]
8409 // CHECK11-NEXT:    [[SUB3:%.*]] = sub i32 [[SUB]], 1
8410 // CHECK11-NEXT:    [[ADD:%.*]] = add i32 [[SUB3]], 1
8411 // CHECK11-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
8412 // CHECK11-NEXT:    [[SUB4:%.*]] = sub i32 [[DIV]], 1
8413 // CHECK11-NEXT:    store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 4
8414 // CHECK11-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
8415 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
8416 // CHECK11-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4
8417 // CHECK11-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
8418 // CHECK11-NEXT:    store i32 [[TMP5]], ptr [[I]], align 4
8419 // CHECK11-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
8420 // CHECK11-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
8421 // CHECK11-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
8422 // CHECK11-NEXT:    br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]
8423 // CHECK11:       simd.if.then:
8424 // CHECK11-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
8425 // CHECK11-NEXT:    store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4
8426 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
8427 // CHECK11:       omp.inner.for.cond:
8428 // CHECK11-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22:![0-9]+]]
8429 // CHECK11-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP22]]
8430 // CHECK11-NEXT:    [[ADD6:%.*]] = add i32 [[TMP10]], 1
8431 // CHECK11-NEXT:    [[CMP7:%.*]] = icmp ult i32 [[TMP9]], [[ADD6]]
8432 // CHECK11-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
8433 // CHECK11:       omp.inner.for.body:
8434 // CHECK11-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group [[ACC_GRP22]]
8435 // CHECK11-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]]
8436 // CHECK11-NEXT:    [[MUL:%.*]] = mul i32 [[TMP12]], 1
8437 // CHECK11-NEXT:    [[ADD8:%.*]] = add i32 [[TMP11]], [[MUL]]
8438 // CHECK11-NEXT:    store i32 [[ADD8]], ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP22]]
8439 // CHECK11-NEXT:    [[TMP13:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP22]]
8440 // CHECK11-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1
8441 // CHECK11-NEXT:    store i32 [[ADD9]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP22]]
8442 // CHECK11-NEXT:    [[TMP14:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP22]]
8443 // CHECK11-NEXT:    [[CONV:%.*]] = sext i16 [[TMP14]] to i32
8444 // CHECK11-NEXT:    [[ADD10:%.*]] = add nsw i32 [[CONV]], 1
8445 // CHECK11-NEXT:    [[CONV11:%.*]] = trunc i32 [[ADD10]] to i16
8446 // CHECK11-NEXT:    store i16 [[CONV11]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP22]]
8447 // CHECK11-NEXT:    [[TMP15:%.*]] = load i8, ptr [[AAA]], align 1, !llvm.access.group [[ACC_GRP22]]
8448 // CHECK11-NEXT:    [[CONV12:%.*]] = sext i8 [[TMP15]] to i32
8449 // CHECK11-NEXT:    [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
8450 // CHECK11-NEXT:    [[CONV14:%.*]] = trunc i32 [[ADD13]] to i8
8451 // CHECK11-NEXT:    store i8 [[CONV14]], ptr [[AAA]], align 1, !llvm.access.group [[ACC_GRP22]]
8452 // CHECK11-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i32 0, i32 2
8453 // CHECK11-NEXT:    [[TMP16:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP22]]
8454 // CHECK11-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1
8455 // CHECK11-NEXT:    store i32 [[ADD15]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP22]]
8456 // CHECK11-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
8457 // CHECK11:       omp.body.continue:
8458 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
8459 // CHECK11:       omp.inner.for.inc:
8460 // CHECK11-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]]
8461 // CHECK11-NEXT:    [[ADD16:%.*]] = add i32 [[TMP17]], 1
8462 // CHECK11-NEXT:    store i32 [[ADD16]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]]
8463 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
8464 // CHECK11:       omp.inner.for.end:
8465 // CHECK11-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
8466 // CHECK11-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
8467 // CHECK11-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
8468 // CHECK11-NEXT:    [[SUB17:%.*]] = sub i32 [[TMP19]], [[TMP20]]
8469 // CHECK11-NEXT:    [[SUB18:%.*]] = sub i32 [[SUB17]], 1
8470 // CHECK11-NEXT:    [[ADD19:%.*]] = add i32 [[SUB18]], 1
8471 // CHECK11-NEXT:    [[DIV20:%.*]] = udiv i32 [[ADD19]], 1
8472 // CHECK11-NEXT:    [[MUL21:%.*]] = mul i32 [[DIV20]], 1
8473 // CHECK11-NEXT:    [[ADD22:%.*]] = add i32 [[TMP18]], [[MUL21]]
8474 // CHECK11-NEXT:    store i32 [[ADD22]], ptr [[I5]], align 4
8475 // CHECK11-NEXT:    br label [[SIMD_IF_END]]
8476 // CHECK11:       simd.if.end:
8477 // CHECK11-NEXT:    [[TMP21:%.*]] = load i32, ptr [[A]], align 4
8478 // CHECK11-NEXT:    ret i32 [[TMP21]]
8479 //
8480 //
8481 // CHECK11-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
8482 // CHECK11-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat {
8483 // CHECK11-NEXT:  entry:
8484 // CHECK11-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
8485 // CHECK11-NEXT:    [[A:%.*]] = alloca i32, align 4
8486 // CHECK11-NEXT:    [[AA:%.*]] = alloca i16, align 2
8487 // CHECK11-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
8488 // CHECK11-NEXT:    [[TMP:%.*]] = alloca i32, align 4
8489 // CHECK11-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
8490 // CHECK11-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
8491 // CHECK11-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
8492 // CHECK11-NEXT:    [[I:%.*]] = alloca i32, align 4
8493 // CHECK11-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
8494 // CHECK11-NEXT:    store i32 0, ptr [[A]], align 4
8495 // CHECK11-NEXT:    store i16 0, ptr [[AA]], align 2
8496 // CHECK11-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
8497 // CHECK11-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4
8498 // CHECK11-NEXT:    [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
8499 // CHECK11-NEXT:    store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4
8500 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
8501 // CHECK11:       omp.inner.for.cond:
8502 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25:![0-9]+]]
8503 // CHECK11-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP25]]
8504 // CHECK11-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
8505 // CHECK11-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
8506 // CHECK11:       omp.inner.for.body:
8507 // CHECK11-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]]
8508 // CHECK11-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
8509 // CHECK11-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
8510 // CHECK11-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP25]]
8511 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP25]]
8512 // CHECK11-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
8513 // CHECK11-NEXT:    store i32 [[ADD1]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP25]]
8514 // CHECK11-NEXT:    [[TMP5:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP25]]
8515 // CHECK11-NEXT:    [[CONV:%.*]] = sext i16 [[TMP5]] to i32
8516 // CHECK11-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
8517 // CHECK11-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
8518 // CHECK11-NEXT:    store i16 [[CONV3]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP25]]
8519 // CHECK11-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i32 0, i32 2
8520 // CHECK11-NEXT:    [[TMP6:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP25]]
8521 // CHECK11-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1
8522 // CHECK11-NEXT:    store i32 [[ADD4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP25]]
8523 // CHECK11-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
8524 // CHECK11:       omp.body.continue:
8525 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
8526 // CHECK11:       omp.inner.for.inc:
8527 // CHECK11-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]]
8528 // CHECK11-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP7]], 1
8529 // CHECK11-NEXT:    store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]]
8530 // CHECK11-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]
8531 // CHECK11:       omp.inner.for.end:
8532 // CHECK11-NEXT:    store i32 10, ptr [[I]], align 4
8533 // CHECK11-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A]], align 4
8534 // CHECK11-NEXT:    ret i32 [[TMP8]]
8535 //
8536 //
8537 // CHECK13-LABEL: define {{[^@]+}}@_Z3fooi
8538 // CHECK13-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
8539 // CHECK13-NEXT:  entry:
8540 // CHECK13-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
8541 // CHECK13-NEXT:    [[A:%.*]] = alloca i32, align 4
8542 // CHECK13-NEXT:    [[AA:%.*]] = alloca i16, align 2
8543 // CHECK13-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
8544 // CHECK13-NEXT:    [[SAVED_STACK:%.*]] = alloca ptr, align 8
8545 // CHECK13-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
8546 // CHECK13-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
8547 // CHECK13-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
8548 // CHECK13-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
8549 // CHECK13-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
8550 // CHECK13-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
8551 // CHECK13-NEXT:    [[TMP:%.*]] = alloca i32, align 4
8552 // CHECK13-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
8553 // CHECK13-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
8554 // CHECK13-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
8555 // CHECK13-NEXT:    [[I:%.*]] = alloca i32, align 4
8556 // CHECK13-NEXT:    [[_TMP4:%.*]] = alloca i32, align 4
8557 // CHECK13-NEXT:    [[DOTOMP_LB5:%.*]] = alloca i32, align 4
8558 // CHECK13-NEXT:    [[DOTOMP_UB6:%.*]] = alloca i32, align 4
8559 // CHECK13-NEXT:    [[DOTOMP_IV7:%.*]] = alloca i32, align 4
8560 // CHECK13-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i32, align 4
8561 // CHECK13-NEXT:    [[A8:%.*]] = alloca i32, align 4
8562 // CHECK13-NEXT:    [[A9:%.*]] = alloca i32, align 4
8563 // CHECK13-NEXT:    [[_TMP20:%.*]] = alloca i32, align 4
8564 // CHECK13-NEXT:    [[DOTOMP_LB21:%.*]] = alloca i32, align 4
8565 // CHECK13-NEXT:    [[DOTOMP_UB22:%.*]] = alloca i32, align 4
8566 // CHECK13-NEXT:    [[DOTOMP_IV23:%.*]] = alloca i32, align 4
8567 // CHECK13-NEXT:    [[I24:%.*]] = alloca i32, align 4
8568 // CHECK13-NEXT:    [[_TMP36:%.*]] = alloca i32, align 4
8569 // CHECK13-NEXT:    [[DOTOMP_LB37:%.*]] = alloca i32, align 4
8570 // CHECK13-NEXT:    [[DOTOMP_UB38:%.*]] = alloca i32, align 4
8571 // CHECK13-NEXT:    [[DOTOMP_IV39:%.*]] = alloca i32, align 4
8572 // CHECK13-NEXT:    [[I40:%.*]] = alloca i32, align 4
8573 // CHECK13-NEXT:    [[_TMP54:%.*]] = alloca i32, align 4
8574 // CHECK13-NEXT:    [[DOTOMP_LB55:%.*]] = alloca i32, align 4
8575 // CHECK13-NEXT:    [[DOTOMP_UB56:%.*]] = alloca i32, align 4
8576 // CHECK13-NEXT:    [[DOTOMP_IV57:%.*]] = alloca i32, align 4
8577 // CHECK13-NEXT:    [[I58:%.*]] = alloca i32, align 4
8578 // CHECK13-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
8579 // CHECK13-NEXT:    store i32 0, ptr [[A]], align 4
8580 // CHECK13-NEXT:    store i16 0, ptr [[AA]], align 2
8581 // CHECK13-NEXT:    [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
8582 // CHECK13-NEXT:    [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
8583 // CHECK13-NEXT:    [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
8584 // CHECK13-NEXT:    store ptr [[TMP2]], ptr [[SAVED_STACK]], align 8
8585 // CHECK13-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
8586 // CHECK13-NEXT:    store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
8587 // CHECK13-NEXT:    [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4
8588 // CHECK13-NEXT:    [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
8589 // CHECK13-NEXT:    [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]
8590 // CHECK13-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8
8591 // CHECK13-NEXT:    store i64 [[TMP4]], ptr [[__VLA_EXPR1]], align 8
8592 // CHECK13-NEXT:    [[TMP6:%.*]] = load i32, ptr [[A]], align 4
8593 // CHECK13-NEXT:    store i32 [[TMP6]], ptr [[DOTCAPTURE_EXPR_]], align 4
8594 // CHECK13-NEXT:    [[TMP7:%.*]] = load i32, ptr [[A]], align 4
8595 // CHECK13-NEXT:    store i32 [[TMP7]], ptr [[DOTCAPTURE_EXPR_2]], align 4
8596 // CHECK13-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
8597 // CHECK13-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4
8598 // CHECK13-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
8599 // CHECK13-NEXT:    store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4
8600 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
8601 // CHECK13:       omp.inner.for.cond:
8602 // CHECK13-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]]
8603 // CHECK13-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP2]]
8604 // CHECK13-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
8605 // CHECK13-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
8606 // CHECK13:       omp.inner.for.body:
8607 // CHECK13-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
8608 // CHECK13-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
8609 // CHECK13-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
8610 // CHECK13-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]
8611 // CHECK13-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
8612 // CHECK13:       omp.body.continue:
8613 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
8614 // CHECK13:       omp.inner.for.inc:
8615 // CHECK13-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
8616 // CHECK13-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1
8617 // CHECK13-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
8618 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
8619 // CHECK13:       omp.inner.for.end:
8620 // CHECK13-NEXT:    store i32 10, ptr [[I]], align 4
8621 // CHECK13-NEXT:    store i32 0, ptr [[DOTOMP_LB5]], align 4
8622 // CHECK13-NEXT:    store i32 9, ptr [[DOTOMP_UB6]], align 4
8623 // CHECK13-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB5]], align 4
8624 // CHECK13-NEXT:    store i32 [[TMP13]], ptr [[DOTOMP_IV7]], align 4
8625 // CHECK13-NEXT:    [[TMP14:%.*]] = load i32, ptr [[A]], align 4
8626 // CHECK13-NEXT:    store i32 [[TMP14]], ptr [[DOTLINEAR_START]], align 4
8627 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND10:%.*]]
8628 // CHECK13:       omp.inner.for.cond10:
8629 // CHECK13-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV7]], align 4
8630 // CHECK13-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_UB6]], align 4
8631 // CHECK13-NEXT:    [[CMP11:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
8632 // CHECK13-NEXT:    br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY12:%.*]], label [[OMP_INNER_FOR_END19:%.*]]
8633 // CHECK13:       omp.inner.for.body12:
8634 // CHECK13-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV7]], align 4
8635 // CHECK13-NEXT:    [[MUL13:%.*]] = mul nsw i32 [[TMP17]], 1
8636 // CHECK13-NEXT:    [[ADD14:%.*]] = add nsw i32 0, [[MUL13]]
8637 // CHECK13-NEXT:    store i32 [[ADD14]], ptr [[A8]], align 4, !nontemporal !7
8638 // CHECK13-NEXT:    [[TMP18:%.*]] = load i32, ptr [[A8]], align 4, !nontemporal !7
8639 // CHECK13-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP18]], 1
8640 // CHECK13-NEXT:    store i32 [[ADD15]], ptr [[A8]], align 4, !nontemporal !7
8641 // CHECK13-NEXT:    br label [[OMP_BODY_CONTINUE16:%.*]]
8642 // CHECK13:       omp.body.continue16:
8643 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_INC17:%.*]]
8644 // CHECK13:       omp.inner.for.inc17:
8645 // CHECK13-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV7]], align 4
8646 // CHECK13-NEXT:    [[ADD18:%.*]] = add nsw i32 [[TMP19]], 1
8647 // CHECK13-NEXT:    store i32 [[ADD18]], ptr [[DOTOMP_IV7]], align 4
8648 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP8:![0-9]+]]
8649 // CHECK13:       omp.inner.for.end19:
8650 // CHECK13-NEXT:    store i32 10, ptr [[A]], align 4
8651 // CHECK13-NEXT:    store i32 0, ptr [[DOTOMP_LB21]], align 4
8652 // CHECK13-NEXT:    store i32 9, ptr [[DOTOMP_UB22]], align 4
8653 // CHECK13-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTOMP_LB21]], align 4
8654 // CHECK13-NEXT:    store i32 [[TMP20]], ptr [[DOTOMP_IV23]], align 4
8655 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND25:%.*]]
8656 // CHECK13:       omp.inner.for.cond25:
8657 // CHECK13-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IV23]], align 4, !llvm.access.group [[ACC_GRP10:![0-9]+]]
8658 // CHECK13-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTOMP_UB22]], align 4, !llvm.access.group [[ACC_GRP10]]
8659 // CHECK13-NEXT:    [[CMP26:%.*]] = icmp sle i32 [[TMP21]], [[TMP22]]
8660 // CHECK13-NEXT:    br i1 [[CMP26]], label [[OMP_INNER_FOR_BODY27:%.*]], label [[OMP_INNER_FOR_END35:%.*]]
8661 // CHECK13:       omp.inner.for.body27:
8662 // CHECK13-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV23]], align 4, !llvm.access.group [[ACC_GRP10]]
8663 // CHECK13-NEXT:    [[MUL28:%.*]] = mul nsw i32 [[TMP23]], 1
8664 // CHECK13-NEXT:    [[ADD29:%.*]] = add nsw i32 0, [[MUL28]]
8665 // CHECK13-NEXT:    store i32 [[ADD29]], ptr [[I24]], align 4, !llvm.access.group [[ACC_GRP10]]
8666 // CHECK13-NEXT:    [[TMP24:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP10]]
8667 // CHECK13-NEXT:    [[CONV:%.*]] = sext i16 [[TMP24]] to i32
8668 // CHECK13-NEXT:    [[ADD30:%.*]] = add nsw i32 [[CONV]], 1
8669 // CHECK13-NEXT:    [[CONV31:%.*]] = trunc i32 [[ADD30]] to i16
8670 // CHECK13-NEXT:    store i16 [[CONV31]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP10]]
8671 // CHECK13-NEXT:    br label [[OMP_BODY_CONTINUE32:%.*]]
8672 // CHECK13:       omp.body.continue32:
8673 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_INC33:%.*]]
8674 // CHECK13:       omp.inner.for.inc33:
8675 // CHECK13-NEXT:    [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV23]], align 4, !llvm.access.group [[ACC_GRP10]]
8676 // CHECK13-NEXT:    [[ADD34:%.*]] = add nsw i32 [[TMP25]], 1
8677 // CHECK13-NEXT:    store i32 [[ADD34]], ptr [[DOTOMP_IV23]], align 4, !llvm.access.group [[ACC_GRP10]]
8678 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND25]], !llvm.loop [[LOOP11:![0-9]+]]
8679 // CHECK13:       omp.inner.for.end35:
8680 // CHECK13-NEXT:    store i32 10, ptr [[I24]], align 4
8681 // CHECK13-NEXT:    store i32 0, ptr [[DOTOMP_LB37]], align 4
8682 // CHECK13-NEXT:    store i32 9, ptr [[DOTOMP_UB38]], align 4
8683 // CHECK13-NEXT:    [[TMP26:%.*]] = load i32, ptr [[DOTOMP_LB37]], align 4
8684 // CHECK13-NEXT:    store i32 [[TMP26]], ptr [[DOTOMP_IV39]], align 4
8685 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND41:%.*]]
8686 // CHECK13:       omp.inner.for.cond41:
8687 // CHECK13-NEXT:    [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV39]], align 4, !llvm.access.group [[ACC_GRP13:![0-9]+]]
8688 // CHECK13-NEXT:    [[TMP28:%.*]] = load i32, ptr [[DOTOMP_UB38]], align 4, !llvm.access.group [[ACC_GRP13]]
8689 // CHECK13-NEXT:    [[CMP42:%.*]] = icmp sle i32 [[TMP27]], [[TMP28]]
8690 // CHECK13-NEXT:    br i1 [[CMP42]], label [[OMP_INNER_FOR_BODY43:%.*]], label [[OMP_INNER_FOR_END53:%.*]]
8691 // CHECK13:       omp.inner.for.body43:
8692 // CHECK13-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IV39]], align 4, !llvm.access.group [[ACC_GRP13]]
8693 // CHECK13-NEXT:    [[MUL44:%.*]] = mul nsw i32 [[TMP29]], 1
8694 // CHECK13-NEXT:    [[ADD45:%.*]] = add nsw i32 0, [[MUL44]]
8695 // CHECK13-NEXT:    store i32 [[ADD45]], ptr [[I40]], align 4, !llvm.access.group [[ACC_GRP13]]
8696 // CHECK13-NEXT:    [[TMP30:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP13]]
8697 // CHECK13-NEXT:    [[ADD46:%.*]] = add nsw i32 [[TMP30]], 1
8698 // CHECK13-NEXT:    store i32 [[ADD46]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP13]]
8699 // CHECK13-NEXT:    [[TMP31:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP13]]
8700 // CHECK13-NEXT:    [[CONV47:%.*]] = sext i16 [[TMP31]] to i32
8701 // CHECK13-NEXT:    [[ADD48:%.*]] = add nsw i32 [[CONV47]], 1
8702 // CHECK13-NEXT:    [[CONV49:%.*]] = trunc i32 [[ADD48]] to i16
8703 // CHECK13-NEXT:    store i16 [[CONV49]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP13]]
8704 // CHECK13-NEXT:    br label [[OMP_BODY_CONTINUE50:%.*]]
8705 // CHECK13:       omp.body.continue50:
8706 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_INC51:%.*]]
8707 // CHECK13:       omp.inner.for.inc51:
8708 // CHECK13-NEXT:    [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IV39]], align 4, !llvm.access.group [[ACC_GRP13]]
8709 // CHECK13-NEXT:    [[ADD52:%.*]] = add nsw i32 [[TMP32]], 1
8710 // CHECK13-NEXT:    store i32 [[ADD52]], ptr [[DOTOMP_IV39]], align 4, !llvm.access.group [[ACC_GRP13]]
8711 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND41]], !llvm.loop [[LOOP14:![0-9]+]]
8712 // CHECK13:       omp.inner.for.end53:
8713 // CHECK13-NEXT:    store i32 10, ptr [[I40]], align 4
8714 // CHECK13-NEXT:    store i32 0, ptr [[DOTOMP_LB55]], align 4
8715 // CHECK13-NEXT:    store i32 9, ptr [[DOTOMP_UB56]], align 4
8716 // CHECK13-NEXT:    [[TMP33:%.*]] = load i32, ptr [[DOTOMP_LB55]], align 4
8717 // CHECK13-NEXT:    store i32 [[TMP33]], ptr [[DOTOMP_IV57]], align 4
8718 // CHECK13-NEXT:    [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], ptr [[B]], i64 0, i64 0
8719 // CHECK13-NEXT:    call void @llvm.assume(i1 true) [ "align"(ptr [[ARRAYDECAY]], i64 16) ]
8720 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND59:%.*]]
8721 // CHECK13:       omp.inner.for.cond59:
8722 // CHECK13-NEXT:    [[TMP34:%.*]] = load i32, ptr [[DOTOMP_IV57]], align 4, !llvm.access.group [[ACC_GRP16:![0-9]+]]
8723 // CHECK13-NEXT:    [[TMP35:%.*]] = load i32, ptr [[DOTOMP_UB56]], align 4, !llvm.access.group [[ACC_GRP16]]
8724 // CHECK13-NEXT:    [[CMP60:%.*]] = icmp sle i32 [[TMP34]], [[TMP35]]
8725 // CHECK13-NEXT:    br i1 [[CMP60]], label [[OMP_INNER_FOR_BODY61:%.*]], label [[OMP_INNER_FOR_END85:%.*]]
8726 // CHECK13:       omp.inner.for.body61:
8727 // CHECK13-NEXT:    [[TMP36:%.*]] = load i32, ptr [[DOTOMP_IV57]], align 4, !llvm.access.group [[ACC_GRP16]]
8728 // CHECK13-NEXT:    [[MUL62:%.*]] = mul nsw i32 [[TMP36]], 1
8729 // CHECK13-NEXT:    [[ADD63:%.*]] = add nsw i32 0, [[MUL62]]
8730 // CHECK13-NEXT:    store i32 [[ADD63]], ptr [[I58]], align 4, !llvm.access.group [[ACC_GRP16]]
8731 // CHECK13-NEXT:    [[TMP37:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP16]]
8732 // CHECK13-NEXT:    [[ADD64:%.*]] = add nsw i32 [[TMP37]], 1
8733 // CHECK13-NEXT:    store i32 [[ADD64]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP16]]
8734 // CHECK13-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B]], i64 0, i64 2
8735 // CHECK13-NEXT:    [[TMP38:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP16]]
8736 // CHECK13-NEXT:    [[CONV65:%.*]] = fpext float [[TMP38]] to double
8737 // CHECK13-NEXT:    [[ADD66:%.*]] = fadd double [[CONV65]], 1.000000e+00
8738 // CHECK13-NEXT:    [[CONV67:%.*]] = fptrunc double [[ADD66]] to float
8739 // CHECK13-NEXT:    store float [[CONV67]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP16]]
8740 // CHECK13-NEXT:    [[ARRAYIDX68:%.*]] = getelementptr inbounds float, ptr [[VLA]], i64 3
8741 // CHECK13-NEXT:    [[TMP39:%.*]] = load float, ptr [[ARRAYIDX68]], align 4, !llvm.access.group [[ACC_GRP16]]
8742 // CHECK13-NEXT:    [[CONV69:%.*]] = fpext float [[TMP39]] to double
8743 // CHECK13-NEXT:    [[ADD70:%.*]] = fadd double [[CONV69]], 1.000000e+00
8744 // CHECK13-NEXT:    [[CONV71:%.*]] = fptrunc double [[ADD70]] to float
8745 // CHECK13-NEXT:    store float [[CONV71]], ptr [[ARRAYIDX68]], align 4, !llvm.access.group [[ACC_GRP16]]
8746 // CHECK13-NEXT:    [[ARRAYIDX72:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C]], i64 0, i64 1
8747 // CHECK13-NEXT:    [[ARRAYIDX73:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX72]], i64 0, i64 2
8748 // CHECK13-NEXT:    [[TMP40:%.*]] = load double, ptr [[ARRAYIDX73]], align 8, !llvm.access.group [[ACC_GRP16]]
8749 // CHECK13-NEXT:    [[ADD74:%.*]] = fadd double [[TMP40]], 1.000000e+00
8750 // CHECK13-NEXT:    store double [[ADD74]], ptr [[ARRAYIDX73]], align 8, !llvm.access.group [[ACC_GRP16]]
8751 // CHECK13-NEXT:    [[TMP41:%.*]] = mul nsw i64 1, [[TMP4]]
8752 // CHECK13-NEXT:    [[ARRAYIDX75:%.*]] = getelementptr inbounds double, ptr [[VLA1]], i64 [[TMP41]]
8753 // CHECK13-NEXT:    [[ARRAYIDX76:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX75]], i64 3
8754 // CHECK13-NEXT:    [[TMP42:%.*]] = load double, ptr [[ARRAYIDX76]], align 8, !llvm.access.group [[ACC_GRP16]]
8755 // CHECK13-NEXT:    [[ADD77:%.*]] = fadd double [[TMP42]], 1.000000e+00
8756 // CHECK13-NEXT:    store double [[ADD77]], ptr [[ARRAYIDX76]], align 8, !llvm.access.group [[ACC_GRP16]]
8757 // CHECK13-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D]], i32 0, i32 0
8758 // CHECK13-NEXT:    [[TMP43:%.*]] = load i64, ptr [[X]], align 8, !llvm.access.group [[ACC_GRP16]]
8759 // CHECK13-NEXT:    [[ADD78:%.*]] = add nsw i64 [[TMP43]], 1
8760 // CHECK13-NEXT:    store i64 [[ADD78]], ptr [[X]], align 8, !llvm.access.group [[ACC_GRP16]]
8761 // CHECK13-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D]], i32 0, i32 1
8762 // CHECK13-NEXT:    [[TMP44:%.*]] = load i8, ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP16]]
8763 // CHECK13-NEXT:    [[CONV79:%.*]] = sext i8 [[TMP44]] to i32
8764 // CHECK13-NEXT:    [[ADD80:%.*]] = add nsw i32 [[CONV79]], 1
8765 // CHECK13-NEXT:    [[CONV81:%.*]] = trunc i32 [[ADD80]] to i8
8766 // CHECK13-NEXT:    store i8 [[CONV81]], ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP16]]
8767 // CHECK13-NEXT:    br label [[OMP_BODY_CONTINUE82:%.*]]
8768 // CHECK13:       omp.body.continue82:
8769 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_INC83:%.*]]
8770 // CHECK13:       omp.inner.for.inc83:
8771 // CHECK13-NEXT:    [[TMP45:%.*]] = load i32, ptr [[DOTOMP_IV57]], align 4, !llvm.access.group [[ACC_GRP16]]
8772 // CHECK13-NEXT:    [[ADD84:%.*]] = add nsw i32 [[TMP45]], 1
8773 // CHECK13-NEXT:    store i32 [[ADD84]], ptr [[DOTOMP_IV57]], align 4, !llvm.access.group [[ACC_GRP16]]
8774 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND59]], !llvm.loop [[LOOP17:![0-9]+]]
8775 // CHECK13:       omp.inner.for.end85:
8776 // CHECK13-NEXT:    store i32 10, ptr [[I58]], align 4
8777 // CHECK13-NEXT:    [[TMP46:%.*]] = load i32, ptr [[A]], align 4
8778 // CHECK13-NEXT:    [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
8779 // CHECK13-NEXT:    call void @llvm.stackrestore.p0(ptr [[TMP47]])
8780 // CHECK13-NEXT:    ret i32 [[TMP46]]
8781 //
8782 //
8783 // CHECK13-LABEL: define {{[^@]+}}@_Z3bari
8784 // CHECK13-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
8785 // CHECK13-NEXT:  entry:
8786 // CHECK13-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
8787 // CHECK13-NEXT:    [[A:%.*]] = alloca i32, align 4
8788 // CHECK13-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
8789 // CHECK13-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
8790 // CHECK13-NEXT:    store i32 0, ptr [[A]], align 4
8791 // CHECK13-NEXT:    [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
8792 // CHECK13-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]])
8793 // CHECK13-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A]], align 4
8794 // CHECK13-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
8795 // CHECK13-NEXT:    store i32 [[ADD]], ptr [[A]], align 4
8796 // CHECK13-NEXT:    [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
8797 // CHECK13-NEXT:    [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(ptr noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]])
8798 // CHECK13-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A]], align 4
8799 // CHECK13-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
8800 // CHECK13-NEXT:    store i32 [[ADD2]], ptr [[A]], align 4
8801 // CHECK13-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
8802 // CHECK13-NEXT:    [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]])
8803 // CHECK13-NEXT:    [[TMP5:%.*]] = load i32, ptr [[A]], align 4
8804 // CHECK13-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
8805 // CHECK13-NEXT:    store i32 [[ADD4]], ptr [[A]], align 4
8806 // CHECK13-NEXT:    [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4
8807 // CHECK13-NEXT:    [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]])
8808 // CHECK13-NEXT:    [[TMP7:%.*]] = load i32, ptr [[A]], align 4
8809 // CHECK13-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
8810 // CHECK13-NEXT:    store i32 [[ADD6]], ptr [[A]], align 4
8811 // CHECK13-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A]], align 4
8812 // CHECK13-NEXT:    ret i32 [[TMP8]]
8813 //
8814 //
8815 // CHECK13-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
8816 // CHECK13-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
8817 // CHECK13-NEXT:  entry:
8818 // CHECK13-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
8819 // CHECK13-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
8820 // CHECK13-NEXT:    [[B:%.*]] = alloca i32, align 4
8821 // CHECK13-NEXT:    [[SAVED_STACK:%.*]] = alloca ptr, align 8
8822 // CHECK13-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
8823 // CHECK13-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
8824 // CHECK13-NEXT:    [[TMP:%.*]] = alloca i32, align 4
8825 // CHECK13-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
8826 // CHECK13-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
8827 // CHECK13-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
8828 // CHECK13-NEXT:    [[I:%.*]] = alloca i32, align 4
8829 // CHECK13-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
8830 // CHECK13-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
8831 // CHECK13-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
8832 // CHECK13-NEXT:    [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
8833 // CHECK13-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
8834 // CHECK13-NEXT:    store i32 [[ADD]], ptr [[B]], align 4
8835 // CHECK13-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
8836 // CHECK13-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
8837 // CHECK13-NEXT:    [[TMP3:%.*]] = call ptr @llvm.stacksave.p0()
8838 // CHECK13-NEXT:    store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8
8839 // CHECK13-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
8840 // CHECK13-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
8841 // CHECK13-NEXT:    store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8
8842 // CHECK13-NEXT:    [[TMP5:%.*]] = load i32, ptr [[N_ADDR]], align 4
8843 // CHECK13-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 60
8844 // CHECK13-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
8845 // CHECK13-NEXT:    store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR_]], align 1
8846 // CHECK13-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
8847 // CHECK13-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4
8848 // CHECK13-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
8849 // CHECK13-NEXT:    store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4
8850 // CHECK13-NEXT:    [[TMP7:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
8851 // CHECK13-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1
8852 // CHECK13-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
8853 // CHECK13:       omp_if.then:
8854 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
8855 // CHECK13:       omp.inner.for.cond:
8856 // CHECK13-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19:![0-9]+]]
8857 // CHECK13-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP19]]
8858 // CHECK13-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
8859 // CHECK13-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
8860 // CHECK13:       omp.inner.for.body:
8861 // CHECK13-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]]
8862 // CHECK13-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
8863 // CHECK13-NEXT:    [[ADD3:%.*]] = add nsw i32 0, [[MUL]]
8864 // CHECK13-NEXT:    store i32 [[ADD3]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]]
8865 // CHECK13-NEXT:    [[TMP11:%.*]] = load i32, ptr [[B]], align 4, !llvm.access.group [[ACC_GRP19]]
8866 // CHECK13-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP11]] to double
8867 // CHECK13-NEXT:    [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00
8868 // CHECK13-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0
8869 // CHECK13-NEXT:    store double [[ADD4]], ptr [[A]], align 8, !llvm.access.group [[ACC_GRP19]]
8870 // CHECK13-NEXT:    [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[THIS1]], i32 0, i32 0
8871 // CHECK13-NEXT:    [[TMP12:%.*]] = load double, ptr [[A5]], align 8, !llvm.access.group [[ACC_GRP19]]
8872 // CHECK13-NEXT:    [[INC:%.*]] = fadd double [[TMP12]], 1.000000e+00
8873 // CHECK13-NEXT:    store double [[INC]], ptr [[A5]], align 8, !llvm.access.group [[ACC_GRP19]]
8874 // CHECK13-NEXT:    [[CONV6:%.*]] = fptosi double [[INC]] to i16
8875 // CHECK13-NEXT:    [[TMP13:%.*]] = mul nsw i64 1, [[TMP2]]
8876 // CHECK13-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP13]]
8877 // CHECK13-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1
8878 // CHECK13-NEXT:    store i16 [[CONV6]], ptr [[ARRAYIDX7]], align 2, !llvm.access.group [[ACC_GRP19]]
8879 // CHECK13-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
8880 // CHECK13:       omp.body.continue:
8881 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
8882 // CHECK13:       omp.inner.for.inc:
8883 // CHECK13-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]]
8884 // CHECK13-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP14]], 1
8885 // CHECK13-NEXT:    store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]]
8886 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
8887 // CHECK13:       omp.inner.for.end:
8888 // CHECK13-NEXT:    br label [[OMP_IF_END:%.*]]
8889 // CHECK13:       omp_if.else:
8890 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND9:%.*]]
8891 // CHECK13:       omp.inner.for.cond9:
8892 // CHECK13-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
8893 // CHECK13-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
8894 // CHECK13-NEXT:    [[CMP10:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]]
8895 // CHECK13-NEXT:    br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END25:%.*]]
8896 // CHECK13:       omp.inner.for.body11:
8897 // CHECK13-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
8898 // CHECK13-NEXT:    [[MUL12:%.*]] = mul nsw i32 [[TMP17]], 1
8899 // CHECK13-NEXT:    [[ADD13:%.*]] = add nsw i32 0, [[MUL12]]
8900 // CHECK13-NEXT:    store i32 [[ADD13]], ptr [[I]], align 4
8901 // CHECK13-NEXT:    [[TMP18:%.*]] = load i32, ptr [[B]], align 4
8902 // CHECK13-NEXT:    [[CONV14:%.*]] = sitofp i32 [[TMP18]] to double
8903 // CHECK13-NEXT:    [[ADD15:%.*]] = fadd double [[CONV14]], 1.500000e+00
8904 // CHECK13-NEXT:    [[A16:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[THIS1]], i32 0, i32 0
8905 // CHECK13-NEXT:    store double [[ADD15]], ptr [[A16]], align 8
8906 // CHECK13-NEXT:    [[A17:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[THIS1]], i32 0, i32 0
8907 // CHECK13-NEXT:    [[TMP19:%.*]] = load double, ptr [[A17]], align 8
8908 // CHECK13-NEXT:    [[INC18:%.*]] = fadd double [[TMP19]], 1.000000e+00
8909 // CHECK13-NEXT:    store double [[INC18]], ptr [[A17]], align 8
8910 // CHECK13-NEXT:    [[CONV19:%.*]] = fptosi double [[INC18]] to i16
8911 // CHECK13-NEXT:    [[TMP20:%.*]] = mul nsw i64 1, [[TMP2]]
8912 // CHECK13-NEXT:    [[ARRAYIDX20:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP20]]
8913 // CHECK13-NEXT:    [[ARRAYIDX21:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX20]], i64 1
8914 // CHECK13-NEXT:    store i16 [[CONV19]], ptr [[ARRAYIDX21]], align 2
8915 // CHECK13-NEXT:    br label [[OMP_BODY_CONTINUE22:%.*]]
8916 // CHECK13:       omp.body.continue22:
8917 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_INC23:%.*]]
8918 // CHECK13:       omp.inner.for.inc23:
8919 // CHECK13-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
8920 // CHECK13-NEXT:    [[ADD24:%.*]] = add nsw i32 [[TMP21]], 1
8921 // CHECK13-NEXT:    store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4
8922 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP22:![0-9]+]]
8923 // CHECK13:       omp.inner.for.end25:
8924 // CHECK13-NEXT:    br label [[OMP_IF_END]]
8925 // CHECK13:       omp_if.end:
8926 // CHECK13-NEXT:    store i32 10, ptr [[I]], align 4
8927 // CHECK13-NEXT:    [[TMP22:%.*]] = mul nsw i64 1, [[TMP2]]
8928 // CHECK13-NEXT:    [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP22]]
8929 // CHECK13-NEXT:    [[ARRAYIDX27:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX26]], i64 1
8930 // CHECK13-NEXT:    [[TMP23:%.*]] = load i16, ptr [[ARRAYIDX27]], align 2
8931 // CHECK13-NEXT:    [[CONV28:%.*]] = sext i16 [[TMP23]] to i32
8932 // CHECK13-NEXT:    [[TMP24:%.*]] = load i32, ptr [[B]], align 4
8933 // CHECK13-NEXT:    [[ADD29:%.*]] = add nsw i32 [[CONV28]], [[TMP24]]
8934 // CHECK13-NEXT:    [[TMP25:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
8935 // CHECK13-NEXT:    call void @llvm.stackrestore.p0(ptr [[TMP25]])
8936 // CHECK13-NEXT:    ret i32 [[ADD29]]
8937 //
8938 //
8939 // CHECK13-LABEL: define {{[^@]+}}@_ZL7fstatici
8940 // CHECK13-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
8941 // CHECK13-NEXT:  entry:
8942 // CHECK13-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
8943 // CHECK13-NEXT:    [[A:%.*]] = alloca i32, align 4
8944 // CHECK13-NEXT:    [[AA:%.*]] = alloca i16, align 2
8945 // CHECK13-NEXT:    [[AAA:%.*]] = alloca i8, align 1
8946 // CHECK13-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
8947 // CHECK13-NEXT:    [[TMP:%.*]] = alloca i32, align 4
8948 // CHECK13-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
8949 // CHECK13-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
8950 // CHECK13-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
8951 // CHECK13-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
8952 // CHECK13-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
8953 // CHECK13-NEXT:    [[I:%.*]] = alloca i32, align 4
8954 // CHECK13-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
8955 // CHECK13-NEXT:    [[I5:%.*]] = alloca i32, align 4
8956 // CHECK13-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
8957 // CHECK13-NEXT:    store i32 0, ptr [[A]], align 4
8958 // CHECK13-NEXT:    store i16 0, ptr [[AA]], align 2
8959 // CHECK13-NEXT:    store i8 0, ptr [[AAA]], align 1
8960 // CHECK13-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A]], align 4
8961 // CHECK13-NEXT:    store i32 [[TMP0]], ptr [[DOTCAPTURE_EXPR_]], align 4
8962 // CHECK13-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
8963 // CHECK13-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_1]], align 4
8964 // CHECK13-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
8965 // CHECK13-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
8966 // CHECK13-NEXT:    [[SUB:%.*]] = sub i32 [[TMP2]], [[TMP3]]
8967 // CHECK13-NEXT:    [[SUB3:%.*]] = sub i32 [[SUB]], 1
8968 // CHECK13-NEXT:    [[ADD:%.*]] = add i32 [[SUB3]], 1
8969 // CHECK13-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
8970 // CHECK13-NEXT:    [[SUB4:%.*]] = sub i32 [[DIV]], 1
8971 // CHECK13-NEXT:    store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 4
8972 // CHECK13-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
8973 // CHECK13-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
8974 // CHECK13-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4
8975 // CHECK13-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
8976 // CHECK13-NEXT:    store i32 [[TMP5]], ptr [[I]], align 4
8977 // CHECK13-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
8978 // CHECK13-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
8979 // CHECK13-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
8980 // CHECK13-NEXT:    br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]
8981 // CHECK13:       simd.if.then:
8982 // CHECK13-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
8983 // CHECK13-NEXT:    store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4
8984 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
8985 // CHECK13:       omp.inner.for.cond:
8986 // CHECK13-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24:![0-9]+]]
8987 // CHECK13-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP24]]
8988 // CHECK13-NEXT:    [[ADD6:%.*]] = add i32 [[TMP10]], 1
8989 // CHECK13-NEXT:    [[CMP7:%.*]] = icmp ult i32 [[TMP9]], [[ADD6]]
8990 // CHECK13-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
8991 // CHECK13:       omp.inner.for.body:
8992 // CHECK13-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group [[ACC_GRP24]]
8993 // CHECK13-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]]
8994 // CHECK13-NEXT:    [[MUL:%.*]] = mul i32 [[TMP12]], 1
8995 // CHECK13-NEXT:    [[ADD8:%.*]] = add i32 [[TMP11]], [[MUL]]
8996 // CHECK13-NEXT:    store i32 [[ADD8]], ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP24]]
8997 // CHECK13-NEXT:    [[TMP13:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP24]]
8998 // CHECK13-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1
8999 // CHECK13-NEXT:    store i32 [[ADD9]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP24]]
9000 // CHECK13-NEXT:    [[TMP14:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP24]]
9001 // CHECK13-NEXT:    [[CONV:%.*]] = sext i16 [[TMP14]] to i32
9002 // CHECK13-NEXT:    [[ADD10:%.*]] = add nsw i32 [[CONV]], 1
9003 // CHECK13-NEXT:    [[CONV11:%.*]] = trunc i32 [[ADD10]] to i16
9004 // CHECK13-NEXT:    store i16 [[CONV11]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP24]]
9005 // CHECK13-NEXT:    [[TMP15:%.*]] = load i8, ptr [[AAA]], align 1, !llvm.access.group [[ACC_GRP24]]
9006 // CHECK13-NEXT:    [[CONV12:%.*]] = sext i8 [[TMP15]] to i32
9007 // CHECK13-NEXT:    [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
9008 // CHECK13-NEXT:    [[CONV14:%.*]] = trunc i32 [[ADD13]] to i8
9009 // CHECK13-NEXT:    store i8 [[CONV14]], ptr [[AAA]], align 1, !llvm.access.group [[ACC_GRP24]]
9010 // CHECK13-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i64 0, i64 2
9011 // CHECK13-NEXT:    [[TMP16:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP24]]
9012 // CHECK13-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1
9013 // CHECK13-NEXT:    store i32 [[ADD15]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP24]]
9014 // CHECK13-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
9015 // CHECK13:       omp.body.continue:
9016 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
9017 // CHECK13:       omp.inner.for.inc:
9018 // CHECK13-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]]
9019 // CHECK13-NEXT:    [[ADD16:%.*]] = add i32 [[TMP17]], 1
9020 // CHECK13-NEXT:    store i32 [[ADD16]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]]
9021 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
9022 // CHECK13:       omp.inner.for.end:
9023 // CHECK13-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
9024 // CHECK13-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
9025 // CHECK13-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
9026 // CHECK13-NEXT:    [[SUB17:%.*]] = sub i32 [[TMP19]], [[TMP20]]
9027 // CHECK13-NEXT:    [[SUB18:%.*]] = sub i32 [[SUB17]], 1
9028 // CHECK13-NEXT:    [[ADD19:%.*]] = add i32 [[SUB18]], 1
9029 // CHECK13-NEXT:    [[DIV20:%.*]] = udiv i32 [[ADD19]], 1
9030 // CHECK13-NEXT:    [[MUL21:%.*]] = mul i32 [[DIV20]], 1
9031 // CHECK13-NEXT:    [[ADD22:%.*]] = add i32 [[TMP18]], [[MUL21]]
9032 // CHECK13-NEXT:    store i32 [[ADD22]], ptr [[I5]], align 4
9033 // CHECK13-NEXT:    br label [[SIMD_IF_END]]
9034 // CHECK13:       simd.if.end:
9035 // CHECK13-NEXT:    [[TMP21:%.*]] = load i32, ptr [[A]], align 4
9036 // CHECK13-NEXT:    ret i32 [[TMP21]]
9037 //
9038 //
9039 // CHECK13-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
9040 // CHECK13-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
9041 // CHECK13-NEXT:  entry:
9042 // CHECK13-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
9043 // CHECK13-NEXT:    [[A:%.*]] = alloca i32, align 4
9044 // CHECK13-NEXT:    [[AA:%.*]] = alloca i16, align 2
9045 // CHECK13-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
9046 // CHECK13-NEXT:    [[TMP:%.*]] = alloca i32, align 4
9047 // CHECK13-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
9048 // CHECK13-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
9049 // CHECK13-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
9050 // CHECK13-NEXT:    [[I:%.*]] = alloca i32, align 4
9051 // CHECK13-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
9052 // CHECK13-NEXT:    store i32 0, ptr [[A]], align 4
9053 // CHECK13-NEXT:    store i16 0, ptr [[AA]], align 2
9054 // CHECK13-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
9055 // CHECK13-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4
9056 // CHECK13-NEXT:    [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
9057 // CHECK13-NEXT:    store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4
9058 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
9059 // CHECK13:       omp.inner.for.cond:
9060 // CHECK13-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27:![0-9]+]]
9061 // CHECK13-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP27]]
9062 // CHECK13-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
9063 // CHECK13-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
9064 // CHECK13:       omp.inner.for.body:
9065 // CHECK13-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]]
9066 // CHECK13-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
9067 // CHECK13-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
9068 // CHECK13-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP27]]
9069 // CHECK13-NEXT:    [[TMP4:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP27]]
9070 // CHECK13-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
9071 // CHECK13-NEXT:    store i32 [[ADD1]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP27]]
9072 // CHECK13-NEXT:    [[TMP5:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP27]]
9073 // CHECK13-NEXT:    [[CONV:%.*]] = sext i16 [[TMP5]] to i32
9074 // CHECK13-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
9075 // CHECK13-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
9076 // CHECK13-NEXT:    store i16 [[CONV3]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP27]]
9077 // CHECK13-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i64 0, i64 2
9078 // CHECK13-NEXT:    [[TMP6:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP27]]
9079 // CHECK13-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1
9080 // CHECK13-NEXT:    store i32 [[ADD4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP27]]
9081 // CHECK13-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
9082 // CHECK13:       omp.body.continue:
9083 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
9084 // CHECK13:       omp.inner.for.inc:
9085 // CHECK13-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]]
9086 // CHECK13-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP7]], 1
9087 // CHECK13-NEXT:    store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]]
9088 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]
9089 // CHECK13:       omp.inner.for.end:
9090 // CHECK13-NEXT:    store i32 10, ptr [[I]], align 4
9091 // CHECK13-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A]], align 4
9092 // CHECK13-NEXT:    ret i32 [[TMP8]]
9093 //
9094 //
9095 // CHECK15-LABEL: define {{[^@]+}}@_Z3fooi
9096 // CHECK15-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] {
9097 // CHECK15-NEXT:  entry:
9098 // CHECK15-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
9099 // CHECK15-NEXT:    [[A:%.*]] = alloca i32, align 4
9100 // CHECK15-NEXT:    [[AA:%.*]] = alloca i16, align 2
9101 // CHECK15-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
9102 // CHECK15-NEXT:    [[SAVED_STACK:%.*]] = alloca ptr, align 4
9103 // CHECK15-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
9104 // CHECK15-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
9105 // CHECK15-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
9106 // CHECK15-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
9107 // CHECK15-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
9108 // CHECK15-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
9109 // CHECK15-NEXT:    [[TMP:%.*]] = alloca i32, align 4
9110 // CHECK15-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
9111 // CHECK15-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
9112 // CHECK15-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
9113 // CHECK15-NEXT:    [[I:%.*]] = alloca i32, align 4
9114 // CHECK15-NEXT:    [[_TMP4:%.*]] = alloca i32, align 4
9115 // CHECK15-NEXT:    [[DOTOMP_LB5:%.*]] = alloca i32, align 4
9116 // CHECK15-NEXT:    [[DOTOMP_UB6:%.*]] = alloca i32, align 4
9117 // CHECK15-NEXT:    [[DOTOMP_IV7:%.*]] = alloca i32, align 4
9118 // CHECK15-NEXT:    [[DOTLINEAR_START:%.*]] = alloca i32, align 4
9119 // CHECK15-NEXT:    [[A8:%.*]] = alloca i32, align 4
9120 // CHECK15-NEXT:    [[A9:%.*]] = alloca i32, align 4
9121 // CHECK15-NEXT:    [[_TMP20:%.*]] = alloca i32, align 4
9122 // CHECK15-NEXT:    [[DOTOMP_LB21:%.*]] = alloca i32, align 4
9123 // CHECK15-NEXT:    [[DOTOMP_UB22:%.*]] = alloca i32, align 4
9124 // CHECK15-NEXT:    [[DOTOMP_IV23:%.*]] = alloca i32, align 4
9125 // CHECK15-NEXT:    [[I24:%.*]] = alloca i32, align 4
9126 // CHECK15-NEXT:    [[_TMP36:%.*]] = alloca i32, align 4
9127 // CHECK15-NEXT:    [[DOTOMP_LB37:%.*]] = alloca i32, align 4
9128 // CHECK15-NEXT:    [[DOTOMP_UB38:%.*]] = alloca i32, align 4
9129 // CHECK15-NEXT:    [[DOTOMP_IV39:%.*]] = alloca i32, align 4
9130 // CHECK15-NEXT:    [[I40:%.*]] = alloca i32, align 4
9131 // CHECK15-NEXT:    [[_TMP54:%.*]] = alloca i32, align 4
9132 // CHECK15-NEXT:    [[DOTOMP_LB55:%.*]] = alloca i32, align 4
9133 // CHECK15-NEXT:    [[DOTOMP_UB56:%.*]] = alloca i32, align 4
9134 // CHECK15-NEXT:    [[DOTOMP_IV57:%.*]] = alloca i32, align 4
9135 // CHECK15-NEXT:    [[I58:%.*]] = alloca i32, align 4
9136 // CHECK15-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
9137 // CHECK15-NEXT:    store i32 0, ptr [[A]], align 4
9138 // CHECK15-NEXT:    store i16 0, ptr [[AA]], align 2
9139 // CHECK15-NEXT:    [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
9140 // CHECK15-NEXT:    [[TMP1:%.*]] = call ptr @llvm.stacksave.p0()
9141 // CHECK15-NEXT:    store ptr [[TMP1]], ptr [[SAVED_STACK]], align 4
9142 // CHECK15-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4
9143 // CHECK15-NEXT:    store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4
9144 // CHECK15-NEXT:    [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
9145 // CHECK15-NEXT:    [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]
9146 // CHECK15-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8
9147 // CHECK15-NEXT:    store i32 [[TMP2]], ptr [[__VLA_EXPR1]], align 4
9148 // CHECK15-NEXT:    [[TMP4:%.*]] = load i32, ptr [[A]], align 4
9149 // CHECK15-NEXT:    store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 4
9150 // CHECK15-NEXT:    [[TMP5:%.*]] = load i32, ptr [[A]], align 4
9151 // CHECK15-NEXT:    store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_2]], align 4
9152 // CHECK15-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
9153 // CHECK15-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4
9154 // CHECK15-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
9155 // CHECK15-NEXT:    store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4
9156 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
9157 // CHECK15:       omp.inner.for.cond:
9158 // CHECK15-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3:![0-9]+]]
9159 // CHECK15-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP3]]
9160 // CHECK15-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
9161 // CHECK15-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
9162 // CHECK15:       omp.inner.for.body:
9163 // CHECK15-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]
9164 // CHECK15-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
9165 // CHECK15-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
9166 // CHECK15-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]]
9167 // CHECK15-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
9168 // CHECK15:       omp.body.continue:
9169 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
9170 // CHECK15:       omp.inner.for.inc:
9171 // CHECK15-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]
9172 // CHECK15-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
9173 // CHECK15-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]
9174 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
9175 // CHECK15:       omp.inner.for.end:
9176 // CHECK15-NEXT:    store i32 10, ptr [[I]], align 4
9177 // CHECK15-NEXT:    store i32 0, ptr [[DOTOMP_LB5]], align 4
9178 // CHECK15-NEXT:    store i32 9, ptr [[DOTOMP_UB6]], align 4
9179 // CHECK15-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_LB5]], align 4
9180 // CHECK15-NEXT:    store i32 [[TMP11]], ptr [[DOTOMP_IV7]], align 4
9181 // CHECK15-NEXT:    [[TMP12:%.*]] = load i32, ptr [[A]], align 4
9182 // CHECK15-NEXT:    store i32 [[TMP12]], ptr [[DOTLINEAR_START]], align 4
9183 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND10:%.*]]
9184 // CHECK15:       omp.inner.for.cond10:
9185 // CHECK15-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV7]], align 4
9186 // CHECK15-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB6]], align 4
9187 // CHECK15-NEXT:    [[CMP11:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
9188 // CHECK15-NEXT:    br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY12:%.*]], label [[OMP_INNER_FOR_END19:%.*]]
9189 // CHECK15:       omp.inner.for.body12:
9190 // CHECK15-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV7]], align 4
9191 // CHECK15-NEXT:    [[MUL13:%.*]] = mul nsw i32 [[TMP15]], 1
9192 // CHECK15-NEXT:    [[ADD14:%.*]] = add nsw i32 0, [[MUL13]]
9193 // CHECK15-NEXT:    store i32 [[ADD14]], ptr [[A8]], align 4, !nontemporal !8
9194 // CHECK15-NEXT:    [[TMP16:%.*]] = load i32, ptr [[A8]], align 4, !nontemporal !8
9195 // CHECK15-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1
9196 // CHECK15-NEXT:    store i32 [[ADD15]], ptr [[A8]], align 4, !nontemporal !8
9197 // CHECK15-NEXT:    br label [[OMP_BODY_CONTINUE16:%.*]]
9198 // CHECK15:       omp.body.continue16:
9199 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_INC17:%.*]]
9200 // CHECK15:       omp.inner.for.inc17:
9201 // CHECK15-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV7]], align 4
9202 // CHECK15-NEXT:    [[ADD18:%.*]] = add nsw i32 [[TMP17]], 1
9203 // CHECK15-NEXT:    store i32 [[ADD18]], ptr [[DOTOMP_IV7]], align 4
9204 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND10]], !llvm.loop [[LOOP9:![0-9]+]]
9205 // CHECK15:       omp.inner.for.end19:
9206 // CHECK15-NEXT:    store i32 10, ptr [[A]], align 4
9207 // CHECK15-NEXT:    store i32 0, ptr [[DOTOMP_LB21]], align 4
9208 // CHECK15-NEXT:    store i32 9, ptr [[DOTOMP_UB22]], align 4
9209 // CHECK15-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_LB21]], align 4
9210 // CHECK15-NEXT:    store i32 [[TMP18]], ptr [[DOTOMP_IV23]], align 4
9211 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND25:%.*]]
9212 // CHECK15:       omp.inner.for.cond25:
9213 // CHECK15-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV23]], align 4, !llvm.access.group [[ACC_GRP11:![0-9]+]]
9214 // CHECK15-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTOMP_UB22]], align 4, !llvm.access.group [[ACC_GRP11]]
9215 // CHECK15-NEXT:    [[CMP26:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]]
9216 // CHECK15-NEXT:    br i1 [[CMP26]], label [[OMP_INNER_FOR_BODY27:%.*]], label [[OMP_INNER_FOR_END35:%.*]]
9217 // CHECK15:       omp.inner.for.body27:
9218 // CHECK15-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IV23]], align 4, !llvm.access.group [[ACC_GRP11]]
9219 // CHECK15-NEXT:    [[MUL28:%.*]] = mul nsw i32 [[TMP21]], 1
9220 // CHECK15-NEXT:    [[ADD29:%.*]] = add nsw i32 0, [[MUL28]]
9221 // CHECK15-NEXT:    store i32 [[ADD29]], ptr [[I24]], align 4, !llvm.access.group [[ACC_GRP11]]
9222 // CHECK15-NEXT:    [[TMP22:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP11]]
9223 // CHECK15-NEXT:    [[CONV:%.*]] = sext i16 [[TMP22]] to i32
9224 // CHECK15-NEXT:    [[ADD30:%.*]] = add nsw i32 [[CONV]], 1
9225 // CHECK15-NEXT:    [[CONV31:%.*]] = trunc i32 [[ADD30]] to i16
9226 // CHECK15-NEXT:    store i16 [[CONV31]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP11]]
9227 // CHECK15-NEXT:    br label [[OMP_BODY_CONTINUE32:%.*]]
9228 // CHECK15:       omp.body.continue32:
9229 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_INC33:%.*]]
9230 // CHECK15:       omp.inner.for.inc33:
9231 // CHECK15-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV23]], align 4, !llvm.access.group [[ACC_GRP11]]
9232 // CHECK15-NEXT:    [[ADD34:%.*]] = add nsw i32 [[TMP23]], 1
9233 // CHECK15-NEXT:    store i32 [[ADD34]], ptr [[DOTOMP_IV23]], align 4, !llvm.access.group [[ACC_GRP11]]
9234 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND25]], !llvm.loop [[LOOP12:![0-9]+]]
9235 // CHECK15:       omp.inner.for.end35:
9236 // CHECK15-NEXT:    store i32 10, ptr [[I24]], align 4
9237 // CHECK15-NEXT:    store i32 0, ptr [[DOTOMP_LB37]], align 4
9238 // CHECK15-NEXT:    store i32 9, ptr [[DOTOMP_UB38]], align 4
9239 // CHECK15-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTOMP_LB37]], align 4
9240 // CHECK15-NEXT:    store i32 [[TMP24]], ptr [[DOTOMP_IV39]], align 4
9241 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND41:%.*]]
9242 // CHECK15:       omp.inner.for.cond41:
9243 // CHECK15-NEXT:    [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV39]], align 4, !llvm.access.group [[ACC_GRP14:![0-9]+]]
9244 // CHECK15-NEXT:    [[TMP26:%.*]] = load i32, ptr [[DOTOMP_UB38]], align 4, !llvm.access.group [[ACC_GRP14]]
9245 // CHECK15-NEXT:    [[CMP42:%.*]] = icmp sle i32 [[TMP25]], [[TMP26]]
9246 // CHECK15-NEXT:    br i1 [[CMP42]], label [[OMP_INNER_FOR_BODY43:%.*]], label [[OMP_INNER_FOR_END53:%.*]]
9247 // CHECK15:       omp.inner.for.body43:
9248 // CHECK15-NEXT:    [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV39]], align 4, !llvm.access.group [[ACC_GRP14]]
9249 // CHECK15-NEXT:    [[MUL44:%.*]] = mul nsw i32 [[TMP27]], 1
9250 // CHECK15-NEXT:    [[ADD45:%.*]] = add nsw i32 0, [[MUL44]]
9251 // CHECK15-NEXT:    store i32 [[ADD45]], ptr [[I40]], align 4, !llvm.access.group [[ACC_GRP14]]
9252 // CHECK15-NEXT:    [[TMP28:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP14]]
9253 // CHECK15-NEXT:    [[ADD46:%.*]] = add nsw i32 [[TMP28]], 1
9254 // CHECK15-NEXT:    store i32 [[ADD46]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP14]]
9255 // CHECK15-NEXT:    [[TMP29:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP14]]
9256 // CHECK15-NEXT:    [[CONV47:%.*]] = sext i16 [[TMP29]] to i32
9257 // CHECK15-NEXT:    [[ADD48:%.*]] = add nsw i32 [[CONV47]], 1
9258 // CHECK15-NEXT:    [[CONV49:%.*]] = trunc i32 [[ADD48]] to i16
9259 // CHECK15-NEXT:    store i16 [[CONV49]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP14]]
9260 // CHECK15-NEXT:    br label [[OMP_BODY_CONTINUE50:%.*]]
9261 // CHECK15:       omp.body.continue50:
9262 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_INC51:%.*]]
9263 // CHECK15:       omp.inner.for.inc51:
9264 // CHECK15-NEXT:    [[TMP30:%.*]] = load i32, ptr [[DOTOMP_IV39]], align 4, !llvm.access.group [[ACC_GRP14]]
9265 // CHECK15-NEXT:    [[ADD52:%.*]] = add nsw i32 [[TMP30]], 1
9266 // CHECK15-NEXT:    store i32 [[ADD52]], ptr [[DOTOMP_IV39]], align 4, !llvm.access.group [[ACC_GRP14]]
9267 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND41]], !llvm.loop [[LOOP15:![0-9]+]]
9268 // CHECK15:       omp.inner.for.end53:
9269 // CHECK15-NEXT:    store i32 10, ptr [[I40]], align 4
9270 // CHECK15-NEXT:    store i32 0, ptr [[DOTOMP_LB55]], align 4
9271 // CHECK15-NEXT:    store i32 9, ptr [[DOTOMP_UB56]], align 4
9272 // CHECK15-NEXT:    [[TMP31:%.*]] = load i32, ptr [[DOTOMP_LB55]], align 4
9273 // CHECK15-NEXT:    store i32 [[TMP31]], ptr [[DOTOMP_IV57]], align 4
9274 // CHECK15-NEXT:    [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], ptr [[B]], i32 0, i32 0
9275 // CHECK15-NEXT:    call void @llvm.assume(i1 true) [ "align"(ptr [[ARRAYDECAY]], i32 16) ]
9276 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND59:%.*]]
9277 // CHECK15:       omp.inner.for.cond59:
9278 // CHECK15-NEXT:    [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IV57]], align 4, !llvm.access.group [[ACC_GRP17:![0-9]+]]
9279 // CHECK15-NEXT:    [[TMP33:%.*]] = load i32, ptr [[DOTOMP_UB56]], align 4, !llvm.access.group [[ACC_GRP17]]
9280 // CHECK15-NEXT:    [[CMP60:%.*]] = icmp sle i32 [[TMP32]], [[TMP33]]
9281 // CHECK15-NEXT:    br i1 [[CMP60]], label [[OMP_INNER_FOR_BODY61:%.*]], label [[OMP_INNER_FOR_END85:%.*]]
9282 // CHECK15:       omp.inner.for.body61:
9283 // CHECK15-NEXT:    [[TMP34:%.*]] = load i32, ptr [[DOTOMP_IV57]], align 4, !llvm.access.group [[ACC_GRP17]]
9284 // CHECK15-NEXT:    [[MUL62:%.*]] = mul nsw i32 [[TMP34]], 1
9285 // CHECK15-NEXT:    [[ADD63:%.*]] = add nsw i32 0, [[MUL62]]
9286 // CHECK15-NEXT:    store i32 [[ADD63]], ptr [[I58]], align 4, !llvm.access.group [[ACC_GRP17]]
9287 // CHECK15-NEXT:    [[TMP35:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP17]]
9288 // CHECK15-NEXT:    [[ADD64:%.*]] = add nsw i32 [[TMP35]], 1
9289 // CHECK15-NEXT:    store i32 [[ADD64]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP17]]
9290 // CHECK15-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B]], i32 0, i32 2
9291 // CHECK15-NEXT:    [[TMP36:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP17]]
9292 // CHECK15-NEXT:    [[CONV65:%.*]] = fpext float [[TMP36]] to double
9293 // CHECK15-NEXT:    [[ADD66:%.*]] = fadd double [[CONV65]], 1.000000e+00
9294 // CHECK15-NEXT:    [[CONV67:%.*]] = fptrunc double [[ADD66]] to float
9295 // CHECK15-NEXT:    store float [[CONV67]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP17]]
9296 // CHECK15-NEXT:    [[ARRAYIDX68:%.*]] = getelementptr inbounds float, ptr [[VLA]], i32 3
9297 // CHECK15-NEXT:    [[TMP37:%.*]] = load float, ptr [[ARRAYIDX68]], align 4, !llvm.access.group [[ACC_GRP17]]
9298 // CHECK15-NEXT:    [[CONV69:%.*]] = fpext float [[TMP37]] to double
9299 // CHECK15-NEXT:    [[ADD70:%.*]] = fadd double [[CONV69]], 1.000000e+00
9300 // CHECK15-NEXT:    [[CONV71:%.*]] = fptrunc double [[ADD70]] to float
9301 // CHECK15-NEXT:    store float [[CONV71]], ptr [[ARRAYIDX68]], align 4, !llvm.access.group [[ACC_GRP17]]
9302 // CHECK15-NEXT:    [[ARRAYIDX72:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C]], i32 0, i32 1
9303 // CHECK15-NEXT:    [[ARRAYIDX73:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX72]], i32 0, i32 2
9304 // CHECK15-NEXT:    [[TMP38:%.*]] = load double, ptr [[ARRAYIDX73]], align 8, !llvm.access.group [[ACC_GRP17]]
9305 // CHECK15-NEXT:    [[ADD74:%.*]] = fadd double [[TMP38]], 1.000000e+00
9306 // CHECK15-NEXT:    store double [[ADD74]], ptr [[ARRAYIDX73]], align 8, !llvm.access.group [[ACC_GRP17]]
9307 // CHECK15-NEXT:    [[TMP39:%.*]] = mul nsw i32 1, [[TMP2]]
9308 // CHECK15-NEXT:    [[ARRAYIDX75:%.*]] = getelementptr inbounds double, ptr [[VLA1]], i32 [[TMP39]]
9309 // CHECK15-NEXT:    [[ARRAYIDX76:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX75]], i32 3
9310 // CHECK15-NEXT:    [[TMP40:%.*]] = load double, ptr [[ARRAYIDX76]], align 8, !llvm.access.group [[ACC_GRP17]]
9311 // CHECK15-NEXT:    [[ADD77:%.*]] = fadd double [[TMP40]], 1.000000e+00
9312 // CHECK15-NEXT:    store double [[ADD77]], ptr [[ARRAYIDX76]], align 8, !llvm.access.group [[ACC_GRP17]]
9313 // CHECK15-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D]], i32 0, i32 0
9314 // CHECK15-NEXT:    [[TMP41:%.*]] = load i64, ptr [[X]], align 4, !llvm.access.group [[ACC_GRP17]]
9315 // CHECK15-NEXT:    [[ADD78:%.*]] = add nsw i64 [[TMP41]], 1
9316 // CHECK15-NEXT:    store i64 [[ADD78]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP17]]
9317 // CHECK15-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[D]], i32 0, i32 1
9318 // CHECK15-NEXT:    [[TMP42:%.*]] = load i8, ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP17]]
9319 // CHECK15-NEXT:    [[CONV79:%.*]] = sext i8 [[TMP42]] to i32
9320 // CHECK15-NEXT:    [[ADD80:%.*]] = add nsw i32 [[CONV79]], 1
9321 // CHECK15-NEXT:    [[CONV81:%.*]] = trunc i32 [[ADD80]] to i8
9322 // CHECK15-NEXT:    store i8 [[CONV81]], ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP17]]
9323 // CHECK15-NEXT:    br label [[OMP_BODY_CONTINUE82:%.*]]
9324 // CHECK15:       omp.body.continue82:
9325 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_INC83:%.*]]
9326 // CHECK15:       omp.inner.for.inc83:
9327 // CHECK15-NEXT:    [[TMP43:%.*]] = load i32, ptr [[DOTOMP_IV57]], align 4, !llvm.access.group [[ACC_GRP17]]
9328 // CHECK15-NEXT:    [[ADD84:%.*]] = add nsw i32 [[TMP43]], 1
9329 // CHECK15-NEXT:    store i32 [[ADD84]], ptr [[DOTOMP_IV57]], align 4, !llvm.access.group [[ACC_GRP17]]
9330 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND59]], !llvm.loop [[LOOP18:![0-9]+]]
9331 // CHECK15:       omp.inner.for.end85:
9332 // CHECK15-NEXT:    store i32 10, ptr [[I58]], align 4
9333 // CHECK15-NEXT:    [[TMP44:%.*]] = load i32, ptr [[A]], align 4
9334 // CHECK15-NEXT:    [[TMP45:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
9335 // CHECK15-NEXT:    call void @llvm.stackrestore.p0(ptr [[TMP45]])
9336 // CHECK15-NEXT:    ret i32 [[TMP44]]
9337 //
9338 //
9339 // CHECK15-LABEL: define {{[^@]+}}@_Z3bari
9340 // CHECK15-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
9341 // CHECK15-NEXT:  entry:
9342 // CHECK15-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
9343 // CHECK15-NEXT:    [[A:%.*]] = alloca i32, align 4
9344 // CHECK15-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
9345 // CHECK15-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
9346 // CHECK15-NEXT:    store i32 0, ptr [[A]], align 4
9347 // CHECK15-NEXT:    [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
9348 // CHECK15-NEXT:    [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]])
9349 // CHECK15-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A]], align 4
9350 // CHECK15-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
9351 // CHECK15-NEXT:    store i32 [[ADD]], ptr [[A]], align 4
9352 // CHECK15-NEXT:    [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
9353 // CHECK15-NEXT:    [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]])
9354 // CHECK15-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A]], align 4
9355 // CHECK15-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
9356 // CHECK15-NEXT:    store i32 [[ADD2]], ptr [[A]], align 4
9357 // CHECK15-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
9358 // CHECK15-NEXT:    [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]])
9359 // CHECK15-NEXT:    [[TMP5:%.*]] = load i32, ptr [[A]], align 4
9360 // CHECK15-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
9361 // CHECK15-NEXT:    store i32 [[ADD4]], ptr [[A]], align 4
9362 // CHECK15-NEXT:    [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4
9363 // CHECK15-NEXT:    [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]])
9364 // CHECK15-NEXT:    [[TMP7:%.*]] = load i32, ptr [[A]], align 4
9365 // CHECK15-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
9366 // CHECK15-NEXT:    store i32 [[ADD6]], ptr [[A]], align 4
9367 // CHECK15-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A]], align 4
9368 // CHECK15-NEXT:    ret i32 [[TMP8]]
9369 //
9370 //
9371 // CHECK15-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
9372 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 {
9373 // CHECK15-NEXT:  entry:
9374 // CHECK15-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
9375 // CHECK15-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
9376 // CHECK15-NEXT:    [[B:%.*]] = alloca i32, align 4
9377 // CHECK15-NEXT:    [[SAVED_STACK:%.*]] = alloca ptr, align 4
9378 // CHECK15-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
9379 // CHECK15-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
9380 // CHECK15-NEXT:    [[TMP:%.*]] = alloca i32, align 4
9381 // CHECK15-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
9382 // CHECK15-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
9383 // CHECK15-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
9384 // CHECK15-NEXT:    [[I:%.*]] = alloca i32, align 4
9385 // CHECK15-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
9386 // CHECK15-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
9387 // CHECK15-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
9388 // CHECK15-NEXT:    [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
9389 // CHECK15-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
9390 // CHECK15-NEXT:    store i32 [[ADD]], ptr [[B]], align 4
9391 // CHECK15-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
9392 // CHECK15-NEXT:    [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
9393 // CHECK15-NEXT:    store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4
9394 // CHECK15-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
9395 // CHECK15-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
9396 // CHECK15-NEXT:    store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4
9397 // CHECK15-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
9398 // CHECK15-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 60
9399 // CHECK15-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
9400 // CHECK15-NEXT:    store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR_]], align 1
9401 // CHECK15-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
9402 // CHECK15-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4
9403 // CHECK15-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
9404 // CHECK15-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
9405 // CHECK15-NEXT:    [[TMP6:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR_]], align 1
9406 // CHECK15-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1
9407 // CHECK15-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
9408 // CHECK15:       omp_if.then:
9409 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
9410 // CHECK15:       omp.inner.for.cond:
9411 // CHECK15-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20:![0-9]+]]
9412 // CHECK15-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP20]]
9413 // CHECK15-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
9414 // CHECK15-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
9415 // CHECK15:       omp.inner.for.body:
9416 // CHECK15-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]]
9417 // CHECK15-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
9418 // CHECK15-NEXT:    [[ADD3:%.*]] = add nsw i32 0, [[MUL]]
9419 // CHECK15-NEXT:    store i32 [[ADD3]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP20]]
9420 // CHECK15-NEXT:    [[TMP10:%.*]] = load i32, ptr [[B]], align 4, !llvm.access.group [[ACC_GRP20]]
9421 // CHECK15-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP10]] to double
9422 // CHECK15-NEXT:    [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00
9423 // CHECK15-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0
9424 // CHECK15-NEXT:    store double [[ADD4]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP20]]
9425 // CHECK15-NEXT:    [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[THIS1]], i32 0, i32 0
9426 // CHECK15-NEXT:    [[TMP11:%.*]] = load double, ptr [[A5]], align 4, !llvm.access.group [[ACC_GRP20]]
9427 // CHECK15-NEXT:    [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+00
9428 // CHECK15-NEXT:    store double [[INC]], ptr [[A5]], align 4, !llvm.access.group [[ACC_GRP20]]
9429 // CHECK15-NEXT:    [[CONV6:%.*]] = fptosi double [[INC]] to i16
9430 // CHECK15-NEXT:    [[TMP12:%.*]] = mul nsw i32 1, [[TMP1]]
9431 // CHECK15-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP12]]
9432 // CHECK15-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1
9433 // CHECK15-NEXT:    store i16 [[CONV6]], ptr [[ARRAYIDX7]], align 2, !llvm.access.group [[ACC_GRP20]]
9434 // CHECK15-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
9435 // CHECK15:       omp.body.continue:
9436 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
9437 // CHECK15:       omp.inner.for.inc:
9438 // CHECK15-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]]
9439 // CHECK15-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP13]], 1
9440 // CHECK15-NEXT:    store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]]
9441 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]
9442 // CHECK15:       omp.inner.for.end:
9443 // CHECK15-NEXT:    br label [[OMP_IF_END:%.*]]
9444 // CHECK15:       omp_if.else:
9445 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND9:%.*]]
9446 // CHECK15:       omp.inner.for.cond9:
9447 // CHECK15-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
9448 // CHECK15-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
9449 // CHECK15-NEXT:    [[CMP10:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
9450 // CHECK15-NEXT:    br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END25:%.*]]
9451 // CHECK15:       omp.inner.for.body11:
9452 // CHECK15-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
9453 // CHECK15-NEXT:    [[MUL12:%.*]] = mul nsw i32 [[TMP16]], 1
9454 // CHECK15-NEXT:    [[ADD13:%.*]] = add nsw i32 0, [[MUL12]]
9455 // CHECK15-NEXT:    store i32 [[ADD13]], ptr [[I]], align 4
9456 // CHECK15-NEXT:    [[TMP17:%.*]] = load i32, ptr [[B]], align 4
9457 // CHECK15-NEXT:    [[CONV14:%.*]] = sitofp i32 [[TMP17]] to double
9458 // CHECK15-NEXT:    [[ADD15:%.*]] = fadd double [[CONV14]], 1.500000e+00
9459 // CHECK15-NEXT:    [[A16:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[THIS1]], i32 0, i32 0
9460 // CHECK15-NEXT:    store double [[ADD15]], ptr [[A16]], align 4
9461 // CHECK15-NEXT:    [[A17:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[THIS1]], i32 0, i32 0
9462 // CHECK15-NEXT:    [[TMP18:%.*]] = load double, ptr [[A17]], align 4
9463 // CHECK15-NEXT:    [[INC18:%.*]] = fadd double [[TMP18]], 1.000000e+00
9464 // CHECK15-NEXT:    store double [[INC18]], ptr [[A17]], align 4
9465 // CHECK15-NEXT:    [[CONV19:%.*]] = fptosi double [[INC18]] to i16
9466 // CHECK15-NEXT:    [[TMP19:%.*]] = mul nsw i32 1, [[TMP1]]
9467 // CHECK15-NEXT:    [[ARRAYIDX20:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP19]]
9468 // CHECK15-NEXT:    [[ARRAYIDX21:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX20]], i32 1
9469 // CHECK15-NEXT:    store i16 [[CONV19]], ptr [[ARRAYIDX21]], align 2
9470 // CHECK15-NEXT:    br label [[OMP_BODY_CONTINUE22:%.*]]
9471 // CHECK15:       omp.body.continue22:
9472 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_INC23:%.*]]
9473 // CHECK15:       omp.inner.for.inc23:
9474 // CHECK15-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
9475 // CHECK15-NEXT:    [[ADD24:%.*]] = add nsw i32 [[TMP20]], 1
9476 // CHECK15-NEXT:    store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4
9477 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP23:![0-9]+]]
9478 // CHECK15:       omp.inner.for.end25:
9479 // CHECK15-NEXT:    br label [[OMP_IF_END]]
9480 // CHECK15:       omp_if.end:
9481 // CHECK15-NEXT:    store i32 10, ptr [[I]], align 4
9482 // CHECK15-NEXT:    [[TMP21:%.*]] = mul nsw i32 1, [[TMP1]]
9483 // CHECK15-NEXT:    [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP21]]
9484 // CHECK15-NEXT:    [[ARRAYIDX27:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX26]], i32 1
9485 // CHECK15-NEXT:    [[TMP22:%.*]] = load i16, ptr [[ARRAYIDX27]], align 2
9486 // CHECK15-NEXT:    [[CONV28:%.*]] = sext i16 [[TMP22]] to i32
9487 // CHECK15-NEXT:    [[TMP23:%.*]] = load i32, ptr [[B]], align 4
9488 // CHECK15-NEXT:    [[ADD29:%.*]] = add nsw i32 [[CONV28]], [[TMP23]]
9489 // CHECK15-NEXT:    [[TMP24:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
9490 // CHECK15-NEXT:    call void @llvm.stackrestore.p0(ptr [[TMP24]])
9491 // CHECK15-NEXT:    ret i32 [[ADD29]]
9492 //
9493 //
9494 // CHECK15-LABEL: define {{[^@]+}}@_ZL7fstatici
9495 // CHECK15-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
9496 // CHECK15-NEXT:  entry:
9497 // CHECK15-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
9498 // CHECK15-NEXT:    [[A:%.*]] = alloca i32, align 4
9499 // CHECK15-NEXT:    [[AA:%.*]] = alloca i16, align 2
9500 // CHECK15-NEXT:    [[AAA:%.*]] = alloca i8, align 1
9501 // CHECK15-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
9502 // CHECK15-NEXT:    [[TMP:%.*]] = alloca i32, align 4
9503 // CHECK15-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
9504 // CHECK15-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
9505 // CHECK15-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
9506 // CHECK15-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
9507 // CHECK15-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
9508 // CHECK15-NEXT:    [[I:%.*]] = alloca i32, align 4
9509 // CHECK15-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
9510 // CHECK15-NEXT:    [[I5:%.*]] = alloca i32, align 4
9511 // CHECK15-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
9512 // CHECK15-NEXT:    store i32 0, ptr [[A]], align 4
9513 // CHECK15-NEXT:    store i16 0, ptr [[AA]], align 2
9514 // CHECK15-NEXT:    store i8 0, ptr [[AAA]], align 1
9515 // CHECK15-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A]], align 4
9516 // CHECK15-NEXT:    store i32 [[TMP0]], ptr [[DOTCAPTURE_EXPR_]], align 4
9517 // CHECK15-NEXT:    [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
9518 // CHECK15-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_1]], align 4
9519 // CHECK15-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
9520 // CHECK15-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
9521 // CHECK15-NEXT:    [[SUB:%.*]] = sub i32 [[TMP2]], [[TMP3]]
9522 // CHECK15-NEXT:    [[SUB3:%.*]] = sub i32 [[SUB]], 1
9523 // CHECK15-NEXT:    [[ADD:%.*]] = add i32 [[SUB3]], 1
9524 // CHECK15-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
9525 // CHECK15-NEXT:    [[SUB4:%.*]] = sub i32 [[DIV]], 1
9526 // CHECK15-NEXT:    store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 4
9527 // CHECK15-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
9528 // CHECK15-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
9529 // CHECK15-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4
9530 // CHECK15-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
9531 // CHECK15-NEXT:    store i32 [[TMP5]], ptr [[I]], align 4
9532 // CHECK15-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
9533 // CHECK15-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
9534 // CHECK15-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
9535 // CHECK15-NEXT:    br i1 [[CMP]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END:%.*]]
9536 // CHECK15:       simd.if.then:
9537 // CHECK15-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
9538 // CHECK15-NEXT:    store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4
9539 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
9540 // CHECK15:       omp.inner.for.cond:
9541 // CHECK15-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25:![0-9]+]]
9542 // CHECK15-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP25]]
9543 // CHECK15-NEXT:    [[ADD6:%.*]] = add i32 [[TMP10]], 1
9544 // CHECK15-NEXT:    [[CMP7:%.*]] = icmp ult i32 [[TMP9]], [[ADD6]]
9545 // CHECK15-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
9546 // CHECK15:       omp.inner.for.body:
9547 // CHECK15-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group [[ACC_GRP25]]
9548 // CHECK15-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]]
9549 // CHECK15-NEXT:    [[MUL:%.*]] = mul i32 [[TMP12]], 1
9550 // CHECK15-NEXT:    [[ADD8:%.*]] = add i32 [[TMP11]], [[MUL]]
9551 // CHECK15-NEXT:    store i32 [[ADD8]], ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP25]]
9552 // CHECK15-NEXT:    [[TMP13:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP25]]
9553 // CHECK15-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1
9554 // CHECK15-NEXT:    store i32 [[ADD9]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP25]]
9555 // CHECK15-NEXT:    [[TMP14:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP25]]
9556 // CHECK15-NEXT:    [[CONV:%.*]] = sext i16 [[TMP14]] to i32
9557 // CHECK15-NEXT:    [[ADD10:%.*]] = add nsw i32 [[CONV]], 1
9558 // CHECK15-NEXT:    [[CONV11:%.*]] = trunc i32 [[ADD10]] to i16
9559 // CHECK15-NEXT:    store i16 [[CONV11]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP25]]
9560 // CHECK15-NEXT:    [[TMP15:%.*]] = load i8, ptr [[AAA]], align 1, !llvm.access.group [[ACC_GRP25]]
9561 // CHECK15-NEXT:    [[CONV12:%.*]] = sext i8 [[TMP15]] to i32
9562 // CHECK15-NEXT:    [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1
9563 // CHECK15-NEXT:    [[CONV14:%.*]] = trunc i32 [[ADD13]] to i8
9564 // CHECK15-NEXT:    store i8 [[CONV14]], ptr [[AAA]], align 1, !llvm.access.group [[ACC_GRP25]]
9565 // CHECK15-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i32 0, i32 2
9566 // CHECK15-NEXT:    [[TMP16:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP25]]
9567 // CHECK15-NEXT:    [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1
9568 // CHECK15-NEXT:    store i32 [[ADD15]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP25]]
9569 // CHECK15-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
9570 // CHECK15:       omp.body.continue:
9571 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
9572 // CHECK15:       omp.inner.for.inc:
9573 // CHECK15-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]]
9574 // CHECK15-NEXT:    [[ADD16:%.*]] = add i32 [[TMP17]], 1
9575 // CHECK15-NEXT:    store i32 [[ADD16]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]]
9576 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]
9577 // CHECK15:       omp.inner.for.end:
9578 // CHECK15-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
9579 // CHECK15-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
9580 // CHECK15-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
9581 // CHECK15-NEXT:    [[SUB17:%.*]] = sub i32 [[TMP19]], [[TMP20]]
9582 // CHECK15-NEXT:    [[SUB18:%.*]] = sub i32 [[SUB17]], 1
9583 // CHECK15-NEXT:    [[ADD19:%.*]] = add i32 [[SUB18]], 1
9584 // CHECK15-NEXT:    [[DIV20:%.*]] = udiv i32 [[ADD19]], 1
9585 // CHECK15-NEXT:    [[MUL21:%.*]] = mul i32 [[DIV20]], 1
9586 // CHECK15-NEXT:    [[ADD22:%.*]] = add i32 [[TMP18]], [[MUL21]]
9587 // CHECK15-NEXT:    store i32 [[ADD22]], ptr [[I5]], align 4
9588 // CHECK15-NEXT:    br label [[SIMD_IF_END]]
9589 // CHECK15:       simd.if.end:
9590 // CHECK15-NEXT:    [[TMP21:%.*]] = load i32, ptr [[A]], align 4
9591 // CHECK15-NEXT:    ret i32 [[TMP21]]
9592 //
9593 //
9594 // CHECK15-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
9595 // CHECK15-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat {
9596 // CHECK15-NEXT:  entry:
9597 // CHECK15-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
9598 // CHECK15-NEXT:    [[A:%.*]] = alloca i32, align 4
9599 // CHECK15-NEXT:    [[AA:%.*]] = alloca i16, align 2
9600 // CHECK15-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
9601 // CHECK15-NEXT:    [[TMP:%.*]] = alloca i32, align 4
9602 // CHECK15-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
9603 // CHECK15-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
9604 // CHECK15-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
9605 // CHECK15-NEXT:    [[I:%.*]] = alloca i32, align 4
9606 // CHECK15-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
9607 // CHECK15-NEXT:    store i32 0, ptr [[A]], align 4
9608 // CHECK15-NEXT:    store i16 0, ptr [[AA]], align 2
9609 // CHECK15-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
9610 // CHECK15-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4
9611 // CHECK15-NEXT:    [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
9612 // CHECK15-NEXT:    store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4
9613 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
9614 // CHECK15:       omp.inner.for.cond:
9615 // CHECK15-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28:![0-9]+]]
9616 // CHECK15-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP28]]
9617 // CHECK15-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
9618 // CHECK15-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
9619 // CHECK15:       omp.inner.for.body:
9620 // CHECK15-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]]
9621 // CHECK15-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
9622 // CHECK15-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
9623 // CHECK15-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP28]]
9624 // CHECK15-NEXT:    [[TMP4:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP28]]
9625 // CHECK15-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
9626 // CHECK15-NEXT:    store i32 [[ADD1]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP28]]
9627 // CHECK15-NEXT:    [[TMP5:%.*]] = load i16, ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP28]]
9628 // CHECK15-NEXT:    [[CONV:%.*]] = sext i16 [[TMP5]] to i32
9629 // CHECK15-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
9630 // CHECK15-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
9631 // CHECK15-NEXT:    store i16 [[CONV3]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP28]]
9632 // CHECK15-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i32 0, i32 2
9633 // CHECK15-NEXT:    [[TMP6:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP28]]
9634 // CHECK15-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1
9635 // CHECK15-NEXT:    store i32 [[ADD4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP28]]
9636 // CHECK15-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
9637 // CHECK15:       omp.body.continue:
9638 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
9639 // CHECK15:       omp.inner.for.inc:
9640 // CHECK15-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]]
9641 // CHECK15-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP7]], 1
9642 // CHECK15-NEXT:    store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]]
9643 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]]
9644 // CHECK15:       omp.inner.for.end:
9645 // CHECK15-NEXT:    store i32 10, ptr [[I]], align 4
9646 // CHECK15-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A]], align 4
9647 // CHECK15-NEXT:    ret i32 [[TMP8]]
9648 //
9649 //
9650 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97
9651 // CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] {
9652 // CHECK17-NEXT:  entry:
9653 // CHECK17-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
9654 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
9655 // CHECK17-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
9656 // CHECK17-NEXT:    [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8
9657 // CHECK17-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
9658 // CHECK17-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])
9659 // CHECK17-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
9660 // CHECK17-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
9661 // CHECK17-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
9662 // CHECK17-NEXT:    store i64 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 8
9663 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
9664 // CHECK17-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4
9665 // CHECK17-NEXT:    call void @__kmpc_push_num_teams(ptr @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
9666 // CHECK17-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
9667 // CHECK17-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
9668 // CHECK17-NEXT:    [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8
9669 // CHECK17-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.omp_outlined, i64 [[TMP4]])
9670 // CHECK17-NEXT:    ret void
9671 //
9672 //
9673 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.omp_outlined
9674 // CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {
9675 // CHECK17-NEXT:  entry:
9676 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
9677 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
9678 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
9679 // CHECK17-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
9680 // CHECK17-NEXT:    [[TMP:%.*]] = alloca i32, align 4
9681 // CHECK17-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
9682 // CHECK17-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
9683 // CHECK17-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
9684 // CHECK17-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
9685 // CHECK17-NEXT:    [[I:%.*]] = alloca i32, align 4
9686 // CHECK17-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
9687 // CHECK17-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
9688 // CHECK17-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
9689 // CHECK17-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
9690 // CHECK17-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4
9691 // CHECK17-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
9692 // CHECK17-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
9693 // CHECK17-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
9694 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
9695 // CHECK17-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
9696 // CHECK17-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
9697 // CHECK17-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
9698 // CHECK17-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
9699 // CHECK17:       cond.true:
9700 // CHECK17-NEXT:    br label [[COND_END:%.*]]
9701 // CHECK17:       cond.false:
9702 // CHECK17-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
9703 // CHECK17-NEXT:    br label [[COND_END]]
9704 // CHECK17:       cond.end:
9705 // CHECK17-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
9706 // CHECK17-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
9707 // CHECK17-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
9708 // CHECK17-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
9709 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
9710 // CHECK17:       omp.inner.for.cond:
9711 // CHECK17-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11:![0-9]+]]
9712 // CHECK17-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP11]]
9713 // CHECK17-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
9714 // CHECK17-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
9715 // CHECK17:       omp.inner.for.body:
9716 // CHECK17-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]
9717 // CHECK17-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
9718 // CHECK17-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
9719 // CHECK17-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]]
9720 // CHECK17-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
9721 // CHECK17:       omp.body.continue:
9722 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
9723 // CHECK17:       omp.inner.for.inc:
9724 // CHECK17-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]
9725 // CHECK17-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
9726 // CHECK17-NEXT:    store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]
9727 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
9728 // CHECK17:       omp.inner.for.end:
9729 // CHECK17-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
9730 // CHECK17:       omp.loop.exit:
9731 // CHECK17-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
9732 // CHECK17-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
9733 // CHECK17-NEXT:    [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
9734 // CHECK17-NEXT:    br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
9735 // CHECK17:       .omp.final.then:
9736 // CHECK17-NEXT:    store i32 10, ptr [[I]], align 4
9737 // CHECK17-NEXT:    br label [[DOTOMP_FINAL_DONE]]
9738 // CHECK17:       .omp.final.done:
9739 // CHECK17-NEXT:    ret void
9740 //
9741 //
9742 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
9743 // CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {
9744 // CHECK17-NEXT:  entry:
9745 // CHECK17-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
9746 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
9747 // CHECK17-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
9748 // CHECK17-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
9749 // CHECK17-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
9750 // CHECK17-NEXT:    [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2
9751 // CHECK17-NEXT:    store i16 [[TMP0]], ptr [[AA_CASTED]], align 2
9752 // CHECK17-NEXT:    [[TMP1:%.*]] = load i64, ptr [[AA_CASTED]], align 8
9753 // CHECK17-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined, i64 [[TMP1]])
9754 // CHECK17-NEXT:    ret void
9755 //
9756 //
9757 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined
9758 // CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {
9759 // CHECK17-NEXT:  entry:
9760 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
9761 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
9762 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
9763 // CHECK17-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
9764 // CHECK17-NEXT:    [[TMP:%.*]] = alloca i32, align 4
9765 // CHECK17-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
9766 // CHECK17-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
9767 // CHECK17-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
9768 // CHECK17-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
9769 // CHECK17-NEXT:    [[I:%.*]] = alloca i32, align 4
9770 // CHECK17-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
9771 // CHECK17-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
9772 // CHECK17-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
9773 // CHECK17-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
9774 // CHECK17-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4
9775 // CHECK17-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
9776 // CHECK17-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
9777 // CHECK17-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
9778 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
9779 // CHECK17-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
9780 // CHECK17-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
9781 // CHECK17-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
9782 // CHECK17-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
9783 // CHECK17:       cond.true:
9784 // CHECK17-NEXT:    br label [[COND_END:%.*]]
9785 // CHECK17:       cond.false:
9786 // CHECK17-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
9787 // CHECK17-NEXT:    br label [[COND_END]]
9788 // CHECK17:       cond.end:
9789 // CHECK17-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
9790 // CHECK17-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
9791 // CHECK17-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
9792 // CHECK17-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
9793 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
9794 // CHECK17:       omp.inner.for.cond:
9795 // CHECK17-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18:![0-9]+]]
9796 // CHECK17-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP18]]
9797 // CHECK17-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
9798 // CHECK17-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
9799 // CHECK17:       omp.inner.for.body:
9800 // CHECK17-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]]
9801 // CHECK17-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
9802 // CHECK17-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
9803 // CHECK17-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]]
9804 // CHECK17-NEXT:    [[TMP8:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP18]]
9805 // CHECK17-NEXT:    [[CONV:%.*]] = sext i16 [[TMP8]] to i32
9806 // CHECK17-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
9807 // CHECK17-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
9808 // CHECK17-NEXT:    store i16 [[CONV3]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP18]]
9809 // CHECK17-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
9810 // CHECK17:       omp.body.continue:
9811 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
9812 // CHECK17:       omp.inner.for.inc:
9813 // CHECK17-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]]
9814 // CHECK17-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP9]], 1
9815 // CHECK17-NEXT:    store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]]
9816 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
9817 // CHECK17:       omp.inner.for.end:
9818 // CHECK17-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
9819 // CHECK17:       omp.loop.exit:
9820 // CHECK17-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
9821 // CHECK17-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
9822 // CHECK17-NEXT:    [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
9823 // CHECK17-NEXT:    br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
9824 // CHECK17:       .omp.final.then:
9825 // CHECK17-NEXT:    store i32 10, ptr [[I]], align 4
9826 // CHECK17-NEXT:    br label [[DOTOMP_FINAL_DONE]]
9827 // CHECK17:       .omp.final.done:
9828 // CHECK17-NEXT:    ret void
9829 //
9830 //
9831 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118
9832 // CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {
9833 // CHECK17-NEXT:  entry:
9834 // CHECK17-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
9835 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
9836 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
9837 // CHECK17-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
9838 // CHECK17-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
9839 // CHECK17-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
9840 // CHECK17-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
9841 // CHECK17-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
9842 // CHECK17-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
9843 // CHECK17-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 4
9844 // CHECK17-NEXT:    [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8
9845 // CHECK17-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2
9846 // CHECK17-NEXT:    store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
9847 // CHECK17-NEXT:    [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8
9848 // CHECK17-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined, i64 [[TMP1]], i64 [[TMP3]])
9849 // CHECK17-NEXT:    ret void
9850 //
9851 //
9852 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined
9853 // CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {
9854 // CHECK17-NEXT:  entry:
9855 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
9856 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
9857 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
9858 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
9859 // CHECK17-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
9860 // CHECK17-NEXT:    [[TMP:%.*]] = alloca i32, align 4
9861 // CHECK17-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
9862 // CHECK17-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
9863 // CHECK17-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
9864 // CHECK17-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
9865 // CHECK17-NEXT:    [[I:%.*]] = alloca i32, align 4
9866 // CHECK17-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
9867 // CHECK17-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
9868 // CHECK17-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
9869 // CHECK17-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
9870 // CHECK17-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
9871 // CHECK17-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4
9872 // CHECK17-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
9873 // CHECK17-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
9874 // CHECK17-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
9875 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
9876 // CHECK17-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
9877 // CHECK17-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
9878 // CHECK17-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
9879 // CHECK17-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
9880 // CHECK17:       cond.true:
9881 // CHECK17-NEXT:    br label [[COND_END:%.*]]
9882 // CHECK17:       cond.false:
9883 // CHECK17-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
9884 // CHECK17-NEXT:    br label [[COND_END]]
9885 // CHECK17:       cond.end:
9886 // CHECK17-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
9887 // CHECK17-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
9888 // CHECK17-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
9889 // CHECK17-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
9890 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
9891 // CHECK17:       omp.inner.for.cond:
9892 // CHECK17-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21:![0-9]+]]
9893 // CHECK17-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP21]]
9894 // CHECK17-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
9895 // CHECK17-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
9896 // CHECK17:       omp.inner.for.body:
9897 // CHECK17-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]]
9898 // CHECK17-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
9899 // CHECK17-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
9900 // CHECK17-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP21]]
9901 // CHECK17-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP21]]
9902 // CHECK17-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
9903 // CHECK17-NEXT:    store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP21]]
9904 // CHECK17-NEXT:    [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP21]]
9905 // CHECK17-NEXT:    [[CONV:%.*]] = sext i16 [[TMP9]] to i32
9906 // CHECK17-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV]], 1
9907 // CHECK17-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
9908 // CHECK17-NEXT:    store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP21]]
9909 // CHECK17-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
9910 // CHECK17:       omp.body.continue:
9911 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
9912 // CHECK17:       omp.inner.for.inc:
9913 // CHECK17-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]]
9914 // CHECK17-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP10]], 1
9915 // CHECK17-NEXT:    store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]]
9916 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
9917 // CHECK17:       omp.inner.for.end:
9918 // CHECK17-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
9919 // CHECK17:       omp.loop.exit:
9920 // CHECK17-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
9921 // CHECK17-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
9922 // CHECK17-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
9923 // CHECK17-NEXT:    br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
9924 // CHECK17:       .omp.final.then:
9925 // CHECK17-NEXT:    store i32 10, ptr [[I]], align 4
9926 // CHECK17-NEXT:    br label [[DOTOMP_FINAL_DONE]]
9927 // CHECK17:       .omp.final.done:
9928 // CHECK17-NEXT:    ret void
9929 //
9930 //
9931 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142
9932 // CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] {
9933 // CHECK17-NEXT:  entry:
9934 // CHECK17-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
9935 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
9936 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
9937 // CHECK17-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
9938 // CHECK17-NEXT:    [[BN_ADDR:%.*]] = alloca ptr, align 8
9939 // CHECK17-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
9940 // CHECK17-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
9941 // CHECK17-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
9942 // CHECK17-NEXT:    [[CN_ADDR:%.*]] = alloca ptr, align 8
9943 // CHECK17-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
9944 // CHECK17-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
9945 // CHECK17-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
9946 // CHECK17-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
9947 // CHECK17-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
9948 // CHECK17-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
9949 // CHECK17-NEXT:    store ptr [[BN]], ptr [[BN_ADDR]], align 8
9950 // CHECK17-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
9951 // CHECK17-NEXT:    store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
9952 // CHECK17-NEXT:    store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8
9953 // CHECK17-NEXT:    store ptr [[CN]], ptr [[CN_ADDR]], align 8
9954 // CHECK17-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
9955 // CHECK17-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
9956 // CHECK17-NEXT:    [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
9957 // CHECK17-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8
9958 // CHECK17-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
9959 // CHECK17-NEXT:    [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
9960 // CHECK17-NEXT:    [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8
9961 // CHECK17-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8
9962 // CHECK17-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8
9963 // CHECK17-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
9964 // CHECK17-NEXT:    store i32 [[TMP8]], ptr [[A_CASTED]], align 4
9965 // CHECK17-NEXT:    [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 8
9966 // CHECK17-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.omp_outlined, i64 [[TMP9]], ptr [[TMP0]], i64 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]])
9967 // CHECK17-NEXT:    ret void
9968 //
9969 //
9970 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.omp_outlined
9971 // CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] {
9972 // CHECK17-NEXT:  entry:
9973 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
9974 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
9975 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
9976 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
9977 // CHECK17-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
9978 // CHECK17-NEXT:    [[BN_ADDR:%.*]] = alloca ptr, align 8
9979 // CHECK17-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
9980 // CHECK17-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
9981 // CHECK17-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
9982 // CHECK17-NEXT:    [[CN_ADDR:%.*]] = alloca ptr, align 8
9983 // CHECK17-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
9984 // CHECK17-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
9985 // CHECK17-NEXT:    [[TMP:%.*]] = alloca i32, align 4
9986 // CHECK17-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
9987 // CHECK17-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
9988 // CHECK17-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
9989 // CHECK17-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
9990 // CHECK17-NEXT:    [[I:%.*]] = alloca i32, align 4
9991 // CHECK17-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
9992 // CHECK17-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
9993 // CHECK17-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
9994 // CHECK17-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
9995 // CHECK17-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
9996 // CHECK17-NEXT:    store ptr [[BN]], ptr [[BN_ADDR]], align 8
9997 // CHECK17-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
9998 // CHECK17-NEXT:    store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
9999 // CHECK17-NEXT:    store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8
10000 // CHECK17-NEXT:    store ptr [[CN]], ptr [[CN_ADDR]], align 8
10001 // CHECK17-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
10002 // CHECK17-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
10003 // CHECK17-NEXT:    [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
10004 // CHECK17-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8
10005 // CHECK17-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
10006 // CHECK17-NEXT:    [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
10007 // CHECK17-NEXT:    [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8
10008 // CHECK17-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8
10009 // CHECK17-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8
10010 // CHECK17-NEXT:    [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 0
10011 // CHECK17-NEXT:    call void @llvm.assume(i1 true) [ "align"(ptr [[ARRAYDECAY]], i64 16) ]
10012 // CHECK17-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
10013 // CHECK17-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4
10014 // CHECK17-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
10015 // CHECK17-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
10016 // CHECK17-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
10017 // CHECK17-NEXT:    [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
10018 // CHECK17-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP9]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
10019 // CHECK17-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
10020 // CHECK17-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 9
10021 // CHECK17-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
10022 // CHECK17:       cond.true:
10023 // CHECK17-NEXT:    br label [[COND_END:%.*]]
10024 // CHECK17:       cond.false:
10025 // CHECK17-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
10026 // CHECK17-NEXT:    br label [[COND_END]]
10027 // CHECK17:       cond.end:
10028 // CHECK17-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
10029 // CHECK17-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
10030 // CHECK17-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
10031 // CHECK17-NEXT:    store i32 [[TMP12]], ptr [[DOTOMP_IV]], align 4
10032 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
10033 // CHECK17:       omp.inner.for.cond:
10034 // CHECK17-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24:![0-9]+]]
10035 // CHECK17-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP24]]
10036 // CHECK17-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
10037 // CHECK17-NEXT:    br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
10038 // CHECK17:       omp.inner.for.body:
10039 // CHECK17-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]]
10040 // CHECK17-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
10041 // CHECK17-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
10042 // CHECK17-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP24]]
10043 // CHECK17-NEXT:    [[TMP16:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP24]]
10044 // CHECK17-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1
10045 // CHECK17-NEXT:    store i32 [[ADD6]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP24]]
10046 // CHECK17-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 2
10047 // CHECK17-NEXT:    [[TMP17:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP24]]
10048 // CHECK17-NEXT:    [[CONV:%.*]] = fpext float [[TMP17]] to double
10049 // CHECK17-NEXT:    [[ADD7:%.*]] = fadd double [[CONV]], 1.000000e+00
10050 // CHECK17-NEXT:    [[CONV8:%.*]] = fptrunc double [[ADD7]] to float
10051 // CHECK17-NEXT:    store float [[CONV8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP24]]
10052 // CHECK17-NEXT:    [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 3
10053 // CHECK17-NEXT:    [[TMP18:%.*]] = load float, ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP24]]
10054 // CHECK17-NEXT:    [[CONV10:%.*]] = fpext float [[TMP18]] to double
10055 // CHECK17-NEXT:    [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00
10056 // CHECK17-NEXT:    [[CONV12:%.*]] = fptrunc double [[ADD11]] to float
10057 // CHECK17-NEXT:    store float [[CONV12]], ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP24]]
10058 // CHECK17-NEXT:    [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 1
10059 // CHECK17-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX13]], i64 0, i64 2
10060 // CHECK17-NEXT:    [[TMP19:%.*]] = load double, ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP24]]
10061 // CHECK17-NEXT:    [[ADD15:%.*]] = fadd double [[TMP19]], 1.000000e+00
10062 // CHECK17-NEXT:    store double [[ADD15]], ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP24]]
10063 // CHECK17-NEXT:    [[TMP20:%.*]] = mul nsw i64 1, [[TMP5]]
10064 // CHECK17-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i64 [[TMP20]]
10065 // CHECK17-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX16]], i64 3
10066 // CHECK17-NEXT:    [[TMP21:%.*]] = load double, ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP24]]
10067 // CHECK17-NEXT:    [[ADD18:%.*]] = fadd double [[TMP21]], 1.000000e+00
10068 // CHECK17-NEXT:    store double [[ADD18]], ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP24]]
10069 // CHECK17-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0
10070 // CHECK17-NEXT:    [[TMP22:%.*]] = load i64, ptr [[X]], align 8, !llvm.access.group [[ACC_GRP24]]
10071 // CHECK17-NEXT:    [[ADD19:%.*]] = add nsw i64 [[TMP22]], 1
10072 // CHECK17-NEXT:    store i64 [[ADD19]], ptr [[X]], align 8, !llvm.access.group [[ACC_GRP24]]
10073 // CHECK17-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1
10074 // CHECK17-NEXT:    [[TMP23:%.*]] = load i8, ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP24]]
10075 // CHECK17-NEXT:    [[CONV20:%.*]] = sext i8 [[TMP23]] to i32
10076 // CHECK17-NEXT:    [[ADD21:%.*]] = add nsw i32 [[CONV20]], 1
10077 // CHECK17-NEXT:    [[CONV22:%.*]] = trunc i32 [[ADD21]] to i8
10078 // CHECK17-NEXT:    store i8 [[CONV22]], ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP24]]
10079 // CHECK17-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
10080 // CHECK17:       omp.body.continue:
10081 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
10082 // CHECK17:       omp.inner.for.inc:
10083 // CHECK17-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]]
10084 // CHECK17-NEXT:    [[ADD23:%.*]] = add nsw i32 [[TMP24]], 1
10085 // CHECK17-NEXT:    store i32 [[ADD23]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]]
10086 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
10087 // CHECK17:       omp.inner.for.end:
10088 // CHECK17-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
10089 // CHECK17:       omp.loop.exit:
10090 // CHECK17-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP9]])
10091 // CHECK17-NEXT:    [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
10092 // CHECK17-NEXT:    [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
10093 // CHECK17-NEXT:    br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
10094 // CHECK17:       .omp.final.then:
10095 // CHECK17-NEXT:    store i32 10, ptr [[I]], align 4
10096 // CHECK17-NEXT:    br label [[DOTOMP_FINAL_DONE]]
10097 // CHECK17:       .omp.final.done:
10098 // CHECK17-NEXT:    ret void
10099 //
10100 //
10101 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197
10102 // CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
10103 // CHECK17-NEXT:  entry:
10104 // CHECK17-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
10105 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
10106 // CHECK17-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
10107 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
10108 // CHECK17-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
10109 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
10110 // CHECK17-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
10111 // CHECK17-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8
10112 // CHECK17-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
10113 // CHECK17-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
10114 // CHECK17-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
10115 // CHECK17-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
10116 // CHECK17-NEXT:    store i64 [[N]], ptr [[N_ADDR]], align 8
10117 // CHECK17-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
10118 // CHECK17-NEXT:    store i64 [[AAA]], ptr [[AAA_ADDR]], align 8
10119 // CHECK17-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
10120 // CHECK17-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
10121 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
10122 // CHECK17-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 4
10123 // CHECK17-NEXT:    [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8
10124 // CHECK17-NEXT:    [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4
10125 // CHECK17-NEXT:    store i32 [[TMP3]], ptr [[N_CASTED]], align 4
10126 // CHECK17-NEXT:    [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8
10127 // CHECK17-NEXT:    [[TMP5:%.*]] = load i16, ptr [[AA_ADDR]], align 2
10128 // CHECK17-NEXT:    store i16 [[TMP5]], ptr [[AA_CASTED]], align 2
10129 // CHECK17-NEXT:    [[TMP6:%.*]] = load i64, ptr [[AA_CASTED]], align 8
10130 // CHECK17-NEXT:    [[TMP7:%.*]] = load i8, ptr [[AAA_ADDR]], align 1
10131 // CHECK17-NEXT:    store i8 [[TMP7]], ptr [[AAA_CASTED]], align 1
10132 // CHECK17-NEXT:    [[TMP8:%.*]] = load i64, ptr [[AAA_CASTED]], align 8
10133 // CHECK17-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], ptr [[TMP0]])
10134 // CHECK17-NEXT:    ret void
10135 //
10136 //
10137 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.omp_outlined
10138 // CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
10139 // CHECK17-NEXT:  entry:
10140 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
10141 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
10142 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
10143 // CHECK17-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
10144 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
10145 // CHECK17-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
10146 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
10147 // CHECK17-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
10148 // CHECK17-NEXT:    [[TMP:%.*]] = alloca i32, align 4
10149 // CHECK17-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
10150 // CHECK17-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
10151 // CHECK17-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
10152 // CHECK17-NEXT:    [[I:%.*]] = alloca i32, align 4
10153 // CHECK17-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
10154 // CHECK17-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
10155 // CHECK17-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
10156 // CHECK17-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
10157 // CHECK17-NEXT:    [[I5:%.*]] = alloca i32, align 4
10158 // CHECK17-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
10159 // CHECK17-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
10160 // CHECK17-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
10161 // CHECK17-NEXT:    store i64 [[N]], ptr [[N_ADDR]], align 8
10162 // CHECK17-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
10163 // CHECK17-NEXT:    store i64 [[AAA]], ptr [[AAA_ADDR]], align 8
10164 // CHECK17-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
10165 // CHECK17-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
10166 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
10167 // CHECK17-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
10168 // CHECK17-NEXT:    [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
10169 // CHECK17-NEXT:    store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
10170 // CHECK17-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
10171 // CHECK17-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
10172 // CHECK17-NEXT:    [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
10173 // CHECK17-NEXT:    [[SUB3:%.*]] = sub i32 [[SUB]], 1
10174 // CHECK17-NEXT:    [[ADD:%.*]] = add i32 [[SUB3]], 1
10175 // CHECK17-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
10176 // CHECK17-NEXT:    [[SUB4:%.*]] = sub i32 [[DIV]], 1
10177 // CHECK17-NEXT:    store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 4
10178 // CHECK17-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
10179 // CHECK17-NEXT:    store i32 [[TMP5]], ptr [[I]], align 4
10180 // CHECK17-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
10181 // CHECK17-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
10182 // CHECK17-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
10183 // CHECK17-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
10184 // CHECK17:       omp.precond.then:
10185 // CHECK17-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
10186 // CHECK17-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
10187 // CHECK17-NEXT:    store i32 [[TMP8]], ptr [[DOTOMP_UB]], align 4
10188 // CHECK17-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
10189 // CHECK17-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
10190 // CHECK17-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
10191 // CHECK17-NEXT:    [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4
10192 // CHECK17-NEXT:    call void @__kmpc_for_static_init_4u(ptr @[[GLOB1]], i32 [[TMP10]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
10193 // CHECK17-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
10194 // CHECK17-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
10195 // CHECK17-NEXT:    [[CMP6:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]]
10196 // CHECK17-NEXT:    br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
10197 // CHECK17:       cond.true:
10198 // CHECK17-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
10199 // CHECK17-NEXT:    br label [[COND_END:%.*]]
10200 // CHECK17:       cond.false:
10201 // CHECK17-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
10202 // CHECK17-NEXT:    br label [[COND_END]]
10203 // CHECK17:       cond.end:
10204 // CHECK17-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ]
10205 // CHECK17-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
10206 // CHECK17-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
10207 // CHECK17-NEXT:    store i32 [[TMP15]], ptr [[DOTOMP_IV]], align 4
10208 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
10209 // CHECK17:       omp.inner.for.cond:
10210 // CHECK17-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27:![0-9]+]]
10211 // CHECK17-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP27]]
10212 // CHECK17-NEXT:    [[ADD7:%.*]] = add i32 [[TMP17]], 1
10213 // CHECK17-NEXT:    [[CMP8:%.*]] = icmp ult i32 [[TMP16]], [[ADD7]]
10214 // CHECK17-NEXT:    br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
10215 // CHECK17:       omp.inner.for.body:
10216 // CHECK17-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group [[ACC_GRP27]]
10217 // CHECK17-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]]
10218 // CHECK17-NEXT:    [[MUL:%.*]] = mul i32 [[TMP19]], 1
10219 // CHECK17-NEXT:    [[ADD9:%.*]] = add i32 [[TMP18]], [[MUL]]
10220 // CHECK17-NEXT:    store i32 [[ADD9]], ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP27]]
10221 // CHECK17-NEXT:    [[TMP20:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP27]]
10222 // CHECK17-NEXT:    [[ADD10:%.*]] = add nsw i32 [[TMP20]], 1
10223 // CHECK17-NEXT:    store i32 [[ADD10]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP27]]
10224 // CHECK17-NEXT:    [[TMP21:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP27]]
10225 // CHECK17-NEXT:    [[CONV:%.*]] = sext i16 [[TMP21]] to i32
10226 // CHECK17-NEXT:    [[ADD11:%.*]] = add nsw i32 [[CONV]], 1
10227 // CHECK17-NEXT:    [[CONV12:%.*]] = trunc i32 [[ADD11]] to i16
10228 // CHECK17-NEXT:    store i16 [[CONV12]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP27]]
10229 // CHECK17-NEXT:    [[TMP22:%.*]] = load i8, ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP27]]
10230 // CHECK17-NEXT:    [[CONV13:%.*]] = sext i8 [[TMP22]] to i32
10231 // CHECK17-NEXT:    [[ADD14:%.*]] = add nsw i32 [[CONV13]], 1
10232 // CHECK17-NEXT:    [[CONV15:%.*]] = trunc i32 [[ADD14]] to i8
10233 // CHECK17-NEXT:    store i8 [[CONV15]], ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP27]]
10234 // CHECK17-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2
10235 // CHECK17-NEXT:    [[TMP23:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP27]]
10236 // CHECK17-NEXT:    [[ADD16:%.*]] = add nsw i32 [[TMP23]], 1
10237 // CHECK17-NEXT:    store i32 [[ADD16]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP27]]
10238 // CHECK17-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
10239 // CHECK17:       omp.body.continue:
10240 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
10241 // CHECK17:       omp.inner.for.inc:
10242 // CHECK17-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]]
10243 // CHECK17-NEXT:    [[ADD17:%.*]] = add i32 [[TMP24]], 1
10244 // CHECK17-NEXT:    store i32 [[ADD17]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]]
10245 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]
10246 // CHECK17:       omp.inner.for.end:
10247 // CHECK17-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
10248 // CHECK17:       omp.loop.exit:
10249 // CHECK17-NEXT:    [[TMP25:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
10250 // CHECK17-NEXT:    [[TMP26:%.*]] = load i32, ptr [[TMP25]], align 4
10251 // CHECK17-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP26]])
10252 // CHECK17-NEXT:    [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
10253 // CHECK17-NEXT:    [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
10254 // CHECK17-NEXT:    br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
10255 // CHECK17:       .omp.final.then:
10256 // CHECK17-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
10257 // CHECK17-NEXT:    [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
10258 // CHECK17-NEXT:    [[TMP31:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
10259 // CHECK17-NEXT:    [[SUB18:%.*]] = sub i32 [[TMP30]], [[TMP31]]
10260 // CHECK17-NEXT:    [[SUB19:%.*]] = sub i32 [[SUB18]], 1
10261 // CHECK17-NEXT:    [[ADD20:%.*]] = add i32 [[SUB19]], 1
10262 // CHECK17-NEXT:    [[DIV21:%.*]] = udiv i32 [[ADD20]], 1
10263 // CHECK17-NEXT:    [[MUL22:%.*]] = mul i32 [[DIV21]], 1
10264 // CHECK17-NEXT:    [[ADD23:%.*]] = add i32 [[TMP29]], [[MUL22]]
10265 // CHECK17-NEXT:    store i32 [[ADD23]], ptr [[I5]], align 4
10266 // CHECK17-NEXT:    br label [[DOTOMP_FINAL_DONE]]
10267 // CHECK17:       .omp.final.done:
10268 // CHECK17-NEXT:    br label [[OMP_PRECOND_END]]
10269 // CHECK17:       omp.precond.end:
10270 // CHECK17-NEXT:    ret void
10271 //
10272 //
10273 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215
10274 // CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
10275 // CHECK17-NEXT:  entry:
10276 // CHECK17-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
10277 // CHECK17-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
10278 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
10279 // CHECK17-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
10280 // CHECK17-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
10281 // CHECK17-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
10282 // CHECK17-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
10283 // CHECK17-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
10284 // CHECK17-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
10285 // CHECK17-NEXT:    store i64 [[B]], ptr [[B_ADDR]], align 8
10286 // CHECK17-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
10287 // CHECK17-NEXT:    store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
10288 // CHECK17-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
10289 // CHECK17-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
10290 // CHECK17-NEXT:    [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
10291 // CHECK17-NEXT:    [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
10292 // CHECK17-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
10293 // CHECK17-NEXT:    [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4
10294 // CHECK17-NEXT:    store i32 [[TMP4]], ptr [[B_CASTED]], align 4
10295 // CHECK17-NEXT:    [[TMP5:%.*]] = load i64, ptr [[B_CASTED]], align 8
10296 // CHECK17-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.omp_outlined, ptr [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], ptr [[TMP3]])
10297 // CHECK17-NEXT:    ret void
10298 //
10299 //
10300 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.omp_outlined
10301 // CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
10302 // CHECK17-NEXT:  entry:
10303 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
10304 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
10305 // CHECK17-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
10306 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
10307 // CHECK17-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
10308 // CHECK17-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
10309 // CHECK17-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
10310 // CHECK17-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
10311 // CHECK17-NEXT:    [[TMP:%.*]] = alloca i32, align 4
10312 // CHECK17-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
10313 // CHECK17-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
10314 // CHECK17-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
10315 // CHECK17-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
10316 // CHECK17-NEXT:    [[I:%.*]] = alloca i32, align 4
10317 // CHECK17-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
10318 // CHECK17-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
10319 // CHECK17-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
10320 // CHECK17-NEXT:    store i64 [[B]], ptr [[B_ADDR]], align 8
10321 // CHECK17-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
10322 // CHECK17-NEXT:    store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
10323 // CHECK17-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
10324 // CHECK17-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
10325 // CHECK17-NEXT:    [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
10326 // CHECK17-NEXT:    [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
10327 // CHECK17-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
10328 // CHECK17-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
10329 // CHECK17-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4
10330 // CHECK17-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
10331 // CHECK17-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
10332 // CHECK17-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
10333 // CHECK17-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
10334 // CHECK17-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
10335 // CHECK17-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
10336 // CHECK17-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9
10337 // CHECK17-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
10338 // CHECK17:       cond.true:
10339 // CHECK17-NEXT:    br label [[COND_END:%.*]]
10340 // CHECK17:       cond.false:
10341 // CHECK17-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
10342 // CHECK17-NEXT:    br label [[COND_END]]
10343 // CHECK17:       cond.end:
10344 // CHECK17-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
10345 // CHECK17-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
10346 // CHECK17-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
10347 // CHECK17-NEXT:    store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4
10348 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
10349 // CHECK17:       omp.inner.for.cond:
10350 // CHECK17-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30:![0-9]+]]
10351 // CHECK17-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP30]]
10352 // CHECK17-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
10353 // CHECK17-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
10354 // CHECK17:       omp.inner.for.body:
10355 // CHECK17-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30]]
10356 // CHECK17-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
10357 // CHECK17-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
10358 // CHECK17-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP30]]
10359 // CHECK17-NEXT:    [[TMP12:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP30]]
10360 // CHECK17-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP12]] to double
10361 // CHECK17-NEXT:    [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00
10362 // CHECK17-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0
10363 // CHECK17-NEXT:    store double [[ADD4]], ptr [[A]], align 8, !llvm.access.group [[ACC_GRP30]]
10364 // CHECK17-NEXT:    [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0
10365 // CHECK17-NEXT:    [[TMP13:%.*]] = load double, ptr [[A5]], align 8, !llvm.access.group [[ACC_GRP30]]
10366 // CHECK17-NEXT:    [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
10367 // CHECK17-NEXT:    store double [[INC]], ptr [[A5]], align 8, !llvm.access.group [[ACC_GRP30]]
10368 // CHECK17-NEXT:    [[CONV6:%.*]] = fptosi double [[INC]] to i16
10369 // CHECK17-NEXT:    [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]]
10370 // CHECK17-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i64 [[TMP14]]
10371 // CHECK17-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1
10372 // CHECK17-NEXT:    store i16 [[CONV6]], ptr [[ARRAYIDX7]], align 2, !llvm.access.group [[ACC_GRP30]]
10373 // CHECK17-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
10374 // CHECK17:       omp.body.continue:
10375 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
10376 // CHECK17:       omp.inner.for.inc:
10377 // CHECK17-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30]]
10378 // CHECK17-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1
10379 // CHECK17-NEXT:    store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30]]
10380 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]]
10381 // CHECK17:       omp.inner.for.end:
10382 // CHECK17-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
10383 // CHECK17:       omp.loop.exit:
10384 // CHECK17-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])
10385 // CHECK17-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
10386 // CHECK17-NEXT:    [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
10387 // CHECK17-NEXT:    br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
10388 // CHECK17:       .omp.final.then:
10389 // CHECK17-NEXT:    store i32 10, ptr [[I]], align 4
10390 // CHECK17-NEXT:    br label [[DOTOMP_FINAL_DONE]]
10391 // CHECK17:       .omp.final.done:
10392 // CHECK17-NEXT:    ret void
10393 //
10394 //
10395 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180
10396 // CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
10397 // CHECK17-NEXT:  entry:
10398 // CHECK17-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
10399 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
10400 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
10401 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
10402 // CHECK17-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
10403 // CHECK17-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
10404 // CHECK17-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
10405 // CHECK17-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
10406 // CHECK17-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
10407 // CHECK17-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
10408 // CHECK17-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
10409 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
10410 // CHECK17-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 4
10411 // CHECK17-NEXT:    [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8
10412 // CHECK17-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
10413 // CHECK17-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
10414 // CHECK17-NEXT:    [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8
10415 // CHECK17-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], ptr [[TMP0]])
10416 // CHECK17-NEXT:    ret void
10417 //
10418 //
10419 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.omp_outlined
10420 // CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
10421 // CHECK17-NEXT:  entry:
10422 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
10423 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
10424 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
10425 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
10426 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
10427 // CHECK17-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
10428 // CHECK17-NEXT:    [[TMP:%.*]] = alloca i32, align 4
10429 // CHECK17-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
10430 // CHECK17-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
10431 // CHECK17-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
10432 // CHECK17-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
10433 // CHECK17-NEXT:    [[I:%.*]] = alloca i32, align 4
10434 // CHECK17-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
10435 // CHECK17-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
10436 // CHECK17-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
10437 // CHECK17-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
10438 // CHECK17-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
10439 // CHECK17-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
10440 // CHECK17-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
10441 // CHECK17-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4
10442 // CHECK17-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
10443 // CHECK17-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
10444 // CHECK17-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
10445 // CHECK17-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
10446 // CHECK17-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
10447 // CHECK17-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
10448 // CHECK17-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
10449 // CHECK17-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
10450 // CHECK17:       cond.true:
10451 // CHECK17-NEXT:    br label [[COND_END:%.*]]
10452 // CHECK17:       cond.false:
10453 // CHECK17-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
10454 // CHECK17-NEXT:    br label [[COND_END]]
10455 // CHECK17:       cond.end:
10456 // CHECK17-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
10457 // CHECK17-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
10458 // CHECK17-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
10459 // CHECK17-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
10460 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
10461 // CHECK17:       omp.inner.for.cond:
10462 // CHECK17-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33:![0-9]+]]
10463 // CHECK17-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP33]]
10464 // CHECK17-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
10465 // CHECK17-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
10466 // CHECK17:       omp.inner.for.body:
10467 // CHECK17-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]]
10468 // CHECK17-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
10469 // CHECK17-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
10470 // CHECK17-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP33]]
10471 // CHECK17-NEXT:    [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP33]]
10472 // CHECK17-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
10473 // CHECK17-NEXT:    store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP33]]
10474 // CHECK17-NEXT:    [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP33]]
10475 // CHECK17-NEXT:    [[CONV:%.*]] = sext i16 [[TMP10]] to i32
10476 // CHECK17-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV]], 1
10477 // CHECK17-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
10478 // CHECK17-NEXT:    store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP33]]
10479 // CHECK17-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2
10480 // CHECK17-NEXT:    [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP33]]
10481 // CHECK17-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1
10482 // CHECK17-NEXT:    store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP33]]
10483 // CHECK17-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
10484 // CHECK17:       omp.body.continue:
10485 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
10486 // CHECK17:       omp.inner.for.inc:
10487 // CHECK17-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]]
10488 // CHECK17-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP12]], 1
10489 // CHECK17-NEXT:    store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]]
10490 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]]
10491 // CHECK17:       omp.inner.for.end:
10492 // CHECK17-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
10493 // CHECK17:       omp.loop.exit:
10494 // CHECK17-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])
10495 // CHECK17-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
10496 // CHECK17-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
10497 // CHECK17-NEXT:    br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
10498 // CHECK17:       .omp.final.then:
10499 // CHECK17-NEXT:    store i32 10, ptr [[I]], align 4
10500 // CHECK17-NEXT:    br label [[DOTOMP_FINAL_DONE]]
10501 // CHECK17:       .omp.final.done:
10502 // CHECK17-NEXT:    ret void
10503 //
10504 //
10505 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97
10506 // CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] {
10507 // CHECK19-NEXT:  entry:
10508 // CHECK19-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
10509 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
10510 // CHECK19-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
10511 // CHECK19-NEXT:    [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4
10512 // CHECK19-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
10513 // CHECK19-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])
10514 // CHECK19-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
10515 // CHECK19-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
10516 // CHECK19-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
10517 // CHECK19-NEXT:    store i32 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4
10518 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
10519 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4
10520 // CHECK19-NEXT:    call void @__kmpc_push_num_teams(ptr @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
10521 // CHECK19-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
10522 // CHECK19-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
10523 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4
10524 // CHECK19-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.omp_outlined, i32 [[TMP4]])
10525 // CHECK19-NEXT:    ret void
10526 //
10527 //
10528 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.omp_outlined
10529 // CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {
10530 // CHECK19-NEXT:  entry:
10531 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
10532 // CHECK19-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
10533 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
10534 // CHECK19-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
10535 // CHECK19-NEXT:    [[TMP:%.*]] = alloca i32, align 4
10536 // CHECK19-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
10537 // CHECK19-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
10538 // CHECK19-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
10539 // CHECK19-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
10540 // CHECK19-NEXT:    [[I:%.*]] = alloca i32, align 4
10541 // CHECK19-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
10542 // CHECK19-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
10543 // CHECK19-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
10544 // CHECK19-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
10545 // CHECK19-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4
10546 // CHECK19-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
10547 // CHECK19-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
10548 // CHECK19-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
10549 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
10550 // CHECK19-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
10551 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
10552 // CHECK19-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
10553 // CHECK19-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
10554 // CHECK19:       cond.true:
10555 // CHECK19-NEXT:    br label [[COND_END:%.*]]
10556 // CHECK19:       cond.false:
10557 // CHECK19-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
10558 // CHECK19-NEXT:    br label [[COND_END]]
10559 // CHECK19:       cond.end:
10560 // CHECK19-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
10561 // CHECK19-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
10562 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
10563 // CHECK19-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
10564 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
10565 // CHECK19:       omp.inner.for.cond:
10566 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12:![0-9]+]]
10567 // CHECK19-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP12]]
10568 // CHECK19-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
10569 // CHECK19-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
10570 // CHECK19:       omp.inner.for.body:
10571 // CHECK19-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]
10572 // CHECK19-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
10573 // CHECK19-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
10574 // CHECK19-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]]
10575 // CHECK19-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
10576 // CHECK19:       omp.body.continue:
10577 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
10578 // CHECK19:       omp.inner.for.inc:
10579 // CHECK19-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]
10580 // CHECK19-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
10581 // CHECK19-NEXT:    store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]
10582 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
10583 // CHECK19:       omp.inner.for.end:
10584 // CHECK19-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
10585 // CHECK19:       omp.loop.exit:
10586 // CHECK19-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
10587 // CHECK19-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
10588 // CHECK19-NEXT:    [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
10589 // CHECK19-NEXT:    br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
10590 // CHECK19:       .omp.final.then:
10591 // CHECK19-NEXT:    store i32 10, ptr [[I]], align 4
10592 // CHECK19-NEXT:    br label [[DOTOMP_FINAL_DONE]]
10593 // CHECK19:       .omp.final.done:
10594 // CHECK19-NEXT:    ret void
10595 //
10596 //
10597 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
10598 // CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {
10599 // CHECK19-NEXT:  entry:
10600 // CHECK19-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
10601 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
10602 // CHECK19-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
10603 // CHECK19-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
10604 // CHECK19-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
10605 // CHECK19-NEXT:    [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2
10606 // CHECK19-NEXT:    store i16 [[TMP0]], ptr [[AA_CASTED]], align 2
10607 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, ptr [[AA_CASTED]], align 4
10608 // CHECK19-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined, i32 [[TMP1]])
10609 // CHECK19-NEXT:    ret void
10610 //
10611 //
10612 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined
10613 // CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {
10614 // CHECK19-NEXT:  entry:
10615 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
10616 // CHECK19-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
10617 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
10618 // CHECK19-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
10619 // CHECK19-NEXT:    [[TMP:%.*]] = alloca i32, align 4
10620 // CHECK19-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
10621 // CHECK19-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
10622 // CHECK19-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
10623 // CHECK19-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
10624 // CHECK19-NEXT:    [[I:%.*]] = alloca i32, align 4
10625 // CHECK19-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
10626 // CHECK19-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
10627 // CHECK19-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
10628 // CHECK19-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
10629 // CHECK19-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4
10630 // CHECK19-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
10631 // CHECK19-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
10632 // CHECK19-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
10633 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
10634 // CHECK19-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
10635 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
10636 // CHECK19-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
10637 // CHECK19-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
10638 // CHECK19:       cond.true:
10639 // CHECK19-NEXT:    br label [[COND_END:%.*]]
10640 // CHECK19:       cond.false:
10641 // CHECK19-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
10642 // CHECK19-NEXT:    br label [[COND_END]]
10643 // CHECK19:       cond.end:
10644 // CHECK19-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
10645 // CHECK19-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
10646 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
10647 // CHECK19-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
10648 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
10649 // CHECK19:       omp.inner.for.cond:
10650 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19:![0-9]+]]
10651 // CHECK19-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP19]]
10652 // CHECK19-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
10653 // CHECK19-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
10654 // CHECK19:       omp.inner.for.body:
10655 // CHECK19-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]]
10656 // CHECK19-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
10657 // CHECK19-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
10658 // CHECK19-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]]
10659 // CHECK19-NEXT:    [[TMP8:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP19]]
10660 // CHECK19-NEXT:    [[CONV:%.*]] = sext i16 [[TMP8]] to i32
10661 // CHECK19-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
10662 // CHECK19-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
10663 // CHECK19-NEXT:    store i16 [[CONV3]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP19]]
10664 // CHECK19-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
10665 // CHECK19:       omp.body.continue:
10666 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
10667 // CHECK19:       omp.inner.for.inc:
10668 // CHECK19-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]]
10669 // CHECK19-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP9]], 1
10670 // CHECK19-NEXT:    store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]]
10671 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
10672 // CHECK19:       omp.inner.for.end:
10673 // CHECK19-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
10674 // CHECK19:       omp.loop.exit:
10675 // CHECK19-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
10676 // CHECK19-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
10677 // CHECK19-NEXT:    [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
10678 // CHECK19-NEXT:    br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
10679 // CHECK19:       .omp.final.then:
10680 // CHECK19-NEXT:    store i32 10, ptr [[I]], align 4
10681 // CHECK19-NEXT:    br label [[DOTOMP_FINAL_DONE]]
10682 // CHECK19:       .omp.final.done:
10683 // CHECK19-NEXT:    ret void
10684 //
10685 //
10686 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118
10687 // CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {
10688 // CHECK19-NEXT:  entry:
10689 // CHECK19-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
10690 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
10691 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
10692 // CHECK19-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
10693 // CHECK19-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
10694 // CHECK19-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
10695 // CHECK19-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
10696 // CHECK19-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
10697 // CHECK19-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
10698 // CHECK19-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 4
10699 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4
10700 // CHECK19-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2
10701 // CHECK19-NEXT:    store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
10702 // CHECK19-NEXT:    [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4
10703 // CHECK19-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined, i32 [[TMP1]], i32 [[TMP3]])
10704 // CHECK19-NEXT:    ret void
10705 //
10706 //
10707 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined
10708 // CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {
10709 // CHECK19-NEXT:  entry:
10710 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
10711 // CHECK19-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
10712 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
10713 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
10714 // CHECK19-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
10715 // CHECK19-NEXT:    [[TMP:%.*]] = alloca i32, align 4
10716 // CHECK19-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
10717 // CHECK19-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
10718 // CHECK19-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
10719 // CHECK19-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
10720 // CHECK19-NEXT:    [[I:%.*]] = alloca i32, align 4
10721 // CHECK19-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
10722 // CHECK19-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
10723 // CHECK19-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
10724 // CHECK19-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
10725 // CHECK19-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
10726 // CHECK19-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4
10727 // CHECK19-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
10728 // CHECK19-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
10729 // CHECK19-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
10730 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
10731 // CHECK19-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
10732 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
10733 // CHECK19-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
10734 // CHECK19-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
10735 // CHECK19:       cond.true:
10736 // CHECK19-NEXT:    br label [[COND_END:%.*]]
10737 // CHECK19:       cond.false:
10738 // CHECK19-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
10739 // CHECK19-NEXT:    br label [[COND_END]]
10740 // CHECK19:       cond.end:
10741 // CHECK19-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
10742 // CHECK19-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
10743 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
10744 // CHECK19-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
10745 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
10746 // CHECK19:       omp.inner.for.cond:
10747 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22:![0-9]+]]
10748 // CHECK19-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP22]]
10749 // CHECK19-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
10750 // CHECK19-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
10751 // CHECK19:       omp.inner.for.body:
10752 // CHECK19-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]]
10753 // CHECK19-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
10754 // CHECK19-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
10755 // CHECK19-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]]
10756 // CHECK19-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP22]]
10757 // CHECK19-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
10758 // CHECK19-NEXT:    store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP22]]
10759 // CHECK19-NEXT:    [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP22]]
10760 // CHECK19-NEXT:    [[CONV:%.*]] = sext i16 [[TMP9]] to i32
10761 // CHECK19-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV]], 1
10762 // CHECK19-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
10763 // CHECK19-NEXT:    store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP22]]
10764 // CHECK19-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
10765 // CHECK19:       omp.body.continue:
10766 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
10767 // CHECK19:       omp.inner.for.inc:
10768 // CHECK19-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]]
10769 // CHECK19-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP10]], 1
10770 // CHECK19-NEXT:    store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]]
10771 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
10772 // CHECK19:       omp.inner.for.end:
10773 // CHECK19-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
10774 // CHECK19:       omp.loop.exit:
10775 // CHECK19-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
10776 // CHECK19-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
10777 // CHECK19-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
10778 // CHECK19-NEXT:    br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
10779 // CHECK19:       .omp.final.then:
10780 // CHECK19-NEXT:    store i32 10, ptr [[I]], align 4
10781 // CHECK19-NEXT:    br label [[DOTOMP_FINAL_DONE]]
10782 // CHECK19:       .omp.final.done:
10783 // CHECK19-NEXT:    ret void
10784 //
10785 //
10786 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142
10787 // CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] {
10788 // CHECK19-NEXT:  entry:
10789 // CHECK19-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
10790 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
10791 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
10792 // CHECK19-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
10793 // CHECK19-NEXT:    [[BN_ADDR:%.*]] = alloca ptr, align 4
10794 // CHECK19-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
10795 // CHECK19-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
10796 // CHECK19-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
10797 // CHECK19-NEXT:    [[CN_ADDR:%.*]] = alloca ptr, align 4
10798 // CHECK19-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4
10799 // CHECK19-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
10800 // CHECK19-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
10801 // CHECK19-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
10802 // CHECK19-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
10803 // CHECK19-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
10804 // CHECK19-NEXT:    store ptr [[BN]], ptr [[BN_ADDR]], align 4
10805 // CHECK19-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
10806 // CHECK19-NEXT:    store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
10807 // CHECK19-NEXT:    store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4
10808 // CHECK19-NEXT:    store ptr [[CN]], ptr [[CN_ADDR]], align 4
10809 // CHECK19-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4
10810 // CHECK19-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
10811 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
10812 // CHECK19-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4
10813 // CHECK19-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
10814 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
10815 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4
10816 // CHECK19-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4
10817 // CHECK19-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4
10818 // CHECK19-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
10819 // CHECK19-NEXT:    store i32 [[TMP8]], ptr [[A_CASTED]], align 4
10820 // CHECK19-NEXT:    [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4
10821 // CHECK19-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.omp_outlined, i32 [[TMP9]], ptr [[TMP0]], i32 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]])
10822 // CHECK19-NEXT:    ret void
10823 //
10824 //
10825 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.omp_outlined
10826 // CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] {
10827 // CHECK19-NEXT:  entry:
10828 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
10829 // CHECK19-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
10830 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
10831 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
10832 // CHECK19-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
10833 // CHECK19-NEXT:    [[BN_ADDR:%.*]] = alloca ptr, align 4
10834 // CHECK19-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
10835 // CHECK19-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
10836 // CHECK19-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
10837 // CHECK19-NEXT:    [[CN_ADDR:%.*]] = alloca ptr, align 4
10838 // CHECK19-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4
10839 // CHECK19-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
10840 // CHECK19-NEXT:    [[TMP:%.*]] = alloca i32, align 4
10841 // CHECK19-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
10842 // CHECK19-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
10843 // CHECK19-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
10844 // CHECK19-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
10845 // CHECK19-NEXT:    [[I:%.*]] = alloca i32, align 4
10846 // CHECK19-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
10847 // CHECK19-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
10848 // CHECK19-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
10849 // CHECK19-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
10850 // CHECK19-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
10851 // CHECK19-NEXT:    store ptr [[BN]], ptr [[BN_ADDR]], align 4
10852 // CHECK19-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
10853 // CHECK19-NEXT:    store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
10854 // CHECK19-NEXT:    store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4
10855 // CHECK19-NEXT:    store ptr [[CN]], ptr [[CN_ADDR]], align 4
10856 // CHECK19-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4
10857 // CHECK19-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
10858 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
10859 // CHECK19-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4
10860 // CHECK19-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
10861 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
10862 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4
10863 // CHECK19-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4
10864 // CHECK19-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4
10865 // CHECK19-NEXT:    [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 0
10866 // CHECK19-NEXT:    call void @llvm.assume(i1 true) [ "align"(ptr [[ARRAYDECAY]], i32 16) ]
10867 // CHECK19-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
10868 // CHECK19-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4
10869 // CHECK19-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
10870 // CHECK19-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
10871 // CHECK19-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
10872 // CHECK19-NEXT:    [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
10873 // CHECK19-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP9]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
10874 // CHECK19-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
10875 // CHECK19-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 9
10876 // CHECK19-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
10877 // CHECK19:       cond.true:
10878 // CHECK19-NEXT:    br label [[COND_END:%.*]]
10879 // CHECK19:       cond.false:
10880 // CHECK19-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
10881 // CHECK19-NEXT:    br label [[COND_END]]
10882 // CHECK19:       cond.end:
10883 // CHECK19-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
10884 // CHECK19-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
10885 // CHECK19-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
10886 // CHECK19-NEXT:    store i32 [[TMP12]], ptr [[DOTOMP_IV]], align 4
10887 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
10888 // CHECK19:       omp.inner.for.cond:
10889 // CHECK19-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25:![0-9]+]]
10890 // CHECK19-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP25]]
10891 // CHECK19-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
10892 // CHECK19-NEXT:    br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
10893 // CHECK19:       omp.inner.for.body:
10894 // CHECK19-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]]
10895 // CHECK19-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
10896 // CHECK19-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
10897 // CHECK19-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP25]]
10898 // CHECK19-NEXT:    [[TMP16:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP25]]
10899 // CHECK19-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1
10900 // CHECK19-NEXT:    store i32 [[ADD6]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP25]]
10901 // CHECK19-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 2
10902 // CHECK19-NEXT:    [[TMP17:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP25]]
10903 // CHECK19-NEXT:    [[CONV:%.*]] = fpext float [[TMP17]] to double
10904 // CHECK19-NEXT:    [[ADD7:%.*]] = fadd double [[CONV]], 1.000000e+00
10905 // CHECK19-NEXT:    [[CONV8:%.*]] = fptrunc double [[ADD7]] to float
10906 // CHECK19-NEXT:    store float [[CONV8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP25]]
10907 // CHECK19-NEXT:    [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i32 3
10908 // CHECK19-NEXT:    [[TMP18:%.*]] = load float, ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP25]]
10909 // CHECK19-NEXT:    [[CONV10:%.*]] = fpext float [[TMP18]] to double
10910 // CHECK19-NEXT:    [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00
10911 // CHECK19-NEXT:    [[CONV12:%.*]] = fptrunc double [[ADD11]] to float
10912 // CHECK19-NEXT:    store float [[CONV12]], ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP25]]
10913 // CHECK19-NEXT:    [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 1
10914 // CHECK19-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX13]], i32 0, i32 2
10915 // CHECK19-NEXT:    [[TMP19:%.*]] = load double, ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP25]]
10916 // CHECK19-NEXT:    [[ADD15:%.*]] = fadd double [[TMP19]], 1.000000e+00
10917 // CHECK19-NEXT:    store double [[ADD15]], ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP25]]
10918 // CHECK19-NEXT:    [[TMP20:%.*]] = mul nsw i32 1, [[TMP5]]
10919 // CHECK19-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i32 [[TMP20]]
10920 // CHECK19-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX16]], i32 3
10921 // CHECK19-NEXT:    [[TMP21:%.*]] = load double, ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP25]]
10922 // CHECK19-NEXT:    [[ADD18:%.*]] = fadd double [[TMP21]], 1.000000e+00
10923 // CHECK19-NEXT:    store double [[ADD18]], ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP25]]
10924 // CHECK19-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0
10925 // CHECK19-NEXT:    [[TMP22:%.*]] = load i64, ptr [[X]], align 4, !llvm.access.group [[ACC_GRP25]]
10926 // CHECK19-NEXT:    [[ADD19:%.*]] = add nsw i64 [[TMP22]], 1
10927 // CHECK19-NEXT:    store i64 [[ADD19]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP25]]
10928 // CHECK19-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1
10929 // CHECK19-NEXT:    [[TMP23:%.*]] = load i8, ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP25]]
10930 // CHECK19-NEXT:    [[CONV20:%.*]] = sext i8 [[TMP23]] to i32
10931 // CHECK19-NEXT:    [[ADD21:%.*]] = add nsw i32 [[CONV20]], 1
10932 // CHECK19-NEXT:    [[CONV22:%.*]] = trunc i32 [[ADD21]] to i8
10933 // CHECK19-NEXT:    store i8 [[CONV22]], ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP25]]
10934 // CHECK19-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
10935 // CHECK19:       omp.body.continue:
10936 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
10937 // CHECK19:       omp.inner.for.inc:
10938 // CHECK19-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]]
10939 // CHECK19-NEXT:    [[ADD23:%.*]] = add nsw i32 [[TMP24]], 1
10940 // CHECK19-NEXT:    store i32 [[ADD23]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]]
10941 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]
10942 // CHECK19:       omp.inner.for.end:
10943 // CHECK19-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
10944 // CHECK19:       omp.loop.exit:
10945 // CHECK19-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP9]])
10946 // CHECK19-NEXT:    [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
10947 // CHECK19-NEXT:    [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
10948 // CHECK19-NEXT:    br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
10949 // CHECK19:       .omp.final.then:
10950 // CHECK19-NEXT:    store i32 10, ptr [[I]], align 4
10951 // CHECK19-NEXT:    br label [[DOTOMP_FINAL_DONE]]
10952 // CHECK19:       .omp.final.done:
10953 // CHECK19-NEXT:    ret void
10954 //
10955 //
10956 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197
10957 // CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
10958 // CHECK19-NEXT:  entry:
10959 // CHECK19-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
10960 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
10961 // CHECK19-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
10962 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
10963 // CHECK19-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
10964 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
10965 // CHECK19-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
10966 // CHECK19-NEXT:    [[N_CASTED:%.*]] = alloca i32, align 4
10967 // CHECK19-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
10968 // CHECK19-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
10969 // CHECK19-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
10970 // CHECK19-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
10971 // CHECK19-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
10972 // CHECK19-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
10973 // CHECK19-NEXT:    store i32 [[AAA]], ptr [[AAA_ADDR]], align 4
10974 // CHECK19-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
10975 // CHECK19-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
10976 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
10977 // CHECK19-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 4
10978 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4
10979 // CHECK19-NEXT:    [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4
10980 // CHECK19-NEXT:    store i32 [[TMP3]], ptr [[N_CASTED]], align 4
10981 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N_CASTED]], align 4
10982 // CHECK19-NEXT:    [[TMP5:%.*]] = load i16, ptr [[AA_ADDR]], align 2
10983 // CHECK19-NEXT:    store i16 [[TMP5]], ptr [[AA_CASTED]], align 2
10984 // CHECK19-NEXT:    [[TMP6:%.*]] = load i32, ptr [[AA_CASTED]], align 4
10985 // CHECK19-NEXT:    [[TMP7:%.*]] = load i8, ptr [[AAA_ADDR]], align 1
10986 // CHECK19-NEXT:    store i8 [[TMP7]], ptr [[AAA_CASTED]], align 1
10987 // CHECK19-NEXT:    [[TMP8:%.*]] = load i32, ptr [[AAA_CASTED]], align 4
10988 // CHECK19-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], ptr [[TMP0]])
10989 // CHECK19-NEXT:    ret void
10990 //
10991 //
10992 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.omp_outlined
10993 // CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
10994 // CHECK19-NEXT:  entry:
10995 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
10996 // CHECK19-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
10997 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
10998 // CHECK19-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
10999 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
11000 // CHECK19-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
11001 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
11002 // CHECK19-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
11003 // CHECK19-NEXT:    [[TMP:%.*]] = alloca i32, align 4
11004 // CHECK19-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
11005 // CHECK19-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
11006 // CHECK19-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
11007 // CHECK19-NEXT:    [[I:%.*]] = alloca i32, align 4
11008 // CHECK19-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
11009 // CHECK19-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
11010 // CHECK19-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
11011 // CHECK19-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
11012 // CHECK19-NEXT:    [[I5:%.*]] = alloca i32, align 4
11013 // CHECK19-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
11014 // CHECK19-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
11015 // CHECK19-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
11016 // CHECK19-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
11017 // CHECK19-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
11018 // CHECK19-NEXT:    store i32 [[AAA]], ptr [[AAA_ADDR]], align 4
11019 // CHECK19-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
11020 // CHECK19-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
11021 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
11022 // CHECK19-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
11023 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
11024 // CHECK19-NEXT:    store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
11025 // CHECK19-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
11026 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
11027 // CHECK19-NEXT:    [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
11028 // CHECK19-NEXT:    [[SUB3:%.*]] = sub i32 [[SUB]], 1
11029 // CHECK19-NEXT:    [[ADD:%.*]] = add i32 [[SUB3]], 1
11030 // CHECK19-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
11031 // CHECK19-NEXT:    [[SUB4:%.*]] = sub i32 [[DIV]], 1
11032 // CHECK19-NEXT:    store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 4
11033 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
11034 // CHECK19-NEXT:    store i32 [[TMP5]], ptr [[I]], align 4
11035 // CHECK19-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
11036 // CHECK19-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
11037 // CHECK19-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
11038 // CHECK19-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
11039 // CHECK19:       omp.precond.then:
11040 // CHECK19-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
11041 // CHECK19-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
11042 // CHECK19-NEXT:    store i32 [[TMP8]], ptr [[DOTOMP_UB]], align 4
11043 // CHECK19-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
11044 // CHECK19-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
11045 // CHECK19-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
11046 // CHECK19-NEXT:    [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4
11047 // CHECK19-NEXT:    call void @__kmpc_for_static_init_4u(ptr @[[GLOB1]], i32 [[TMP10]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
11048 // CHECK19-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
11049 // CHECK19-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
11050 // CHECK19-NEXT:    [[CMP6:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]]
11051 // CHECK19-NEXT:    br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
11052 // CHECK19:       cond.true:
11053 // CHECK19-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
11054 // CHECK19-NEXT:    br label [[COND_END:%.*]]
11055 // CHECK19:       cond.false:
11056 // CHECK19-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
11057 // CHECK19-NEXT:    br label [[COND_END]]
11058 // CHECK19:       cond.end:
11059 // CHECK19-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ]
11060 // CHECK19-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
11061 // CHECK19-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
11062 // CHECK19-NEXT:    store i32 [[TMP15]], ptr [[DOTOMP_IV]], align 4
11063 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
11064 // CHECK19:       omp.inner.for.cond:
11065 // CHECK19-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28:![0-9]+]]
11066 // CHECK19-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP28]]
11067 // CHECK19-NEXT:    [[ADD7:%.*]] = add i32 [[TMP17]], 1
11068 // CHECK19-NEXT:    [[CMP8:%.*]] = icmp ult i32 [[TMP16]], [[ADD7]]
11069 // CHECK19-NEXT:    br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
11070 // CHECK19:       omp.inner.for.body:
11071 // CHECK19-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group [[ACC_GRP28]]
11072 // CHECK19-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]]
11073 // CHECK19-NEXT:    [[MUL:%.*]] = mul i32 [[TMP19]], 1
11074 // CHECK19-NEXT:    [[ADD9:%.*]] = add i32 [[TMP18]], [[MUL]]
11075 // CHECK19-NEXT:    store i32 [[ADD9]], ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP28]]
11076 // CHECK19-NEXT:    [[TMP20:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP28]]
11077 // CHECK19-NEXT:    [[ADD10:%.*]] = add nsw i32 [[TMP20]], 1
11078 // CHECK19-NEXT:    store i32 [[ADD10]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP28]]
11079 // CHECK19-NEXT:    [[TMP21:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP28]]
11080 // CHECK19-NEXT:    [[CONV:%.*]] = sext i16 [[TMP21]] to i32
11081 // CHECK19-NEXT:    [[ADD11:%.*]] = add nsw i32 [[CONV]], 1
11082 // CHECK19-NEXT:    [[CONV12:%.*]] = trunc i32 [[ADD11]] to i16
11083 // CHECK19-NEXT:    store i16 [[CONV12]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP28]]
11084 // CHECK19-NEXT:    [[TMP22:%.*]] = load i8, ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP28]]
11085 // CHECK19-NEXT:    [[CONV13:%.*]] = sext i8 [[TMP22]] to i32
11086 // CHECK19-NEXT:    [[ADD14:%.*]] = add nsw i32 [[CONV13]], 1
11087 // CHECK19-NEXT:    [[CONV15:%.*]] = trunc i32 [[ADD14]] to i8
11088 // CHECK19-NEXT:    store i8 [[CONV15]], ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP28]]
11089 // CHECK19-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2
11090 // CHECK19-NEXT:    [[TMP23:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP28]]
11091 // CHECK19-NEXT:    [[ADD16:%.*]] = add nsw i32 [[TMP23]], 1
11092 // CHECK19-NEXT:    store i32 [[ADD16]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP28]]
11093 // CHECK19-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
11094 // CHECK19:       omp.body.continue:
11095 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
11096 // CHECK19:       omp.inner.for.inc:
11097 // CHECK19-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]]
11098 // CHECK19-NEXT:    [[ADD17:%.*]] = add i32 [[TMP24]], 1
11099 // CHECK19-NEXT:    store i32 [[ADD17]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]]
11100 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]]
11101 // CHECK19:       omp.inner.for.end:
11102 // CHECK19-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
11103 // CHECK19:       omp.loop.exit:
11104 // CHECK19-NEXT:    [[TMP25:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
11105 // CHECK19-NEXT:    [[TMP26:%.*]] = load i32, ptr [[TMP25]], align 4
11106 // CHECK19-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP26]])
11107 // CHECK19-NEXT:    [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
11108 // CHECK19-NEXT:    [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
11109 // CHECK19-NEXT:    br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
11110 // CHECK19:       .omp.final.then:
11111 // CHECK19-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
11112 // CHECK19-NEXT:    [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
11113 // CHECK19-NEXT:    [[TMP31:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
11114 // CHECK19-NEXT:    [[SUB18:%.*]] = sub i32 [[TMP30]], [[TMP31]]
11115 // CHECK19-NEXT:    [[SUB19:%.*]] = sub i32 [[SUB18]], 1
11116 // CHECK19-NEXT:    [[ADD20:%.*]] = add i32 [[SUB19]], 1
11117 // CHECK19-NEXT:    [[DIV21:%.*]] = udiv i32 [[ADD20]], 1
11118 // CHECK19-NEXT:    [[MUL22:%.*]] = mul i32 [[DIV21]], 1
11119 // CHECK19-NEXT:    [[ADD23:%.*]] = add i32 [[TMP29]], [[MUL22]]
11120 // CHECK19-NEXT:    store i32 [[ADD23]], ptr [[I5]], align 4
11121 // CHECK19-NEXT:    br label [[DOTOMP_FINAL_DONE]]
11122 // CHECK19:       .omp.final.done:
11123 // CHECK19-NEXT:    br label [[OMP_PRECOND_END]]
11124 // CHECK19:       omp.precond.end:
11125 // CHECK19-NEXT:    ret void
11126 //
11127 //
11128 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215
11129 // CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
11130 // CHECK19-NEXT:  entry:
11131 // CHECK19-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
11132 // CHECK19-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
11133 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
11134 // CHECK19-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
11135 // CHECK19-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
11136 // CHECK19-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
11137 // CHECK19-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
11138 // CHECK19-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
11139 // CHECK19-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
11140 // CHECK19-NEXT:    store i32 [[B]], ptr [[B_ADDR]], align 4
11141 // CHECK19-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
11142 // CHECK19-NEXT:    store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
11143 // CHECK19-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
11144 // CHECK19-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
11145 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
11146 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
11147 // CHECK19-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
11148 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4
11149 // CHECK19-NEXT:    store i32 [[TMP4]], ptr [[B_CASTED]], align 4
11150 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4
11151 // CHECK19-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.omp_outlined, ptr [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], ptr [[TMP3]])
11152 // CHECK19-NEXT:    ret void
11153 //
11154 //
11155 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.omp_outlined
11156 // CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
11157 // CHECK19-NEXT:  entry:
11158 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
11159 // CHECK19-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
11160 // CHECK19-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
11161 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
11162 // CHECK19-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
11163 // CHECK19-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
11164 // CHECK19-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
11165 // CHECK19-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
11166 // CHECK19-NEXT:    [[TMP:%.*]] = alloca i32, align 4
11167 // CHECK19-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
11168 // CHECK19-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
11169 // CHECK19-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
11170 // CHECK19-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
11171 // CHECK19-NEXT:    [[I:%.*]] = alloca i32, align 4
11172 // CHECK19-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
11173 // CHECK19-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
11174 // CHECK19-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
11175 // CHECK19-NEXT:    store i32 [[B]], ptr [[B_ADDR]], align 4
11176 // CHECK19-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
11177 // CHECK19-NEXT:    store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
11178 // CHECK19-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
11179 // CHECK19-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
11180 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
11181 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
11182 // CHECK19-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
11183 // CHECK19-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
11184 // CHECK19-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4
11185 // CHECK19-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
11186 // CHECK19-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
11187 // CHECK19-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
11188 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
11189 // CHECK19-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
11190 // CHECK19-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
11191 // CHECK19-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9
11192 // CHECK19-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
11193 // CHECK19:       cond.true:
11194 // CHECK19-NEXT:    br label [[COND_END:%.*]]
11195 // CHECK19:       cond.false:
11196 // CHECK19-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
11197 // CHECK19-NEXT:    br label [[COND_END]]
11198 // CHECK19:       cond.end:
11199 // CHECK19-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
11200 // CHECK19-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
11201 // CHECK19-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
11202 // CHECK19-NEXT:    store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4
11203 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
11204 // CHECK19:       omp.inner.for.cond:
11205 // CHECK19-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31:![0-9]+]]
11206 // CHECK19-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP31]]
11207 // CHECK19-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
11208 // CHECK19-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
11209 // CHECK19:       omp.inner.for.body:
11210 // CHECK19-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31]]
11211 // CHECK19-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
11212 // CHECK19-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
11213 // CHECK19-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP31]]
11214 // CHECK19-NEXT:    [[TMP12:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP31]]
11215 // CHECK19-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP12]] to double
11216 // CHECK19-NEXT:    [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00
11217 // CHECK19-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0
11218 // CHECK19-NEXT:    store double [[ADD4]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP31]]
11219 // CHECK19-NEXT:    [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0
11220 // CHECK19-NEXT:    [[TMP13:%.*]] = load double, ptr [[A5]], align 4, !llvm.access.group [[ACC_GRP31]]
11221 // CHECK19-NEXT:    [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
11222 // CHECK19-NEXT:    store double [[INC]], ptr [[A5]], align 4, !llvm.access.group [[ACC_GRP31]]
11223 // CHECK19-NEXT:    [[CONV6:%.*]] = fptosi double [[INC]] to i16
11224 // CHECK19-NEXT:    [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]]
11225 // CHECK19-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i32 [[TMP14]]
11226 // CHECK19-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1
11227 // CHECK19-NEXT:    store i16 [[CONV6]], ptr [[ARRAYIDX7]], align 2, !llvm.access.group [[ACC_GRP31]]
11228 // CHECK19-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
11229 // CHECK19:       omp.body.continue:
11230 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
11231 // CHECK19:       omp.inner.for.inc:
11232 // CHECK19-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31]]
11233 // CHECK19-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP15]], 1
11234 // CHECK19-NEXT:    store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31]]
11235 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP32:![0-9]+]]
11236 // CHECK19:       omp.inner.for.end:
11237 // CHECK19-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
11238 // CHECK19:       omp.loop.exit:
11239 // CHECK19-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])
11240 // CHECK19-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
11241 // CHECK19-NEXT:    [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
11242 // CHECK19-NEXT:    br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
11243 // CHECK19:       .omp.final.then:
11244 // CHECK19-NEXT:    store i32 10, ptr [[I]], align 4
11245 // CHECK19-NEXT:    br label [[DOTOMP_FINAL_DONE]]
11246 // CHECK19:       .omp.final.done:
11247 // CHECK19-NEXT:    ret void
11248 //
11249 //
11250 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180
11251 // CHECK19-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
11252 // CHECK19-NEXT:  entry:
11253 // CHECK19-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
11254 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
11255 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
11256 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
11257 // CHECK19-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
11258 // CHECK19-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
11259 // CHECK19-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
11260 // CHECK19-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
11261 // CHECK19-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
11262 // CHECK19-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
11263 // CHECK19-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
11264 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
11265 // CHECK19-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 4
11266 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4
11267 // CHECK19-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
11268 // CHECK19-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
11269 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4
11270 // CHECK19-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], ptr [[TMP0]])
11271 // CHECK19-NEXT:    ret void
11272 //
11273 //
11274 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.omp_outlined
11275 // CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
11276 // CHECK19-NEXT:  entry:
11277 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
11278 // CHECK19-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
11279 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
11280 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
11281 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
11282 // CHECK19-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
11283 // CHECK19-NEXT:    [[TMP:%.*]] = alloca i32, align 4
11284 // CHECK19-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
11285 // CHECK19-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
11286 // CHECK19-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
11287 // CHECK19-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
11288 // CHECK19-NEXT:    [[I:%.*]] = alloca i32, align 4
11289 // CHECK19-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
11290 // CHECK19-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
11291 // CHECK19-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
11292 // CHECK19-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
11293 // CHECK19-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
11294 // CHECK19-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
11295 // CHECK19-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
11296 // CHECK19-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4
11297 // CHECK19-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
11298 // CHECK19-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
11299 // CHECK19-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
11300 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
11301 // CHECK19-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
11302 // CHECK19-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
11303 // CHECK19-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
11304 // CHECK19-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
11305 // CHECK19:       cond.true:
11306 // CHECK19-NEXT:    br label [[COND_END:%.*]]
11307 // CHECK19:       cond.false:
11308 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
11309 // CHECK19-NEXT:    br label [[COND_END]]
11310 // CHECK19:       cond.end:
11311 // CHECK19-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
11312 // CHECK19-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
11313 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
11314 // CHECK19-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
11315 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
11316 // CHECK19:       omp.inner.for.cond:
11317 // CHECK19-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP34:![0-9]+]]
11318 // CHECK19-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP34]]
11319 // CHECK19-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
11320 // CHECK19-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
11321 // CHECK19:       omp.inner.for.body:
11322 // CHECK19-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP34]]
11323 // CHECK19-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
11324 // CHECK19-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
11325 // CHECK19-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP34]]
11326 // CHECK19-NEXT:    [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP34]]
11327 // CHECK19-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
11328 // CHECK19-NEXT:    store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP34]]
11329 // CHECK19-NEXT:    [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP34]]
11330 // CHECK19-NEXT:    [[CONV:%.*]] = sext i16 [[TMP10]] to i32
11331 // CHECK19-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV]], 1
11332 // CHECK19-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
11333 // CHECK19-NEXT:    store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP34]]
11334 // CHECK19-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2
11335 // CHECK19-NEXT:    [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP34]]
11336 // CHECK19-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1
11337 // CHECK19-NEXT:    store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP34]]
11338 // CHECK19-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
11339 // CHECK19:       omp.body.continue:
11340 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
11341 // CHECK19:       omp.inner.for.inc:
11342 // CHECK19-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP34]]
11343 // CHECK19-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP12]], 1
11344 // CHECK19-NEXT:    store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP34]]
11345 // CHECK19-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP35:![0-9]+]]
11346 // CHECK19:       omp.inner.for.end:
11347 // CHECK19-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
11348 // CHECK19:       omp.loop.exit:
11349 // CHECK19-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])
11350 // CHECK19-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
11351 // CHECK19-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
11352 // CHECK19-NEXT:    br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
11353 // CHECK19:       .omp.final.then:
11354 // CHECK19-NEXT:    store i32 10, ptr [[I]], align 4
11355 // CHECK19-NEXT:    br label [[DOTOMP_FINAL_DONE]]
11356 // CHECK19:       .omp.final.done:
11357 // CHECK19-NEXT:    ret void
11358 //
11359 //
11360 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97
11361 // CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] {
11362 // CHECK21-NEXT:  entry:
11363 // CHECK21-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
11364 // CHECK21-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
11365 // CHECK21-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
11366 // CHECK21-NEXT:    [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8
11367 // CHECK21-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
11368 // CHECK21-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])
11369 // CHECK21-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
11370 // CHECK21-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
11371 // CHECK21-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
11372 // CHECK21-NEXT:    store i64 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 8
11373 // CHECK21-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
11374 // CHECK21-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4
11375 // CHECK21-NEXT:    call void @__kmpc_push_num_teams(ptr @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
11376 // CHECK21-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
11377 // CHECK21-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
11378 // CHECK21-NEXT:    [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8
11379 // CHECK21-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.omp_outlined, i64 [[TMP4]])
11380 // CHECK21-NEXT:    ret void
11381 //
11382 //
11383 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.omp_outlined
11384 // CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {
11385 // CHECK21-NEXT:  entry:
11386 // CHECK21-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
11387 // CHECK21-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
11388 // CHECK21-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
11389 // CHECK21-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
11390 // CHECK21-NEXT:    [[TMP:%.*]] = alloca i32, align 4
11391 // CHECK21-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
11392 // CHECK21-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
11393 // CHECK21-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
11394 // CHECK21-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
11395 // CHECK21-NEXT:    [[I:%.*]] = alloca i32, align 4
11396 // CHECK21-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
11397 // CHECK21-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
11398 // CHECK21-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
11399 // CHECK21-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
11400 // CHECK21-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4
11401 // CHECK21-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
11402 // CHECK21-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
11403 // CHECK21-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
11404 // CHECK21-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
11405 // CHECK21-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
11406 // CHECK21-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
11407 // CHECK21-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
11408 // CHECK21-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
11409 // CHECK21:       cond.true:
11410 // CHECK21-NEXT:    br label [[COND_END:%.*]]
11411 // CHECK21:       cond.false:
11412 // CHECK21-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
11413 // CHECK21-NEXT:    br label [[COND_END]]
11414 // CHECK21:       cond.end:
11415 // CHECK21-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
11416 // CHECK21-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
11417 // CHECK21-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
11418 // CHECK21-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
11419 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
11420 // CHECK21:       omp.inner.for.cond:
11421 // CHECK21-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11:![0-9]+]]
11422 // CHECK21-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP11]]
11423 // CHECK21-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
11424 // CHECK21-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
11425 // CHECK21:       omp.inner.for.body:
11426 // CHECK21-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]
11427 // CHECK21-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
11428 // CHECK21-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
11429 // CHECK21-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]]
11430 // CHECK21-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
11431 // CHECK21:       omp.body.continue:
11432 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
11433 // CHECK21:       omp.inner.for.inc:
11434 // CHECK21-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]
11435 // CHECK21-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
11436 // CHECK21-NEXT:    store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]
11437 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
11438 // CHECK21:       omp.inner.for.end:
11439 // CHECK21-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
11440 // CHECK21:       omp.loop.exit:
11441 // CHECK21-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
11442 // CHECK21-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
11443 // CHECK21-NEXT:    [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
11444 // CHECK21-NEXT:    br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
11445 // CHECK21:       .omp.final.then:
11446 // CHECK21-NEXT:    store i32 10, ptr [[I]], align 4
11447 // CHECK21-NEXT:    br label [[DOTOMP_FINAL_DONE]]
11448 // CHECK21:       .omp.final.done:
11449 // CHECK21-NEXT:    ret void
11450 //
11451 //
11452 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
11453 // CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {
11454 // CHECK21-NEXT:  entry:
11455 // CHECK21-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
11456 // CHECK21-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
11457 // CHECK21-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
11458 // CHECK21-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
11459 // CHECK21-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
11460 // CHECK21-NEXT:    [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2
11461 // CHECK21-NEXT:    store i16 [[TMP0]], ptr [[AA_CASTED]], align 2
11462 // CHECK21-NEXT:    [[TMP1:%.*]] = load i64, ptr [[AA_CASTED]], align 8
11463 // CHECK21-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined, i64 [[TMP1]])
11464 // CHECK21-NEXT:    ret void
11465 //
11466 //
11467 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined
11468 // CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {
11469 // CHECK21-NEXT:  entry:
11470 // CHECK21-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
11471 // CHECK21-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
11472 // CHECK21-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
11473 // CHECK21-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
11474 // CHECK21-NEXT:    [[TMP:%.*]] = alloca i32, align 4
11475 // CHECK21-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
11476 // CHECK21-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
11477 // CHECK21-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
11478 // CHECK21-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
11479 // CHECK21-NEXT:    [[I:%.*]] = alloca i32, align 4
11480 // CHECK21-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
11481 // CHECK21-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
11482 // CHECK21-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
11483 // CHECK21-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
11484 // CHECK21-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4
11485 // CHECK21-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
11486 // CHECK21-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
11487 // CHECK21-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
11488 // CHECK21-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
11489 // CHECK21-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
11490 // CHECK21-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
11491 // CHECK21-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
11492 // CHECK21-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
11493 // CHECK21:       cond.true:
11494 // CHECK21-NEXT:    br label [[COND_END:%.*]]
11495 // CHECK21:       cond.false:
11496 // CHECK21-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
11497 // CHECK21-NEXT:    br label [[COND_END]]
11498 // CHECK21:       cond.end:
11499 // CHECK21-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
11500 // CHECK21-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
11501 // CHECK21-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
11502 // CHECK21-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
11503 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
11504 // CHECK21:       omp.inner.for.cond:
11505 // CHECK21-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18:![0-9]+]]
11506 // CHECK21-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP18]]
11507 // CHECK21-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
11508 // CHECK21-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
11509 // CHECK21:       omp.inner.for.body:
11510 // CHECK21-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]]
11511 // CHECK21-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
11512 // CHECK21-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
11513 // CHECK21-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]]
11514 // CHECK21-NEXT:    [[TMP8:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP18]]
11515 // CHECK21-NEXT:    [[CONV:%.*]] = sext i16 [[TMP8]] to i32
11516 // CHECK21-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
11517 // CHECK21-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
11518 // CHECK21-NEXT:    store i16 [[CONV3]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP18]]
11519 // CHECK21-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
11520 // CHECK21:       omp.body.continue:
11521 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
11522 // CHECK21:       omp.inner.for.inc:
11523 // CHECK21-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]]
11524 // CHECK21-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP9]], 1
11525 // CHECK21-NEXT:    store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]]
11526 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
11527 // CHECK21:       omp.inner.for.end:
11528 // CHECK21-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
11529 // CHECK21:       omp.loop.exit:
11530 // CHECK21-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
11531 // CHECK21-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
11532 // CHECK21-NEXT:    [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
11533 // CHECK21-NEXT:    br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
11534 // CHECK21:       .omp.final.then:
11535 // CHECK21-NEXT:    store i32 10, ptr [[I]], align 4
11536 // CHECK21-NEXT:    br label [[DOTOMP_FINAL_DONE]]
11537 // CHECK21:       .omp.final.done:
11538 // CHECK21-NEXT:    ret void
11539 //
11540 //
11541 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118
11542 // CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {
11543 // CHECK21-NEXT:  entry:
11544 // CHECK21-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
11545 // CHECK21-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
11546 // CHECK21-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
11547 // CHECK21-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
11548 // CHECK21-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
11549 // CHECK21-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
11550 // CHECK21-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
11551 // CHECK21-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
11552 // CHECK21-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
11553 // CHECK21-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 4
11554 // CHECK21-NEXT:    [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8
11555 // CHECK21-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2
11556 // CHECK21-NEXT:    store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
11557 // CHECK21-NEXT:    [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8
11558 // CHECK21-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined, i64 [[TMP1]], i64 [[TMP3]])
11559 // CHECK21-NEXT:    ret void
11560 //
11561 //
11562 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined
11563 // CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {
11564 // CHECK21-NEXT:  entry:
11565 // CHECK21-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
11566 // CHECK21-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
11567 // CHECK21-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
11568 // CHECK21-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
11569 // CHECK21-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
11570 // CHECK21-NEXT:    [[TMP:%.*]] = alloca i32, align 4
11571 // CHECK21-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
11572 // CHECK21-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
11573 // CHECK21-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
11574 // CHECK21-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
11575 // CHECK21-NEXT:    [[I:%.*]] = alloca i32, align 4
11576 // CHECK21-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
11577 // CHECK21-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
11578 // CHECK21-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
11579 // CHECK21-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
11580 // CHECK21-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
11581 // CHECK21-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4
11582 // CHECK21-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
11583 // CHECK21-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
11584 // CHECK21-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
11585 // CHECK21-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
11586 // CHECK21-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
11587 // CHECK21-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
11588 // CHECK21-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
11589 // CHECK21-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
11590 // CHECK21:       cond.true:
11591 // CHECK21-NEXT:    br label [[COND_END:%.*]]
11592 // CHECK21:       cond.false:
11593 // CHECK21-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
11594 // CHECK21-NEXT:    br label [[COND_END]]
11595 // CHECK21:       cond.end:
11596 // CHECK21-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
11597 // CHECK21-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
11598 // CHECK21-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
11599 // CHECK21-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
11600 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
11601 // CHECK21:       omp.inner.for.cond:
11602 // CHECK21-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21:![0-9]+]]
11603 // CHECK21-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP21]]
11604 // CHECK21-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
11605 // CHECK21-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
11606 // CHECK21:       omp.inner.for.body:
11607 // CHECK21-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]]
11608 // CHECK21-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
11609 // CHECK21-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
11610 // CHECK21-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP21]]
11611 // CHECK21-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP21]]
11612 // CHECK21-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
11613 // CHECK21-NEXT:    store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP21]]
11614 // CHECK21-NEXT:    [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP21]]
11615 // CHECK21-NEXT:    [[CONV:%.*]] = sext i16 [[TMP9]] to i32
11616 // CHECK21-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV]], 1
11617 // CHECK21-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
11618 // CHECK21-NEXT:    store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP21]]
11619 // CHECK21-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
11620 // CHECK21:       omp.body.continue:
11621 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
11622 // CHECK21:       omp.inner.for.inc:
11623 // CHECK21-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]]
11624 // CHECK21-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP10]], 1
11625 // CHECK21-NEXT:    store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]]
11626 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]]
11627 // CHECK21:       omp.inner.for.end:
11628 // CHECK21-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
11629 // CHECK21:       omp.loop.exit:
11630 // CHECK21-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
11631 // CHECK21-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
11632 // CHECK21-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
11633 // CHECK21-NEXT:    br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
11634 // CHECK21:       .omp.final.then:
11635 // CHECK21-NEXT:    store i32 10, ptr [[I]], align 4
11636 // CHECK21-NEXT:    br label [[DOTOMP_FINAL_DONE]]
11637 // CHECK21:       .omp.final.done:
11638 // CHECK21-NEXT:    ret void
11639 //
11640 //
11641 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142
11642 // CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] {
11643 // CHECK21-NEXT:  entry:
11644 // CHECK21-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
11645 // CHECK21-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
11646 // CHECK21-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
11647 // CHECK21-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
11648 // CHECK21-NEXT:    [[BN_ADDR:%.*]] = alloca ptr, align 8
11649 // CHECK21-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
11650 // CHECK21-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
11651 // CHECK21-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
11652 // CHECK21-NEXT:    [[CN_ADDR:%.*]] = alloca ptr, align 8
11653 // CHECK21-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
11654 // CHECK21-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
11655 // CHECK21-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
11656 // CHECK21-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
11657 // CHECK21-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
11658 // CHECK21-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
11659 // CHECK21-NEXT:    store ptr [[BN]], ptr [[BN_ADDR]], align 8
11660 // CHECK21-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
11661 // CHECK21-NEXT:    store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
11662 // CHECK21-NEXT:    store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8
11663 // CHECK21-NEXT:    store ptr [[CN]], ptr [[CN_ADDR]], align 8
11664 // CHECK21-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
11665 // CHECK21-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
11666 // CHECK21-NEXT:    [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
11667 // CHECK21-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8
11668 // CHECK21-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
11669 // CHECK21-NEXT:    [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
11670 // CHECK21-NEXT:    [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8
11671 // CHECK21-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8
11672 // CHECK21-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8
11673 // CHECK21-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
11674 // CHECK21-NEXT:    store i32 [[TMP8]], ptr [[A_CASTED]], align 4
11675 // CHECK21-NEXT:    [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 8
11676 // CHECK21-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.omp_outlined, i64 [[TMP9]], ptr [[TMP0]], i64 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]])
11677 // CHECK21-NEXT:    ret void
11678 //
11679 //
11680 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.omp_outlined
11681 // CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] {
11682 // CHECK21-NEXT:  entry:
11683 // CHECK21-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
11684 // CHECK21-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
11685 // CHECK21-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
11686 // CHECK21-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
11687 // CHECK21-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
11688 // CHECK21-NEXT:    [[BN_ADDR:%.*]] = alloca ptr, align 8
11689 // CHECK21-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
11690 // CHECK21-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
11691 // CHECK21-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
11692 // CHECK21-NEXT:    [[CN_ADDR:%.*]] = alloca ptr, align 8
11693 // CHECK21-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 8
11694 // CHECK21-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
11695 // CHECK21-NEXT:    [[TMP:%.*]] = alloca i32, align 4
11696 // CHECK21-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
11697 // CHECK21-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
11698 // CHECK21-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
11699 // CHECK21-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
11700 // CHECK21-NEXT:    [[I:%.*]] = alloca i32, align 4
11701 // CHECK21-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
11702 // CHECK21-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
11703 // CHECK21-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
11704 // CHECK21-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
11705 // CHECK21-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
11706 // CHECK21-NEXT:    store ptr [[BN]], ptr [[BN_ADDR]], align 8
11707 // CHECK21-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
11708 // CHECK21-NEXT:    store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
11709 // CHECK21-NEXT:    store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8
11710 // CHECK21-NEXT:    store ptr [[CN]], ptr [[CN_ADDR]], align 8
11711 // CHECK21-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 8
11712 // CHECK21-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
11713 // CHECK21-NEXT:    [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
11714 // CHECK21-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8
11715 // CHECK21-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
11716 // CHECK21-NEXT:    [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
11717 // CHECK21-NEXT:    [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8
11718 // CHECK21-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8
11719 // CHECK21-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8
11720 // CHECK21-NEXT:    [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 0
11721 // CHECK21-NEXT:    call void @llvm.assume(i1 true) [ "align"(ptr [[ARRAYDECAY]], i64 16) ]
11722 // CHECK21-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
11723 // CHECK21-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4
11724 // CHECK21-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
11725 // CHECK21-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
11726 // CHECK21-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
11727 // CHECK21-NEXT:    [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
11728 // CHECK21-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP9]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
11729 // CHECK21-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
11730 // CHECK21-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 9
11731 // CHECK21-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
11732 // CHECK21:       cond.true:
11733 // CHECK21-NEXT:    br label [[COND_END:%.*]]
11734 // CHECK21:       cond.false:
11735 // CHECK21-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
11736 // CHECK21-NEXT:    br label [[COND_END]]
11737 // CHECK21:       cond.end:
11738 // CHECK21-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
11739 // CHECK21-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
11740 // CHECK21-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
11741 // CHECK21-NEXT:    store i32 [[TMP12]], ptr [[DOTOMP_IV]], align 4
11742 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
11743 // CHECK21:       omp.inner.for.cond:
11744 // CHECK21-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24:![0-9]+]]
11745 // CHECK21-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP24]]
11746 // CHECK21-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
11747 // CHECK21-NEXT:    br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
11748 // CHECK21:       omp.inner.for.body:
11749 // CHECK21-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]]
11750 // CHECK21-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
11751 // CHECK21-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
11752 // CHECK21-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP24]]
11753 // CHECK21-NEXT:    [[TMP16:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP24]]
11754 // CHECK21-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1
11755 // CHECK21-NEXT:    store i32 [[ADD6]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP24]]
11756 // CHECK21-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 2
11757 // CHECK21-NEXT:    [[TMP17:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP24]]
11758 // CHECK21-NEXT:    [[CONV:%.*]] = fpext float [[TMP17]] to double
11759 // CHECK21-NEXT:    [[ADD7:%.*]] = fadd double [[CONV]], 1.000000e+00
11760 // CHECK21-NEXT:    [[CONV8:%.*]] = fptrunc double [[ADD7]] to float
11761 // CHECK21-NEXT:    store float [[CONV8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP24]]
11762 // CHECK21-NEXT:    [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 3
11763 // CHECK21-NEXT:    [[TMP18:%.*]] = load float, ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP24]]
11764 // CHECK21-NEXT:    [[CONV10:%.*]] = fpext float [[TMP18]] to double
11765 // CHECK21-NEXT:    [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00
11766 // CHECK21-NEXT:    [[CONV12:%.*]] = fptrunc double [[ADD11]] to float
11767 // CHECK21-NEXT:    store float [[CONV12]], ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP24]]
11768 // CHECK21-NEXT:    [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 1
11769 // CHECK21-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX13]], i64 0, i64 2
11770 // CHECK21-NEXT:    [[TMP19:%.*]] = load double, ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP24]]
11771 // CHECK21-NEXT:    [[ADD15:%.*]] = fadd double [[TMP19]], 1.000000e+00
11772 // CHECK21-NEXT:    store double [[ADD15]], ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP24]]
11773 // CHECK21-NEXT:    [[TMP20:%.*]] = mul nsw i64 1, [[TMP5]]
11774 // CHECK21-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i64 [[TMP20]]
11775 // CHECK21-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX16]], i64 3
11776 // CHECK21-NEXT:    [[TMP21:%.*]] = load double, ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP24]]
11777 // CHECK21-NEXT:    [[ADD18:%.*]] = fadd double [[TMP21]], 1.000000e+00
11778 // CHECK21-NEXT:    store double [[ADD18]], ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP24]]
11779 // CHECK21-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0
11780 // CHECK21-NEXT:    [[TMP22:%.*]] = load i64, ptr [[X]], align 8, !llvm.access.group [[ACC_GRP24]]
11781 // CHECK21-NEXT:    [[ADD19:%.*]] = add nsw i64 [[TMP22]], 1
11782 // CHECK21-NEXT:    store i64 [[ADD19]], ptr [[X]], align 8, !llvm.access.group [[ACC_GRP24]]
11783 // CHECK21-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1
11784 // CHECK21-NEXT:    [[TMP23:%.*]] = load i8, ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP24]]
11785 // CHECK21-NEXT:    [[CONV20:%.*]] = sext i8 [[TMP23]] to i32
11786 // CHECK21-NEXT:    [[ADD21:%.*]] = add nsw i32 [[CONV20]], 1
11787 // CHECK21-NEXT:    [[CONV22:%.*]] = trunc i32 [[ADD21]] to i8
11788 // CHECK21-NEXT:    store i8 [[CONV22]], ptr [[Y]], align 8, !llvm.access.group [[ACC_GRP24]]
11789 // CHECK21-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
11790 // CHECK21:       omp.body.continue:
11791 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
11792 // CHECK21:       omp.inner.for.inc:
11793 // CHECK21-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]]
11794 // CHECK21-NEXT:    [[ADD23:%.*]] = add nsw i32 [[TMP24]], 1
11795 // CHECK21-NEXT:    store i32 [[ADD23]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]]
11796 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]]
11797 // CHECK21:       omp.inner.for.end:
11798 // CHECK21-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
11799 // CHECK21:       omp.loop.exit:
11800 // CHECK21-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP9]])
11801 // CHECK21-NEXT:    [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
11802 // CHECK21-NEXT:    [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
11803 // CHECK21-NEXT:    br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
11804 // CHECK21:       .omp.final.then:
11805 // CHECK21-NEXT:    store i32 10, ptr [[I]], align 4
11806 // CHECK21-NEXT:    br label [[DOTOMP_FINAL_DONE]]
11807 // CHECK21:       .omp.final.done:
11808 // CHECK21-NEXT:    ret void
11809 //
11810 //
11811 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197
11812 // CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
11813 // CHECK21-NEXT:  entry:
11814 // CHECK21-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
11815 // CHECK21-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
11816 // CHECK21-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
11817 // CHECK21-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
11818 // CHECK21-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
11819 // CHECK21-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
11820 // CHECK21-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
11821 // CHECK21-NEXT:    [[N_CASTED:%.*]] = alloca i64, align 8
11822 // CHECK21-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
11823 // CHECK21-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
11824 // CHECK21-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
11825 // CHECK21-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
11826 // CHECK21-NEXT:    store i64 [[N]], ptr [[N_ADDR]], align 8
11827 // CHECK21-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
11828 // CHECK21-NEXT:    store i64 [[AAA]], ptr [[AAA_ADDR]], align 8
11829 // CHECK21-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
11830 // CHECK21-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
11831 // CHECK21-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
11832 // CHECK21-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 4
11833 // CHECK21-NEXT:    [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8
11834 // CHECK21-NEXT:    [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4
11835 // CHECK21-NEXT:    store i32 [[TMP3]], ptr [[N_CASTED]], align 4
11836 // CHECK21-NEXT:    [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8
11837 // CHECK21-NEXT:    [[TMP5:%.*]] = load i16, ptr [[AA_ADDR]], align 2
11838 // CHECK21-NEXT:    store i16 [[TMP5]], ptr [[AA_CASTED]], align 2
11839 // CHECK21-NEXT:    [[TMP6:%.*]] = load i64, ptr [[AA_CASTED]], align 8
11840 // CHECK21-NEXT:    [[TMP7:%.*]] = load i8, ptr [[AAA_ADDR]], align 1
11841 // CHECK21-NEXT:    store i8 [[TMP7]], ptr [[AAA_CASTED]], align 1
11842 // CHECK21-NEXT:    [[TMP8:%.*]] = load i64, ptr [[AAA_CASTED]], align 8
11843 // CHECK21-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]], ptr [[TMP0]])
11844 // CHECK21-NEXT:    ret void
11845 //
11846 //
11847 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.omp_outlined
11848 // CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[N:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
11849 // CHECK21-NEXT:  entry:
11850 // CHECK21-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
11851 // CHECK21-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
11852 // CHECK21-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
11853 // CHECK21-NEXT:    [[N_ADDR:%.*]] = alloca i64, align 8
11854 // CHECK21-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
11855 // CHECK21-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
11856 // CHECK21-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
11857 // CHECK21-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
11858 // CHECK21-NEXT:    [[TMP:%.*]] = alloca i32, align 4
11859 // CHECK21-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
11860 // CHECK21-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
11861 // CHECK21-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
11862 // CHECK21-NEXT:    [[I:%.*]] = alloca i32, align 4
11863 // CHECK21-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
11864 // CHECK21-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
11865 // CHECK21-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
11866 // CHECK21-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
11867 // CHECK21-NEXT:    [[I5:%.*]] = alloca i32, align 4
11868 // CHECK21-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
11869 // CHECK21-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
11870 // CHECK21-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
11871 // CHECK21-NEXT:    store i64 [[N]], ptr [[N_ADDR]], align 8
11872 // CHECK21-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
11873 // CHECK21-NEXT:    store i64 [[AAA]], ptr [[AAA_ADDR]], align 8
11874 // CHECK21-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
11875 // CHECK21-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
11876 // CHECK21-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
11877 // CHECK21-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
11878 // CHECK21-NEXT:    [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
11879 // CHECK21-NEXT:    store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
11880 // CHECK21-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
11881 // CHECK21-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
11882 // CHECK21-NEXT:    [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
11883 // CHECK21-NEXT:    [[SUB3:%.*]] = sub i32 [[SUB]], 1
11884 // CHECK21-NEXT:    [[ADD:%.*]] = add i32 [[SUB3]], 1
11885 // CHECK21-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
11886 // CHECK21-NEXT:    [[SUB4:%.*]] = sub i32 [[DIV]], 1
11887 // CHECK21-NEXT:    store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 4
11888 // CHECK21-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
11889 // CHECK21-NEXT:    store i32 [[TMP5]], ptr [[I]], align 4
11890 // CHECK21-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
11891 // CHECK21-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
11892 // CHECK21-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
11893 // CHECK21-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
11894 // CHECK21:       omp.precond.then:
11895 // CHECK21-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
11896 // CHECK21-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
11897 // CHECK21-NEXT:    store i32 [[TMP8]], ptr [[DOTOMP_UB]], align 4
11898 // CHECK21-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
11899 // CHECK21-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
11900 // CHECK21-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
11901 // CHECK21-NEXT:    [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4
11902 // CHECK21-NEXT:    call void @__kmpc_for_static_init_4u(ptr @[[GLOB1]], i32 [[TMP10]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
11903 // CHECK21-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
11904 // CHECK21-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
11905 // CHECK21-NEXT:    [[CMP6:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]]
11906 // CHECK21-NEXT:    br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
11907 // CHECK21:       cond.true:
11908 // CHECK21-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
11909 // CHECK21-NEXT:    br label [[COND_END:%.*]]
11910 // CHECK21:       cond.false:
11911 // CHECK21-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
11912 // CHECK21-NEXT:    br label [[COND_END]]
11913 // CHECK21:       cond.end:
11914 // CHECK21-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ]
11915 // CHECK21-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
11916 // CHECK21-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
11917 // CHECK21-NEXT:    store i32 [[TMP15]], ptr [[DOTOMP_IV]], align 4
11918 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
11919 // CHECK21:       omp.inner.for.cond:
11920 // CHECK21-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27:![0-9]+]]
11921 // CHECK21-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP27]]
11922 // CHECK21-NEXT:    [[ADD7:%.*]] = add i32 [[TMP17]], 1
11923 // CHECK21-NEXT:    [[CMP8:%.*]] = icmp ult i32 [[TMP16]], [[ADD7]]
11924 // CHECK21-NEXT:    br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
11925 // CHECK21:       omp.inner.for.body:
11926 // CHECK21-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group [[ACC_GRP27]]
11927 // CHECK21-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]]
11928 // CHECK21-NEXT:    [[MUL:%.*]] = mul i32 [[TMP19]], 1
11929 // CHECK21-NEXT:    [[ADD9:%.*]] = add i32 [[TMP18]], [[MUL]]
11930 // CHECK21-NEXT:    store i32 [[ADD9]], ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP27]]
11931 // CHECK21-NEXT:    [[TMP20:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP27]]
11932 // CHECK21-NEXT:    [[ADD10:%.*]] = add nsw i32 [[TMP20]], 1
11933 // CHECK21-NEXT:    store i32 [[ADD10]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP27]]
11934 // CHECK21-NEXT:    [[TMP21:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP27]]
11935 // CHECK21-NEXT:    [[CONV:%.*]] = sext i16 [[TMP21]] to i32
11936 // CHECK21-NEXT:    [[ADD11:%.*]] = add nsw i32 [[CONV]], 1
11937 // CHECK21-NEXT:    [[CONV12:%.*]] = trunc i32 [[ADD11]] to i16
11938 // CHECK21-NEXT:    store i16 [[CONV12]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP27]]
11939 // CHECK21-NEXT:    [[TMP22:%.*]] = load i8, ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP27]]
11940 // CHECK21-NEXT:    [[CONV13:%.*]] = sext i8 [[TMP22]] to i32
11941 // CHECK21-NEXT:    [[ADD14:%.*]] = add nsw i32 [[CONV13]], 1
11942 // CHECK21-NEXT:    [[CONV15:%.*]] = trunc i32 [[ADD14]] to i8
11943 // CHECK21-NEXT:    store i8 [[CONV15]], ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP27]]
11944 // CHECK21-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2
11945 // CHECK21-NEXT:    [[TMP23:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP27]]
11946 // CHECK21-NEXT:    [[ADD16:%.*]] = add nsw i32 [[TMP23]], 1
11947 // CHECK21-NEXT:    store i32 [[ADD16]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP27]]
11948 // CHECK21-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
11949 // CHECK21:       omp.body.continue:
11950 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
11951 // CHECK21:       omp.inner.for.inc:
11952 // CHECK21-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]]
11953 // CHECK21-NEXT:    [[ADD17:%.*]] = add i32 [[TMP24]], 1
11954 // CHECK21-NEXT:    store i32 [[ADD17]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]]
11955 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]]
11956 // CHECK21:       omp.inner.for.end:
11957 // CHECK21-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
11958 // CHECK21:       omp.loop.exit:
11959 // CHECK21-NEXT:    [[TMP25:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
11960 // CHECK21-NEXT:    [[TMP26:%.*]] = load i32, ptr [[TMP25]], align 4
11961 // CHECK21-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP26]])
11962 // CHECK21-NEXT:    [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
11963 // CHECK21-NEXT:    [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
11964 // CHECK21-NEXT:    br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
11965 // CHECK21:       .omp.final.then:
11966 // CHECK21-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
11967 // CHECK21-NEXT:    [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
11968 // CHECK21-NEXT:    [[TMP31:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
11969 // CHECK21-NEXT:    [[SUB18:%.*]] = sub i32 [[TMP30]], [[TMP31]]
11970 // CHECK21-NEXT:    [[SUB19:%.*]] = sub i32 [[SUB18]], 1
11971 // CHECK21-NEXT:    [[ADD20:%.*]] = add i32 [[SUB19]], 1
11972 // CHECK21-NEXT:    [[DIV21:%.*]] = udiv i32 [[ADD20]], 1
11973 // CHECK21-NEXT:    [[MUL22:%.*]] = mul i32 [[DIV21]], 1
11974 // CHECK21-NEXT:    [[ADD23:%.*]] = add i32 [[TMP29]], [[MUL22]]
11975 // CHECK21-NEXT:    store i32 [[ADD23]], ptr [[I5]], align 4
11976 // CHECK21-NEXT:    br label [[DOTOMP_FINAL_DONE]]
11977 // CHECK21:       .omp.final.done:
11978 // CHECK21-NEXT:    br label [[OMP_PRECOND_END]]
11979 // CHECK21:       omp.precond.end:
11980 // CHECK21-NEXT:    ret void
11981 //
11982 //
11983 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215
11984 // CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
11985 // CHECK21-NEXT:  entry:
11986 // CHECK21-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
11987 // CHECK21-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
11988 // CHECK21-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
11989 // CHECK21-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
11990 // CHECK21-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
11991 // CHECK21-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
11992 // CHECK21-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
11993 // CHECK21-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
11994 // CHECK21-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
11995 // CHECK21-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
11996 // CHECK21-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
11997 // CHECK21-NEXT:    store i64 [[B]], ptr [[B_ADDR]], align 8
11998 // CHECK21-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
11999 // CHECK21-NEXT:    store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
12000 // CHECK21-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
12001 // CHECK21-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
12002 // CHECK21-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
12003 // CHECK21-NEXT:    [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
12004 // CHECK21-NEXT:    [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
12005 // CHECK21-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
12006 // CHECK21-NEXT:    [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4
12007 // CHECK21-NEXT:    store i32 [[TMP4]], ptr [[B_CASTED]], align 4
12008 // CHECK21-NEXT:    [[TMP5:%.*]] = load i64, ptr [[B_CASTED]], align 8
12009 // CHECK21-NEXT:    [[TMP6:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1
12010 // CHECK21-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1
12011 // CHECK21-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
12012 // CHECK21-NEXT:    store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1
12013 // CHECK21-NEXT:    [[TMP7:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8
12014 // CHECK21-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.omp_outlined, ptr [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], ptr [[TMP3]], i64 [[TMP7]])
12015 // CHECK21-NEXT:    ret void
12016 //
12017 //
12018 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.omp_outlined
12019 // CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
12020 // CHECK21-NEXT:  entry:
12021 // CHECK21-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
12022 // CHECK21-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
12023 // CHECK21-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
12024 // CHECK21-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
12025 // CHECK21-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
12026 // CHECK21-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
12027 // CHECK21-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 8
12028 // CHECK21-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
12029 // CHECK21-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
12030 // CHECK21-NEXT:    [[TMP:%.*]] = alloca i32, align 4
12031 // CHECK21-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
12032 // CHECK21-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
12033 // CHECK21-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
12034 // CHECK21-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
12035 // CHECK21-NEXT:    [[I:%.*]] = alloca i32, align 4
12036 // CHECK21-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
12037 // CHECK21-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
12038 // CHECK21-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
12039 // CHECK21-NEXT:    store i64 [[B]], ptr [[B_ADDR]], align 8
12040 // CHECK21-NEXT:    store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
12041 // CHECK21-NEXT:    store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
12042 // CHECK21-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 8
12043 // CHECK21-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
12044 // CHECK21-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
12045 // CHECK21-NEXT:    [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
12046 // CHECK21-NEXT:    [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
12047 // CHECK21-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
12048 // CHECK21-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
12049 // CHECK21-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4
12050 // CHECK21-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
12051 // CHECK21-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
12052 // CHECK21-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
12053 // CHECK21-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
12054 // CHECK21-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
12055 // CHECK21-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
12056 // CHECK21-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9
12057 // CHECK21-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
12058 // CHECK21:       cond.true:
12059 // CHECK21-NEXT:    br label [[COND_END:%.*]]
12060 // CHECK21:       cond.false:
12061 // CHECK21-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
12062 // CHECK21-NEXT:    br label [[COND_END]]
12063 // CHECK21:       cond.end:
12064 // CHECK21-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
12065 // CHECK21-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
12066 // CHECK21-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
12067 // CHECK21-NEXT:    store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4
12068 // CHECK21-NEXT:    [[TMP9:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1
12069 // CHECK21-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP9]] to i1
12070 // CHECK21-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
12071 // CHECK21:       omp_if.then:
12072 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
12073 // CHECK21:       omp.inner.for.cond:
12074 // CHECK21-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30:![0-9]+]]
12075 // CHECK21-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP30]]
12076 // CHECK21-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
12077 // CHECK21-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
12078 // CHECK21:       omp.inner.for.body:
12079 // CHECK21-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30]]
12080 // CHECK21-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
12081 // CHECK21-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
12082 // CHECK21-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP30]]
12083 // CHECK21-NEXT:    [[TMP13:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP30]]
12084 // CHECK21-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP13]] to double
12085 // CHECK21-NEXT:    [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00
12086 // CHECK21-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0
12087 // CHECK21-NEXT:    store double [[ADD4]], ptr [[A]], align 8, !llvm.access.group [[ACC_GRP30]]
12088 // CHECK21-NEXT:    [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0
12089 // CHECK21-NEXT:    [[TMP14:%.*]] = load double, ptr [[A5]], align 8, !llvm.access.group [[ACC_GRP30]]
12090 // CHECK21-NEXT:    [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00
12091 // CHECK21-NEXT:    store double [[INC]], ptr [[A5]], align 8, !llvm.access.group [[ACC_GRP30]]
12092 // CHECK21-NEXT:    [[CONV6:%.*]] = fptosi double [[INC]] to i16
12093 // CHECK21-NEXT:    [[TMP15:%.*]] = mul nsw i64 1, [[TMP2]]
12094 // CHECK21-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i64 [[TMP15]]
12095 // CHECK21-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1
12096 // CHECK21-NEXT:    store i16 [[CONV6]], ptr [[ARRAYIDX7]], align 2, !llvm.access.group [[ACC_GRP30]]
12097 // CHECK21-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
12098 // CHECK21:       omp.body.continue:
12099 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
12100 // CHECK21:       omp.inner.for.inc:
12101 // CHECK21-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30]]
12102 // CHECK21-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP16]], 1
12103 // CHECK21-NEXT:    store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP30]]
12104 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]]
12105 // CHECK21:       omp.inner.for.end:
12106 // CHECK21-NEXT:    br label [[OMP_IF_END:%.*]]
12107 // CHECK21:       omp_if.else:
12108 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND9:%.*]]
12109 // CHECK21:       omp.inner.for.cond9:
12110 // CHECK21-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
12111 // CHECK21-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
12112 // CHECK21-NEXT:    [[CMP10:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]
12113 // CHECK21-NEXT:    br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END25:%.*]]
12114 // CHECK21:       omp.inner.for.body11:
12115 // CHECK21-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
12116 // CHECK21-NEXT:    [[MUL12:%.*]] = mul nsw i32 [[TMP19]], 1
12117 // CHECK21-NEXT:    [[ADD13:%.*]] = add nsw i32 0, [[MUL12]]
12118 // CHECK21-NEXT:    store i32 [[ADD13]], ptr [[I]], align 4
12119 // CHECK21-NEXT:    [[TMP20:%.*]] = load i32, ptr [[B_ADDR]], align 4
12120 // CHECK21-NEXT:    [[CONV14:%.*]] = sitofp i32 [[TMP20]] to double
12121 // CHECK21-NEXT:    [[ADD15:%.*]] = fadd double [[CONV14]], 1.500000e+00
12122 // CHECK21-NEXT:    [[A16:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0
12123 // CHECK21-NEXT:    store double [[ADD15]], ptr [[A16]], align 8
12124 // CHECK21-NEXT:    [[A17:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0
12125 // CHECK21-NEXT:    [[TMP21:%.*]] = load double, ptr [[A17]], align 8
12126 // CHECK21-NEXT:    [[INC18:%.*]] = fadd double [[TMP21]], 1.000000e+00
12127 // CHECK21-NEXT:    store double [[INC18]], ptr [[A17]], align 8
12128 // CHECK21-NEXT:    [[CONV19:%.*]] = fptosi double [[INC18]] to i16
12129 // CHECK21-NEXT:    [[TMP22:%.*]] = mul nsw i64 1, [[TMP2]]
12130 // CHECK21-NEXT:    [[ARRAYIDX20:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i64 [[TMP22]]
12131 // CHECK21-NEXT:    [[ARRAYIDX21:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX20]], i64 1
12132 // CHECK21-NEXT:    store i16 [[CONV19]], ptr [[ARRAYIDX21]], align 2
12133 // CHECK21-NEXT:    br label [[OMP_BODY_CONTINUE22:%.*]]
12134 // CHECK21:       omp.body.continue22:
12135 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_INC23:%.*]]
12136 // CHECK21:       omp.inner.for.inc23:
12137 // CHECK21-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
12138 // CHECK21-NEXT:    [[ADD24:%.*]] = add nsw i32 [[TMP23]], 1
12139 // CHECK21-NEXT:    store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4
12140 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP33:![0-9]+]]
12141 // CHECK21:       omp.inner.for.end25:
12142 // CHECK21-NEXT:    br label [[OMP_IF_END]]
12143 // CHECK21:       omp_if.end:
12144 // CHECK21-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
12145 // CHECK21:       omp.loop.exit:
12146 // CHECK21-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])
12147 // CHECK21-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
12148 // CHECK21-NEXT:    [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
12149 // CHECK21-NEXT:    br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
12150 // CHECK21:       .omp.final.then:
12151 // CHECK21-NEXT:    store i32 10, ptr [[I]], align 4
12152 // CHECK21-NEXT:    br label [[DOTOMP_FINAL_DONE]]
12153 // CHECK21:       .omp.final.done:
12154 // CHECK21-NEXT:    ret void
12155 //
12156 //
12157 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180
12158 // CHECK21-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
12159 // CHECK21-NEXT:  entry:
12160 // CHECK21-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
12161 // CHECK21-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
12162 // CHECK21-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
12163 // CHECK21-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
12164 // CHECK21-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
12165 // CHECK21-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
12166 // CHECK21-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
12167 // CHECK21-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
12168 // CHECK21-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
12169 // CHECK21-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
12170 // CHECK21-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
12171 // CHECK21-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
12172 // CHECK21-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 4
12173 // CHECK21-NEXT:    [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8
12174 // CHECK21-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
12175 // CHECK21-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
12176 // CHECK21-NEXT:    [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8
12177 // CHECK21-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.omp_outlined, i64 [[TMP2]], i64 [[TMP4]], ptr [[TMP0]])
12178 // CHECK21-NEXT:    ret void
12179 //
12180 //
12181 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.omp_outlined
12182 // CHECK21-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
12183 // CHECK21-NEXT:  entry:
12184 // CHECK21-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
12185 // CHECK21-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
12186 // CHECK21-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
12187 // CHECK21-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
12188 // CHECK21-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 8
12189 // CHECK21-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
12190 // CHECK21-NEXT:    [[TMP:%.*]] = alloca i32, align 4
12191 // CHECK21-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
12192 // CHECK21-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
12193 // CHECK21-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
12194 // CHECK21-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
12195 // CHECK21-NEXT:    [[I:%.*]] = alloca i32, align 4
12196 // CHECK21-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
12197 // CHECK21-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
12198 // CHECK21-NEXT:    store i64 [[A]], ptr [[A_ADDR]], align 8
12199 // CHECK21-NEXT:    store i64 [[AA]], ptr [[AA_ADDR]], align 8
12200 // CHECK21-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 8
12201 // CHECK21-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
12202 // CHECK21-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
12203 // CHECK21-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4
12204 // CHECK21-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
12205 // CHECK21-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
12206 // CHECK21-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
12207 // CHECK21-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
12208 // CHECK21-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
12209 // CHECK21-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
12210 // CHECK21-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
12211 // CHECK21-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
12212 // CHECK21:       cond.true:
12213 // CHECK21-NEXT:    br label [[COND_END:%.*]]
12214 // CHECK21:       cond.false:
12215 // CHECK21-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
12216 // CHECK21-NEXT:    br label [[COND_END]]
12217 // CHECK21:       cond.end:
12218 // CHECK21-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
12219 // CHECK21-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
12220 // CHECK21-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
12221 // CHECK21-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
12222 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
12223 // CHECK21:       omp.inner.for.cond:
12224 // CHECK21-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35:![0-9]+]]
12225 // CHECK21-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP35]]
12226 // CHECK21-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
12227 // CHECK21-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
12228 // CHECK21:       omp.inner.for.body:
12229 // CHECK21-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35]]
12230 // CHECK21-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
12231 // CHECK21-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
12232 // CHECK21-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP35]]
12233 // CHECK21-NEXT:    [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP35]]
12234 // CHECK21-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
12235 // CHECK21-NEXT:    store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP35]]
12236 // CHECK21-NEXT:    [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP35]]
12237 // CHECK21-NEXT:    [[CONV:%.*]] = sext i16 [[TMP10]] to i32
12238 // CHECK21-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV]], 1
12239 // CHECK21-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
12240 // CHECK21-NEXT:    store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP35]]
12241 // CHECK21-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2
12242 // CHECK21-NEXT:    [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP35]]
12243 // CHECK21-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1
12244 // CHECK21-NEXT:    store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP35]]
12245 // CHECK21-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
12246 // CHECK21:       omp.body.continue:
12247 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
12248 // CHECK21:       omp.inner.for.inc:
12249 // CHECK21-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35]]
12250 // CHECK21-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP12]], 1
12251 // CHECK21-NEXT:    store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35]]
12252 // CHECK21-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP36:![0-9]+]]
12253 // CHECK21:       omp.inner.for.end:
12254 // CHECK21-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
12255 // CHECK21:       omp.loop.exit:
12256 // CHECK21-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])
12257 // CHECK21-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
12258 // CHECK21-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
12259 // CHECK21-NEXT:    br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
12260 // CHECK21:       .omp.final.then:
12261 // CHECK21-NEXT:    store i32 10, ptr [[I]], align 4
12262 // CHECK21-NEXT:    br label [[DOTOMP_FINAL_DONE]]
12263 // CHECK21:       .omp.final.done:
12264 // CHECK21-NEXT:    ret void
12265 //
12266 //
12267 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97
12268 // CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] {
12269 // CHECK23-NEXT:  entry:
12270 // CHECK23-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
12271 // CHECK23-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
12272 // CHECK23-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
12273 // CHECK23-NEXT:    [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4
12274 // CHECK23-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
12275 // CHECK23-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])
12276 // CHECK23-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
12277 // CHECK23-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
12278 // CHECK23-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
12279 // CHECK23-NEXT:    store i32 [[DOTCAPTURE_EXPR_1]], ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4
12280 // CHECK23-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
12281 // CHECK23-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR2]], align 4
12282 // CHECK23-NEXT:    call void @__kmpc_push_num_teams(ptr @[[GLOB2]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]])
12283 // CHECK23-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
12284 // CHECK23-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
12285 // CHECK23-NEXT:    [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4
12286 // CHECK23-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.omp_outlined, i32 [[TMP4]])
12287 // CHECK23-NEXT:    ret void
12288 //
12289 //
12290 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l97.omp_outlined
12291 // CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {
12292 // CHECK23-NEXT:  entry:
12293 // CHECK23-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
12294 // CHECK23-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
12295 // CHECK23-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
12296 // CHECK23-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
12297 // CHECK23-NEXT:    [[TMP:%.*]] = alloca i32, align 4
12298 // CHECK23-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
12299 // CHECK23-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
12300 // CHECK23-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
12301 // CHECK23-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
12302 // CHECK23-NEXT:    [[I:%.*]] = alloca i32, align 4
12303 // CHECK23-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
12304 // CHECK23-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
12305 // CHECK23-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
12306 // CHECK23-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
12307 // CHECK23-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4
12308 // CHECK23-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
12309 // CHECK23-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
12310 // CHECK23-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
12311 // CHECK23-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
12312 // CHECK23-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
12313 // CHECK23-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
12314 // CHECK23-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
12315 // CHECK23-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
12316 // CHECK23:       cond.true:
12317 // CHECK23-NEXT:    br label [[COND_END:%.*]]
12318 // CHECK23:       cond.false:
12319 // CHECK23-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
12320 // CHECK23-NEXT:    br label [[COND_END]]
12321 // CHECK23:       cond.end:
12322 // CHECK23-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
12323 // CHECK23-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
12324 // CHECK23-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
12325 // CHECK23-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
12326 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
12327 // CHECK23:       omp.inner.for.cond:
12328 // CHECK23-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12:![0-9]+]]
12329 // CHECK23-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP12]]
12330 // CHECK23-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
12331 // CHECK23-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
12332 // CHECK23:       omp.inner.for.body:
12333 // CHECK23-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]
12334 // CHECK23-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
12335 // CHECK23-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
12336 // CHECK23-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]]
12337 // CHECK23-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
12338 // CHECK23:       omp.body.continue:
12339 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
12340 // CHECK23:       omp.inner.for.inc:
12341 // CHECK23-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]
12342 // CHECK23-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
12343 // CHECK23-NEXT:    store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]
12344 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
12345 // CHECK23:       omp.inner.for.end:
12346 // CHECK23-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
12347 // CHECK23:       omp.loop.exit:
12348 // CHECK23-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
12349 // CHECK23-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
12350 // CHECK23-NEXT:    [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
12351 // CHECK23-NEXT:    br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
12352 // CHECK23:       .omp.final.then:
12353 // CHECK23-NEXT:    store i32 10, ptr [[I]], align 4
12354 // CHECK23-NEXT:    br label [[DOTOMP_FINAL_DONE]]
12355 // CHECK23:       .omp.final.done:
12356 // CHECK23-NEXT:    ret void
12357 //
12358 //
12359 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111
12360 // CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {
12361 // CHECK23-NEXT:  entry:
12362 // CHECK23-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
12363 // CHECK23-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
12364 // CHECK23-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
12365 // CHECK23-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
12366 // CHECK23-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
12367 // CHECK23-NEXT:    [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2
12368 // CHECK23-NEXT:    store i16 [[TMP0]], ptr [[AA_CASTED]], align 2
12369 // CHECK23-NEXT:    [[TMP1:%.*]] = load i32, ptr [[AA_CASTED]], align 4
12370 // CHECK23-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined, i32 [[TMP1]])
12371 // CHECK23-NEXT:    ret void
12372 //
12373 //
12374 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.omp_outlined
12375 // CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {
12376 // CHECK23-NEXT:  entry:
12377 // CHECK23-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
12378 // CHECK23-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
12379 // CHECK23-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
12380 // CHECK23-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
12381 // CHECK23-NEXT:    [[TMP:%.*]] = alloca i32, align 4
12382 // CHECK23-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
12383 // CHECK23-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
12384 // CHECK23-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
12385 // CHECK23-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
12386 // CHECK23-NEXT:    [[I:%.*]] = alloca i32, align 4
12387 // CHECK23-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
12388 // CHECK23-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
12389 // CHECK23-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
12390 // CHECK23-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
12391 // CHECK23-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4
12392 // CHECK23-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
12393 // CHECK23-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
12394 // CHECK23-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
12395 // CHECK23-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
12396 // CHECK23-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
12397 // CHECK23-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
12398 // CHECK23-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
12399 // CHECK23-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
12400 // CHECK23:       cond.true:
12401 // CHECK23-NEXT:    br label [[COND_END:%.*]]
12402 // CHECK23:       cond.false:
12403 // CHECK23-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
12404 // CHECK23-NEXT:    br label [[COND_END]]
12405 // CHECK23:       cond.end:
12406 // CHECK23-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
12407 // CHECK23-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
12408 // CHECK23-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
12409 // CHECK23-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
12410 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
12411 // CHECK23:       omp.inner.for.cond:
12412 // CHECK23-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19:![0-9]+]]
12413 // CHECK23-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP19]]
12414 // CHECK23-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
12415 // CHECK23-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
12416 // CHECK23:       omp.inner.for.body:
12417 // CHECK23-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]]
12418 // CHECK23-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
12419 // CHECK23-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
12420 // CHECK23-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]]
12421 // CHECK23-NEXT:    [[TMP8:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP19]]
12422 // CHECK23-NEXT:    [[CONV:%.*]] = sext i16 [[TMP8]] to i32
12423 // CHECK23-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
12424 // CHECK23-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
12425 // CHECK23-NEXT:    store i16 [[CONV3]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP19]]
12426 // CHECK23-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
12427 // CHECK23:       omp.body.continue:
12428 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
12429 // CHECK23:       omp.inner.for.inc:
12430 // CHECK23-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]]
12431 // CHECK23-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP9]], 1
12432 // CHECK23-NEXT:    store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP19]]
12433 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]]
12434 // CHECK23:       omp.inner.for.end:
12435 // CHECK23-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
12436 // CHECK23:       omp.loop.exit:
12437 // CHECK23-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
12438 // CHECK23-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
12439 // CHECK23-NEXT:    [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
12440 // CHECK23-NEXT:    br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
12441 // CHECK23:       .omp.final.then:
12442 // CHECK23-NEXT:    store i32 10, ptr [[I]], align 4
12443 // CHECK23-NEXT:    br label [[DOTOMP_FINAL_DONE]]
12444 // CHECK23:       .omp.final.done:
12445 // CHECK23-NEXT:    ret void
12446 //
12447 //
12448 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118
12449 // CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {
12450 // CHECK23-NEXT:  entry:
12451 // CHECK23-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
12452 // CHECK23-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
12453 // CHECK23-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
12454 // CHECK23-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
12455 // CHECK23-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
12456 // CHECK23-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
12457 // CHECK23-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
12458 // CHECK23-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
12459 // CHECK23-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
12460 // CHECK23-NEXT:    store i32 [[TMP0]], ptr [[A_CASTED]], align 4
12461 // CHECK23-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4
12462 // CHECK23-NEXT:    [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2
12463 // CHECK23-NEXT:    store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
12464 // CHECK23-NEXT:    [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4
12465 // CHECK23-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined, i32 [[TMP1]], i32 [[TMP3]])
12466 // CHECK23-NEXT:    ret void
12467 //
12468 //
12469 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.omp_outlined
12470 // CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {
12471 // CHECK23-NEXT:  entry:
12472 // CHECK23-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
12473 // CHECK23-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
12474 // CHECK23-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
12475 // CHECK23-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
12476 // CHECK23-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
12477 // CHECK23-NEXT:    [[TMP:%.*]] = alloca i32, align 4
12478 // CHECK23-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
12479 // CHECK23-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
12480 // CHECK23-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
12481 // CHECK23-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
12482 // CHECK23-NEXT:    [[I:%.*]] = alloca i32, align 4
12483 // CHECK23-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
12484 // CHECK23-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
12485 // CHECK23-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
12486 // CHECK23-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
12487 // CHECK23-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
12488 // CHECK23-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4
12489 // CHECK23-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
12490 // CHECK23-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
12491 // CHECK23-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
12492 // CHECK23-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
12493 // CHECK23-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
12494 // CHECK23-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
12495 // CHECK23-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
12496 // CHECK23-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
12497 // CHECK23:       cond.true:
12498 // CHECK23-NEXT:    br label [[COND_END:%.*]]
12499 // CHECK23:       cond.false:
12500 // CHECK23-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
12501 // CHECK23-NEXT:    br label [[COND_END]]
12502 // CHECK23:       cond.end:
12503 // CHECK23-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
12504 // CHECK23-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
12505 // CHECK23-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
12506 // CHECK23-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
12507 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
12508 // CHECK23:       omp.inner.for.cond:
12509 // CHECK23-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22:![0-9]+]]
12510 // CHECK23-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP22]]
12511 // CHECK23-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
12512 // CHECK23-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
12513 // CHECK23:       omp.inner.for.body:
12514 // CHECK23-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]]
12515 // CHECK23-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
12516 // CHECK23-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
12517 // CHECK23-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]]
12518 // CHECK23-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP22]]
12519 // CHECK23-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
12520 // CHECK23-NEXT:    store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP22]]
12521 // CHECK23-NEXT:    [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP22]]
12522 // CHECK23-NEXT:    [[CONV:%.*]] = sext i16 [[TMP9]] to i32
12523 // CHECK23-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV]], 1
12524 // CHECK23-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
12525 // CHECK23-NEXT:    store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP22]]
12526 // CHECK23-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
12527 // CHECK23:       omp.body.continue:
12528 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
12529 // CHECK23:       omp.inner.for.inc:
12530 // CHECK23-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]]
12531 // CHECK23-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP10]], 1
12532 // CHECK23-NEXT:    store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP22]]
12533 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]]
12534 // CHECK23:       omp.inner.for.end:
12535 // CHECK23-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
12536 // CHECK23:       omp.loop.exit:
12537 // CHECK23-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
12538 // CHECK23-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
12539 // CHECK23-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
12540 // CHECK23-NEXT:    br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
12541 // CHECK23:       .omp.final.then:
12542 // CHECK23-NEXT:    store i32 10, ptr [[I]], align 4
12543 // CHECK23-NEXT:    br label [[DOTOMP_FINAL_DONE]]
12544 // CHECK23:       .omp.final.done:
12545 // CHECK23-NEXT:    ret void
12546 //
12547 //
12548 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142
12549 // CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] {
12550 // CHECK23-NEXT:  entry:
12551 // CHECK23-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
12552 // CHECK23-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
12553 // CHECK23-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
12554 // CHECK23-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
12555 // CHECK23-NEXT:    [[BN_ADDR:%.*]] = alloca ptr, align 4
12556 // CHECK23-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
12557 // CHECK23-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
12558 // CHECK23-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
12559 // CHECK23-NEXT:    [[CN_ADDR:%.*]] = alloca ptr, align 4
12560 // CHECK23-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4
12561 // CHECK23-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
12562 // CHECK23-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
12563 // CHECK23-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
12564 // CHECK23-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
12565 // CHECK23-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
12566 // CHECK23-NEXT:    store ptr [[BN]], ptr [[BN_ADDR]], align 4
12567 // CHECK23-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
12568 // CHECK23-NEXT:    store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
12569 // CHECK23-NEXT:    store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4
12570 // CHECK23-NEXT:    store ptr [[CN]], ptr [[CN_ADDR]], align 4
12571 // CHECK23-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4
12572 // CHECK23-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
12573 // CHECK23-NEXT:    [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
12574 // CHECK23-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4
12575 // CHECK23-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
12576 // CHECK23-NEXT:    [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
12577 // CHECK23-NEXT:    [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4
12578 // CHECK23-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4
12579 // CHECK23-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4
12580 // CHECK23-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
12581 // CHECK23-NEXT:    store i32 [[TMP8]], ptr [[A_CASTED]], align 4
12582 // CHECK23-NEXT:    [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4
12583 // CHECK23-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 9, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.omp_outlined, i32 [[TMP9]], ptr [[TMP0]], i32 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]])
12584 // CHECK23-NEXT:    ret void
12585 //
12586 //
12587 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.omp_outlined
12588 // CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] {
12589 // CHECK23-NEXT:  entry:
12590 // CHECK23-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
12591 // CHECK23-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
12592 // CHECK23-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
12593 // CHECK23-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
12594 // CHECK23-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
12595 // CHECK23-NEXT:    [[BN_ADDR:%.*]] = alloca ptr, align 4
12596 // CHECK23-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
12597 // CHECK23-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
12598 // CHECK23-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
12599 // CHECK23-NEXT:    [[CN_ADDR:%.*]] = alloca ptr, align 4
12600 // CHECK23-NEXT:    [[D_ADDR:%.*]] = alloca ptr, align 4
12601 // CHECK23-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
12602 // CHECK23-NEXT:    [[TMP:%.*]] = alloca i32, align 4
12603 // CHECK23-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
12604 // CHECK23-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
12605 // CHECK23-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
12606 // CHECK23-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
12607 // CHECK23-NEXT:    [[I:%.*]] = alloca i32, align 4
12608 // CHECK23-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
12609 // CHECK23-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
12610 // CHECK23-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
12611 // CHECK23-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
12612 // CHECK23-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
12613 // CHECK23-NEXT:    store ptr [[BN]], ptr [[BN_ADDR]], align 4
12614 // CHECK23-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
12615 // CHECK23-NEXT:    store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
12616 // CHECK23-NEXT:    store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4
12617 // CHECK23-NEXT:    store ptr [[CN]], ptr [[CN_ADDR]], align 4
12618 // CHECK23-NEXT:    store ptr [[D]], ptr [[D_ADDR]], align 4
12619 // CHECK23-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
12620 // CHECK23-NEXT:    [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
12621 // CHECK23-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4
12622 // CHECK23-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
12623 // CHECK23-NEXT:    [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
12624 // CHECK23-NEXT:    [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4
12625 // CHECK23-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4
12626 // CHECK23-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4
12627 // CHECK23-NEXT:    [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 0
12628 // CHECK23-NEXT:    call void @llvm.assume(i1 true) [ "align"(ptr [[ARRAYDECAY]], i32 16) ]
12629 // CHECK23-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
12630 // CHECK23-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4
12631 // CHECK23-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
12632 // CHECK23-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
12633 // CHECK23-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
12634 // CHECK23-NEXT:    [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
12635 // CHECK23-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP9]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
12636 // CHECK23-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
12637 // CHECK23-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP10]], 9
12638 // CHECK23-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
12639 // CHECK23:       cond.true:
12640 // CHECK23-NEXT:    br label [[COND_END:%.*]]
12641 // CHECK23:       cond.false:
12642 // CHECK23-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
12643 // CHECK23-NEXT:    br label [[COND_END]]
12644 // CHECK23:       cond.end:
12645 // CHECK23-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
12646 // CHECK23-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
12647 // CHECK23-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
12648 // CHECK23-NEXT:    store i32 [[TMP12]], ptr [[DOTOMP_IV]], align 4
12649 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
12650 // CHECK23:       omp.inner.for.cond:
12651 // CHECK23-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25:![0-9]+]]
12652 // CHECK23-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP25]]
12653 // CHECK23-NEXT:    [[CMP5:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]]
12654 // CHECK23-NEXT:    br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
12655 // CHECK23:       omp.inner.for.body:
12656 // CHECK23-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]]
12657 // CHECK23-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
12658 // CHECK23-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
12659 // CHECK23-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP25]]
12660 // CHECK23-NEXT:    [[TMP16:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP25]]
12661 // CHECK23-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1
12662 // CHECK23-NEXT:    store i32 [[ADD6]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP25]]
12663 // CHECK23-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 2
12664 // CHECK23-NEXT:    [[TMP17:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP25]]
12665 // CHECK23-NEXT:    [[CONV:%.*]] = fpext float [[TMP17]] to double
12666 // CHECK23-NEXT:    [[ADD7:%.*]] = fadd double [[CONV]], 1.000000e+00
12667 // CHECK23-NEXT:    [[CONV8:%.*]] = fptrunc double [[ADD7]] to float
12668 // CHECK23-NEXT:    store float [[CONV8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP25]]
12669 // CHECK23-NEXT:    [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i32 3
12670 // CHECK23-NEXT:    [[TMP18:%.*]] = load float, ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP25]]
12671 // CHECK23-NEXT:    [[CONV10:%.*]] = fpext float [[TMP18]] to double
12672 // CHECK23-NEXT:    [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00
12673 // CHECK23-NEXT:    [[CONV12:%.*]] = fptrunc double [[ADD11]] to float
12674 // CHECK23-NEXT:    store float [[CONV12]], ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP25]]
12675 // CHECK23-NEXT:    [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 1
12676 // CHECK23-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX13]], i32 0, i32 2
12677 // CHECK23-NEXT:    [[TMP19:%.*]] = load double, ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP25]]
12678 // CHECK23-NEXT:    [[ADD15:%.*]] = fadd double [[TMP19]], 1.000000e+00
12679 // CHECK23-NEXT:    store double [[ADD15]], ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP25]]
12680 // CHECK23-NEXT:    [[TMP20:%.*]] = mul nsw i32 1, [[TMP5]]
12681 // CHECK23-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i32 [[TMP20]]
12682 // CHECK23-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX16]], i32 3
12683 // CHECK23-NEXT:    [[TMP21:%.*]] = load double, ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP25]]
12684 // CHECK23-NEXT:    [[ADD18:%.*]] = fadd double [[TMP21]], 1.000000e+00
12685 // CHECK23-NEXT:    store double [[ADD18]], ptr [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP25]]
12686 // CHECK23-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0
12687 // CHECK23-NEXT:    [[TMP22:%.*]] = load i64, ptr [[X]], align 4, !llvm.access.group [[ACC_GRP25]]
12688 // CHECK23-NEXT:    [[ADD19:%.*]] = add nsw i64 [[TMP22]], 1
12689 // CHECK23-NEXT:    store i64 [[ADD19]], ptr [[X]], align 4, !llvm.access.group [[ACC_GRP25]]
12690 // CHECK23-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1
12691 // CHECK23-NEXT:    [[TMP23:%.*]] = load i8, ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP25]]
12692 // CHECK23-NEXT:    [[CONV20:%.*]] = sext i8 [[TMP23]] to i32
12693 // CHECK23-NEXT:    [[ADD21:%.*]] = add nsw i32 [[CONV20]], 1
12694 // CHECK23-NEXT:    [[CONV22:%.*]] = trunc i32 [[ADD21]] to i8
12695 // CHECK23-NEXT:    store i8 [[CONV22]], ptr [[Y]], align 4, !llvm.access.group [[ACC_GRP25]]
12696 // CHECK23-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
12697 // CHECK23:       omp.body.continue:
12698 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
12699 // CHECK23:       omp.inner.for.inc:
12700 // CHECK23-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]]
12701 // CHECK23-NEXT:    [[ADD23:%.*]] = add nsw i32 [[TMP24]], 1
12702 // CHECK23-NEXT:    store i32 [[ADD23]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP25]]
12703 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]]
12704 // CHECK23:       omp.inner.for.end:
12705 // CHECK23-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
12706 // CHECK23:       omp.loop.exit:
12707 // CHECK23-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP9]])
12708 // CHECK23-NEXT:    [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
12709 // CHECK23-NEXT:    [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
12710 // CHECK23-NEXT:    br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
12711 // CHECK23:       .omp.final.then:
12712 // CHECK23-NEXT:    store i32 10, ptr [[I]], align 4
12713 // CHECK23-NEXT:    br label [[DOTOMP_FINAL_DONE]]
12714 // CHECK23:       .omp.final.done:
12715 // CHECK23-NEXT:    ret void
12716 //
12717 //
12718 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197
12719 // CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
12720 // CHECK23-NEXT:  entry:
12721 // CHECK23-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
12722 // CHECK23-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
12723 // CHECK23-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
12724 // CHECK23-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
12725 // CHECK23-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
12726 // CHECK23-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
12727 // CHECK23-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
12728 // CHECK23-NEXT:    [[N_CASTED:%.*]] = alloca i32, align 4
12729 // CHECK23-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
12730 // CHECK23-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
12731 // CHECK23-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
12732 // CHECK23-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
12733 // CHECK23-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
12734 // CHECK23-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
12735 // CHECK23-NEXT:    store i32 [[AAA]], ptr [[AAA_ADDR]], align 4
12736 // CHECK23-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
12737 // CHECK23-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
12738 // CHECK23-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
12739 // CHECK23-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 4
12740 // CHECK23-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4
12741 // CHECK23-NEXT:    [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4
12742 // CHECK23-NEXT:    store i32 [[TMP3]], ptr [[N_CASTED]], align 4
12743 // CHECK23-NEXT:    [[TMP4:%.*]] = load i32, ptr [[N_CASTED]], align 4
12744 // CHECK23-NEXT:    [[TMP5:%.*]] = load i16, ptr [[AA_ADDR]], align 2
12745 // CHECK23-NEXT:    store i16 [[TMP5]], ptr [[AA_CASTED]], align 2
12746 // CHECK23-NEXT:    [[TMP6:%.*]] = load i32, ptr [[AA_CASTED]], align 4
12747 // CHECK23-NEXT:    [[TMP7:%.*]] = load i8, ptr [[AAA_ADDR]], align 1
12748 // CHECK23-NEXT:    store i8 [[TMP7]], ptr [[AAA_CASTED]], align 1
12749 // CHECK23-NEXT:    [[TMP8:%.*]] = load i32, ptr [[AAA_CASTED]], align 4
12750 // CHECK23-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]], ptr [[TMP0]])
12751 // CHECK23-NEXT:    ret void
12752 //
12753 //
12754 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l197.omp_outlined
12755 // CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[N:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
12756 // CHECK23-NEXT:  entry:
12757 // CHECK23-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
12758 // CHECK23-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
12759 // CHECK23-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
12760 // CHECK23-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
12761 // CHECK23-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
12762 // CHECK23-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
12763 // CHECK23-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
12764 // CHECK23-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
12765 // CHECK23-NEXT:    [[TMP:%.*]] = alloca i32, align 4
12766 // CHECK23-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
12767 // CHECK23-NEXT:    [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
12768 // CHECK23-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
12769 // CHECK23-NEXT:    [[I:%.*]] = alloca i32, align 4
12770 // CHECK23-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
12771 // CHECK23-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
12772 // CHECK23-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
12773 // CHECK23-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
12774 // CHECK23-NEXT:    [[I5:%.*]] = alloca i32, align 4
12775 // CHECK23-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
12776 // CHECK23-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
12777 // CHECK23-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
12778 // CHECK23-NEXT:    store i32 [[N]], ptr [[N_ADDR]], align 4
12779 // CHECK23-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
12780 // CHECK23-NEXT:    store i32 [[AAA]], ptr [[AAA_ADDR]], align 4
12781 // CHECK23-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
12782 // CHECK23-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
12783 // CHECK23-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
12784 // CHECK23-NEXT:    store i32 [[TMP1]], ptr [[DOTCAPTURE_EXPR_]], align 4
12785 // CHECK23-NEXT:    [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
12786 // CHECK23-NEXT:    store i32 [[TMP2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
12787 // CHECK23-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
12788 // CHECK23-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
12789 // CHECK23-NEXT:    [[SUB:%.*]] = sub i32 [[TMP3]], [[TMP4]]
12790 // CHECK23-NEXT:    [[SUB3:%.*]] = sub i32 [[SUB]], 1
12791 // CHECK23-NEXT:    [[ADD:%.*]] = add i32 [[SUB3]], 1
12792 // CHECK23-NEXT:    [[DIV:%.*]] = udiv i32 [[ADD]], 1
12793 // CHECK23-NEXT:    [[SUB4:%.*]] = sub i32 [[DIV]], 1
12794 // CHECK23-NEXT:    store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_2]], align 4
12795 // CHECK23-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
12796 // CHECK23-NEXT:    store i32 [[TMP5]], ptr [[I]], align 4
12797 // CHECK23-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
12798 // CHECK23-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
12799 // CHECK23-NEXT:    [[CMP:%.*]] = icmp slt i32 [[TMP6]], [[TMP7]]
12800 // CHECK23-NEXT:    br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
12801 // CHECK23:       omp.precond.then:
12802 // CHECK23-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
12803 // CHECK23-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
12804 // CHECK23-NEXT:    store i32 [[TMP8]], ptr [[DOTOMP_UB]], align 4
12805 // CHECK23-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
12806 // CHECK23-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
12807 // CHECK23-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
12808 // CHECK23-NEXT:    [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4
12809 // CHECK23-NEXT:    call void @__kmpc_for_static_init_4u(ptr @[[GLOB1]], i32 [[TMP10]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
12810 // CHECK23-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
12811 // CHECK23-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
12812 // CHECK23-NEXT:    [[CMP6:%.*]] = icmp ugt i32 [[TMP11]], [[TMP12]]
12813 // CHECK23-NEXT:    br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
12814 // CHECK23:       cond.true:
12815 // CHECK23-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
12816 // CHECK23-NEXT:    br label [[COND_END:%.*]]
12817 // CHECK23:       cond.false:
12818 // CHECK23-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
12819 // CHECK23-NEXT:    br label [[COND_END]]
12820 // CHECK23:       cond.end:
12821 // CHECK23-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP13]], [[COND_TRUE]] ], [ [[TMP14]], [[COND_FALSE]] ]
12822 // CHECK23-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
12823 // CHECK23-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
12824 // CHECK23-NEXT:    store i32 [[TMP15]], ptr [[DOTOMP_IV]], align 4
12825 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
12826 // CHECK23:       omp.inner.for.cond:
12827 // CHECK23-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28:![0-9]+]]
12828 // CHECK23-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP28]]
12829 // CHECK23-NEXT:    [[ADD7:%.*]] = add i32 [[TMP17]], 1
12830 // CHECK23-NEXT:    [[CMP8:%.*]] = icmp ult i32 [[TMP16]], [[ADD7]]
12831 // CHECK23-NEXT:    br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
12832 // CHECK23:       omp.inner.for.body:
12833 // CHECK23-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4, !llvm.access.group [[ACC_GRP28]]
12834 // CHECK23-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]]
12835 // CHECK23-NEXT:    [[MUL:%.*]] = mul i32 [[TMP19]], 1
12836 // CHECK23-NEXT:    [[ADD9:%.*]] = add i32 [[TMP18]], [[MUL]]
12837 // CHECK23-NEXT:    store i32 [[ADD9]], ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP28]]
12838 // CHECK23-NEXT:    [[TMP20:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP28]]
12839 // CHECK23-NEXT:    [[ADD10:%.*]] = add nsw i32 [[TMP20]], 1
12840 // CHECK23-NEXT:    store i32 [[ADD10]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP28]]
12841 // CHECK23-NEXT:    [[TMP21:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP28]]
12842 // CHECK23-NEXT:    [[CONV:%.*]] = sext i16 [[TMP21]] to i32
12843 // CHECK23-NEXT:    [[ADD11:%.*]] = add nsw i32 [[CONV]], 1
12844 // CHECK23-NEXT:    [[CONV12:%.*]] = trunc i32 [[ADD11]] to i16
12845 // CHECK23-NEXT:    store i16 [[CONV12]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP28]]
12846 // CHECK23-NEXT:    [[TMP22:%.*]] = load i8, ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP28]]
12847 // CHECK23-NEXT:    [[CONV13:%.*]] = sext i8 [[TMP22]] to i32
12848 // CHECK23-NEXT:    [[ADD14:%.*]] = add nsw i32 [[CONV13]], 1
12849 // CHECK23-NEXT:    [[CONV15:%.*]] = trunc i32 [[ADD14]] to i8
12850 // CHECK23-NEXT:    store i8 [[CONV15]], ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP28]]
12851 // CHECK23-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2
12852 // CHECK23-NEXT:    [[TMP23:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP28]]
12853 // CHECK23-NEXT:    [[ADD16:%.*]] = add nsw i32 [[TMP23]], 1
12854 // CHECK23-NEXT:    store i32 [[ADD16]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP28]]
12855 // CHECK23-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
12856 // CHECK23:       omp.body.continue:
12857 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
12858 // CHECK23:       omp.inner.for.inc:
12859 // CHECK23-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]]
12860 // CHECK23-NEXT:    [[ADD17:%.*]] = add i32 [[TMP24]], 1
12861 // CHECK23-NEXT:    store i32 [[ADD17]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP28]]
12862 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]]
12863 // CHECK23:       omp.inner.for.end:
12864 // CHECK23-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
12865 // CHECK23:       omp.loop.exit:
12866 // CHECK23-NEXT:    [[TMP25:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
12867 // CHECK23-NEXT:    [[TMP26:%.*]] = load i32, ptr [[TMP25]], align 4
12868 // CHECK23-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP26]])
12869 // CHECK23-NEXT:    [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
12870 // CHECK23-NEXT:    [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
12871 // CHECK23-NEXT:    br i1 [[TMP28]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
12872 // CHECK23:       .omp.final.then:
12873 // CHECK23-NEXT:    [[TMP29:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
12874 // CHECK23-NEXT:    [[TMP30:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
12875 // CHECK23-NEXT:    [[TMP31:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
12876 // CHECK23-NEXT:    [[SUB18:%.*]] = sub i32 [[TMP30]], [[TMP31]]
12877 // CHECK23-NEXT:    [[SUB19:%.*]] = sub i32 [[SUB18]], 1
12878 // CHECK23-NEXT:    [[ADD20:%.*]] = add i32 [[SUB19]], 1
12879 // CHECK23-NEXT:    [[DIV21:%.*]] = udiv i32 [[ADD20]], 1
12880 // CHECK23-NEXT:    [[MUL22:%.*]] = mul i32 [[DIV21]], 1
12881 // CHECK23-NEXT:    [[ADD23:%.*]] = add i32 [[TMP29]], [[MUL22]]
12882 // CHECK23-NEXT:    store i32 [[ADD23]], ptr [[I5]], align 4
12883 // CHECK23-NEXT:    br label [[DOTOMP_FINAL_DONE]]
12884 // CHECK23:       .omp.final.done:
12885 // CHECK23-NEXT:    br label [[OMP_PRECOND_END]]
12886 // CHECK23:       omp.precond.end:
12887 // CHECK23-NEXT:    ret void
12888 //
12889 //
12890 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215
12891 // CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
12892 // CHECK23-NEXT:  entry:
12893 // CHECK23-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
12894 // CHECK23-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
12895 // CHECK23-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
12896 // CHECK23-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
12897 // CHECK23-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
12898 // CHECK23-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
12899 // CHECK23-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
12900 // CHECK23-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
12901 // CHECK23-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
12902 // CHECK23-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
12903 // CHECK23-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
12904 // CHECK23-NEXT:    store i32 [[B]], ptr [[B_ADDR]], align 4
12905 // CHECK23-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
12906 // CHECK23-NEXT:    store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
12907 // CHECK23-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
12908 // CHECK23-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
12909 // CHECK23-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
12910 // CHECK23-NEXT:    [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
12911 // CHECK23-NEXT:    [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
12912 // CHECK23-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
12913 // CHECK23-NEXT:    [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4
12914 // CHECK23-NEXT:    store i32 [[TMP4]], ptr [[B_CASTED]], align 4
12915 // CHECK23-NEXT:    [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4
12916 // CHECK23-NEXT:    [[TMP6:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1
12917 // CHECK23-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1
12918 // CHECK23-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8
12919 // CHECK23-NEXT:    store i8 [[FROMBOOL]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1
12920 // CHECK23-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
12921 // CHECK23-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.omp_outlined, ptr [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], ptr [[TMP3]], i32 [[TMP7]])
12922 // CHECK23-NEXT:    ret void
12923 //
12924 //
12925 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l215.omp_outlined
12926 // CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
12927 // CHECK23-NEXT:  entry:
12928 // CHECK23-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
12929 // CHECK23-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
12930 // CHECK23-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
12931 // CHECK23-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
12932 // CHECK23-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
12933 // CHECK23-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
12934 // CHECK23-NEXT:    [[C_ADDR:%.*]] = alloca ptr, align 4
12935 // CHECK23-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
12936 // CHECK23-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
12937 // CHECK23-NEXT:    [[TMP:%.*]] = alloca i32, align 4
12938 // CHECK23-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
12939 // CHECK23-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
12940 // CHECK23-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
12941 // CHECK23-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
12942 // CHECK23-NEXT:    [[I:%.*]] = alloca i32, align 4
12943 // CHECK23-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
12944 // CHECK23-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
12945 // CHECK23-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
12946 // CHECK23-NEXT:    store i32 [[B]], ptr [[B_ADDR]], align 4
12947 // CHECK23-NEXT:    store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
12948 // CHECK23-NEXT:    store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
12949 // CHECK23-NEXT:    store ptr [[C]], ptr [[C_ADDR]], align 4
12950 // CHECK23-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
12951 // CHECK23-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
12952 // CHECK23-NEXT:    [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
12953 // CHECK23-NEXT:    [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
12954 // CHECK23-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
12955 // CHECK23-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
12956 // CHECK23-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4
12957 // CHECK23-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
12958 // CHECK23-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
12959 // CHECK23-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
12960 // CHECK23-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
12961 // CHECK23-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
12962 // CHECK23-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
12963 // CHECK23-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 9
12964 // CHECK23-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
12965 // CHECK23:       cond.true:
12966 // CHECK23-NEXT:    br label [[COND_END:%.*]]
12967 // CHECK23:       cond.false:
12968 // CHECK23-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
12969 // CHECK23-NEXT:    br label [[COND_END]]
12970 // CHECK23:       cond.end:
12971 // CHECK23-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
12972 // CHECK23-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
12973 // CHECK23-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
12974 // CHECK23-NEXT:    store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4
12975 // CHECK23-NEXT:    [[TMP9:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1
12976 // CHECK23-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP9]] to i1
12977 // CHECK23-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
12978 // CHECK23:       omp_if.then:
12979 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
12980 // CHECK23:       omp.inner.for.cond:
12981 // CHECK23-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31:![0-9]+]]
12982 // CHECK23-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP31]]
12983 // CHECK23-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
12984 // CHECK23-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
12985 // CHECK23:       omp.inner.for.body:
12986 // CHECK23-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31]]
12987 // CHECK23-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
12988 // CHECK23-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
12989 // CHECK23-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP31]]
12990 // CHECK23-NEXT:    [[TMP13:%.*]] = load i32, ptr [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP31]]
12991 // CHECK23-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP13]] to double
12992 // CHECK23-NEXT:    [[ADD4:%.*]] = fadd double [[CONV]], 1.500000e+00
12993 // CHECK23-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0
12994 // CHECK23-NEXT:    store double [[ADD4]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP31]]
12995 // CHECK23-NEXT:    [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0
12996 // CHECK23-NEXT:    [[TMP14:%.*]] = load double, ptr [[A5]], align 4, !llvm.access.group [[ACC_GRP31]]
12997 // CHECK23-NEXT:    [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00
12998 // CHECK23-NEXT:    store double [[INC]], ptr [[A5]], align 4, !llvm.access.group [[ACC_GRP31]]
12999 // CHECK23-NEXT:    [[CONV6:%.*]] = fptosi double [[INC]] to i16
13000 // CHECK23-NEXT:    [[TMP15:%.*]] = mul nsw i32 1, [[TMP2]]
13001 // CHECK23-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i32 [[TMP15]]
13002 // CHECK23-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1
13003 // CHECK23-NEXT:    store i16 [[CONV6]], ptr [[ARRAYIDX7]], align 2, !llvm.access.group [[ACC_GRP31]]
13004 // CHECK23-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
13005 // CHECK23:       omp.body.continue:
13006 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
13007 // CHECK23:       omp.inner.for.inc:
13008 // CHECK23-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31]]
13009 // CHECK23-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP16]], 1
13010 // CHECK23-NEXT:    store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP31]]
13011 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP32:![0-9]+]]
13012 // CHECK23:       omp.inner.for.end:
13013 // CHECK23-NEXT:    br label [[OMP_IF_END:%.*]]
13014 // CHECK23:       omp_if.else:
13015 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND9:%.*]]
13016 // CHECK23:       omp.inner.for.cond9:
13017 // CHECK23-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
13018 // CHECK23-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
13019 // CHECK23-NEXT:    [[CMP10:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]]
13020 // CHECK23-NEXT:    br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END25:%.*]]
13021 // CHECK23:       omp.inner.for.body11:
13022 // CHECK23-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
13023 // CHECK23-NEXT:    [[MUL12:%.*]] = mul nsw i32 [[TMP19]], 1
13024 // CHECK23-NEXT:    [[ADD13:%.*]] = add nsw i32 0, [[MUL12]]
13025 // CHECK23-NEXT:    store i32 [[ADD13]], ptr [[I]], align 4
13026 // CHECK23-NEXT:    [[TMP20:%.*]] = load i32, ptr [[B_ADDR]], align 4
13027 // CHECK23-NEXT:    [[CONV14:%.*]] = sitofp i32 [[TMP20]] to double
13028 // CHECK23-NEXT:    [[ADD15:%.*]] = fadd double [[CONV14]], 1.500000e+00
13029 // CHECK23-NEXT:    [[A16:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0
13030 // CHECK23-NEXT:    store double [[ADD15]], ptr [[A16]], align 4
13031 // CHECK23-NEXT:    [[A17:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0
13032 // CHECK23-NEXT:    [[TMP21:%.*]] = load double, ptr [[A17]], align 4
13033 // CHECK23-NEXT:    [[INC18:%.*]] = fadd double [[TMP21]], 1.000000e+00
13034 // CHECK23-NEXT:    store double [[INC18]], ptr [[A17]], align 4
13035 // CHECK23-NEXT:    [[CONV19:%.*]] = fptosi double [[INC18]] to i16
13036 // CHECK23-NEXT:    [[TMP22:%.*]] = mul nsw i32 1, [[TMP2]]
13037 // CHECK23-NEXT:    [[ARRAYIDX20:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i32 [[TMP22]]
13038 // CHECK23-NEXT:    [[ARRAYIDX21:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX20]], i32 1
13039 // CHECK23-NEXT:    store i16 [[CONV19]], ptr [[ARRAYIDX21]], align 2
13040 // CHECK23-NEXT:    br label [[OMP_BODY_CONTINUE22:%.*]]
13041 // CHECK23:       omp.body.continue22:
13042 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_INC23:%.*]]
13043 // CHECK23:       omp.inner.for.inc23:
13044 // CHECK23-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
13045 // CHECK23-NEXT:    [[ADD24:%.*]] = add nsw i32 [[TMP23]], 1
13046 // CHECK23-NEXT:    store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4
13047 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP34:![0-9]+]]
13048 // CHECK23:       omp.inner.for.end25:
13049 // CHECK23-NEXT:    br label [[OMP_IF_END]]
13050 // CHECK23:       omp_if.end:
13051 // CHECK23-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
13052 // CHECK23:       omp.loop.exit:
13053 // CHECK23-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])
13054 // CHECK23-NEXT:    [[TMP24:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
13055 // CHECK23-NEXT:    [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
13056 // CHECK23-NEXT:    br i1 [[TMP25]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
13057 // CHECK23:       .omp.final.then:
13058 // CHECK23-NEXT:    store i32 10, ptr [[I]], align 4
13059 // CHECK23-NEXT:    br label [[DOTOMP_FINAL_DONE]]
13060 // CHECK23:       .omp.final.done:
13061 // CHECK23-NEXT:    ret void
13062 //
13063 //
13064 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180
13065 // CHECK23-SAME: (ptr noalias noundef [[DYN_PTR:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
13066 // CHECK23-NEXT:  entry:
13067 // CHECK23-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
13068 // CHECK23-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
13069 // CHECK23-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
13070 // CHECK23-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
13071 // CHECK23-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
13072 // CHECK23-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
13073 // CHECK23-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
13074 // CHECK23-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
13075 // CHECK23-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
13076 // CHECK23-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
13077 // CHECK23-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
13078 // CHECK23-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
13079 // CHECK23-NEXT:    store i32 [[TMP1]], ptr [[A_CASTED]], align 4
13080 // CHECK23-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4
13081 // CHECK23-NEXT:    [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
13082 // CHECK23-NEXT:    store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
13083 // CHECK23-NEXT:    [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4
13084 // CHECK23-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.omp_outlined, i32 [[TMP2]], i32 [[TMP4]], ptr [[TMP0]])
13085 // CHECK23-NEXT:    ret void
13086 //
13087 //
13088 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l180.omp_outlined
13089 // CHECK23-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
13090 // CHECK23-NEXT:  entry:
13091 // CHECK23-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
13092 // CHECK23-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
13093 // CHECK23-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
13094 // CHECK23-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
13095 // CHECK23-NEXT:    [[B_ADDR:%.*]] = alloca ptr, align 4
13096 // CHECK23-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
13097 // CHECK23-NEXT:    [[TMP:%.*]] = alloca i32, align 4
13098 // CHECK23-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
13099 // CHECK23-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
13100 // CHECK23-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
13101 // CHECK23-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
13102 // CHECK23-NEXT:    [[I:%.*]] = alloca i32, align 4
13103 // CHECK23-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
13104 // CHECK23-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
13105 // CHECK23-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
13106 // CHECK23-NEXT:    store i32 [[AA]], ptr [[AA_ADDR]], align 4
13107 // CHECK23-NEXT:    store ptr [[B]], ptr [[B_ADDR]], align 4
13108 // CHECK23-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
13109 // CHECK23-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
13110 // CHECK23-NEXT:    store i32 9, ptr [[DOTOMP_UB]], align 4
13111 // CHECK23-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
13112 // CHECK23-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
13113 // CHECK23-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
13114 // CHECK23-NEXT:    [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
13115 // CHECK23-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
13116 // CHECK23-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
13117 // CHECK23-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
13118 // CHECK23-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
13119 // CHECK23:       cond.true:
13120 // CHECK23-NEXT:    br label [[COND_END:%.*]]
13121 // CHECK23:       cond.false:
13122 // CHECK23-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
13123 // CHECK23-NEXT:    br label [[COND_END]]
13124 // CHECK23:       cond.end:
13125 // CHECK23-NEXT:    [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
13126 // CHECK23-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
13127 // CHECK23-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
13128 // CHECK23-NEXT:    store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
13129 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
13130 // CHECK23:       omp.inner.for.cond:
13131 // CHECK23-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36:![0-9]+]]
13132 // CHECK23-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP36]]
13133 // CHECK23-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
13134 // CHECK23-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
13135 // CHECK23:       omp.inner.for.body:
13136 // CHECK23-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]]
13137 // CHECK23-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
13138 // CHECK23-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
13139 // CHECK23-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP36]]
13140 // CHECK23-NEXT:    [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP36]]
13141 // CHECK23-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
13142 // CHECK23-NEXT:    store i32 [[ADD2]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP36]]
13143 // CHECK23-NEXT:    [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP36]]
13144 // CHECK23-NEXT:    [[CONV:%.*]] = sext i16 [[TMP10]] to i32
13145 // CHECK23-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV]], 1
13146 // CHECK23-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
13147 // CHECK23-NEXT:    store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP36]]
13148 // CHECK23-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2
13149 // CHECK23-NEXT:    [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP36]]
13150 // CHECK23-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1
13151 // CHECK23-NEXT:    store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP36]]
13152 // CHECK23-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
13153 // CHECK23:       omp.body.continue:
13154 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
13155 // CHECK23:       omp.inner.for.inc:
13156 // CHECK23-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]]
13157 // CHECK23-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP12]], 1
13158 // CHECK23-NEXT:    store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]]
13159 // CHECK23-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]]
13160 // CHECK23:       omp.inner.for.end:
13161 // CHECK23-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
13162 // CHECK23:       omp.loop.exit:
13163 // CHECK23-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])
13164 // CHECK23-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
13165 // CHECK23-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
13166 // CHECK23-NEXT:    br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
13167 // CHECK23:       .omp.final.then:
13168 // CHECK23-NEXT:    store i32 10, ptr [[I]], align 4
13169 // CHECK23-NEXT:    br label [[DOTOMP_FINAL_DONE]]
13170 // CHECK23:       .omp.final.done:
13171 // CHECK23-NEXT:    ret void
13172 //