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Run DCE after a LoopFlatten test to reduce spurious output [nfc]
[llvm-project.git] / clang / test / OpenMP / target_teams_distribute_simd_collapse_codegen.cpp
blob3a303fe951cf45c268dc1907d4a3e9ff1c8fdfa6
1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
2 // expected-no-diagnostics
3 #ifndef HEADER
4 #define HEADER
5
6 // Test host codegen.
7 // RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1
8 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
9 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1
10 // RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3
11 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
12 // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3
13
14 // RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5
15 // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
16 // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK5
17 // RUN: %clang_cc1 -DCK1 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7
18 // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
19 // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK7
20 #ifdef CK1
21
22 template <typename T, int X, long long Y>
23 struct SS{
24 T a[X][Y];
25
26 int foo(void) {
27
28 #pragma omp target teams distribute simd collapse(2)
29 for(int i = 0; i < X; i++) {
30 for(int j = 0; j < Y; j++) {
31 a[i][j] = (T)0;
32 }
33 }
34
35 // discard loop variables not needed here
36
37 return a[0][0];
38 }
39 };
40
41 int teams_template_struct(void) {
42 SS<int, 123, 456> V;
43 return V.foo();
44
45 }
46 #endif // CK1
47
48 // Test host codegen.
49 // RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9
50 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
51 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9
52 // RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11
53 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
54 // RUN: %clang_cc1 -DCK2 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11
55
56 // RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13
57 // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
58 // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK13
59 // RUN: %clang_cc1 -DCK2 -verify -Wno-vla -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15
60 // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
61 // RUN: %clang_cc1 -DCK2 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify -Wno-vla %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK15
62 #ifdef CK2
63
64 template <typename T, int n, int m>
65 int tmain(T argc) {
66 T a[n][m];
67 #pragma omp target teams distribute simd collapse(2)
68 for(int i = 0; i < n; i++) {
69 for(int j = 0; j < m; j++) {
70 a[i][j] = (T)0;
71 }
72 }
73 return 0;
74 }
75
76 int main (int argc, char **argv) {
77 int n = 100;
78 int m = 2;
79 int a[n][m];
80 #pragma omp target teams distribute simd collapse(2)
81 for(int i = 0; i < n; i++) {
82 for(int j = 0; j < m; j++) {
83 a[i][j] = 0;
84 }
85 }
86 return tmain<int, 10, 2>(argc);
87 }
88
89
90
91
92
93 // discard loop variables not needed here
94
95 #endif // CK2
96 #endif // #ifndef HEADER
97 // CHECK1-LABEL: define {{[^@]+}}@_Z21teams_template_structv
98 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
99 // CHECK1-NEXT: entry:
100 // CHECK1-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
101 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(224352) [[V]])
102 // CHECK1-NEXT: ret i32 [[CALL]]
103 //
104 //
105 // CHECK1-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
106 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat {
107 // CHECK1-NEXT: entry:
108 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
109 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8
110 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8
111 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8
112 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
113 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca i32, align 4
114 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
115 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
116 // CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
117 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 0
118 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
119 // CHECK1-NEXT: store ptr [[THIS1]], ptr [[TMP0]], align 8
120 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
121 // CHECK1-NEXT: store ptr [[A]], ptr [[TMP1]], align 8
122 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
123 // CHECK1-NEXT: store ptr null, ptr [[TMP2]], align 8
124 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
125 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
126 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
127 // CHECK1-NEXT: store i32 2, ptr [[TMP5]], align 4
128 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
129 // CHECK1-NEXT: store i32 1, ptr [[TMP6]], align 4
130 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
131 // CHECK1-NEXT: store ptr [[TMP3]], ptr [[TMP7]], align 8
132 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
133 // CHECK1-NEXT: store ptr [[TMP4]], ptr [[TMP8]], align 8
134 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
135 // CHECK1-NEXT: store ptr @.offload_sizes, ptr [[TMP9]], align 8
136 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
137 // CHECK1-NEXT: store ptr @.offload_maptypes, ptr [[TMP10]], align 8
138 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
139 // CHECK1-NEXT: store ptr null, ptr [[TMP11]], align 8
140 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
141 // CHECK1-NEXT: store ptr null, ptr [[TMP12]], align 8
142 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
143 // CHECK1-NEXT: store i64 56088, ptr [[TMP13]], align 8
144 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
145 // CHECK1-NEXT: store i64 0, ptr [[TMP14]], align 8
146 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
147 // CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP15]], align 4
148 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
149 // CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP16]], align 4
150 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
151 // CHECK1-NEXT: store i32 0, ptr [[TMP17]], align 4
152 // CHECK1-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.region_id, ptr [[KERNEL_ARGS]])
153 // CHECK1-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
154 // CHECK1-NEXT: br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
155 // CHECK1: omp_offload.failed:
156 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28(ptr [[THIS1]]) #[[ATTR2:[0-9]+]]
157 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
158 // CHECK1: omp_offload.cont:
159 // CHECK1-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0
160 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A3]], i64 0, i64 0
161 // CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i64 0, i64 0
162 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[ARRAYIDX4]], align 4
163 // CHECK1-NEXT: ret i32 [[TMP20]]
164 //
165 //
166 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28
167 // CHECK1-SAME: (ptr noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] {
168 // CHECK1-NEXT: entry:
169 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
170 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
171 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
172 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.omp_outlined, ptr [[TMP0]])
173 // CHECK1-NEXT: ret void
174 //
175 //
176 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.omp_outlined
177 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]]) #[[ATTR1]] {
178 // CHECK1-NEXT: entry:
179 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
180 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
181 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
182 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
183 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
184 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
185 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
186 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
187 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
188 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
189 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
190 // CHECK1-NEXT: [[J:%.*]] = alloca i32, align 4
191 // CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
192 // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
193 // CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
194 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
195 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
196 // CHECK1-NEXT: store i32 56087, ptr [[DOTOMP_UB]], align 4
197 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
198 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
199 // CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
200 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
201 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
202 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
203 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 56087
204 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
205 // CHECK1: cond.true:
206 // CHECK1-NEXT: br label [[COND_END:%.*]]
207 // CHECK1: cond.false:
208 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
209 // CHECK1-NEXT: br label [[COND_END]]
210 // CHECK1: cond.end:
211 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
212 // CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
213 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
214 // CHECK1-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
215 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
216 // CHECK1: omp.inner.for.cond:
217 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4:![0-9]+]]
218 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP4]]
219 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
220 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
221 // CHECK1: omp.inner.for.body:
222 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]]
223 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 456
224 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
225 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
226 // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP4]]
227 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]]
228 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]]
229 // CHECK1-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 456
230 // CHECK1-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456
231 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]]
232 // CHECK1-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1
233 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]
234 // CHECK1-NEXT: store i32 [[ADD6]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP4]]
235 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0
236 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP4]]
237 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64
238 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A]], i64 0, i64 [[IDXPROM]]
239 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP4]]
240 // CHECK1-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i64
241 // CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]]
242 // CHECK1-NEXT: store i32 0, ptr [[ARRAYIDX8]], align 4, !llvm.access.group [[ACC_GRP4]]
243 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
244 // CHECK1: omp.body.continue:
245 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
246 // CHECK1: omp.inner.for.inc:
247 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]]
248 // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1
249 // CHECK1-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]]
250 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
251 // CHECK1: omp.inner.for.end:
252 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
253 // CHECK1: omp.loop.exit:
254 // CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])
255 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
256 // CHECK1-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
257 // CHECK1-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
258 // CHECK1: .omp.final.then:
259 // CHECK1-NEXT: store i32 123, ptr [[I]], align 4
260 // CHECK1-NEXT: store i32 456, ptr [[J]], align 4
261 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
262 // CHECK1: .omp.final.done:
263 // CHECK1-NEXT: ret void
264 //
265 //
266 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
267 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] {
268 // CHECK1-NEXT: entry:
269 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1)
270 // CHECK1-NEXT: ret void
271 //
272 //
273 // CHECK3-LABEL: define {{[^@]+}}@_Z21teams_template_structv
274 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] {
275 // CHECK3-NEXT: entry:
276 // CHECK3-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
277 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(224352) [[V]])
278 // CHECK3-NEXT: ret i32 [[CALL]]
279 //
280 //
281 // CHECK3-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
282 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 {
283 // CHECK3-NEXT: entry:
284 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
285 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 4
286 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 4
287 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 4
288 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
289 // CHECK3-NEXT: [[_TMP2:%.*]] = alloca i32, align 4
290 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
291 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
292 // CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
293 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 0
294 // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
295 // CHECK3-NEXT: store ptr [[THIS1]], ptr [[TMP0]], align 4
296 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
297 // CHECK3-NEXT: store ptr [[A]], ptr [[TMP1]], align 4
298 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
299 // CHECK3-NEXT: store ptr null, ptr [[TMP2]], align 4
300 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
301 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
302 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
303 // CHECK3-NEXT: store i32 2, ptr [[TMP5]], align 4
304 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
305 // CHECK3-NEXT: store i32 1, ptr [[TMP6]], align 4
306 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
307 // CHECK3-NEXT: store ptr [[TMP3]], ptr [[TMP7]], align 4
308 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
309 // CHECK3-NEXT: store ptr [[TMP4]], ptr [[TMP8]], align 4
310 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
311 // CHECK3-NEXT: store ptr @.offload_sizes, ptr [[TMP9]], align 4
312 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
313 // CHECK3-NEXT: store ptr @.offload_maptypes, ptr [[TMP10]], align 4
314 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
315 // CHECK3-NEXT: store ptr null, ptr [[TMP11]], align 4
316 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
317 // CHECK3-NEXT: store ptr null, ptr [[TMP12]], align 4
318 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
319 // CHECK3-NEXT: store i64 56088, ptr [[TMP13]], align 8
320 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
321 // CHECK3-NEXT: store i64 0, ptr [[TMP14]], align 8
322 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
323 // CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP15]], align 4
324 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
325 // CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP16]], align 4
326 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
327 // CHECK3-NEXT: store i32 0, ptr [[TMP17]], align 4
328 // CHECK3-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.region_id, ptr [[KERNEL_ARGS]])
329 // CHECK3-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
330 // CHECK3-NEXT: br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
331 // CHECK3: omp_offload.failed:
332 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28(ptr [[THIS1]]) #[[ATTR2:[0-9]+]]
333 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
334 // CHECK3: omp_offload.cont:
335 // CHECK3-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0
336 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A3]], i32 0, i32 0
337 // CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i32 0, i32 0
338 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[ARRAYIDX4]], align 4
339 // CHECK3-NEXT: ret i32 [[TMP20]]
340 //
341 //
342 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28
343 // CHECK3-SAME: (ptr noundef [[THIS:%.*]]) #[[ATTR1:[0-9]+]] {
344 // CHECK3-NEXT: entry:
345 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
346 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
347 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
348 // CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.omp_outlined, ptr [[TMP0]])
349 // CHECK3-NEXT: ret void
350 //
351 //
352 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2SSIiLi123ELx456EE3fooEv_l28.omp_outlined
353 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]]) #[[ATTR1]] {
354 // CHECK3-NEXT: entry:
355 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
356 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
357 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
358 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
359 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
360 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
361 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
362 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
363 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
364 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
365 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
366 // CHECK3-NEXT: [[J:%.*]] = alloca i32, align 4
367 // CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
368 // CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
369 // CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
370 // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
371 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
372 // CHECK3-NEXT: store i32 56087, ptr [[DOTOMP_UB]], align 4
373 // CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
374 // CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
375 // CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
376 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
377 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
378 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
379 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 56087
380 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
381 // CHECK3: cond.true:
382 // CHECK3-NEXT: br label [[COND_END:%.*]]
383 // CHECK3: cond.false:
384 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
385 // CHECK3-NEXT: br label [[COND_END]]
386 // CHECK3: cond.end:
387 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 56087, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
388 // CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
389 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
390 // CHECK3-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
391 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
392 // CHECK3: omp.inner.for.cond:
393 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5:![0-9]+]]
394 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP5]]
395 // CHECK3-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
396 // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
397 // CHECK3: omp.inner.for.body:
398 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]]
399 // CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 456
400 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
401 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
402 // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]]
403 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]]
404 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]]
405 // CHECK3-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 456
406 // CHECK3-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456
407 // CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]]
408 // CHECK3-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1
409 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]
410 // CHECK3-NEXT: store i32 [[ADD6]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP5]]
411 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0
412 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]]
413 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A]], i32 0, i32 [[TMP11]]
414 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP5]]
415 // CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i32 0, i32 [[TMP12]]
416 // CHECK3-NEXT: store i32 0, ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP5]]
417 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
418 // CHECK3: omp.body.continue:
419 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
420 // CHECK3: omp.inner.for.inc:
421 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]]
422 // CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP13]], 1
423 // CHECK3-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]]
424 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
425 // CHECK3: omp.inner.for.end:
426 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
427 // CHECK3: omp.loop.exit:
428 // CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])
429 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
430 // CHECK3-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
431 // CHECK3-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
432 // CHECK3: .omp.final.then:
433 // CHECK3-NEXT: store i32 123, ptr [[I]], align 4
434 // CHECK3-NEXT: store i32 456, ptr [[J]], align 4
435 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]]
436 // CHECK3: .omp.final.done:
437 // CHECK3-NEXT: ret void
438 //
439 //
440 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
441 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] {
442 // CHECK3-NEXT: entry:
443 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1)
444 // CHECK3-NEXT: ret void
445 //
446 //
447 // CHECK5-LABEL: define {{[^@]+}}@_Z21teams_template_structv
448 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] {
449 // CHECK5-NEXT: entry:
450 // CHECK5-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
451 // CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(224352) [[V]])
452 // CHECK5-NEXT: ret i32 [[CALL]]
453 //
454 //
455 // CHECK5-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
456 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat {
457 // CHECK5-NEXT: entry:
458 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
459 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4
460 // CHECK5-NEXT: [[_TMP2:%.*]] = alloca i32, align 4
461 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
462 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
463 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
464 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4
465 // CHECK5-NEXT: [[J:%.*]] = alloca i32, align 4
466 // CHECK5-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
467 // CHECK5-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
468 // CHECK5-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
469 // CHECK5-NEXT: store i32 56087, ptr [[DOTOMP_UB]], align 4
470 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
471 // CHECK5-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4
472 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
473 // CHECK5: omp.inner.for.cond:
474 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]]
475 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP2]]
476 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
477 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
478 // CHECK5: omp.inner.for.body:
479 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
480 // CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP3]], 456
481 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
482 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
483 // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]
484 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
485 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
486 // CHECK5-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP5]], 456
487 // CHECK5-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456
488 // CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], [[MUL4]]
489 // CHECK5-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1
490 // CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]
491 // CHECK5-NEXT: store i32 [[ADD6]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP2]]
492 // CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 0
493 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]
494 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64
495 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A]], i64 0, i64 [[IDXPROM]]
496 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP2]]
497 // CHECK5-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP7]] to i64
498 // CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]]
499 // CHECK5-NEXT: store i32 0, ptr [[ARRAYIDX8]], align 4, !llvm.access.group [[ACC_GRP2]]
500 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
501 // CHECK5: omp.body.continue:
502 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
503 // CHECK5: omp.inner.for.inc:
504 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
505 // CHECK5-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP8]], 1
506 // CHECK5-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
507 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
508 // CHECK5: omp.inner.for.end:
509 // CHECK5-NEXT: store i32 123, ptr [[I]], align 4
510 // CHECK5-NEXT: store i32 456, ptr [[J]], align 4
511 // CHECK5-NEXT: [[A10:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0
512 // CHECK5-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A10]], i64 0, i64 0
513 // CHECK5-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX11]], i64 0, i64 0
514 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[ARRAYIDX12]], align 4
515 // CHECK5-NEXT: ret i32 [[TMP9]]
516 //
517 //
518 // CHECK7-LABEL: define {{[^@]+}}@_Z21teams_template_structv
519 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] {
520 // CHECK7-NEXT: entry:
521 // CHECK7-NEXT: [[V:%.*]] = alloca [[STRUCT_SS:%.*]], align 4
522 // CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_ZN2SSIiLi123ELx456EE3fooEv(ptr noundef nonnull align 4 dereferenceable(224352) [[V]])
523 // CHECK7-NEXT: ret i32 [[CALL]]
524 //
525 //
526 // CHECK7-LABEL: define {{[^@]+}}@_ZN2SSIiLi123ELx456EE3fooEv
527 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(224352) [[THIS:%.*]]) #[[ATTR0]] comdat align 2 {
528 // CHECK7-NEXT: entry:
529 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
530 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4
531 // CHECK7-NEXT: [[_TMP2:%.*]] = alloca i32, align 4
532 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
533 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
534 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
535 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4
536 // CHECK7-NEXT: [[J:%.*]] = alloca i32, align 4
537 // CHECK7-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
538 // CHECK7-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
539 // CHECK7-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
540 // CHECK7-NEXT: store i32 56087, ptr [[DOTOMP_UB]], align 4
541 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
542 // CHECK7-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4
543 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
544 // CHECK7: omp.inner.for.cond:
545 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3:![0-9]+]]
546 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP3]]
547 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
548 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
549 // CHECK7: omp.inner.for.body:
550 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]
551 // CHECK7-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP3]], 456
552 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
553 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
554 // CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]]
555 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]
556 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]
557 // CHECK7-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP5]], 456
558 // CHECK7-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 456
559 // CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], [[MUL4]]
560 // CHECK7-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1
561 // CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]
562 // CHECK7-NEXT: store i32 [[ADD6]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP3]]
563 // CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 0
564 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]]
565 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A]], i32 0, i32 [[TMP6]]
566 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP3]]
567 // CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i32 0, i32 [[TMP7]]
568 // CHECK7-NEXT: store i32 0, ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP3]]
569 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
570 // CHECK7: omp.body.continue:
571 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
572 // CHECK7: omp.inner.for.inc:
573 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]
574 // CHECK7-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP8]], 1
575 // CHECK7-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]
576 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
577 // CHECK7: omp.inner.for.end:
578 // CHECK7-NEXT: store i32 123, ptr [[I]], align 4
579 // CHECK7-NEXT: store i32 456, ptr [[J]], align 4
580 // CHECK7-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0
581 // CHECK7-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A9]], i32 0, i32 0
582 // CHECK7-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX10]], i32 0, i32 0
583 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[ARRAYIDX11]], align 4
584 // CHECK7-NEXT: ret i32 [[TMP9]]
585 //
586 //
587 // CHECK9-LABEL: define {{[^@]+}}@main
588 // CHECK9-SAME: (i32 noundef signext [[ARGC:%.*]], ptr noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] {
589 // CHECK9-NEXT: entry:
590 // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
591 // CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
592 // CHECK9-NEXT: [[ARGV_ADDR:%.*]] = alloca ptr, align 8
593 // CHECK9-NEXT: [[N:%.*]] = alloca i32, align 4
594 // CHECK9-NEXT: [[M:%.*]] = alloca i32, align 4
595 // CHECK9-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8
596 // CHECK9-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
597 // CHECK9-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8
598 // CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
599 // CHECK9-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8
600 // CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 8
601 // CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 8
602 // CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 8
603 // CHECK9-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8
604 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
605 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
606 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
607 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
608 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8
609 // CHECK9-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
610 // CHECK9-NEXT: store i32 0, ptr [[RETVAL]], align 4
611 // CHECK9-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
612 // CHECK9-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
613 // CHECK9-NEXT: store i32 100, ptr [[N]], align 4
614 // CHECK9-NEXT: store i32 2, ptr [[M]], align 4
615 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
616 // CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
617 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[M]], align 4
618 // CHECK9-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
619 // CHECK9-NEXT: [[TMP4:%.*]] = call ptr @llvm.stacksave.p0()
620 // CHECK9-NEXT: store ptr [[TMP4]], ptr [[SAVED_STACK]], align 8
621 // CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]]
622 // CHECK9-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4
623 // CHECK9-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
624 // CHECK9-NEXT: store i64 [[TMP3]], ptr [[__VLA_EXPR1]], align 8
625 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[N]], align 4
626 // CHECK9-NEXT: store i32 [[TMP6]], ptr [[N_CASTED]], align 4
627 // CHECK9-NEXT: [[TMP7:%.*]] = load i64, ptr [[N_CASTED]], align 8
628 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[M]], align 4
629 // CHECK9-NEXT: store i32 [[TMP8]], ptr [[M_CASTED]], align 4
630 // CHECK9-NEXT: [[TMP9:%.*]] = load i64, ptr [[M_CASTED]], align 8
631 // CHECK9-NEXT: [[TMP10:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]]
632 // CHECK9-NEXT: [[TMP11:%.*]] = mul nuw i64 [[TMP10]], 4
633 // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes, i64 40, i1 false)
634 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
635 // CHECK9-NEXT: store i64 [[TMP7]], ptr [[TMP12]], align 8
636 // CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
637 // CHECK9-NEXT: store i64 [[TMP7]], ptr [[TMP13]], align 8
638 // CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
639 // CHECK9-NEXT: store ptr null, ptr [[TMP14]], align 8
640 // CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
641 // CHECK9-NEXT: store i64 [[TMP9]], ptr [[TMP15]], align 8
642 // CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
643 // CHECK9-NEXT: store i64 [[TMP9]], ptr [[TMP16]], align 8
644 // CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
645 // CHECK9-NEXT: store ptr null, ptr [[TMP17]], align 8
646 // CHECK9-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
647 // CHECK9-NEXT: store i64 [[TMP1]], ptr [[TMP18]], align 8
648 // CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
649 // CHECK9-NEXT: store i64 [[TMP1]], ptr [[TMP19]], align 8
650 // CHECK9-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
651 // CHECK9-NEXT: store ptr null, ptr [[TMP20]], align 8
652 // CHECK9-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
653 // CHECK9-NEXT: store i64 [[TMP3]], ptr [[TMP21]], align 8
654 // CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
655 // CHECK9-NEXT: store i64 [[TMP3]], ptr [[TMP22]], align 8
656 // CHECK9-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
657 // CHECK9-NEXT: store ptr null, ptr [[TMP23]], align 8
658 // CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
659 // CHECK9-NEXT: store ptr [[VLA]], ptr [[TMP24]], align 8
660 // CHECK9-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4
661 // CHECK9-NEXT: store ptr [[VLA]], ptr [[TMP25]], align 8
662 // CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 4
663 // CHECK9-NEXT: store i64 [[TMP11]], ptr [[TMP26]], align 8
664 // CHECK9-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
665 // CHECK9-NEXT: store ptr null, ptr [[TMP27]], align 8
666 // CHECK9-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
667 // CHECK9-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
668 // CHECK9-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0
669 // CHECK9-NEXT: [[TMP31:%.*]] = load i32, ptr [[N]], align 4
670 // CHECK9-NEXT: store i32 [[TMP31]], ptr [[DOTCAPTURE_EXPR_]], align 4
671 // CHECK9-NEXT: [[TMP32:%.*]] = load i32, ptr [[M]], align 4
672 // CHECK9-NEXT: store i32 [[TMP32]], ptr [[DOTCAPTURE_EXPR_2]], align 4
673 // CHECK9-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
674 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP33]], 0
675 // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
676 // CHECK9-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64
677 // CHECK9-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
678 // CHECK9-NEXT: [[SUB4:%.*]] = sub nsw i32 [[TMP34]], 0
679 // CHECK9-NEXT: [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1
680 // CHECK9-NEXT: [[CONV6:%.*]] = sext i32 [[DIV5]] to i64
681 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]]
682 // CHECK9-NEXT: [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1
683 // CHECK9-NEXT: store i64 [[SUB7]], ptr [[DOTCAPTURE_EXPR_3]], align 8
684 // CHECK9-NEXT: [[TMP35:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_3]], align 8
685 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP35]], 1
686 // CHECK9-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
687 // CHECK9-NEXT: store i32 2, ptr [[TMP36]], align 4
688 // CHECK9-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
689 // CHECK9-NEXT: store i32 5, ptr [[TMP37]], align 4
690 // CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
691 // CHECK9-NEXT: store ptr [[TMP28]], ptr [[TMP38]], align 8
692 // CHECK9-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
693 // CHECK9-NEXT: store ptr [[TMP29]], ptr [[TMP39]], align 8
694 // CHECK9-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
695 // CHECK9-NEXT: store ptr [[TMP30]], ptr [[TMP40]], align 8
696 // CHECK9-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
697 // CHECK9-NEXT: store ptr @.offload_maptypes, ptr [[TMP41]], align 8
698 // CHECK9-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
699 // CHECK9-NEXT: store ptr null, ptr [[TMP42]], align 8
700 // CHECK9-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
701 // CHECK9-NEXT: store ptr null, ptr [[TMP43]], align 8
702 // CHECK9-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
703 // CHECK9-NEXT: store i64 [[ADD]], ptr [[TMP44]], align 8
704 // CHECK9-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
705 // CHECK9-NEXT: store i64 0, ptr [[TMP45]], align 8
706 // CHECK9-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
707 // CHECK9-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP46]], align 4
708 // CHECK9-NEXT: [[TMP47:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
709 // CHECK9-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP47]], align 4
710 // CHECK9-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
711 // CHECK9-NEXT: store i32 0, ptr [[TMP48]], align 4
712 // CHECK9-NEXT: [[TMP49:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80.region_id, ptr [[KERNEL_ARGS]])
713 // CHECK9-NEXT: [[TMP50:%.*]] = icmp ne i32 [[TMP49]], 0
714 // CHECK9-NEXT: br i1 [[TMP50]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
715 // CHECK9: omp_offload.failed:
716 // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80(i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP1]], i64 [[TMP3]], ptr [[VLA]]) #[[ATTR3:[0-9]+]]
717 // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]]
718 // CHECK9: omp_offload.cont:
719 // CHECK9-NEXT: [[TMP51:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
720 // CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP51]])
721 // CHECK9-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
722 // CHECK9-NEXT: [[TMP52:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
723 // CHECK9-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP52]])
724 // CHECK9-NEXT: [[TMP53:%.*]] = load i32, ptr [[RETVAL]], align 4
725 // CHECK9-NEXT: ret i32 [[TMP53]]
726 //
727 //
728 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80
729 // CHECK9-SAME: (i64 noundef [[N:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
730 // CHECK9-NEXT: entry:
731 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
732 // CHECK9-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8
733 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
734 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
735 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
736 // CHECK9-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8
737 // CHECK9-NEXT: [[M_CASTED:%.*]] = alloca i64, align 8
738 // CHECK9-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
739 // CHECK9-NEXT: store i64 [[M]], ptr [[M_ADDR]], align 8
740 // CHECK9-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
741 // CHECK9-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
742 // CHECK9-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
743 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
744 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
745 // CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A_ADDR]], align 8
746 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4
747 // CHECK9-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 4
748 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8
749 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[M_ADDR]], align 4
750 // CHECK9-NEXT: store i32 [[TMP5]], ptr [[M_CASTED]], align 4
751 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, ptr [[M_CASTED]], align 8
752 // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80.omp_outlined, i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP0]], i64 [[TMP1]], ptr [[TMP2]])
753 // CHECK9-NEXT: ret void
754 //
755 //
756 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80.omp_outlined
757 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] {
758 // CHECK9-NEXT: entry:
759 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
760 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
761 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
762 // CHECK9-NEXT: [[M_ADDR:%.*]] = alloca i64, align 8
763 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
764 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
765 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
766 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
767 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
768 // CHECK9-NEXT: [[_TMP3:%.*]] = alloca i32, align 4
769 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
770 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4
771 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8
772 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4
773 // CHECK9-NEXT: [[J:%.*]] = alloca i32, align 4
774 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
775 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
776 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
777 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
778 // CHECK9-NEXT: [[I11:%.*]] = alloca i32, align 4
779 // CHECK9-NEXT: [[J12:%.*]] = alloca i32, align 4
780 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
781 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
782 // CHECK9-NEXT: store i64 [[N]], ptr [[N_ADDR]], align 8
783 // CHECK9-NEXT: store i64 [[M]], ptr [[M_ADDR]], align 8
784 // CHECK9-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
785 // CHECK9-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
786 // CHECK9-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
787 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
788 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
789 // CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A_ADDR]], align 8
790 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4
791 // CHECK9-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4
792 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[M_ADDR]], align 4
793 // CHECK9-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_4]], align 4
794 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
795 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0
796 // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
797 // CHECK9-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64
798 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4
799 // CHECK9-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP6]], 0
800 // CHECK9-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1
801 // CHECK9-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64
802 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]]
803 // CHECK9-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1
804 // CHECK9-NEXT: store i64 [[SUB9]], ptr [[DOTCAPTURE_EXPR_5]], align 8
805 // CHECK9-NEXT: store i32 0, ptr [[I]], align 4
806 // CHECK9-NEXT: store i32 0, ptr [[J]], align 4
807 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
808 // CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP7]]
809 // CHECK9-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]]
810 // CHECK9: land.lhs.true:
811 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4
812 // CHECK9-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP8]]
813 // CHECK9-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]]
814 // CHECK9: omp.precond.then:
815 // CHECK9-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
816 // CHECK9-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8
817 // CHECK9-NEXT: store i64 [[TMP9]], ptr [[DOTOMP_UB]], align 8
818 // CHECK9-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8
819 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
820 // CHECK9-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
821 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4
822 // CHECK9-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1:[0-9]+]], i32 [[TMP11]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
823 // CHECK9-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
824 // CHECK9-NEXT: [[TMP13:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8
825 // CHECK9-NEXT: [[CMP13:%.*]] = icmp sgt i64 [[TMP12]], [[TMP13]]
826 // CHECK9-NEXT: br i1 [[CMP13]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
827 // CHECK9: cond.true:
828 // CHECK9-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8
829 // CHECK9-NEXT: br label [[COND_END:%.*]]
830 // CHECK9: cond.false:
831 // CHECK9-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
832 // CHECK9-NEXT: br label [[COND_END]]
833 // CHECK9: cond.end:
834 // CHECK9-NEXT: [[COND:%.*]] = phi i64 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ]
835 // CHECK9-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8
836 // CHECK9-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
837 // CHECK9-NEXT: store i64 [[TMP16]], ptr [[DOTOMP_IV]], align 8
838 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
839 // CHECK9: omp.inner.for.cond:
840 // CHECK9-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP5:![0-9]+]]
841 // CHECK9-NEXT: [[TMP18:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP5]]
842 // CHECK9-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]]
843 // CHECK9-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
844 // CHECK9: omp.inner.for.body:
845 // CHECK9-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP5]]
846 // CHECK9-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group [[ACC_GRP5]]
847 // CHECK9-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP20]], 0
848 // CHECK9-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1
849 // CHECK9-NEXT: [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]]
850 // CHECK9-NEXT: [[CONV18:%.*]] = sext i32 [[MUL17]] to i64
851 // CHECK9-NEXT: [[DIV19:%.*]] = sdiv i64 [[TMP19]], [[CONV18]]
852 // CHECK9-NEXT: [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1
853 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL20]]
854 // CHECK9-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD]] to i32
855 // CHECK9-NEXT: store i32 [[CONV21]], ptr [[I11]], align 4, !llvm.access.group [[ACC_GRP5]]
856 // CHECK9-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP5]]
857 // CHECK9-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP5]]
858 // CHECK9-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group [[ACC_GRP5]]
859 // CHECK9-NEXT: [[SUB22:%.*]] = sub nsw i32 [[TMP23]], 0
860 // CHECK9-NEXT: [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1
861 // CHECK9-NEXT: [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]]
862 // CHECK9-NEXT: [[CONV25:%.*]] = sext i32 [[MUL24]] to i64
863 // CHECK9-NEXT: [[DIV26:%.*]] = sdiv i64 [[TMP22]], [[CONV25]]
864 // CHECK9-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group [[ACC_GRP5]]
865 // CHECK9-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP24]], 0
866 // CHECK9-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1
867 // CHECK9-NEXT: [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]]
868 // CHECK9-NEXT: [[CONV30:%.*]] = sext i32 [[MUL29]] to i64
869 // CHECK9-NEXT: [[MUL31:%.*]] = mul nsw i64 [[DIV26]], [[CONV30]]
870 // CHECK9-NEXT: [[SUB32:%.*]] = sub nsw i64 [[TMP21]], [[MUL31]]
871 // CHECK9-NEXT: [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 1
872 // CHECK9-NEXT: [[ADD34:%.*]] = add nsw i64 0, [[MUL33]]
873 // CHECK9-NEXT: [[CONV35:%.*]] = trunc i64 [[ADD34]] to i32
874 // CHECK9-NEXT: store i32 [[CONV35]], ptr [[J12]], align 4, !llvm.access.group [[ACC_GRP5]]
875 // CHECK9-NEXT: [[TMP25:%.*]] = load i32, ptr [[I11]], align 4, !llvm.access.group [[ACC_GRP5]]
876 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP25]] to i64
877 // CHECK9-NEXT: [[TMP26:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP1]]
878 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP2]], i64 [[TMP26]]
879 // CHECK9-NEXT: [[TMP27:%.*]] = load i32, ptr [[J12]], align 4, !llvm.access.group [[ACC_GRP5]]
880 // CHECK9-NEXT: [[IDXPROM36:%.*]] = sext i32 [[TMP27]] to i64
881 // CHECK9-NEXT: [[ARRAYIDX37:%.*]] = getelementptr inbounds i32, ptr [[ARRAYIDX]], i64 [[IDXPROM36]]
882 // CHECK9-NEXT: store i32 0, ptr [[ARRAYIDX37]], align 4, !llvm.access.group [[ACC_GRP5]]
883 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
884 // CHECK9: omp.body.continue:
885 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
886 // CHECK9: omp.inner.for.inc:
887 // CHECK9-NEXT: [[TMP28:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP5]]
888 // CHECK9-NEXT: [[ADD38:%.*]] = add nsw i64 [[TMP28]], 1
889 // CHECK9-NEXT: store i64 [[ADD38]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP5]]
890 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
891 // CHECK9: omp.inner.for.end:
892 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
893 // CHECK9: omp.loop.exit:
894 // CHECK9-NEXT: [[TMP29:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
895 // CHECK9-NEXT: [[TMP30:%.*]] = load i32, ptr [[TMP29]], align 4
896 // CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP30]])
897 // CHECK9-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
898 // CHECK9-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0
899 // CHECK9-NEXT: br i1 [[TMP32]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
900 // CHECK9: .omp.final.then:
901 // CHECK9-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
902 // CHECK9-NEXT: [[SUB39:%.*]] = sub nsw i32 [[TMP33]], 0
903 // CHECK9-NEXT: [[DIV40:%.*]] = sdiv i32 [[SUB39]], 1
904 // CHECK9-NEXT: [[MUL41:%.*]] = mul nsw i32 [[DIV40]], 1
905 // CHECK9-NEXT: [[ADD42:%.*]] = add nsw i32 0, [[MUL41]]
906 // CHECK9-NEXT: store i32 [[ADD42]], ptr [[I11]], align 4
907 // CHECK9-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4
908 // CHECK9-NEXT: [[SUB43:%.*]] = sub nsw i32 [[TMP34]], 0
909 // CHECK9-NEXT: [[DIV44:%.*]] = sdiv i32 [[SUB43]], 1
910 // CHECK9-NEXT: [[MUL45:%.*]] = mul nsw i32 [[DIV44]], 1
911 // CHECK9-NEXT: [[ADD46:%.*]] = add nsw i32 0, [[MUL45]]
912 // CHECK9-NEXT: store i32 [[ADD46]], ptr [[J12]], align 4
913 // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]]
914 // CHECK9: .omp.final.done:
915 // CHECK9-NEXT: br label [[OMP_PRECOND_END]]
916 // CHECK9: omp.precond.end:
917 // CHECK9-NEXT: ret void
918 //
919 //
920 // CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_
921 // CHECK9-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR5:[0-9]+]] comdat {
922 // CHECK9-NEXT: entry:
923 // CHECK9-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
924 // CHECK9-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4
925 // CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 8
926 // CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 8
927 // CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 8
928 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
929 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
930 // CHECK9-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
931 // CHECK9-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
932 // CHECK9-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
933 // CHECK9-NEXT: store ptr [[A]], ptr [[TMP0]], align 8
934 // CHECK9-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
935 // CHECK9-NEXT: store ptr [[A]], ptr [[TMP1]], align 8
936 // CHECK9-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
937 // CHECK9-NEXT: store ptr null, ptr [[TMP2]], align 8
938 // CHECK9-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
939 // CHECK9-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
940 // CHECK9-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
941 // CHECK9-NEXT: store i32 2, ptr [[TMP5]], align 4
942 // CHECK9-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
943 // CHECK9-NEXT: store i32 1, ptr [[TMP6]], align 4
944 // CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
945 // CHECK9-NEXT: store ptr [[TMP3]], ptr [[TMP7]], align 8
946 // CHECK9-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
947 // CHECK9-NEXT: store ptr [[TMP4]], ptr [[TMP8]], align 8
948 // CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
949 // CHECK9-NEXT: store ptr @.offload_sizes.1, ptr [[TMP9]], align 8
950 // CHECK9-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
951 // CHECK9-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP10]], align 8
952 // CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
953 // CHECK9-NEXT: store ptr null, ptr [[TMP11]], align 8
954 // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
955 // CHECK9-NEXT: store ptr null, ptr [[TMP12]], align 8
956 // CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
957 // CHECK9-NEXT: store i64 20, ptr [[TMP13]], align 8
958 // CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
959 // CHECK9-NEXT: store i64 0, ptr [[TMP14]], align 8
960 // CHECK9-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
961 // CHECK9-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP15]], align 4
962 // CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
963 // CHECK9-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP16]], align 4
964 // CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
965 // CHECK9-NEXT: store i32 0, ptr [[TMP17]], align 4
966 // CHECK9-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67.region_id, ptr [[KERNEL_ARGS]])
967 // CHECK9-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
968 // CHECK9-NEXT: br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
969 // CHECK9: omp_offload.failed:
970 // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67(ptr [[A]]) #[[ATTR3]]
971 // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]]
972 // CHECK9: omp_offload.cont:
973 // CHECK9-NEXT: ret i32 0
974 //
975 //
976 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67
977 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] {
978 // CHECK9-NEXT: entry:
979 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
980 // CHECK9-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
981 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
982 // CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67.omp_outlined, ptr [[TMP0]])
983 // CHECK9-NEXT: ret void
984 //
985 //
986 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67.omp_outlined
987 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] {
988 // CHECK9-NEXT: entry:
989 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
990 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
991 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
992 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
993 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
994 // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
995 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
996 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
997 // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
998 // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
999 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4
1000 // CHECK9-NEXT: [[J:%.*]] = alloca i32, align 4
1001 // CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1002 // CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1003 // CHECK9-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 8
1004 // CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 8
1005 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
1006 // CHECK9-NEXT: store i32 19, ptr [[DOTOMP_UB]], align 4
1007 // CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1008 // CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1009 // CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1010 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
1011 // CHECK9-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
1012 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1013 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 19
1014 // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1015 // CHECK9: cond.true:
1016 // CHECK9-NEXT: br label [[COND_END:%.*]]
1017 // CHECK9: cond.false:
1018 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1019 // CHECK9-NEXT: br label [[COND_END]]
1020 // CHECK9: cond.end:
1021 // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
1022 // CHECK9-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
1023 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1024 // CHECK9-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
1025 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1026 // CHECK9: omp.inner.for.cond:
1027 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11:![0-9]+]]
1028 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP11]]
1029 // CHECK9-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
1030 // CHECK9-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1031 // CHECK9: omp.inner.for.body:
1032 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]
1033 // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 2
1034 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
1035 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1036 // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]]
1037 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]
1038 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]
1039 // CHECK9-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 2
1040 // CHECK9-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2
1041 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]]
1042 // CHECK9-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1
1043 // CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]
1044 // CHECK9-NEXT: store i32 [[ADD6]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP11]]
1045 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]]
1046 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64
1047 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], ptr [[TMP0]], i64 0, i64 [[IDXPROM]]
1048 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP11]]
1049 // CHECK9-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i64
1050 // CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]]
1051 // CHECK9-NEXT: store i32 0, ptr [[ARRAYIDX8]], align 4, !llvm.access.group [[ACC_GRP11]]
1052 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1053 // CHECK9: omp.body.continue:
1054 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1055 // CHECK9: omp.inner.for.inc:
1056 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]
1057 // CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP13]], 1
1058 // CHECK9-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]
1059 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
1060 // CHECK9: omp.inner.for.end:
1061 // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1062 // CHECK9: omp.loop.exit:
1063 // CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])
1064 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
1065 // CHECK9-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
1066 // CHECK9-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1067 // CHECK9: .omp.final.then:
1068 // CHECK9-NEXT: store i32 10, ptr [[I]], align 4
1069 // CHECK9-NEXT: store i32 2, ptr [[J]], align 4
1070 // CHECK9-NEXT: br label [[DOTOMP_FINAL_DONE]]
1071 // CHECK9: .omp.final.done:
1072 // CHECK9-NEXT: ret void
1073 //
1074 //
1075 // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
1076 // CHECK9-SAME: () #[[ATTR6:[0-9]+]] {
1077 // CHECK9-NEXT: entry:
1078 // CHECK9-NEXT: call void @__tgt_register_requires(i64 1)
1079 // CHECK9-NEXT: ret void
1080 //
1081 //
1082 // CHECK11-LABEL: define {{[^@]+}}@main
1083 // CHECK11-SAME: (i32 noundef [[ARGC:%.*]], ptr noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] {
1084 // CHECK11-NEXT: entry:
1085 // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1086 // CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
1087 // CHECK11-NEXT: [[ARGV_ADDR:%.*]] = alloca ptr, align 4
1088 // CHECK11-NEXT: [[N:%.*]] = alloca i32, align 4
1089 // CHECK11-NEXT: [[M:%.*]] = alloca i32, align 4
1090 // CHECK11-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4
1091 // CHECK11-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
1092 // CHECK11-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4
1093 // CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4
1094 // CHECK11-NEXT: [[M_CASTED:%.*]] = alloca i32, align 4
1095 // CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 4
1096 // CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 4
1097 // CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 4
1098 // CHECK11-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4
1099 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4
1100 // CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
1101 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
1102 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
1103 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8
1104 // CHECK11-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1105 // CHECK11-NEXT: store i32 0, ptr [[RETVAL]], align 4
1106 // CHECK11-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
1107 // CHECK11-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4
1108 // CHECK11-NEXT: store i32 100, ptr [[N]], align 4
1109 // CHECK11-NEXT: store i32 2, ptr [[M]], align 4
1110 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
1111 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[M]], align 4
1112 // CHECK11-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
1113 // CHECK11-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4
1114 // CHECK11-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]]
1115 // CHECK11-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4
1116 // CHECK11-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4
1117 // CHECK11-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR1]], align 4
1118 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[N]], align 4
1119 // CHECK11-NEXT: store i32 [[TMP4]], ptr [[N_CASTED]], align 4
1120 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[N_CASTED]], align 4
1121 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[M]], align 4
1122 // CHECK11-NEXT: store i32 [[TMP6]], ptr [[M_CASTED]], align 4
1123 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[M_CASTED]], align 4
1124 // CHECK11-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]]
1125 // CHECK11-NEXT: [[TMP9:%.*]] = mul nuw i32 [[TMP8]], 4
1126 // CHECK11-NEXT: [[TMP10:%.*]] = sext i32 [[TMP9]] to i64
1127 // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes, i32 40, i1 false)
1128 // CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1129 // CHECK11-NEXT: store i32 [[TMP5]], ptr [[TMP11]], align 4
1130 // CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1131 // CHECK11-NEXT: store i32 [[TMP5]], ptr [[TMP12]], align 4
1132 // CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
1133 // CHECK11-NEXT: store ptr null, ptr [[TMP13]], align 4
1134 // CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1135 // CHECK11-NEXT: store i32 [[TMP7]], ptr [[TMP14]], align 4
1136 // CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1137 // CHECK11-NEXT: store i32 [[TMP7]], ptr [[TMP15]], align 4
1138 // CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
1139 // CHECK11-NEXT: store ptr null, ptr [[TMP16]], align 4
1140 // CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1141 // CHECK11-NEXT: store i32 [[TMP0]], ptr [[TMP17]], align 4
1142 // CHECK11-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1143 // CHECK11-NEXT: store i32 [[TMP0]], ptr [[TMP18]], align 4
1144 // CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
1145 // CHECK11-NEXT: store ptr null, ptr [[TMP19]], align 4
1146 // CHECK11-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1147 // CHECK11-NEXT: store i32 [[TMP1]], ptr [[TMP20]], align 4
1148 // CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1149 // CHECK11-NEXT: store i32 [[TMP1]], ptr [[TMP21]], align 4
1150 // CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
1151 // CHECK11-NEXT: store ptr null, ptr [[TMP22]], align 4
1152 // CHECK11-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
1153 // CHECK11-NEXT: store ptr [[VLA]], ptr [[TMP23]], align 4
1154 // CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4
1155 // CHECK11-NEXT: store ptr [[VLA]], ptr [[TMP24]], align 4
1156 // CHECK11-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 4
1157 // CHECK11-NEXT: store i64 [[TMP10]], ptr [[TMP25]], align 4
1158 // CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
1159 // CHECK11-NEXT: store ptr null, ptr [[TMP26]], align 4
1160 // CHECK11-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1161 // CHECK11-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1162 // CHECK11-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0
1163 // CHECK11-NEXT: [[TMP30:%.*]] = load i32, ptr [[N]], align 4
1164 // CHECK11-NEXT: store i32 [[TMP30]], ptr [[DOTCAPTURE_EXPR_]], align 4
1165 // CHECK11-NEXT: [[TMP31:%.*]] = load i32, ptr [[M]], align 4
1166 // CHECK11-NEXT: store i32 [[TMP31]], ptr [[DOTCAPTURE_EXPR_2]], align 4
1167 // CHECK11-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1168 // CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP32]], 0
1169 // CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
1170 // CHECK11-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64
1171 // CHECK11-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
1172 // CHECK11-NEXT: [[SUB4:%.*]] = sub nsw i32 [[TMP33]], 0
1173 // CHECK11-NEXT: [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1
1174 // CHECK11-NEXT: [[CONV6:%.*]] = sext i32 [[DIV5]] to i64
1175 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]]
1176 // CHECK11-NEXT: [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1
1177 // CHECK11-NEXT: store i64 [[SUB7]], ptr [[DOTCAPTURE_EXPR_3]], align 8
1178 // CHECK11-NEXT: [[TMP34:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_3]], align 8
1179 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP34]], 1
1180 // CHECK11-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
1181 // CHECK11-NEXT: store i32 2, ptr [[TMP35]], align 4
1182 // CHECK11-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
1183 // CHECK11-NEXT: store i32 5, ptr [[TMP36]], align 4
1184 // CHECK11-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
1185 // CHECK11-NEXT: store ptr [[TMP27]], ptr [[TMP37]], align 4
1186 // CHECK11-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
1187 // CHECK11-NEXT: store ptr [[TMP28]], ptr [[TMP38]], align 4
1188 // CHECK11-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
1189 // CHECK11-NEXT: store ptr [[TMP29]], ptr [[TMP39]], align 4
1190 // CHECK11-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
1191 // CHECK11-NEXT: store ptr @.offload_maptypes, ptr [[TMP40]], align 4
1192 // CHECK11-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
1193 // CHECK11-NEXT: store ptr null, ptr [[TMP41]], align 4
1194 // CHECK11-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
1195 // CHECK11-NEXT: store ptr null, ptr [[TMP42]], align 4
1196 // CHECK11-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
1197 // CHECK11-NEXT: store i64 [[ADD]], ptr [[TMP43]], align 8
1198 // CHECK11-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
1199 // CHECK11-NEXT: store i64 0, ptr [[TMP44]], align 8
1200 // CHECK11-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
1201 // CHECK11-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP45]], align 4
1202 // CHECK11-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
1203 // CHECK11-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP46]], align 4
1204 // CHECK11-NEXT: [[TMP47:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
1205 // CHECK11-NEXT: store i32 0, ptr [[TMP47]], align 4
1206 // CHECK11-NEXT: [[TMP48:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80.region_id, ptr [[KERNEL_ARGS]])
1207 // CHECK11-NEXT: [[TMP49:%.*]] = icmp ne i32 [[TMP48]], 0
1208 // CHECK11-NEXT: br i1 [[TMP49]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1209 // CHECK11: omp_offload.failed:
1210 // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80(i32 [[TMP5]], i32 [[TMP7]], i32 [[TMP0]], i32 [[TMP1]], ptr [[VLA]]) #[[ATTR3:[0-9]+]]
1211 // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]]
1212 // CHECK11: omp_offload.cont:
1213 // CHECK11-NEXT: [[TMP50:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
1214 // CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP50]])
1215 // CHECK11-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
1216 // CHECK11-NEXT: [[TMP51:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
1217 // CHECK11-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP51]])
1218 // CHECK11-NEXT: [[TMP52:%.*]] = load i32, ptr [[RETVAL]], align 4
1219 // CHECK11-NEXT: ret i32 [[TMP52]]
1220 //
1221 //
1222 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80
1223 // CHECK11-SAME: (i32 noundef [[N:%.*]], i32 noundef [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2:[0-9]+]] {
1224 // CHECK11-NEXT: entry:
1225 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
1226 // CHECK11-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4
1227 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
1228 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
1229 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4
1230 // CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4
1231 // CHECK11-NEXT: [[M_CASTED:%.*]] = alloca i32, align 4
1232 // CHECK11-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
1233 // CHECK11-NEXT: store i32 [[M]], ptr [[M_ADDR]], align 4
1234 // CHECK11-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
1235 // CHECK11-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
1236 // CHECK11-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4
1237 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
1238 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
1239 // CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A_ADDR]], align 4
1240 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4
1241 // CHECK11-NEXT: store i32 [[TMP3]], ptr [[N_CASTED]], align 4
1242 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_CASTED]], align 4
1243 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[M_ADDR]], align 4
1244 // CHECK11-NEXT: store i32 [[TMP5]], ptr [[M_CASTED]], align 4
1245 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[M_CASTED]], align 4
1246 // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80.omp_outlined, i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP0]], i32 [[TMP1]], ptr [[TMP2]])
1247 // CHECK11-NEXT: ret void
1248 //
1249 //
1250 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l80.omp_outlined
1251 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[N:%.*]], i32 noundef [[M:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR2]] {
1252 // CHECK11-NEXT: entry:
1253 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
1254 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
1255 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
1256 // CHECK11-NEXT: [[M_ADDR:%.*]] = alloca i32, align 4
1257 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
1258 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
1259 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4
1260 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
1261 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4
1262 // CHECK11-NEXT: [[_TMP3:%.*]] = alloca i32, align 4
1263 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
1264 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4
1265 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i64, align 8
1266 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4
1267 // CHECK11-NEXT: [[J:%.*]] = alloca i32, align 4
1268 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
1269 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
1270 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
1271 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1272 // CHECK11-NEXT: [[I11:%.*]] = alloca i32, align 4
1273 // CHECK11-NEXT: [[J12:%.*]] = alloca i32, align 4
1274 // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
1275 // CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
1276 // CHECK11-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
1277 // CHECK11-NEXT: store i32 [[M]], ptr [[M_ADDR]], align 4
1278 // CHECK11-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
1279 // CHECK11-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
1280 // CHECK11-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4
1281 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
1282 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
1283 // CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[A_ADDR]], align 4
1284 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4
1285 // CHECK11-NEXT: store i32 [[TMP3]], ptr [[DOTCAPTURE_EXPR_]], align 4
1286 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[M_ADDR]], align 4
1287 // CHECK11-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_4]], align 4
1288 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1289 // CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP5]], 0
1290 // CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
1291 // CHECK11-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64
1292 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4
1293 // CHECK11-NEXT: [[SUB6:%.*]] = sub nsw i32 [[TMP6]], 0
1294 // CHECK11-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB6]], 1
1295 // CHECK11-NEXT: [[CONV8:%.*]] = sext i32 [[DIV7]] to i64
1296 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV8]]
1297 // CHECK11-NEXT: [[SUB9:%.*]] = sub nsw i64 [[MUL]], 1
1298 // CHECK11-NEXT: store i64 [[SUB9]], ptr [[DOTCAPTURE_EXPR_5]], align 8
1299 // CHECK11-NEXT: store i32 0, ptr [[I]], align 4
1300 // CHECK11-NEXT: store i32 0, ptr [[J]], align 4
1301 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1302 // CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP7]]
1303 // CHECK11-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]]
1304 // CHECK11: land.lhs.true:
1305 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4
1306 // CHECK11-NEXT: [[CMP10:%.*]] = icmp slt i32 0, [[TMP8]]
1307 // CHECK11-NEXT: br i1 [[CMP10]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]]
1308 // CHECK11: omp.precond.then:
1309 // CHECK11-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
1310 // CHECK11-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8
1311 // CHECK11-NEXT: store i64 [[TMP9]], ptr [[DOTOMP_UB]], align 8
1312 // CHECK11-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8
1313 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1314 // CHECK11-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
1315 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4
1316 // CHECK11-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1:[0-9]+]], i32 [[TMP11]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
1317 // CHECK11-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
1318 // CHECK11-NEXT: [[TMP13:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8
1319 // CHECK11-NEXT: [[CMP13:%.*]] = icmp sgt i64 [[TMP12]], [[TMP13]]
1320 // CHECK11-NEXT: br i1 [[CMP13]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1321 // CHECK11: cond.true:
1322 // CHECK11-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5]], align 8
1323 // CHECK11-NEXT: br label [[COND_END:%.*]]
1324 // CHECK11: cond.false:
1325 // CHECK11-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
1326 // CHECK11-NEXT: br label [[COND_END]]
1327 // CHECK11: cond.end:
1328 // CHECK11-NEXT: [[COND:%.*]] = phi i64 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ]
1329 // CHECK11-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8
1330 // CHECK11-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
1331 // CHECK11-NEXT: store i64 [[TMP16]], ptr [[DOTOMP_IV]], align 8
1332 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1333 // CHECK11: omp.inner.for.cond:
1334 // CHECK11-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP6:![0-9]+]]
1335 // CHECK11-NEXT: [[TMP18:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP6]]
1336 // CHECK11-NEXT: [[CMP14:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]]
1337 // CHECK11-NEXT: br i1 [[CMP14]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1338 // CHECK11: omp.inner.for.body:
1339 // CHECK11-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP6]]
1340 // CHECK11-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group [[ACC_GRP6]]
1341 // CHECK11-NEXT: [[SUB15:%.*]] = sub nsw i32 [[TMP20]], 0
1342 // CHECK11-NEXT: [[DIV16:%.*]] = sdiv i32 [[SUB15]], 1
1343 // CHECK11-NEXT: [[MUL17:%.*]] = mul nsw i32 1, [[DIV16]]
1344 // CHECK11-NEXT: [[CONV18:%.*]] = sext i32 [[MUL17]] to i64
1345 // CHECK11-NEXT: [[DIV19:%.*]] = sdiv i64 [[TMP19]], [[CONV18]]
1346 // CHECK11-NEXT: [[MUL20:%.*]] = mul nsw i64 [[DIV19]], 1
1347 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL20]]
1348 // CHECK11-NEXT: [[CONV21:%.*]] = trunc i64 [[ADD]] to i32
1349 // CHECK11-NEXT: store i32 [[CONV21]], ptr [[I11]], align 4, !llvm.access.group [[ACC_GRP6]]
1350 // CHECK11-NEXT: [[TMP21:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP6]]
1351 // CHECK11-NEXT: [[TMP22:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP6]]
1352 // CHECK11-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group [[ACC_GRP6]]
1353 // CHECK11-NEXT: [[SUB22:%.*]] = sub nsw i32 [[TMP23]], 0
1354 // CHECK11-NEXT: [[DIV23:%.*]] = sdiv i32 [[SUB22]], 1
1355 // CHECK11-NEXT: [[MUL24:%.*]] = mul nsw i32 1, [[DIV23]]
1356 // CHECK11-NEXT: [[CONV25:%.*]] = sext i32 [[MUL24]] to i64
1357 // CHECK11-NEXT: [[DIV26:%.*]] = sdiv i64 [[TMP22]], [[CONV25]]
1358 // CHECK11-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4, !llvm.access.group [[ACC_GRP6]]
1359 // CHECK11-NEXT: [[SUB27:%.*]] = sub nsw i32 [[TMP24]], 0
1360 // CHECK11-NEXT: [[DIV28:%.*]] = sdiv i32 [[SUB27]], 1
1361 // CHECK11-NEXT: [[MUL29:%.*]] = mul nsw i32 1, [[DIV28]]
1362 // CHECK11-NEXT: [[CONV30:%.*]] = sext i32 [[MUL29]] to i64
1363 // CHECK11-NEXT: [[MUL31:%.*]] = mul nsw i64 [[DIV26]], [[CONV30]]
1364 // CHECK11-NEXT: [[SUB32:%.*]] = sub nsw i64 [[TMP21]], [[MUL31]]
1365 // CHECK11-NEXT: [[MUL33:%.*]] = mul nsw i64 [[SUB32]], 1
1366 // CHECK11-NEXT: [[ADD34:%.*]] = add nsw i64 0, [[MUL33]]
1367 // CHECK11-NEXT: [[CONV35:%.*]] = trunc i64 [[ADD34]] to i32
1368 // CHECK11-NEXT: store i32 [[CONV35]], ptr [[J12]], align 4, !llvm.access.group [[ACC_GRP6]]
1369 // CHECK11-NEXT: [[TMP25:%.*]] = load i32, ptr [[I11]], align 4, !llvm.access.group [[ACC_GRP6]]
1370 // CHECK11-NEXT: [[TMP26:%.*]] = mul nsw i32 [[TMP25]], [[TMP1]]
1371 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP2]], i32 [[TMP26]]
1372 // CHECK11-NEXT: [[TMP27:%.*]] = load i32, ptr [[J12]], align 4, !llvm.access.group [[ACC_GRP6]]
1373 // CHECK11-NEXT: [[ARRAYIDX36:%.*]] = getelementptr inbounds i32, ptr [[ARRAYIDX]], i32 [[TMP27]]
1374 // CHECK11-NEXT: store i32 0, ptr [[ARRAYIDX36]], align 4, !llvm.access.group [[ACC_GRP6]]
1375 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1376 // CHECK11: omp.body.continue:
1377 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1378 // CHECK11: omp.inner.for.inc:
1379 // CHECK11-NEXT: [[TMP28:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP6]]
1380 // CHECK11-NEXT: [[ADD37:%.*]] = add nsw i64 [[TMP28]], 1
1381 // CHECK11-NEXT: store i64 [[ADD37]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP6]]
1382 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
1383 // CHECK11: omp.inner.for.end:
1384 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1385 // CHECK11: omp.loop.exit:
1386 // CHECK11-NEXT: [[TMP29:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
1387 // CHECK11-NEXT: [[TMP30:%.*]] = load i32, ptr [[TMP29]], align 4
1388 // CHECK11-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP30]])
1389 // CHECK11-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
1390 // CHECK11-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0
1391 // CHECK11-NEXT: br i1 [[TMP32]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1392 // CHECK11: .omp.final.then:
1393 // CHECK11-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1394 // CHECK11-NEXT: [[SUB38:%.*]] = sub nsw i32 [[TMP33]], 0
1395 // CHECK11-NEXT: [[DIV39:%.*]] = sdiv i32 [[SUB38]], 1
1396 // CHECK11-NEXT: [[MUL40:%.*]] = mul nsw i32 [[DIV39]], 1
1397 // CHECK11-NEXT: [[ADD41:%.*]] = add nsw i32 0, [[MUL40]]
1398 // CHECK11-NEXT: store i32 [[ADD41]], ptr [[I11]], align 4
1399 // CHECK11-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_4]], align 4
1400 // CHECK11-NEXT: [[SUB42:%.*]] = sub nsw i32 [[TMP34]], 0
1401 // CHECK11-NEXT: [[DIV43:%.*]] = sdiv i32 [[SUB42]], 1
1402 // CHECK11-NEXT: [[MUL44:%.*]] = mul nsw i32 [[DIV43]], 1
1403 // CHECK11-NEXT: [[ADD45:%.*]] = add nsw i32 0, [[MUL44]]
1404 // CHECK11-NEXT: store i32 [[ADD45]], ptr [[J12]], align 4
1405 // CHECK11-NEXT: br label [[DOTOMP_FINAL_DONE]]
1406 // CHECK11: .omp.final.done:
1407 // CHECK11-NEXT: br label [[OMP_PRECOND_END]]
1408 // CHECK11: omp.precond.end:
1409 // CHECK11-NEXT: ret void
1410 //
1411 //
1412 // CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_
1413 // CHECK11-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR5:[0-9]+]] comdat {
1414 // CHECK11-NEXT: entry:
1415 // CHECK11-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
1416 // CHECK11-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4
1417 // CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x ptr], align 4
1418 // CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x ptr], align 4
1419 // CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x ptr], align 4
1420 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4
1421 // CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
1422 // CHECK11-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1423 // CHECK11-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
1424 // CHECK11-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1425 // CHECK11-NEXT: store ptr [[A]], ptr [[TMP0]], align 4
1426 // CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1427 // CHECK11-NEXT: store ptr [[A]], ptr [[TMP1]], align 4
1428 // CHECK11-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
1429 // CHECK11-NEXT: store ptr null, ptr [[TMP2]], align 4
1430 // CHECK11-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1431 // CHECK11-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1432 // CHECK11-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
1433 // CHECK11-NEXT: store i32 2, ptr [[TMP5]], align 4
1434 // CHECK11-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
1435 // CHECK11-NEXT: store i32 1, ptr [[TMP6]], align 4
1436 // CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
1437 // CHECK11-NEXT: store ptr [[TMP3]], ptr [[TMP7]], align 4
1438 // CHECK11-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
1439 // CHECK11-NEXT: store ptr [[TMP4]], ptr [[TMP8]], align 4
1440 // CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
1441 // CHECK11-NEXT: store ptr @.offload_sizes.1, ptr [[TMP9]], align 4
1442 // CHECK11-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
1443 // CHECK11-NEXT: store ptr @.offload_maptypes.2, ptr [[TMP10]], align 4
1444 // CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
1445 // CHECK11-NEXT: store ptr null, ptr [[TMP11]], align 4
1446 // CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
1447 // CHECK11-NEXT: store ptr null, ptr [[TMP12]], align 4
1448 // CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
1449 // CHECK11-NEXT: store i64 20, ptr [[TMP13]], align 8
1450 // CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
1451 // CHECK11-NEXT: store i64 0, ptr [[TMP14]], align 8
1452 // CHECK11-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
1453 // CHECK11-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP15]], align 4
1454 // CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
1455 // CHECK11-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP16]], align 4
1456 // CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
1457 // CHECK11-NEXT: store i32 0, ptr [[TMP17]], align 4
1458 // CHECK11-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67.region_id, ptr [[KERNEL_ARGS]])
1459 // CHECK11-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
1460 // CHECK11-NEXT: br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1461 // CHECK11: omp_offload.failed:
1462 // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67(ptr [[A]]) #[[ATTR3]]
1463 // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]]
1464 // CHECK11: omp_offload.cont:
1465 // CHECK11-NEXT: ret i32 0
1466 //
1467 //
1468 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67
1469 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] {
1470 // CHECK11-NEXT: entry:
1471 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4
1472 // CHECK11-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4
1473 // CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4
1474 // CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67.omp_outlined, ptr [[TMP0]])
1475 // CHECK11-NEXT: ret void
1476 //
1477 //
1478 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiLi10ELi2EEiT__l67.omp_outlined
1479 // CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(80) [[A:%.*]]) #[[ATTR2]] {
1480 // CHECK11-NEXT: entry:
1481 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
1482 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
1483 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4
1484 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1485 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4
1486 // CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
1487 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1488 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1489 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1490 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1491 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4
1492 // CHECK11-NEXT: [[J:%.*]] = alloca i32, align 4
1493 // CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
1494 // CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
1495 // CHECK11-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4
1496 // CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4
1497 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
1498 // CHECK11-NEXT: store i32 19, ptr [[DOTOMP_UB]], align 4
1499 // CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1500 // CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1501 // CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
1502 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
1503 // CHECK11-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP2]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
1504 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1505 // CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 19
1506 // CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1507 // CHECK11: cond.true:
1508 // CHECK11-NEXT: br label [[COND_END:%.*]]
1509 // CHECK11: cond.false:
1510 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1511 // CHECK11-NEXT: br label [[COND_END]]
1512 // CHECK11: cond.end:
1513 // CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 19, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
1514 // CHECK11-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
1515 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1516 // CHECK11-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
1517 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1518 // CHECK11: omp.inner.for.cond:
1519 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12:![0-9]+]]
1520 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP12]]
1521 // CHECK11-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
1522 // CHECK11-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1523 // CHECK11: omp.inner.for.body:
1524 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]
1525 // CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 2
1526 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
1527 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1528 // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]]
1529 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]
1530 // CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]
1531 // CHECK11-NEXT: [[DIV3:%.*]] = sdiv i32 [[TMP10]], 2
1532 // CHECK11-NEXT: [[MUL4:%.*]] = mul nsw i32 [[DIV3]], 2
1533 // CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL4]]
1534 // CHECK11-NEXT: [[MUL5:%.*]] = mul nsw i32 [[SUB]], 1
1535 // CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]
1536 // CHECK11-NEXT: store i32 [[ADD6]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP12]]
1537 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]]
1538 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], ptr [[TMP0]], i32 0, i32 [[TMP11]]
1539 // CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP12]]
1540 // CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], i32 0, i32 [[TMP12]]
1541 // CHECK11-NEXT: store i32 0, ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP12]]
1542 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1543 // CHECK11: omp.body.continue:
1544 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1545 // CHECK11: omp.inner.for.inc:
1546 // CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]
1547 // CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP13]], 1
1548 // CHECK11-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]
1549 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
1550 // CHECK11: omp.inner.for.end:
1551 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
1552 // CHECK11: omp.loop.exit:
1553 // CHECK11-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])
1554 // CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
1555 // CHECK11-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
1556 // CHECK11-NEXT: br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1557 // CHECK11: .omp.final.then:
1558 // CHECK11-NEXT: store i32 10, ptr [[I]], align 4
1559 // CHECK11-NEXT: store i32 2, ptr [[J]], align 4
1560 // CHECK11-NEXT: br label [[DOTOMP_FINAL_DONE]]
1561 // CHECK11: .omp.final.done:
1562 // CHECK11-NEXT: ret void
1563 //
1564 //
1565 // CHECK11-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
1566 // CHECK11-SAME: () #[[ATTR6:[0-9]+]] {
1567 // CHECK11-NEXT: entry:
1568 // CHECK11-NEXT: call void @__tgt_register_requires(i64 1)
1569 // CHECK11-NEXT: ret void
1570 //
1571 //
1572 // CHECK13-LABEL: define {{[^@]+}}@main
1573 // CHECK13-SAME: (i32 noundef signext [[ARGC:%.*]], ptr noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] {
1574 // CHECK13-NEXT: entry:
1575 // CHECK13-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1576 // CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
1577 // CHECK13-NEXT: [[ARGV_ADDR:%.*]] = alloca ptr, align 8
1578 // CHECK13-NEXT: [[N:%.*]] = alloca i32, align 4
1579 // CHECK13-NEXT: [[M:%.*]] = alloca i32, align 4
1580 // CHECK13-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8
1581 // CHECK13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
1582 // CHECK13-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8
1583 // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4
1584 // CHECK13-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
1585 // CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
1586 // CHECK13-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
1587 // CHECK13-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8
1588 // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
1589 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
1590 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4
1591 // CHECK13-NEXT: [[J:%.*]] = alloca i32, align 4
1592 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
1593 // CHECK13-NEXT: [[I9:%.*]] = alloca i32, align 4
1594 // CHECK13-NEXT: [[J10:%.*]] = alloca i32, align 4
1595 // CHECK13-NEXT: store i32 0, ptr [[RETVAL]], align 4
1596 // CHECK13-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
1597 // CHECK13-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 8
1598 // CHECK13-NEXT: store i32 100, ptr [[N]], align 4
1599 // CHECK13-NEXT: store i32 2, ptr [[M]], align 4
1600 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
1601 // CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
1602 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, ptr [[M]], align 4
1603 // CHECK13-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
1604 // CHECK13-NEXT: [[TMP4:%.*]] = call ptr @llvm.stacksave.p0()
1605 // CHECK13-NEXT: store ptr [[TMP4]], ptr [[SAVED_STACK]], align 8
1606 // CHECK13-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP1]], [[TMP3]]
1607 // CHECK13-NEXT: [[VLA:%.*]] = alloca i32, i64 [[TMP5]], align 4
1608 // CHECK13-NEXT: store i64 [[TMP1]], ptr [[__VLA_EXPR0]], align 8
1609 // CHECK13-NEXT: store i64 [[TMP3]], ptr [[__VLA_EXPR1]], align 8
1610 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[N]], align 4
1611 // CHECK13-NEXT: store i32 [[TMP6]], ptr [[DOTCAPTURE_EXPR_]], align 4
1612 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[M]], align 4
1613 // CHECK13-NEXT: store i32 [[TMP7]], ptr [[DOTCAPTURE_EXPR_2]], align 4
1614 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1615 // CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP8]], 0
1616 // CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
1617 // CHECK13-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64
1618 // CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
1619 // CHECK13-NEXT: [[SUB4:%.*]] = sub nsw i32 [[TMP9]], 0
1620 // CHECK13-NEXT: [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1
1621 // CHECK13-NEXT: [[CONV6:%.*]] = sext i32 [[DIV5]] to i64
1622 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]]
1623 // CHECK13-NEXT: [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1
1624 // CHECK13-NEXT: store i64 [[SUB7]], ptr [[DOTCAPTURE_EXPR_3]], align 8
1625 // CHECK13-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
1626 // CHECK13-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_3]], align 8
1627 // CHECK13-NEXT: store i64 [[TMP10]], ptr [[DOTOMP_UB]], align 8
1628 // CHECK13-NEXT: store i32 0, ptr [[I]], align 4
1629 // CHECK13-NEXT: store i32 0, ptr [[J]], align 4
1630 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1631 // CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP11]]
1632 // CHECK13-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[SIMD_IF_END:%.*]]
1633 // CHECK13: land.lhs.true:
1634 // CHECK13-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
1635 // CHECK13-NEXT: [[CMP8:%.*]] = icmp slt i32 0, [[TMP12]]
1636 // CHECK13-NEXT: br i1 [[CMP8]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END]]
1637 // CHECK13: simd.if.then:
1638 // CHECK13-NEXT: [[TMP13:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
1639 // CHECK13-NEXT: store i64 [[TMP13]], ptr [[DOTOMP_IV]], align 8
1640 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1641 // CHECK13: omp.inner.for.cond:
1642 // CHECK13-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP2:![0-9]+]]
1643 // CHECK13-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP2]]
1644 // CHECK13-NEXT: [[CMP11:%.*]] = icmp sle i64 [[TMP14]], [[TMP15]]
1645 // CHECK13-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1646 // CHECK13: omp.inner.for.body:
1647 // CHECK13-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP2]]
1648 // CHECK13-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group [[ACC_GRP2]]
1649 // CHECK13-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP17]], 0
1650 // CHECK13-NEXT: [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1
1651 // CHECK13-NEXT: [[MUL14:%.*]] = mul nsw i32 1, [[DIV13]]
1652 // CHECK13-NEXT: [[CONV15:%.*]] = sext i32 [[MUL14]] to i64
1653 // CHECK13-NEXT: [[DIV16:%.*]] = sdiv i64 [[TMP16]], [[CONV15]]
1654 // CHECK13-NEXT: [[MUL17:%.*]] = mul nsw i64 [[DIV16]], 1
1655 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL17]]
1656 // CHECK13-NEXT: [[CONV18:%.*]] = trunc i64 [[ADD]] to i32
1657 // CHECK13-NEXT: store i32 [[CONV18]], ptr [[I9]], align 4, !llvm.access.group [[ACC_GRP2]]
1658 // CHECK13-NEXT: [[TMP18:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP2]]
1659 // CHECK13-NEXT: [[TMP19:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP2]]
1660 // CHECK13-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group [[ACC_GRP2]]
1661 // CHECK13-NEXT: [[SUB19:%.*]] = sub nsw i32 [[TMP20]], 0
1662 // CHECK13-NEXT: [[DIV20:%.*]] = sdiv i32 [[SUB19]], 1
1663 // CHECK13-NEXT: [[MUL21:%.*]] = mul nsw i32 1, [[DIV20]]
1664 // CHECK13-NEXT: [[CONV22:%.*]] = sext i32 [[MUL21]] to i64
1665 // CHECK13-NEXT: [[DIV23:%.*]] = sdiv i64 [[TMP19]], [[CONV22]]
1666 // CHECK13-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group [[ACC_GRP2]]
1667 // CHECK13-NEXT: [[SUB24:%.*]] = sub nsw i32 [[TMP21]], 0
1668 // CHECK13-NEXT: [[DIV25:%.*]] = sdiv i32 [[SUB24]], 1
1669 // CHECK13-NEXT: [[MUL26:%.*]] = mul nsw i32 1, [[DIV25]]
1670 // CHECK13-NEXT: [[CONV27:%.*]] = sext i32 [[MUL26]] to i64
1671 // CHECK13-NEXT: [[MUL28:%.*]] = mul nsw i64 [[DIV23]], [[CONV27]]
1672 // CHECK13-NEXT: [[SUB29:%.*]] = sub nsw i64 [[TMP18]], [[MUL28]]
1673 // CHECK13-NEXT: [[MUL30:%.*]] = mul nsw i64 [[SUB29]], 1
1674 // CHECK13-NEXT: [[ADD31:%.*]] = add nsw i64 0, [[MUL30]]
1675 // CHECK13-NEXT: [[CONV32:%.*]] = trunc i64 [[ADD31]] to i32
1676 // CHECK13-NEXT: store i32 [[CONV32]], ptr [[J10]], align 4, !llvm.access.group [[ACC_GRP2]]
1677 // CHECK13-NEXT: [[TMP22:%.*]] = load i32, ptr [[I9]], align 4, !llvm.access.group [[ACC_GRP2]]
1678 // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP22]] to i64
1679 // CHECK13-NEXT: [[TMP23:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP3]]
1680 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[VLA]], i64 [[TMP23]]
1681 // CHECK13-NEXT: [[TMP24:%.*]] = load i32, ptr [[J10]], align 4, !llvm.access.group [[ACC_GRP2]]
1682 // CHECK13-NEXT: [[IDXPROM33:%.*]] = sext i32 [[TMP24]] to i64
1683 // CHECK13-NEXT: [[ARRAYIDX34:%.*]] = getelementptr inbounds i32, ptr [[ARRAYIDX]], i64 [[IDXPROM33]]
1684 // CHECK13-NEXT: store i32 0, ptr [[ARRAYIDX34]], align 4, !llvm.access.group [[ACC_GRP2]]
1685 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1686 // CHECK13: omp.body.continue:
1687 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1688 // CHECK13: omp.inner.for.inc:
1689 // CHECK13-NEXT: [[TMP25:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP2]]
1690 // CHECK13-NEXT: [[ADD35:%.*]] = add nsw i64 [[TMP25]], 1
1691 // CHECK13-NEXT: store i64 [[ADD35]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP2]]
1692 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
1693 // CHECK13: omp.inner.for.end:
1694 // CHECK13-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1695 // CHECK13-NEXT: [[SUB36:%.*]] = sub nsw i32 [[TMP26]], 0
1696 // CHECK13-NEXT: [[DIV37:%.*]] = sdiv i32 [[SUB36]], 1
1697 // CHECK13-NEXT: [[MUL38:%.*]] = mul nsw i32 [[DIV37]], 1
1698 // CHECK13-NEXT: [[ADD39:%.*]] = add nsw i32 0, [[MUL38]]
1699 // CHECK13-NEXT: store i32 [[ADD39]], ptr [[I9]], align 4
1700 // CHECK13-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
1701 // CHECK13-NEXT: [[SUB40:%.*]] = sub nsw i32 [[TMP27]], 0
1702 // CHECK13-NEXT: [[DIV41:%.*]] = sdiv i32 [[SUB40]], 1
1703 // CHECK13-NEXT: [[MUL42:%.*]] = mul nsw i32 [[DIV41]], 1
1704 // CHECK13-NEXT: [[ADD43:%.*]] = add nsw i32 0, [[MUL42]]
1705 // CHECK13-NEXT: store i32 [[ADD43]], ptr [[J10]], align 4
1706 // CHECK13-NEXT: br label [[SIMD_IF_END]]
1707 // CHECK13: simd.if.end:
1708 // CHECK13-NEXT: [[TMP28:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
1709 // CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef signext [[TMP28]])
1710 // CHECK13-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
1711 // CHECK13-NEXT: [[TMP29:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
1712 // CHECK13-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP29]])
1713 // CHECK13-NEXT: [[TMP30:%.*]] = load i32, ptr [[RETVAL]], align 4
1714 // CHECK13-NEXT: ret i32 [[TMP30]]
1715 //
1716 //
1717 // CHECK13-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_
1718 // CHECK13-SAME: (i32 noundef signext [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat {
1719 // CHECK13-NEXT: entry:
1720 // CHECK13-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
1721 // CHECK13-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4
1722 // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4
1723 // CHECK13-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
1724 // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1725 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1726 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1727 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4
1728 // CHECK13-NEXT: [[J:%.*]] = alloca i32, align 4
1729 // CHECK13-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
1730 // CHECK13-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
1731 // CHECK13-NEXT: store i32 19, ptr [[DOTOMP_UB]], align 4
1732 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1733 // CHECK13-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4
1734 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1735 // CHECK13: omp.inner.for.cond:
1736 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]]
1737 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP6]]
1738 // CHECK13-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
1739 // CHECK13-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1740 // CHECK13: omp.inner.for.body:
1741 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
1742 // CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP3]], 2
1743 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
1744 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1745 // CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]]
1746 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
1747 // CHECK13-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
1748 // CHECK13-NEXT: [[DIV2:%.*]] = sdiv i32 [[TMP5]], 2
1749 // CHECK13-NEXT: [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 2
1750 // CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], [[MUL3]]
1751 // CHECK13-NEXT: [[MUL4:%.*]] = mul nsw i32 [[SUB]], 1
1752 // CHECK13-NEXT: [[ADD5:%.*]] = add nsw i32 0, [[MUL4]]
1753 // CHECK13-NEXT: store i32 [[ADD5]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP6]]
1754 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]]
1755 // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64
1756 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], ptr [[A]], i64 0, i64 [[IDXPROM]]
1757 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP6]]
1758 // CHECK13-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP7]] to i64
1759 // CHECK13-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM6]]
1760 // CHECK13-NEXT: store i32 0, ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP6]]
1761 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1762 // CHECK13: omp.body.continue:
1763 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1764 // CHECK13: omp.inner.for.inc:
1765 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
1766 // CHECK13-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP8]], 1
1767 // CHECK13-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
1768 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
1769 // CHECK13: omp.inner.for.end:
1770 // CHECK13-NEXT: store i32 10, ptr [[I]], align 4
1771 // CHECK13-NEXT: store i32 2, ptr [[J]], align 4
1772 // CHECK13-NEXT: ret i32 0
1773 //
1774 //
1775 // CHECK15-LABEL: define {{[^@]+}}@main
1776 // CHECK15-SAME: (i32 noundef [[ARGC:%.*]], ptr noundef [[ARGV:%.*]]) #[[ATTR0:[0-9]+]] {
1777 // CHECK15-NEXT: entry:
1778 // CHECK15-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
1779 // CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
1780 // CHECK15-NEXT: [[ARGV_ADDR:%.*]] = alloca ptr, align 4
1781 // CHECK15-NEXT: [[N:%.*]] = alloca i32, align 4
1782 // CHECK15-NEXT: [[M:%.*]] = alloca i32, align 4
1783 // CHECK15-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4
1784 // CHECK15-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
1785 // CHECK15-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4
1786 // CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4
1787 // CHECK15-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
1788 // CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
1789 // CHECK15-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4
1790 // CHECK15-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8
1791 // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
1792 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
1793 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4
1794 // CHECK15-NEXT: [[J:%.*]] = alloca i32, align 4
1795 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
1796 // CHECK15-NEXT: [[I9:%.*]] = alloca i32, align 4
1797 // CHECK15-NEXT: [[J10:%.*]] = alloca i32, align 4
1798 // CHECK15-NEXT: store i32 0, ptr [[RETVAL]], align 4
1799 // CHECK15-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
1800 // CHECK15-NEXT: store ptr [[ARGV]], ptr [[ARGV_ADDR]], align 4
1801 // CHECK15-NEXT: store i32 100, ptr [[N]], align 4
1802 // CHECK15-NEXT: store i32 2, ptr [[M]], align 4
1803 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[N]], align 4
1804 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, ptr [[M]], align 4
1805 // CHECK15-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave.p0()
1806 // CHECK15-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4
1807 // CHECK15-NEXT: [[TMP3:%.*]] = mul nuw i32 [[TMP0]], [[TMP1]]
1808 // CHECK15-NEXT: [[VLA:%.*]] = alloca i32, i32 [[TMP3]], align 4
1809 // CHECK15-NEXT: store i32 [[TMP0]], ptr [[__VLA_EXPR0]], align 4
1810 // CHECK15-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR1]], align 4
1811 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[N]], align 4
1812 // CHECK15-NEXT: store i32 [[TMP4]], ptr [[DOTCAPTURE_EXPR_]], align 4
1813 // CHECK15-NEXT: [[TMP5:%.*]] = load i32, ptr [[M]], align 4
1814 // CHECK15-NEXT: store i32 [[TMP5]], ptr [[DOTCAPTURE_EXPR_2]], align 4
1815 // CHECK15-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1816 // CHECK15-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP6]], 0
1817 // CHECK15-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
1818 // CHECK15-NEXT: [[CONV:%.*]] = sext i32 [[DIV]] to i64
1819 // CHECK15-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
1820 // CHECK15-NEXT: [[SUB4:%.*]] = sub nsw i32 [[TMP7]], 0
1821 // CHECK15-NEXT: [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1
1822 // CHECK15-NEXT: [[CONV6:%.*]] = sext i32 [[DIV5]] to i64
1823 // CHECK15-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV]], [[CONV6]]
1824 // CHECK15-NEXT: [[SUB7:%.*]] = sub nsw i64 [[MUL]], 1
1825 // CHECK15-NEXT: store i64 [[SUB7]], ptr [[DOTCAPTURE_EXPR_3]], align 8
1826 // CHECK15-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
1827 // CHECK15-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_3]], align 8
1828 // CHECK15-NEXT: store i64 [[TMP8]], ptr [[DOTOMP_UB]], align 8
1829 // CHECK15-NEXT: store i32 0, ptr [[I]], align 4
1830 // CHECK15-NEXT: store i32 0, ptr [[J]], align 4
1831 // CHECK15-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1832 // CHECK15-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP9]]
1833 // CHECK15-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[SIMD_IF_END:%.*]]
1834 // CHECK15: land.lhs.true:
1835 // CHECK15-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
1836 // CHECK15-NEXT: [[CMP8:%.*]] = icmp slt i32 0, [[TMP10]]
1837 // CHECK15-NEXT: br i1 [[CMP8]], label [[SIMD_IF_THEN:%.*]], label [[SIMD_IF_END]]
1838 // CHECK15: simd.if.then:
1839 // CHECK15-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
1840 // CHECK15-NEXT: store i64 [[TMP11]], ptr [[DOTOMP_IV]], align 8
1841 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1842 // CHECK15: omp.inner.for.cond:
1843 // CHECK15-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP3:![0-9]+]]
1844 // CHECK15-NEXT: [[TMP13:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP3]]
1845 // CHECK15-NEXT: [[CMP11:%.*]] = icmp sle i64 [[TMP12]], [[TMP13]]
1846 // CHECK15-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1847 // CHECK15: omp.inner.for.body:
1848 // CHECK15-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP3]]
1849 // CHECK15-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group [[ACC_GRP3]]
1850 // CHECK15-NEXT: [[SUB12:%.*]] = sub nsw i32 [[TMP15]], 0
1851 // CHECK15-NEXT: [[DIV13:%.*]] = sdiv i32 [[SUB12]], 1
1852 // CHECK15-NEXT: [[MUL14:%.*]] = mul nsw i32 1, [[DIV13]]
1853 // CHECK15-NEXT: [[CONV15:%.*]] = sext i32 [[MUL14]] to i64
1854 // CHECK15-NEXT: [[DIV16:%.*]] = sdiv i64 [[TMP14]], [[CONV15]]
1855 // CHECK15-NEXT: [[MUL17:%.*]] = mul nsw i64 [[DIV16]], 1
1856 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i64 0, [[MUL17]]
1857 // CHECK15-NEXT: [[CONV18:%.*]] = trunc i64 [[ADD]] to i32
1858 // CHECK15-NEXT: store i32 [[CONV18]], ptr [[I9]], align 4, !llvm.access.group [[ACC_GRP3]]
1859 // CHECK15-NEXT: [[TMP16:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP3]]
1860 // CHECK15-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP3]]
1861 // CHECK15-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group [[ACC_GRP3]]
1862 // CHECK15-NEXT: [[SUB19:%.*]] = sub nsw i32 [[TMP18]], 0
1863 // CHECK15-NEXT: [[DIV20:%.*]] = sdiv i32 [[SUB19]], 1
1864 // CHECK15-NEXT: [[MUL21:%.*]] = mul nsw i32 1, [[DIV20]]
1865 // CHECK15-NEXT: [[CONV22:%.*]] = sext i32 [[MUL21]] to i64
1866 // CHECK15-NEXT: [[DIV23:%.*]] = sdiv i64 [[TMP17]], [[CONV22]]
1867 // CHECK15-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4, !llvm.access.group [[ACC_GRP3]]
1868 // CHECK15-NEXT: [[SUB24:%.*]] = sub nsw i32 [[TMP19]], 0
1869 // CHECK15-NEXT: [[DIV25:%.*]] = sdiv i32 [[SUB24]], 1
1870 // CHECK15-NEXT: [[MUL26:%.*]] = mul nsw i32 1, [[DIV25]]
1871 // CHECK15-NEXT: [[CONV27:%.*]] = sext i32 [[MUL26]] to i64
1872 // CHECK15-NEXT: [[MUL28:%.*]] = mul nsw i64 [[DIV23]], [[CONV27]]
1873 // CHECK15-NEXT: [[SUB29:%.*]] = sub nsw i64 [[TMP16]], [[MUL28]]
1874 // CHECK15-NEXT: [[MUL30:%.*]] = mul nsw i64 [[SUB29]], 1
1875 // CHECK15-NEXT: [[ADD31:%.*]] = add nsw i64 0, [[MUL30]]
1876 // CHECK15-NEXT: [[CONV32:%.*]] = trunc i64 [[ADD31]] to i32
1877 // CHECK15-NEXT: store i32 [[CONV32]], ptr [[J10]], align 4, !llvm.access.group [[ACC_GRP3]]
1878 // CHECK15-NEXT: [[TMP20:%.*]] = load i32, ptr [[I9]], align 4, !llvm.access.group [[ACC_GRP3]]
1879 // CHECK15-NEXT: [[TMP21:%.*]] = mul nsw i32 [[TMP20]], [[TMP1]]
1880 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[VLA]], i32 [[TMP21]]
1881 // CHECK15-NEXT: [[TMP22:%.*]] = load i32, ptr [[J10]], align 4, !llvm.access.group [[ACC_GRP3]]
1882 // CHECK15-NEXT: [[ARRAYIDX33:%.*]] = getelementptr inbounds i32, ptr [[ARRAYIDX]], i32 [[TMP22]]
1883 // CHECK15-NEXT: store i32 0, ptr [[ARRAYIDX33]], align 4, !llvm.access.group [[ACC_GRP3]]
1884 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1885 // CHECK15: omp.body.continue:
1886 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1887 // CHECK15: omp.inner.for.inc:
1888 // CHECK15-NEXT: [[TMP23:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP3]]
1889 // CHECK15-NEXT: [[ADD34:%.*]] = add nsw i64 [[TMP23]], 1
1890 // CHECK15-NEXT: store i64 [[ADD34]], ptr [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP3]]
1891 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
1892 // CHECK15: omp.inner.for.end:
1893 // CHECK15-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
1894 // CHECK15-NEXT: [[SUB35:%.*]] = sub nsw i32 [[TMP24]], 0
1895 // CHECK15-NEXT: [[DIV36:%.*]] = sdiv i32 [[SUB35]], 1
1896 // CHECK15-NEXT: [[MUL37:%.*]] = mul nsw i32 [[DIV36]], 1
1897 // CHECK15-NEXT: [[ADD38:%.*]] = add nsw i32 0, [[MUL37]]
1898 // CHECK15-NEXT: store i32 [[ADD38]], ptr [[I9]], align 4
1899 // CHECK15-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2]], align 4
1900 // CHECK15-NEXT: [[SUB39:%.*]] = sub nsw i32 [[TMP25]], 0
1901 // CHECK15-NEXT: [[DIV40:%.*]] = sdiv i32 [[SUB39]], 1
1902 // CHECK15-NEXT: [[MUL41:%.*]] = mul nsw i32 [[DIV40]], 1
1903 // CHECK15-NEXT: [[ADD42:%.*]] = add nsw i32 0, [[MUL41]]
1904 // CHECK15-NEXT: store i32 [[ADD42]], ptr [[J10]], align 4
1905 // CHECK15-NEXT: br label [[SIMD_IF_END]]
1906 // CHECK15: simd.if.end:
1907 // CHECK15-NEXT: [[TMP26:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4
1908 // CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z5tmainIiLi10ELi2EEiT_(i32 noundef [[TMP26]])
1909 // CHECK15-NEXT: store i32 [[CALL]], ptr [[RETVAL]], align 4
1910 // CHECK15-NEXT: [[TMP27:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
1911 // CHECK15-NEXT: call void @llvm.stackrestore.p0(ptr [[TMP27]])
1912 // CHECK15-NEXT: [[TMP28:%.*]] = load i32, ptr [[RETVAL]], align 4
1913 // CHECK15-NEXT: ret i32 [[TMP28]]
1914 //
1915 //
1916 // CHECK15-LABEL: define {{[^@]+}}@_Z5tmainIiLi10ELi2EEiT_
1917 // CHECK15-SAME: (i32 noundef [[ARGC:%.*]]) #[[ATTR2:[0-9]+]] comdat {
1918 // CHECK15-NEXT: entry:
1919 // CHECK15-NEXT: [[ARGC_ADDR:%.*]] = alloca i32, align 4
1920 // CHECK15-NEXT: [[A:%.*]] = alloca [10 x [2 x i32]], align 4
1921 // CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4
1922 // CHECK15-NEXT: [[_TMP1:%.*]] = alloca i32, align 4
1923 // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
1924 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
1925 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
1926 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4
1927 // CHECK15-NEXT: [[J:%.*]] = alloca i32, align 4
1928 // CHECK15-NEXT: store i32 [[ARGC]], ptr [[ARGC_ADDR]], align 4
1929 // CHECK15-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
1930 // CHECK15-NEXT: store i32 19, ptr [[DOTOMP_UB]], align 4
1931 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1932 // CHECK15-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4
1933 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
1934 // CHECK15: omp.inner.for.cond:
1935 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7:![0-9]+]]
1936 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP7]]
1937 // CHECK15-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
1938 // CHECK15-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1939 // CHECK15: omp.inner.for.body:
1940 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]]
1941 // CHECK15-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP3]], 2
1942 // CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
1943 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1944 // CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]]
1945 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]]
1946 // CHECK15-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]]
1947 // CHECK15-NEXT: [[DIV2:%.*]] = sdiv i32 [[TMP5]], 2
1948 // CHECK15-NEXT: [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 2
1949 // CHECK15-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP4]], [[MUL3]]
1950 // CHECK15-NEXT: [[MUL4:%.*]] = mul nsw i32 [[SUB]], 1
1951 // CHECK15-NEXT: [[ADD5:%.*]] = add nsw i32 0, [[MUL4]]
1952 // CHECK15-NEXT: store i32 [[ADD5]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP7]]
1953 // CHECK15-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]]
1954 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], ptr [[A]], i32 0, i32 [[TMP6]]
1955 // CHECK15-NEXT: [[TMP7:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP7]]
1956 // CHECK15-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], i32 0, i32 [[TMP7]]
1957 // CHECK15-NEXT: store i32 0, ptr [[ARRAYIDX6]], align 4, !llvm.access.group [[ACC_GRP7]]
1958 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
1959 // CHECK15: omp.body.continue:
1960 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
1961 // CHECK15: omp.inner.for.inc:
1962 // CHECK15-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]]
1963 // CHECK15-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP8]], 1
1964 // CHECK15-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]]
1965 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
1966 // CHECK15: omp.inner.for.end:
1967 // CHECK15-NEXT: store i32 10, ptr [[I]], align 4
1968 // CHECK15-NEXT: store i32 2, ptr [[J]], align 4
1969 // CHECK15-NEXT: ret i32 0
1970 //
LLVM monorepo