clang/test/OpenMP/target_teams_distribute_simd_private_codegen.cpp

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
   2 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK1
   3 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
   4 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK1
   5 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK3
   6 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
   7 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK3
   8
   9 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK5
  10 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
  11 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK5
  12 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK7
  13 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
  14 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK7
  15
  16 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK9
  17 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
  18 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++  -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK9
  19
  20 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK11
  21 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
  22 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++  -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK11
  23
  24 // expected-no-diagnostics
  25 #ifndef HEADER
  26 #define HEADER
  27
  28 struct St {
  29   int a, b;
  30   St() : a(0), b(0) {}
  31   St(const St &st) : a(st.a + st.b), b(0) {}
  32   ~St() {}
  33 };
  34
  35 volatile int g = 1212;
  36 volatile int &g1 = g;
  37
  38 template <class T>
  39 struct S {
  40   T f;
  41   S(T a) : f(a + g) {}
  42   S() : f(g) {}
  43   S(const S &s, St t = St()) : f(s.f + t.a) {}
  44   operator T() { return T(); }
  45   ~S() {}
  46 };
  47
  48
  49 template <typename T>
  50 T tmain() {
  51   S<T> test;
  52   T t_var = T();
  53   T vec[] = {1, 2};
  54   S<T> s_arr[] = {1, 2};
  55   S<T> &var = test;
  56 #pragma omp target teams distribute simd private(t_var, vec, s_arr, var)
  57   for (int i = 0; i < 2; ++i) {
  58     vec[i] = t_var;
  59     s_arr[i] = var;
  60   }
  61   return T();
  62 }
  63
  64 S<float> test;
  65 int t_var = 333;
  66 int vec[] = {1, 2};
  67 S<float> s_arr[] = {1, 2};
  68 S<float> var(3);
  69
  70 int main() {
  71   static int sivar;
  72 #ifdef LAMBDA
  73   [&]() {
  74 #pragma omp target teams distribute simd private(g, g1, sivar)
  75   for (int i = 0; i < 2; ++i) {
  76
  77     // Skip global, bound tid and loop vars
  78     g = 1;
  79     g1 = 1;
  80     sivar = 2;
  81     [&]() {
  82       g = 2;
  83       g1 = 2;
  84       sivar = 4;
  85
  86     }();
  87   }
  88   }();
  89   return 0;
  90 #else
  91 #pragma omp target teams distribute simd private(t_var, vec, s_arr, var, sivar)
  92   for (int i = 0; i < 2; ++i) {
  93     vec[i] = t_var;
  94     s_arr[i] = var;
  95     sivar += i;
  96   }
  97   return tmain<int>();
  98 #endif
  99 }
 100
 101
 102
 103 // Skip global, bound tid and loop vars
 104
 105 // private(s_arr)
 106
 107 // private(var)
 108
 109
 110
 111
 112
 113 // Skip global, bound tid and loop vars
 114
 115 // private(s_arr)
 116
 117
 118 // private(var)
 119
 120
 121 #endif
 122 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init
 123 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
 124 // CHECK1-NEXT:  entry:
 125 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
 126 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
 127 // CHECK1-NEXT:    ret void
 128 //
 129 //
 130 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
 131 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
 132 // CHECK1-NEXT:  entry:
 133 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 134 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 135 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 136 // CHECK1-NEXT:    call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
 137 // CHECK1-NEXT:    ret void
 138 //
 139 //
 140 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
 141 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
 142 // CHECK1-NEXT:  entry:
 143 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 144 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 145 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 146 // CHECK1-NEXT:    call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
 147 // CHECK1-NEXT:    ret void
 148 //
 149 //
 150 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
 151 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
 152 // CHECK1-NEXT:  entry:
 153 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 154 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 155 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 156 // CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
 157 // CHECK1-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
 158 // CHECK1-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
 159 // CHECK1-NEXT:    store float [[CONV]], ptr [[F]], align 4
 160 // CHECK1-NEXT:    ret void
 161 //
 162 //
 163 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
 164 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
 165 // CHECK1-NEXT:  entry:
 166 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 167 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 168 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 169 // CHECK1-NEXT:    ret void
 170 //
 171 //
 172 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
 173 // CHECK1-SAME: () #[[ATTR0]] {
 174 // CHECK1-NEXT:  entry:
 175 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
 176 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)
 177 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
 178 // CHECK1-NEXT:    ret void
 179 //
 180 //
 181 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
 182 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
 183 // CHECK1-NEXT:  entry:
 184 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 185 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
 186 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 187 // CHECK1-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
 188 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 189 // CHECK1-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
 190 // CHECK1-NEXT:    call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
 191 // CHECK1-NEXT:    ret void
 192 //
 193 //
 194 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
 195 // CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {
 196 // CHECK1-NEXT:  entry:
 197 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
 198 // CHECK1-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
 199 // CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
 200 // CHECK1:       arraydestroy.body:
 201 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
 202 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
 203 // CHECK1-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
 204 // CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr
 205 // CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
 206 // CHECK1:       arraydestroy.done1:
 207 // CHECK1-NEXT:    ret void
 208 //
 209 //
 210 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
 211 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
 212 // CHECK1-NEXT:  entry:
 213 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 214 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
 215 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 216 // CHECK1-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
 217 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 218 // CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
 219 // CHECK1-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
 220 // CHECK1-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
 221 // CHECK1-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
 222 // CHECK1-NEXT:    [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
 223 // CHECK1-NEXT:    store float [[ADD]], ptr [[F]], align 4
 224 // CHECK1-NEXT:    ret void
 225 //
 226 //
 227 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
 228 // CHECK1-SAME: () #[[ATTR0]] {
 229 // CHECK1-NEXT:  entry:
 230 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)
 231 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]
 232 // CHECK1-NEXT:    ret void
 233 //
 234 //
 235 // CHECK1-LABEL: define {{[^@]+}}@main
 236 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] {
 237 // CHECK1-NEXT:  entry:
 238 // CHECK1-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
 239 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 240 // CHECK1-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
 241 // CHECK1-NEXT:    store i32 0, ptr [[RETVAL]], align 4
 242 // CHECK1-NEXT:    [[TMP0:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
 243 // CHECK1-NEXT:    store i32 2, ptr [[TMP0]], align 4
 244 // CHECK1-NEXT:    [[TMP1:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
 245 // CHECK1-NEXT:    store i32 0, ptr [[TMP1]], align 4
 246 // CHECK1-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
 247 // CHECK1-NEXT:    store ptr null, ptr [[TMP2]], align 8
 248 // CHECK1-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
 249 // CHECK1-NEXT:    store ptr null, ptr [[TMP3]], align 8
 250 // CHECK1-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
 251 // CHECK1-NEXT:    store ptr null, ptr [[TMP4]], align 8
 252 // CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
 253 // CHECK1-NEXT:    store ptr null, ptr [[TMP5]], align 8
 254 // CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
 255 // CHECK1-NEXT:    store ptr null, ptr [[TMP6]], align 8
 256 // CHECK1-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
 257 // CHECK1-NEXT:    store ptr null, ptr [[TMP7]], align 8
 258 // CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
 259 // CHECK1-NEXT:    store i64 2, ptr [[TMP8]], align 8
 260 // CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
 261 // CHECK1-NEXT:    store i64 0, ptr [[TMP9]], align 8
 262 // CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
 263 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4
 264 // CHECK1-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
 265 // CHECK1-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP11]], align 4
 266 // CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
 267 // CHECK1-NEXT:    store i32 0, ptr [[TMP12]], align 4
 268 // CHECK1-NEXT:    [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91.region_id, ptr [[KERNEL_ARGS]])
 269 // CHECK1-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
 270 // CHECK1-NEXT:    br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
 271 // CHECK1:       omp_offload.failed:
 272 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91() #[[ATTR2]]
 273 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
 274 // CHECK1:       omp_offload.cont:
 275 // CHECK1-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v()
 276 // CHECK1-NEXT:    ret i32 [[CALL]]
 277 //
 278 //
 279 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91
 280 // CHECK1-SAME: () #[[ATTR4:[0-9]+]] {
 281 // CHECK1-NEXT:  entry:
 282 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91.omp_outlined)
 283 // CHECK1-NEXT:    ret void
 284 //
 285 //
 286 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91.omp_outlined
 287 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {
 288 // CHECK1-NEXT:  entry:
 289 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 290 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 291 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 292 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 293 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
 294 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
 295 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 296 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 297 // CHECK1-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
 298 // CHECK1-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
 299 // CHECK1-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
 300 // CHECK1-NEXT:    [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
 301 // CHECK1-NEXT:    [[SIVAR:%.*]] = alloca i32, align 4
 302 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
 303 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 304 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 305 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
 306 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
 307 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 308 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 309 // CHECK1-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
 310 // CHECK1-NEXT:    [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2
 311 // CHECK1-NEXT:    br label [[ARRAYCTOR_LOOP:%.*]]
 312 // CHECK1:       arrayctor.loop:
 313 // CHECK1-NEXT:    [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
 314 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
 315 // CHECK1-NEXT:    [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1
 316 // CHECK1-NEXT:    [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
 317 // CHECK1-NEXT:    br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
 318 // CHECK1:       arrayctor.cont:
 319 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]])
 320 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 321 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
 322 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
 323 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 324 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
 325 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 326 // CHECK1:       cond.true:
 327 // CHECK1-NEXT:    br label [[COND_END:%.*]]
 328 // CHECK1:       cond.false:
 329 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 330 // CHECK1-NEXT:    br label [[COND_END]]
 331 // CHECK1:       cond.end:
 332 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
 333 // CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
 334 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
 335 // CHECK1-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
 336 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 337 // CHECK1:       omp.inner.for.cond:
 338 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5:![0-9]+]]
 339 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP5]]
 340 // CHECK1-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
 341 // CHECK1-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
 342 // CHECK1:       omp.inner.for.cond.cleanup:
 343 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
 344 // CHECK1:       omp.inner.for.body:
 345 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]]
 346 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
 347 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
 348 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]]
 349 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP5]]
 350 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]]
 351 // CHECK1-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64
 352 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]]
 353 // CHECK1-NEXT:    store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP5]]
 354 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]]
 355 // CHECK1-NEXT:    [[IDXPROM2:%.*]] = sext i32 [[TMP10]] to i64
 356 // CHECK1-NEXT:    [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM2]]
 357 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX3]], ptr align 4 [[VAR]], i64 4, i1 false), !llvm.access.group [[ACC_GRP5]]
 358 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]]
 359 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP5]]
 360 // CHECK1-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP12]], [[TMP11]]
 361 // CHECK1-NEXT:    store i32 [[ADD4]], ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP5]]
 362 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 363 // CHECK1:       omp.body.continue:
 364 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 365 // CHECK1:       omp.inner.for.inc:
 366 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]]
 367 // CHECK1-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP13]], 1
 368 // CHECK1-NEXT:    store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]]
 369 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
 370 // CHECK1:       omp.inner.for.end:
 371 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
 372 // CHECK1:       omp.loop.exit:
 373 // CHECK1-NEXT:    [[TMP14:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 374 // CHECK1-NEXT:    [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4
 375 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP15]])
 376 // CHECK1-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
 377 // CHECK1-NEXT:    [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
 378 // CHECK1-NEXT:    br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
 379 // CHECK1:       .omp.final.then:
 380 // CHECK1-NEXT:    store i32 2, ptr [[I]], align 4
 381 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
 382 // CHECK1:       .omp.final.done:
 383 // CHECK1-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
 384 // CHECK1-NEXT:    [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
 385 // CHECK1-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN6]], i64 2
 386 // CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
 387 // CHECK1:       arraydestroy.body:
 388 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP18]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
 389 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
 390 // CHECK1-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
 391 // CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]]
 392 // CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]]
 393 // CHECK1:       arraydestroy.done7:
 394 // CHECK1-NEXT:    ret void
 395 //
 396 //
 397 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
 398 // CHECK1-SAME: () #[[ATTR6:[0-9]+]] comdat {
 399 // CHECK1-NEXT:  entry:
 400 // CHECK1-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
 401 // CHECK1-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
 402 // CHECK1-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
 403 // CHECK1-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
 404 // CHECK1-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
 405 // CHECK1-NEXT:    [[VAR:%.*]] = alloca ptr, align 8
 406 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 407 // CHECK1-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 8
 408 // CHECK1-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
 409 // CHECK1-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])
 410 // CHECK1-NEXT:    store i32 0, ptr [[T_VAR]], align 4
 411 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false)
 412 // CHECK1-NEXT:    [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 0
 413 // CHECK1-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef signext 1)
 414 // CHECK1-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYINIT_BEGIN]], i64 1
 415 // CHECK1-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2)
 416 // CHECK1-NEXT:    store ptr [[TEST]], ptr [[VAR]], align 8
 417 // CHECK1-NEXT:    store ptr undef, ptr [[_TMP1]], align 8
 418 // CHECK1-NEXT:    [[TMP0:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
 419 // CHECK1-NEXT:    store i32 2, ptr [[TMP0]], align 4
 420 // CHECK1-NEXT:    [[TMP1:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
 421 // CHECK1-NEXT:    store i32 0, ptr [[TMP1]], align 4
 422 // CHECK1-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
 423 // CHECK1-NEXT:    store ptr null, ptr [[TMP2]], align 8
 424 // CHECK1-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
 425 // CHECK1-NEXT:    store ptr null, ptr [[TMP3]], align 8
 426 // CHECK1-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
 427 // CHECK1-NEXT:    store ptr null, ptr [[TMP4]], align 8
 428 // CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
 429 // CHECK1-NEXT:    store ptr null, ptr [[TMP5]], align 8
 430 // CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
 431 // CHECK1-NEXT:    store ptr null, ptr [[TMP6]], align 8
 432 // CHECK1-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
 433 // CHECK1-NEXT:    store ptr null, ptr [[TMP7]], align 8
 434 // CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
 435 // CHECK1-NEXT:    store i64 2, ptr [[TMP8]], align 8
 436 // CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
 437 // CHECK1-NEXT:    store i64 0, ptr [[TMP9]], align 8
 438 // CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
 439 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4
 440 // CHECK1-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
 441 // CHECK1-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP11]], align 4
 442 // CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
 443 // CHECK1-NEXT:    store i32 0, ptr [[TMP12]], align 4
 444 // CHECK1-NEXT:    [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, ptr [[KERNEL_ARGS]])
 445 // CHECK1-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
 446 // CHECK1-NEXT:    br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
 447 // CHECK1:       omp_offload.failed:
 448 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56() #[[ATTR2]]
 449 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
 450 // CHECK1:       omp_offload.cont:
 451 // CHECK1-NEXT:    store i32 0, ptr [[RETVAL]], align 4
 452 // CHECK1-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
 453 // CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2
 454 // CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
 455 // CHECK1:       arraydestroy.body:
 456 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
 457 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
 458 // CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
 459 // CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
 460 // CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
 461 // CHECK1:       arraydestroy.done2:
 462 // CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
 463 // CHECK1-NEXT:    [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4
 464 // CHECK1-NEXT:    ret i32 [[TMP16]]
 465 //
 466 //
 467 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
 468 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
 469 // CHECK1-NEXT:  entry:
 470 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 471 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 472 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 473 // CHECK1-NEXT:    call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
 474 // CHECK1-NEXT:    ret void
 475 //
 476 //
 477 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
 478 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
 479 // CHECK1-NEXT:  entry:
 480 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 481 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
 482 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 483 // CHECK1-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
 484 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 485 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
 486 // CHECK1-NEXT:    call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
 487 // CHECK1-NEXT:    ret void
 488 //
 489 //
 490 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56
 491 // CHECK1-SAME: () #[[ATTR4]] {
 492 // CHECK1-NEXT:  entry:
 493 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined)
 494 // CHECK1-NEXT:    ret void
 495 //
 496 //
 497 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined
 498 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {
 499 // CHECK1-NEXT:  entry:
 500 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 501 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 502 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 503 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 504 // CHECK1-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 8
 505 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
 506 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
 507 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 508 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 509 // CHECK1-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
 510 // CHECK1-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
 511 // CHECK1-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
 512 // CHECK1-NEXT:    [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
 513 // CHECK1-NEXT:    [[_TMP2:%.*]] = alloca ptr, align 8
 514 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
 515 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 516 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 517 // CHECK1-NEXT:    store ptr undef, ptr [[_TMP1]], align 8
 518 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
 519 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
 520 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 521 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 522 // CHECK1-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
 523 // CHECK1-NEXT:    [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2
 524 // CHECK1-NEXT:    br label [[ARRAYCTOR_LOOP:%.*]]
 525 // CHECK1:       arrayctor.loop:
 526 // CHECK1-NEXT:    [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
 527 // CHECK1-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
 528 // CHECK1-NEXT:    [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i64 1
 529 // CHECK1-NEXT:    [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
 530 // CHECK1-NEXT:    br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
 531 // CHECK1:       arrayctor.cont:
 532 // CHECK1-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]])
 533 // CHECK1-NEXT:    store ptr [[VAR]], ptr [[_TMP2]], align 8
 534 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 535 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
 536 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
 537 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 538 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
 539 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 540 // CHECK1:       cond.true:
 541 // CHECK1-NEXT:    br label [[COND_END:%.*]]
 542 // CHECK1:       cond.false:
 543 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 544 // CHECK1-NEXT:    br label [[COND_END]]
 545 // CHECK1:       cond.end:
 546 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
 547 // CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
 548 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
 549 // CHECK1-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
 550 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 551 // CHECK1:       omp.inner.for.cond:
 552 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11:![0-9]+]]
 553 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP11]]
 554 // CHECK1-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
 555 // CHECK1-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
 556 // CHECK1:       omp.inner.for.cond.cleanup:
 557 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
 558 // CHECK1:       omp.inner.for.body:
 559 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]
 560 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
 561 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
 562 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]]
 563 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP11]]
 564 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]]
 565 // CHECK1-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64
 566 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]]
 567 // CHECK1-NEXT:    store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP11]]
 568 // CHECK1-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8, !llvm.access.group [[ACC_GRP11]]
 569 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]]
 570 // CHECK1-NEXT:    [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64
 571 // CHECK1-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]]
 572 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX5]], ptr align 4 [[TMP10]], i64 4, i1 false), !llvm.access.group [[ACC_GRP11]]
 573 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 574 // CHECK1:       omp.body.continue:
 575 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 576 // CHECK1:       omp.inner.for.inc:
 577 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]
 578 // CHECK1-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP12]], 1
 579 // CHECK1-NEXT:    store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]]
 580 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]]
 581 // CHECK1:       omp.inner.for.end:
 582 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
 583 // CHECK1:       omp.loop.exit:
 584 // CHECK1-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 585 // CHECK1-NEXT:    [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4
 586 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]])
 587 // CHECK1-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
 588 // CHECK1-NEXT:    [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0
 589 // CHECK1-NEXT:    br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
 590 // CHECK1:       .omp.final.then:
 591 // CHECK1-NEXT:    store i32 2, ptr [[I]], align 4
 592 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
 593 // CHECK1:       .omp.final.done:
 594 // CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
 595 // CHECK1-NEXT:    [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
 596 // CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN7]], i64 2
 597 // CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
 598 // CHECK1:       arraydestroy.body:
 599 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
 600 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
 601 // CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
 602 // CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]
 603 // CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]
 604 // CHECK1:       arraydestroy.done8:
 605 // CHECK1-NEXT:    ret void
 606 //
 607 //
 608 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
 609 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
 610 // CHECK1-NEXT:  entry:
 611 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 612 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 613 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 614 // CHECK1-NEXT:    call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
 615 // CHECK1-NEXT:    ret void
 616 //
 617 //
 618 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
 619 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
 620 // CHECK1-NEXT:  entry:
 621 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 622 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 623 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 624 // CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
 625 // CHECK1-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
 626 // CHECK1-NEXT:    store i32 [[TMP0]], ptr [[F]], align 4
 627 // CHECK1-NEXT:    ret void
 628 //
 629 //
 630 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
 631 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
 632 // CHECK1-NEXT:  entry:
 633 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 634 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
 635 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 636 // CHECK1-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
 637 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 638 // CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
 639 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
 640 // CHECK1-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
 641 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
 642 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[F]], align 4
 643 // CHECK1-NEXT:    ret void
 644 //
 645 //
 646 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
 647 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
 648 // CHECK1-NEXT:  entry:
 649 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 650 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 651 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 652 // CHECK1-NEXT:    ret void
 653 //
 654 //
 655 // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_private_codegen.cpp
 656 // CHECK1-SAME: () #[[ATTR0]] {
 657 // CHECK1-NEXT:  entry:
 658 // CHECK1-NEXT:    call void @__cxx_global_var_init()
 659 // CHECK1-NEXT:    call void @__cxx_global_var_init.1()
 660 // CHECK1-NEXT:    call void @__cxx_global_var_init.2()
 661 // CHECK1-NEXT:    ret void
 662 //
 663 //
 664 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
 665 // CHECK1-SAME: () #[[ATTR0]] {
 666 // CHECK1-NEXT:  entry:
 667 // CHECK1-NEXT:    call void @__tgt_register_requires(i64 1)
 668 // CHECK1-NEXT:    ret void
 669 //
 670 //
 671 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init
 672 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] {
 673 // CHECK3-NEXT:  entry:
 674 // CHECK3-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
 675 // CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
 676 // CHECK3-NEXT:    ret void
 677 //
 678 //
 679 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
 680 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
 681 // CHECK3-NEXT:  entry:
 682 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
 683 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
 684 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
 685 // CHECK3-NEXT:    call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
 686 // CHECK3-NEXT:    ret void
 687 //
 688 //
 689 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
 690 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
 691 // CHECK3-NEXT:  entry:
 692 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
 693 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
 694 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
 695 // CHECK3-NEXT:    call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
 696 // CHECK3-NEXT:    ret void
 697 //
 698 //
 699 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
 700 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
 701 // CHECK3-NEXT:  entry:
 702 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
 703 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
 704 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
 705 // CHECK3-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
 706 // CHECK3-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
 707 // CHECK3-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
 708 // CHECK3-NEXT:    store float [[CONV]], ptr [[F]], align 4
 709 // CHECK3-NEXT:    ret void
 710 //
 711 //
 712 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
 713 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
 714 // CHECK3-NEXT:  entry:
 715 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
 716 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
 717 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
 718 // CHECK3-NEXT:    ret void
 719 //
 720 //
 721 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
 722 // CHECK3-SAME: () #[[ATTR0]] {
 723 // CHECK3-NEXT:  entry:
 724 // CHECK3-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
 725 // CHECK3-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 1), float noundef 2.000000e+00)
 726 // CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
 727 // CHECK3-NEXT:    ret void
 728 //
 729 //
 730 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
 731 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
 732 // CHECK3-NEXT:  entry:
 733 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
 734 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
 735 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
 736 // CHECK3-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
 737 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
 738 // CHECK3-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
 739 // CHECK3-NEXT:    call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
 740 // CHECK3-NEXT:    ret void
 741 //
 742 //
 743 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
 744 // CHECK3-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {
 745 // CHECK3-NEXT:  entry:
 746 // CHECK3-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 4
 747 // CHECK3-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 4
 748 // CHECK3-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
 749 // CHECK3:       arraydestroy.body:
 750 // CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
 751 // CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
 752 // CHECK3-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
 753 // CHECK3-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr
 754 // CHECK3-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
 755 // CHECK3:       arraydestroy.done1:
 756 // CHECK3-NEXT:    ret void
 757 //
 758 //
 759 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
 760 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
 761 // CHECK3-NEXT:  entry:
 762 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
 763 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
 764 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
 765 // CHECK3-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
 766 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
 767 // CHECK3-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
 768 // CHECK3-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
 769 // CHECK3-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
 770 // CHECK3-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
 771 // CHECK3-NEXT:    [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
 772 // CHECK3-NEXT:    store float [[ADD]], ptr [[F]], align 4
 773 // CHECK3-NEXT:    ret void
 774 //
 775 //
 776 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
 777 // CHECK3-SAME: () #[[ATTR0]] {
 778 // CHECK3-NEXT:  entry:
 779 // CHECK3-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)
 780 // CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]
 781 // CHECK3-NEXT:    ret void
 782 //
 783 //
 784 // CHECK3-LABEL: define {{[^@]+}}@main
 785 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] {
 786 // CHECK3-NEXT:  entry:
 787 // CHECK3-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
 788 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 789 // CHECK3-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
 790 // CHECK3-NEXT:    store i32 0, ptr [[RETVAL]], align 4
 791 // CHECK3-NEXT:    [[TMP0:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
 792 // CHECK3-NEXT:    store i32 2, ptr [[TMP0]], align 4
 793 // CHECK3-NEXT:    [[TMP1:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
 794 // CHECK3-NEXT:    store i32 0, ptr [[TMP1]], align 4
 795 // CHECK3-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
 796 // CHECK3-NEXT:    store ptr null, ptr [[TMP2]], align 4
 797 // CHECK3-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
 798 // CHECK3-NEXT:    store ptr null, ptr [[TMP3]], align 4
 799 // CHECK3-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
 800 // CHECK3-NEXT:    store ptr null, ptr [[TMP4]], align 4
 801 // CHECK3-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
 802 // CHECK3-NEXT:    store ptr null, ptr [[TMP5]], align 4
 803 // CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
 804 // CHECK3-NEXT:    store ptr null, ptr [[TMP6]], align 4
 805 // CHECK3-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
 806 // CHECK3-NEXT:    store ptr null, ptr [[TMP7]], align 4
 807 // CHECK3-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
 808 // CHECK3-NEXT:    store i64 2, ptr [[TMP8]], align 8
 809 // CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
 810 // CHECK3-NEXT:    store i64 0, ptr [[TMP9]], align 8
 811 // CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
 812 // CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4
 813 // CHECK3-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
 814 // CHECK3-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP11]], align 4
 815 // CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
 816 // CHECK3-NEXT:    store i32 0, ptr [[TMP12]], align 4
 817 // CHECK3-NEXT:    [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2:[0-9]+]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91.region_id, ptr [[KERNEL_ARGS]])
 818 // CHECK3-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
 819 // CHECK3-NEXT:    br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
 820 // CHECK3:       omp_offload.failed:
 821 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91() #[[ATTR2]]
 822 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]
 823 // CHECK3:       omp_offload.cont:
 824 // CHECK3-NEXT:    [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()
 825 // CHECK3-NEXT:    ret i32 [[CALL]]
 826 //
 827 //
 828 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91
 829 // CHECK3-SAME: () #[[ATTR4:[0-9]+]] {
 830 // CHECK3-NEXT:  entry:
 831 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91.omp_outlined)
 832 // CHECK3-NEXT:    ret void
 833 //
 834 //
 835 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l91.omp_outlined
 836 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {
 837 // CHECK3-NEXT:  entry:
 838 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
 839 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
 840 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 841 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 842 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
 843 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
 844 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 845 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 846 // CHECK3-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
 847 // CHECK3-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
 848 // CHECK3-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
 849 // CHECK3-NEXT:    [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
 850 // CHECK3-NEXT:    [[SIVAR:%.*]] = alloca i32, align 4
 851 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
 852 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
 853 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
 854 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
 855 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
 856 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 857 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 858 // CHECK3-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
 859 // CHECK3-NEXT:    [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2
 860 // CHECK3-NEXT:    br label [[ARRAYCTOR_LOOP:%.*]]
 861 // CHECK3:       arrayctor.loop:
 862 // CHECK3-NEXT:    [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
 863 // CHECK3-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
 864 // CHECK3-NEXT:    [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i32 1
 865 // CHECK3-NEXT:    [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
 866 // CHECK3-NEXT:    br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
 867 // CHECK3:       arrayctor.cont:
 868 // CHECK3-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]])
 869 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
 870 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
 871 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
 872 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 873 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
 874 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 875 // CHECK3:       cond.true:
 876 // CHECK3-NEXT:    br label [[COND_END:%.*]]
 877 // CHECK3:       cond.false:
 878 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 879 // CHECK3-NEXT:    br label [[COND_END]]
 880 // CHECK3:       cond.end:
 881 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
 882 // CHECK3-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
 883 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
 884 // CHECK3-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
 885 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 886 // CHECK3:       omp.inner.for.cond:
 887 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]]
 888 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP6]]
 889 // CHECK3-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
 890 // CHECK3-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
 891 // CHECK3:       omp.inner.for.cond.cleanup:
 892 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
 893 // CHECK3:       omp.inner.for.body:
 894 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
 895 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
 896 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
 897 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]]
 898 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP6]]
 899 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]]
 900 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]]
 901 // CHECK3-NEXT:    store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]]
 902 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]]
 903 // CHECK3-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP10]]
 904 // CHECK3-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[VAR]], i32 4, i1 false), !llvm.access.group [[ACC_GRP6]]
 905 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]]
 906 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP6]]
 907 // CHECK3-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]]
 908 // CHECK3-NEXT:    store i32 [[ADD3]], ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP6]]
 909 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 910 // CHECK3:       omp.body.continue:
 911 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 912 // CHECK3:       omp.inner.for.inc:
 913 // CHECK3-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
 914 // CHECK3-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1
 915 // CHECK3-NEXT:    store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
 916 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
 917 // CHECK3:       omp.inner.for.end:
 918 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
 919 // CHECK3:       omp.loop.exit:
 920 // CHECK3-NEXT:    [[TMP14:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
 921 // CHECK3-NEXT:    [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4
 922 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP15]])
 923 // CHECK3-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
 924 // CHECK3-NEXT:    [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
 925 // CHECK3-NEXT:    br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
 926 // CHECK3:       .omp.final.then:
 927 // CHECK3-NEXT:    store i32 2, ptr [[I]], align 4
 928 // CHECK3-NEXT:    br label [[DOTOMP_FINAL_DONE]]
 929 // CHECK3:       .omp.final.done:
 930 // CHECK3-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
 931 // CHECK3-NEXT:    [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
 932 // CHECK3-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN5]], i32 2
 933 // CHECK3-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
 934 // CHECK3:       arraydestroy.body:
 935 // CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP18]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
 936 // CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
 937 // CHECK3-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
 938 // CHECK3-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]]
 939 // CHECK3-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]]
 940 // CHECK3:       arraydestroy.done6:
 941 // CHECK3-NEXT:    ret void
 942 //
 943 //
 944 // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
 945 // CHECK3-SAME: () #[[ATTR6:[0-9]+]] comdat {
 946 // CHECK3-NEXT:  entry:
 947 // CHECK3-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
 948 // CHECK3-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
 949 // CHECK3-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
 950 // CHECK3-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
 951 // CHECK3-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
 952 // CHECK3-NEXT:    [[VAR:%.*]] = alloca ptr, align 4
 953 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 954 // CHECK3-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 4
 955 // CHECK3-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
 956 // CHECK3-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])
 957 // CHECK3-NEXT:    store i32 0, ptr [[T_VAR]], align 4
 958 // CHECK3-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false)
 959 // CHECK3-NEXT:    [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
 960 // CHECK3-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef 1)
 961 // CHECK3-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYINIT_BEGIN]], i32 1
 962 // CHECK3-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)
 963 // CHECK3-NEXT:    store ptr [[TEST]], ptr [[VAR]], align 4
 964 // CHECK3-NEXT:    store ptr undef, ptr [[_TMP1]], align 4
 965 // CHECK3-NEXT:    [[TMP0:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
 966 // CHECK3-NEXT:    store i32 2, ptr [[TMP0]], align 4
 967 // CHECK3-NEXT:    [[TMP1:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
 968 // CHECK3-NEXT:    store i32 0, ptr [[TMP1]], align 4
 969 // CHECK3-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
 970 // CHECK3-NEXT:    store ptr null, ptr [[TMP2]], align 4
 971 // CHECK3-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
 972 // CHECK3-NEXT:    store ptr null, ptr [[TMP3]], align 4
 973 // CHECK3-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
 974 // CHECK3-NEXT:    store ptr null, ptr [[TMP4]], align 4
 975 // CHECK3-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
 976 // CHECK3-NEXT:    store ptr null, ptr [[TMP5]], align 4
 977 // CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
 978 // CHECK3-NEXT:    store ptr null, ptr [[TMP6]], align 4
 979 // CHECK3-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
 980 // CHECK3-NEXT:    store ptr null, ptr [[TMP7]], align 4
 981 // CHECK3-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
 982 // CHECK3-NEXT:    store i64 2, ptr [[TMP8]], align 8
 983 // CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
 984 // CHECK3-NEXT:    store i64 0, ptr [[TMP9]], align 8
 985 // CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
 986 // CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4
 987 // CHECK3-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
 988 // CHECK3-NEXT:    store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP11]], align 4
 989 // CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
 990 // CHECK3-NEXT:    store i32 0, ptr [[TMP12]], align 4
 991 // CHECK3-NEXT:    [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 0, i32 1, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, ptr [[KERNEL_ARGS]])
 992 // CHECK3-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
 993 // CHECK3-NEXT:    br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
 994 // CHECK3:       omp_offload.failed:
 995 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56() #[[ATTR2]]
 996 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]
 997 // CHECK3:       omp_offload.cont:
 998 // CHECK3-NEXT:    store i32 0, ptr [[RETVAL]], align 4
 999 // CHECK3-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
1000 // CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2
1001 // CHECK3-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1002 // CHECK3:       arraydestroy.body:
1003 // CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1004 // CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1005 // CHECK3-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1006 // CHECK3-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
1007 // CHECK3-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
1008 // CHECK3:       arraydestroy.done2:
1009 // CHECK3-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
1010 // CHECK3-NEXT:    [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4
1011 // CHECK3-NEXT:    ret i32 [[TMP16]]
1012 //
1013 //
1014 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
1015 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1016 // CHECK3-NEXT:  entry:
1017 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1018 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1019 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1020 // CHECK3-NEXT:    call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
1021 // CHECK3-NEXT:    ret void
1022 //
1023 //
1024 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
1025 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1026 // CHECK3-NEXT:  entry:
1027 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1028 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
1029 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1030 // CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
1031 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1032 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
1033 // CHECK3-NEXT:    call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])
1034 // CHECK3-NEXT:    ret void
1035 //
1036 //
1037 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56
1038 // CHECK3-SAME: () #[[ATTR4]] {
1039 // CHECK3-NEXT:  entry:
1040 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined)
1041 // CHECK3-NEXT:    ret void
1042 //
1043 //
1044 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined
1045 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {
1046 // CHECK3-NEXT:  entry:
1047 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
1048 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
1049 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1050 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1051 // CHECK3-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 4
1052 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1053 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1054 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1055 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1056 // CHECK3-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
1057 // CHECK3-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
1058 // CHECK3-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
1059 // CHECK3-NEXT:    [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1060 // CHECK3-NEXT:    [[_TMP2:%.*]] = alloca ptr, align 4
1061 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
1062 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
1063 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
1064 // CHECK3-NEXT:    store ptr undef, ptr [[_TMP1]], align 4
1065 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
1066 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
1067 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1068 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1069 // CHECK3-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
1070 // CHECK3-NEXT:    [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2
1071 // CHECK3-NEXT:    br label [[ARRAYCTOR_LOOP:%.*]]
1072 // CHECK3:       arrayctor.loop:
1073 // CHECK3-NEXT:    [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1074 // CHECK3-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1075 // CHECK3-NEXT:    [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i32 1
1076 // CHECK3-NEXT:    [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1077 // CHECK3-NEXT:    br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1078 // CHECK3:       arrayctor.cont:
1079 // CHECK3-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]])
1080 // CHECK3-NEXT:    store ptr [[VAR]], ptr [[_TMP2]], align 4
1081 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
1082 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
1083 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
1084 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1085 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
1086 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1087 // CHECK3:       cond.true:
1088 // CHECK3-NEXT:    br label [[COND_END:%.*]]
1089 // CHECK3:       cond.false:
1090 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1091 // CHECK3-NEXT:    br label [[COND_END]]
1092 // CHECK3:       cond.end:
1093 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
1094 // CHECK3-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
1095 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1096 // CHECK3-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
1097 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1098 // CHECK3:       omp.inner.for.cond:
1099 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12:![0-9]+]]
1100 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP12]]
1101 // CHECK3-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
1102 // CHECK3-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1103 // CHECK3:       omp.inner.for.cond.cleanup:
1104 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
1105 // CHECK3:       omp.inner.for.body:
1106 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]
1107 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
1108 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1109 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]]
1110 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP12]]
1111 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]]
1112 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]]
1113 // CHECK3-NEXT:    store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP12]]
1114 // CHECK3-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 4, !llvm.access.group [[ACC_GRP12]]
1115 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]]
1116 // CHECK3-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP11]]
1117 // CHECK3-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP10]], i32 4, i1 false), !llvm.access.group [[ACC_GRP12]]
1118 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1119 // CHECK3:       omp.body.continue:
1120 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1121 // CHECK3:       omp.inner.for.inc:
1122 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]
1123 // CHECK3-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP12]], 1
1124 // CHECK3-NEXT:    store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]
1125 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
1126 // CHECK3:       omp.inner.for.end:
1127 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1128 // CHECK3:       omp.loop.exit:
1129 // CHECK3-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
1130 // CHECK3-NEXT:    [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4
1131 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]])
1132 // CHECK3-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
1133 // CHECK3-NEXT:    [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0
1134 // CHECK3-NEXT:    br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1135 // CHECK3:       .omp.final.then:
1136 // CHECK3-NEXT:    store i32 2, ptr [[I]], align 4
1137 // CHECK3-NEXT:    br label [[DOTOMP_FINAL_DONE]]
1138 // CHECK3:       .omp.final.done:
1139 // CHECK3-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
1140 // CHECK3-NEXT:    [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
1141 // CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN6]], i32 2
1142 // CHECK3-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1143 // CHECK3:       arraydestroy.body:
1144 // CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1145 // CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1146 // CHECK3-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1147 // CHECK3-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]]
1148 // CHECK3-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]]
1149 // CHECK3:       arraydestroy.done7:
1150 // CHECK3-NEXT:    ret void
1151 //
1152 //
1153 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
1154 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1155 // CHECK3-NEXT:  entry:
1156 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1157 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1158 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1159 // CHECK3-NEXT:    call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
1160 // CHECK3-NEXT:    ret void
1161 //
1162 //
1163 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
1164 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1165 // CHECK3-NEXT:  entry:
1166 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1167 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1168 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1169 // CHECK3-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
1170 // CHECK3-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
1171 // CHECK3-NEXT:    store i32 [[TMP0]], ptr [[F]], align 4
1172 // CHECK3-NEXT:    ret void
1173 //
1174 //
1175 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
1176 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1177 // CHECK3-NEXT:  entry:
1178 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1179 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
1180 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1181 // CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
1182 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1183 // CHECK3-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
1184 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
1185 // CHECK3-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
1186 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
1187 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[F]], align 4
1188 // CHECK3-NEXT:    ret void
1189 //
1190 //
1191 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
1192 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1193 // CHECK3-NEXT:  entry:
1194 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1195 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1196 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1197 // CHECK3-NEXT:    ret void
1198 //
1199 //
1200 // CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_private_codegen.cpp
1201 // CHECK3-SAME: () #[[ATTR0]] {
1202 // CHECK3-NEXT:  entry:
1203 // CHECK3-NEXT:    call void @__cxx_global_var_init()
1204 // CHECK3-NEXT:    call void @__cxx_global_var_init.1()
1205 // CHECK3-NEXT:    call void @__cxx_global_var_init.2()
1206 // CHECK3-NEXT:    ret void
1207 //
1208 //
1209 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
1210 // CHECK3-SAME: () #[[ATTR0]] {
1211 // CHECK3-NEXT:  entry:
1212 // CHECK3-NEXT:    call void @__tgt_register_requires(i64 1)
1213 // CHECK3-NEXT:    ret void
1214 //
1215 //
1216 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init
1217 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] {
1218 // CHECK5-NEXT:  entry:
1219 // CHECK5-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
1220 // CHECK5-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
1221 // CHECK5-NEXT:    ret void
1222 //
1223 //
1224 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
1225 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
1226 // CHECK5-NEXT:  entry:
1227 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1228 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1229 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1230 // CHECK5-NEXT:    call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
1231 // CHECK5-NEXT:    ret void
1232 //
1233 //
1234 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
1235 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1236 // CHECK5-NEXT:  entry:
1237 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1238 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1239 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1240 // CHECK5-NEXT:    call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
1241 // CHECK5-NEXT:    ret void
1242 //
1243 //
1244 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
1245 // CHECK5-SAME: () #[[ATTR0]] {
1246 // CHECK5-NEXT:  entry:
1247 // CHECK5-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
1248 // CHECK5-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)
1249 // CHECK5-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
1250 // CHECK5-NEXT:    ret void
1251 //
1252 //
1253 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
1254 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1255 // CHECK5-NEXT:  entry:
1256 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1257 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
1258 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1259 // CHECK5-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
1260 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1261 // CHECK5-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
1262 // CHECK5-NEXT:    call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
1263 // CHECK5-NEXT:    ret void
1264 //
1265 //
1266 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
1267 // CHECK5-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {
1268 // CHECK5-NEXT:  entry:
1269 // CHECK5-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
1270 // CHECK5-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
1271 // CHECK5-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1272 // CHECK5:       arraydestroy.body:
1273 // CHECK5-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1274 // CHECK5-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1275 // CHECK5-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1276 // CHECK5-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr
1277 // CHECK5-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
1278 // CHECK5:       arraydestroy.done1:
1279 // CHECK5-NEXT:    ret void
1280 //
1281 //
1282 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
1283 // CHECK5-SAME: () #[[ATTR0]] {
1284 // CHECK5-NEXT:  entry:
1285 // CHECK5-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)
1286 // CHECK5-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]
1287 // CHECK5-NEXT:    ret void
1288 //
1289 //
1290 // CHECK5-LABEL: define {{[^@]+}}@main
1291 // CHECK5-SAME: () #[[ATTR3:[0-9]+]] {
1292 // CHECK5-NEXT:  entry:
1293 // CHECK5-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
1294 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1295 // CHECK5-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1296 // CHECK5-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1297 // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1298 // CHECK5-NEXT:    [[I:%.*]] = alloca i32, align 4
1299 // CHECK5-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
1300 // CHECK5-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
1301 // CHECK5-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
1302 // CHECK5-NEXT:    [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
1303 // CHECK5-NEXT:    [[SIVAR:%.*]] = alloca i32, align 4
1304 // CHECK5-NEXT:    store i32 0, ptr [[RETVAL]], align 4
1305 // CHECK5-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
1306 // CHECK5-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
1307 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1308 // CHECK5-NEXT:    store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4
1309 // CHECK5-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
1310 // CHECK5-NEXT:    [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2
1311 // CHECK5-NEXT:    br label [[ARRAYCTOR_LOOP:%.*]]
1312 // CHECK5:       arrayctor.loop:
1313 // CHECK5-NEXT:    [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1314 // CHECK5-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1315 // CHECK5-NEXT:    [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1
1316 // CHECK5-NEXT:    [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1317 // CHECK5-NEXT:    br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1318 // CHECK5:       arrayctor.cont:
1319 // CHECK5-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]])
1320 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1321 // CHECK5:       omp.inner.for.cond:
1322 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]]
1323 // CHECK5-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP2]]
1324 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
1325 // CHECK5-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1326 // CHECK5:       omp.inner.for.cond.cleanup:
1327 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
1328 // CHECK5:       omp.inner.for.body:
1329 // CHECK5-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
1330 // CHECK5-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
1331 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1332 // CHECK5-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]
1333 // CHECK5-NEXT:    [[TMP4:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP2]]
1334 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]
1335 // CHECK5-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64
1336 // CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]]
1337 // CHECK5-NEXT:    store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]]
1338 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]
1339 // CHECK5-NEXT:    [[IDXPROM1:%.*]] = sext i32 [[TMP6]] to i64
1340 // CHECK5-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM1]]
1341 // CHECK5-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[VAR]], i64 4, i1 false), !llvm.access.group [[ACC_GRP2]]
1342 // CHECK5-NEXT:    [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]
1343 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP2]]
1344 // CHECK5-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP8]], [[TMP7]]
1345 // CHECK5-NEXT:    store i32 [[ADD3]], ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP2]]
1346 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1347 // CHECK5:       omp.body.continue:
1348 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1349 // CHECK5:       omp.inner.for.inc:
1350 // CHECK5-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
1351 // CHECK5-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP9]], 1
1352 // CHECK5-NEXT:    store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
1353 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
1354 // CHECK5:       omp.inner.for.end:
1355 // CHECK5-NEXT:    store i32 2, ptr [[I]], align 4
1356 // CHECK5-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
1357 // CHECK5-NEXT:    [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
1358 // CHECK5-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN5]], i64 2
1359 // CHECK5-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1360 // CHECK5:       arraydestroy.body:
1361 // CHECK5-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP10]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1362 // CHECK5-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1363 // CHECK5-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1364 // CHECK5-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]]
1365 // CHECK5-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]]
1366 // CHECK5:       arraydestroy.done6:
1367 // CHECK5-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v()
1368 // CHECK5-NEXT:    ret i32 [[CALL]]
1369 //
1370 //
1371 // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
1372 // CHECK5-SAME: () #[[ATTR5:[0-9]+]] comdat {
1373 // CHECK5-NEXT:  entry:
1374 // CHECK5-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
1375 // CHECK5-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1376 // CHECK5-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
1377 // CHECK5-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
1378 // CHECK5-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
1379 // CHECK5-NEXT:    [[VAR:%.*]] = alloca ptr, align 8
1380 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1381 // CHECK5-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 8
1382 // CHECK5-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1383 // CHECK5-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1384 // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1385 // CHECK5-NEXT:    [[I:%.*]] = alloca i32, align 4
1386 // CHECK5-NEXT:    [[T_VAR2:%.*]] = alloca i32, align 4
1387 // CHECK5-NEXT:    [[VEC3:%.*]] = alloca [2 x i32], align 4
1388 // CHECK5-NEXT:    [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4
1389 // CHECK5-NEXT:    [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4
1390 // CHECK5-NEXT:    [[_TMP6:%.*]] = alloca ptr, align 8
1391 // CHECK5-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])
1392 // CHECK5-NEXT:    store i32 0, ptr [[T_VAR]], align 4
1393 // CHECK5-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false)
1394 // CHECK5-NEXT:    [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 0
1395 // CHECK5-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef signext 1)
1396 // CHECK5-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYINIT_BEGIN]], i64 1
1397 // CHECK5-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2)
1398 // CHECK5-NEXT:    store ptr [[TEST]], ptr [[VAR]], align 8
1399 // CHECK5-NEXT:    store ptr undef, ptr [[_TMP1]], align 8
1400 // CHECK5-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
1401 // CHECK5-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
1402 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1403 // CHECK5-NEXT:    store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4
1404 // CHECK5-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0
1405 // CHECK5-NEXT:    [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2
1406 // CHECK5-NEXT:    br label [[ARRAYCTOR_LOOP:%.*]]
1407 // CHECK5:       arrayctor.loop:
1408 // CHECK5-NEXT:    [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1409 // CHECK5-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1410 // CHECK5-NEXT:    [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i64 1
1411 // CHECK5-NEXT:    [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1412 // CHECK5-NEXT:    br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1413 // CHECK5:       arrayctor.cont:
1414 // CHECK5-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]])
1415 // CHECK5-NEXT:    store ptr [[VAR5]], ptr [[_TMP6]], align 8
1416 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1417 // CHECK5:       omp.inner.for.cond:
1418 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]]
1419 // CHECK5-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP6]]
1420 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
1421 // CHECK5-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1422 // CHECK5:       omp.inner.for.cond.cleanup:
1423 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
1424 // CHECK5:       omp.inner.for.body:
1425 // CHECK5-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
1426 // CHECK5-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
1427 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1428 // CHECK5-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]]
1429 // CHECK5-NEXT:    [[TMP4:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP6]]
1430 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]]
1431 // CHECK5-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64
1432 // CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i64 0, i64 [[IDXPROM]]
1433 // CHECK5-NEXT:    store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]]
1434 // CHECK5-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[_TMP6]], align 8, !llvm.access.group [[ACC_GRP6]]
1435 // CHECK5-NEXT:    [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]]
1436 // CHECK5-NEXT:    [[IDXPROM7:%.*]] = sext i32 [[TMP7]] to i64
1437 // CHECK5-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM7]]
1438 // CHECK5-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP6]], i64 4, i1 false), !llvm.access.group [[ACC_GRP6]]
1439 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1440 // CHECK5:       omp.body.continue:
1441 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1442 // CHECK5:       omp.inner.for.inc:
1443 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
1444 // CHECK5-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP8]], 1
1445 // CHECK5-NEXT:    store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
1446 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
1447 // CHECK5:       omp.inner.for.end:
1448 // CHECK5-NEXT:    store i32 2, ptr [[I]], align 4
1449 // CHECK5-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]
1450 // CHECK5-NEXT:    [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0
1451 // CHECK5-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN10]], i64 2
1452 // CHECK5-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1453 // CHECK5:       arraydestroy.body:
1454 // CHECK5-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP9]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1455 // CHECK5-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1456 // CHECK5-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1457 // CHECK5-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]]
1458 // CHECK5-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]]
1459 // CHECK5:       arraydestroy.done11:
1460 // CHECK5-NEXT:    store i32 0, ptr [[RETVAL]], align 4
1461 // CHECK5-NEXT:    [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
1462 // CHECK5-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i64 2
1463 // CHECK5-NEXT:    br label [[ARRAYDESTROY_BODY13:%.*]]
1464 // CHECK5:       arraydestroy.body13:
1465 // CHECK5-NEXT:    [[ARRAYDESTROY_ELEMENTPAST14:%.*]] = phi ptr [ [[TMP10]], [[ARRAYDESTROY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT15:%.*]], [[ARRAYDESTROY_BODY13]] ]
1466 // CHECK5-NEXT:    [[ARRAYDESTROY_ELEMENT15]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST14]], i64 -1
1467 // CHECK5-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR2]]
1468 // CHECK5-NEXT:    [[ARRAYDESTROY_DONE16:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT15]], [[ARRAY_BEGIN12]]
1469 // CHECK5-NEXT:    br i1 [[ARRAYDESTROY_DONE16]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY13]]
1470 // CHECK5:       arraydestroy.done17:
1471 // CHECK5-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
1472 // CHECK5-NEXT:    [[TMP11:%.*]] = load i32, ptr [[RETVAL]], align 4
1473 // CHECK5-NEXT:    ret i32 [[TMP11]]
1474 //
1475 //
1476 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
1477 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1478 // CHECK5-NEXT:  entry:
1479 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1480 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1481 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1482 // CHECK5-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
1483 // CHECK5-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
1484 // CHECK5-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
1485 // CHECK5-NEXT:    store float [[CONV]], ptr [[F]], align 4
1486 // CHECK5-NEXT:    ret void
1487 //
1488 //
1489 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
1490 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1491 // CHECK5-NEXT:  entry:
1492 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1493 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1494 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1495 // CHECK5-NEXT:    ret void
1496 //
1497 //
1498 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
1499 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1500 // CHECK5-NEXT:  entry:
1501 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1502 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
1503 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1504 // CHECK5-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
1505 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1506 // CHECK5-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
1507 // CHECK5-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
1508 // CHECK5-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
1509 // CHECK5-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
1510 // CHECK5-NEXT:    [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
1511 // CHECK5-NEXT:    store float [[ADD]], ptr [[F]], align 4
1512 // CHECK5-NEXT:    ret void
1513 //
1514 //
1515 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
1516 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1517 // CHECK5-NEXT:  entry:
1518 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1519 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1520 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1521 // CHECK5-NEXT:    call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
1522 // CHECK5-NEXT:    ret void
1523 //
1524 //
1525 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
1526 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1527 // CHECK5-NEXT:  entry:
1528 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1529 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
1530 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1531 // CHECK5-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
1532 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1533 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
1534 // CHECK5-NEXT:    call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
1535 // CHECK5-NEXT:    ret void
1536 //
1537 //
1538 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
1539 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1540 // CHECK5-NEXT:  entry:
1541 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1542 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1543 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1544 // CHECK5-NEXT:    call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
1545 // CHECK5-NEXT:    ret void
1546 //
1547 //
1548 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
1549 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1550 // CHECK5-NEXT:  entry:
1551 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1552 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1553 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1554 // CHECK5-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
1555 // CHECK5-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
1556 // CHECK5-NEXT:    store i32 [[TMP0]], ptr [[F]], align 4
1557 // CHECK5-NEXT:    ret void
1558 //
1559 //
1560 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
1561 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1562 // CHECK5-NEXT:  entry:
1563 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1564 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
1565 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1566 // CHECK5-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
1567 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1568 // CHECK5-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
1569 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
1570 // CHECK5-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
1571 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
1572 // CHECK5-NEXT:    store i32 [[ADD]], ptr [[F]], align 4
1573 // CHECK5-NEXT:    ret void
1574 //
1575 //
1576 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
1577 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1578 // CHECK5-NEXT:  entry:
1579 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1580 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1581 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1582 // CHECK5-NEXT:    ret void
1583 //
1584 //
1585 // CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_private_codegen.cpp
1586 // CHECK5-SAME: () #[[ATTR0]] {
1587 // CHECK5-NEXT:  entry:
1588 // CHECK5-NEXT:    call void @__cxx_global_var_init()
1589 // CHECK5-NEXT:    call void @__cxx_global_var_init.1()
1590 // CHECK5-NEXT:    call void @__cxx_global_var_init.2()
1591 // CHECK5-NEXT:    ret void
1592 //
1593 //
1594 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init
1595 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] {
1596 // CHECK7-NEXT:  entry:
1597 // CHECK7-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
1598 // CHECK7-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
1599 // CHECK7-NEXT:    ret void
1600 //
1601 //
1602 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
1603 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
1604 // CHECK7-NEXT:  entry:
1605 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1606 // CHECK7-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1607 // CHECK7-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1608 // CHECK7-NEXT:    call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
1609 // CHECK7-NEXT:    ret void
1610 //
1611 //
1612 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
1613 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1614 // CHECK7-NEXT:  entry:
1615 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1616 // CHECK7-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1617 // CHECK7-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1618 // CHECK7-NEXT:    call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
1619 // CHECK7-NEXT:    ret void
1620 //
1621 //
1622 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
1623 // CHECK7-SAME: () #[[ATTR0]] {
1624 // CHECK7-NEXT:  entry:
1625 // CHECK7-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
1626 // CHECK7-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 1), float noundef 2.000000e+00)
1627 // CHECK7-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
1628 // CHECK7-NEXT:    ret void
1629 //
1630 //
1631 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
1632 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1633 // CHECK7-NEXT:  entry:
1634 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1635 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
1636 // CHECK7-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1637 // CHECK7-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
1638 // CHECK7-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1639 // CHECK7-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
1640 // CHECK7-NEXT:    call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
1641 // CHECK7-NEXT:    ret void
1642 //
1643 //
1644 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
1645 // CHECK7-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {
1646 // CHECK7-NEXT:  entry:
1647 // CHECK7-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 4
1648 // CHECK7-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 4
1649 // CHECK7-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1650 // CHECK7:       arraydestroy.body:
1651 // CHECK7-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1652 // CHECK7-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1653 // CHECK7-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1654 // CHECK7-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr
1655 // CHECK7-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
1656 // CHECK7:       arraydestroy.done1:
1657 // CHECK7-NEXT:    ret void
1658 //
1659 //
1660 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
1661 // CHECK7-SAME: () #[[ATTR0]] {
1662 // CHECK7-NEXT:  entry:
1663 // CHECK7-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)
1664 // CHECK7-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]
1665 // CHECK7-NEXT:    ret void
1666 //
1667 //
1668 // CHECK7-LABEL: define {{[^@]+}}@main
1669 // CHECK7-SAME: () #[[ATTR3:[0-9]+]] {
1670 // CHECK7-NEXT:  entry:
1671 // CHECK7-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
1672 // CHECK7-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1673 // CHECK7-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1674 // CHECK7-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1675 // CHECK7-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1676 // CHECK7-NEXT:    [[I:%.*]] = alloca i32, align 4
1677 // CHECK7-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
1678 // CHECK7-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
1679 // CHECK7-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
1680 // CHECK7-NEXT:    [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
1681 // CHECK7-NEXT:    [[SIVAR:%.*]] = alloca i32, align 4
1682 // CHECK7-NEXT:    store i32 0, ptr [[RETVAL]], align 4
1683 // CHECK7-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
1684 // CHECK7-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
1685 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1686 // CHECK7-NEXT:    store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4
1687 // CHECK7-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
1688 // CHECK7-NEXT:    [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2
1689 // CHECK7-NEXT:    br label [[ARRAYCTOR_LOOP:%.*]]
1690 // CHECK7:       arrayctor.loop:
1691 // CHECK7-NEXT:    [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1692 // CHECK7-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1693 // CHECK7-NEXT:    [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i32 1
1694 // CHECK7-NEXT:    [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1695 // CHECK7-NEXT:    br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1696 // CHECK7:       arrayctor.cont:
1697 // CHECK7-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]])
1698 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1699 // CHECK7:       omp.inner.for.cond:
1700 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3:![0-9]+]]
1701 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP3]]
1702 // CHECK7-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
1703 // CHECK7-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1704 // CHECK7:       omp.inner.for.cond.cleanup:
1705 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
1706 // CHECK7:       omp.inner.for.body:
1707 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]
1708 // CHECK7-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
1709 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1710 // CHECK7-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]]
1711 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP3]]
1712 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]]
1713 // CHECK7-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP5]]
1714 // CHECK7-NEXT:    store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]]
1715 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]]
1716 // CHECK7-NEXT:    [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP6]]
1717 // CHECK7-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX1]], ptr align 4 [[VAR]], i32 4, i1 false), !llvm.access.group [[ACC_GRP3]]
1718 // CHECK7-NEXT:    [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]]
1719 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP3]]
1720 // CHECK7-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], [[TMP7]]
1721 // CHECK7-NEXT:    store i32 [[ADD2]], ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP3]]
1722 // CHECK7-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1723 // CHECK7:       omp.body.continue:
1724 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1725 // CHECK7:       omp.inner.for.inc:
1726 // CHECK7-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]
1727 // CHECK7-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
1728 // CHECK7-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]
1729 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
1730 // CHECK7:       omp.inner.for.end:
1731 // CHECK7-NEXT:    store i32 2, ptr [[I]], align 4
1732 // CHECK7-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
1733 // CHECK7-NEXT:    [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
1734 // CHECK7-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN4]], i32 2
1735 // CHECK7-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1736 // CHECK7:       arraydestroy.body:
1737 // CHECK7-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP10]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1738 // CHECK7-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1739 // CHECK7-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1740 // CHECK7-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]]
1741 // CHECK7-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]]
1742 // CHECK7:       arraydestroy.done5:
1743 // CHECK7-NEXT:    [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()
1744 // CHECK7-NEXT:    ret i32 [[CALL]]
1745 //
1746 //
1747 // CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
1748 // CHECK7-SAME: () #[[ATTR5:[0-9]+]] comdat {
1749 // CHECK7-NEXT:  entry:
1750 // CHECK7-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
1751 // CHECK7-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1752 // CHECK7-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
1753 // CHECK7-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
1754 // CHECK7-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
1755 // CHECK7-NEXT:    [[VAR:%.*]] = alloca ptr, align 4
1756 // CHECK7-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1757 // CHECK7-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 4
1758 // CHECK7-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1759 // CHECK7-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1760 // CHECK7-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1761 // CHECK7-NEXT:    [[I:%.*]] = alloca i32, align 4
1762 // CHECK7-NEXT:    [[T_VAR2:%.*]] = alloca i32, align 4
1763 // CHECK7-NEXT:    [[VEC3:%.*]] = alloca [2 x i32], align 4
1764 // CHECK7-NEXT:    [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4
1765 // CHECK7-NEXT:    [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4
1766 // CHECK7-NEXT:    [[_TMP6:%.*]] = alloca ptr, align 4
1767 // CHECK7-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])
1768 // CHECK7-NEXT:    store i32 0, ptr [[T_VAR]], align 4
1769 // CHECK7-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false)
1770 // CHECK7-NEXT:    [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
1771 // CHECK7-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef 1)
1772 // CHECK7-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYINIT_BEGIN]], i32 1
1773 // CHECK7-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)
1774 // CHECK7-NEXT:    store ptr [[TEST]], ptr [[VAR]], align 4
1775 // CHECK7-NEXT:    store ptr undef, ptr [[_TMP1]], align 4
1776 // CHECK7-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
1777 // CHECK7-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
1778 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1779 // CHECK7-NEXT:    store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4
1780 // CHECK7-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0
1781 // CHECK7-NEXT:    [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2
1782 // CHECK7-NEXT:    br label [[ARRAYCTOR_LOOP:%.*]]
1783 // CHECK7:       arrayctor.loop:
1784 // CHECK7-NEXT:    [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1785 // CHECK7-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1786 // CHECK7-NEXT:    [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i32 1
1787 // CHECK7-NEXT:    [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1788 // CHECK7-NEXT:    br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1789 // CHECK7:       arrayctor.cont:
1790 // CHECK7-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]])
1791 // CHECK7-NEXT:    store ptr [[VAR5]], ptr [[_TMP6]], align 4
1792 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1793 // CHECK7:       omp.inner.for.cond:
1794 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7:![0-9]+]]
1795 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP7]]
1796 // CHECK7-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
1797 // CHECK7-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1798 // CHECK7:       omp.inner.for.cond.cleanup:
1799 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
1800 // CHECK7:       omp.inner.for.body:
1801 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]]
1802 // CHECK7-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
1803 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1804 // CHECK7-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]]
1805 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP7]]
1806 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]]
1807 // CHECK7-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i32 0, i32 [[TMP5]]
1808 // CHECK7-NEXT:    store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP7]]
1809 // CHECK7-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[_TMP6]], align 4, !llvm.access.group [[ACC_GRP7]]
1810 // CHECK7-NEXT:    [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]]
1811 // CHECK7-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 [[TMP7]]
1812 // CHECK7-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[TMP6]], i32 4, i1 false), !llvm.access.group [[ACC_GRP7]]
1813 // CHECK7-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1814 // CHECK7:       omp.body.continue:
1815 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1816 // CHECK7:       omp.inner.for.inc:
1817 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]]
1818 // CHECK7-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP8]], 1
1819 // CHECK7-NEXT:    store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]]
1820 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
1821 // CHECK7:       omp.inner.for.end:
1822 // CHECK7-NEXT:    store i32 2, ptr [[I]], align 4
1823 // CHECK7-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]
1824 // CHECK7-NEXT:    [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0
1825 // CHECK7-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN9]], i32 2
1826 // CHECK7-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1827 // CHECK7:       arraydestroy.body:
1828 // CHECK7-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP9]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1829 // CHECK7-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1830 // CHECK7-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1831 // CHECK7-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]]
1832 // CHECK7-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]]
1833 // CHECK7:       arraydestroy.done10:
1834 // CHECK7-NEXT:    store i32 0, ptr [[RETVAL]], align 4
1835 // CHECK7-NEXT:    [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
1836 // CHECK7-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN11]], i32 2
1837 // CHECK7-NEXT:    br label [[ARRAYDESTROY_BODY12:%.*]]
1838 // CHECK7:       arraydestroy.body12:
1839 // CHECK7-NEXT:    [[ARRAYDESTROY_ELEMENTPAST13:%.*]] = phi ptr [ [[TMP10]], [[ARRAYDESTROY_DONE10]] ], [ [[ARRAYDESTROY_ELEMENT14:%.*]], [[ARRAYDESTROY_BODY12]] ]
1840 // CHECK7-NEXT:    [[ARRAYDESTROY_ELEMENT14]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST13]], i32 -1
1841 // CHECK7-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT14]]) #[[ATTR2]]
1842 // CHECK7-NEXT:    [[ARRAYDESTROY_DONE15:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT14]], [[ARRAY_BEGIN11]]
1843 // CHECK7-NEXT:    br i1 [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY12]]
1844 // CHECK7:       arraydestroy.done16:
1845 // CHECK7-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
1846 // CHECK7-NEXT:    [[TMP11:%.*]] = load i32, ptr [[RETVAL]], align 4
1847 // CHECK7-NEXT:    ret i32 [[TMP11]]
1848 //
1849 //
1850 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
1851 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1852 // CHECK7-NEXT:  entry:
1853 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1854 // CHECK7-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1855 // CHECK7-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1856 // CHECK7-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
1857 // CHECK7-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
1858 // CHECK7-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
1859 // CHECK7-NEXT:    store float [[CONV]], ptr [[F]], align 4
1860 // CHECK7-NEXT:    ret void
1861 //
1862 //
1863 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
1864 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1865 // CHECK7-NEXT:  entry:
1866 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1867 // CHECK7-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1868 // CHECK7-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1869 // CHECK7-NEXT:    ret void
1870 //
1871 //
1872 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
1873 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1874 // CHECK7-NEXT:  entry:
1875 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1876 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
1877 // CHECK7-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1878 // CHECK7-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
1879 // CHECK7-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1880 // CHECK7-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
1881 // CHECK7-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
1882 // CHECK7-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
1883 // CHECK7-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
1884 // CHECK7-NEXT:    [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
1885 // CHECK7-NEXT:    store float [[ADD]], ptr [[F]], align 4
1886 // CHECK7-NEXT:    ret void
1887 //
1888 //
1889 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
1890 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1891 // CHECK7-NEXT:  entry:
1892 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1893 // CHECK7-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1894 // CHECK7-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1895 // CHECK7-NEXT:    call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
1896 // CHECK7-NEXT:    ret void
1897 //
1898 //
1899 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
1900 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1901 // CHECK7-NEXT:  entry:
1902 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1903 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
1904 // CHECK7-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1905 // CHECK7-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
1906 // CHECK7-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1907 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
1908 // CHECK7-NEXT:    call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])
1909 // CHECK7-NEXT:    ret void
1910 //
1911 //
1912 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
1913 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1914 // CHECK7-NEXT:  entry:
1915 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1916 // CHECK7-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1917 // CHECK7-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1918 // CHECK7-NEXT:    call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
1919 // CHECK7-NEXT:    ret void
1920 //
1921 //
1922 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
1923 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1924 // CHECK7-NEXT:  entry:
1925 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1926 // CHECK7-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1927 // CHECK7-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1928 // CHECK7-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
1929 // CHECK7-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
1930 // CHECK7-NEXT:    store i32 [[TMP0]], ptr [[F]], align 4
1931 // CHECK7-NEXT:    ret void
1932 //
1933 //
1934 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
1935 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1936 // CHECK7-NEXT:  entry:
1937 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1938 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
1939 // CHECK7-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1940 // CHECK7-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
1941 // CHECK7-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1942 // CHECK7-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
1943 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
1944 // CHECK7-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
1945 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
1946 // CHECK7-NEXT:    store i32 [[ADD]], ptr [[F]], align 4
1947 // CHECK7-NEXT:    ret void
1948 //
1949 //
1950 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
1951 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1952 // CHECK7-NEXT:  entry:
1953 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1954 // CHECK7-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1955 // CHECK7-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1956 // CHECK7-NEXT:    ret void
1957 //
1958 //
1959 // CHECK7-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_private_codegen.cpp
1960 // CHECK7-SAME: () #[[ATTR0]] {
1961 // CHECK7-NEXT:  entry:
1962 // CHECK7-NEXT:    call void @__cxx_global_var_init()
1963 // CHECK7-NEXT:    call void @__cxx_global_var_init.1()
1964 // CHECK7-NEXT:    call void @__cxx_global_var_init.2()
1965 // CHECK7-NEXT:    ret void
1966 //
1967 //
1968 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init
1969 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] {
1970 // CHECK9-NEXT:  entry:
1971 // CHECK9-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
1972 // CHECK9-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
1973 // CHECK9-NEXT:    ret void
1974 //
1975 //
1976 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
1977 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
1978 // CHECK9-NEXT:  entry:
1979 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1980 // CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1981 // CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1982 // CHECK9-NEXT:    call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
1983 // CHECK9-NEXT:    ret void
1984 //
1985 //
1986 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
1987 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1988 // CHECK9-NEXT:  entry:
1989 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1990 // CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1991 // CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1992 // CHECK9-NEXT:    call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
1993 // CHECK9-NEXT:    ret void
1994 //
1995 //
1996 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
1997 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1998 // CHECK9-NEXT:  entry:
1999 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2000 // CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2001 // CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2002 // CHECK9-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
2003 // CHECK9-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
2004 // CHECK9-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
2005 // CHECK9-NEXT:    store float [[CONV]], ptr [[F]], align 4
2006 // CHECK9-NEXT:    ret void
2007 //
2008 //
2009 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
2010 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
2011 // CHECK9-NEXT:  entry:
2012 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2013 // CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2014 // CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2015 // CHECK9-NEXT:    ret void
2016 //
2017 //
2018 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
2019 // CHECK9-SAME: () #[[ATTR0]] {
2020 // CHECK9-NEXT:  entry:
2021 // CHECK9-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
2022 // CHECK9-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)
2023 // CHECK9-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
2024 // CHECK9-NEXT:    ret void
2025 //
2026 //
2027 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
2028 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
2029 // CHECK9-NEXT:  entry:
2030 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2031 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
2032 // CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2033 // CHECK9-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
2034 // CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2035 // CHECK9-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
2036 // CHECK9-NEXT:    call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
2037 // CHECK9-NEXT:    ret void
2038 //
2039 //
2040 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
2041 // CHECK9-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {
2042 // CHECK9-NEXT:  entry:
2043 // CHECK9-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
2044 // CHECK9-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
2045 // CHECK9-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
2046 // CHECK9:       arraydestroy.body:
2047 // CHECK9-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2048 // CHECK9-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
2049 // CHECK9-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2050 // CHECK9-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr
2051 // CHECK9-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
2052 // CHECK9:       arraydestroy.done1:
2053 // CHECK9-NEXT:    ret void
2054 //
2055 //
2056 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
2057 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
2058 // CHECK9-NEXT:  entry:
2059 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2060 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
2061 // CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2062 // CHECK9-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
2063 // CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2064 // CHECK9-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
2065 // CHECK9-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
2066 // CHECK9-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
2067 // CHECK9-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
2068 // CHECK9-NEXT:    [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
2069 // CHECK9-NEXT:    store float [[ADD]], ptr [[F]], align 4
2070 // CHECK9-NEXT:    ret void
2071 //
2072 //
2073 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
2074 // CHECK9-SAME: () #[[ATTR0]] {
2075 // CHECK9-NEXT:  entry:
2076 // CHECK9-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)
2077 // CHECK9-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]
2078 // CHECK9-NEXT:    ret void
2079 //
2080 //
2081 // CHECK9-LABEL: define {{[^@]+}}@main
2082 // CHECK9-SAME: () #[[ATTR3:[0-9]+]] {
2083 // CHECK9-NEXT:  entry:
2084 // CHECK9-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
2085 // CHECK9-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
2086 // CHECK9-NEXT:    store i32 0, ptr [[RETVAL]], align 4
2087 // CHECK9-NEXT:    call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])
2088 // CHECK9-NEXT:    ret i32 0
2089 //
2090 //
2091 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74
2092 // CHECK9-SAME: () #[[ATTR5:[0-9]+]] {
2093 // CHECK9-NEXT:  entry:
2094 // CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74.omp_outlined)
2095 // CHECK9-NEXT:    ret void
2096 //
2097 //
2098 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l74.omp_outlined
2099 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] {
2100 // CHECK9-NEXT:  entry:
2101 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
2102 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
2103 // CHECK9-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2104 // CHECK9-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2105 // CHECK9-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 8
2106 // CHECK9-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2107 // CHECK9-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2108 // CHECK9-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2109 // CHECK9-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2110 // CHECK9-NEXT:    [[G:%.*]] = alloca i32, align 4
2111 // CHECK9-NEXT:    [[G1:%.*]] = alloca i32, align 4
2112 // CHECK9-NEXT:    [[_TMP2:%.*]] = alloca ptr, align 8
2113 // CHECK9-NEXT:    [[SIVAR:%.*]] = alloca i32, align 4
2114 // CHECK9-NEXT:    [[I:%.*]] = alloca i32, align 4
2115 // CHECK9-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8
2116 // CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
2117 // CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
2118 // CHECK9-NEXT:    store ptr undef, ptr [[_TMP1]], align 8
2119 // CHECK9-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
2120 // CHECK9-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
2121 // CHECK9-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
2122 // CHECK9-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2123 // CHECK9-NEXT:    store ptr [[G1]], ptr [[_TMP2]], align 8
2124 // CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
2125 // CHECK9-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
2126 // CHECK9-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
2127 // CHECK9-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2128 // CHECK9-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
2129 // CHECK9-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2130 // CHECK9:       cond.true:
2131 // CHECK9-NEXT:    br label [[COND_END:%.*]]
2132 // CHECK9:       cond.false:
2133 // CHECK9-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2134 // CHECK9-NEXT:    br label [[COND_END]]
2135 // CHECK9:       cond.end:
2136 // CHECK9-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
2137 // CHECK9-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
2138 // CHECK9-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
2139 // CHECK9-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
2140 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2141 // CHECK9:       omp.inner.for.cond:
2142 // CHECK9-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4:![0-9]+]]
2143 // CHECK9-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP4]]
2144 // CHECK9-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
2145 // CHECK9-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2146 // CHECK9:       omp.inner.for.body:
2147 // CHECK9-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]]
2148 // CHECK9-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
2149 // CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2150 // CHECK9-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP4]]
2151 // CHECK9-NEXT:    store i32 1, ptr [[G]], align 4, !llvm.access.group [[ACC_GRP4]]
2152 // CHECK9-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8, !llvm.access.group [[ACC_GRP4]]
2153 // CHECK9-NEXT:    store volatile i32 1, ptr [[TMP8]], align 4, !llvm.access.group [[ACC_GRP4]]
2154 // CHECK9-NEXT:    store i32 2, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP4]]
2155 // CHECK9-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0
2156 // CHECK9-NEXT:    store ptr [[G]], ptr [[TMP9]], align 8, !llvm.access.group [[ACC_GRP4]]
2157 // CHECK9-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1
2158 // CHECK9-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[_TMP2]], align 8, !llvm.access.group [[ACC_GRP4]]
2159 // CHECK9-NEXT:    store ptr [[TMP11]], ptr [[TMP10]], align 8, !llvm.access.group [[ACC_GRP4]]
2160 // CHECK9-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2
2161 // CHECK9-NEXT:    store ptr [[SIVAR]], ptr [[TMP12]], align 8, !llvm.access.group [[ACC_GRP4]]
2162 // CHECK9-NEXT:    call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]), !llvm.access.group [[ACC_GRP4]]
2163 // CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2164 // CHECK9:       omp.body.continue:
2165 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2166 // CHECK9:       omp.inner.for.inc:
2167 // CHECK9-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]]
2168 // CHECK9-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP13]], 1
2169 // CHECK9-NEXT:    store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]]
2170 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
2171 // CHECK9:       omp.inner.for.end:
2172 // CHECK9-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2173 // CHECK9:       omp.loop.exit:
2174 // CHECK9-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
2175 // CHECK9-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
2176 // CHECK9-NEXT:    [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0
2177 // CHECK9-NEXT:    br i1 [[TMP15]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2178 // CHECK9:       .omp.final.then:
2179 // CHECK9-NEXT:    store i32 2, ptr [[I]], align 4
2180 // CHECK9-NEXT:    br label [[DOTOMP_FINAL_DONE]]
2181 // CHECK9:       .omp.final.done:
2182 // CHECK9-NEXT:    ret void
2183 //
2184 //
2185 // CHECK9-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_private_codegen.cpp
2186 // CHECK9-SAME: () #[[ATTR0]] {
2187 // CHECK9-NEXT:  entry:
2188 // CHECK9-NEXT:    call void @__cxx_global_var_init()
2189 // CHECK9-NEXT:    call void @__cxx_global_var_init.1()
2190 // CHECK9-NEXT:    call void @__cxx_global_var_init.2()
2191 // CHECK9-NEXT:    ret void
2192 //
2193 //
2194 // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
2195 // CHECK9-SAME: () #[[ATTR0]] {
2196 // CHECK9-NEXT:  entry:
2197 // CHECK9-NEXT:    call void @__tgt_register_requires(i64 1)
2198 // CHECK9-NEXT:    ret void
2199 //
2200 //
2201 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init
2202 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] {
2203 // CHECK11-NEXT:  entry:
2204 // CHECK11-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
2205 // CHECK11-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
2206 // CHECK11-NEXT:    ret void
2207 //
2208 //
2209 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
2210 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
2211 // CHECK11-NEXT:  entry:
2212 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2213 // CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2214 // CHECK11-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2215 // CHECK11-NEXT:    call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
2216 // CHECK11-NEXT:    ret void
2217 //
2218 //
2219 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
2220 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
2221 // CHECK11-NEXT:  entry:
2222 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2223 // CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2224 // CHECK11-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2225 // CHECK11-NEXT:    call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
2226 // CHECK11-NEXT:    ret void
2227 //
2228 //
2229 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
2230 // CHECK11-SAME: () #[[ATTR0]] {
2231 // CHECK11-NEXT:  entry:
2232 // CHECK11-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
2233 // CHECK11-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)
2234 // CHECK11-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
2235 // CHECK11-NEXT:    ret void
2236 //
2237 //
2238 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
2239 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
2240 // CHECK11-NEXT:  entry:
2241 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2242 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
2243 // CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2244 // CHECK11-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
2245 // CHECK11-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2246 // CHECK11-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
2247 // CHECK11-NEXT:    call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
2248 // CHECK11-NEXT:    ret void
2249 //
2250 //
2251 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
2252 // CHECK11-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {
2253 // CHECK11-NEXT:  entry:
2254 // CHECK11-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
2255 // CHECK11-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
2256 // CHECK11-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
2257 // CHECK11:       arraydestroy.body:
2258 // CHECK11-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2259 // CHECK11-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
2260 // CHECK11-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2261 // CHECK11-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr
2262 // CHECK11-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
2263 // CHECK11:       arraydestroy.done1:
2264 // CHECK11-NEXT:    ret void
2265 //
2266 //
2267 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
2268 // CHECK11-SAME: () #[[ATTR0]] {
2269 // CHECK11-NEXT:  entry:
2270 // CHECK11-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)
2271 // CHECK11-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]
2272 // CHECK11-NEXT:    ret void
2273 //
2274 //
2275 // CHECK11-LABEL: define {{[^@]+}}@main
2276 // CHECK11-SAME: () #[[ATTR3:[0-9]+]] {
2277 // CHECK11-NEXT:  entry:
2278 // CHECK11-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
2279 // CHECK11-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
2280 // CHECK11-NEXT:    store i32 0, ptr [[RETVAL]], align 4
2281 // CHECK11-NEXT:    call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])
2282 // CHECK11-NEXT:    ret i32 0
2283 //
2284 //
2285 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
2286 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
2287 // CHECK11-NEXT:  entry:
2288 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2289 // CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2290 // CHECK11-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2291 // CHECK11-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
2292 // CHECK11-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
2293 // CHECK11-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
2294 // CHECK11-NEXT:    store float [[CONV]], ptr [[F]], align 4
2295 // CHECK11-NEXT:    ret void
2296 //
2297 //
2298 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
2299 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
2300 // CHECK11-NEXT:  entry:
2301 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2302 // CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2303 // CHECK11-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2304 // CHECK11-NEXT:    ret void
2305 //
2306 //
2307 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
2308 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
2309 // CHECK11-NEXT:  entry:
2310 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2311 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
2312 // CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2313 // CHECK11-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
2314 // CHECK11-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2315 // CHECK11-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
2316 // CHECK11-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
2317 // CHECK11-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
2318 // CHECK11-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
2319 // CHECK11-NEXT:    [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
2320 // CHECK11-NEXT:    store float [[ADD]], ptr [[F]], align 4
2321 // CHECK11-NEXT:    ret void
2322 //
2323 //
2324 // CHECK11-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_distribute_simd_private_codegen.cpp
2325 // CHECK11-SAME: () #[[ATTR0]] {
2326 // CHECK11-NEXT:  entry:
2327 // CHECK11-NEXT:    call void @__cxx_global_var_init()
2328 // CHECK11-NEXT:    call void @__cxx_global_var_init.1()
2329 // CHECK11-NEXT:    call void @__cxx_global_var_init.2()
2330 // CHECK11-NEXT:    ret void
2331 //