clang/test/OpenMP/target_teams_generic_loop_private_codegen.cpp

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
   2 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK1
   3 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
   4 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK1
   5 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK3
   6 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
   7 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK3
   8
   9 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK5
  10 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
  11 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++  -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK5
  12
  13 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  14 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
  15 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  16 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  17 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
  18 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  19
  20 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  21 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
  22 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++  -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  23
  24 // Test target codegen - host bc file has to be created first. (no significant differences with host version of target region)
  25 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
  26 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK13
  27 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
  28 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK13
  29 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
  30 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK15
  31 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
  32 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK15
  33
  34 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
  35 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK17
  36
  37 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
  38 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  39 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
  40 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  41 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
  42 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  43 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
  44 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  45 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
  46 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
  47
  48 // expected-no-diagnostics
  49 #ifndef HEADER
  50 #define HEADER
  51
  52 struct St {
  53   int a, b;
  54   St() : a(0), b(0) {}
  55   St(const St &st) : a(st.a + st.b), b(0) {}
  56   ~St() {}
  57 };
  58
  59 volatile int g = 1212;
  60 volatile int &g1 = g;
  61
  62 template <class T>
  63 struct S {
  64   T f;
  65   S(T a) : f(a + g) {}
  66   S() : f(g) {}
  67   S(const S &s, St t = St()) : f(s.f + t.a) {}
  68   operator T() { return T(); }
  69   ~S() {}
  70 };
  71
  72
  73 template <typename T>
  74 T tmain() {
  75   S<T> test;
  76   T t_var = T();
  77   T vec[] = {1, 2};
  78   S<T> s_arr[] = {1, 2};
  79   S<T> &var = test;
  80 #pragma omp target teams loop private(t_var, vec, s_arr, var)
  81   for (int i = 0; i < 2; ++i) {
  82     vec[i] = t_var;
  83     s_arr[i] = var;
  84   }
  85   return T();
  86 }
  87
  88 // HCHECK-DAG: [[TEST:@.+]] ={{.*}} global [[S_FLOAT_TY]] zeroinitializer,
  89 S<float> test;
  90 // HCHECK-DAG: [[T_VAR:@.+]] ={{.+}} global i{{[0-9]+}} 333,
  91 int t_var = 333;
  92 // HCHECK-DAG: [[VEC:@.+]] ={{.+}} global [2 x i{{[0-9]+}}] [i{{[0-9]+}} 1, i{{[0-9]+}} 2],
  93 int vec[] = {1, 2};
  94 // HCHECK-DAG: [[S_ARR:@.+]] ={{.+}} global [2 x [[S_FLOAT_TY]]] zeroinitializer,
  95 S<float> s_arr[] = {1, 2};
  96 // HCHECK-DAG: [[VAR:@.+]] ={{.+}} global [[S_FLOAT_TY]] zeroinitializer,
  97 S<float> var(3);
  98 // HCHECK-DAG: [[SIVAR:@.+]] = internal global i{{[0-9]+}} 0,
  99
 100 int main() {
 101   static int sivar;
 102 #ifdef LAMBDA
 103   [&]() {
 104 #pragma omp target teams loop private(g, g1, sivar)
 105   for (int i = 0; i < 2; ++i) {
 106
 107     // Skip global, bound tid and loop vars
 108
 109     g = 1;
 110     g1 = 1;
 111     sivar = 2;
 112
 113     // Skip global, bound tid and loop vars
 114     [&]() {
 115       g = 2;
 116       g1 = 2;
 117       sivar = 4;
 118
 119     }();
 120   }
 121   }();
 122   return 0;
 123 #else
 124 #pragma omp target teams loop private(t_var, vec, s_arr, var, sivar)
 125   for (int i = 0; i < 2; ++i) {
 126     vec[i] = t_var;
 127     s_arr[i] = var;
 128     sivar += i;
 129   }
 130   return tmain<int>();
 131 #endif
 132 }
 133
 134 // HCHECK: define {{.*}}i{{[0-9]+}} @main()
 135 // HCHECK: call i32 @__tgt_target_teams_mapper(ptr @{{.+}}, i64 -1, ptr @{{[^,]+}}, i32 0, ptr null, ptr null, {{.+}} null, {{.+}} null, ptr null, ptr null, i32 0, i32 0)
 136 // HCHECK: call void @[[OFFL1:.+]]()
 137 // HCHECK: {{%.+}} = call{{.*}} i32 @[[TMAIN_INT:.+]]()
 138 // HCHECK:  ret
 139
 140 // HCHECK: define{{.*}} void @[[OFFL1]]()
 141
 142 // Skip global, bound tid and loop vars
 143
 144 // private(s_arr)
 145
 146 // private(var)
 147
 148
 149 // Skip global, bound tid and loop vars
 150
 151 // private(s_arr)
 152
 153 // private(var)
 154
 155
 156 // HCHECK: define{{.*}} i{{[0-9]+}} @[[TMAIN_INT]]()
 157 // HCHECK: call i32 @__tgt_target_teams_mapper(ptr @{{.+}}, i64 -1, ptr @{{[^,]+}}, i32 0,
 158 // HCHECK: call void @[[TOFFL1:.+]]()
 159 // HCHECK: ret
 160
 161 // HCHECK: define {{.*}}void @[[TOFFL1]]()
 162
 163 // Skip global, bound tid and loop vars
 164
 165 // private(s_arr)
 166
 167
 168 // private(var)
 169
 170
 171 // Skip global, bound tid and loop vars
 172 // prev lb and ub
 173 // iter variables
 174
 175 // private(s_arr)
 176
 177
 178 // private(var)
 179
 180
 181
 182 #endif
 183 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init
 184 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
 185 // CHECK1-NEXT:  entry:
 186 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
 187 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
 188 // CHECK1-NEXT:    ret void
 189 //
 190 //
 191 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
 192 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
 193 // CHECK1-NEXT:  entry:
 194 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 195 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 196 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 197 // CHECK1-NEXT:    call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
 198 // CHECK1-NEXT:    ret void
 199 //
 200 //
 201 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
 202 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
 203 // CHECK1-NEXT:  entry:
 204 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 205 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 206 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 207 // CHECK1-NEXT:    call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
 208 // CHECK1-NEXT:    ret void
 209 //
 210 //
 211 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
 212 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
 213 // CHECK1-NEXT:  entry:
 214 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 215 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 216 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 217 // CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
 218 // CHECK1-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
 219 // CHECK1-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
 220 // CHECK1-NEXT:    store float [[CONV]], ptr [[F]], align 4
 221 // CHECK1-NEXT:    ret void
 222 //
 223 //
 224 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
 225 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
 226 // CHECK1-NEXT:  entry:
 227 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 228 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 229 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 230 // CHECK1-NEXT:    ret void
 231 //
 232 //
 233 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
 234 // CHECK1-SAME: () #[[ATTR0]] {
 235 // CHECK1-NEXT:  entry:
 236 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
 237 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)
 238 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
 239 // CHECK1-NEXT:    ret void
 240 //
 241 //
 242 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
 243 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
 244 // CHECK1-NEXT:  entry:
 245 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 246 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
 247 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 248 // CHECK1-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
 249 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 250 // CHECK1-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
 251 // CHECK1-NEXT:    call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
 252 // CHECK1-NEXT:    ret void
 253 //
 254 //
 255 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
 256 // CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {
 257 // CHECK1-NEXT:  entry:
 258 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
 259 // CHECK1-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
 260 // CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
 261 // CHECK1:       arraydestroy.body:
 262 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
 263 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
 264 // CHECK1-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
 265 // CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr
 266 // CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
 267 // CHECK1:       arraydestroy.done1:
 268 // CHECK1-NEXT:    ret void
 269 //
 270 //
 271 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
 272 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
 273 // CHECK1-NEXT:  entry:
 274 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 275 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
 276 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 277 // CHECK1-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
 278 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 279 // CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
 280 // CHECK1-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
 281 // CHECK1-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
 282 // CHECK1-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
 283 // CHECK1-NEXT:    [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
 284 // CHECK1-NEXT:    store float [[ADD]], ptr [[F]], align 4
 285 // CHECK1-NEXT:    ret void
 286 //
 287 //
 288 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
 289 // CHECK1-SAME: () #[[ATTR0]] {
 290 // CHECK1-NEXT:  entry:
 291 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)
 292 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]
 293 // CHECK1-NEXT:    ret void
 294 //
 295 //
 296 // CHECK1-LABEL: define {{[^@]+}}@main
 297 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] {
 298 // CHECK1-NEXT:  entry:
 299 // CHECK1-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
 300 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 301 // CHECK1-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
 302 // CHECK1-NEXT:    store i32 0, ptr [[RETVAL]], align 4
 303 // CHECK1-NEXT:    [[TMP0:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
 304 // CHECK1-NEXT:    store i32 2, ptr [[TMP0]], align 4
 305 // CHECK1-NEXT:    [[TMP1:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
 306 // CHECK1-NEXT:    store i32 0, ptr [[TMP1]], align 4
 307 // CHECK1-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
 308 // CHECK1-NEXT:    store ptr null, ptr [[TMP2]], align 8
 309 // CHECK1-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
 310 // CHECK1-NEXT:    store ptr null, ptr [[TMP3]], align 8
 311 // CHECK1-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
 312 // CHECK1-NEXT:    store ptr null, ptr [[TMP4]], align 8
 313 // CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
 314 // CHECK1-NEXT:    store ptr null, ptr [[TMP5]], align 8
 315 // CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
 316 // CHECK1-NEXT:    store ptr null, ptr [[TMP6]], align 8
 317 // CHECK1-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
 318 // CHECK1-NEXT:    store ptr null, ptr [[TMP7]], align 8
 319 // CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
 320 // CHECK1-NEXT:    store i64 2, ptr [[TMP8]], align 8
 321 // CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
 322 // CHECK1-NEXT:    store i64 0, ptr [[TMP9]], align 8
 323 // CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
 324 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4
 325 // CHECK1-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
 326 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4
 327 // CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
 328 // CHECK1-NEXT:    store i32 0, ptr [[TMP12]], align 4
 329 // CHECK1-NEXT:    [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.region_id, ptr [[KERNEL_ARGS]])
 330 // CHECK1-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
 331 // CHECK1-NEXT:    br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
 332 // CHECK1:       omp_offload.failed:
 333 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124() #[[ATTR2]]
 334 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
 335 // CHECK1:       omp_offload.cont:
 336 // CHECK1-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v()
 337 // CHECK1-NEXT:    ret i32 [[CALL]]
 338 //
 339 //
 340 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124
 341 // CHECK1-SAME: () #[[ATTR4:[0-9]+]] {
 342 // CHECK1-NEXT:  entry:
 343 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined)
 344 // CHECK1-NEXT:    ret void
 345 //
 346 //
 347 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined
 348 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {
 349 // CHECK1-NEXT:  entry:
 350 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 351 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 352 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 353 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 354 // CHECK1-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
 355 // CHECK1-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
 356 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 357 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 358 // CHECK1-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
 359 // CHECK1-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
 360 // CHECK1-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
 361 // CHECK1-NEXT:    [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
 362 // CHECK1-NEXT:    [[SIVAR:%.*]] = alloca i32, align 4
 363 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
 364 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 365 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 366 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
 367 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_COMB_UB]], align 4
 368 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 369 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 370 // CHECK1-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
 371 // CHECK1-NEXT:    [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2
 372 // CHECK1-NEXT:    br label [[ARRAYCTOR_LOOP:%.*]]
 373 // CHECK1:       arrayctor.loop:
 374 // CHECK1-NEXT:    [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
 375 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
 376 // CHECK1-NEXT:    [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1
 377 // CHECK1-NEXT:    [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
 378 // CHECK1-NEXT:    br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
 379 // CHECK1:       arrayctor.cont:
 380 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]])
 381 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 382 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
 383 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
 384 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 385 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
 386 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 387 // CHECK1:       cond.true:
 388 // CHECK1-NEXT:    br label [[COND_END:%.*]]
 389 // CHECK1:       cond.false:
 390 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 391 // CHECK1-NEXT:    br label [[COND_END]]
 392 // CHECK1:       cond.end:
 393 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
 394 // CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
 395 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
 396 // CHECK1-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
 397 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 398 // CHECK1:       omp.inner.for.cond:
 399 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 400 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 401 // CHECK1-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
 402 // CHECK1-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
 403 // CHECK1:       omp.inner.for.cond.cleanup:
 404 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
 405 // CHECK1:       omp.inner.for.body:
 406 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
 407 // CHECK1-NEXT:    [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
 408 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 409 // CHECK1-NEXT:    [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
 410 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]])
 411 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 412 // CHECK1:       omp.inner.for.inc:
 413 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 414 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
 415 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
 416 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
 417 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]
 418 // CHECK1:       omp.inner.for.end:
 419 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
 420 // CHECK1:       omp.loop.exit:
 421 // CHECK1-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 422 // CHECK1-NEXT:    [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4
 423 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB2:[0-9]+]], i32 [[TMP14]])
 424 // CHECK1-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
 425 // CHECK1-NEXT:    [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
 426 // CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN2]], i64 2
 427 // CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
 428 // CHECK1:       arraydestroy.body:
 429 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
 430 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
 431 // CHECK1-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
 432 // CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]]
 433 // CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]]
 434 // CHECK1:       arraydestroy.done3:
 435 // CHECK1-NEXT:    ret void
 436 //
 437 //
 438 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined.omp_outlined
 439 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] {
 440 // CHECK1-NEXT:  entry:
 441 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 442 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 443 // CHECK1-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
 444 // CHECK1-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
 445 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 446 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 447 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
 448 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
 449 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 450 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 451 // CHECK1-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
 452 // CHECK1-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
 453 // CHECK1-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
 454 // CHECK1-NEXT:    [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
 455 // CHECK1-NEXT:    [[SIVAR:%.*]] = alloca i32, align 4
 456 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
 457 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 458 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 459 // CHECK1-NEXT:    store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
 460 // CHECK1-NEXT:    store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
 461 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
 462 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
 463 // CHECK1-NEXT:    [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
 464 // CHECK1-NEXT:    [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
 465 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
 466 // CHECK1-NEXT:    [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
 467 // CHECK1-NEXT:    store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
 468 // CHECK1-NEXT:    store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4
 469 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 470 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 471 // CHECK1-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
 472 // CHECK1-NEXT:    [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2
 473 // CHECK1-NEXT:    br label [[ARRAYCTOR_LOOP:%.*]]
 474 // CHECK1:       arrayctor.loop:
 475 // CHECK1-NEXT:    [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
 476 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
 477 // CHECK1-NEXT:    [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1
 478 // CHECK1-NEXT:    [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
 479 // CHECK1-NEXT:    br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
 480 // CHECK1:       arrayctor.cont:
 481 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]])
 482 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 483 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
 484 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
 485 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 486 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1
 487 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 488 // CHECK1:       cond.true:
 489 // CHECK1-NEXT:    br label [[COND_END:%.*]]
 490 // CHECK1:       cond.false:
 491 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 492 // CHECK1-NEXT:    br label [[COND_END]]
 493 // CHECK1:       cond.end:
 494 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
 495 // CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
 496 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
 497 // CHECK1-NEXT:    store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4
 498 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 499 // CHECK1:       omp.inner.for.cond:
 500 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 501 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 502 // CHECK1-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
 503 // CHECK1-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
 504 // CHECK1:       omp.inner.for.cond.cleanup:
 505 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
 506 // CHECK1:       omp.inner.for.body:
 507 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 508 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
 509 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
 510 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[I]], align 4
 511 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4
 512 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 4
 513 // CHECK1-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64
 514 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]]
 515 // CHECK1-NEXT:    store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4
 516 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[I]], align 4
 517 // CHECK1-NEXT:    [[IDXPROM3:%.*]] = sext i32 [[TMP12]] to i64
 518 // CHECK1-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM3]]
 519 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[VAR]], i64 4, i1 false)
 520 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, ptr [[I]], align 4
 521 // CHECK1-NEXT:    [[TMP14:%.*]] = load i32, ptr [[SIVAR]], align 4
 522 // CHECK1-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP14]], [[TMP13]]
 523 // CHECK1-NEXT:    store i32 [[ADD5]], ptr [[SIVAR]], align 4
 524 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 525 // CHECK1:       omp.body.continue:
 526 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 527 // CHECK1:       omp.inner.for.inc:
 528 // CHECK1-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 529 // CHECK1-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP15]], 1
 530 // CHECK1-NEXT:    store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4
 531 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]
 532 // CHECK1:       omp.inner.for.end:
 533 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
 534 // CHECK1:       omp.loop.exit:
 535 // CHECK1-NEXT:    [[TMP16:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 536 // CHECK1-NEXT:    [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 4
 537 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP17]])
 538 // CHECK1-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
 539 // CHECK1-NEXT:    [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
 540 // CHECK1-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i64 2
 541 // CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
 542 // CHECK1:       arraydestroy.body:
 543 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP18]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
 544 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
 545 // CHECK1-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
 546 // CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]
 547 // CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]
 548 // CHECK1:       arraydestroy.done8:
 549 // CHECK1-NEXT:    ret void
 550 //
 551 //
 552 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
 553 // CHECK1-SAME: () #[[ATTR6:[0-9]+]] comdat {
 554 // CHECK1-NEXT:  entry:
 555 // CHECK1-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
 556 // CHECK1-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
 557 // CHECK1-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
 558 // CHECK1-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
 559 // CHECK1-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
 560 // CHECK1-NEXT:    [[VAR:%.*]] = alloca ptr, align 8
 561 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 562 // CHECK1-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 8
 563 // CHECK1-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
 564 // CHECK1-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])
 565 // CHECK1-NEXT:    store i32 0, ptr [[T_VAR]], align 4
 566 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false)
 567 // CHECK1-NEXT:    [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 0
 568 // CHECK1-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef signext 1)
 569 // CHECK1-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYINIT_BEGIN]], i64 1
 570 // CHECK1-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2)
 571 // CHECK1-NEXT:    store ptr [[TEST]], ptr [[VAR]], align 8
 572 // CHECK1-NEXT:    store ptr undef, ptr [[_TMP1]], align 8
 573 // CHECK1-NEXT:    [[TMP0:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
 574 // CHECK1-NEXT:    store i32 2, ptr [[TMP0]], align 4
 575 // CHECK1-NEXT:    [[TMP1:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
 576 // CHECK1-NEXT:    store i32 0, ptr [[TMP1]], align 4
 577 // CHECK1-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
 578 // CHECK1-NEXT:    store ptr null, ptr [[TMP2]], align 8
 579 // CHECK1-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
 580 // CHECK1-NEXT:    store ptr null, ptr [[TMP3]], align 8
 581 // CHECK1-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
 582 // CHECK1-NEXT:    store ptr null, ptr [[TMP4]], align 8
 583 // CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
 584 // CHECK1-NEXT:    store ptr null, ptr [[TMP5]], align 8
 585 // CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
 586 // CHECK1-NEXT:    store ptr null, ptr [[TMP6]], align 8
 587 // CHECK1-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
 588 // CHECK1-NEXT:    store ptr null, ptr [[TMP7]], align 8
 589 // CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
 590 // CHECK1-NEXT:    store i64 2, ptr [[TMP8]], align 8
 591 // CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
 592 // CHECK1-NEXT:    store i64 0, ptr [[TMP9]], align 8
 593 // CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
 594 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4
 595 // CHECK1-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
 596 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4
 597 // CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
 598 // CHECK1-NEXT:    store i32 0, ptr [[TMP12]], align 4
 599 // CHECK1-NEXT:    [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.region_id, ptr [[KERNEL_ARGS]])
 600 // CHECK1-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
 601 // CHECK1-NEXT:    br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
 602 // CHECK1:       omp_offload.failed:
 603 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80() #[[ATTR2]]
 604 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
 605 // CHECK1:       omp_offload.cont:
 606 // CHECK1-NEXT:    store i32 0, ptr [[RETVAL]], align 4
 607 // CHECK1-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
 608 // CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2
 609 // CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
 610 // CHECK1:       arraydestroy.body:
 611 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
 612 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
 613 // CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
 614 // CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
 615 // CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
 616 // CHECK1:       arraydestroy.done2:
 617 // CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
 618 // CHECK1-NEXT:    [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4
 619 // CHECK1-NEXT:    ret i32 [[TMP16]]
 620 //
 621 //
 622 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
 623 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
 624 // CHECK1-NEXT:  entry:
 625 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 626 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 627 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 628 // CHECK1-NEXT:    call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
 629 // CHECK1-NEXT:    ret void
 630 //
 631 //
 632 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
 633 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
 634 // CHECK1-NEXT:  entry:
 635 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 636 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
 637 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 638 // CHECK1-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
 639 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 640 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
 641 // CHECK1-NEXT:    call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
 642 // CHECK1-NEXT:    ret void
 643 //
 644 //
 645 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80
 646 // CHECK1-SAME: () #[[ATTR4]] {
 647 // CHECK1-NEXT:  entry:
 648 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined)
 649 // CHECK1-NEXT:    ret void
 650 //
 651 //
 652 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined
 653 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {
 654 // CHECK1-NEXT:  entry:
 655 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 656 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 657 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 658 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 659 // CHECK1-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 8
 660 // CHECK1-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
 661 // CHECK1-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
 662 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 663 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 664 // CHECK1-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
 665 // CHECK1-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
 666 // CHECK1-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
 667 // CHECK1-NEXT:    [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
 668 // CHECK1-NEXT:    [[_TMP2:%.*]] = alloca ptr, align 8
 669 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
 670 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 671 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 672 // CHECK1-NEXT:    store ptr undef, ptr [[_TMP1]], align 8
 673 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
 674 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_COMB_UB]], align 4
 675 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 676 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 677 // CHECK1-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
 678 // CHECK1-NEXT:    [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2
 679 // CHECK1-NEXT:    br label [[ARRAYCTOR_LOOP:%.*]]
 680 // CHECK1:       arrayctor.loop:
 681 // CHECK1-NEXT:    [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
 682 // CHECK1-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
 683 // CHECK1-NEXT:    [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i64 1
 684 // CHECK1-NEXT:    [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
 685 // CHECK1-NEXT:    br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
 686 // CHECK1:       arrayctor.cont:
 687 // CHECK1-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]])
 688 // CHECK1-NEXT:    store ptr [[VAR]], ptr [[_TMP2]], align 8
 689 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 690 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
 691 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
 692 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 693 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
 694 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 695 // CHECK1:       cond.true:
 696 // CHECK1-NEXT:    br label [[COND_END:%.*]]
 697 // CHECK1:       cond.false:
 698 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 699 // CHECK1-NEXT:    br label [[COND_END]]
 700 // CHECK1:       cond.end:
 701 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
 702 // CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
 703 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
 704 // CHECK1-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
 705 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 706 // CHECK1:       omp.inner.for.cond:
 707 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 708 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 709 // CHECK1-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
 710 // CHECK1-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
 711 // CHECK1:       omp.inner.for.cond.cleanup:
 712 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
 713 // CHECK1:       omp.inner.for.body:
 714 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
 715 // CHECK1-NEXT:    [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
 716 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 717 // CHECK1-NEXT:    [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
 718 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]])
 719 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 720 // CHECK1:       omp.inner.for.inc:
 721 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 722 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
 723 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
 724 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
 725 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]
 726 // CHECK1:       omp.inner.for.end:
 727 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
 728 // CHECK1:       omp.loop.exit:
 729 // CHECK1-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 730 // CHECK1-NEXT:    [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4
 731 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP14]])
 732 // CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
 733 // CHECK1-NEXT:    [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
 734 // CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN4]], i64 2
 735 // CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
 736 // CHECK1:       arraydestroy.body:
 737 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
 738 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
 739 // CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
 740 // CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]]
 741 // CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]]
 742 // CHECK1:       arraydestroy.done5:
 743 // CHECK1-NEXT:    ret void
 744 //
 745 //
 746 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined.omp_outlined
 747 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] {
 748 // CHECK1-NEXT:  entry:
 749 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 750 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 751 // CHECK1-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
 752 // CHECK1-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
 753 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 754 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 755 // CHECK1-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 8
 756 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
 757 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
 758 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 759 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 760 // CHECK1-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
 761 // CHECK1-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
 762 // CHECK1-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
 763 // CHECK1-NEXT:    [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
 764 // CHECK1-NEXT:    [[_TMP3:%.*]] = alloca ptr, align 8
 765 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
 766 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 767 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 768 // CHECK1-NEXT:    store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
 769 // CHECK1-NEXT:    store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
 770 // CHECK1-NEXT:    store ptr undef, ptr [[_TMP1]], align 8
 771 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
 772 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
 773 // CHECK1-NEXT:    [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
 774 // CHECK1-NEXT:    [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
 775 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
 776 // CHECK1-NEXT:    [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32
 777 // CHECK1-NEXT:    store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
 778 // CHECK1-NEXT:    store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4
 779 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 780 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 781 // CHECK1-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
 782 // CHECK1-NEXT:    [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2
 783 // CHECK1-NEXT:    br label [[ARRAYCTOR_LOOP:%.*]]
 784 // CHECK1:       arrayctor.loop:
 785 // CHECK1-NEXT:    [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
 786 // CHECK1-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
 787 // CHECK1-NEXT:    [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i64 1
 788 // CHECK1-NEXT:    [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
 789 // CHECK1-NEXT:    br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
 790 // CHECK1:       arrayctor.cont:
 791 // CHECK1-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]])
 792 // CHECK1-NEXT:    store ptr [[VAR]], ptr [[_TMP3]], align 8
 793 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 794 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
 795 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
 796 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 797 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1
 798 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 799 // CHECK1:       cond.true:
 800 // CHECK1-NEXT:    br label [[COND_END:%.*]]
 801 // CHECK1:       cond.false:
 802 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 803 // CHECK1-NEXT:    br label [[COND_END]]
 804 // CHECK1:       cond.end:
 805 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
 806 // CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
 807 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
 808 // CHECK1-NEXT:    store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4
 809 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 810 // CHECK1:       omp.inner.for.cond:
 811 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 812 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 813 // CHECK1-NEXT:    [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
 814 // CHECK1-NEXT:    br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
 815 // CHECK1:       omp.inner.for.cond.cleanup:
 816 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
 817 // CHECK1:       omp.inner.for.body:
 818 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 819 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
 820 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
 821 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[I]], align 4
 822 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4
 823 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 4
 824 // CHECK1-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64
 825 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]]
 826 // CHECK1-NEXT:    store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4
 827 // CHECK1-NEXT:    [[TMP12:%.*]] = load ptr, ptr [[_TMP3]], align 8
 828 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, ptr [[I]], align 4
 829 // CHECK1-NEXT:    [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64
 830 // CHECK1-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM5]]
 831 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX6]], ptr align 4 [[TMP12]], i64 4, i1 false)
 832 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 833 // CHECK1:       omp.body.continue:
 834 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 835 // CHECK1:       omp.inner.for.inc:
 836 // CHECK1-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
 837 // CHECK1-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP14]], 1
 838 // CHECK1-NEXT:    store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4
 839 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]]
 840 // CHECK1:       omp.inner.for.end:
 841 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
 842 // CHECK1:       omp.loop.exit:
 843 // CHECK1-NEXT:    [[TMP15:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 844 // CHECK1-NEXT:    [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 4
 845 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP16]])
 846 // CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
 847 // CHECK1-NEXT:    [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
 848 // CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN8]], i64 2
 849 // CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
 850 // CHECK1:       arraydestroy.body:
 851 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
 852 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
 853 // CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
 854 // CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]]
 855 // CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]]
 856 // CHECK1:       arraydestroy.done9:
 857 // CHECK1-NEXT:    ret void
 858 //
 859 //
 860 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
 861 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
 862 // CHECK1-NEXT:  entry:
 863 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 864 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 865 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 866 // CHECK1-NEXT:    call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
 867 // CHECK1-NEXT:    ret void
 868 //
 869 //
 870 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
 871 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
 872 // CHECK1-NEXT:  entry:
 873 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 874 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 875 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 876 // CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
 877 // CHECK1-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
 878 // CHECK1-NEXT:    store i32 [[TMP0]], ptr [[F]], align 4
 879 // CHECK1-NEXT:    ret void
 880 //
 881 //
 882 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
 883 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
 884 // CHECK1-NEXT:  entry:
 885 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 886 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
 887 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 888 // CHECK1-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
 889 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 890 // CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
 891 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
 892 // CHECK1-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
 893 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
 894 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[F]], align 4
 895 // CHECK1-NEXT:    ret void
 896 //
 897 //
 898 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
 899 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
 900 // CHECK1-NEXT:  entry:
 901 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 902 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 903 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 904 // CHECK1-NEXT:    ret void
 905 //
 906 //
 907 // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_generic_loop_private_codegen.cpp
 908 // CHECK1-SAME: () #[[ATTR0]] {
 909 // CHECK1-NEXT:  entry:
 910 // CHECK1-NEXT:    call void @__cxx_global_var_init()
 911 // CHECK1-NEXT:    call void @__cxx_global_var_init.1()
 912 // CHECK1-NEXT:    call void @__cxx_global_var_init.2()
 913 // CHECK1-NEXT:    ret void
 914 //
 915 //
 916 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
 917 // CHECK1-SAME: () #[[ATTR0]] {
 918 // CHECK1-NEXT:  entry:
 919 // CHECK1-NEXT:    call void @__tgt_register_requires(i64 1)
 920 // CHECK1-NEXT:    ret void
 921 //
 922 //
 923 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init
 924 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] {
 925 // CHECK3-NEXT:  entry:
 926 // CHECK3-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
 927 // CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
 928 // CHECK3-NEXT:    ret void
 929 //
 930 //
 931 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
 932 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
 933 // CHECK3-NEXT:  entry:
 934 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
 935 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
 936 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
 937 // CHECK3-NEXT:    call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
 938 // CHECK3-NEXT:    ret void
 939 //
 940 //
 941 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
 942 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
 943 // CHECK3-NEXT:  entry:
 944 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
 945 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
 946 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
 947 // CHECK3-NEXT:    call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
 948 // CHECK3-NEXT:    ret void
 949 //
 950 //
 951 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
 952 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
 953 // CHECK3-NEXT:  entry:
 954 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
 955 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
 956 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
 957 // CHECK3-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
 958 // CHECK3-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
 959 // CHECK3-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
 960 // CHECK3-NEXT:    store float [[CONV]], ptr [[F]], align 4
 961 // CHECK3-NEXT:    ret void
 962 //
 963 //
 964 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
 965 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
 966 // CHECK3-NEXT:  entry:
 967 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
 968 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
 969 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
 970 // CHECK3-NEXT:    ret void
 971 //
 972 //
 973 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
 974 // CHECK3-SAME: () #[[ATTR0]] {
 975 // CHECK3-NEXT:  entry:
 976 // CHECK3-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
 977 // CHECK3-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 1), float noundef 2.000000e+00)
 978 // CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
 979 // CHECK3-NEXT:    ret void
 980 //
 981 //
 982 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
 983 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
 984 // CHECK3-NEXT:  entry:
 985 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
 986 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
 987 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
 988 // CHECK3-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
 989 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
 990 // CHECK3-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
 991 // CHECK3-NEXT:    call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
 992 // CHECK3-NEXT:    ret void
 993 //
 994 //
 995 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
 996 // CHECK3-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {
 997 // CHECK3-NEXT:  entry:
 998 // CHECK3-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 4
 999 // CHECK3-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 4
1000 // CHECK3-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1001 // CHECK3:       arraydestroy.body:
1002 // CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1003 // CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1004 // CHECK3-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1005 // CHECK3-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr
1006 // CHECK3-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
1007 // CHECK3:       arraydestroy.done1:
1008 // CHECK3-NEXT:    ret void
1009 //
1010 //
1011 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
1012 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1013 // CHECK3-NEXT:  entry:
1014 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1015 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
1016 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1017 // CHECK3-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
1018 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1019 // CHECK3-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
1020 // CHECK3-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
1021 // CHECK3-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
1022 // CHECK3-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
1023 // CHECK3-NEXT:    [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
1024 // CHECK3-NEXT:    store float [[ADD]], ptr [[F]], align 4
1025 // CHECK3-NEXT:    ret void
1026 //
1027 //
1028 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
1029 // CHECK3-SAME: () #[[ATTR0]] {
1030 // CHECK3-NEXT:  entry:
1031 // CHECK3-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)
1032 // CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]
1033 // CHECK3-NEXT:    ret void
1034 //
1035 //
1036 // CHECK3-LABEL: define {{[^@]+}}@main
1037 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] {
1038 // CHECK3-NEXT:  entry:
1039 // CHECK3-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
1040 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1041 // CHECK3-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1042 // CHECK3-NEXT:    store i32 0, ptr [[RETVAL]], align 4
1043 // CHECK3-NEXT:    [[TMP0:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
1044 // CHECK3-NEXT:    store i32 2, ptr [[TMP0]], align 4
1045 // CHECK3-NEXT:    [[TMP1:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
1046 // CHECK3-NEXT:    store i32 0, ptr [[TMP1]], align 4
1047 // CHECK3-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
1048 // CHECK3-NEXT:    store ptr null, ptr [[TMP2]], align 4
1049 // CHECK3-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
1050 // CHECK3-NEXT:    store ptr null, ptr [[TMP3]], align 4
1051 // CHECK3-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
1052 // CHECK3-NEXT:    store ptr null, ptr [[TMP4]], align 4
1053 // CHECK3-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
1054 // CHECK3-NEXT:    store ptr null, ptr [[TMP5]], align 4
1055 // CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
1056 // CHECK3-NEXT:    store ptr null, ptr [[TMP6]], align 4
1057 // CHECK3-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
1058 // CHECK3-NEXT:    store ptr null, ptr [[TMP7]], align 4
1059 // CHECK3-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
1060 // CHECK3-NEXT:    store i64 2, ptr [[TMP8]], align 8
1061 // CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
1062 // CHECK3-NEXT:    store i64 0, ptr [[TMP9]], align 8
1063 // CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
1064 // CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4
1065 // CHECK3-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
1066 // CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4
1067 // CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
1068 // CHECK3-NEXT:    store i32 0, ptr [[TMP12]], align 4
1069 // CHECK3-NEXT:    [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.region_id, ptr [[KERNEL_ARGS]])
1070 // CHECK3-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
1071 // CHECK3-NEXT:    br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1072 // CHECK3:       omp_offload.failed:
1073 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124() #[[ATTR2]]
1074 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]
1075 // CHECK3:       omp_offload.cont:
1076 // CHECK3-NEXT:    [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()
1077 // CHECK3-NEXT:    ret i32 [[CALL]]
1078 //
1079 //
1080 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124
1081 // CHECK3-SAME: () #[[ATTR4:[0-9]+]] {
1082 // CHECK3-NEXT:  entry:
1083 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined)
1084 // CHECK3-NEXT:    ret void
1085 //
1086 //
1087 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined
1088 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {
1089 // CHECK3-NEXT:  entry:
1090 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
1091 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
1092 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1093 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1094 // CHECK3-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
1095 // CHECK3-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
1096 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1097 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1098 // CHECK3-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
1099 // CHECK3-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
1100 // CHECK3-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
1101 // CHECK3-NEXT:    [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
1102 // CHECK3-NEXT:    [[SIVAR:%.*]] = alloca i32, align 4
1103 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
1104 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
1105 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
1106 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
1107 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_COMB_UB]], align 4
1108 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1109 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1110 // CHECK3-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
1111 // CHECK3-NEXT:    [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2
1112 // CHECK3-NEXT:    br label [[ARRAYCTOR_LOOP:%.*]]
1113 // CHECK3:       arrayctor.loop:
1114 // CHECK3-NEXT:    [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1115 // CHECK3-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1116 // CHECK3-NEXT:    [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i32 1
1117 // CHECK3-NEXT:    [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1118 // CHECK3-NEXT:    br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1119 // CHECK3:       arrayctor.cont:
1120 // CHECK3-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]])
1121 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
1122 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
1123 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
1124 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1125 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
1126 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1127 // CHECK3:       cond.true:
1128 // CHECK3-NEXT:    br label [[COND_END:%.*]]
1129 // CHECK3:       cond.false:
1130 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1131 // CHECK3-NEXT:    br label [[COND_END]]
1132 // CHECK3:       cond.end:
1133 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
1134 // CHECK3-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
1135 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
1136 // CHECK3-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
1137 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1138 // CHECK3:       omp.inner.for.cond:
1139 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1140 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1141 // CHECK3-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
1142 // CHECK3-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1143 // CHECK3:       omp.inner.for.cond.cleanup:
1144 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
1145 // CHECK3:       omp.inner.for.body:
1146 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
1147 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1148 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined.omp_outlined, i32 [[TMP7]], i32 [[TMP8]])
1149 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1150 // CHECK3:       omp.inner.for.inc:
1151 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1152 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
1153 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]]
1154 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
1155 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]]
1156 // CHECK3:       omp.inner.for.end:
1157 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1158 // CHECK3:       omp.loop.exit:
1159 // CHECK3-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
1160 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4
1161 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB2:[0-9]+]], i32 [[TMP12]])
1162 // CHECK3-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
1163 // CHECK3-NEXT:    [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
1164 // CHECK3-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN2]], i32 2
1165 // CHECK3-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1166 // CHECK3:       arraydestroy.body:
1167 // CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP13]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1168 // CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1169 // CHECK3-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1170 // CHECK3-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]]
1171 // CHECK3-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]]
1172 // CHECK3:       arraydestroy.done3:
1173 // CHECK3-NEXT:    ret void
1174 //
1175 //
1176 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined.omp_outlined
1177 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] {
1178 // CHECK3-NEXT:  entry:
1179 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
1180 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
1181 // CHECK3-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
1182 // CHECK3-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
1183 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1184 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1185 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1186 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1187 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1188 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1189 // CHECK3-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
1190 // CHECK3-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
1191 // CHECK3-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
1192 // CHECK3-NEXT:    [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
1193 // CHECK3-NEXT:    [[SIVAR:%.*]] = alloca i32, align 4
1194 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
1195 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
1196 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
1197 // CHECK3-NEXT:    store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4
1198 // CHECK3-NEXT:    store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
1199 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
1200 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
1201 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4
1202 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
1203 // CHECK3-NEXT:    store i32 [[TMP0]], ptr [[DOTOMP_LB]], align 4
1204 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[DOTOMP_UB]], align 4
1205 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1206 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1207 // CHECK3-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
1208 // CHECK3-NEXT:    [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2
1209 // CHECK3-NEXT:    br label [[ARRAYCTOR_LOOP:%.*]]
1210 // CHECK3:       arrayctor.loop:
1211 // CHECK3-NEXT:    [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1212 // CHECK3-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1213 // CHECK3-NEXT:    [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i32 1
1214 // CHECK3-NEXT:    [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1215 // CHECK3-NEXT:    br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1216 // CHECK3:       arrayctor.cont:
1217 // CHECK3-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]])
1218 // CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
1219 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
1220 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
1221 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1222 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1
1223 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1224 // CHECK3:       cond.true:
1225 // CHECK3-NEXT:    br label [[COND_END:%.*]]
1226 // CHECK3:       cond.false:
1227 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1228 // CHECK3-NEXT:    br label [[COND_END]]
1229 // CHECK3:       cond.end:
1230 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
1231 // CHECK3-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
1232 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1233 // CHECK3-NEXT:    store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4
1234 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1235 // CHECK3:       omp.inner.for.cond:
1236 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1237 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1238 // CHECK3-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
1239 // CHECK3-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1240 // CHECK3:       omp.inner.for.cond.cleanup:
1241 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
1242 // CHECK3:       omp.inner.for.body:
1243 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1244 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
1245 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1246 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[I]], align 4
1247 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4
1248 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 4
1249 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP11]]
1250 // CHECK3-NEXT:    store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4
1251 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, ptr [[I]], align 4
1252 // CHECK3-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP12]]
1253 // CHECK3-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[VAR]], i32 4, i1 false)
1254 // CHECK3-NEXT:    [[TMP13:%.*]] = load i32, ptr [[I]], align 4
1255 // CHECK3-NEXT:    [[TMP14:%.*]] = load i32, ptr [[SIVAR]], align 4
1256 // CHECK3-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP14]], [[TMP13]]
1257 // CHECK3-NEXT:    store i32 [[ADD3]], ptr [[SIVAR]], align 4
1258 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1259 // CHECK3:       omp.body.continue:
1260 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1261 // CHECK3:       omp.inner.for.inc:
1262 // CHECK3-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1263 // CHECK3-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP15]], 1
1264 // CHECK3-NEXT:    store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4
1265 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]]
1266 // CHECK3:       omp.inner.for.end:
1267 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1268 // CHECK3:       omp.loop.exit:
1269 // CHECK3-NEXT:    [[TMP16:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
1270 // CHECK3-NEXT:    [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 4
1271 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP17]])
1272 // CHECK3-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
1273 // CHECK3-NEXT:    [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
1274 // CHECK3-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN5]], i32 2
1275 // CHECK3-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1276 // CHECK3:       arraydestroy.body:
1277 // CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP18]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1278 // CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1279 // CHECK3-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1280 // CHECK3-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]]
1281 // CHECK3-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]]
1282 // CHECK3:       arraydestroy.done6:
1283 // CHECK3-NEXT:    ret void
1284 //
1285 //
1286 // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
1287 // CHECK3-SAME: () #[[ATTR6:[0-9]+]] comdat {
1288 // CHECK3-NEXT:  entry:
1289 // CHECK3-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
1290 // CHECK3-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1291 // CHECK3-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
1292 // CHECK3-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
1293 // CHECK3-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
1294 // CHECK3-NEXT:    [[VAR:%.*]] = alloca ptr, align 4
1295 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1296 // CHECK3-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 4
1297 // CHECK3-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1298 // CHECK3-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])
1299 // CHECK3-NEXT:    store i32 0, ptr [[T_VAR]], align 4
1300 // CHECK3-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false)
1301 // CHECK3-NEXT:    [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
1302 // CHECK3-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef 1)
1303 // CHECK3-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYINIT_BEGIN]], i32 1
1304 // CHECK3-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)
1305 // CHECK3-NEXT:    store ptr [[TEST]], ptr [[VAR]], align 4
1306 // CHECK3-NEXT:    store ptr undef, ptr [[_TMP1]], align 4
1307 // CHECK3-NEXT:    [[TMP0:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
1308 // CHECK3-NEXT:    store i32 2, ptr [[TMP0]], align 4
1309 // CHECK3-NEXT:    [[TMP1:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
1310 // CHECK3-NEXT:    store i32 0, ptr [[TMP1]], align 4
1311 // CHECK3-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
1312 // CHECK3-NEXT:    store ptr null, ptr [[TMP2]], align 4
1313 // CHECK3-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
1314 // CHECK3-NEXT:    store ptr null, ptr [[TMP3]], align 4
1315 // CHECK3-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
1316 // CHECK3-NEXT:    store ptr null, ptr [[TMP4]], align 4
1317 // CHECK3-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
1318 // CHECK3-NEXT:    store ptr null, ptr [[TMP5]], align 4
1319 // CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
1320 // CHECK3-NEXT:    store ptr null, ptr [[TMP6]], align 4
1321 // CHECK3-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
1322 // CHECK3-NEXT:    store ptr null, ptr [[TMP7]], align 4
1323 // CHECK3-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
1324 // CHECK3-NEXT:    store i64 2, ptr [[TMP8]], align 8
1325 // CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
1326 // CHECK3-NEXT:    store i64 0, ptr [[TMP9]], align 8
1327 // CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
1328 // CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4
1329 // CHECK3-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
1330 // CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4
1331 // CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
1332 // CHECK3-NEXT:    store i32 0, ptr [[TMP12]], align 4
1333 // CHECK3-NEXT:    [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.region_id, ptr [[KERNEL_ARGS]])
1334 // CHECK3-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
1335 // CHECK3-NEXT:    br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1336 // CHECK3:       omp_offload.failed:
1337 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80() #[[ATTR2]]
1338 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]
1339 // CHECK3:       omp_offload.cont:
1340 // CHECK3-NEXT:    store i32 0, ptr [[RETVAL]], align 4
1341 // CHECK3-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
1342 // CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2
1343 // CHECK3-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1344 // CHECK3:       arraydestroy.body:
1345 // CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1346 // CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1347 // CHECK3-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1348 // CHECK3-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
1349 // CHECK3-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
1350 // CHECK3:       arraydestroy.done2:
1351 // CHECK3-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
1352 // CHECK3-NEXT:    [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4
1353 // CHECK3-NEXT:    ret i32 [[TMP16]]
1354 //
1355 //
1356 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
1357 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1358 // CHECK3-NEXT:  entry:
1359 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1360 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1361 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1362 // CHECK3-NEXT:    call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
1363 // CHECK3-NEXT:    ret void
1364 //
1365 //
1366 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
1367 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1368 // CHECK3-NEXT:  entry:
1369 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1370 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
1371 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1372 // CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
1373 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1374 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
1375 // CHECK3-NEXT:    call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])
1376 // CHECK3-NEXT:    ret void
1377 //
1378 //
1379 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80
1380 // CHECK3-SAME: () #[[ATTR4]] {
1381 // CHECK3-NEXT:  entry:
1382 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined)
1383 // CHECK3-NEXT:    ret void
1384 //
1385 //
1386 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined
1387 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR4]] {
1388 // CHECK3-NEXT:  entry:
1389 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
1390 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
1391 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1392 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1393 // CHECK3-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 4
1394 // CHECK3-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
1395 // CHECK3-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
1396 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1397 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1398 // CHECK3-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
1399 // CHECK3-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
1400 // CHECK3-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
1401 // CHECK3-NEXT:    [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1402 // CHECK3-NEXT:    [[_TMP2:%.*]] = alloca ptr, align 4
1403 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
1404 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
1405 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
1406 // CHECK3-NEXT:    store ptr undef, ptr [[_TMP1]], align 4
1407 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
1408 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_COMB_UB]], align 4
1409 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1410 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1411 // CHECK3-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
1412 // CHECK3-NEXT:    [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2
1413 // CHECK3-NEXT:    br label [[ARRAYCTOR_LOOP:%.*]]
1414 // CHECK3:       arrayctor.loop:
1415 // CHECK3-NEXT:    [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1416 // CHECK3-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1417 // CHECK3-NEXT:    [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i32 1
1418 // CHECK3-NEXT:    [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1419 // CHECK3-NEXT:    br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1420 // CHECK3:       arrayctor.cont:
1421 // CHECK3-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]])
1422 // CHECK3-NEXT:    store ptr [[VAR]], ptr [[_TMP2]], align 4
1423 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
1424 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
1425 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
1426 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1427 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
1428 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1429 // CHECK3:       cond.true:
1430 // CHECK3-NEXT:    br label [[COND_END:%.*]]
1431 // CHECK3:       cond.false:
1432 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1433 // CHECK3-NEXT:    br label [[COND_END]]
1434 // CHECK3:       cond.end:
1435 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
1436 // CHECK3-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
1437 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
1438 // CHECK3-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
1439 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1440 // CHECK3:       omp.inner.for.cond:
1441 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1442 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1443 // CHECK3-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
1444 // CHECK3-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1445 // CHECK3:       omp.inner.for.cond.cleanup:
1446 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
1447 // CHECK3:       omp.inner.for.body:
1448 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
1449 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1450 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined.omp_outlined, i32 [[TMP7]], i32 [[TMP8]])
1451 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1452 // CHECK3:       omp.inner.for.inc:
1453 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1454 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
1455 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]]
1456 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
1457 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]]
1458 // CHECK3:       omp.inner.for.end:
1459 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1460 // CHECK3:       omp.loop.exit:
1461 // CHECK3-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
1462 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4
1463 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP12]])
1464 // CHECK3-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
1465 // CHECK3-NEXT:    [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
1466 // CHECK3-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN4]], i32 2
1467 // CHECK3-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1468 // CHECK3:       arraydestroy.body:
1469 // CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP13]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1470 // CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1471 // CHECK3-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1472 // CHECK3-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]]
1473 // CHECK3-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]]
1474 // CHECK3:       arraydestroy.done5:
1475 // CHECK3-NEXT:    ret void
1476 //
1477 //
1478 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined.omp_outlined
1479 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR4]] {
1480 // CHECK3-NEXT:  entry:
1481 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
1482 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
1483 // CHECK3-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
1484 // CHECK3-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
1485 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1486 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1487 // CHECK3-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 4
1488 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1489 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1490 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1491 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1492 // CHECK3-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
1493 // CHECK3-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
1494 // CHECK3-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
1495 // CHECK3-NEXT:    [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1496 // CHECK3-NEXT:    [[_TMP2:%.*]] = alloca ptr, align 4
1497 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
1498 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
1499 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
1500 // CHECK3-NEXT:    store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4
1501 // CHECK3-NEXT:    store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
1502 // CHECK3-NEXT:    store ptr undef, ptr [[_TMP1]], align 4
1503 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
1504 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
1505 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4
1506 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
1507 // CHECK3-NEXT:    store i32 [[TMP0]], ptr [[DOTOMP_LB]], align 4
1508 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[DOTOMP_UB]], align 4
1509 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1510 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1511 // CHECK3-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
1512 // CHECK3-NEXT:    [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2
1513 // CHECK3-NEXT:    br label [[ARRAYCTOR_LOOP:%.*]]
1514 // CHECK3:       arrayctor.loop:
1515 // CHECK3-NEXT:    [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1516 // CHECK3-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1517 // CHECK3-NEXT:    [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i32 1
1518 // CHECK3-NEXT:    [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1519 // CHECK3-NEXT:    br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1520 // CHECK3:       arrayctor.cont:
1521 // CHECK3-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]])
1522 // CHECK3-NEXT:    store ptr [[VAR]], ptr [[_TMP2]], align 4
1523 // CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
1524 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
1525 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
1526 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1527 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1
1528 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1529 // CHECK3:       cond.true:
1530 // CHECK3-NEXT:    br label [[COND_END:%.*]]
1531 // CHECK3:       cond.false:
1532 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1533 // CHECK3-NEXT:    br label [[COND_END]]
1534 // CHECK3:       cond.end:
1535 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
1536 // CHECK3-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
1537 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1538 // CHECK3-NEXT:    store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4
1539 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1540 // CHECK3:       omp.inner.for.cond:
1541 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1542 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1543 // CHECK3-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
1544 // CHECK3-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1545 // CHECK3:       omp.inner.for.cond.cleanup:
1546 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
1547 // CHECK3:       omp.inner.for.body:
1548 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1549 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
1550 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1551 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[I]], align 4
1552 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4
1553 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 4
1554 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP11]]
1555 // CHECK3-NEXT:    store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4
1556 // CHECK3-NEXT:    [[TMP12:%.*]] = load ptr, ptr [[_TMP2]], align 4
1557 // CHECK3-NEXT:    [[TMP13:%.*]] = load i32, ptr [[I]], align 4
1558 // CHECK3-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP13]]
1559 // CHECK3-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP12]], i32 4, i1 false)
1560 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1561 // CHECK3:       omp.body.continue:
1562 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1563 // CHECK3:       omp.inner.for.inc:
1564 // CHECK3-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1565 // CHECK3-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1
1566 // CHECK3-NEXT:    store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4
1567 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]]
1568 // CHECK3:       omp.inner.for.end:
1569 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1570 // CHECK3:       omp.loop.exit:
1571 // CHECK3-NEXT:    [[TMP15:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
1572 // CHECK3-NEXT:    [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 4
1573 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP16]])
1574 // CHECK3-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
1575 // CHECK3-NEXT:    [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
1576 // CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN6]], i32 2
1577 // CHECK3-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1578 // CHECK3:       arraydestroy.body:
1579 // CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1580 // CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1581 // CHECK3-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1582 // CHECK3-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]]
1583 // CHECK3-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]]
1584 // CHECK3:       arraydestroy.done7:
1585 // CHECK3-NEXT:    ret void
1586 //
1587 //
1588 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
1589 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1590 // CHECK3-NEXT:  entry:
1591 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1592 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1593 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1594 // CHECK3-NEXT:    call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
1595 // CHECK3-NEXT:    ret void
1596 //
1597 //
1598 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
1599 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1600 // CHECK3-NEXT:  entry:
1601 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1602 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1603 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1604 // CHECK3-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
1605 // CHECK3-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
1606 // CHECK3-NEXT:    store i32 [[TMP0]], ptr [[F]], align 4
1607 // CHECK3-NEXT:    ret void
1608 //
1609 //
1610 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
1611 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1612 // CHECK3-NEXT:  entry:
1613 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1614 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
1615 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1616 // CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
1617 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1618 // CHECK3-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
1619 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
1620 // CHECK3-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
1621 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
1622 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[F]], align 4
1623 // CHECK3-NEXT:    ret void
1624 //
1625 //
1626 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
1627 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1628 // CHECK3-NEXT:  entry:
1629 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1630 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1631 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1632 // CHECK3-NEXT:    ret void
1633 //
1634 //
1635 // CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_generic_loop_private_codegen.cpp
1636 // CHECK3-SAME: () #[[ATTR0]] {
1637 // CHECK3-NEXT:  entry:
1638 // CHECK3-NEXT:    call void @__cxx_global_var_init()
1639 // CHECK3-NEXT:    call void @__cxx_global_var_init.1()
1640 // CHECK3-NEXT:    call void @__cxx_global_var_init.2()
1641 // CHECK3-NEXT:    ret void
1642 //
1643 //
1644 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
1645 // CHECK3-SAME: () #[[ATTR0]] {
1646 // CHECK3-NEXT:  entry:
1647 // CHECK3-NEXT:    call void @__tgt_register_requires(i64 1)
1648 // CHECK3-NEXT:    ret void
1649 //
1650 //
1651 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init
1652 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] {
1653 // CHECK5-NEXT:  entry:
1654 // CHECK5-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
1655 // CHECK5-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
1656 // CHECK5-NEXT:    ret void
1657 //
1658 //
1659 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
1660 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
1661 // CHECK5-NEXT:  entry:
1662 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1663 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1664 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1665 // CHECK5-NEXT:    call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
1666 // CHECK5-NEXT:    ret void
1667 //
1668 //
1669 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
1670 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1671 // CHECK5-NEXT:  entry:
1672 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1673 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1674 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1675 // CHECK5-NEXT:    call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
1676 // CHECK5-NEXT:    ret void
1677 //
1678 //
1679 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
1680 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1681 // CHECK5-NEXT:  entry:
1682 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1683 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1684 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1685 // CHECK5-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
1686 // CHECK5-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
1687 // CHECK5-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
1688 // CHECK5-NEXT:    store float [[CONV]], ptr [[F]], align 4
1689 // CHECK5-NEXT:    ret void
1690 //
1691 //
1692 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
1693 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1694 // CHECK5-NEXT:  entry:
1695 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1696 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1697 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1698 // CHECK5-NEXT:    ret void
1699 //
1700 //
1701 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
1702 // CHECK5-SAME: () #[[ATTR0]] {
1703 // CHECK5-NEXT:  entry:
1704 // CHECK5-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
1705 // CHECK5-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)
1706 // CHECK5-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
1707 // CHECK5-NEXT:    ret void
1708 //
1709 //
1710 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
1711 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1712 // CHECK5-NEXT:  entry:
1713 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1714 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
1715 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1716 // CHECK5-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
1717 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1718 // CHECK5-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
1719 // CHECK5-NEXT:    call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
1720 // CHECK5-NEXT:    ret void
1721 //
1722 //
1723 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
1724 // CHECK5-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {
1725 // CHECK5-NEXT:  entry:
1726 // CHECK5-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
1727 // CHECK5-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
1728 // CHECK5-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1729 // CHECK5:       arraydestroy.body:
1730 // CHECK5-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1731 // CHECK5-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1732 // CHECK5-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1733 // CHECK5-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr
1734 // CHECK5-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
1735 // CHECK5:       arraydestroy.done1:
1736 // CHECK5-NEXT:    ret void
1737 //
1738 //
1739 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
1740 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1741 // CHECK5-NEXT:  entry:
1742 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1743 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
1744 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1745 // CHECK5-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
1746 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1747 // CHECK5-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
1748 // CHECK5-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
1749 // CHECK5-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
1750 // CHECK5-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
1751 // CHECK5-NEXT:    [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
1752 // CHECK5-NEXT:    store float [[ADD]], ptr [[F]], align 4
1753 // CHECK5-NEXT:    ret void
1754 //
1755 //
1756 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
1757 // CHECK5-SAME: () #[[ATTR0]] {
1758 // CHECK5-NEXT:  entry:
1759 // CHECK5-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)
1760 // CHECK5-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]
1761 // CHECK5-NEXT:    ret void
1762 //
1763 //
1764 // CHECK5-LABEL: define {{[^@]+}}@main
1765 // CHECK5-SAME: () #[[ATTR3:[0-9]+]] {
1766 // CHECK5-NEXT:  entry:
1767 // CHECK5-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
1768 // CHECK5-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
1769 // CHECK5-NEXT:    store i32 0, ptr [[RETVAL]], align 4
1770 // CHECK5-NEXT:    call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])
1771 // CHECK5-NEXT:    ret i32 0
1772 //
1773 //
1774 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104
1775 // CHECK5-SAME: () #[[ATTR5:[0-9]+]] {
1776 // CHECK5-NEXT:  entry:
1777 // CHECK5-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104.omp_outlined)
1778 // CHECK5-NEXT:    ret void
1779 //
1780 //
1781 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104.omp_outlined
1782 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] {
1783 // CHECK5-NEXT:  entry:
1784 // CHECK5-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1785 // CHECK5-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1786 // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1787 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1788 // CHECK5-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 8
1789 // CHECK5-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
1790 // CHECK5-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
1791 // CHECK5-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1792 // CHECK5-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1793 // CHECK5-NEXT:    [[G:%.*]] = alloca i32, align 4
1794 // CHECK5-NEXT:    [[G1:%.*]] = alloca i32, align 4
1795 // CHECK5-NEXT:    [[_TMP2:%.*]] = alloca ptr, align 8
1796 // CHECK5-NEXT:    [[SIVAR:%.*]] = alloca i32, align 4
1797 // CHECK5-NEXT:    [[I:%.*]] = alloca i32, align 4
1798 // CHECK5-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1799 // CHECK5-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1800 // CHECK5-NEXT:    store ptr undef, ptr [[_TMP1]], align 8
1801 // CHECK5-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
1802 // CHECK5-NEXT:    store i32 1, ptr [[DOTOMP_COMB_UB]], align 4
1803 // CHECK5-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1804 // CHECK5-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1805 // CHECK5-NEXT:    store ptr [[G1]], ptr [[_TMP2]], align 8
1806 // CHECK5-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1807 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
1808 // CHECK5-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
1809 // CHECK5-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1810 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
1811 // CHECK5-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1812 // CHECK5:       cond.true:
1813 // CHECK5-NEXT:    br label [[COND_END:%.*]]
1814 // CHECK5:       cond.false:
1815 // CHECK5-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1816 // CHECK5-NEXT:    br label [[COND_END]]
1817 // CHECK5:       cond.end:
1818 // CHECK5-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
1819 // CHECK5-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
1820 // CHECK5-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
1821 // CHECK5-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
1822 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1823 // CHECK5:       omp.inner.for.cond:
1824 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1825 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1826 // CHECK5-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
1827 // CHECK5-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1828 // CHECK5:       omp.inner.for.body:
1829 // CHECK5-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
1830 // CHECK5-NEXT:    [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
1831 // CHECK5-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1832 // CHECK5-NEXT:    [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
1833 // CHECK5-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]])
1834 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1835 // CHECK5:       omp.inner.for.inc:
1836 // CHECK5-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1837 // CHECK5-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
1838 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
1839 // CHECK5-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
1840 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]]
1841 // CHECK5:       omp.inner.for.end:
1842 // CHECK5-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1843 // CHECK5:       omp.loop.exit:
1844 // CHECK5-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB2:[0-9]+]], i32 [[TMP1]])
1845 // CHECK5-NEXT:    ret void
1846 //
1847 //
1848 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104.omp_outlined.omp_outlined
1849 // CHECK5-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR5]] {
1850 // CHECK5-NEXT:  entry:
1851 // CHECK5-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1852 // CHECK5-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1853 // CHECK5-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
1854 // CHECK5-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
1855 // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1856 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1857 // CHECK5-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 8
1858 // CHECK5-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1859 // CHECK5-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1860 // CHECK5-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1861 // CHECK5-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1862 // CHECK5-NEXT:    [[G:%.*]] = alloca i32, align 4
1863 // CHECK5-NEXT:    [[G1:%.*]] = alloca i32, align 4
1864 // CHECK5-NEXT:    [[_TMP3:%.*]] = alloca ptr, align 8
1865 // CHECK5-NEXT:    [[SIVAR:%.*]] = alloca i32, align 4
1866 // CHECK5-NEXT:    [[I:%.*]] = alloca i32, align 4
1867 // CHECK5-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8
1868 // CHECK5-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1869 // CHECK5-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1870 // CHECK5-NEXT:    store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
1871 // CHECK5-NEXT:    store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
1872 // CHECK5-NEXT:    store ptr undef, ptr [[_TMP1]], align 8
1873 // CHECK5-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
1874 // CHECK5-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
1875 // CHECK5-NEXT:    [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
1876 // CHECK5-NEXT:    [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
1877 // CHECK5-NEXT:    [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
1878 // CHECK5-NEXT:    [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32
1879 // CHECK5-NEXT:    store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
1880 // CHECK5-NEXT:    store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4
1881 // CHECK5-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1882 // CHECK5-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1883 // CHECK5-NEXT:    store ptr [[G1]], ptr [[_TMP3]], align 8
1884 // CHECK5-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1885 // CHECK5-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
1886 // CHECK5-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
1887 // CHECK5-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1888 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1
1889 // CHECK5-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1890 // CHECK5:       cond.true:
1891 // CHECK5-NEXT:    br label [[COND_END:%.*]]
1892 // CHECK5:       cond.false:
1893 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1894 // CHECK5-NEXT:    br label [[COND_END]]
1895 // CHECK5:       cond.end:
1896 // CHECK5-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
1897 // CHECK5-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
1898 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1899 // CHECK5-NEXT:    store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4
1900 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1901 // CHECK5:       omp.inner.for.cond:
1902 // CHECK5-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1903 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1904 // CHECK5-NEXT:    [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
1905 // CHECK5-NEXT:    br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
1906 // CHECK5:       omp.inner.for.body:
1907 // CHECK5-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1908 // CHECK5-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
1909 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1910 // CHECK5-NEXT:    store i32 [[ADD]], ptr [[I]], align 4
1911 // CHECK5-NEXT:    store i32 1, ptr [[G]], align 4
1912 // CHECK5-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[_TMP3]], align 8
1913 // CHECK5-NEXT:    store volatile i32 1, ptr [[TMP10]], align 4
1914 // CHECK5-NEXT:    store i32 2, ptr [[SIVAR]], align 4
1915 // CHECK5-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0
1916 // CHECK5-NEXT:    store ptr [[G]], ptr [[TMP11]], align 8
1917 // CHECK5-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1
1918 // CHECK5-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[_TMP3]], align 8
1919 // CHECK5-NEXT:    store ptr [[TMP13]], ptr [[TMP12]], align 8
1920 // CHECK5-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2
1921 // CHECK5-NEXT:    store ptr [[SIVAR]], ptr [[TMP14]], align 8
1922 // CHECK5-NEXT:    call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]])
1923 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1924 // CHECK5:       omp.body.continue:
1925 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1926 // CHECK5:       omp.inner.for.inc:
1927 // CHECK5-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
1928 // CHECK5-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP15]], 1
1929 // CHECK5-NEXT:    store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4
1930 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]]
1931 // CHECK5:       omp.inner.for.end:
1932 // CHECK5-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1933 // CHECK5:       omp.loop.exit:
1934 // CHECK5-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP3]])
1935 // CHECK5-NEXT:    ret void
1936 //
1937 //
1938 // CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_target_teams_generic_loop_private_codegen.cpp
1939 // CHECK5-SAME: () #[[ATTR0]] {
1940 // CHECK5-NEXT:  entry:
1941 // CHECK5-NEXT:    call void @__cxx_global_var_init()
1942 // CHECK5-NEXT:    call void @__cxx_global_var_init.1()
1943 // CHECK5-NEXT:    call void @__cxx_global_var_init.2()
1944 // CHECK5-NEXT:    ret void
1945 //
1946 //
1947 // CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
1948 // CHECK5-SAME: () #[[ATTR0]] {
1949 // CHECK5-NEXT:  entry:
1950 // CHECK5-NEXT:    call void @__tgt_register_requires(i64 1)
1951 // CHECK5-NEXT:    ret void
1952 //
1953 //
1954 // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124
1955 // CHECK13-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
1956 // CHECK13-NEXT:  entry:
1957 // CHECK13-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
1958 // CHECK13-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
1959 // CHECK13-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined)
1960 // CHECK13-NEXT:    ret void
1961 //
1962 //
1963 // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined
1964 // CHECK13-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
1965 // CHECK13-NEXT:  entry:
1966 // CHECK13-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1967 // CHECK13-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1968 // CHECK13-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1969 // CHECK13-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1970 // CHECK13-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
1971 // CHECK13-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
1972 // CHECK13-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1973 // CHECK13-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1974 // CHECK13-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
1975 // CHECK13-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
1976 // CHECK13-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
1977 // CHECK13-NEXT:    [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
1978 // CHECK13-NEXT:    [[SIVAR:%.*]] = alloca i32, align 4
1979 // CHECK13-NEXT:    [[I:%.*]] = alloca i32, align 4
1980 // CHECK13-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1981 // CHECK13-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1982 // CHECK13-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
1983 // CHECK13-NEXT:    store i32 1, ptr [[DOTOMP_COMB_UB]], align 4
1984 // CHECK13-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1985 // CHECK13-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1986 // CHECK13-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
1987 // CHECK13-NEXT:    [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2
1988 // CHECK13-NEXT:    br label [[ARRAYCTOR_LOOP:%.*]]
1989 // CHECK13:       arrayctor.loop:
1990 // CHECK13-NEXT:    [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1991 // CHECK13-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4:[0-9]+]]
1992 // CHECK13-NEXT:    [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1
1993 // CHECK13-NEXT:    [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1994 // CHECK13-NEXT:    br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1995 // CHECK13:       arrayctor.cont:
1996 // CHECK13-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]]
1997 // CHECK13-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1998 // CHECK13-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
1999 // CHECK13-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
2000 // CHECK13-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2001 // CHECK13-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
2002 // CHECK13-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2003 // CHECK13:       cond.true:
2004 // CHECK13-NEXT:    br label [[COND_END:%.*]]
2005 // CHECK13:       cond.false:
2006 // CHECK13-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2007 // CHECK13-NEXT:    br label [[COND_END]]
2008 // CHECK13:       cond.end:
2009 // CHECK13-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
2010 // CHECK13-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
2011 // CHECK13-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
2012 // CHECK13-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
2013 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2014 // CHECK13:       omp.inner.for.cond:
2015 // CHECK13-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2016 // CHECK13-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2017 // CHECK13-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
2018 // CHECK13-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2019 // CHECK13:       omp.inner.for.cond.cleanup:
2020 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
2021 // CHECK13:       omp.inner.for.body:
2022 // CHECK13-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
2023 // CHECK13-NEXT:    [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
2024 // CHECK13-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2025 // CHECK13-NEXT:    [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
2026 // CHECK13-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]])
2027 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2028 // CHECK13:       omp.inner.for.inc:
2029 // CHECK13-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2030 // CHECK13-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
2031 // CHECK13-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
2032 // CHECK13-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
2033 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND]]
2034 // CHECK13:       omp.inner.for.end:
2035 // CHECK13-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2036 // CHECK13:       omp.loop.exit:
2037 // CHECK13-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
2038 // CHECK13-NEXT:    [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4
2039 // CHECK13-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB2:[0-9]+]], i32 [[TMP14]])
2040 // CHECK13-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5:[0-9]+]]
2041 // CHECK13-NEXT:    [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
2042 // CHECK13-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN2]], i64 2
2043 // CHECK13-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
2044 // CHECK13:       arraydestroy.body:
2045 // CHECK13-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2046 // CHECK13-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
2047 // CHECK13-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]]
2048 // CHECK13-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]]
2049 // CHECK13-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]]
2050 // CHECK13:       arraydestroy.done3:
2051 // CHECK13-NEXT:    ret void
2052 //
2053 //
2054 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
2055 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
2056 // CHECK13-NEXT:  entry:
2057 // CHECK13-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2058 // CHECK13-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2059 // CHECK13-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2060 // CHECK13-NEXT:    call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
2061 // CHECK13-NEXT:    ret void
2062 //
2063 //
2064 // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined.omp_outlined
2065 // CHECK13-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] {
2066 // CHECK13-NEXT:  entry:
2067 // CHECK13-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
2068 // CHECK13-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
2069 // CHECK13-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
2070 // CHECK13-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
2071 // CHECK13-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2072 // CHECK13-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2073 // CHECK13-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2074 // CHECK13-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2075 // CHECK13-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2076 // CHECK13-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2077 // CHECK13-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
2078 // CHECK13-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
2079 // CHECK13-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
2080 // CHECK13-NEXT:    [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
2081 // CHECK13-NEXT:    [[SIVAR:%.*]] = alloca i32, align 4
2082 // CHECK13-NEXT:    [[I:%.*]] = alloca i32, align 4
2083 // CHECK13-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
2084 // CHECK13-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
2085 // CHECK13-NEXT:    store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
2086 // CHECK13-NEXT:    store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
2087 // CHECK13-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
2088 // CHECK13-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
2089 // CHECK13-NEXT:    [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
2090 // CHECK13-NEXT:    [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
2091 // CHECK13-NEXT:    [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
2092 // CHECK13-NEXT:    [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
2093 // CHECK13-NEXT:    store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
2094 // CHECK13-NEXT:    store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4
2095 // CHECK13-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
2096 // CHECK13-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2097 // CHECK13-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
2098 // CHECK13-NEXT:    [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2
2099 // CHECK13-NEXT:    br label [[ARRAYCTOR_LOOP:%.*]]
2100 // CHECK13:       arrayctor.loop:
2101 // CHECK13-NEXT:    [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
2102 // CHECK13-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]]
2103 // CHECK13-NEXT:    [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1
2104 // CHECK13-NEXT:    [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
2105 // CHECK13-NEXT:    br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
2106 // CHECK13:       arrayctor.cont:
2107 // CHECK13-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]]
2108 // CHECK13-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
2109 // CHECK13-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
2110 // CHECK13-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
2111 // CHECK13-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2112 // CHECK13-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1
2113 // CHECK13-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2114 // CHECK13:       cond.true:
2115 // CHECK13-NEXT:    br label [[COND_END:%.*]]
2116 // CHECK13:       cond.false:
2117 // CHECK13-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2118 // CHECK13-NEXT:    br label [[COND_END]]
2119 // CHECK13:       cond.end:
2120 // CHECK13-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
2121 // CHECK13-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
2122 // CHECK13-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
2123 // CHECK13-NEXT:    store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4
2124 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2125 // CHECK13:       omp.inner.for.cond:
2126 // CHECK13-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2127 // CHECK13-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2128 // CHECK13-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
2129 // CHECK13-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2130 // CHECK13:       omp.inner.for.cond.cleanup:
2131 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
2132 // CHECK13:       omp.inner.for.body:
2133 // CHECK13-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2134 // CHECK13-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
2135 // CHECK13-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2136 // CHECK13-NEXT:    store i32 [[ADD]], ptr [[I]], align 4
2137 // CHECK13-NEXT:    [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4
2138 // CHECK13-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 4
2139 // CHECK13-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64
2140 // CHECK13-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]]
2141 // CHECK13-NEXT:    store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4
2142 // CHECK13-NEXT:    [[TMP12:%.*]] = load i32, ptr [[I]], align 4
2143 // CHECK13-NEXT:    [[IDXPROM3:%.*]] = sext i32 [[TMP12]] to i64
2144 // CHECK13-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM3]]
2145 // CHECK13-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[VAR]], i64 4, i1 false)
2146 // CHECK13-NEXT:    [[TMP13:%.*]] = load i32, ptr [[I]], align 4
2147 // CHECK13-NEXT:    [[TMP14:%.*]] = load i32, ptr [[SIVAR]], align 4
2148 // CHECK13-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP14]], [[TMP13]]
2149 // CHECK13-NEXT:    store i32 [[ADD5]], ptr [[SIVAR]], align 4
2150 // CHECK13-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2151 // CHECK13:       omp.body.continue:
2152 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2153 // CHECK13:       omp.inner.for.inc:
2154 // CHECK13-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2155 // CHECK13-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP15]], 1
2156 // CHECK13-NEXT:    store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4
2157 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND]]
2158 // CHECK13:       omp.inner.for.end:
2159 // CHECK13-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2160 // CHECK13:       omp.loop.exit:
2161 // CHECK13-NEXT:    [[TMP16:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
2162 // CHECK13-NEXT:    [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 4
2163 // CHECK13-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP17]])
2164 // CHECK13-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]]
2165 // CHECK13-NEXT:    [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
2166 // CHECK13-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i64 2
2167 // CHECK13-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
2168 // CHECK13:       arraydestroy.body:
2169 // CHECK13-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP18]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2170 // CHECK13-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
2171 // CHECK13-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]]
2172 // CHECK13-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]
2173 // CHECK13-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]
2174 // CHECK13:       arraydestroy.done8:
2175 // CHECK13-NEXT:    ret void
2176 //
2177 //
2178 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
2179 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
2180 // CHECK13-NEXT:  entry:
2181 // CHECK13-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2182 // CHECK13-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2183 // CHECK13-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2184 // CHECK13-NEXT:    call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]]
2185 // CHECK13-NEXT:    ret void
2186 //
2187 //
2188 // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80
2189 // CHECK13-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
2190 // CHECK13-NEXT:  entry:
2191 // CHECK13-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
2192 // CHECK13-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
2193 // CHECK13-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined)
2194 // CHECK13-NEXT:    ret void
2195 //
2196 //
2197 // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined
2198 // CHECK13-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
2199 // CHECK13-NEXT:  entry:
2200 // CHECK13-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
2201 // CHECK13-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
2202 // CHECK13-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2203 // CHECK13-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2204 // CHECK13-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 8
2205 // CHECK13-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
2206 // CHECK13-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
2207 // CHECK13-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2208 // CHECK13-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2209 // CHECK13-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
2210 // CHECK13-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
2211 // CHECK13-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
2212 // CHECK13-NEXT:    [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
2213 // CHECK13-NEXT:    [[_TMP2:%.*]] = alloca ptr, align 8
2214 // CHECK13-NEXT:    [[I:%.*]] = alloca i32, align 4
2215 // CHECK13-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
2216 // CHECK13-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
2217 // CHECK13-NEXT:    store ptr undef, ptr [[_TMP1]], align 8
2218 // CHECK13-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
2219 // CHECK13-NEXT:    store i32 1, ptr [[DOTOMP_COMB_UB]], align 4
2220 // CHECK13-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
2221 // CHECK13-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2222 // CHECK13-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
2223 // CHECK13-NEXT:    [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2
2224 // CHECK13-NEXT:    br label [[ARRAYCTOR_LOOP:%.*]]
2225 // CHECK13:       arrayctor.loop:
2226 // CHECK13-NEXT:    [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
2227 // CHECK13-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]]
2228 // CHECK13-NEXT:    [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i64 1
2229 // CHECK13-NEXT:    [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
2230 // CHECK13-NEXT:    br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
2231 // CHECK13:       arrayctor.cont:
2232 // CHECK13-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]]
2233 // CHECK13-NEXT:    store ptr [[VAR]], ptr [[_TMP2]], align 8
2234 // CHECK13-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
2235 // CHECK13-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
2236 // CHECK13-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
2237 // CHECK13-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2238 // CHECK13-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
2239 // CHECK13-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2240 // CHECK13:       cond.true:
2241 // CHECK13-NEXT:    br label [[COND_END:%.*]]
2242 // CHECK13:       cond.false:
2243 // CHECK13-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2244 // CHECK13-NEXT:    br label [[COND_END]]
2245 // CHECK13:       cond.end:
2246 // CHECK13-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
2247 // CHECK13-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
2248 // CHECK13-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
2249 // CHECK13-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
2250 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2251 // CHECK13:       omp.inner.for.cond:
2252 // CHECK13-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2253 // CHECK13-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2254 // CHECK13-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
2255 // CHECK13-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2256 // CHECK13:       omp.inner.for.cond.cleanup:
2257 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
2258 // CHECK13:       omp.inner.for.body:
2259 // CHECK13-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
2260 // CHECK13-NEXT:    [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
2261 // CHECK13-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2262 // CHECK13-NEXT:    [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
2263 // CHECK13-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]])
2264 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2265 // CHECK13:       omp.inner.for.inc:
2266 // CHECK13-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2267 // CHECK13-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
2268 // CHECK13-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
2269 // CHECK13-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
2270 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND]]
2271 // CHECK13:       omp.inner.for.end:
2272 // CHECK13-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2273 // CHECK13:       omp.loop.exit:
2274 // CHECK13-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
2275 // CHECK13-NEXT:    [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4
2276 // CHECK13-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP14]])
2277 // CHECK13-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]]
2278 // CHECK13-NEXT:    [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
2279 // CHECK13-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN4]], i64 2
2280 // CHECK13-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
2281 // CHECK13:       arraydestroy.body:
2282 // CHECK13-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2283 // CHECK13-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
2284 // CHECK13-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]]
2285 // CHECK13-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]]
2286 // CHECK13-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]]
2287 // CHECK13:       arraydestroy.done5:
2288 // CHECK13-NEXT:    ret void
2289 //
2290 //
2291 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
2292 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
2293 // CHECK13-NEXT:  entry:
2294 // CHECK13-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2295 // CHECK13-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2296 // CHECK13-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2297 // CHECK13-NEXT:    call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
2298 // CHECK13-NEXT:    ret void
2299 //
2300 //
2301 // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined.omp_outlined
2302 // CHECK13-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] {
2303 // CHECK13-NEXT:  entry:
2304 // CHECK13-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
2305 // CHECK13-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
2306 // CHECK13-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
2307 // CHECK13-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
2308 // CHECK13-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2309 // CHECK13-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2310 // CHECK13-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 8
2311 // CHECK13-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2312 // CHECK13-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2313 // CHECK13-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2314 // CHECK13-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2315 // CHECK13-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
2316 // CHECK13-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
2317 // CHECK13-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
2318 // CHECK13-NEXT:    [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
2319 // CHECK13-NEXT:    [[_TMP3:%.*]] = alloca ptr, align 8
2320 // CHECK13-NEXT:    [[I:%.*]] = alloca i32, align 4
2321 // CHECK13-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
2322 // CHECK13-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
2323 // CHECK13-NEXT:    store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
2324 // CHECK13-NEXT:    store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
2325 // CHECK13-NEXT:    store ptr undef, ptr [[_TMP1]], align 8
2326 // CHECK13-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
2327 // CHECK13-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
2328 // CHECK13-NEXT:    [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
2329 // CHECK13-NEXT:    [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
2330 // CHECK13-NEXT:    [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
2331 // CHECK13-NEXT:    [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32
2332 // CHECK13-NEXT:    store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
2333 // CHECK13-NEXT:    store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4
2334 // CHECK13-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
2335 // CHECK13-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2336 // CHECK13-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
2337 // CHECK13-NEXT:    [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2
2338 // CHECK13-NEXT:    br label [[ARRAYCTOR_LOOP:%.*]]
2339 // CHECK13:       arrayctor.loop:
2340 // CHECK13-NEXT:    [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
2341 // CHECK13-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]]
2342 // CHECK13-NEXT:    [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i64 1
2343 // CHECK13-NEXT:    [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
2344 // CHECK13-NEXT:    br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
2345 // CHECK13:       arrayctor.cont:
2346 // CHECK13-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]]
2347 // CHECK13-NEXT:    store ptr [[VAR]], ptr [[_TMP3]], align 8
2348 // CHECK13-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
2349 // CHECK13-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
2350 // CHECK13-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
2351 // CHECK13-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2352 // CHECK13-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1
2353 // CHECK13-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2354 // CHECK13:       cond.true:
2355 // CHECK13-NEXT:    br label [[COND_END:%.*]]
2356 // CHECK13:       cond.false:
2357 // CHECK13-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2358 // CHECK13-NEXT:    br label [[COND_END]]
2359 // CHECK13:       cond.end:
2360 // CHECK13-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
2361 // CHECK13-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
2362 // CHECK13-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
2363 // CHECK13-NEXT:    store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4
2364 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2365 // CHECK13:       omp.inner.for.cond:
2366 // CHECK13-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2367 // CHECK13-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2368 // CHECK13-NEXT:    [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
2369 // CHECK13-NEXT:    br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2370 // CHECK13:       omp.inner.for.cond.cleanup:
2371 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
2372 // CHECK13:       omp.inner.for.body:
2373 // CHECK13-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2374 // CHECK13-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
2375 // CHECK13-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2376 // CHECK13-NEXT:    store i32 [[ADD]], ptr [[I]], align 4
2377 // CHECK13-NEXT:    [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4
2378 // CHECK13-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 4
2379 // CHECK13-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64
2380 // CHECK13-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]]
2381 // CHECK13-NEXT:    store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4
2382 // CHECK13-NEXT:    [[TMP12:%.*]] = load ptr, ptr [[_TMP3]], align 8
2383 // CHECK13-NEXT:    [[TMP13:%.*]] = load i32, ptr [[I]], align 4
2384 // CHECK13-NEXT:    [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64
2385 // CHECK13-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM5]]
2386 // CHECK13-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX6]], ptr align 4 [[TMP12]], i64 4, i1 false)
2387 // CHECK13-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2388 // CHECK13:       omp.body.continue:
2389 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2390 // CHECK13:       omp.inner.for.inc:
2391 // CHECK13-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2392 // CHECK13-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP14]], 1
2393 // CHECK13-NEXT:    store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4
2394 // CHECK13-NEXT:    br label [[OMP_INNER_FOR_COND]]
2395 // CHECK13:       omp.inner.for.end:
2396 // CHECK13-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2397 // CHECK13:       omp.loop.exit:
2398 // CHECK13-NEXT:    [[TMP15:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
2399 // CHECK13-NEXT:    [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 4
2400 // CHECK13-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP16]])
2401 // CHECK13-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]]
2402 // CHECK13-NEXT:    [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
2403 // CHECK13-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN8]], i64 2
2404 // CHECK13-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
2405 // CHECK13:       arraydestroy.body:
2406 // CHECK13-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2407 // CHECK13-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
2408 // CHECK13-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]]
2409 // CHECK13-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]]
2410 // CHECK13-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]]
2411 // CHECK13:       arraydestroy.done9:
2412 // CHECK13-NEXT:    ret void
2413 //
2414 //
2415 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
2416 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
2417 // CHECK13-NEXT:  entry:
2418 // CHECK13-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2419 // CHECK13-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2420 // CHECK13-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2421 // CHECK13-NEXT:    call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]]
2422 // CHECK13-NEXT:    ret void
2423 //
2424 //
2425 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
2426 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
2427 // CHECK13-NEXT:  entry:
2428 // CHECK13-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2429 // CHECK13-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2430 // CHECK13-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2431 // CHECK13-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
2432 // CHECK13-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
2433 // CHECK13-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
2434 // CHECK13-NEXT:    store float [[CONV]], ptr [[F]], align 4
2435 // CHECK13-NEXT:    ret void
2436 //
2437 //
2438 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
2439 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
2440 // CHECK13-NEXT:  entry:
2441 // CHECK13-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2442 // CHECK13-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2443 // CHECK13-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2444 // CHECK13-NEXT:    ret void
2445 //
2446 //
2447 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
2448 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
2449 // CHECK13-NEXT:  entry:
2450 // CHECK13-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2451 // CHECK13-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2452 // CHECK13-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2453 // CHECK13-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
2454 // CHECK13-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
2455 // CHECK13-NEXT:    store i32 [[TMP0]], ptr [[F]], align 4
2456 // CHECK13-NEXT:    ret void
2457 //
2458 //
2459 // CHECK13-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
2460 // CHECK13-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
2461 // CHECK13-NEXT:  entry:
2462 // CHECK13-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2463 // CHECK13-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2464 // CHECK13-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2465 // CHECK13-NEXT:    ret void
2466 //
2467 //
2468 // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124
2469 // CHECK15-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
2470 // CHECK15-NEXT:  entry:
2471 // CHECK15-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
2472 // CHECK15-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
2473 // CHECK15-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined)
2474 // CHECK15-NEXT:    ret void
2475 //
2476 //
2477 // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined
2478 // CHECK15-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
2479 // CHECK15-NEXT:  entry:
2480 // CHECK15-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
2481 // CHECK15-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
2482 // CHECK15-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2483 // CHECK15-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2484 // CHECK15-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
2485 // CHECK15-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
2486 // CHECK15-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2487 // CHECK15-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2488 // CHECK15-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
2489 // CHECK15-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
2490 // CHECK15-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
2491 // CHECK15-NEXT:    [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
2492 // CHECK15-NEXT:    [[SIVAR:%.*]] = alloca i32, align 4
2493 // CHECK15-NEXT:    [[I:%.*]] = alloca i32, align 4
2494 // CHECK15-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
2495 // CHECK15-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
2496 // CHECK15-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
2497 // CHECK15-NEXT:    store i32 1, ptr [[DOTOMP_COMB_UB]], align 4
2498 // CHECK15-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
2499 // CHECK15-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2500 // CHECK15-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
2501 // CHECK15-NEXT:    [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2
2502 // CHECK15-NEXT:    br label [[ARRAYCTOR_LOOP:%.*]]
2503 // CHECK15:       arrayctor.loop:
2504 // CHECK15-NEXT:    [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
2505 // CHECK15-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4:[0-9]+]]
2506 // CHECK15-NEXT:    [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i32 1
2507 // CHECK15-NEXT:    [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
2508 // CHECK15-NEXT:    br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
2509 // CHECK15:       arrayctor.cont:
2510 // CHECK15-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]]
2511 // CHECK15-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
2512 // CHECK15-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
2513 // CHECK15-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
2514 // CHECK15-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2515 // CHECK15-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
2516 // CHECK15-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2517 // CHECK15:       cond.true:
2518 // CHECK15-NEXT:    br label [[COND_END:%.*]]
2519 // CHECK15:       cond.false:
2520 // CHECK15-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2521 // CHECK15-NEXT:    br label [[COND_END]]
2522 // CHECK15:       cond.end:
2523 // CHECK15-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
2524 // CHECK15-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
2525 // CHECK15-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
2526 // CHECK15-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
2527 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2528 // CHECK15:       omp.inner.for.cond:
2529 // CHECK15-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2530 // CHECK15-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2531 // CHECK15-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
2532 // CHECK15-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2533 // CHECK15:       omp.inner.for.cond.cleanup:
2534 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
2535 // CHECK15:       omp.inner.for.body:
2536 // CHECK15-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
2537 // CHECK15-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2538 // CHECK15-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined.omp_outlined, i32 [[TMP7]], i32 [[TMP8]])
2539 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2540 // CHECK15:       omp.inner.for.inc:
2541 // CHECK15-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2542 // CHECK15-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
2543 // CHECK15-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]]
2544 // CHECK15-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
2545 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND]]
2546 // CHECK15:       omp.inner.for.end:
2547 // CHECK15-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2548 // CHECK15:       omp.loop.exit:
2549 // CHECK15-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
2550 // CHECK15-NEXT:    [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4
2551 // CHECK15-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB2:[0-9]+]], i32 [[TMP12]])
2552 // CHECK15-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5:[0-9]+]]
2553 // CHECK15-NEXT:    [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
2554 // CHECK15-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN2]], i32 2
2555 // CHECK15-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
2556 // CHECK15:       arraydestroy.body:
2557 // CHECK15-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP13]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2558 // CHECK15-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2559 // CHECK15-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]]
2560 // CHECK15-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]]
2561 // CHECK15-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]]
2562 // CHECK15:       arraydestroy.done3:
2563 // CHECK15-NEXT:    ret void
2564 //
2565 //
2566 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
2567 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
2568 // CHECK15-NEXT:  entry:
2569 // CHECK15-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2570 // CHECK15-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2571 // CHECK15-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2572 // CHECK15-NEXT:    call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
2573 // CHECK15-NEXT:    ret void
2574 //
2575 //
2576 // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l124.omp_outlined.omp_outlined
2577 // CHECK15-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] {
2578 // CHECK15-NEXT:  entry:
2579 // CHECK15-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
2580 // CHECK15-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
2581 // CHECK15-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
2582 // CHECK15-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
2583 // CHECK15-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2584 // CHECK15-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2585 // CHECK15-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2586 // CHECK15-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2587 // CHECK15-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2588 // CHECK15-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2589 // CHECK15-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
2590 // CHECK15-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
2591 // CHECK15-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
2592 // CHECK15-NEXT:    [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
2593 // CHECK15-NEXT:    [[SIVAR:%.*]] = alloca i32, align 4
2594 // CHECK15-NEXT:    [[I:%.*]] = alloca i32, align 4
2595 // CHECK15-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
2596 // CHECK15-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
2597 // CHECK15-NEXT:    store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4
2598 // CHECK15-NEXT:    store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
2599 // CHECK15-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
2600 // CHECK15-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
2601 // CHECK15-NEXT:    [[TMP0:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4
2602 // CHECK15-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
2603 // CHECK15-NEXT:    store i32 [[TMP0]], ptr [[DOTOMP_LB]], align 4
2604 // CHECK15-NEXT:    store i32 [[TMP1]], ptr [[DOTOMP_UB]], align 4
2605 // CHECK15-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
2606 // CHECK15-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2607 // CHECK15-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
2608 // CHECK15-NEXT:    [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2
2609 // CHECK15-NEXT:    br label [[ARRAYCTOR_LOOP:%.*]]
2610 // CHECK15:       arrayctor.loop:
2611 // CHECK15-NEXT:    [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
2612 // CHECK15-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]]
2613 // CHECK15-NEXT:    [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i32 1
2614 // CHECK15-NEXT:    [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
2615 // CHECK15-NEXT:    br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
2616 // CHECK15:       arrayctor.cont:
2617 // CHECK15-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]]
2618 // CHECK15-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
2619 // CHECK15-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
2620 // CHECK15-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
2621 // CHECK15-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2622 // CHECK15-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1
2623 // CHECK15-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2624 // CHECK15:       cond.true:
2625 // CHECK15-NEXT:    br label [[COND_END:%.*]]
2626 // CHECK15:       cond.false:
2627 // CHECK15-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2628 // CHECK15-NEXT:    br label [[COND_END]]
2629 // CHECK15:       cond.end:
2630 // CHECK15-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
2631 // CHECK15-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
2632 // CHECK15-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
2633 // CHECK15-NEXT:    store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4
2634 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2635 // CHECK15:       omp.inner.for.cond:
2636 // CHECK15-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2637 // CHECK15-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2638 // CHECK15-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
2639 // CHECK15-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2640 // CHECK15:       omp.inner.for.cond.cleanup:
2641 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
2642 // CHECK15:       omp.inner.for.body:
2643 // CHECK15-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2644 // CHECK15-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
2645 // CHECK15-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2646 // CHECK15-NEXT:    store i32 [[ADD]], ptr [[I]], align 4
2647 // CHECK15-NEXT:    [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4
2648 // CHECK15-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 4
2649 // CHECK15-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP11]]
2650 // CHECK15-NEXT:    store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4
2651 // CHECK15-NEXT:    [[TMP12:%.*]] = load i32, ptr [[I]], align 4
2652 // CHECK15-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP12]]
2653 // CHECK15-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[VAR]], i32 4, i1 false)
2654 // CHECK15-NEXT:    [[TMP13:%.*]] = load i32, ptr [[I]], align 4
2655 // CHECK15-NEXT:    [[TMP14:%.*]] = load i32, ptr [[SIVAR]], align 4
2656 // CHECK15-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP14]], [[TMP13]]
2657 // CHECK15-NEXT:    store i32 [[ADD3]], ptr [[SIVAR]], align 4
2658 // CHECK15-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2659 // CHECK15:       omp.body.continue:
2660 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2661 // CHECK15:       omp.inner.for.inc:
2662 // CHECK15-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2663 // CHECK15-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP15]], 1
2664 // CHECK15-NEXT:    store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4
2665 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND]]
2666 // CHECK15:       omp.inner.for.end:
2667 // CHECK15-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2668 // CHECK15:       omp.loop.exit:
2669 // CHECK15-NEXT:    [[TMP16:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
2670 // CHECK15-NEXT:    [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 4
2671 // CHECK15-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP17]])
2672 // CHECK15-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]]
2673 // CHECK15-NEXT:    [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
2674 // CHECK15-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN5]], i32 2
2675 // CHECK15-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
2676 // CHECK15:       arraydestroy.body:
2677 // CHECK15-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP18]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2678 // CHECK15-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2679 // CHECK15-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]]
2680 // CHECK15-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]]
2681 // CHECK15-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]]
2682 // CHECK15:       arraydestroy.done6:
2683 // CHECK15-NEXT:    ret void
2684 //
2685 //
2686 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
2687 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2688 // CHECK15-NEXT:  entry:
2689 // CHECK15-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2690 // CHECK15-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2691 // CHECK15-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2692 // CHECK15-NEXT:    call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]]
2693 // CHECK15-NEXT:    ret void
2694 //
2695 //
2696 // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80
2697 // CHECK15-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
2698 // CHECK15-NEXT:  entry:
2699 // CHECK15-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
2700 // CHECK15-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
2701 // CHECK15-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined)
2702 // CHECK15-NEXT:    ret void
2703 //
2704 //
2705 // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined
2706 // CHECK15-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
2707 // CHECK15-NEXT:  entry:
2708 // CHECK15-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
2709 // CHECK15-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
2710 // CHECK15-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2711 // CHECK15-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2712 // CHECK15-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 4
2713 // CHECK15-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
2714 // CHECK15-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
2715 // CHECK15-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2716 // CHECK15-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2717 // CHECK15-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
2718 // CHECK15-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
2719 // CHECK15-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
2720 // CHECK15-NEXT:    [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
2721 // CHECK15-NEXT:    [[_TMP2:%.*]] = alloca ptr, align 4
2722 // CHECK15-NEXT:    [[I:%.*]] = alloca i32, align 4
2723 // CHECK15-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
2724 // CHECK15-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
2725 // CHECK15-NEXT:    store ptr undef, ptr [[_TMP1]], align 4
2726 // CHECK15-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
2727 // CHECK15-NEXT:    store i32 1, ptr [[DOTOMP_COMB_UB]], align 4
2728 // CHECK15-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
2729 // CHECK15-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2730 // CHECK15-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
2731 // CHECK15-NEXT:    [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2
2732 // CHECK15-NEXT:    br label [[ARRAYCTOR_LOOP:%.*]]
2733 // CHECK15:       arrayctor.loop:
2734 // CHECK15-NEXT:    [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
2735 // CHECK15-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]]
2736 // CHECK15-NEXT:    [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i32 1
2737 // CHECK15-NEXT:    [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
2738 // CHECK15-NEXT:    br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
2739 // CHECK15:       arrayctor.cont:
2740 // CHECK15-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]]
2741 // CHECK15-NEXT:    store ptr [[VAR]], ptr [[_TMP2]], align 4
2742 // CHECK15-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
2743 // CHECK15-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
2744 // CHECK15-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
2745 // CHECK15-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2746 // CHECK15-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
2747 // CHECK15-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2748 // CHECK15:       cond.true:
2749 // CHECK15-NEXT:    br label [[COND_END:%.*]]
2750 // CHECK15:       cond.false:
2751 // CHECK15-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2752 // CHECK15-NEXT:    br label [[COND_END]]
2753 // CHECK15:       cond.end:
2754 // CHECK15-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
2755 // CHECK15-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
2756 // CHECK15-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
2757 // CHECK15-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
2758 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2759 // CHECK15:       omp.inner.for.cond:
2760 // CHECK15-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2761 // CHECK15-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2762 // CHECK15-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
2763 // CHECK15-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2764 // CHECK15:       omp.inner.for.cond.cleanup:
2765 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
2766 // CHECK15:       omp.inner.for.body:
2767 // CHECK15-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
2768 // CHECK15-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2769 // CHECK15-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined.omp_outlined, i32 [[TMP7]], i32 [[TMP8]])
2770 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2771 // CHECK15:       omp.inner.for.inc:
2772 // CHECK15-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2773 // CHECK15-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
2774 // CHECK15-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]]
2775 // CHECK15-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
2776 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND]]
2777 // CHECK15:       omp.inner.for.end:
2778 // CHECK15-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2779 // CHECK15:       omp.loop.exit:
2780 // CHECK15-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
2781 // CHECK15-NEXT:    [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4
2782 // CHECK15-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP12]])
2783 // CHECK15-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]]
2784 // CHECK15-NEXT:    [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
2785 // CHECK15-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN4]], i32 2
2786 // CHECK15-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
2787 // CHECK15:       arraydestroy.body:
2788 // CHECK15-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP13]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2789 // CHECK15-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2790 // CHECK15-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]]
2791 // CHECK15-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]]
2792 // CHECK15-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]]
2793 // CHECK15:       arraydestroy.done5:
2794 // CHECK15-NEXT:    ret void
2795 //
2796 //
2797 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
2798 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2799 // CHECK15-NEXT:  entry:
2800 // CHECK15-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2801 // CHECK15-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2802 // CHECK15-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2803 // CHECK15-NEXT:    call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
2804 // CHECK15-NEXT:    ret void
2805 //
2806 //
2807 // CHECK15-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l80.omp_outlined.omp_outlined
2808 // CHECK15-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] {
2809 // CHECK15-NEXT:  entry:
2810 // CHECK15-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
2811 // CHECK15-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
2812 // CHECK15-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
2813 // CHECK15-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
2814 // CHECK15-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2815 // CHECK15-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2816 // CHECK15-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 4
2817 // CHECK15-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2818 // CHECK15-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2819 // CHECK15-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2820 // CHECK15-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2821 // CHECK15-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
2822 // CHECK15-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
2823 // CHECK15-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
2824 // CHECK15-NEXT:    [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
2825 // CHECK15-NEXT:    [[_TMP2:%.*]] = alloca ptr, align 4
2826 // CHECK15-NEXT:    [[I:%.*]] = alloca i32, align 4
2827 // CHECK15-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
2828 // CHECK15-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
2829 // CHECK15-NEXT:    store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4
2830 // CHECK15-NEXT:    store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
2831 // CHECK15-NEXT:    store ptr undef, ptr [[_TMP1]], align 4
2832 // CHECK15-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
2833 // CHECK15-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
2834 // CHECK15-NEXT:    [[TMP0:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4
2835 // CHECK15-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
2836 // CHECK15-NEXT:    store i32 [[TMP0]], ptr [[DOTOMP_LB]], align 4
2837 // CHECK15-NEXT:    store i32 [[TMP1]], ptr [[DOTOMP_UB]], align 4
2838 // CHECK15-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
2839 // CHECK15-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2840 // CHECK15-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
2841 // CHECK15-NEXT:    [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2
2842 // CHECK15-NEXT:    br label [[ARRAYCTOR_LOOP:%.*]]
2843 // CHECK15:       arrayctor.loop:
2844 // CHECK15-NEXT:    [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
2845 // CHECK15-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]]) #[[ATTR4]]
2846 // CHECK15-NEXT:    [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i32 1
2847 // CHECK15-NEXT:    [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
2848 // CHECK15-NEXT:    br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
2849 // CHECK15:       arrayctor.cont:
2850 // CHECK15-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]]
2851 // CHECK15-NEXT:    store ptr [[VAR]], ptr [[_TMP2]], align 4
2852 // CHECK15-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
2853 // CHECK15-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
2854 // CHECK15-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
2855 // CHECK15-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2856 // CHECK15-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1
2857 // CHECK15-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2858 // CHECK15:       cond.true:
2859 // CHECK15-NEXT:    br label [[COND_END:%.*]]
2860 // CHECK15:       cond.false:
2861 // CHECK15-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2862 // CHECK15-NEXT:    br label [[COND_END]]
2863 // CHECK15:       cond.end:
2864 // CHECK15-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
2865 // CHECK15-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
2866 // CHECK15-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
2867 // CHECK15-NEXT:    store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4
2868 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2869 // CHECK15:       omp.inner.for.cond:
2870 // CHECK15-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2871 // CHECK15-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2872 // CHECK15-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
2873 // CHECK15-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2874 // CHECK15:       omp.inner.for.cond.cleanup:
2875 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
2876 // CHECK15:       omp.inner.for.body:
2877 // CHECK15-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2878 // CHECK15-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
2879 // CHECK15-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2880 // CHECK15-NEXT:    store i32 [[ADD]], ptr [[I]], align 4
2881 // CHECK15-NEXT:    [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4
2882 // CHECK15-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 4
2883 // CHECK15-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP11]]
2884 // CHECK15-NEXT:    store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4
2885 // CHECK15-NEXT:    [[TMP12:%.*]] = load ptr, ptr [[_TMP2]], align 4
2886 // CHECK15-NEXT:    [[TMP13:%.*]] = load i32, ptr [[I]], align 4
2887 // CHECK15-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP13]]
2888 // CHECK15-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP12]], i32 4, i1 false)
2889 // CHECK15-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2890 // CHECK15:       omp.body.continue:
2891 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2892 // CHECK15:       omp.inner.for.inc:
2893 // CHECK15-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
2894 // CHECK15-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1
2895 // CHECK15-NEXT:    store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4
2896 // CHECK15-NEXT:    br label [[OMP_INNER_FOR_COND]]
2897 // CHECK15:       omp.inner.for.end:
2898 // CHECK15-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2899 // CHECK15:       omp.loop.exit:
2900 // CHECK15-NEXT:    [[TMP15:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
2901 // CHECK15-NEXT:    [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 4
2902 // CHECK15-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP16]])
2903 // CHECK15-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]]
2904 // CHECK15-NEXT:    [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
2905 // CHECK15-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN6]], i32 2
2906 // CHECK15-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
2907 // CHECK15:       arraydestroy.body:
2908 // CHECK15-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2909 // CHECK15-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2910 // CHECK15-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]]
2911 // CHECK15-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]]
2912 // CHECK15-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]]
2913 // CHECK15:       arraydestroy.done7:
2914 // CHECK15-NEXT:    ret void
2915 //
2916 //
2917 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
2918 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2919 // CHECK15-NEXT:  entry:
2920 // CHECK15-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2921 // CHECK15-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2922 // CHECK15-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2923 // CHECK15-NEXT:    call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]]
2924 // CHECK15-NEXT:    ret void
2925 //
2926 //
2927 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
2928 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2929 // CHECK15-NEXT:  entry:
2930 // CHECK15-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2931 // CHECK15-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2932 // CHECK15-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2933 // CHECK15-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
2934 // CHECK15-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
2935 // CHECK15-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
2936 // CHECK15-NEXT:    store float [[CONV]], ptr [[F]], align 4
2937 // CHECK15-NEXT:    ret void
2938 //
2939 //
2940 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
2941 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2942 // CHECK15-NEXT:  entry:
2943 // CHECK15-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2944 // CHECK15-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2945 // CHECK15-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2946 // CHECK15-NEXT:    ret void
2947 //
2948 //
2949 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
2950 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2951 // CHECK15-NEXT:  entry:
2952 // CHECK15-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2953 // CHECK15-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2954 // CHECK15-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2955 // CHECK15-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
2956 // CHECK15-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
2957 // CHECK15-NEXT:    store i32 [[TMP0]], ptr [[F]], align 4
2958 // CHECK15-NEXT:    ret void
2959 //
2960 //
2961 // CHECK15-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
2962 // CHECK15-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2963 // CHECK15-NEXT:  entry:
2964 // CHECK15-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2965 // CHECK15-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2966 // CHECK15-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2967 // CHECK15-NEXT:    ret void
2968 //
2969 //
2970 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104
2971 // CHECK17-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
2972 // CHECK17-NEXT:  entry:
2973 // CHECK17-NEXT:    [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
2974 // CHECK17-NEXT:    store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
2975 // CHECK17-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104.omp_outlined)
2976 // CHECK17-NEXT:    ret void
2977 //
2978 //
2979 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104.omp_outlined
2980 // CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
2981 // CHECK17-NEXT:  entry:
2982 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
2983 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
2984 // CHECK17-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2985 // CHECK17-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2986 // CHECK17-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 8
2987 // CHECK17-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
2988 // CHECK17-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
2989 // CHECK17-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2990 // CHECK17-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2991 // CHECK17-NEXT:    [[G:%.*]] = alloca i32, align 4
2992 // CHECK17-NEXT:    [[G1:%.*]] = alloca i32, align 4
2993 // CHECK17-NEXT:    [[_TMP2:%.*]] = alloca ptr, align 8
2994 // CHECK17-NEXT:    [[SIVAR:%.*]] = alloca i32, align 4
2995 // CHECK17-NEXT:    [[I:%.*]] = alloca i32, align 4
2996 // CHECK17-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
2997 // CHECK17-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
2998 // CHECK17-NEXT:    store ptr undef, ptr [[_TMP1]], align 8
2999 // CHECK17-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
3000 // CHECK17-NEXT:    store i32 1, ptr [[DOTOMP_COMB_UB]], align 4
3001 // CHECK17-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
3002 // CHECK17-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
3003 // CHECK17-NEXT:    store ptr [[G1]], ptr [[_TMP2]], align 8
3004 // CHECK17-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
3005 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
3006 // CHECK17-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
3007 // CHECK17-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
3008 // CHECK17-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
3009 // CHECK17-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3010 // CHECK17:       cond.true:
3011 // CHECK17-NEXT:    br label [[COND_END:%.*]]
3012 // CHECK17:       cond.false:
3013 // CHECK17-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
3014 // CHECK17-NEXT:    br label [[COND_END]]
3015 // CHECK17:       cond.end:
3016 // CHECK17-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
3017 // CHECK17-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
3018 // CHECK17-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
3019 // CHECK17-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
3020 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
3021 // CHECK17:       omp.inner.for.cond:
3022 // CHECK17-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3023 // CHECK17-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
3024 // CHECK17-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
3025 // CHECK17-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3026 // CHECK17:       omp.inner.for.body:
3027 // CHECK17-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
3028 // CHECK17-NEXT:    [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
3029 // CHECK17-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
3030 // CHECK17-NEXT:    [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
3031 // CHECK17-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]])
3032 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
3033 // CHECK17:       omp.inner.for.inc:
3034 // CHECK17-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3035 // CHECK17-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
3036 // CHECK17-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
3037 // CHECK17-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
3038 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND]]
3039 // CHECK17:       omp.inner.for.end:
3040 // CHECK17-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
3041 // CHECK17:       omp.loop.exit:
3042 // CHECK17-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB2:[0-9]+]], i32 [[TMP1]])
3043 // CHECK17-NEXT:    ret void
3044 //
3045 //
3046 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l104.omp_outlined.omp_outlined
3047 // CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR0]] {
3048 // CHECK17-NEXT:  entry:
3049 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
3050 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
3051 // CHECK17-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
3052 // CHECK17-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
3053 // CHECK17-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
3054 // CHECK17-NEXT:    [[TMP:%.*]] = alloca i32, align 4
3055 // CHECK17-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 8
3056 // CHECK17-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
3057 // CHECK17-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
3058 // CHECK17-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3059 // CHECK17-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3060 // CHECK17-NEXT:    [[G:%.*]] = alloca i32, align 4
3061 // CHECK17-NEXT:    [[G1:%.*]] = alloca i32, align 4
3062 // CHECK17-NEXT:    [[_TMP3:%.*]] = alloca ptr, align 8
3063 // CHECK17-NEXT:    [[SIVAR:%.*]] = alloca i32, align 4
3064 // CHECK17-NEXT:    [[I:%.*]] = alloca i32, align 4
3065 // CHECK17-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8
3066 // CHECK17-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
3067 // CHECK17-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
3068 // CHECK17-NEXT:    store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
3069 // CHECK17-NEXT:    store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
3070 // CHECK17-NEXT:    store ptr undef, ptr [[_TMP1]], align 8
3071 // CHECK17-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
3072 // CHECK17-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
3073 // CHECK17-NEXT:    [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
3074 // CHECK17-NEXT:    [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
3075 // CHECK17-NEXT:    [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
3076 // CHECK17-NEXT:    [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32
3077 // CHECK17-NEXT:    store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
3078 // CHECK17-NEXT:    store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4
3079 // CHECK17-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
3080 // CHECK17-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
3081 // CHECK17-NEXT:    store ptr [[G1]], ptr [[_TMP3]], align 8
3082 // CHECK17-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
3083 // CHECK17-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
3084 // CHECK17-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
3085 // CHECK17-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
3086 // CHECK17-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1
3087 // CHECK17-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3088 // CHECK17:       cond.true:
3089 // CHECK17-NEXT:    br label [[COND_END:%.*]]
3090 // CHECK17:       cond.false:
3091 // CHECK17-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
3092 // CHECK17-NEXT:    br label [[COND_END]]
3093 // CHECK17:       cond.end:
3094 // CHECK17-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
3095 // CHECK17-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
3096 // CHECK17-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
3097 // CHECK17-NEXT:    store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4
3098 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
3099 // CHECK17:       omp.inner.for.cond:
3100 // CHECK17-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3101 // CHECK17-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
3102 // CHECK17-NEXT:    [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
3103 // CHECK17-NEXT:    br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3104 // CHECK17:       omp.inner.for.body:
3105 // CHECK17-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3106 // CHECK17-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
3107 // CHECK17-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
3108 // CHECK17-NEXT:    store i32 [[ADD]], ptr [[I]], align 4
3109 // CHECK17-NEXT:    store i32 1, ptr [[G]], align 4
3110 // CHECK17-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[_TMP3]], align 8
3111 // CHECK17-NEXT:    store volatile i32 1, ptr [[TMP10]], align 4
3112 // CHECK17-NEXT:    store i32 2, ptr [[SIVAR]], align 4
3113 // CHECK17-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 0
3114 // CHECK17-NEXT:    store ptr [[G]], ptr [[TMP11]], align 8
3115 // CHECK17-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 1
3116 // CHECK17-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[_TMP3]], align 8
3117 // CHECK17-NEXT:    store ptr [[TMP13]], ptr [[TMP12]], align 8
3118 // CHECK17-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON]], ptr [[REF_TMP]], i32 0, i32 2
3119 // CHECK17-NEXT:    store ptr [[SIVAR]], ptr [[TMP14]], align 8
3120 // CHECK17-NEXT:    call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]) #[[ATTR3:[0-9]+]]
3121 // CHECK17-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
3122 // CHECK17:       omp.body.continue:
3123 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
3124 // CHECK17:       omp.inner.for.inc:
3125 // CHECK17-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
3126 // CHECK17-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP15]], 1
3127 // CHECK17-NEXT:    store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4
3128 // CHECK17-NEXT:    br label [[OMP_INNER_FOR_COND]]
3129 // CHECK17:       omp.inner.for.end:
3130 // CHECK17-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
3131 // CHECK17:       omp.loop.exit:
3132 // CHECK17-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB2]], i32 [[TMP3]])
3133 // CHECK17-NEXT:    ret void
3134 //