clang/test/OpenMP/teams_distribute_parallel_for_simd_firstprivate_codegen.cpp

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
   2 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK1
   3 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping
   4 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK1
   5 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK3
   6 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping
   7 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK3
   8
   9 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK5
  10 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping
  11 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK5
  12 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK7
  13 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping
  14 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK7
  15
  16 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK9
  17 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping
  18 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++  -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK9
  19
  20 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK11
  21 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s -Wno-openmp-mapping
  22 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++  -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK11
  23
  24 // expected-no-diagnostics
  25 #ifndef HEADER
  26 #define HEADER
  27
  28 struct St {
  29   int a, b;
  30   St() : a(0), b(0) {}
  31   St(const St &st) : a(st.a + st.b), b(0) {}
  32   ~St() {}
  33 };
  34
  35 volatile int g = 1212;
  36 volatile int &g1 = g;
  37
  38 template <class T>
  39 struct S {
  40   T f;
  41   S(T a) : f(a + g) {}
  42   S() : f(g) {}
  43   S(const S &s, St t = St()) : f(s.f + t.a) {}
  44   operator T() { return T(); }
  45   ~S() {}
  46 };
  47
  48
  49 template <typename T>
  50 T tmain() {
  51   S<T> test;
  52   T t_var = T();
  53   T vec[] = {1, 2};
  54   S<T> s_arr[] = {1, 2};
  55   S<T> &var = test;
  56 #pragma omp target
  57 #pragma omp teams distribute parallel for simd firstprivate(t_var, vec, s_arr, var)
  58   for (int i = 0; i < 2; ++i) {
  59     vec[i] = t_var;
  60     s_arr[i] = var;
  61   }
  62   return T();
  63 }
  64
  65 S<float> test;
  66 int t_var = 333;
  67 int vec[] = {1, 2};
  68 S<float> s_arr[] = {1, 2};
  69 S<float> var(3);
  70
  71 int main() {
  72   static int sivar;
  73 #ifdef LAMBDA
  74   [&]() {
  75 #pragma omp target
  76 #pragma omp teams distribute parallel for simd firstprivate(g, g1, sivar)
  77   for (int i = 0; i < 2; ++i) {
  78
  79     // Skip global and bound tid vars
  80     // skip loop vars
  81     g = 1;
  82     g1 = 1;
  83     sivar = 2;
  84
  85     // Skip global and bound tid vars, and prev lb and ub vars
  86     // skip loop vars
  87
  88     // use of private vars
  89     [&]() {
  90       g = 2;
  91       g1 = 2;
  92       sivar = 4;
  93
  94     }();
  95   }
  96   }();
  97   return 0;
  98
  99
 100 #else
 101 #pragma omp target
 102 #pragma omp teams distribute parallel for simd firstprivate(t_var, vec, s_arr, var, sivar)
 103   for (int i = 0; i < 2; ++i) {
 104     vec[i] = t_var;
 105     s_arr[i] = var;
 106     sivar += i;
 107   }
 108   return tmain<int>();
 109 #endif
 110 }
 111
 112
 113
 114
 115
 116 // Skip global and bound tid vars
 117 // Skip temp vars for loop
 118
 119 // param copy
 120
 121 // T_VAR and SIVAR
 122
 123 // preparation vars
 124
 125 // firstprivate vec(vec): copy from *_addr into priv1 and then from priv1 into priv2
 126
 127 // firstprivate(s_arr)
 128
 129 // firstprivate(var)
 130
 131
 132 // Skip global and bound tid vars, and prev lb ub vars
 133 // Skip temp vars for loop
 134
 135 // param copy
 136
 137 // T_VAR and SIVAR
 138
 139 // preparation vars
 140
 141 // firstprivate vec(vec): copy from *_addr into priv1 and then from priv1 into priv2
 142
 143 // firstprivate(s_arr)
 144
 145 // firstprivate(var)
 146
 147
 148
 149
 150
 151
 152 // Skip global and bound tid vars
 153 // Skip temp vars for loop
 154
 155 // param copy
 156
 157 // T_VAR and preparation variables
 158
 159 // firstprivate vec(vec): copy from *_addr into priv1 and then from priv1 into priv2
 160
 161 // firstprivate(s_arr)
 162
 163 // firstprivate(var)
 164
 165
 166 // Skip global and bound tid vars
 167 // Skip temp vars for loop
 168
 169 // param copy
 170
 171 // T_VAR and preparation variables
 172
 173 // firstprivate vec(vec): copy from *_addr into priv1 and then from priv1 into priv2
 174
 175 // firstprivate(s_arr)
 176
 177 // firstprivate(var)
 178
 179
 180
 181 #endif
 182 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init
 183 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
 184 // CHECK1-NEXT:  entry:
 185 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
 186 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
 187 // CHECK1-NEXT:    ret void
 188 //
 189 //
 190 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
 191 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
 192 // CHECK1-NEXT:  entry:
 193 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 194 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 195 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 196 // CHECK1-NEXT:    call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
 197 // CHECK1-NEXT:    ret void
 198 //
 199 //
 200 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
 201 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
 202 // CHECK1-NEXT:  entry:
 203 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 204 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 205 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 206 // CHECK1-NEXT:    call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
 207 // CHECK1-NEXT:    ret void
 208 //
 209 //
 210 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
 211 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
 212 // CHECK1-NEXT:  entry:
 213 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 214 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 215 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 216 // CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
 217 // CHECK1-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
 218 // CHECK1-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
 219 // CHECK1-NEXT:    store float [[CONV]], ptr [[F]], align 4
 220 // CHECK1-NEXT:    ret void
 221 //
 222 //
 223 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
 224 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
 225 // CHECK1-NEXT:  entry:
 226 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 227 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 228 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 229 // CHECK1-NEXT:    ret void
 230 //
 231 //
 232 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
 233 // CHECK1-SAME: () #[[ATTR0]] {
 234 // CHECK1-NEXT:  entry:
 235 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
 236 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)
 237 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
 238 // CHECK1-NEXT:    ret void
 239 //
 240 //
 241 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
 242 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
 243 // CHECK1-NEXT:  entry:
 244 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 245 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
 246 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 247 // CHECK1-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
 248 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 249 // CHECK1-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
 250 // CHECK1-NEXT:    call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
 251 // CHECK1-NEXT:    ret void
 252 //
 253 //
 254 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
 255 // CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {
 256 // CHECK1-NEXT:  entry:
 257 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
 258 // CHECK1-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
 259 // CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
 260 // CHECK1:       arraydestroy.body:
 261 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
 262 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
 263 // CHECK1-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
 264 // CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr
 265 // CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
 266 // CHECK1:       arraydestroy.done1:
 267 // CHECK1-NEXT:    ret void
 268 //
 269 //
 270 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
 271 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
 272 // CHECK1-NEXT:  entry:
 273 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 274 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
 275 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 276 // CHECK1-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
 277 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 278 // CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
 279 // CHECK1-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
 280 // CHECK1-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
 281 // CHECK1-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
 282 // CHECK1-NEXT:    [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
 283 // CHECK1-NEXT:    store float [[ADD]], ptr [[F]], align 4
 284 // CHECK1-NEXT:    ret void
 285 //
 286 //
 287 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
 288 // CHECK1-SAME: () #[[ATTR0]] {
 289 // CHECK1-NEXT:  entry:
 290 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)
 291 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]
 292 // CHECK1-NEXT:    ret void
 293 //
 294 //
 295 // CHECK1-LABEL: define {{[^@]+}}@main
 296 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] {
 297 // CHECK1-NEXT:  entry:
 298 // CHECK1-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
 299 // CHECK1-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i64, align 8
 300 // CHECK1-NEXT:    [[SIVAR_CASTED:%.*]] = alloca i64, align 8
 301 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 8
 302 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 8
 303 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 8
 304 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 305 // CHECK1-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
 306 // CHECK1-NEXT:    store i32 0, ptr [[RETVAL]], align 4
 307 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr @t_var, align 4
 308 // CHECK1-NEXT:    store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 4
 309 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8
 310 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4
 311 // CHECK1-NEXT:    store i32 [[TMP2]], ptr [[SIVAR_CASTED]], align 4
 312 // CHECK1-NEXT:    [[TMP3:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8
 313 // CHECK1-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
 314 // CHECK1-NEXT:    store i64 [[TMP1]], ptr [[TMP4]], align 8
 315 // CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
 316 // CHECK1-NEXT:    store i64 [[TMP1]], ptr [[TMP5]], align 8
 317 // CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
 318 // CHECK1-NEXT:    store ptr null, ptr [[TMP6]], align 8
 319 // CHECK1-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
 320 // CHECK1-NEXT:    store ptr @vec, ptr [[TMP7]], align 8
 321 // CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
 322 // CHECK1-NEXT:    store ptr @vec, ptr [[TMP8]], align 8
 323 // CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
 324 // CHECK1-NEXT:    store ptr null, ptr [[TMP9]], align 8
 325 // CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
 326 // CHECK1-NEXT:    store ptr @s_arr, ptr [[TMP10]], align 8
 327 // CHECK1-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
 328 // CHECK1-NEXT:    store ptr @s_arr, ptr [[TMP11]], align 8
 329 // CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
 330 // CHECK1-NEXT:    store ptr null, ptr [[TMP12]], align 8
 331 // CHECK1-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
 332 // CHECK1-NEXT:    store ptr @var, ptr [[TMP13]], align 8
 333 // CHECK1-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
 334 // CHECK1-NEXT:    store ptr @var, ptr [[TMP14]], align 8
 335 // CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
 336 // CHECK1-NEXT:    store ptr null, ptr [[TMP15]], align 8
 337 // CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
 338 // CHECK1-NEXT:    store i64 [[TMP3]], ptr [[TMP16]], align 8
 339 // CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4
 340 // CHECK1-NEXT:    store i64 [[TMP3]], ptr [[TMP17]], align 8
 341 // CHECK1-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
 342 // CHECK1-NEXT:    store ptr null, ptr [[TMP18]], align 8
 343 // CHECK1-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
 344 // CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
 345 // CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
 346 // CHECK1-NEXT:    store i32 2, ptr [[TMP21]], align 4
 347 // CHECK1-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
 348 // CHECK1-NEXT:    store i32 5, ptr [[TMP22]], align 4
 349 // CHECK1-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
 350 // CHECK1-NEXT:    store ptr [[TMP19]], ptr [[TMP23]], align 8
 351 // CHECK1-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
 352 // CHECK1-NEXT:    store ptr [[TMP20]], ptr [[TMP24]], align 8
 353 // CHECK1-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
 354 // CHECK1-NEXT:    store ptr @.offload_sizes, ptr [[TMP25]], align 8
 355 // CHECK1-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
 356 // CHECK1-NEXT:    store ptr @.offload_maptypes, ptr [[TMP26]], align 8
 357 // CHECK1-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
 358 // CHECK1-NEXT:    store ptr null, ptr [[TMP27]], align 8
 359 // CHECK1-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
 360 // CHECK1-NEXT:    store ptr null, ptr [[TMP28]], align 8
 361 // CHECK1-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
 362 // CHECK1-NEXT:    store i64 2, ptr [[TMP29]], align 8
 363 // CHECK1-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
 364 // CHECK1-NEXT:    store i64 0, ptr [[TMP30]], align 8
 365 // CHECK1-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
 366 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP31]], align 4
 367 // CHECK1-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
 368 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP32]], align 4
 369 // CHECK1-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
 370 // CHECK1-NEXT:    store i32 0, ptr [[TMP33]], align 4
 371 // CHECK1-NEXT:    [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l101.region_id, ptr [[KERNEL_ARGS]])
 372 // CHECK1-NEXT:    [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0
 373 // CHECK1-NEXT:    br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
 374 // CHECK1:       omp_offload.failed:
 375 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l101(i64 [[TMP1]], ptr @vec, ptr @s_arr, ptr @var, i64 [[TMP3]]) #[[ATTR2]]
 376 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
 377 // CHECK1:       omp_offload.cont:
 378 // CHECK1-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v()
 379 // CHECK1-NEXT:    ret i32 [[CALL]]
 380 //
 381 //
 382 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l101
 383 // CHECK1-SAME: (i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] {
 384 // CHECK1-NEXT:  entry:
 385 // CHECK1-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i64, align 8
 386 // CHECK1-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 8
 387 // CHECK1-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 8
 388 // CHECK1-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 8
 389 // CHECK1-NEXT:    [[SIVAR_ADDR:%.*]] = alloca i64, align 8
 390 // CHECK1-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i64, align 8
 391 // CHECK1-NEXT:    [[SIVAR_CASTED:%.*]] = alloca i64, align 8
 392 // CHECK1-NEXT:    store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
 393 // CHECK1-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 8
 394 // CHECK1-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8
 395 // CHECK1-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 8
 396 // CHECK1-NEXT:    store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8
 397 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8
 398 // CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8
 399 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8
 400 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4
 401 // CHECK1-NEXT:    store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4
 402 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8
 403 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4
 404 // CHECK1-NEXT:    store i32 [[TMP5]], ptr [[SIVAR_CASTED]], align 4
 405 // CHECK1-NEXT:    [[TMP6:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8
 406 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l101.omp_outlined, ptr [[TMP0]], i64 [[TMP4]], ptr [[TMP1]], ptr [[TMP2]], i64 [[TMP6]])
 407 // CHECK1-NEXT:    ret void
 408 //
 409 //
 410 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l101.omp_outlined
 411 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR5:[0-9]+]] {
 412 // CHECK1-NEXT:  entry:
 413 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 414 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 415 // CHECK1-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 8
 416 // CHECK1-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i64, align 8
 417 // CHECK1-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 8
 418 // CHECK1-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 8
 419 // CHECK1-NEXT:    [[SIVAR_ADDR:%.*]] = alloca i64, align 8
 420 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 421 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 422 // CHECK1-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
 423 // CHECK1-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
 424 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 425 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 426 // CHECK1-NEXT:    [[VEC1:%.*]] = alloca [2 x i32], align 4
 427 // CHECK1-NEXT:    [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4
 428 // CHECK1-NEXT:    [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
 429 // CHECK1-NEXT:    [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4
 430 // CHECK1-NEXT:    [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4
 431 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
 432 // CHECK1-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i64, align 8
 433 // CHECK1-NEXT:    [[SIVAR_CASTED:%.*]] = alloca i64, align 8
 434 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 435 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 436 // CHECK1-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 8
 437 // CHECK1-NEXT:    store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
 438 // CHECK1-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8
 439 // CHECK1-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 8
 440 // CHECK1-NEXT:    store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8
 441 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8
 442 // CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8
 443 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8
 444 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
 445 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_COMB_UB]], align 4
 446 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 447 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 448 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i64 8, i1 false)
 449 // CHECK1-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0
 450 // CHECK1-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2
 451 // CHECK1-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]]
 452 // CHECK1-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
 453 // CHECK1:       omp.arraycpy.body:
 454 // CHECK1-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
 455 // CHECK1-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
 456 // CHECK1-NEXT:    call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]])
 457 // CHECK1-NEXT:    call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]])
 458 // CHECK1-NEXT:    call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
 459 // CHECK1-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
 460 // CHECK1-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
 461 // CHECK1-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]]
 462 // CHECK1-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]]
 463 // CHECK1:       omp.arraycpy.done3:
 464 // CHECK1-NEXT:    call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]])
 465 // CHECK1-NEXT:    call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP5]])
 466 // CHECK1-NEXT:    call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]]
 467 // CHECK1-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 468 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
 469 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
 470 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 471 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1
 472 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 473 // CHECK1:       cond.true:
 474 // CHECK1-NEXT:    br label [[COND_END:%.*]]
 475 // CHECK1:       cond.false:
 476 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 477 // CHECK1-NEXT:    br label [[COND_END]]
 478 // CHECK1:       cond.end:
 479 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
 480 // CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
 481 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
 482 // CHECK1-NEXT:    store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4
 483 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 484 // CHECK1:       omp.inner.for.cond:
 485 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5:![0-9]+]]
 486 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP5]]
 487 // CHECK1-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
 488 // CHECK1-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
 489 // CHECK1:       omp.inner.for.cond.cleanup:
 490 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
 491 // CHECK1:       omp.inner.for.body:
 492 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP5]]
 493 // CHECK1-NEXT:    [[TMP12:%.*]] = zext i32 [[TMP11]] to i64
 494 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP5]]
 495 // CHECK1-NEXT:    [[TMP14:%.*]] = zext i32 [[TMP13]] to i64
 496 // CHECK1-NEXT:    [[TMP15:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP5]]
 497 // CHECK1-NEXT:    store i32 [[TMP15]], ptr [[T_VAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP5]]
 498 // CHECK1-NEXT:    [[TMP16:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8, !llvm.access.group [[ACC_GRP5]]
 499 // CHECK1-NEXT:    [[TMP17:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP5]]
 500 // CHECK1-NEXT:    store i32 [[TMP17]], ptr [[SIVAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP5]]
 501 // CHECK1-NEXT:    [[TMP18:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8, !llvm.access.group [[ACC_GRP5]]
 502 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 7, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l101.omp_outlined.omp_outlined, i64 [[TMP12]], i64 [[TMP14]], ptr [[VEC1]], i64 [[TMP16]], ptr [[S_ARR2]], ptr [[VAR4]], i64 [[TMP18]]), !llvm.access.group [[ACC_GRP5]]
 503 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 504 // CHECK1:       omp.inner.for.inc:
 505 // CHECK1-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]]
 506 // CHECK1-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP5]]
 507 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]]
 508 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]]
 509 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
 510 // CHECK1:       omp.inner.for.end:
 511 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
 512 // CHECK1:       omp.loop.exit:
 513 // CHECK1-NEXT:    [[TMP21:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 514 // CHECK1-NEXT:    [[TMP22:%.*]] = load i32, ptr [[TMP21]], align 4
 515 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP22]])
 516 // CHECK1-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
 517 // CHECK1-NEXT:    [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0
 518 // CHECK1-NEXT:    br i1 [[TMP24]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
 519 // CHECK1:       .omp.final.then:
 520 // CHECK1-NEXT:    store i32 2, ptr [[I]], align 4
 521 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
 522 // CHECK1:       .omp.final.done:
 523 // CHECK1-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]]
 524 // CHECK1-NEXT:    [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0
 525 // CHECK1-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i64 2
 526 // CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
 527 // CHECK1:       arraydestroy.body:
 528 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP25]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
 529 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
 530 // CHECK1-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
 531 // CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]
 532 // CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]
 533 // CHECK1:       arraydestroy.done8:
 534 // CHECK1-NEXT:    ret void
 535 //
 536 //
 537 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC1Ev
 538 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
 539 // CHECK1-NEXT:  entry:
 540 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 541 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 542 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 543 // CHECK1-NEXT:    call void @_ZN2StC2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]])
 544 // CHECK1-NEXT:    ret void
 545 //
 546 //
 547 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St
 548 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat {
 549 // CHECK1-NEXT:  entry:
 550 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 551 // CHECK1-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8
 552 // CHECK1-NEXT:    [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8
 553 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 554 // CHECK1-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8
 555 // CHECK1-NEXT:    store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8
 556 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 557 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
 558 // CHECK1-NEXT:    call void @_ZN1SIfEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]])
 559 // CHECK1-NEXT:    ret void
 560 //
 561 //
 562 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD1Ev
 563 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
 564 // CHECK1-NEXT:  entry:
 565 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 566 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 567 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 568 // CHECK1-NEXT:    call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]]
 569 // CHECK1-NEXT:    ret void
 570 //
 571 //
 572 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l101.omp_outlined.omp_outlined
 573 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR5]] {
 574 // CHECK1-NEXT:  entry:
 575 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 576 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 577 // CHECK1-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
 578 // CHECK1-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
 579 // CHECK1-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 8
 580 // CHECK1-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i64, align 8
 581 // CHECK1-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 8
 582 // CHECK1-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 8
 583 // CHECK1-NEXT:    [[SIVAR_ADDR:%.*]] = alloca i64, align 8
 584 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 585 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 586 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
 587 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
 588 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 589 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 590 // CHECK1-NEXT:    [[VEC2:%.*]] = alloca [2 x i32], align 4
 591 // CHECK1-NEXT:    [[S_ARR3:%.*]] = alloca [2 x %struct.S], align 4
 592 // CHECK1-NEXT:    [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
 593 // CHECK1-NEXT:    [[VAR5:%.*]] = alloca [[STRUCT_S:%.*]], align 4
 594 // CHECK1-NEXT:    [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4
 595 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
 596 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 597 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 598 // CHECK1-NEXT:    store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
 599 // CHECK1-NEXT:    store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
 600 // CHECK1-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 8
 601 // CHECK1-NEXT:    store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
 602 // CHECK1-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8
 603 // CHECK1-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 8
 604 // CHECK1-NEXT:    store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8
 605 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8
 606 // CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8
 607 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8
 608 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
 609 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
 610 // CHECK1-NEXT:    [[TMP3:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
 611 // CHECK1-NEXT:    [[CONV:%.*]] = trunc i64 [[TMP3]] to i32
 612 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
 613 // CHECK1-NEXT:    [[CONV1:%.*]] = trunc i64 [[TMP4]] to i32
 614 // CHECK1-NEXT:    store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
 615 // CHECK1-NEXT:    store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4
 616 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 617 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 618 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i64 8, i1 false)
 619 // CHECK1-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i32 0, i32 0
 620 // CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2
 621 // CHECK1-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]]
 622 // CHECK1-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
 623 // CHECK1:       omp.arraycpy.body:
 624 // CHECK1-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
 625 // CHECK1-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
 626 // CHECK1-NEXT:    call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]])
 627 // CHECK1-NEXT:    call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]])
 628 // CHECK1-NEXT:    call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
 629 // CHECK1-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
 630 // CHECK1-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
 631 // CHECK1-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]]
 632 // CHECK1-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]
 633 // CHECK1:       omp.arraycpy.done4:
 634 // CHECK1-NEXT:    call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]])
 635 // CHECK1-NEXT:    call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP6]])
 636 // CHECK1-NEXT:    call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]]
 637 // CHECK1-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 638 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
 639 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP7]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
 640 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 641 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1
 642 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 643 // CHECK1:       cond.true:
 644 // CHECK1-NEXT:    br label [[COND_END:%.*]]
 645 // CHECK1:       cond.false:
 646 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 647 // CHECK1-NEXT:    br label [[COND_END]]
 648 // CHECK1:       cond.end:
 649 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]
 650 // CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
 651 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
 652 // CHECK1-NEXT:    store i32 [[TMP10]], ptr [[DOTOMP_IV]], align 4
 653 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 654 // CHECK1:       omp.inner.for.cond:
 655 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9:![0-9]+]]
 656 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP9]]
 657 // CHECK1-NEXT:    [[CMP7:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]
 658 // CHECK1-NEXT:    br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
 659 // CHECK1:       omp.inner.for.cond.cleanup:
 660 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
 661 // CHECK1:       omp.inner.for.body:
 662 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]]
 663 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1
 664 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
 665 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]]
 666 // CHECK1-NEXT:    [[TMP14:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP9]]
 667 // CHECK1-NEXT:    [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]]
 668 // CHECK1-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64
 669 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i64 0, i64 [[IDXPROM]]
 670 // CHECK1-NEXT:    store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP9]]
 671 // CHECK1-NEXT:    [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]]
 672 // CHECK1-NEXT:    [[IDXPROM8:%.*]] = sext i32 [[TMP16]] to i64
 673 // CHECK1-NEXT:    [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i64 0, i64 [[IDXPROM8]]
 674 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[VAR5]], i64 4, i1 false), !llvm.access.group [[ACC_GRP9]]
 675 // CHECK1-NEXT:    [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]]
 676 // CHECK1-NEXT:    [[TMP18:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP9]]
 677 // CHECK1-NEXT:    [[ADD10:%.*]] = add nsw i32 [[TMP18]], [[TMP17]]
 678 // CHECK1-NEXT:    store i32 [[ADD10]], ptr [[SIVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP9]]
 679 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 680 // CHECK1:       omp.body.continue:
 681 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 682 // CHECK1:       omp.inner.for.inc:
 683 // CHECK1-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]]
 684 // CHECK1-NEXT:    [[ADD11:%.*]] = add nsw i32 [[TMP19]], 1
 685 // CHECK1-NEXT:    store i32 [[ADD11]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]]
 686 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
 687 // CHECK1:       omp.inner.for.end:
 688 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
 689 // CHECK1:       omp.loop.exit:
 690 // CHECK1-NEXT:    [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 691 // CHECK1-NEXT:    [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4
 692 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP21]])
 693 // CHECK1-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
 694 // CHECK1-NEXT:    [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
 695 // CHECK1-NEXT:    br i1 [[TMP23]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
 696 // CHECK1:       .omp.final.then:
 697 // CHECK1-NEXT:    store i32 2, ptr [[I]], align 4
 698 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
 699 // CHECK1:       .omp.final.done:
 700 // CHECK1-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]
 701 // CHECK1-NEXT:    [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i32 0, i32 0
 702 // CHECK1-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN12]], i64 2
 703 // CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
 704 // CHECK1:       arraydestroy.body:
 705 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP24]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
 706 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
 707 // CHECK1-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
 708 // CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]]
 709 // CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]]
 710 // CHECK1:       arraydestroy.done13:
 711 // CHECK1-NEXT:    ret void
 712 //
 713 //
 714 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
 715 // CHECK1-SAME: () #[[ATTR7:[0-9]+]] comdat {
 716 // CHECK1-NEXT:  entry:
 717 // CHECK1-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
 718 // CHECK1-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
 719 // CHECK1-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
 720 // CHECK1-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
 721 // CHECK1-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
 722 // CHECK1-NEXT:    [[VAR:%.*]] = alloca ptr, align 8
 723 // CHECK1-NEXT:    [[TMP:%.*]] = alloca ptr, align 8
 724 // CHECK1-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i64, align 8
 725 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 8
 726 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 8
 727 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 8
 728 // CHECK1-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
 729 // CHECK1-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
 730 // CHECK1-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])
 731 // CHECK1-NEXT:    store i32 0, ptr [[T_VAR]], align 4
 732 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false)
 733 // CHECK1-NEXT:    [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 0
 734 // CHECK1-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef signext 1)
 735 // CHECK1-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYINIT_BEGIN]], i64 1
 736 // CHECK1-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2)
 737 // CHECK1-NEXT:    store ptr [[TEST]], ptr [[VAR]], align 8
 738 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8
 739 // CHECK1-NEXT:    store ptr [[TMP0]], ptr [[TMP]], align 8
 740 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4
 741 // CHECK1-NEXT:    store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4
 742 // CHECK1-NEXT:    [[TMP2:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8
 743 // CHECK1-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8
 744 // CHECK1-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8
 745 // CHECK1-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8
 746 // CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
 747 // CHECK1-NEXT:    store i64 [[TMP2]], ptr [[TMP6]], align 8
 748 // CHECK1-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
 749 // CHECK1-NEXT:    store i64 [[TMP2]], ptr [[TMP7]], align 8
 750 // CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
 751 // CHECK1-NEXT:    store ptr null, ptr [[TMP8]], align 8
 752 // CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
 753 // CHECK1-NEXT:    store ptr [[VEC]], ptr [[TMP9]], align 8
 754 // CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
 755 // CHECK1-NEXT:    store ptr [[VEC]], ptr [[TMP10]], align 8
 756 // CHECK1-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
 757 // CHECK1-NEXT:    store ptr null, ptr [[TMP11]], align 8
 758 // CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
 759 // CHECK1-NEXT:    store ptr [[S_ARR]], ptr [[TMP12]], align 8
 760 // CHECK1-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
 761 // CHECK1-NEXT:    store ptr [[S_ARR]], ptr [[TMP13]], align 8
 762 // CHECK1-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
 763 // CHECK1-NEXT:    store ptr null, ptr [[TMP14]], align 8
 764 // CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
 765 // CHECK1-NEXT:    store ptr [[TMP4]], ptr [[TMP15]], align 8
 766 // CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
 767 // CHECK1-NEXT:    store ptr [[TMP5]], ptr [[TMP16]], align 8
 768 // CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
 769 // CHECK1-NEXT:    store ptr null, ptr [[TMP17]], align 8
 770 // CHECK1-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
 771 // CHECK1-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
 772 // CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
 773 // CHECK1-NEXT:    store i32 2, ptr [[TMP20]], align 4
 774 // CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
 775 // CHECK1-NEXT:    store i32 4, ptr [[TMP21]], align 4
 776 // CHECK1-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
 777 // CHECK1-NEXT:    store ptr [[TMP18]], ptr [[TMP22]], align 8
 778 // CHECK1-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
 779 // CHECK1-NEXT:    store ptr [[TMP19]], ptr [[TMP23]], align 8
 780 // CHECK1-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
 781 // CHECK1-NEXT:    store ptr @.offload_sizes.3, ptr [[TMP24]], align 8
 782 // CHECK1-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
 783 // CHECK1-NEXT:    store ptr @.offload_maptypes.4, ptr [[TMP25]], align 8
 784 // CHECK1-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
 785 // CHECK1-NEXT:    store ptr null, ptr [[TMP26]], align 8
 786 // CHECK1-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
 787 // CHECK1-NEXT:    store ptr null, ptr [[TMP27]], align 8
 788 // CHECK1-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
 789 // CHECK1-NEXT:    store i64 2, ptr [[TMP28]], align 8
 790 // CHECK1-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
 791 // CHECK1-NEXT:    store i64 0, ptr [[TMP29]], align 8
 792 // CHECK1-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
 793 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP30]], align 4
 794 // CHECK1-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
 795 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP31]], align 4
 796 // CHECK1-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
 797 // CHECK1-NEXT:    store i32 0, ptr [[TMP32]], align 4
 798 // CHECK1-NEXT:    [[TMP33:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, ptr [[KERNEL_ARGS]])
 799 // CHECK1-NEXT:    [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0
 800 // CHECK1-NEXT:    br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
 801 // CHECK1:       omp_offload.failed:
 802 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56(i64 [[TMP2]], ptr [[VEC]], ptr [[S_ARR]], ptr [[TMP3]]) #[[ATTR2]]
 803 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
 804 // CHECK1:       omp_offload.cont:
 805 // CHECK1-NEXT:    store i32 0, ptr [[RETVAL]], align 4
 806 // CHECK1-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
 807 // CHECK1-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2
 808 // CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
 809 // CHECK1:       arraydestroy.body:
 810 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP35]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
 811 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
 812 // CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
 813 // CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
 814 // CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
 815 // CHECK1:       arraydestroy.done2:
 816 // CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
 817 // CHECK1-NEXT:    [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4
 818 // CHECK1-NEXT:    ret i32 [[TMP36]]
 819 //
 820 //
 821 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StC2Ev
 822 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
 823 // CHECK1-NEXT:  entry:
 824 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 825 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 826 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 827 // CHECK1-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0
 828 // CHECK1-NEXT:    store i32 0, ptr [[A]], align 4
 829 // CHECK1-NEXT:    [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1
 830 // CHECK1-NEXT:    store i32 0, ptr [[B]], align 4
 831 // CHECK1-NEXT:    ret void
 832 //
 833 //
 834 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St
 835 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat {
 836 // CHECK1-NEXT:  entry:
 837 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 838 // CHECK1-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8
 839 // CHECK1-NEXT:    [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8
 840 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 841 // CHECK1-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8
 842 // CHECK1-NEXT:    store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8
 843 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 844 // CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
 845 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
 846 // CHECK1-NEXT:    [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0
 847 // CHECK1-NEXT:    [[TMP1:%.*]] = load float, ptr [[F2]], align 4
 848 // CHECK1-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0
 849 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 4
 850 // CHECK1-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP2]] to float
 851 // CHECK1-NEXT:    [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]]
 852 // CHECK1-NEXT:    store float [[ADD]], ptr [[F]], align 4
 853 // CHECK1-NEXT:    ret void
 854 //
 855 //
 856 // CHECK1-LABEL: define {{[^@]+}}@_ZN2StD2Ev
 857 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
 858 // CHECK1-NEXT:  entry:
 859 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 860 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 861 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 862 // CHECK1-NEXT:    ret void
 863 //
 864 //
 865 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
 866 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
 867 // CHECK1-NEXT:  entry:
 868 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 869 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 870 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 871 // CHECK1-NEXT:    call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
 872 // CHECK1-NEXT:    ret void
 873 //
 874 //
 875 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
 876 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
 877 // CHECK1-NEXT:  entry:
 878 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 879 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
 880 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 881 // CHECK1-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
 882 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 883 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
 884 // CHECK1-NEXT:    call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
 885 // CHECK1-NEXT:    ret void
 886 //
 887 //
 888 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56
 889 // CHECK1-SAME: (i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {
 890 // CHECK1-NEXT:  entry:
 891 // CHECK1-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i64, align 8
 892 // CHECK1-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 8
 893 // CHECK1-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 8
 894 // CHECK1-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 8
 895 // CHECK1-NEXT:    [[TMP:%.*]] = alloca ptr, align 8
 896 // CHECK1-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i64, align 8
 897 // CHECK1-NEXT:    store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
 898 // CHECK1-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 8
 899 // CHECK1-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8
 900 // CHECK1-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 8
 901 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8
 902 // CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8
 903 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8
 904 // CHECK1-NEXT:    store ptr [[TMP2]], ptr [[TMP]], align 8
 905 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4
 906 // CHECK1-NEXT:    store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4
 907 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8
 908 // CHECK1-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 8
 909 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined, ptr [[TMP0]], i64 [[TMP4]], ptr [[TMP1]], ptr [[TMP5]])
 910 // CHECK1-NEXT:    ret void
 911 //
 912 //
 913 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined
 914 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR5]] {
 915 // CHECK1-NEXT:  entry:
 916 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 917 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 918 // CHECK1-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 8
 919 // CHECK1-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i64, align 8
 920 // CHECK1-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 8
 921 // CHECK1-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 8
 922 // CHECK1-NEXT:    [[TMP:%.*]] = alloca ptr, align 8
 923 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 924 // CHECK1-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
 925 // CHECK1-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
 926 // CHECK1-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
 927 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 928 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 929 // CHECK1-NEXT:    [[VEC2:%.*]] = alloca [2 x i32], align 4
 930 // CHECK1-NEXT:    [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4
 931 // CHECK1-NEXT:    [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
 932 // CHECK1-NEXT:    [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
 933 // CHECK1-NEXT:    [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4
 934 // CHECK1-NEXT:    [[_TMP7:%.*]] = alloca ptr, align 8
 935 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
 936 // CHECK1-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i64, align 8
 937 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 938 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 939 // CHECK1-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 8
 940 // CHECK1-NEXT:    store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
 941 // CHECK1-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8
 942 // CHECK1-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 8
 943 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8
 944 // CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8
 945 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8
 946 // CHECK1-NEXT:    store ptr [[TMP2]], ptr [[TMP]], align 8
 947 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
 948 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_COMB_UB]], align 4
 949 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 950 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 951 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i64 8, i1 false)
 952 // CHECK1-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0
 953 // CHECK1-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2
 954 // CHECK1-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]]
 955 // CHECK1-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
 956 // CHECK1:       omp.arraycpy.body:
 957 // CHECK1-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
 958 // CHECK1-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
 959 // CHECK1-NEXT:    call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]])
 960 // CHECK1-NEXT:    call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]])
 961 // CHECK1-NEXT:    call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
 962 // CHECK1-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
 963 // CHECK1-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
 964 // CHECK1-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]]
 965 // CHECK1-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]
 966 // CHECK1:       omp.arraycpy.done4:
 967 // CHECK1-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 8
 968 // CHECK1-NEXT:    call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]])
 969 // CHECK1-NEXT:    call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP4]], ptr noundef [[AGG_TMP6]])
 970 // CHECK1-NEXT:    call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]]
 971 // CHECK1-NEXT:    store ptr [[VAR5]], ptr [[_TMP7]], align 8
 972 // CHECK1-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 973 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
 974 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP6]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
 975 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 976 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 1
 977 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 978 // CHECK1:       cond.true:
 979 // CHECK1-NEXT:    br label [[COND_END:%.*]]
 980 // CHECK1:       cond.false:
 981 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 982 // CHECK1-NEXT:    br label [[COND_END]]
 983 // CHECK1:       cond.end:
 984 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
 985 // CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
 986 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
 987 // CHECK1-NEXT:    store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4
 988 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 989 // CHECK1:       omp.inner.for.cond:
 990 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14:![0-9]+]]
 991 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP14]]
 992 // CHECK1-NEXT:    [[CMP8:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
 993 // CHECK1-NEXT:    br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
 994 // CHECK1:       omp.inner.for.cond.cleanup:
 995 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
 996 // CHECK1:       omp.inner.for.body:
 997 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP14]]
 998 // CHECK1-NEXT:    [[TMP13:%.*]] = zext i32 [[TMP12]] to i64
 999 // CHECK1-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP14]]
1000 // CHECK1-NEXT:    [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
1001 // CHECK1-NEXT:    [[TMP16:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP14]]
1002 // CHECK1-NEXT:    store i32 [[TMP16]], ptr [[T_VAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP14]]
1003 // CHECK1-NEXT:    [[TMP17:%.*]] = load i64, ptr [[T_VAR_CASTED]], align 8, !llvm.access.group [[ACC_GRP14]]
1004 // CHECK1-NEXT:    [[TMP18:%.*]] = load ptr, ptr [[_TMP7]], align 8, !llvm.access.group [[ACC_GRP14]]
1005 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined.omp_outlined, i64 [[TMP13]], i64 [[TMP15]], ptr [[VEC2]], i64 [[TMP17]], ptr [[S_ARR3]], ptr [[TMP18]]), !llvm.access.group [[ACC_GRP14]]
1006 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1007 // CHECK1:       omp.inner.for.inc:
1008 // CHECK1-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]
1009 // CHECK1-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP14]]
1010 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]]
1011 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]
1012 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
1013 // CHECK1:       omp.inner.for.end:
1014 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1015 // CHECK1:       omp.loop.exit:
1016 // CHECK1-NEXT:    [[TMP21:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1017 // CHECK1-NEXT:    [[TMP22:%.*]] = load i32, ptr [[TMP21]], align 4
1018 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP22]])
1019 // CHECK1-NEXT:    [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
1020 // CHECK1-NEXT:    [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0
1021 // CHECK1-NEXT:    br i1 [[TMP24]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1022 // CHECK1:       .omp.final.then:
1023 // CHECK1-NEXT:    store i32 2, ptr [[I]], align 4
1024 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
1025 // CHECK1:       .omp.final.done:
1026 // CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]
1027 // CHECK1-NEXT:    [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0
1028 // CHECK1-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN9]], i64 2
1029 // CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1030 // CHECK1:       arraydestroy.body:
1031 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP25]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1032 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1033 // CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1034 // CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]]
1035 // CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]]
1036 // CHECK1:       arraydestroy.done10:
1037 // CHECK1-NEXT:    ret void
1038 //
1039 //
1040 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St
1041 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1042 // CHECK1-NEXT:  entry:
1043 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1044 // CHECK1-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8
1045 // CHECK1-NEXT:    [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8
1046 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1047 // CHECK1-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8
1048 // CHECK1-NEXT:    store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8
1049 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1050 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
1051 // CHECK1-NEXT:    call void @_ZN1SIiEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]])
1052 // CHECK1-NEXT:    ret void
1053 //
1054 //
1055 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined.omp_outlined
1056 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i64 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR5]] {
1057 // CHECK1-NEXT:  entry:
1058 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
1059 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
1060 // CHECK1-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
1061 // CHECK1-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
1062 // CHECK1-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 8
1063 // CHECK1-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i64, align 8
1064 // CHECK1-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 8
1065 // CHECK1-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 8
1066 // CHECK1-NEXT:    [[TMP:%.*]] = alloca ptr, align 8
1067 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1068 // CHECK1-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
1069 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1070 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1071 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1072 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1073 // CHECK1-NEXT:    [[VEC3:%.*]] = alloca [2 x i32], align 4
1074 // CHECK1-NEXT:    [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4
1075 // CHECK1-NEXT:    [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
1076 // CHECK1-NEXT:    [[VAR6:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1077 // CHECK1-NEXT:    [[AGG_TMP7:%.*]] = alloca [[STRUCT_ST]], align 4
1078 // CHECK1-NEXT:    [[_TMP8:%.*]] = alloca ptr, align 8
1079 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
1080 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
1081 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
1082 // CHECK1-NEXT:    store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
1083 // CHECK1-NEXT:    store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
1084 // CHECK1-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 8
1085 // CHECK1-NEXT:    store i64 [[T_VAR]], ptr [[T_VAR_ADDR]], align 8
1086 // CHECK1-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 8
1087 // CHECK1-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 8
1088 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 8
1089 // CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 8
1090 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 8
1091 // CHECK1-NEXT:    store ptr [[TMP2]], ptr [[TMP]], align 8
1092 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
1093 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
1094 // CHECK1-NEXT:    [[TMP3:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
1095 // CHECK1-NEXT:    [[CONV:%.*]] = trunc i64 [[TMP3]] to i32
1096 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
1097 // CHECK1-NEXT:    [[CONV2:%.*]] = trunc i64 [[TMP4]] to i32
1098 // CHECK1-NEXT:    store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
1099 // CHECK1-NEXT:    store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4
1100 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1101 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1102 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC3]], ptr align 4 [[TMP0]], i64 8, i1 false)
1103 // CHECK1-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0
1104 // CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2
1105 // CHECK1-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]]
1106 // CHECK1-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE5:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
1107 // CHECK1:       omp.arraycpy.body:
1108 // CHECK1-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1109 // CHECK1-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1110 // CHECK1-NEXT:    call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]])
1111 // CHECK1-NEXT:    call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]])
1112 // CHECK1-NEXT:    call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
1113 // CHECK1-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
1114 // CHECK1-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
1115 // CHECK1-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]]
1116 // CHECK1-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE5]], label [[OMP_ARRAYCPY_BODY]]
1117 // CHECK1:       omp.arraycpy.done5:
1118 // CHECK1-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 8
1119 // CHECK1-NEXT:    call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP7]])
1120 // CHECK1-NEXT:    call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP6]], ptr noundef [[AGG_TMP7]])
1121 // CHECK1-NEXT:    call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP7]]) #[[ATTR2]]
1122 // CHECK1-NEXT:    store ptr [[VAR6]], ptr [[_TMP8]], align 8
1123 // CHECK1-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1124 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
1125 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP8]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
1126 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1127 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1
1128 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1129 // CHECK1:       cond.true:
1130 // CHECK1-NEXT:    br label [[COND_END:%.*]]
1131 // CHECK1:       cond.false:
1132 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1133 // CHECK1-NEXT:    br label [[COND_END]]
1134 // CHECK1:       cond.end:
1135 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
1136 // CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
1137 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1138 // CHECK1-NEXT:    store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 4
1139 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1140 // CHECK1:       omp.inner.for.cond:
1141 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17:![0-9]+]]
1142 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP17]]
1143 // CHECK1-NEXT:    [[CMP9:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
1144 // CHECK1-NEXT:    br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1145 // CHECK1:       omp.inner.for.cond.cleanup:
1146 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
1147 // CHECK1:       omp.inner.for.body:
1148 // CHECK1-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]]
1149 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1
1150 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1151 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP17]]
1152 // CHECK1-NEXT:    [[TMP15:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP17]]
1153 // CHECK1-NEXT:    [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP17]]
1154 // CHECK1-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64
1155 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i64 0, i64 [[IDXPROM]]
1156 // CHECK1-NEXT:    store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP17]]
1157 // CHECK1-NEXT:    [[TMP17:%.*]] = load ptr, ptr [[_TMP8]], align 8, !llvm.access.group [[ACC_GRP17]]
1158 // CHECK1-NEXT:    [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP17]]
1159 // CHECK1-NEXT:    [[IDXPROM10:%.*]] = sext i32 [[TMP18]] to i64
1160 // CHECK1-NEXT:    [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM10]]
1161 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX11]], ptr align 4 [[TMP17]], i64 4, i1 false), !llvm.access.group [[ACC_GRP17]]
1162 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1163 // CHECK1:       omp.body.continue:
1164 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1165 // CHECK1:       omp.inner.for.inc:
1166 // CHECK1-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]]
1167 // CHECK1-NEXT:    [[ADD12:%.*]] = add nsw i32 [[TMP19]], 1
1168 // CHECK1-NEXT:    store i32 [[ADD12]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]]
1169 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]
1170 // CHECK1:       omp.inner.for.end:
1171 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1172 // CHECK1:       omp.loop.exit:
1173 // CHECK1-NEXT:    [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
1174 // CHECK1-NEXT:    [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4
1175 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP21]])
1176 // CHECK1-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
1177 // CHECK1-NEXT:    [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
1178 // CHECK1-NEXT:    br i1 [[TMP23]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1179 // CHECK1:       .omp.final.then:
1180 // CHECK1-NEXT:    store i32 2, ptr [[I]], align 4
1181 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
1182 // CHECK1:       .omp.final.done:
1183 // CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR6]]) #[[ATTR2]]
1184 // CHECK1-NEXT:    [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0
1185 // CHECK1-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN13]], i64 2
1186 // CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1187 // CHECK1:       arraydestroy.body:
1188 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP24]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1189 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1190 // CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1191 // CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]]
1192 // CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]]
1193 // CHECK1:       arraydestroy.done14:
1194 // CHECK1-NEXT:    ret void
1195 //
1196 //
1197 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
1198 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1199 // CHECK1-NEXT:  entry:
1200 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1201 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1202 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1203 // CHECK1-NEXT:    call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
1204 // CHECK1-NEXT:    ret void
1205 //
1206 //
1207 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
1208 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1209 // CHECK1-NEXT:  entry:
1210 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1211 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1212 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1213 // CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
1214 // CHECK1-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
1215 // CHECK1-NEXT:    store i32 [[TMP0]], ptr [[F]], align 4
1216 // CHECK1-NEXT:    ret void
1217 //
1218 //
1219 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
1220 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1221 // CHECK1-NEXT:  entry:
1222 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1223 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
1224 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1225 // CHECK1-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
1226 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1227 // CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
1228 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
1229 // CHECK1-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
1230 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
1231 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[F]], align 4
1232 // CHECK1-NEXT:    ret void
1233 //
1234 //
1235 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St
1236 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1237 // CHECK1-NEXT:  entry:
1238 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1239 // CHECK1-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 8
1240 // CHECK1-NEXT:    [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 8
1241 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1242 // CHECK1-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 8
1243 // CHECK1-NEXT:    store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 8
1244 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1245 // CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
1246 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 8
1247 // CHECK1-NEXT:    [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0
1248 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[F2]], align 4
1249 // CHECK1-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0
1250 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 4
1251 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]
1252 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[F]], align 4
1253 // CHECK1-NEXT:    ret void
1254 //
1255 //
1256 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
1257 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1258 // CHECK1-NEXT:  entry:
1259 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1260 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1261 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1262 // CHECK1-NEXT:    ret void
1263 //
1264 //
1265 // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp
1266 // CHECK1-SAME: () #[[ATTR0]] {
1267 // CHECK1-NEXT:  entry:
1268 // CHECK1-NEXT:    call void @__cxx_global_var_init()
1269 // CHECK1-NEXT:    call void @__cxx_global_var_init.1()
1270 // CHECK1-NEXT:    call void @__cxx_global_var_init.2()
1271 // CHECK1-NEXT:    ret void
1272 //
1273 //
1274 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
1275 // CHECK1-SAME: () #[[ATTR0]] {
1276 // CHECK1-NEXT:  entry:
1277 // CHECK1-NEXT:    call void @__tgt_register_requires(i64 1)
1278 // CHECK1-NEXT:    ret void
1279 //
1280 //
1281 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init
1282 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] {
1283 // CHECK3-NEXT:  entry:
1284 // CHECK3-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
1285 // CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
1286 // CHECK3-NEXT:    ret void
1287 //
1288 //
1289 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
1290 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
1291 // CHECK3-NEXT:  entry:
1292 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1293 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1294 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1295 // CHECK3-NEXT:    call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
1296 // CHECK3-NEXT:    ret void
1297 //
1298 //
1299 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
1300 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1301 // CHECK3-NEXT:  entry:
1302 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1303 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1304 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1305 // CHECK3-NEXT:    call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
1306 // CHECK3-NEXT:    ret void
1307 //
1308 //
1309 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
1310 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1311 // CHECK3-NEXT:  entry:
1312 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1313 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1314 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1315 // CHECK3-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
1316 // CHECK3-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
1317 // CHECK3-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
1318 // CHECK3-NEXT:    store float [[CONV]], ptr [[F]], align 4
1319 // CHECK3-NEXT:    ret void
1320 //
1321 //
1322 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
1323 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1324 // CHECK3-NEXT:  entry:
1325 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1326 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1327 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1328 // CHECK3-NEXT:    ret void
1329 //
1330 //
1331 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
1332 // CHECK3-SAME: () #[[ATTR0]] {
1333 // CHECK3-NEXT:  entry:
1334 // CHECK3-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
1335 // CHECK3-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 1), float noundef 2.000000e+00)
1336 // CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
1337 // CHECK3-NEXT:    ret void
1338 //
1339 //
1340 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
1341 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1342 // CHECK3-NEXT:  entry:
1343 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1344 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
1345 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1346 // CHECK3-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
1347 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1348 // CHECK3-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
1349 // CHECK3-NEXT:    call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
1350 // CHECK3-NEXT:    ret void
1351 //
1352 //
1353 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
1354 // CHECK3-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {
1355 // CHECK3-NEXT:  entry:
1356 // CHECK3-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 4
1357 // CHECK3-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 4
1358 // CHECK3-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1359 // CHECK3:       arraydestroy.body:
1360 // CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1361 // CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1362 // CHECK3-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1363 // CHECK3-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr
1364 // CHECK3-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
1365 // CHECK3:       arraydestroy.done1:
1366 // CHECK3-NEXT:    ret void
1367 //
1368 //
1369 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
1370 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1371 // CHECK3-NEXT:  entry:
1372 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1373 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
1374 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1375 // CHECK3-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
1376 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1377 // CHECK3-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
1378 // CHECK3-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
1379 // CHECK3-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
1380 // CHECK3-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
1381 // CHECK3-NEXT:    [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
1382 // CHECK3-NEXT:    store float [[ADD]], ptr [[F]], align 4
1383 // CHECK3-NEXT:    ret void
1384 //
1385 //
1386 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
1387 // CHECK3-SAME: () #[[ATTR0]] {
1388 // CHECK3-NEXT:  entry:
1389 // CHECK3-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)
1390 // CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]
1391 // CHECK3-NEXT:    ret void
1392 //
1393 //
1394 // CHECK3-LABEL: define {{[^@]+}}@main
1395 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] {
1396 // CHECK3-NEXT:  entry:
1397 // CHECK3-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
1398 // CHECK3-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i32, align 4
1399 // CHECK3-NEXT:    [[SIVAR_CASTED:%.*]] = alloca i32, align 4
1400 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 4
1401 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 4
1402 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 4
1403 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1404 // CHECK3-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1405 // CHECK3-NEXT:    store i32 0, ptr [[RETVAL]], align 4
1406 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr @t_var, align 4
1407 // CHECK3-NEXT:    store i32 [[TMP0]], ptr [[T_VAR_CASTED]], align 4
1408 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4
1409 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4
1410 // CHECK3-NEXT:    store i32 [[TMP2]], ptr [[SIVAR_CASTED]], align 4
1411 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[SIVAR_CASTED]], align 4
1412 // CHECK3-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1413 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[TMP4]], align 4
1414 // CHECK3-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1415 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[TMP5]], align 4
1416 // CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
1417 // CHECK3-NEXT:    store ptr null, ptr [[TMP6]], align 4
1418 // CHECK3-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1419 // CHECK3-NEXT:    store ptr @vec, ptr [[TMP7]], align 4
1420 // CHECK3-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1421 // CHECK3-NEXT:    store ptr @vec, ptr [[TMP8]], align 4
1422 // CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
1423 // CHECK3-NEXT:    store ptr null, ptr [[TMP9]], align 4
1424 // CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1425 // CHECK3-NEXT:    store ptr @s_arr, ptr [[TMP10]], align 4
1426 // CHECK3-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1427 // CHECK3-NEXT:    store ptr @s_arr, ptr [[TMP11]], align 4
1428 // CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
1429 // CHECK3-NEXT:    store ptr null, ptr [[TMP12]], align 4
1430 // CHECK3-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1431 // CHECK3-NEXT:    store ptr @var, ptr [[TMP13]], align 4
1432 // CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1433 // CHECK3-NEXT:    store ptr @var, ptr [[TMP14]], align 4
1434 // CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
1435 // CHECK3-NEXT:    store ptr null, ptr [[TMP15]], align 4
1436 // CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
1437 // CHECK3-NEXT:    store i32 [[TMP3]], ptr [[TMP16]], align 4
1438 // CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4
1439 // CHECK3-NEXT:    store i32 [[TMP3]], ptr [[TMP17]], align 4
1440 // CHECK3-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
1441 // CHECK3-NEXT:    store ptr null, ptr [[TMP18]], align 4
1442 // CHECK3-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1443 // CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1444 // CHECK3-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
1445 // CHECK3-NEXT:    store i32 2, ptr [[TMP21]], align 4
1446 // CHECK3-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
1447 // CHECK3-NEXT:    store i32 5, ptr [[TMP22]], align 4
1448 // CHECK3-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
1449 // CHECK3-NEXT:    store ptr [[TMP19]], ptr [[TMP23]], align 4
1450 // CHECK3-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
1451 // CHECK3-NEXT:    store ptr [[TMP20]], ptr [[TMP24]], align 4
1452 // CHECK3-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
1453 // CHECK3-NEXT:    store ptr @.offload_sizes, ptr [[TMP25]], align 4
1454 // CHECK3-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
1455 // CHECK3-NEXT:    store ptr @.offload_maptypes, ptr [[TMP26]], align 4
1456 // CHECK3-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
1457 // CHECK3-NEXT:    store ptr null, ptr [[TMP27]], align 4
1458 // CHECK3-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
1459 // CHECK3-NEXT:    store ptr null, ptr [[TMP28]], align 4
1460 // CHECK3-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
1461 // CHECK3-NEXT:    store i64 2, ptr [[TMP29]], align 8
1462 // CHECK3-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
1463 // CHECK3-NEXT:    store i64 0, ptr [[TMP30]], align 8
1464 // CHECK3-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
1465 // CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP31]], align 4
1466 // CHECK3-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
1467 // CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP32]], align 4
1468 // CHECK3-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
1469 // CHECK3-NEXT:    store i32 0, ptr [[TMP33]], align 4
1470 // CHECK3-NEXT:    [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l101.region_id, ptr [[KERNEL_ARGS]])
1471 // CHECK3-NEXT:    [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0
1472 // CHECK3-NEXT:    br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1473 // CHECK3:       omp_offload.failed:
1474 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l101(i32 [[TMP1]], ptr @vec, ptr @s_arr, ptr @var, i32 [[TMP3]]) #[[ATTR2]]
1475 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]
1476 // CHECK3:       omp_offload.cont:
1477 // CHECK3-NEXT:    [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()
1478 // CHECK3-NEXT:    ret i32 [[CALL]]
1479 //
1480 //
1481 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l101
1482 // CHECK3-SAME: (i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR4:[0-9]+]] {
1483 // CHECK3-NEXT:  entry:
1484 // CHECK3-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i32, align 4
1485 // CHECK3-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 4
1486 // CHECK3-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 4
1487 // CHECK3-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 4
1488 // CHECK3-NEXT:    [[SIVAR_ADDR:%.*]] = alloca i32, align 4
1489 // CHECK3-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i32, align 4
1490 // CHECK3-NEXT:    [[SIVAR_CASTED:%.*]] = alloca i32, align 4
1491 // CHECK3-NEXT:    store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4
1492 // CHECK3-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 4
1493 // CHECK3-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4
1494 // CHECK3-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 4
1495 // CHECK3-NEXT:    store i32 [[SIVAR]], ptr [[SIVAR_ADDR]], align 4
1496 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4
1497 // CHECK3-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4
1498 // CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4
1499 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4
1500 // CHECK3-NEXT:    store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4
1501 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4
1502 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4
1503 // CHECK3-NEXT:    store i32 [[TMP5]], ptr [[SIVAR_CASTED]], align 4
1504 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[SIVAR_CASTED]], align 4
1505 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l101.omp_outlined, ptr [[TMP0]], i32 [[TMP4]], ptr [[TMP1]], ptr [[TMP2]], i32 [[TMP6]])
1506 // CHECK3-NEXT:    ret void
1507 //
1508 //
1509 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l101.omp_outlined
1510 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR5:[0-9]+]] {
1511 // CHECK3-NEXT:  entry:
1512 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
1513 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
1514 // CHECK3-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 4
1515 // CHECK3-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i32, align 4
1516 // CHECK3-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 4
1517 // CHECK3-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 4
1518 // CHECK3-NEXT:    [[SIVAR_ADDR:%.*]] = alloca i32, align 4
1519 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1520 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1521 // CHECK3-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
1522 // CHECK3-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
1523 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1524 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1525 // CHECK3-NEXT:    [[VEC1:%.*]] = alloca [2 x i32], align 4
1526 // CHECK3-NEXT:    [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4
1527 // CHECK3-NEXT:    [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
1528 // CHECK3-NEXT:    [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4
1529 // CHECK3-NEXT:    [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4
1530 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
1531 // CHECK3-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i32, align 4
1532 // CHECK3-NEXT:    [[SIVAR_CASTED:%.*]] = alloca i32, align 4
1533 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
1534 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
1535 // CHECK3-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 4
1536 // CHECK3-NEXT:    store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4
1537 // CHECK3-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4
1538 // CHECK3-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 4
1539 // CHECK3-NEXT:    store i32 [[SIVAR]], ptr [[SIVAR_ADDR]], align 4
1540 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4
1541 // CHECK3-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4
1542 // CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4
1543 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
1544 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_COMB_UB]], align 4
1545 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1546 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1547 // CHECK3-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i32 8, i1 false)
1548 // CHECK3-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0
1549 // CHECK3-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2
1550 // CHECK3-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]]
1551 // CHECK3-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
1552 // CHECK3:       omp.arraycpy.body:
1553 // CHECK3-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1554 // CHECK3-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1555 // CHECK3-NEXT:    call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]])
1556 // CHECK3-NEXT:    call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]])
1557 // CHECK3-NEXT:    call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
1558 // CHECK3-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
1559 // CHECK3-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
1560 // CHECK3-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]]
1561 // CHECK3-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]]
1562 // CHECK3:       omp.arraycpy.done3:
1563 // CHECK3-NEXT:    call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]])
1564 // CHECK3-NEXT:    call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP5]])
1565 // CHECK3-NEXT:    call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]]
1566 // CHECK3-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
1567 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
1568 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP5]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
1569 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1570 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 1
1571 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1572 // CHECK3:       cond.true:
1573 // CHECK3-NEXT:    br label [[COND_END:%.*]]
1574 // CHECK3:       cond.false:
1575 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1576 // CHECK3-NEXT:    br label [[COND_END]]
1577 // CHECK3:       cond.end:
1578 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
1579 // CHECK3-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
1580 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
1581 // CHECK3-NEXT:    store i32 [[TMP8]], ptr [[DOTOMP_IV]], align 4
1582 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1583 // CHECK3:       omp.inner.for.cond:
1584 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]]
1585 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP6]]
1586 // CHECK3-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]]
1587 // CHECK3-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1588 // CHECK3:       omp.inner.for.cond.cleanup:
1589 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
1590 // CHECK3:       omp.inner.for.body:
1591 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP6]]
1592 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP6]]
1593 // CHECK3-NEXT:    [[TMP13:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP6]]
1594 // CHECK3-NEXT:    store i32 [[TMP13]], ptr [[T_VAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP6]]
1595 // CHECK3-NEXT:    [[TMP14:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP6]]
1596 // CHECK3-NEXT:    [[TMP15:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP6]]
1597 // CHECK3-NEXT:    store i32 [[TMP15]], ptr [[SIVAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP6]]
1598 // CHECK3-NEXT:    [[TMP16:%.*]] = load i32, ptr [[SIVAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP6]]
1599 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 7, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l101.omp_outlined.omp_outlined, i32 [[TMP11]], i32 [[TMP12]], ptr [[VEC1]], i32 [[TMP14]], ptr [[S_ARR2]], ptr [[VAR4]], i32 [[TMP16]]), !llvm.access.group [[ACC_GRP6]]
1600 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1601 // CHECK3:       omp.inner.for.inc:
1602 // CHECK3-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
1603 // CHECK3-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP6]]
1604 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP17]], [[TMP18]]
1605 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
1606 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
1607 // CHECK3:       omp.inner.for.end:
1608 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1609 // CHECK3:       omp.loop.exit:
1610 // CHECK3-NEXT:    [[TMP19:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
1611 // CHECK3-NEXT:    [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4
1612 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP20]])
1613 // CHECK3-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
1614 // CHECK3-NEXT:    [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
1615 // CHECK3-NEXT:    br i1 [[TMP22]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1616 // CHECK3:       .omp.final.then:
1617 // CHECK3-NEXT:    store i32 2, ptr [[I]], align 4
1618 // CHECK3-NEXT:    br label [[DOTOMP_FINAL_DONE]]
1619 // CHECK3:       .omp.final.done:
1620 // CHECK3-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]]
1621 // CHECK3-NEXT:    [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0
1622 // CHECK3-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i32 2
1623 // CHECK3-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1624 // CHECK3:       arraydestroy.body:
1625 // CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP23]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1626 // CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1627 // CHECK3-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1628 // CHECK3-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]
1629 // CHECK3-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]
1630 // CHECK3:       arraydestroy.done8:
1631 // CHECK3-NEXT:    ret void
1632 //
1633 //
1634 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StC1Ev
1635 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1636 // CHECK3-NEXT:  entry:
1637 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1638 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1639 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1640 // CHECK3-NEXT:    call void @_ZN2StC2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]])
1641 // CHECK3-NEXT:    ret void
1642 //
1643 //
1644 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1ERKS0_2St
1645 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1646 // CHECK3-NEXT:  entry:
1647 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1648 // CHECK3-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 4
1649 // CHECK3-NEXT:    [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 4
1650 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1651 // CHECK3-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 4
1652 // CHECK3-NEXT:    store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 4
1653 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1654 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4
1655 // CHECK3-NEXT:    call void @_ZN1SIfEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]])
1656 // CHECK3-NEXT:    ret void
1657 //
1658 //
1659 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StD1Ev
1660 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1661 // CHECK3-NEXT:  entry:
1662 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1663 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1664 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1665 // CHECK3-NEXT:    call void @_ZN2StD2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR2]]
1666 // CHECK3-NEXT:    ret void
1667 //
1668 //
1669 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l101.omp_outlined.omp_outlined
1670 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 noundef [[SIVAR:%.*]]) #[[ATTR5]] {
1671 // CHECK3-NEXT:  entry:
1672 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
1673 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
1674 // CHECK3-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
1675 // CHECK3-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
1676 // CHECK3-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 4
1677 // CHECK3-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i32, align 4
1678 // CHECK3-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 4
1679 // CHECK3-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 4
1680 // CHECK3-NEXT:    [[SIVAR_ADDR:%.*]] = alloca i32, align 4
1681 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1682 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1683 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1684 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1685 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1686 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1687 // CHECK3-NEXT:    [[VEC1:%.*]] = alloca [2 x i32], align 4
1688 // CHECK3-NEXT:    [[S_ARR2:%.*]] = alloca [2 x %struct.S], align 4
1689 // CHECK3-NEXT:    [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
1690 // CHECK3-NEXT:    [[VAR4:%.*]] = alloca [[STRUCT_S:%.*]], align 4
1691 // CHECK3-NEXT:    [[AGG_TMP5:%.*]] = alloca [[STRUCT_ST]], align 4
1692 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
1693 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
1694 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
1695 // CHECK3-NEXT:    store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4
1696 // CHECK3-NEXT:    store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
1697 // CHECK3-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 4
1698 // CHECK3-NEXT:    store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4
1699 // CHECK3-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4
1700 // CHECK3-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 4
1701 // CHECK3-NEXT:    store i32 [[SIVAR]], ptr [[SIVAR_ADDR]], align 4
1702 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4
1703 // CHECK3-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4
1704 // CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4
1705 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
1706 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
1707 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4
1708 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
1709 // CHECK3-NEXT:    store i32 [[TMP3]], ptr [[DOTOMP_LB]], align 4
1710 // CHECK3-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4
1711 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1712 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1713 // CHECK3-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC1]], ptr align 4 [[TMP0]], i32 8, i1 false)
1714 // CHECK3-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0
1715 // CHECK3-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2
1716 // CHECK3-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]]
1717 // CHECK3-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE3:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
1718 // CHECK3:       omp.arraycpy.body:
1719 // CHECK3-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1720 // CHECK3-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1721 // CHECK3-NEXT:    call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]])
1722 // CHECK3-NEXT:    call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]])
1723 // CHECK3-NEXT:    call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
1724 // CHECK3-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
1725 // CHECK3-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
1726 // CHECK3-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]]
1727 // CHECK3-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE3]], label [[OMP_ARRAYCPY_BODY]]
1728 // CHECK3:       omp.arraycpy.done3:
1729 // CHECK3-NEXT:    call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]])
1730 // CHECK3-NEXT:    call void @_ZN1SIfEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP2]], ptr noundef [[AGG_TMP5]])
1731 // CHECK3-NEXT:    call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR2]]
1732 // CHECK3-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
1733 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
1734 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP7]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
1735 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1736 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 1
1737 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1738 // CHECK3:       cond.true:
1739 // CHECK3-NEXT:    br label [[COND_END:%.*]]
1740 // CHECK3:       cond.false:
1741 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1742 // CHECK3-NEXT:    br label [[COND_END]]
1743 // CHECK3:       cond.end:
1744 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]
1745 // CHECK3-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
1746 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1747 // CHECK3-NEXT:    store i32 [[TMP10]], ptr [[DOTOMP_IV]], align 4
1748 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1749 // CHECK3:       omp.inner.for.cond:
1750 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10:![0-9]+]]
1751 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP10]]
1752 // CHECK3-NEXT:    [[CMP6:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]]
1753 // CHECK3-NEXT:    br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1754 // CHECK3:       omp.inner.for.cond.cleanup:
1755 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
1756 // CHECK3:       omp.inner.for.body:
1757 // CHECK3-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]]
1758 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1
1759 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1760 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]]
1761 // CHECK3-NEXT:    [[TMP14:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP10]]
1762 // CHECK3-NEXT:    [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]]
1763 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i32 0, i32 [[TMP15]]
1764 // CHECK3-NEXT:    store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP10]]
1765 // CHECK3-NEXT:    [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]]
1766 // CHECK3-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 [[TMP16]]
1767 // CHECK3-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[VAR4]], i32 4, i1 false), !llvm.access.group [[ACC_GRP10]]
1768 // CHECK3-NEXT:    [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]]
1769 // CHECK3-NEXT:    [[TMP18:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP10]]
1770 // CHECK3-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP18]], [[TMP17]]
1771 // CHECK3-NEXT:    store i32 [[ADD8]], ptr [[SIVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP10]]
1772 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1773 // CHECK3:       omp.body.continue:
1774 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1775 // CHECK3:       omp.inner.for.inc:
1776 // CHECK3-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]]
1777 // CHECK3-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP19]], 1
1778 // CHECK3-NEXT:    store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]]
1779 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
1780 // CHECK3:       omp.inner.for.end:
1781 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1782 // CHECK3:       omp.loop.exit:
1783 // CHECK3-NEXT:    [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
1784 // CHECK3-NEXT:    [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4
1785 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP21]])
1786 // CHECK3-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
1787 // CHECK3-NEXT:    [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
1788 // CHECK3-NEXT:    br i1 [[TMP23]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1789 // CHECK3:       .omp.final.then:
1790 // CHECK3-NEXT:    store i32 2, ptr [[I]], align 4
1791 // CHECK3-NEXT:    br label [[DOTOMP_FINAL_DONE]]
1792 // CHECK3:       .omp.final.done:
1793 // CHECK3-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR2]]
1794 // CHECK3-NEXT:    [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0
1795 // CHECK3-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN10]], i32 2
1796 // CHECK3-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1797 // CHECK3:       arraydestroy.body:
1798 // CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP24]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1799 // CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1800 // CHECK3-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1801 // CHECK3-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]]
1802 // CHECK3-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]]
1803 // CHECK3:       arraydestroy.done11:
1804 // CHECK3-NEXT:    ret void
1805 //
1806 //
1807 // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
1808 // CHECK3-SAME: () #[[ATTR7:[0-9]+]] comdat {
1809 // CHECK3-NEXT:  entry:
1810 // CHECK3-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
1811 // CHECK3-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1812 // CHECK3-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
1813 // CHECK3-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
1814 // CHECK3-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
1815 // CHECK3-NEXT:    [[VAR:%.*]] = alloca ptr, align 4
1816 // CHECK3-NEXT:    [[TMP:%.*]] = alloca ptr, align 4
1817 // CHECK3-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i32, align 4
1818 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 4
1819 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 4
1820 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 4
1821 // CHECK3-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
1822 // CHECK3-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1823 // CHECK3-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])
1824 // CHECK3-NEXT:    store i32 0, ptr [[T_VAR]], align 4
1825 // CHECK3-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false)
1826 // CHECK3-NEXT:    [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
1827 // CHECK3-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef 1)
1828 // CHECK3-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYINIT_BEGIN]], i32 1
1829 // CHECK3-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)
1830 // CHECK3-NEXT:    store ptr [[TEST]], ptr [[VAR]], align 4
1831 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4
1832 // CHECK3-NEXT:    store ptr [[TMP0]], ptr [[TMP]], align 4
1833 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[T_VAR]], align 4
1834 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[T_VAR_CASTED]], align 4
1835 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4
1836 // CHECK3-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4
1837 // CHECK3-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4
1838 // CHECK3-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4
1839 // CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1840 // CHECK3-NEXT:    store i32 [[TMP2]], ptr [[TMP6]], align 4
1841 // CHECK3-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1842 // CHECK3-NEXT:    store i32 [[TMP2]], ptr [[TMP7]], align 4
1843 // CHECK3-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
1844 // CHECK3-NEXT:    store ptr null, ptr [[TMP8]], align 4
1845 // CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1846 // CHECK3-NEXT:    store ptr [[VEC]], ptr [[TMP9]], align 4
1847 // CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1848 // CHECK3-NEXT:    store ptr [[VEC]], ptr [[TMP10]], align 4
1849 // CHECK3-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
1850 // CHECK3-NEXT:    store ptr null, ptr [[TMP11]], align 4
1851 // CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1852 // CHECK3-NEXT:    store ptr [[S_ARR]], ptr [[TMP12]], align 4
1853 // CHECK3-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1854 // CHECK3-NEXT:    store ptr [[S_ARR]], ptr [[TMP13]], align 4
1855 // CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
1856 // CHECK3-NEXT:    store ptr null, ptr [[TMP14]], align 4
1857 // CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1858 // CHECK3-NEXT:    store ptr [[TMP4]], ptr [[TMP15]], align 4
1859 // CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1860 // CHECK3-NEXT:    store ptr [[TMP5]], ptr [[TMP16]], align 4
1861 // CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
1862 // CHECK3-NEXT:    store ptr null, ptr [[TMP17]], align 4
1863 // CHECK3-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1864 // CHECK3-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1865 // CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
1866 // CHECK3-NEXT:    store i32 2, ptr [[TMP20]], align 4
1867 // CHECK3-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
1868 // CHECK3-NEXT:    store i32 4, ptr [[TMP21]], align 4
1869 // CHECK3-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
1870 // CHECK3-NEXT:    store ptr [[TMP18]], ptr [[TMP22]], align 4
1871 // CHECK3-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
1872 // CHECK3-NEXT:    store ptr [[TMP19]], ptr [[TMP23]], align 4
1873 // CHECK3-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
1874 // CHECK3-NEXT:    store ptr @.offload_sizes.3, ptr [[TMP24]], align 4
1875 // CHECK3-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
1876 // CHECK3-NEXT:    store ptr @.offload_maptypes.4, ptr [[TMP25]], align 4
1877 // CHECK3-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
1878 // CHECK3-NEXT:    store ptr null, ptr [[TMP26]], align 4
1879 // CHECK3-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
1880 // CHECK3-NEXT:    store ptr null, ptr [[TMP27]], align 4
1881 // CHECK3-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
1882 // CHECK3-NEXT:    store i64 2, ptr [[TMP28]], align 8
1883 // CHECK3-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
1884 // CHECK3-NEXT:    store i64 0, ptr [[TMP29]], align 8
1885 // CHECK3-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
1886 // CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP30]], align 4
1887 // CHECK3-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
1888 // CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP31]], align 4
1889 // CHECK3-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
1890 // CHECK3-NEXT:    store i32 0, ptr [[TMP32]], align 4
1891 // CHECK3-NEXT:    [[TMP33:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, ptr [[KERNEL_ARGS]])
1892 // CHECK3-NEXT:    [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0
1893 // CHECK3-NEXT:    br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1894 // CHECK3:       omp_offload.failed:
1895 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56(i32 [[TMP2]], ptr [[VEC]], ptr [[S_ARR]], ptr [[TMP3]]) #[[ATTR2]]
1896 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]
1897 // CHECK3:       omp_offload.cont:
1898 // CHECK3-NEXT:    store i32 0, ptr [[RETVAL]], align 4
1899 // CHECK3-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
1900 // CHECK3-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2
1901 // CHECK3-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1902 // CHECK3:       arraydestroy.body:
1903 // CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP35]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1904 // CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1905 // CHECK3-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1906 // CHECK3-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
1907 // CHECK3-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
1908 // CHECK3:       arraydestroy.done2:
1909 // CHECK3-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
1910 // CHECK3-NEXT:    [[TMP36:%.*]] = load i32, ptr [[RETVAL]], align 4
1911 // CHECK3-NEXT:    ret i32 [[TMP36]]
1912 //
1913 //
1914 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StC2Ev
1915 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1916 // CHECK3-NEXT:  entry:
1917 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1918 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1919 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1920 // CHECK3-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[THIS1]], i32 0, i32 0
1921 // CHECK3-NEXT:    store i32 0, ptr [[A]], align 4
1922 // CHECK3-NEXT:    [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[THIS1]], i32 0, i32 1
1923 // CHECK3-NEXT:    store i32 0, ptr [[B]], align 4
1924 // CHECK3-NEXT:    ret void
1925 //
1926 //
1927 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2ERKS0_2St
1928 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1929 // CHECK3-NEXT:  entry:
1930 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1931 // CHECK3-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 4
1932 // CHECK3-NEXT:    [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 4
1933 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1934 // CHECK3-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 4
1935 // CHECK3-NEXT:    store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 4
1936 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1937 // CHECK3-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
1938 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4
1939 // CHECK3-NEXT:    [[F2:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 0
1940 // CHECK3-NEXT:    [[TMP1:%.*]] = load float, ptr [[F2]], align 4
1941 // CHECK3-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0
1942 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 4
1943 // CHECK3-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP2]] to float
1944 // CHECK3-NEXT:    [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]]
1945 // CHECK3-NEXT:    store float [[ADD]], ptr [[F]], align 4
1946 // CHECK3-NEXT:    ret void
1947 //
1948 //
1949 // CHECK3-LABEL: define {{[^@]+}}@_ZN2StD2Ev
1950 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1951 // CHECK3-NEXT:  entry:
1952 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1953 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1954 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1955 // CHECK3-NEXT:    ret void
1956 //
1957 //
1958 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
1959 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1960 // CHECK3-NEXT:  entry:
1961 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1962 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1963 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1964 // CHECK3-NEXT:    call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
1965 // CHECK3-NEXT:    ret void
1966 //
1967 //
1968 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
1969 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1970 // CHECK3-NEXT:  entry:
1971 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1972 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
1973 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1974 // CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
1975 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1976 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
1977 // CHECK3-NEXT:    call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])
1978 // CHECK3-NEXT:    ret void
1979 //
1980 //
1981 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56
1982 // CHECK3-SAME: (i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR4]] {
1983 // CHECK3-NEXT:  entry:
1984 // CHECK3-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i32, align 4
1985 // CHECK3-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 4
1986 // CHECK3-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 4
1987 // CHECK3-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 4
1988 // CHECK3-NEXT:    [[TMP:%.*]] = alloca ptr, align 4
1989 // CHECK3-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i32, align 4
1990 // CHECK3-NEXT:    store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4
1991 // CHECK3-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 4
1992 // CHECK3-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4
1993 // CHECK3-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 4
1994 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4
1995 // CHECK3-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4
1996 // CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4
1997 // CHECK3-NEXT:    store ptr [[TMP2]], ptr [[TMP]], align 4
1998 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4
1999 // CHECK3-NEXT:    store i32 [[TMP3]], ptr [[T_VAR_CASTED]], align 4
2000 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4
2001 // CHECK3-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[TMP]], align 4
2002 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 4, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined, ptr [[TMP0]], i32 [[TMP4]], ptr [[TMP1]], ptr [[TMP5]])
2003 // CHECK3-NEXT:    ret void
2004 //
2005 //
2006 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined
2007 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR5]] {
2008 // CHECK3-NEXT:  entry:
2009 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
2010 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
2011 // CHECK3-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 4
2012 // CHECK3-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i32, align 4
2013 // CHECK3-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 4
2014 // CHECK3-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 4
2015 // CHECK3-NEXT:    [[TMP:%.*]] = alloca ptr, align 4
2016 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2017 // CHECK3-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
2018 // CHECK3-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
2019 // CHECK3-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
2020 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2021 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2022 // CHECK3-NEXT:    [[VEC2:%.*]] = alloca [2 x i32], align 4
2023 // CHECK3-NEXT:    [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4
2024 // CHECK3-NEXT:    [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
2025 // CHECK3-NEXT:    [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
2026 // CHECK3-NEXT:    [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4
2027 // CHECK3-NEXT:    [[_TMP7:%.*]] = alloca ptr, align 4
2028 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
2029 // CHECK3-NEXT:    [[T_VAR_CASTED:%.*]] = alloca i32, align 4
2030 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
2031 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
2032 // CHECK3-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 4
2033 // CHECK3-NEXT:    store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4
2034 // CHECK3-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4
2035 // CHECK3-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 4
2036 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4
2037 // CHECK3-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4
2038 // CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4
2039 // CHECK3-NEXT:    store ptr [[TMP2]], ptr [[TMP]], align 4
2040 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
2041 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_COMB_UB]], align 4
2042 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
2043 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2044 // CHECK3-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i32 8, i1 false)
2045 // CHECK3-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0
2046 // CHECK3-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2
2047 // CHECK3-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP3]]
2048 // CHECK3-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
2049 // CHECK3:       omp.arraycpy.body:
2050 // CHECK3-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2051 // CHECK3-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2052 // CHECK3-NEXT:    call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]])
2053 // CHECK3-NEXT:    call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]])
2054 // CHECK3-NEXT:    call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
2055 // CHECK3-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
2056 // CHECK3-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
2057 // CHECK3-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP3]]
2058 // CHECK3-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]
2059 // CHECK3:       omp.arraycpy.done4:
2060 // CHECK3-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[TMP]], align 4
2061 // CHECK3-NEXT:    call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]])
2062 // CHECK3-NEXT:    call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP4]], ptr noundef [[AGG_TMP6]])
2063 // CHECK3-NEXT:    call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]]
2064 // CHECK3-NEXT:    store ptr [[VAR5]], ptr [[_TMP7]], align 4
2065 // CHECK3-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
2066 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
2067 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP6]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
2068 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2069 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 1
2070 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2071 // CHECK3:       cond.true:
2072 // CHECK3-NEXT:    br label [[COND_END:%.*]]
2073 // CHECK3:       cond.false:
2074 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2075 // CHECK3-NEXT:    br label [[COND_END]]
2076 // CHECK3:       cond.end:
2077 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ]
2078 // CHECK3-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
2079 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
2080 // CHECK3-NEXT:    store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4
2081 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2082 // CHECK3:       omp.inner.for.cond:
2083 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15:![0-9]+]]
2084 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP15]]
2085 // CHECK3-NEXT:    [[CMP8:%.*]] = icmp sle i32 [[TMP10]], [[TMP11]]
2086 // CHECK3-NEXT:    br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2087 // CHECK3:       omp.inner.for.cond.cleanup:
2088 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
2089 // CHECK3:       omp.inner.for.body:
2090 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP15]]
2091 // CHECK3-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP15]]
2092 // CHECK3-NEXT:    [[TMP14:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP15]]
2093 // CHECK3-NEXT:    store i32 [[TMP14]], ptr [[T_VAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP15]]
2094 // CHECK3-NEXT:    [[TMP15:%.*]] = load i32, ptr [[T_VAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP15]]
2095 // CHECK3-NEXT:    [[TMP16:%.*]] = load ptr, ptr [[_TMP7]], align 4, !llvm.access.group [[ACC_GRP15]]
2096 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 6, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined.omp_outlined, i32 [[TMP12]], i32 [[TMP13]], ptr [[VEC2]], i32 [[TMP15]], ptr [[S_ARR3]], ptr [[TMP16]]), !llvm.access.group [[ACC_GRP15]]
2097 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2098 // CHECK3:       omp.inner.for.inc:
2099 // CHECK3-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]]
2100 // CHECK3-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP15]]
2101 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP17]], [[TMP18]]
2102 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]]
2103 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
2104 // CHECK3:       omp.inner.for.end:
2105 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2106 // CHECK3:       omp.loop.exit:
2107 // CHECK3-NEXT:    [[TMP19:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
2108 // CHECK3-NEXT:    [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4
2109 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP20]])
2110 // CHECK3-NEXT:    [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
2111 // CHECK3-NEXT:    [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
2112 // CHECK3-NEXT:    br i1 [[TMP22]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2113 // CHECK3:       .omp.final.then:
2114 // CHECK3-NEXT:    store i32 2, ptr [[I]], align 4
2115 // CHECK3-NEXT:    br label [[DOTOMP_FINAL_DONE]]
2116 // CHECK3:       .omp.final.done:
2117 // CHECK3-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]
2118 // CHECK3-NEXT:    [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0
2119 // CHECK3-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN9]], i32 2
2120 // CHECK3-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
2121 // CHECK3:       arraydestroy.body:
2122 // CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP23]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2123 // CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2124 // CHECK3-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2125 // CHECK3-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]]
2126 // CHECK3-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]]
2127 // CHECK3:       arraydestroy.done10:
2128 // CHECK3-NEXT:    ret void
2129 //
2130 //
2131 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1ERKS0_2St
2132 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2133 // CHECK3-NEXT:  entry:
2134 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2135 // CHECK3-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 4
2136 // CHECK3-NEXT:    [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 4
2137 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2138 // CHECK3-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 4
2139 // CHECK3-NEXT:    store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 4
2140 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2141 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4
2142 // CHECK3-NEXT:    call void @_ZN1SIiEC2ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP0]], ptr noundef [[T]])
2143 // CHECK3-NEXT:    ret void
2144 //
2145 //
2146 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined.omp_outlined
2147 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[VEC:%.*]], i32 noundef [[T_VAR:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR5]] {
2148 // CHECK3-NEXT:  entry:
2149 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
2150 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
2151 // CHECK3-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
2152 // CHECK3-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
2153 // CHECK3-NEXT:    [[VEC_ADDR:%.*]] = alloca ptr, align 4
2154 // CHECK3-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i32, align 4
2155 // CHECK3-NEXT:    [[S_ARR_ADDR:%.*]] = alloca ptr, align 4
2156 // CHECK3-NEXT:    [[VAR_ADDR:%.*]] = alloca ptr, align 4
2157 // CHECK3-NEXT:    [[TMP:%.*]] = alloca ptr, align 4
2158 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2159 // CHECK3-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
2160 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2161 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2162 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2163 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2164 // CHECK3-NEXT:    [[VEC2:%.*]] = alloca [2 x i32], align 4
2165 // CHECK3-NEXT:    [[S_ARR3:%.*]] = alloca [2 x %struct.S.0], align 4
2166 // CHECK3-NEXT:    [[AGG_TMP:%.*]] = alloca [[STRUCT_ST:%.*]], align 4
2167 // CHECK3-NEXT:    [[VAR5:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
2168 // CHECK3-NEXT:    [[AGG_TMP6:%.*]] = alloca [[STRUCT_ST]], align 4
2169 // CHECK3-NEXT:    [[_TMP7:%.*]] = alloca ptr, align 4
2170 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
2171 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
2172 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
2173 // CHECK3-NEXT:    store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4
2174 // CHECK3-NEXT:    store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
2175 // CHECK3-NEXT:    store ptr [[VEC]], ptr [[VEC_ADDR]], align 4
2176 // CHECK3-NEXT:    store i32 [[T_VAR]], ptr [[T_VAR_ADDR]], align 4
2177 // CHECK3-NEXT:    store ptr [[S_ARR]], ptr [[S_ARR_ADDR]], align 4
2178 // CHECK3-NEXT:    store ptr [[VAR]], ptr [[VAR_ADDR]], align 4
2179 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VEC_ADDR]], align 4
2180 // CHECK3-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[S_ARR_ADDR]], align 4
2181 // CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[VAR_ADDR]], align 4
2182 // CHECK3-NEXT:    store ptr [[TMP2]], ptr [[TMP]], align 4
2183 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
2184 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
2185 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4
2186 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
2187 // CHECK3-NEXT:    store i32 [[TMP3]], ptr [[DOTOMP_LB]], align 4
2188 // CHECK3-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4
2189 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
2190 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2191 // CHECK3-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC2]], ptr align 4 [[TMP0]], i32 8, i1 false)
2192 // CHECK3-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0
2193 // CHECK3-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2
2194 // CHECK3-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP5]]
2195 // CHECK3-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE4:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
2196 // CHECK3:       omp.arraycpy.body:
2197 // CHECK3-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi ptr [ [[TMP1]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2198 // CHECK3-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2199 // CHECK3-NEXT:    call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]])
2200 // CHECK3-NEXT:    call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], ptr noundef nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]], ptr noundef [[AGG_TMP]])
2201 // CHECK3-NEXT:    call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP]]) #[[ATTR2]]
2202 // CHECK3-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
2203 // CHECK3-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], ptr [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
2204 // CHECK3-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq ptr [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP5]]
2205 // CHECK3-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE4]], label [[OMP_ARRAYCPY_BODY]]
2206 // CHECK3:       omp.arraycpy.done4:
2207 // CHECK3-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[TMP]], align 4
2208 // CHECK3-NEXT:    call void @_ZN2StC1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]])
2209 // CHECK3-NEXT:    call void @_ZN1SIiEC1ERKS0_2St(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP6]], ptr noundef [[AGG_TMP6]])
2210 // CHECK3-NEXT:    call void @_ZN2StD1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]]
2211 // CHECK3-NEXT:    store ptr [[VAR5]], ptr [[_TMP7]], align 4
2212 // CHECK3-NEXT:    [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
2213 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
2214 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP8]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
2215 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2216 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP9]], 1
2217 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2218 // CHECK3:       cond.true:
2219 // CHECK3-NEXT:    br label [[COND_END:%.*]]
2220 // CHECK3:       cond.false:
2221 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2222 // CHECK3-NEXT:    br label [[COND_END]]
2223 // CHECK3:       cond.end:
2224 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
2225 // CHECK3-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
2226 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
2227 // CHECK3-NEXT:    store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 4
2228 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2229 // CHECK3:       omp.inner.for.cond:
2230 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18:![0-9]+]]
2231 // CHECK3-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP18]]
2232 // CHECK3-NEXT:    [[CMP8:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]]
2233 // CHECK3-NEXT:    br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2234 // CHECK3:       omp.inner.for.cond.cleanup:
2235 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
2236 // CHECK3:       omp.inner.for.body:
2237 // CHECK3-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]]
2238 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP14]], 1
2239 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2240 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]]
2241 // CHECK3-NEXT:    [[TMP15:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP18]]
2242 // CHECK3-NEXT:    [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]]
2243 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i32 0, i32 [[TMP16]]
2244 // CHECK3-NEXT:    store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP18]]
2245 // CHECK3-NEXT:    [[TMP17:%.*]] = load ptr, ptr [[_TMP7]], align 4, !llvm.access.group [[ACC_GRP18]]
2246 // CHECK3-NEXT:    [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]]
2247 // CHECK3-NEXT:    [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 [[TMP18]]
2248 // CHECK3-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP17]], i32 4, i1 false), !llvm.access.group [[ACC_GRP18]]
2249 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2250 // CHECK3:       omp.body.continue:
2251 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2252 // CHECK3:       omp.inner.for.inc:
2253 // CHECK3-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]]
2254 // CHECK3-NEXT:    [[ADD10:%.*]] = add nsw i32 [[TMP19]], 1
2255 // CHECK3-NEXT:    store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]]
2256 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
2257 // CHECK3:       omp.inner.for.end:
2258 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2259 // CHECK3:       omp.loop.exit:
2260 // CHECK3-NEXT:    [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
2261 // CHECK3-NEXT:    [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4
2262 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP21]])
2263 // CHECK3-NEXT:    [[TMP22:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
2264 // CHECK3-NEXT:    [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
2265 // CHECK3-NEXT:    br i1 [[TMP23]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2266 // CHECK3:       .omp.final.then:
2267 // CHECK3-NEXT:    store i32 2, ptr [[I]], align 4
2268 // CHECK3-NEXT:    br label [[DOTOMP_FINAL_DONE]]
2269 // CHECK3:       .omp.final.done:
2270 // CHECK3-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]
2271 // CHECK3-NEXT:    [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0
2272 // CHECK3-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN11]], i32 2
2273 // CHECK3-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
2274 // CHECK3:       arraydestroy.body:
2275 // CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP24]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2276 // CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2277 // CHECK3-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2278 // CHECK3-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN11]]
2279 // CHECK3-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE12:%.*]], label [[ARRAYDESTROY_BODY]]
2280 // CHECK3:       arraydestroy.done12:
2281 // CHECK3-NEXT:    ret void
2282 //
2283 //
2284 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
2285 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2286 // CHECK3-NEXT:  entry:
2287 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2288 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2289 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2290 // CHECK3-NEXT:    call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
2291 // CHECK3-NEXT:    ret void
2292 //
2293 //
2294 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
2295 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2296 // CHECK3-NEXT:  entry:
2297 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2298 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2299 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2300 // CHECK3-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
2301 // CHECK3-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
2302 // CHECK3-NEXT:    store i32 [[TMP0]], ptr [[F]], align 4
2303 // CHECK3-NEXT:    ret void
2304 //
2305 //
2306 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
2307 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2308 // CHECK3-NEXT:  entry:
2309 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2310 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2311 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2312 // CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
2313 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2314 // CHECK3-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
2315 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
2316 // CHECK3-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
2317 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
2318 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[F]], align 4
2319 // CHECK3-NEXT:    ret void
2320 //
2321 //
2322 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2ERKS0_2St
2323 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[S:%.*]], ptr noundef [[T:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2324 // CHECK3-NEXT:  entry:
2325 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2326 // CHECK3-NEXT:    [[S_ADDR:%.*]] = alloca ptr, align 4
2327 // CHECK3-NEXT:    [[T_INDIRECT_ADDR:%.*]] = alloca ptr, align 4
2328 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2329 // CHECK3-NEXT:    store ptr [[S]], ptr [[S_ADDR]], align 4
2330 // CHECK3-NEXT:    store ptr [[T]], ptr [[T_INDIRECT_ADDR]], align 4
2331 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2332 // CHECK3-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
2333 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[S_ADDR]], align 4
2334 // CHECK3-NEXT:    [[F2:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[TMP0]], i32 0, i32 0
2335 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[F2]], align 4
2336 // CHECK3-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[T]], i32 0, i32 0
2337 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 4
2338 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP2]]
2339 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[F]], align 4
2340 // CHECK3-NEXT:    ret void
2341 //
2342 //
2343 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
2344 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2345 // CHECK3-NEXT:  entry:
2346 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2347 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2348 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2349 // CHECK3-NEXT:    ret void
2350 //
2351 //
2352 // CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp
2353 // CHECK3-SAME: () #[[ATTR0]] {
2354 // CHECK3-NEXT:  entry:
2355 // CHECK3-NEXT:    call void @__cxx_global_var_init()
2356 // CHECK3-NEXT:    call void @__cxx_global_var_init.1()
2357 // CHECK3-NEXT:    call void @__cxx_global_var_init.2()
2358 // CHECK3-NEXT:    ret void
2359 //
2360 //
2361 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
2362 // CHECK3-SAME: () #[[ATTR0]] {
2363 // CHECK3-NEXT:  entry:
2364 // CHECK3-NEXT:    call void @__tgt_register_requires(i64 1)
2365 // CHECK3-NEXT:    ret void
2366 //
2367 //
2368 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init
2369 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] {
2370 // CHECK5-NEXT:  entry:
2371 // CHECK5-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
2372 // CHECK5-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
2373 // CHECK5-NEXT:    ret void
2374 //
2375 //
2376 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
2377 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
2378 // CHECK5-NEXT:  entry:
2379 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2380 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2381 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2382 // CHECK5-NEXT:    call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
2383 // CHECK5-NEXT:    ret void
2384 //
2385 //
2386 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
2387 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
2388 // CHECK5-NEXT:  entry:
2389 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2390 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2391 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2392 // CHECK5-NEXT:    call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
2393 // CHECK5-NEXT:    ret void
2394 //
2395 //
2396 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
2397 // CHECK5-SAME: () #[[ATTR0]] {
2398 // CHECK5-NEXT:  entry:
2399 // CHECK5-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
2400 // CHECK5-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)
2401 // CHECK5-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
2402 // CHECK5-NEXT:    ret void
2403 //
2404 //
2405 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
2406 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
2407 // CHECK5-NEXT:  entry:
2408 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2409 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
2410 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2411 // CHECK5-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
2412 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2413 // CHECK5-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
2414 // CHECK5-NEXT:    call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
2415 // CHECK5-NEXT:    ret void
2416 //
2417 //
2418 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
2419 // CHECK5-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {
2420 // CHECK5-NEXT:  entry:
2421 // CHECK5-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
2422 // CHECK5-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
2423 // CHECK5-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
2424 // CHECK5:       arraydestroy.body:
2425 // CHECK5-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2426 // CHECK5-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
2427 // CHECK5-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2428 // CHECK5-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr
2429 // CHECK5-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
2430 // CHECK5:       arraydestroy.done1:
2431 // CHECK5-NEXT:    ret void
2432 //
2433 //
2434 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
2435 // CHECK5-SAME: () #[[ATTR0]] {
2436 // CHECK5-NEXT:  entry:
2437 // CHECK5-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)
2438 // CHECK5-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]
2439 // CHECK5-NEXT:    ret void
2440 //
2441 //
2442 // CHECK5-LABEL: define {{[^@]+}}@main
2443 // CHECK5-SAME: () #[[ATTR3:[0-9]+]] {
2444 // CHECK5-NEXT:  entry:
2445 // CHECK5-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
2446 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2447 // CHECK5-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2448 // CHECK5-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2449 // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2450 // CHECK5-NEXT:    [[I:%.*]] = alloca i32, align 4
2451 // CHECK5-NEXT:    store i32 0, ptr [[RETVAL]], align 4
2452 // CHECK5-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
2453 // CHECK5-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
2454 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
2455 // CHECK5-NEXT:    store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4
2456 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2457 // CHECK5:       omp.inner.for.cond:
2458 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]]
2459 // CHECK5-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP2]]
2460 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
2461 // CHECK5-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2462 // CHECK5:       omp.inner.for.body:
2463 // CHECK5-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
2464 // CHECK5-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
2465 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2466 // CHECK5-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]
2467 // CHECK5-NEXT:    [[TMP4:%.*]] = load i32, ptr @t_var, align 4, !llvm.access.group [[ACC_GRP2]]
2468 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]
2469 // CHECK5-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64
2470 // CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr @vec, i64 0, i64 [[IDXPROM]]
2471 // CHECK5-NEXT:    store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]]
2472 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]
2473 // CHECK5-NEXT:    [[IDXPROM1:%.*]] = sext i32 [[TMP6]] to i64
2474 // CHECK5-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr @s_arr, i64 0, i64 [[IDXPROM1]]
2475 // CHECK5-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX2]], ptr align 4 @var, i64 4, i1 false), !llvm.access.group [[ACC_GRP2]]
2476 // CHECK5-NEXT:    [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]
2477 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4, !llvm.access.group [[ACC_GRP2]]
2478 // CHECK5-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP8]], [[TMP7]]
2479 // CHECK5-NEXT:    store i32 [[ADD3]], ptr @_ZZ4mainE5sivar, align 4, !llvm.access.group [[ACC_GRP2]]
2480 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2481 // CHECK5:       omp.body.continue:
2482 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2483 // CHECK5:       omp.inner.for.inc:
2484 // CHECK5-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
2485 // CHECK5-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP9]], 1
2486 // CHECK5-NEXT:    store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
2487 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
2488 // CHECK5:       omp.inner.for.end:
2489 // CHECK5-NEXT:    store i32 2, ptr [[I]], align 4
2490 // CHECK5-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v()
2491 // CHECK5-NEXT:    ret i32 [[CALL]]
2492 //
2493 //
2494 // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
2495 // CHECK5-SAME: () #[[ATTR5:[0-9]+]] comdat {
2496 // CHECK5-NEXT:  entry:
2497 // CHECK5-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
2498 // CHECK5-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
2499 // CHECK5-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
2500 // CHECK5-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
2501 // CHECK5-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
2502 // CHECK5-NEXT:    [[VAR:%.*]] = alloca ptr, align 8
2503 // CHECK5-NEXT:    [[TMP:%.*]] = alloca ptr, align 8
2504 // CHECK5-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 8
2505 // CHECK5-NEXT:    [[_TMP2:%.*]] = alloca i32, align 4
2506 // CHECK5-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2507 // CHECK5-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2508 // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2509 // CHECK5-NEXT:    [[I:%.*]] = alloca i32, align 4
2510 // CHECK5-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])
2511 // CHECK5-NEXT:    store i32 0, ptr [[T_VAR]], align 4
2512 // CHECK5-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false)
2513 // CHECK5-NEXT:    [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 0
2514 // CHECK5-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef signext 1)
2515 // CHECK5-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYINIT_BEGIN]], i64 1
2516 // CHECK5-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2)
2517 // CHECK5-NEXT:    store ptr [[TEST]], ptr [[VAR]], align 8
2518 // CHECK5-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8
2519 // CHECK5-NEXT:    store ptr [[TMP0]], ptr [[TMP]], align 8
2520 // CHECK5-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[VAR]], align 8
2521 // CHECK5-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8
2522 // CHECK5-NEXT:    store ptr [[TMP2]], ptr [[_TMP1]], align 8
2523 // CHECK5-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 8
2524 // CHECK5-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
2525 // CHECK5-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
2526 // CHECK5-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
2527 // CHECK5-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
2528 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2529 // CHECK5:       omp.inner.for.cond:
2530 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]]
2531 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP6]]
2532 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
2533 // CHECK5-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2534 // CHECK5:       omp.inner.for.body:
2535 // CHECK5-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
2536 // CHECK5-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
2537 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2538 // CHECK5-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]]
2539 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP6]]
2540 // CHECK5-NEXT:    [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]]
2541 // CHECK5-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64
2542 // CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]]
2543 // CHECK5-NEXT:    store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]]
2544 // CHECK5-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[_TMP1]], align 8, !llvm.access.group [[ACC_GRP6]]
2545 // CHECK5-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]]
2546 // CHECK5-NEXT:    [[IDXPROM3:%.*]] = sext i32 [[TMP11]] to i64
2547 // CHECK5-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM3]]
2548 // CHECK5-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP10]], i64 4, i1 false), !llvm.access.group [[ACC_GRP6]]
2549 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2550 // CHECK5:       omp.body.continue:
2551 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2552 // CHECK5:       omp.inner.for.inc:
2553 // CHECK5-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
2554 // CHECK5-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP12]], 1
2555 // CHECK5-NEXT:    store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
2556 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
2557 // CHECK5:       omp.inner.for.end:
2558 // CHECK5-NEXT:    store i32 2, ptr [[I]], align 4
2559 // CHECK5-NEXT:    store i32 0, ptr [[RETVAL]], align 4
2560 // CHECK5-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
2561 // CHECK5-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2
2562 // CHECK5-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
2563 // CHECK5:       arraydestroy.body:
2564 // CHECK5-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP13]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2565 // CHECK5-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
2566 // CHECK5-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2567 // CHECK5-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
2568 // CHECK5-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]]
2569 // CHECK5:       arraydestroy.done6:
2570 // CHECK5-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
2571 // CHECK5-NEXT:    [[TMP14:%.*]] = load i32, ptr [[RETVAL]], align 4
2572 // CHECK5-NEXT:    ret i32 [[TMP14]]
2573 //
2574 //
2575 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
2576 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
2577 // CHECK5-NEXT:  entry:
2578 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2579 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2580 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2581 // CHECK5-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
2582 // CHECK5-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
2583 // CHECK5-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
2584 // CHECK5-NEXT:    store float [[CONV]], ptr [[F]], align 4
2585 // CHECK5-NEXT:    ret void
2586 //
2587 //
2588 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
2589 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
2590 // CHECK5-NEXT:  entry:
2591 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2592 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2593 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2594 // CHECK5-NEXT:    ret void
2595 //
2596 //
2597 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
2598 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
2599 // CHECK5-NEXT:  entry:
2600 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2601 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
2602 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2603 // CHECK5-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
2604 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2605 // CHECK5-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
2606 // CHECK5-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
2607 // CHECK5-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
2608 // CHECK5-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
2609 // CHECK5-NEXT:    [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
2610 // CHECK5-NEXT:    store float [[ADD]], ptr [[F]], align 4
2611 // CHECK5-NEXT:    ret void
2612 //
2613 //
2614 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
2615 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
2616 // CHECK5-NEXT:  entry:
2617 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2618 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2619 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2620 // CHECK5-NEXT:    call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
2621 // CHECK5-NEXT:    ret void
2622 //
2623 //
2624 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
2625 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
2626 // CHECK5-NEXT:  entry:
2627 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2628 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2629 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2630 // CHECK5-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
2631 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2632 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
2633 // CHECK5-NEXT:    call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
2634 // CHECK5-NEXT:    ret void
2635 //
2636 //
2637 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
2638 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
2639 // CHECK5-NEXT:  entry:
2640 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2641 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2642 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2643 // CHECK5-NEXT:    call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
2644 // CHECK5-NEXT:    ret void
2645 //
2646 //
2647 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
2648 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
2649 // CHECK5-NEXT:  entry:
2650 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2651 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2652 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2653 // CHECK5-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
2654 // CHECK5-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
2655 // CHECK5-NEXT:    store i32 [[TMP0]], ptr [[F]], align 4
2656 // CHECK5-NEXT:    ret void
2657 //
2658 //
2659 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
2660 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
2661 // CHECK5-NEXT:  entry:
2662 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2663 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2664 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2665 // CHECK5-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
2666 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2667 // CHECK5-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
2668 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
2669 // CHECK5-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
2670 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
2671 // CHECK5-NEXT:    store i32 [[ADD]], ptr [[F]], align 4
2672 // CHECK5-NEXT:    ret void
2673 //
2674 //
2675 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
2676 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
2677 // CHECK5-NEXT:  entry:
2678 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2679 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2680 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2681 // CHECK5-NEXT:    ret void
2682 //
2683 //
2684 // CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp
2685 // CHECK5-SAME: () #[[ATTR0]] {
2686 // CHECK5-NEXT:  entry:
2687 // CHECK5-NEXT:    call void @__cxx_global_var_init()
2688 // CHECK5-NEXT:    call void @__cxx_global_var_init.1()
2689 // CHECK5-NEXT:    call void @__cxx_global_var_init.2()
2690 // CHECK5-NEXT:    ret void
2691 //
2692 //
2693 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init
2694 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] {
2695 // CHECK7-NEXT:  entry:
2696 // CHECK7-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
2697 // CHECK7-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
2698 // CHECK7-NEXT:    ret void
2699 //
2700 //
2701 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
2702 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
2703 // CHECK7-NEXT:  entry:
2704 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2705 // CHECK7-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2706 // CHECK7-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2707 // CHECK7-NEXT:    call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
2708 // CHECK7-NEXT:    ret void
2709 //
2710 //
2711 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
2712 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2713 // CHECK7-NEXT:  entry:
2714 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2715 // CHECK7-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2716 // CHECK7-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2717 // CHECK7-NEXT:    call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
2718 // CHECK7-NEXT:    ret void
2719 //
2720 //
2721 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
2722 // CHECK7-SAME: () #[[ATTR0]] {
2723 // CHECK7-NEXT:  entry:
2724 // CHECK7-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
2725 // CHECK7-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 1), float noundef 2.000000e+00)
2726 // CHECK7-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
2727 // CHECK7-NEXT:    ret void
2728 //
2729 //
2730 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
2731 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2732 // CHECK7-NEXT:  entry:
2733 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2734 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
2735 // CHECK7-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2736 // CHECK7-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
2737 // CHECK7-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2738 // CHECK7-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
2739 // CHECK7-NEXT:    call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
2740 // CHECK7-NEXT:    ret void
2741 //
2742 //
2743 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
2744 // CHECK7-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {
2745 // CHECK7-NEXT:  entry:
2746 // CHECK7-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 4
2747 // CHECK7-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 4
2748 // CHECK7-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
2749 // CHECK7:       arraydestroy.body:
2750 // CHECK7-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2751 // CHECK7-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2752 // CHECK7-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2753 // CHECK7-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr
2754 // CHECK7-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
2755 // CHECK7:       arraydestroy.done1:
2756 // CHECK7-NEXT:    ret void
2757 //
2758 //
2759 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
2760 // CHECK7-SAME: () #[[ATTR0]] {
2761 // CHECK7-NEXT:  entry:
2762 // CHECK7-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)
2763 // CHECK7-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]
2764 // CHECK7-NEXT:    ret void
2765 //
2766 //
2767 // CHECK7-LABEL: define {{[^@]+}}@main
2768 // CHECK7-SAME: () #[[ATTR3:[0-9]+]] {
2769 // CHECK7-NEXT:  entry:
2770 // CHECK7-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
2771 // CHECK7-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2772 // CHECK7-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2773 // CHECK7-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2774 // CHECK7-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2775 // CHECK7-NEXT:    [[I:%.*]] = alloca i32, align 4
2776 // CHECK7-NEXT:    store i32 0, ptr [[RETVAL]], align 4
2777 // CHECK7-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
2778 // CHECK7-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
2779 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
2780 // CHECK7-NEXT:    store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4
2781 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2782 // CHECK7:       omp.inner.for.cond:
2783 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3:![0-9]+]]
2784 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP3]]
2785 // CHECK7-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
2786 // CHECK7-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2787 // CHECK7:       omp.inner.for.body:
2788 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]
2789 // CHECK7-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
2790 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2791 // CHECK7-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]]
2792 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, ptr @t_var, align 4, !llvm.access.group [[ACC_GRP3]]
2793 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]]
2794 // CHECK7-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr @vec, i32 0, i32 [[TMP5]]
2795 // CHECK7-NEXT:    store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]]
2796 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]]
2797 // CHECK7-NEXT:    [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], ptr @s_arr, i32 0, i32 [[TMP6]]
2798 // CHECK7-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX1]], ptr align 4 @var, i32 4, i1 false), !llvm.access.group [[ACC_GRP3]]
2799 // CHECK7-NEXT:    [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]]
2800 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4, !llvm.access.group [[ACC_GRP3]]
2801 // CHECK7-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], [[TMP7]]
2802 // CHECK7-NEXT:    store i32 [[ADD2]], ptr @_ZZ4mainE5sivar, align 4, !llvm.access.group [[ACC_GRP3]]
2803 // CHECK7-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2804 // CHECK7:       omp.body.continue:
2805 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2806 // CHECK7:       omp.inner.for.inc:
2807 // CHECK7-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]
2808 // CHECK7-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
2809 // CHECK7-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]
2810 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
2811 // CHECK7:       omp.inner.for.end:
2812 // CHECK7-NEXT:    store i32 2, ptr [[I]], align 4
2813 // CHECK7-NEXT:    [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()
2814 // CHECK7-NEXT:    ret i32 [[CALL]]
2815 //
2816 //
2817 // CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
2818 // CHECK7-SAME: () #[[ATTR5:[0-9]+]] comdat {
2819 // CHECK7-NEXT:  entry:
2820 // CHECK7-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
2821 // CHECK7-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
2822 // CHECK7-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
2823 // CHECK7-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
2824 // CHECK7-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
2825 // CHECK7-NEXT:    [[VAR:%.*]] = alloca ptr, align 4
2826 // CHECK7-NEXT:    [[TMP:%.*]] = alloca ptr, align 4
2827 // CHECK7-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 4
2828 // CHECK7-NEXT:    [[_TMP2:%.*]] = alloca i32, align 4
2829 // CHECK7-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2830 // CHECK7-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2831 // CHECK7-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2832 // CHECK7-NEXT:    [[I:%.*]] = alloca i32, align 4
2833 // CHECK7-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])
2834 // CHECK7-NEXT:    store i32 0, ptr [[T_VAR]], align 4
2835 // CHECK7-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false)
2836 // CHECK7-NEXT:    [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
2837 // CHECK7-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef 1)
2838 // CHECK7-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYINIT_BEGIN]], i32 1
2839 // CHECK7-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)
2840 // CHECK7-NEXT:    store ptr [[TEST]], ptr [[VAR]], align 4
2841 // CHECK7-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 4
2842 // CHECK7-NEXT:    store ptr [[TMP0]], ptr [[TMP]], align 4
2843 // CHECK7-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[VAR]], align 4
2844 // CHECK7-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 4
2845 // CHECK7-NEXT:    store ptr [[TMP2]], ptr [[_TMP1]], align 4
2846 // CHECK7-NEXT:    [[TMP3:%.*]] = load ptr, ptr [[TMP]], align 4
2847 // CHECK7-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
2848 // CHECK7-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
2849 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
2850 // CHECK7-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
2851 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2852 // CHECK7:       omp.inner.for.cond:
2853 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7:![0-9]+]]
2854 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP7]]
2855 // CHECK7-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
2856 // CHECK7-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2857 // CHECK7:       omp.inner.for.body:
2858 // CHECK7-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]]
2859 // CHECK7-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
2860 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2861 // CHECK7-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]]
2862 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP7]]
2863 // CHECK7-NEXT:    [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]]
2864 // CHECK7-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]]
2865 // CHECK7-NEXT:    store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP7]]
2866 // CHECK7-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[_TMP1]], align 4, !llvm.access.group [[ACC_GRP7]]
2867 // CHECK7-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]]
2868 // CHECK7-NEXT:    [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP11]]
2869 // CHECK7-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX3]], ptr align 4 [[TMP10]], i32 4, i1 false), !llvm.access.group [[ACC_GRP7]]
2870 // CHECK7-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2871 // CHECK7:       omp.body.continue:
2872 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2873 // CHECK7:       omp.inner.for.inc:
2874 // CHECK7-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]]
2875 // CHECK7-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
2876 // CHECK7-NEXT:    store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]]
2877 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
2878 // CHECK7:       omp.inner.for.end:
2879 // CHECK7-NEXT:    store i32 2, ptr [[I]], align 4
2880 // CHECK7-NEXT:    store i32 0, ptr [[RETVAL]], align 4
2881 // CHECK7-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
2882 // CHECK7-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2
2883 // CHECK7-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
2884 // CHECK7:       arraydestroy.body:
2885 // CHECK7-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP13]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2886 // CHECK7-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2887 // CHECK7-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2888 // CHECK7-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
2889 // CHECK7-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]]
2890 // CHECK7:       arraydestroy.done5:
2891 // CHECK7-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
2892 // CHECK7-NEXT:    [[TMP14:%.*]] = load i32, ptr [[RETVAL]], align 4
2893 // CHECK7-NEXT:    ret i32 [[TMP14]]
2894 //
2895 //
2896 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
2897 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2898 // CHECK7-NEXT:  entry:
2899 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2900 // CHECK7-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2901 // CHECK7-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2902 // CHECK7-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
2903 // CHECK7-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
2904 // CHECK7-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
2905 // CHECK7-NEXT:    store float [[CONV]], ptr [[F]], align 4
2906 // CHECK7-NEXT:    ret void
2907 //
2908 //
2909 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
2910 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2911 // CHECK7-NEXT:  entry:
2912 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2913 // CHECK7-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2914 // CHECK7-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2915 // CHECK7-NEXT:    ret void
2916 //
2917 //
2918 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
2919 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2920 // CHECK7-NEXT:  entry:
2921 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2922 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
2923 // CHECK7-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2924 // CHECK7-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
2925 // CHECK7-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2926 // CHECK7-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
2927 // CHECK7-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
2928 // CHECK7-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
2929 // CHECK7-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
2930 // CHECK7-NEXT:    [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
2931 // CHECK7-NEXT:    store float [[ADD]], ptr [[F]], align 4
2932 // CHECK7-NEXT:    ret void
2933 //
2934 //
2935 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
2936 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2937 // CHECK7-NEXT:  entry:
2938 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2939 // CHECK7-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2940 // CHECK7-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2941 // CHECK7-NEXT:    call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
2942 // CHECK7-NEXT:    ret void
2943 //
2944 //
2945 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
2946 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2947 // CHECK7-NEXT:  entry:
2948 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2949 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2950 // CHECK7-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2951 // CHECK7-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
2952 // CHECK7-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2953 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
2954 // CHECK7-NEXT:    call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])
2955 // CHECK7-NEXT:    ret void
2956 //
2957 //
2958 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
2959 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2960 // CHECK7-NEXT:  entry:
2961 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2962 // CHECK7-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2963 // CHECK7-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2964 // CHECK7-NEXT:    call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
2965 // CHECK7-NEXT:    ret void
2966 //
2967 //
2968 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
2969 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2970 // CHECK7-NEXT:  entry:
2971 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2972 // CHECK7-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2973 // CHECK7-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2974 // CHECK7-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
2975 // CHECK7-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
2976 // CHECK7-NEXT:    store i32 [[TMP0]], ptr [[F]], align 4
2977 // CHECK7-NEXT:    ret void
2978 //
2979 //
2980 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
2981 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2982 // CHECK7-NEXT:  entry:
2983 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2984 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2985 // CHECK7-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2986 // CHECK7-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
2987 // CHECK7-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2988 // CHECK7-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
2989 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
2990 // CHECK7-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
2991 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
2992 // CHECK7-NEXT:    store i32 [[ADD]], ptr [[F]], align 4
2993 // CHECK7-NEXT:    ret void
2994 //
2995 //
2996 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
2997 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2998 // CHECK7-NEXT:  entry:
2999 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
3000 // CHECK7-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
3001 // CHECK7-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
3002 // CHECK7-NEXT:    ret void
3003 //
3004 //
3005 // CHECK7-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp
3006 // CHECK7-SAME: () #[[ATTR0]] {
3007 // CHECK7-NEXT:  entry:
3008 // CHECK7-NEXT:    call void @__cxx_global_var_init()
3009 // CHECK7-NEXT:    call void @__cxx_global_var_init.1()
3010 // CHECK7-NEXT:    call void @__cxx_global_var_init.2()
3011 // CHECK7-NEXT:    ret void
3012 //
3013 //
3014 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init
3015 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] {
3016 // CHECK9-NEXT:  entry:
3017 // CHECK9-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
3018 // CHECK9-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
3019 // CHECK9-NEXT:    ret void
3020 //
3021 //
3022 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
3023 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
3024 // CHECK9-NEXT:  entry:
3025 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
3026 // CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
3027 // CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
3028 // CHECK9-NEXT:    call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
3029 // CHECK9-NEXT:    ret void
3030 //
3031 //
3032 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
3033 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
3034 // CHECK9-NEXT:  entry:
3035 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
3036 // CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
3037 // CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
3038 // CHECK9-NEXT:    call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
3039 // CHECK9-NEXT:    ret void
3040 //
3041 //
3042 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
3043 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
3044 // CHECK9-NEXT:  entry:
3045 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
3046 // CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
3047 // CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
3048 // CHECK9-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
3049 // CHECK9-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
3050 // CHECK9-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
3051 // CHECK9-NEXT:    store float [[CONV]], ptr [[F]], align 4
3052 // CHECK9-NEXT:    ret void
3053 //
3054 //
3055 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
3056 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
3057 // CHECK9-NEXT:  entry:
3058 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
3059 // CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
3060 // CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
3061 // CHECK9-NEXT:    ret void
3062 //
3063 //
3064 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
3065 // CHECK9-SAME: () #[[ATTR0]] {
3066 // CHECK9-NEXT:  entry:
3067 // CHECK9-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
3068 // CHECK9-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)
3069 // CHECK9-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
3070 // CHECK9-NEXT:    ret void
3071 //
3072 //
3073 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
3074 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
3075 // CHECK9-NEXT:  entry:
3076 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
3077 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
3078 // CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
3079 // CHECK9-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
3080 // CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
3081 // CHECK9-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
3082 // CHECK9-NEXT:    call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
3083 // CHECK9-NEXT:    ret void
3084 //
3085 //
3086 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
3087 // CHECK9-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {
3088 // CHECK9-NEXT:  entry:
3089 // CHECK9-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
3090 // CHECK9-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
3091 // CHECK9-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
3092 // CHECK9:       arraydestroy.body:
3093 // CHECK9-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
3094 // CHECK9-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
3095 // CHECK9-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
3096 // CHECK9-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr
3097 // CHECK9-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
3098 // CHECK9:       arraydestroy.done1:
3099 // CHECK9-NEXT:    ret void
3100 //
3101 //
3102 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
3103 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
3104 // CHECK9-NEXT:  entry:
3105 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
3106 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
3107 // CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
3108 // CHECK9-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
3109 // CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
3110 // CHECK9-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
3111 // CHECK9-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
3112 // CHECK9-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
3113 // CHECK9-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
3114 // CHECK9-NEXT:    [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
3115 // CHECK9-NEXT:    store float [[ADD]], ptr [[F]], align 4
3116 // CHECK9-NEXT:    ret void
3117 //
3118 //
3119 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
3120 // CHECK9-SAME: () #[[ATTR0]] {
3121 // CHECK9-NEXT:  entry:
3122 // CHECK9-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)
3123 // CHECK9-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]
3124 // CHECK9-NEXT:    ret void
3125 //
3126 //
3127 // CHECK9-LABEL: define {{[^@]+}}@main
3128 // CHECK9-SAME: () #[[ATTR3:[0-9]+]] {
3129 // CHECK9-NEXT:  entry:
3130 // CHECK9-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
3131 // CHECK9-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
3132 // CHECK9-NEXT:    store i32 0, ptr [[RETVAL]], align 4
3133 // CHECK9-NEXT:    call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])
3134 // CHECK9-NEXT:    ret i32 0
3135 //
3136 //
3137 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75
3138 // CHECK9-SAME: (i64 noundef [[G:%.*]], i64 noundef [[SIVAR:%.*]], i64 noundef [[G1:%.*]]) #[[ATTR5:[0-9]+]] {
3139 // CHECK9-NEXT:  entry:
3140 // CHECK9-NEXT:    [[G_ADDR:%.*]] = alloca i64, align 8
3141 // CHECK9-NEXT:    [[SIVAR_ADDR:%.*]] = alloca i64, align 8
3142 // CHECK9-NEXT:    [[G1_ADDR:%.*]] = alloca i64, align 8
3143 // CHECK9-NEXT:    [[TMP:%.*]] = alloca ptr, align 8
3144 // CHECK9-NEXT:    [[G_CASTED:%.*]] = alloca i64, align 8
3145 // CHECK9-NEXT:    [[G1_CASTED:%.*]] = alloca i64, align 8
3146 // CHECK9-NEXT:    [[SIVAR_CASTED:%.*]] = alloca i64, align 8
3147 // CHECK9-NEXT:    store i64 [[G]], ptr [[G_ADDR]], align 8
3148 // CHECK9-NEXT:    store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8
3149 // CHECK9-NEXT:    store i64 [[G1]], ptr [[G1_ADDR]], align 8
3150 // CHECK9-NEXT:    store ptr [[G1_ADDR]], ptr [[TMP]], align 8
3151 // CHECK9-NEXT:    [[TMP0:%.*]] = load i32, ptr [[G_ADDR]], align 4
3152 // CHECK9-NEXT:    store i32 [[TMP0]], ptr [[G_CASTED]], align 4
3153 // CHECK9-NEXT:    [[TMP1:%.*]] = load i64, ptr [[G_CASTED]], align 8
3154 // CHECK9-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[TMP]], align 8
3155 // CHECK9-NEXT:    [[TMP3:%.*]] = load volatile i32, ptr [[TMP2]], align 4
3156 // CHECK9-NEXT:    store i32 [[TMP3]], ptr [[G1_CASTED]], align 4
3157 // CHECK9-NEXT:    [[TMP4:%.*]] = load i64, ptr [[G1_CASTED]], align 8
3158 // CHECK9-NEXT:    [[TMP5:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4
3159 // CHECK9-NEXT:    store i32 [[TMP5]], ptr [[SIVAR_CASTED]], align 4
3160 // CHECK9-NEXT:    [[TMP6:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8
3161 // CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 3, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75.omp_outlined, i64 [[TMP1]], i64 [[TMP4]], i64 [[TMP6]])
3162 // CHECK9-NEXT:    ret void
3163 //
3164 //
3165 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75.omp_outlined
3166 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR6:[0-9]+]] {
3167 // CHECK9-NEXT:  entry:
3168 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
3169 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
3170 // CHECK9-NEXT:    [[G_ADDR:%.*]] = alloca i64, align 8
3171 // CHECK9-NEXT:    [[G1_ADDR:%.*]] = alloca i64, align 8
3172 // CHECK9-NEXT:    [[SIVAR_ADDR:%.*]] = alloca i64, align 8
3173 // CHECK9-NEXT:    [[TMP:%.*]] = alloca ptr, align 8
3174 // CHECK9-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
3175 // CHECK9-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
3176 // CHECK9-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
3177 // CHECK9-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
3178 // CHECK9-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3179 // CHECK9-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3180 // CHECK9-NEXT:    [[I:%.*]] = alloca i32, align 4
3181 // CHECK9-NEXT:    [[G_CASTED:%.*]] = alloca i64, align 8
3182 // CHECK9-NEXT:    [[G1_CASTED:%.*]] = alloca i64, align 8
3183 // CHECK9-NEXT:    [[SIVAR_CASTED:%.*]] = alloca i64, align 8
3184 // CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
3185 // CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
3186 // CHECK9-NEXT:    store i64 [[G]], ptr [[G_ADDR]], align 8
3187 // CHECK9-NEXT:    store i64 [[G1]], ptr [[G1_ADDR]], align 8
3188 // CHECK9-NEXT:    store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8
3189 // CHECK9-NEXT:    store ptr [[G1_ADDR]], ptr [[TMP]], align 8
3190 // CHECK9-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
3191 // CHECK9-NEXT:    store i32 1, ptr [[DOTOMP_COMB_UB]], align 4
3192 // CHECK9-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
3193 // CHECK9-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
3194 // CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
3195 // CHECK9-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
3196 // CHECK9-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
3197 // CHECK9-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
3198 // CHECK9-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
3199 // CHECK9-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3200 // CHECK9:       cond.true:
3201 // CHECK9-NEXT:    br label [[COND_END:%.*]]
3202 // CHECK9:       cond.false:
3203 // CHECK9-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
3204 // CHECK9-NEXT:    br label [[COND_END]]
3205 // CHECK9:       cond.end:
3206 // CHECK9-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
3207 // CHECK9-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
3208 // CHECK9-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
3209 // CHECK9-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
3210 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
3211 // CHECK9:       omp.inner.for.cond:
3212 // CHECK9-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4:![0-9]+]]
3213 // CHECK9-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP4]]
3214 // CHECK9-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
3215 // CHECK9-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3216 // CHECK9:       omp.inner.for.body:
3217 // CHECK9-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP4]]
3218 // CHECK9-NEXT:    [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
3219 // CHECK9-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP4]]
3220 // CHECK9-NEXT:    [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
3221 // CHECK9-NEXT:    [[TMP11:%.*]] = load i32, ptr [[G_ADDR]], align 4, !llvm.access.group [[ACC_GRP4]]
3222 // CHECK9-NEXT:    store i32 [[TMP11]], ptr [[G_CASTED]], align 4, !llvm.access.group [[ACC_GRP4]]
3223 // CHECK9-NEXT:    [[TMP12:%.*]] = load i64, ptr [[G_CASTED]], align 8, !llvm.access.group [[ACC_GRP4]]
3224 // CHECK9-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[TMP]], align 8, !llvm.access.group [[ACC_GRP4]]
3225 // CHECK9-NEXT:    [[TMP14:%.*]] = load volatile i32, ptr [[TMP13]], align 4, !llvm.access.group [[ACC_GRP4]]
3226 // CHECK9-NEXT:    store i32 [[TMP14]], ptr [[G1_CASTED]], align 4, !llvm.access.group [[ACC_GRP4]]
3227 // CHECK9-NEXT:    [[TMP15:%.*]] = load i64, ptr [[G1_CASTED]], align 8, !llvm.access.group [[ACC_GRP4]]
3228 // CHECK9-NEXT:    [[TMP16:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP4]]
3229 // CHECK9-NEXT:    store i32 [[TMP16]], ptr [[SIVAR_CASTED]], align 4, !llvm.access.group [[ACC_GRP4]]
3230 // CHECK9-NEXT:    [[TMP17:%.*]] = load i64, ptr [[SIVAR_CASTED]], align 8, !llvm.access.group [[ACC_GRP4]]
3231 // CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 5, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]], i64 [[TMP12]], i64 [[TMP15]], i64 [[TMP17]]), !llvm.access.group [[ACC_GRP4]]
3232 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
3233 // CHECK9:       omp.inner.for.inc:
3234 // CHECK9-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]]
3235 // CHECK9-NEXT:    [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP4]]
3236 // CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
3237 // CHECK9-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]]
3238 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
3239 // CHECK9:       omp.inner.for.end:
3240 // CHECK9-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
3241 // CHECK9:       omp.loop.exit:
3242 // CHECK9-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
3243 // CHECK9-NEXT:    [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
3244 // CHECK9-NEXT:    [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
3245 // CHECK9-NEXT:    br i1 [[TMP21]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
3246 // CHECK9:       .omp.final.then:
3247 // CHECK9-NEXT:    store i32 2, ptr [[I]], align 4
3248 // CHECK9-NEXT:    br label [[DOTOMP_FINAL_DONE]]
3249 // CHECK9:       .omp.final.done:
3250 // CHECK9-NEXT:    ret void
3251 //
3252 //
3253 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75.omp_outlined.omp_outlined
3254 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[G:%.*]], i64 noundef [[G1:%.*]], i64 noundef [[SIVAR:%.*]]) #[[ATTR6]] {
3255 // CHECK9-NEXT:  entry:
3256 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
3257 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
3258 // CHECK9-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
3259 // CHECK9-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
3260 // CHECK9-NEXT:    [[G_ADDR:%.*]] = alloca i64, align 8
3261 // CHECK9-NEXT:    [[G1_ADDR:%.*]] = alloca i64, align 8
3262 // CHECK9-NEXT:    [[SIVAR_ADDR:%.*]] = alloca i64, align 8
3263 // CHECK9-NEXT:    [[TMP:%.*]] = alloca ptr, align 8
3264 // CHECK9-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
3265 // CHECK9-NEXT:    [[_TMP1:%.*]] = alloca i32, align 4
3266 // CHECK9-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
3267 // CHECK9-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
3268 // CHECK9-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
3269 // CHECK9-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
3270 // CHECK9-NEXT:    [[I:%.*]] = alloca i32, align 4
3271 // CHECK9-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8
3272 // CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
3273 // CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
3274 // CHECK9-NEXT:    store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
3275 // CHECK9-NEXT:    store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
3276 // CHECK9-NEXT:    store i64 [[G]], ptr [[G_ADDR]], align 8
3277 // CHECK9-NEXT:    store i64 [[G1]], ptr [[G1_ADDR]], align 8
3278 // CHECK9-NEXT:    store i64 [[SIVAR]], ptr [[SIVAR_ADDR]], align 8
3279 // CHECK9-NEXT:    store ptr [[G1_ADDR]], ptr [[TMP]], align 8
3280 // CHECK9-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
3281 // CHECK9-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
3282 // CHECK9-NEXT:    [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
3283 // CHECK9-NEXT:    [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
3284 // CHECK9-NEXT:    [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
3285 // CHECK9-NEXT:    [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32
3286 // CHECK9-NEXT:    store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
3287 // CHECK9-NEXT:    store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4
3288 // CHECK9-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
3289 // CHECK9-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
3290 // CHECK9-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
3291 // CHECK9-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
3292 // CHECK9-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
3293 // CHECK9-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
3294 // CHECK9-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1
3295 // CHECK9-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
3296 // CHECK9:       cond.true:
3297 // CHECK9-NEXT:    br label [[COND_END:%.*]]
3298 // CHECK9:       cond.false:
3299 // CHECK9-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
3300 // CHECK9-NEXT:    br label [[COND_END]]
3301 // CHECK9:       cond.end:
3302 // CHECK9-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
3303 // CHECK9-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
3304 // CHECK9-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
3305 // CHECK9-NEXT:    store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4
3306 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
3307 // CHECK9:       omp.inner.for.cond:
3308 // CHECK9-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8:![0-9]+]]
3309 // CHECK9-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP8]]
3310 // CHECK9-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
3311 // CHECK9-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
3312 // CHECK9:       omp.inner.for.body:
3313 // CHECK9-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]]
3314 // CHECK9-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
3315 // CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
3316 // CHECK9-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]]
3317 // CHECK9-NEXT:    store i32 1, ptr [[G_ADDR]], align 4, !llvm.access.group [[ACC_GRP8]]
3318 // CHECK9-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[TMP]], align 8, !llvm.access.group [[ACC_GRP8]]
3319 // CHECK9-NEXT:    store volatile i32 1, ptr [[TMP10]], align 4, !llvm.access.group [[ACC_GRP8]]
3320 // CHECK9-NEXT:    store i32 2, ptr [[SIVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP8]]
3321 // CHECK9-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0
3322 // CHECK9-NEXT:    store ptr [[G_ADDR]], ptr [[TMP11]], align 8, !llvm.access.group [[ACC_GRP8]]
3323 // CHECK9-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1
3324 // CHECK9-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[TMP]], align 8, !llvm.access.group [[ACC_GRP8]]
3325 // CHECK9-NEXT:    store ptr [[TMP13]], ptr [[TMP12]], align 8, !llvm.access.group [[ACC_GRP8]]
3326 // CHECK9-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2
3327 // CHECK9-NEXT:    store ptr [[SIVAR_ADDR]], ptr [[TMP14]], align 8, !llvm.access.group [[ACC_GRP8]]
3328 // CHECK9-NEXT:    call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]), !llvm.access.group [[ACC_GRP8]]
3329 // CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
3330 // CHECK9:       omp.body.continue:
3331 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
3332 // CHECK9:       omp.inner.for.inc:
3333 // CHECK9-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]]
3334 // CHECK9-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP15]], 1
3335 // CHECK9-NEXT:    store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]]
3336 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
3337 // CHECK9:       omp.inner.for.end:
3338 // CHECK9-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
3339 // CHECK9:       omp.loop.exit:
3340 // CHECK9-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]])
3341 // CHECK9-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
3342 // CHECK9-NEXT:    [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
3343 // CHECK9-NEXT:    br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
3344 // CHECK9:       .omp.final.then:
3345 // CHECK9-NEXT:    store i32 2, ptr [[I]], align 4
3346 // CHECK9-NEXT:    br label [[DOTOMP_FINAL_DONE]]
3347 // CHECK9:       .omp.final.done:
3348 // CHECK9-NEXT:    ret void
3349 //
3350 //
3351 // CHECK9-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp
3352 // CHECK9-SAME: () #[[ATTR0]] {
3353 // CHECK9-NEXT:  entry:
3354 // CHECK9-NEXT:    call void @__cxx_global_var_init()
3355 // CHECK9-NEXT:    call void @__cxx_global_var_init.1()
3356 // CHECK9-NEXT:    call void @__cxx_global_var_init.2()
3357 // CHECK9-NEXT:    ret void
3358 //
3359 //
3360 // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
3361 // CHECK9-SAME: () #[[ATTR0]] {
3362 // CHECK9-NEXT:  entry:
3363 // CHECK9-NEXT:    call void @__tgt_register_requires(i64 1)
3364 // CHECK9-NEXT:    ret void
3365 //
3366 //
3367 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init
3368 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] {
3369 // CHECK11-NEXT:  entry:
3370 // CHECK11-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
3371 // CHECK11-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
3372 // CHECK11-NEXT:    ret void
3373 //
3374 //
3375 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
3376 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
3377 // CHECK11-NEXT:  entry:
3378 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
3379 // CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
3380 // CHECK11-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
3381 // CHECK11-NEXT:    call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
3382 // CHECK11-NEXT:    ret void
3383 //
3384 //
3385 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
3386 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
3387 // CHECK11-NEXT:  entry:
3388 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
3389 // CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
3390 // CHECK11-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
3391 // CHECK11-NEXT:    call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
3392 // CHECK11-NEXT:    ret void
3393 //
3394 //
3395 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
3396 // CHECK11-SAME: () #[[ATTR0]] {
3397 // CHECK11-NEXT:  entry:
3398 // CHECK11-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
3399 // CHECK11-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)
3400 // CHECK11-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
3401 // CHECK11-NEXT:    ret void
3402 //
3403 //
3404 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
3405 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
3406 // CHECK11-NEXT:  entry:
3407 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
3408 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
3409 // CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
3410 // CHECK11-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
3411 // CHECK11-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
3412 // CHECK11-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
3413 // CHECK11-NEXT:    call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
3414 // CHECK11-NEXT:    ret void
3415 //
3416 //
3417 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
3418 // CHECK11-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {
3419 // CHECK11-NEXT:  entry:
3420 // CHECK11-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
3421 // CHECK11-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
3422 // CHECK11-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
3423 // CHECK11:       arraydestroy.body:
3424 // CHECK11-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
3425 // CHECK11-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
3426 // CHECK11-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
3427 // CHECK11-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr
3428 // CHECK11-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
3429 // CHECK11:       arraydestroy.done1:
3430 // CHECK11-NEXT:    ret void
3431 //
3432 //
3433 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
3434 // CHECK11-SAME: () #[[ATTR0]] {
3435 // CHECK11-NEXT:  entry:
3436 // CHECK11-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)
3437 // CHECK11-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]
3438 // CHECK11-NEXT:    ret void
3439 //
3440 //
3441 // CHECK11-LABEL: define {{[^@]+}}@main
3442 // CHECK11-SAME: () #[[ATTR3:[0-9]+]] {
3443 // CHECK11-NEXT:  entry:
3444 // CHECK11-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
3445 // CHECK11-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
3446 // CHECK11-NEXT:    store i32 0, ptr [[RETVAL]], align 4
3447 // CHECK11-NEXT:    call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])
3448 // CHECK11-NEXT:    ret i32 0
3449 //
3450 //
3451 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
3452 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
3453 // CHECK11-NEXT:  entry:
3454 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
3455 // CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
3456 // CHECK11-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
3457 // CHECK11-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
3458 // CHECK11-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
3459 // CHECK11-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
3460 // CHECK11-NEXT:    store float [[CONV]], ptr [[F]], align 4
3461 // CHECK11-NEXT:    ret void
3462 //
3463 //
3464 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
3465 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
3466 // CHECK11-NEXT:  entry:
3467 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
3468 // CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
3469 // CHECK11-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
3470 // CHECK11-NEXT:    ret void
3471 //
3472 //
3473 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
3474 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
3475 // CHECK11-NEXT:  entry:
3476 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
3477 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
3478 // CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
3479 // CHECK11-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
3480 // CHECK11-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
3481 // CHECK11-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
3482 // CHECK11-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
3483 // CHECK11-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
3484 // CHECK11-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
3485 // CHECK11-NEXT:    [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
3486 // CHECK11-NEXT:    store float [[ADD]], ptr [[F]], align 4
3487 // CHECK11-NEXT:    ret void
3488 //
3489 //
3490 // CHECK11-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp
3491 // CHECK11-SAME: () #[[ATTR0]] {
3492 // CHECK11-NEXT:  entry:
3493 // CHECK11-NEXT:    call void @__cxx_global_var_init()
3494 // CHECK11-NEXT:    call void @__cxx_global_var_init.1()
3495 // CHECK11-NEXT:    call void @__cxx_global_var_init.2()
3496 // CHECK11-NEXT:    ret void
3497 //