clang/test/OpenMP/teams_distribute_parallel_for_simd_private_codegen.cpp

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
   2 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK1
   3 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
   4 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK1
   5 // RUN: %clang_cc1 -DCHECK -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK3
   6 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
   7 // RUN: %clang_cc1 -DCHECK -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK3
   8
   9 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK5
  10 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
  11 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK5
  12 // RUN: %clang_cc1 -DCHECK -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK7
  13 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
  14 // RUN: %clang_cc1 -DCHECK -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK7
  15
  16 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK9
  17 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
  18 // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++  -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK9
  19
  20 // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK11
  21 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
  22 // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++  -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap  %s --check-prefix=CHECK11
  23
  24 // expected-no-diagnostics
  25 #ifndef HEADER
  26 #define HEADER
  27
  28 struct St {
  29   int a, b;
  30   St() : a(0), b(0) {}
  31   St(const St &st) : a(st.a + st.b), b(0) {}
  32   ~St() {}
  33 };
  34
  35 volatile int g = 1212;
  36 volatile int &g1 = g;
  37
  38 template <class T>
  39 struct S {
  40   T f;
  41   S(T a) : f(a + g) {}
  42   S() : f(g) {}
  43   S(const S &s, St t = St()) : f(s.f + t.a) {}
  44   operator T() { return T(); }
  45   ~S() {}
  46 };
  47
  48
  49 template <typename T>
  50 T tmain() {
  51   S<T> test;
  52   T t_var = T();
  53   T vec[] = {1, 2};
  54   S<T> s_arr[] = {1, 2};
  55   S<T> &var = test;
  56 #pragma omp target
  57 #pragma omp teams distribute parallel for simd private(t_var, vec, s_arr, var)
  58   for (int i = 0; i < 2; ++i) {
  59     vec[i] = t_var;
  60     s_arr[i] = var;
  61   }
  62   return T();
  63 }
  64
  65 S<float> test;
  66 int t_var = 333;
  67 int vec[] = {1, 2};
  68 S<float> s_arr[] = {1, 2};
  69 S<float> var(3);
  70
  71 int main() {
  72   static int sivar;
  73 #ifdef LAMBDA
  74   [&]() {
  75 #pragma omp target
  76 #pragma omp teams distribute parallel for simd private(g, g1, sivar)
  77   for (int i = 0; i < 2; ++i) {
  78
  79     // Skip global, bound tid and loop vars
  80
  81     g = 1;
  82     g1 = 1;
  83     sivar = 2;
  84
  85     // Skip global, bound tid and loop vars
  86     [&]() {
  87       g = 2;
  88       g1 = 2;
  89       sivar = 4;
  90
  91     }();
  92   }
  93   }();
  94   return 0;
  95
  96
  97 #else
  98 #pragma omp target
  99 #pragma omp teams distribute parallel for simd private(t_var, vec, s_arr, var, sivar)
 100   for (int i = 0; i < 2; ++i) {
 101     vec[i] = t_var;
 102     s_arr[i] = var;
 103     sivar += i;
 104   }
 105   return tmain<int>();
 106 #endif
 107 }
 108
 109
 110
 111 // Skip global, bound tid and loop vars
 112
 113 // private(s_arr)
 114
 115 // private(var)
 116
 117
 118 // Skip global, bound tid and loop vars
 119
 120 // private(s_arr)
 121
 122 // private(var)
 123
 124
 125
 126
 127 // Skip global, bound tid and loop vars
 128
 129 // private(s_arr)
 130
 131
 132 // private(var)
 133
 134
 135 // Skip global, bound tid and loop vars
 136 // prev lb and ub
 137 // iter variables
 138
 139 // private(s_arr)
 140
 141
 142 // private(var)
 143
 144
 145
 146 #endif
 147 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init
 148 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
 149 // CHECK1-NEXT:  entry:
 150 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
 151 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
 152 // CHECK1-NEXT:    ret void
 153 //
 154 //
 155 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
 156 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
 157 // CHECK1-NEXT:  entry:
 158 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 159 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 160 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 161 // CHECK1-NEXT:    call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
 162 // CHECK1-NEXT:    ret void
 163 //
 164 //
 165 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
 166 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
 167 // CHECK1-NEXT:  entry:
 168 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 169 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 170 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 171 // CHECK1-NEXT:    call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
 172 // CHECK1-NEXT:    ret void
 173 //
 174 //
 175 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
 176 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
 177 // CHECK1-NEXT:  entry:
 178 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 179 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 180 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 181 // CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
 182 // CHECK1-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
 183 // CHECK1-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
 184 // CHECK1-NEXT:    store float [[CONV]], ptr [[F]], align 4
 185 // CHECK1-NEXT:    ret void
 186 //
 187 //
 188 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
 189 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
 190 // CHECK1-NEXT:  entry:
 191 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 192 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 193 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 194 // CHECK1-NEXT:    ret void
 195 //
 196 //
 197 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
 198 // CHECK1-SAME: () #[[ATTR0]] {
 199 // CHECK1-NEXT:  entry:
 200 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
 201 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)
 202 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
 203 // CHECK1-NEXT:    ret void
 204 //
 205 //
 206 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
 207 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
 208 // CHECK1-NEXT:  entry:
 209 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 210 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
 211 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 212 // CHECK1-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
 213 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 214 // CHECK1-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
 215 // CHECK1-NEXT:    call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
 216 // CHECK1-NEXT:    ret void
 217 //
 218 //
 219 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
 220 // CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {
 221 // CHECK1-NEXT:  entry:
 222 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
 223 // CHECK1-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
 224 // CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
 225 // CHECK1:       arraydestroy.body:
 226 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
 227 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
 228 // CHECK1-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
 229 // CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr
 230 // CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
 231 // CHECK1:       arraydestroy.done1:
 232 // CHECK1-NEXT:    ret void
 233 //
 234 //
 235 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
 236 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
 237 // CHECK1-NEXT:  entry:
 238 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 239 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
 240 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 241 // CHECK1-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
 242 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 243 // CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
 244 // CHECK1-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
 245 // CHECK1-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
 246 // CHECK1-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
 247 // CHECK1-NEXT:    [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
 248 // CHECK1-NEXT:    store float [[ADD]], ptr [[F]], align 4
 249 // CHECK1-NEXT:    ret void
 250 //
 251 //
 252 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
 253 // CHECK1-SAME: () #[[ATTR0]] {
 254 // CHECK1-NEXT:  entry:
 255 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)
 256 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]
 257 // CHECK1-NEXT:    ret void
 258 //
 259 //
 260 // CHECK1-LABEL: define {{[^@]+}}@main
 261 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] {
 262 // CHECK1-NEXT:  entry:
 263 // CHECK1-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
 264 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 265 // CHECK1-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
 266 // CHECK1-NEXT:    store i32 0, ptr [[RETVAL]], align 4
 267 // CHECK1-NEXT:    [[TMP0:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
 268 // CHECK1-NEXT:    store i32 2, ptr [[TMP0]], align 4
 269 // CHECK1-NEXT:    [[TMP1:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
 270 // CHECK1-NEXT:    store i32 0, ptr [[TMP1]], align 4
 271 // CHECK1-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
 272 // CHECK1-NEXT:    store ptr null, ptr [[TMP2]], align 8
 273 // CHECK1-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
 274 // CHECK1-NEXT:    store ptr null, ptr [[TMP3]], align 8
 275 // CHECK1-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
 276 // CHECK1-NEXT:    store ptr null, ptr [[TMP4]], align 8
 277 // CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
 278 // CHECK1-NEXT:    store ptr null, ptr [[TMP5]], align 8
 279 // CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
 280 // CHECK1-NEXT:    store ptr null, ptr [[TMP6]], align 8
 281 // CHECK1-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
 282 // CHECK1-NEXT:    store ptr null, ptr [[TMP7]], align 8
 283 // CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
 284 // CHECK1-NEXT:    store i64 2, ptr [[TMP8]], align 8
 285 // CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
 286 // CHECK1-NEXT:    store i64 0, ptr [[TMP9]], align 8
 287 // CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
 288 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4
 289 // CHECK1-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
 290 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4
 291 // CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
 292 // CHECK1-NEXT:    store i32 0, ptr [[TMP12]], align 4
 293 // CHECK1-NEXT:    [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98.region_id, ptr [[KERNEL_ARGS]])
 294 // CHECK1-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
 295 // CHECK1-NEXT:    br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
 296 // CHECK1:       omp_offload.failed:
 297 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98() #[[ATTR2]]
 298 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
 299 // CHECK1:       omp_offload.cont:
 300 // CHECK1-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v()
 301 // CHECK1-NEXT:    ret i32 [[CALL]]
 302 //
 303 //
 304 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98
 305 // CHECK1-SAME: () #[[ATTR4:[0-9]+]] {
 306 // CHECK1-NEXT:  entry:
 307 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98.omp_outlined)
 308 // CHECK1-NEXT:    ret void
 309 //
 310 //
 311 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98.omp_outlined
 312 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5:[0-9]+]] {
 313 // CHECK1-NEXT:  entry:
 314 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 315 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 316 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 317 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 318 // CHECK1-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
 319 // CHECK1-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
 320 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 321 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 322 // CHECK1-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
 323 // CHECK1-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
 324 // CHECK1-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
 325 // CHECK1-NEXT:    [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
 326 // CHECK1-NEXT:    [[SIVAR:%.*]] = alloca i32, align 4
 327 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
 328 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 329 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 330 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
 331 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_COMB_UB]], align 4
 332 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 333 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 334 // CHECK1-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
 335 // CHECK1-NEXT:    [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2
 336 // CHECK1-NEXT:    br label [[ARRAYCTOR_LOOP:%.*]]
 337 // CHECK1:       arrayctor.loop:
 338 // CHECK1-NEXT:    [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
 339 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
 340 // CHECK1-NEXT:    [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1
 341 // CHECK1-NEXT:    [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
 342 // CHECK1-NEXT:    br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
 343 // CHECK1:       arrayctor.cont:
 344 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]])
 345 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 346 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
 347 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
 348 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 349 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
 350 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 351 // CHECK1:       cond.true:
 352 // CHECK1-NEXT:    br label [[COND_END:%.*]]
 353 // CHECK1:       cond.false:
 354 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 355 // CHECK1-NEXT:    br label [[COND_END]]
 356 // CHECK1:       cond.end:
 357 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
 358 // CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
 359 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
 360 // CHECK1-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
 361 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 362 // CHECK1:       omp.inner.for.cond:
 363 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5:![0-9]+]]
 364 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP5]]
 365 // CHECK1-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
 366 // CHECK1-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
 367 // CHECK1:       omp.inner.for.cond.cleanup:
 368 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
 369 // CHECK1:       omp.inner.for.body:
 370 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP5]]
 371 // CHECK1-NEXT:    [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
 372 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP5]]
 373 // CHECK1-NEXT:    [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
 374 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP5]]
 375 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 376 // CHECK1:       omp.inner.for.inc:
 377 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]]
 378 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP5]]
 379 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
 380 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP5]]
 381 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
 382 // CHECK1:       omp.inner.for.end:
 383 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
 384 // CHECK1:       omp.loop.exit:
 385 // CHECK1-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 386 // CHECK1-NEXT:    [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4
 387 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]])
 388 // CHECK1-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
 389 // CHECK1-NEXT:    [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0
 390 // CHECK1-NEXT:    br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
 391 // CHECK1:       .omp.final.then:
 392 // CHECK1-NEXT:    store i32 2, ptr [[I]], align 4
 393 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
 394 // CHECK1:       .omp.final.done:
 395 // CHECK1-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
 396 // CHECK1-NEXT:    [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
 397 // CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN2]], i64 2
 398 // CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
 399 // CHECK1:       arraydestroy.body:
 400 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
 401 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
 402 // CHECK1-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
 403 // CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]]
 404 // CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]]
 405 // CHECK1:       arraydestroy.done3:
 406 // CHECK1-NEXT:    ret void
 407 //
 408 //
 409 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98.omp_outlined.omp_outlined
 410 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR5]] {
 411 // CHECK1-NEXT:  entry:
 412 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 413 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 414 // CHECK1-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
 415 // CHECK1-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
 416 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 417 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 418 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
 419 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
 420 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 421 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 422 // CHECK1-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
 423 // CHECK1-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
 424 // CHECK1-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
 425 // CHECK1-NEXT:    [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
 426 // CHECK1-NEXT:    [[SIVAR:%.*]] = alloca i32, align 4
 427 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
 428 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 429 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 430 // CHECK1-NEXT:    store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
 431 // CHECK1-NEXT:    store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
 432 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
 433 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
 434 // CHECK1-NEXT:    [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
 435 // CHECK1-NEXT:    [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
 436 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
 437 // CHECK1-NEXT:    [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
 438 // CHECK1-NEXT:    store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
 439 // CHECK1-NEXT:    store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4
 440 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 441 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 442 // CHECK1-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
 443 // CHECK1-NEXT:    [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2
 444 // CHECK1-NEXT:    br label [[ARRAYCTOR_LOOP:%.*]]
 445 // CHECK1:       arrayctor.loop:
 446 // CHECK1-NEXT:    [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
 447 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
 448 // CHECK1-NEXT:    [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1
 449 // CHECK1-NEXT:    [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
 450 // CHECK1-NEXT:    br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
 451 // CHECK1:       arrayctor.cont:
 452 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]])
 453 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 454 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
 455 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
 456 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 457 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1
 458 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 459 // CHECK1:       cond.true:
 460 // CHECK1-NEXT:    br label [[COND_END:%.*]]
 461 // CHECK1:       cond.false:
 462 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 463 // CHECK1-NEXT:    br label [[COND_END]]
 464 // CHECK1:       cond.end:
 465 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
 466 // CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
 467 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
 468 // CHECK1-NEXT:    store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4
 469 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 470 // CHECK1:       omp.inner.for.cond:
 471 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9:![0-9]+]]
 472 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP9]]
 473 // CHECK1-NEXT:    [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
 474 // CHECK1-NEXT:    br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
 475 // CHECK1:       omp.inner.for.cond.cleanup:
 476 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
 477 // CHECK1:       omp.inner.for.body:
 478 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]]
 479 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
 480 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
 481 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]]
 482 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP9]]
 483 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]]
 484 // CHECK1-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64
 485 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]]
 486 // CHECK1-NEXT:    store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP9]]
 487 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]]
 488 // CHECK1-NEXT:    [[IDXPROM3:%.*]] = sext i32 [[TMP12]] to i64
 489 // CHECK1-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM3]]
 490 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[VAR]], i64 4, i1 false), !llvm.access.group [[ACC_GRP9]]
 491 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]]
 492 // CHECK1-NEXT:    [[TMP14:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP9]]
 493 // CHECK1-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP14]], [[TMP13]]
 494 // CHECK1-NEXT:    store i32 [[ADD5]], ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP9]]
 495 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 496 // CHECK1:       omp.body.continue:
 497 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 498 // CHECK1:       omp.inner.for.inc:
 499 // CHECK1-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]]
 500 // CHECK1-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP15]], 1
 501 // CHECK1-NEXT:    store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP9]]
 502 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
 503 // CHECK1:       omp.inner.for.end:
 504 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
 505 // CHECK1:       omp.loop.exit:
 506 // CHECK1-NEXT:    [[TMP16:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 507 // CHECK1-NEXT:    [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 4
 508 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP17]])
 509 // CHECK1-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
 510 // CHECK1-NEXT:    [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
 511 // CHECK1-NEXT:    br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
 512 // CHECK1:       .omp.final.then:
 513 // CHECK1-NEXT:    store i32 2, ptr [[I]], align 4
 514 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
 515 // CHECK1:       .omp.final.done:
 516 // CHECK1-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
 517 // CHECK1-NEXT:    [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
 518 // CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN7]], i64 2
 519 // CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
 520 // CHECK1:       arraydestroy.body:
 521 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP20]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
 522 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
 523 // CHECK1-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
 524 // CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN7]]
 525 // CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE8:%.*]], label [[ARRAYDESTROY_BODY]]
 526 // CHECK1:       arraydestroy.done8:
 527 // CHECK1-NEXT:    ret void
 528 //
 529 //
 530 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
 531 // CHECK1-SAME: () #[[ATTR7:[0-9]+]] comdat {
 532 // CHECK1-NEXT:  entry:
 533 // CHECK1-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
 534 // CHECK1-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
 535 // CHECK1-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
 536 // CHECK1-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
 537 // CHECK1-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
 538 // CHECK1-NEXT:    [[VAR:%.*]] = alloca ptr, align 8
 539 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 540 // CHECK1-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 8
 541 // CHECK1-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
 542 // CHECK1-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])
 543 // CHECK1-NEXT:    store i32 0, ptr [[T_VAR]], align 4
 544 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false)
 545 // CHECK1-NEXT:    [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 0
 546 // CHECK1-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef signext 1)
 547 // CHECK1-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYINIT_BEGIN]], i64 1
 548 // CHECK1-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2)
 549 // CHECK1-NEXT:    store ptr [[TEST]], ptr [[VAR]], align 8
 550 // CHECK1-NEXT:    store ptr undef, ptr [[_TMP1]], align 8
 551 // CHECK1-NEXT:    [[TMP0:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
 552 // CHECK1-NEXT:    store i32 2, ptr [[TMP0]], align 4
 553 // CHECK1-NEXT:    [[TMP1:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
 554 // CHECK1-NEXT:    store i32 0, ptr [[TMP1]], align 4
 555 // CHECK1-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
 556 // CHECK1-NEXT:    store ptr null, ptr [[TMP2]], align 8
 557 // CHECK1-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
 558 // CHECK1-NEXT:    store ptr null, ptr [[TMP3]], align 8
 559 // CHECK1-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
 560 // CHECK1-NEXT:    store ptr null, ptr [[TMP4]], align 8
 561 // CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
 562 // CHECK1-NEXT:    store ptr null, ptr [[TMP5]], align 8
 563 // CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
 564 // CHECK1-NEXT:    store ptr null, ptr [[TMP6]], align 8
 565 // CHECK1-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
 566 // CHECK1-NEXT:    store ptr null, ptr [[TMP7]], align 8
 567 // CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
 568 // CHECK1-NEXT:    store i64 2, ptr [[TMP8]], align 8
 569 // CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
 570 // CHECK1-NEXT:    store i64 0, ptr [[TMP9]], align 8
 571 // CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
 572 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4
 573 // CHECK1-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
 574 // CHECK1-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4
 575 // CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
 576 // CHECK1-NEXT:    store i32 0, ptr [[TMP12]], align 4
 577 // CHECK1-NEXT:    [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, ptr [[KERNEL_ARGS]])
 578 // CHECK1-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
 579 // CHECK1-NEXT:    br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
 580 // CHECK1:       omp_offload.failed:
 581 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56() #[[ATTR2]]
 582 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
 583 // CHECK1:       omp_offload.cont:
 584 // CHECK1-NEXT:    store i32 0, ptr [[RETVAL]], align 4
 585 // CHECK1-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
 586 // CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2
 587 // CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
 588 // CHECK1:       arraydestroy.body:
 589 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
 590 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
 591 // CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
 592 // CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
 593 // CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
 594 // CHECK1:       arraydestroy.done2:
 595 // CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
 596 // CHECK1-NEXT:    [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4
 597 // CHECK1-NEXT:    ret i32 [[TMP16]]
 598 //
 599 //
 600 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
 601 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
 602 // CHECK1-NEXT:  entry:
 603 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 604 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 605 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 606 // CHECK1-NEXT:    call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
 607 // CHECK1-NEXT:    ret void
 608 //
 609 //
 610 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
 611 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
 612 // CHECK1-NEXT:  entry:
 613 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 614 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
 615 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 616 // CHECK1-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
 617 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 618 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
 619 // CHECK1-NEXT:    call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
 620 // CHECK1-NEXT:    ret void
 621 //
 622 //
 623 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56
 624 // CHECK1-SAME: () #[[ATTR4]] {
 625 // CHECK1-NEXT:  entry:
 626 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined)
 627 // CHECK1-NEXT:    ret void
 628 //
 629 //
 630 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined
 631 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] {
 632 // CHECK1-NEXT:  entry:
 633 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 634 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 635 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 636 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 637 // CHECK1-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 8
 638 // CHECK1-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
 639 // CHECK1-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
 640 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 641 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 642 // CHECK1-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
 643 // CHECK1-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
 644 // CHECK1-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
 645 // CHECK1-NEXT:    [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
 646 // CHECK1-NEXT:    [[_TMP2:%.*]] = alloca ptr, align 8
 647 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
 648 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 649 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 650 // CHECK1-NEXT:    store ptr undef, ptr [[_TMP1]], align 8
 651 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
 652 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_COMB_UB]], align 4
 653 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 654 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 655 // CHECK1-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
 656 // CHECK1-NEXT:    [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2
 657 // CHECK1-NEXT:    br label [[ARRAYCTOR_LOOP:%.*]]
 658 // CHECK1:       arrayctor.loop:
 659 // CHECK1-NEXT:    [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
 660 // CHECK1-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
 661 // CHECK1-NEXT:    [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i64 1
 662 // CHECK1-NEXT:    [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
 663 // CHECK1-NEXT:    br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
 664 // CHECK1:       arrayctor.cont:
 665 // CHECK1-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]])
 666 // CHECK1-NEXT:    store ptr [[VAR]], ptr [[_TMP2]], align 8
 667 // CHECK1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 668 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
 669 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
 670 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 671 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
 672 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 673 // CHECK1:       cond.true:
 674 // CHECK1-NEXT:    br label [[COND_END:%.*]]
 675 // CHECK1:       cond.false:
 676 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
 677 // CHECK1-NEXT:    br label [[COND_END]]
 678 // CHECK1:       cond.end:
 679 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
 680 // CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
 681 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
 682 // CHECK1-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
 683 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 684 // CHECK1:       omp.inner.for.cond:
 685 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14:![0-9]+]]
 686 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP14]]
 687 // CHECK1-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
 688 // CHECK1-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
 689 // CHECK1:       omp.inner.for.cond.cleanup:
 690 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
 691 // CHECK1:       omp.inner.for.body:
 692 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP14]]
 693 // CHECK1-NEXT:    [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
 694 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP14]]
 695 // CHECK1-NEXT:    [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
 696 // CHECK1-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP14]]
 697 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 698 // CHECK1:       omp.inner.for.inc:
 699 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]
 700 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP14]]
 701 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
 702 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP14]]
 703 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
 704 // CHECK1:       omp.inner.for.end:
 705 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
 706 // CHECK1:       omp.loop.exit:
 707 // CHECK1-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 708 // CHECK1-NEXT:    [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4
 709 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP14]])
 710 // CHECK1-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
 711 // CHECK1-NEXT:    [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0
 712 // CHECK1-NEXT:    br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
 713 // CHECK1:       .omp.final.then:
 714 // CHECK1-NEXT:    store i32 2, ptr [[I]], align 4
 715 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
 716 // CHECK1:       .omp.final.done:
 717 // CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
 718 // CHECK1-NEXT:    [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
 719 // CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN4]], i64 2
 720 // CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
 721 // CHECK1:       arraydestroy.body:
 722 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP17]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
 723 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
 724 // CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
 725 // CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]]
 726 // CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]]
 727 // CHECK1:       arraydestroy.done5:
 728 // CHECK1-NEXT:    ret void
 729 //
 730 //
 731 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined.omp_outlined
 732 // CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR5]] {
 733 // CHECK1-NEXT:  entry:
 734 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
 735 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
 736 // CHECK1-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
 737 // CHECK1-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
 738 // CHECK1-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
 739 // CHECK1-NEXT:    [[TMP:%.*]] = alloca i32, align 4
 740 // CHECK1-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 8
 741 // CHECK1-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
 742 // CHECK1-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
 743 // CHECK1-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
 744 // CHECK1-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
 745 // CHECK1-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
 746 // CHECK1-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
 747 // CHECK1-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
 748 // CHECK1-NEXT:    [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
 749 // CHECK1-NEXT:    [[_TMP3:%.*]] = alloca ptr, align 8
 750 // CHECK1-NEXT:    [[I:%.*]] = alloca i32, align 4
 751 // CHECK1-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
 752 // CHECK1-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
 753 // CHECK1-NEXT:    store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
 754 // CHECK1-NEXT:    store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
 755 // CHECK1-NEXT:    store ptr undef, ptr [[_TMP1]], align 8
 756 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
 757 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
 758 // CHECK1-NEXT:    [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
 759 // CHECK1-NEXT:    [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
 760 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
 761 // CHECK1-NEXT:    [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32
 762 // CHECK1-NEXT:    store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
 763 // CHECK1-NEXT:    store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4
 764 // CHECK1-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
 765 // CHECK1-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
 766 // CHECK1-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
 767 // CHECK1-NEXT:    [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2
 768 // CHECK1-NEXT:    br label [[ARRAYCTOR_LOOP:%.*]]
 769 // CHECK1:       arrayctor.loop:
 770 // CHECK1-NEXT:    [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
 771 // CHECK1-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
 772 // CHECK1-NEXT:    [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i64 1
 773 // CHECK1-NEXT:    [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
 774 // CHECK1-NEXT:    br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
 775 // CHECK1:       arrayctor.cont:
 776 // CHECK1-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]])
 777 // CHECK1-NEXT:    store ptr [[VAR]], ptr [[_TMP3]], align 8
 778 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 779 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
 780 // CHECK1-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
 781 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 782 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1
 783 // CHECK1-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
 784 // CHECK1:       cond.true:
 785 // CHECK1-NEXT:    br label [[COND_END:%.*]]
 786 // CHECK1:       cond.false:
 787 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
 788 // CHECK1-NEXT:    br label [[COND_END]]
 789 // CHECK1:       cond.end:
 790 // CHECK1-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
 791 // CHECK1-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
 792 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
 793 // CHECK1-NEXT:    store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4
 794 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
 795 // CHECK1:       omp.inner.for.cond:
 796 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17:![0-9]+]]
 797 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP17]]
 798 // CHECK1-NEXT:    [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
 799 // CHECK1-NEXT:    br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
 800 // CHECK1:       omp.inner.for.cond.cleanup:
 801 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
 802 // CHECK1:       omp.inner.for.body:
 803 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]]
 804 // CHECK1-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
 805 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
 806 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP17]]
 807 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP17]]
 808 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP17]]
 809 // CHECK1-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64
 810 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]]
 811 // CHECK1-NEXT:    store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP17]]
 812 // CHECK1-NEXT:    [[TMP12:%.*]] = load ptr, ptr [[_TMP3]], align 8, !llvm.access.group [[ACC_GRP17]]
 813 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP17]]
 814 // CHECK1-NEXT:    [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64
 815 // CHECK1-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM5]]
 816 // CHECK1-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX6]], ptr align 4 [[TMP12]], i64 4, i1 false), !llvm.access.group [[ACC_GRP17]]
 817 // CHECK1-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
 818 // CHECK1:       omp.body.continue:
 819 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
 820 // CHECK1:       omp.inner.for.inc:
 821 // CHECK1-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]]
 822 // CHECK1-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP14]], 1
 823 // CHECK1-NEXT:    store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]]
 824 // CHECK1-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]
 825 // CHECK1:       omp.inner.for.end:
 826 // CHECK1-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
 827 // CHECK1:       omp.loop.exit:
 828 // CHECK1-NEXT:    [[TMP15:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
 829 // CHECK1-NEXT:    [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 4
 830 // CHECK1-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP16]])
 831 // CHECK1-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
 832 // CHECK1-NEXT:    [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
 833 // CHECK1-NEXT:    br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
 834 // CHECK1:       .omp.final.then:
 835 // CHECK1-NEXT:    store i32 2, ptr [[I]], align 4
 836 // CHECK1-NEXT:    br label [[DOTOMP_FINAL_DONE]]
 837 // CHECK1:       .omp.final.done:
 838 // CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
 839 // CHECK1-NEXT:    [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
 840 // CHECK1-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN8]], i64 2
 841 // CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
 842 // CHECK1:       arraydestroy.body:
 843 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP19]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
 844 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
 845 // CHECK1-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
 846 // CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN8]]
 847 // CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE9:%.*]], label [[ARRAYDESTROY_BODY]]
 848 // CHECK1:       arraydestroy.done9:
 849 // CHECK1-NEXT:    ret void
 850 //
 851 //
 852 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
 853 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
 854 // CHECK1-NEXT:  entry:
 855 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 856 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 857 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 858 // CHECK1-NEXT:    call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
 859 // CHECK1-NEXT:    ret void
 860 //
 861 //
 862 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
 863 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
 864 // CHECK1-NEXT:  entry:
 865 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 866 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 867 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 868 // CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
 869 // CHECK1-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
 870 // CHECK1-NEXT:    store i32 [[TMP0]], ptr [[F]], align 4
 871 // CHECK1-NEXT:    ret void
 872 //
 873 //
 874 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
 875 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
 876 // CHECK1-NEXT:  entry:
 877 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 878 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
 879 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 880 // CHECK1-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
 881 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 882 // CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
 883 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
 884 // CHECK1-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
 885 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
 886 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[F]], align 4
 887 // CHECK1-NEXT:    ret void
 888 //
 889 //
 890 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
 891 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
 892 // CHECK1-NEXT:  entry:
 893 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 894 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 895 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 896 // CHECK1-NEXT:    ret void
 897 //
 898 //
 899 // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_simd_private_codegen.cpp
 900 // CHECK1-SAME: () #[[ATTR0]] {
 901 // CHECK1-NEXT:  entry:
 902 // CHECK1-NEXT:    call void @__cxx_global_var_init()
 903 // CHECK1-NEXT:    call void @__cxx_global_var_init.1()
 904 // CHECK1-NEXT:    call void @__cxx_global_var_init.2()
 905 // CHECK1-NEXT:    ret void
 906 //
 907 //
 908 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
 909 // CHECK1-SAME: () #[[ATTR0]] {
 910 // CHECK1-NEXT:  entry:
 911 // CHECK1-NEXT:    call void @__tgt_register_requires(i64 1)
 912 // CHECK1-NEXT:    ret void
 913 //
 914 //
 915 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init
 916 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] {
 917 // CHECK3-NEXT:  entry:
 918 // CHECK3-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
 919 // CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
 920 // CHECK3-NEXT:    ret void
 921 //
 922 //
 923 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
 924 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
 925 // CHECK3-NEXT:  entry:
 926 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
 927 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
 928 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
 929 // CHECK3-NEXT:    call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
 930 // CHECK3-NEXT:    ret void
 931 //
 932 //
 933 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
 934 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
 935 // CHECK3-NEXT:  entry:
 936 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
 937 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
 938 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
 939 // CHECK3-NEXT:    call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
 940 // CHECK3-NEXT:    ret void
 941 //
 942 //
 943 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
 944 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
 945 // CHECK3-NEXT:  entry:
 946 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
 947 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
 948 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
 949 // CHECK3-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
 950 // CHECK3-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
 951 // CHECK3-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
 952 // CHECK3-NEXT:    store float [[CONV]], ptr [[F]], align 4
 953 // CHECK3-NEXT:    ret void
 954 //
 955 //
 956 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
 957 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
 958 // CHECK3-NEXT:  entry:
 959 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
 960 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
 961 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
 962 // CHECK3-NEXT:    ret void
 963 //
 964 //
 965 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
 966 // CHECK3-SAME: () #[[ATTR0]] {
 967 // CHECK3-NEXT:  entry:
 968 // CHECK3-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
 969 // CHECK3-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 1), float noundef 2.000000e+00)
 970 // CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
 971 // CHECK3-NEXT:    ret void
 972 //
 973 //
 974 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
 975 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
 976 // CHECK3-NEXT:  entry:
 977 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
 978 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
 979 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
 980 // CHECK3-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
 981 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
 982 // CHECK3-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
 983 // CHECK3-NEXT:    call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
 984 // CHECK3-NEXT:    ret void
 985 //
 986 //
 987 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
 988 // CHECK3-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {
 989 // CHECK3-NEXT:  entry:
 990 // CHECK3-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 4
 991 // CHECK3-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 4
 992 // CHECK3-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
 993 // CHECK3:       arraydestroy.body:
 994 // CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
 995 // CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
 996 // CHECK3-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
 997 // CHECK3-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr
 998 // CHECK3-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
 999 // CHECK3:       arraydestroy.done1:
1000 // CHECK3-NEXT:    ret void
1001 //
1002 //
1003 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
1004 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1005 // CHECK3-NEXT:  entry:
1006 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1007 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
1008 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1009 // CHECK3-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
1010 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1011 // CHECK3-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
1012 // CHECK3-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
1013 // CHECK3-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
1014 // CHECK3-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
1015 // CHECK3-NEXT:    [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
1016 // CHECK3-NEXT:    store float [[ADD]], ptr [[F]], align 4
1017 // CHECK3-NEXT:    ret void
1018 //
1019 //
1020 // CHECK3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
1021 // CHECK3-SAME: () #[[ATTR0]] {
1022 // CHECK3-NEXT:  entry:
1023 // CHECK3-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)
1024 // CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]
1025 // CHECK3-NEXT:    ret void
1026 //
1027 //
1028 // CHECK3-LABEL: define {{[^@]+}}@main
1029 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] {
1030 // CHECK3-NEXT:  entry:
1031 // CHECK3-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
1032 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1033 // CHECK3-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1034 // CHECK3-NEXT:    store i32 0, ptr [[RETVAL]], align 4
1035 // CHECK3-NEXT:    [[TMP0:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
1036 // CHECK3-NEXT:    store i32 2, ptr [[TMP0]], align 4
1037 // CHECK3-NEXT:    [[TMP1:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
1038 // CHECK3-NEXT:    store i32 0, ptr [[TMP1]], align 4
1039 // CHECK3-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
1040 // CHECK3-NEXT:    store ptr null, ptr [[TMP2]], align 4
1041 // CHECK3-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
1042 // CHECK3-NEXT:    store ptr null, ptr [[TMP3]], align 4
1043 // CHECK3-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
1044 // CHECK3-NEXT:    store ptr null, ptr [[TMP4]], align 4
1045 // CHECK3-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
1046 // CHECK3-NEXT:    store ptr null, ptr [[TMP5]], align 4
1047 // CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
1048 // CHECK3-NEXT:    store ptr null, ptr [[TMP6]], align 4
1049 // CHECK3-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
1050 // CHECK3-NEXT:    store ptr null, ptr [[TMP7]], align 4
1051 // CHECK3-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
1052 // CHECK3-NEXT:    store i64 2, ptr [[TMP8]], align 8
1053 // CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
1054 // CHECK3-NEXT:    store i64 0, ptr [[TMP9]], align 8
1055 // CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
1056 // CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4
1057 // CHECK3-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
1058 // CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4
1059 // CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
1060 // CHECK3-NEXT:    store i32 0, ptr [[TMP12]], align 4
1061 // CHECK3-NEXT:    [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3:[0-9]+]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98.region_id, ptr [[KERNEL_ARGS]])
1062 // CHECK3-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
1063 // CHECK3-NEXT:    br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1064 // CHECK3:       omp_offload.failed:
1065 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98() #[[ATTR2]]
1066 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]
1067 // CHECK3:       omp_offload.cont:
1068 // CHECK3-NEXT:    [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()
1069 // CHECK3-NEXT:    ret i32 [[CALL]]
1070 //
1071 //
1072 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98
1073 // CHECK3-SAME: () #[[ATTR4:[0-9]+]] {
1074 // CHECK3-NEXT:  entry:
1075 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98.omp_outlined)
1076 // CHECK3-NEXT:    ret void
1077 //
1078 //
1079 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98.omp_outlined
1080 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5:[0-9]+]] {
1081 // CHECK3-NEXT:  entry:
1082 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
1083 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
1084 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1085 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1086 // CHECK3-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
1087 // CHECK3-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
1088 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1089 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1090 // CHECK3-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
1091 // CHECK3-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
1092 // CHECK3-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
1093 // CHECK3-NEXT:    [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
1094 // CHECK3-NEXT:    [[SIVAR:%.*]] = alloca i32, align 4
1095 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
1096 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
1097 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
1098 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
1099 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_COMB_UB]], align 4
1100 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1101 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1102 // CHECK3-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
1103 // CHECK3-NEXT:    [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2
1104 // CHECK3-NEXT:    br label [[ARRAYCTOR_LOOP:%.*]]
1105 // CHECK3:       arrayctor.loop:
1106 // CHECK3-NEXT:    [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1107 // CHECK3-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1108 // CHECK3-NEXT:    [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i32 1
1109 // CHECK3-NEXT:    [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1110 // CHECK3-NEXT:    br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1111 // CHECK3:       arrayctor.cont:
1112 // CHECK3-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]])
1113 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
1114 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
1115 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
1116 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1117 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
1118 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1119 // CHECK3:       cond.true:
1120 // CHECK3-NEXT:    br label [[COND_END:%.*]]
1121 // CHECK3:       cond.false:
1122 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1123 // CHECK3-NEXT:    br label [[COND_END]]
1124 // CHECK3:       cond.end:
1125 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
1126 // CHECK3-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
1127 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
1128 // CHECK3-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
1129 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1130 // CHECK3:       omp.inner.for.cond:
1131 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]]
1132 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP6]]
1133 // CHECK3-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
1134 // CHECK3-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1135 // CHECK3:       omp.inner.for.cond.cleanup:
1136 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
1137 // CHECK3:       omp.inner.for.body:
1138 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP6]]
1139 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP6]]
1140 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98.omp_outlined.omp_outlined, i32 [[TMP7]], i32 [[TMP8]]), !llvm.access.group [[ACC_GRP6]]
1141 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1142 // CHECK3:       omp.inner.for.inc:
1143 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
1144 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP6]]
1145 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]]
1146 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
1147 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
1148 // CHECK3:       omp.inner.for.end:
1149 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1150 // CHECK3:       omp.loop.exit:
1151 // CHECK3-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
1152 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4
1153 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP12]])
1154 // CHECK3-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
1155 // CHECK3-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
1156 // CHECK3-NEXT:    br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1157 // CHECK3:       .omp.final.then:
1158 // CHECK3-NEXT:    store i32 2, ptr [[I]], align 4
1159 // CHECK3-NEXT:    br label [[DOTOMP_FINAL_DONE]]
1160 // CHECK3:       .omp.final.done:
1161 // CHECK3-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
1162 // CHECK3-NEXT:    [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
1163 // CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN2]], i32 2
1164 // CHECK3-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1165 // CHECK3:       arraydestroy.body:
1166 // CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1167 // CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1168 // CHECK3-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1169 // CHECK3-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN2]]
1170 // CHECK3-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]]
1171 // CHECK3:       arraydestroy.done3:
1172 // CHECK3-NEXT:    ret void
1173 //
1174 //
1175 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l98.omp_outlined.omp_outlined
1176 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR5]] {
1177 // CHECK3-NEXT:  entry:
1178 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
1179 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
1180 // CHECK3-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
1181 // CHECK3-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
1182 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1183 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1184 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1185 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1186 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1187 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1188 // CHECK3-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
1189 // CHECK3-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
1190 // CHECK3-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
1191 // CHECK3-NEXT:    [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
1192 // CHECK3-NEXT:    [[SIVAR:%.*]] = alloca i32, align 4
1193 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
1194 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
1195 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
1196 // CHECK3-NEXT:    store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4
1197 // CHECK3-NEXT:    store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
1198 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
1199 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
1200 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4
1201 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
1202 // CHECK3-NEXT:    store i32 [[TMP0]], ptr [[DOTOMP_LB]], align 4
1203 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[DOTOMP_UB]], align 4
1204 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1205 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1206 // CHECK3-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
1207 // CHECK3-NEXT:    [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2
1208 // CHECK3-NEXT:    br label [[ARRAYCTOR_LOOP:%.*]]
1209 // CHECK3:       arrayctor.loop:
1210 // CHECK3-NEXT:    [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1211 // CHECK3-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1212 // CHECK3-NEXT:    [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i32 1
1213 // CHECK3-NEXT:    [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1214 // CHECK3-NEXT:    br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1215 // CHECK3:       arrayctor.cont:
1216 // CHECK3-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]])
1217 // CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
1218 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
1219 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
1220 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1221 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1
1222 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1223 // CHECK3:       cond.true:
1224 // CHECK3-NEXT:    br label [[COND_END:%.*]]
1225 // CHECK3:       cond.false:
1226 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1227 // CHECK3-NEXT:    br label [[COND_END]]
1228 // CHECK3:       cond.end:
1229 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
1230 // CHECK3-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
1231 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1232 // CHECK3-NEXT:    store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4
1233 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1234 // CHECK3:       omp.inner.for.cond:
1235 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10:![0-9]+]]
1236 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP10]]
1237 // CHECK3-NEXT:    [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
1238 // CHECK3-NEXT:    br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1239 // CHECK3:       omp.inner.for.cond.cleanup:
1240 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
1241 // CHECK3:       omp.inner.for.body:
1242 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]]
1243 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
1244 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1245 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]]
1246 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP10]]
1247 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]]
1248 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP11]]
1249 // CHECK3-NEXT:    store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP10]]
1250 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]]
1251 // CHECK3-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP12]]
1252 // CHECK3-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[VAR]], i32 4, i1 false), !llvm.access.group [[ACC_GRP10]]
1253 // CHECK3-NEXT:    [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]]
1254 // CHECK3-NEXT:    [[TMP14:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP10]]
1255 // CHECK3-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP14]], [[TMP13]]
1256 // CHECK3-NEXT:    store i32 [[ADD3]], ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP10]]
1257 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1258 // CHECK3:       omp.body.continue:
1259 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1260 // CHECK3:       omp.inner.for.inc:
1261 // CHECK3-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]]
1262 // CHECK3-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP15]], 1
1263 // CHECK3-NEXT:    store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]]
1264 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]]
1265 // CHECK3:       omp.inner.for.end:
1266 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1267 // CHECK3:       omp.loop.exit:
1268 // CHECK3-NEXT:    [[TMP16:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
1269 // CHECK3-NEXT:    [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 4
1270 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP17]])
1271 // CHECK3-NEXT:    [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
1272 // CHECK3-NEXT:    [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
1273 // CHECK3-NEXT:    br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1274 // CHECK3:       .omp.final.then:
1275 // CHECK3-NEXT:    store i32 2, ptr [[I]], align 4
1276 // CHECK3-NEXT:    br label [[DOTOMP_FINAL_DONE]]
1277 // CHECK3:       .omp.final.done:
1278 // CHECK3-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
1279 // CHECK3-NEXT:    [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
1280 // CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN5]], i32 2
1281 // CHECK3-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1282 // CHECK3:       arraydestroy.body:
1283 // CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP20]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1284 // CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1285 // CHECK3-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1286 // CHECK3-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]]
1287 // CHECK3-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]]
1288 // CHECK3:       arraydestroy.done6:
1289 // CHECK3-NEXT:    ret void
1290 //
1291 //
1292 // CHECK3-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
1293 // CHECK3-SAME: () #[[ATTR7:[0-9]+]] comdat {
1294 // CHECK3-NEXT:  entry:
1295 // CHECK3-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
1296 // CHECK3-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1297 // CHECK3-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
1298 // CHECK3-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
1299 // CHECK3-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
1300 // CHECK3-NEXT:    [[VAR:%.*]] = alloca ptr, align 4
1301 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1302 // CHECK3-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 4
1303 // CHECK3-NEXT:    [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
1304 // CHECK3-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])
1305 // CHECK3-NEXT:    store i32 0, ptr [[T_VAR]], align 4
1306 // CHECK3-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false)
1307 // CHECK3-NEXT:    [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
1308 // CHECK3-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef 1)
1309 // CHECK3-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYINIT_BEGIN]], i32 1
1310 // CHECK3-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)
1311 // CHECK3-NEXT:    store ptr [[TEST]], ptr [[VAR]], align 4
1312 // CHECK3-NEXT:    store ptr undef, ptr [[_TMP1]], align 4
1313 // CHECK3-NEXT:    [[TMP0:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
1314 // CHECK3-NEXT:    store i32 2, ptr [[TMP0]], align 4
1315 // CHECK3-NEXT:    [[TMP1:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
1316 // CHECK3-NEXT:    store i32 0, ptr [[TMP1]], align 4
1317 // CHECK3-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
1318 // CHECK3-NEXT:    store ptr null, ptr [[TMP2]], align 4
1319 // CHECK3-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
1320 // CHECK3-NEXT:    store ptr null, ptr [[TMP3]], align 4
1321 // CHECK3-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
1322 // CHECK3-NEXT:    store ptr null, ptr [[TMP4]], align 4
1323 // CHECK3-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
1324 // CHECK3-NEXT:    store ptr null, ptr [[TMP5]], align 4
1325 // CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
1326 // CHECK3-NEXT:    store ptr null, ptr [[TMP6]], align 4
1327 // CHECK3-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
1328 // CHECK3-NEXT:    store ptr null, ptr [[TMP7]], align 4
1329 // CHECK3-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
1330 // CHECK3-NEXT:    store i64 2, ptr [[TMP8]], align 8
1331 // CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
1332 // CHECK3-NEXT:    store i64 0, ptr [[TMP9]], align 8
1333 // CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
1334 // CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP10]], align 4
1335 // CHECK3-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
1336 // CHECK3-NEXT:    store [3 x i32] zeroinitializer, ptr [[TMP11]], align 4
1337 // CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
1338 // CHECK3-NEXT:    store i32 0, ptr [[TMP12]], align 4
1339 // CHECK3-NEXT:    [[TMP13:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB3]], i64 -1, i32 0, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.region_id, ptr [[KERNEL_ARGS]])
1340 // CHECK3-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
1341 // CHECK3-NEXT:    br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1342 // CHECK3:       omp_offload.failed:
1343 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56() #[[ATTR2]]
1344 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]
1345 // CHECK3:       omp_offload.cont:
1346 // CHECK3-NEXT:    store i32 0, ptr [[RETVAL]], align 4
1347 // CHECK3-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
1348 // CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2
1349 // CHECK3-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1350 // CHECK3:       arraydestroy.body:
1351 // CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1352 // CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1353 // CHECK3-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1354 // CHECK3-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
1355 // CHECK3-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]]
1356 // CHECK3:       arraydestroy.done2:
1357 // CHECK3-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
1358 // CHECK3-NEXT:    [[TMP16:%.*]] = load i32, ptr [[RETVAL]], align 4
1359 // CHECK3-NEXT:    ret i32 [[TMP16]]
1360 //
1361 //
1362 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
1363 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1364 // CHECK3-NEXT:  entry:
1365 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1366 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1367 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1368 // CHECK3-NEXT:    call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
1369 // CHECK3-NEXT:    ret void
1370 //
1371 //
1372 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
1373 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1374 // CHECK3-NEXT:  entry:
1375 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1376 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
1377 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1378 // CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
1379 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1380 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
1381 // CHECK3-NEXT:    call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])
1382 // CHECK3-NEXT:    ret void
1383 //
1384 //
1385 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56
1386 // CHECK3-SAME: () #[[ATTR4]] {
1387 // CHECK3-NEXT:  entry:
1388 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined)
1389 // CHECK3-NEXT:    ret void
1390 //
1391 //
1392 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined
1393 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] {
1394 // CHECK3-NEXT:  entry:
1395 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
1396 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
1397 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1398 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1399 // CHECK3-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 4
1400 // CHECK3-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
1401 // CHECK3-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
1402 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1403 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1404 // CHECK3-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
1405 // CHECK3-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
1406 // CHECK3-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
1407 // CHECK3-NEXT:    [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1408 // CHECK3-NEXT:    [[_TMP2:%.*]] = alloca ptr, align 4
1409 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
1410 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
1411 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
1412 // CHECK3-NEXT:    store ptr undef, ptr [[_TMP1]], align 4
1413 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
1414 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_COMB_UB]], align 4
1415 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1416 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1417 // CHECK3-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
1418 // CHECK3-NEXT:    [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2
1419 // CHECK3-NEXT:    br label [[ARRAYCTOR_LOOP:%.*]]
1420 // CHECK3:       arrayctor.loop:
1421 // CHECK3-NEXT:    [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1422 // CHECK3-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1423 // CHECK3-NEXT:    [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i32 1
1424 // CHECK3-NEXT:    [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1425 // CHECK3-NEXT:    br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1426 // CHECK3:       arrayctor.cont:
1427 // CHECK3-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]])
1428 // CHECK3-NEXT:    store ptr [[VAR]], ptr [[_TMP2]], align 4
1429 // CHECK3-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
1430 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
1431 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
1432 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1433 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
1434 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1435 // CHECK3:       cond.true:
1436 // CHECK3-NEXT:    br label [[COND_END:%.*]]
1437 // CHECK3:       cond.false:
1438 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
1439 // CHECK3-NEXT:    br label [[COND_END]]
1440 // CHECK3:       cond.end:
1441 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
1442 // CHECK3-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
1443 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
1444 // CHECK3-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
1445 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1446 // CHECK3:       omp.inner.for.cond:
1447 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15:![0-9]+]]
1448 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP15]]
1449 // CHECK3-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
1450 // CHECK3-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1451 // CHECK3:       omp.inner.for.cond.cleanup:
1452 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
1453 // CHECK3:       omp.inner.for.body:
1454 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP15]]
1455 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP15]]
1456 // CHECK3-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined.omp_outlined, i32 [[TMP7]], i32 [[TMP8]]), !llvm.access.group [[ACC_GRP15]]
1457 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1458 // CHECK3:       omp.inner.for.inc:
1459 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]]
1460 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP15]]
1461 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP9]], [[TMP10]]
1462 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP15]]
1463 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
1464 // CHECK3:       omp.inner.for.end:
1465 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1466 // CHECK3:       omp.loop.exit:
1467 // CHECK3-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
1468 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4
1469 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP12]])
1470 // CHECK3-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
1471 // CHECK3-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
1472 // CHECK3-NEXT:    br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1473 // CHECK3:       .omp.final.then:
1474 // CHECK3-NEXT:    store i32 2, ptr [[I]], align 4
1475 // CHECK3-NEXT:    br label [[DOTOMP_FINAL_DONE]]
1476 // CHECK3:       .omp.final.done:
1477 // CHECK3-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
1478 // CHECK3-NEXT:    [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
1479 // CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN4]], i32 2
1480 // CHECK3-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1481 // CHECK3:       arraydestroy.body:
1482 // CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP15]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1483 // CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1484 // CHECK3-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1485 // CHECK3-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]]
1486 // CHECK3-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]]
1487 // CHECK3:       arraydestroy.done5:
1488 // CHECK3-NEXT:    ret void
1489 //
1490 //
1491 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l56.omp_outlined.omp_outlined
1492 // CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR5]] {
1493 // CHECK3-NEXT:  entry:
1494 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
1495 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
1496 // CHECK3-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
1497 // CHECK3-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
1498 // CHECK3-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1499 // CHECK3-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1500 // CHECK3-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 4
1501 // CHECK3-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1502 // CHECK3-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1503 // CHECK3-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
1504 // CHECK3-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
1505 // CHECK3-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
1506 // CHECK3-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
1507 // CHECK3-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
1508 // CHECK3-NEXT:    [[VAR:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1509 // CHECK3-NEXT:    [[_TMP2:%.*]] = alloca ptr, align 4
1510 // CHECK3-NEXT:    [[I:%.*]] = alloca i32, align 4
1511 // CHECK3-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
1512 // CHECK3-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
1513 // CHECK3-NEXT:    store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4
1514 // CHECK3-NEXT:    store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
1515 // CHECK3-NEXT:    store ptr undef, ptr [[_TMP1]], align 4
1516 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
1517 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
1518 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4
1519 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
1520 // CHECK3-NEXT:    store i32 [[TMP0]], ptr [[DOTOMP_LB]], align 4
1521 // CHECK3-NEXT:    store i32 [[TMP1]], ptr [[DOTOMP_UB]], align 4
1522 // CHECK3-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
1523 // CHECK3-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
1524 // CHECK3-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
1525 // CHECK3-NEXT:    [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2
1526 // CHECK3-NEXT:    br label [[ARRAYCTOR_LOOP:%.*]]
1527 // CHECK3:       arrayctor.loop:
1528 // CHECK3-NEXT:    [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1529 // CHECK3-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1530 // CHECK3-NEXT:    [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i32 1
1531 // CHECK3-NEXT:    [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1532 // CHECK3-NEXT:    br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1533 // CHECK3:       arrayctor.cont:
1534 // CHECK3-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]])
1535 // CHECK3-NEXT:    store ptr [[VAR]], ptr [[_TMP2]], align 4
1536 // CHECK3-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
1537 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
1538 // CHECK3-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
1539 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1540 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1
1541 // CHECK3-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
1542 // CHECK3:       cond.true:
1543 // CHECK3-NEXT:    br label [[COND_END:%.*]]
1544 // CHECK3:       cond.false:
1545 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
1546 // CHECK3-NEXT:    br label [[COND_END]]
1547 // CHECK3:       cond.end:
1548 // CHECK3-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
1549 // CHECK3-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
1550 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1551 // CHECK3-NEXT:    store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4
1552 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1553 // CHECK3:       omp.inner.for.cond:
1554 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18:![0-9]+]]
1555 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP18]]
1556 // CHECK3-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
1557 // CHECK3-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1558 // CHECK3:       omp.inner.for.cond.cleanup:
1559 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
1560 // CHECK3:       omp.inner.for.body:
1561 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]]
1562 // CHECK3-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
1563 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1564 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]]
1565 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP18]]
1566 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]]
1567 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP11]]
1568 // CHECK3-NEXT:    store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP18]]
1569 // CHECK3-NEXT:    [[TMP12:%.*]] = load ptr, ptr [[_TMP2]], align 4, !llvm.access.group [[ACC_GRP18]]
1570 // CHECK3-NEXT:    [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]]
1571 // CHECK3-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP13]]
1572 // CHECK3-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP12]], i32 4, i1 false), !llvm.access.group [[ACC_GRP18]]
1573 // CHECK3-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1574 // CHECK3:       omp.body.continue:
1575 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1576 // CHECK3:       omp.inner.for.inc:
1577 // CHECK3-NEXT:    [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]]
1578 // CHECK3-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP14]], 1
1579 // CHECK3-NEXT:    store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP18]]
1580 // CHECK3-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]]
1581 // CHECK3:       omp.inner.for.end:
1582 // CHECK3-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
1583 // CHECK3:       omp.loop.exit:
1584 // CHECK3-NEXT:    [[TMP15:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
1585 // CHECK3-NEXT:    [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 4
1586 // CHECK3-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP16]])
1587 // CHECK3-NEXT:    [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
1588 // CHECK3-NEXT:    [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0
1589 // CHECK3-NEXT:    br i1 [[TMP18]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
1590 // CHECK3:       .omp.final.then:
1591 // CHECK3-NEXT:    store i32 2, ptr [[I]], align 4
1592 // CHECK3-NEXT:    br label [[DOTOMP_FINAL_DONE]]
1593 // CHECK3:       .omp.final.done:
1594 // CHECK3-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
1595 // CHECK3-NEXT:    [[ARRAY_BEGIN6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
1596 // CHECK3-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN6]], i32 2
1597 // CHECK3-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1598 // CHECK3:       arraydestroy.body:
1599 // CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP19]], [[DOTOMP_FINAL_DONE]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1600 // CHECK3-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
1601 // CHECK3-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1602 // CHECK3-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN6]]
1603 // CHECK3-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE7:%.*]], label [[ARRAYDESTROY_BODY]]
1604 // CHECK3:       arraydestroy.done7:
1605 // CHECK3-NEXT:    ret void
1606 //
1607 //
1608 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
1609 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1610 // CHECK3-NEXT:  entry:
1611 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1612 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1613 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1614 // CHECK3-NEXT:    call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
1615 // CHECK3-NEXT:    ret void
1616 //
1617 //
1618 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
1619 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1620 // CHECK3-NEXT:  entry:
1621 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1622 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1623 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1624 // CHECK3-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
1625 // CHECK3-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
1626 // CHECK3-NEXT:    store i32 [[TMP0]], ptr [[F]], align 4
1627 // CHECK3-NEXT:    ret void
1628 //
1629 //
1630 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
1631 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1632 // CHECK3-NEXT:  entry:
1633 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1634 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
1635 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1636 // CHECK3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
1637 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1638 // CHECK3-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
1639 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
1640 // CHECK3-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
1641 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
1642 // CHECK3-NEXT:    store i32 [[ADD]], ptr [[F]], align 4
1643 // CHECK3-NEXT:    ret void
1644 //
1645 //
1646 // CHECK3-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
1647 // CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1648 // CHECK3-NEXT:  entry:
1649 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
1650 // CHECK3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
1651 // CHECK3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
1652 // CHECK3-NEXT:    ret void
1653 //
1654 //
1655 // CHECK3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_simd_private_codegen.cpp
1656 // CHECK3-SAME: () #[[ATTR0]] {
1657 // CHECK3-NEXT:  entry:
1658 // CHECK3-NEXT:    call void @__cxx_global_var_init()
1659 // CHECK3-NEXT:    call void @__cxx_global_var_init.1()
1660 // CHECK3-NEXT:    call void @__cxx_global_var_init.2()
1661 // CHECK3-NEXT:    ret void
1662 //
1663 //
1664 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
1665 // CHECK3-SAME: () #[[ATTR0]] {
1666 // CHECK3-NEXT:  entry:
1667 // CHECK3-NEXT:    call void @__tgt_register_requires(i64 1)
1668 // CHECK3-NEXT:    ret void
1669 //
1670 //
1671 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init
1672 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] {
1673 // CHECK5-NEXT:  entry:
1674 // CHECK5-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
1675 // CHECK5-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
1676 // CHECK5-NEXT:    ret void
1677 //
1678 //
1679 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
1680 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
1681 // CHECK5-NEXT:  entry:
1682 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1683 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1684 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1685 // CHECK5-NEXT:    call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
1686 // CHECK5-NEXT:    ret void
1687 //
1688 //
1689 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
1690 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1691 // CHECK5-NEXT:  entry:
1692 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1693 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1694 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1695 // CHECK5-NEXT:    call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
1696 // CHECK5-NEXT:    ret void
1697 //
1698 //
1699 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
1700 // CHECK5-SAME: () #[[ATTR0]] {
1701 // CHECK5-NEXT:  entry:
1702 // CHECK5-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
1703 // CHECK5-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)
1704 // CHECK5-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
1705 // CHECK5-NEXT:    ret void
1706 //
1707 //
1708 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
1709 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1710 // CHECK5-NEXT:  entry:
1711 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1712 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
1713 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1714 // CHECK5-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
1715 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1716 // CHECK5-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
1717 // CHECK5-NEXT:    call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
1718 // CHECK5-NEXT:    ret void
1719 //
1720 //
1721 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
1722 // CHECK5-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {
1723 // CHECK5-NEXT:  entry:
1724 // CHECK5-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
1725 // CHECK5-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
1726 // CHECK5-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1727 // CHECK5:       arraydestroy.body:
1728 // CHECK5-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1729 // CHECK5-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1730 // CHECK5-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1731 // CHECK5-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr
1732 // CHECK5-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
1733 // CHECK5:       arraydestroy.done1:
1734 // CHECK5-NEXT:    ret void
1735 //
1736 //
1737 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
1738 // CHECK5-SAME: () #[[ATTR0]] {
1739 // CHECK5-NEXT:  entry:
1740 // CHECK5-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)
1741 // CHECK5-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]
1742 // CHECK5-NEXT:    ret void
1743 //
1744 //
1745 // CHECK5-LABEL: define {{[^@]+}}@main
1746 // CHECK5-SAME: () #[[ATTR3:[0-9]+]] {
1747 // CHECK5-NEXT:  entry:
1748 // CHECK5-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
1749 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1750 // CHECK5-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1751 // CHECK5-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1752 // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1753 // CHECK5-NEXT:    [[I:%.*]] = alloca i32, align 4
1754 // CHECK5-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
1755 // CHECK5-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
1756 // CHECK5-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
1757 // CHECK5-NEXT:    [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
1758 // CHECK5-NEXT:    [[SIVAR:%.*]] = alloca i32, align 4
1759 // CHECK5-NEXT:    store i32 0, ptr [[RETVAL]], align 4
1760 // CHECK5-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
1761 // CHECK5-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
1762 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1763 // CHECK5-NEXT:    store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4
1764 // CHECK5-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
1765 // CHECK5-NEXT:    [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i64 2
1766 // CHECK5-NEXT:    br label [[ARRAYCTOR_LOOP:%.*]]
1767 // CHECK5:       arrayctor.loop:
1768 // CHECK5-NEXT:    [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1769 // CHECK5-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1770 // CHECK5-NEXT:    [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i64 1
1771 // CHECK5-NEXT:    [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1772 // CHECK5-NEXT:    br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1773 // CHECK5:       arrayctor.cont:
1774 // CHECK5-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]])
1775 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1776 // CHECK5:       omp.inner.for.cond:
1777 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]]
1778 // CHECK5-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP2]]
1779 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
1780 // CHECK5-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1781 // CHECK5:       omp.inner.for.cond.cleanup:
1782 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
1783 // CHECK5:       omp.inner.for.body:
1784 // CHECK5-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
1785 // CHECK5-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
1786 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1787 // CHECK5-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]
1788 // CHECK5-NEXT:    [[TMP4:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP2]]
1789 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]
1790 // CHECK5-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64
1791 // CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]]
1792 // CHECK5-NEXT:    store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]]
1793 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]
1794 // CHECK5-NEXT:    [[IDXPROM1:%.*]] = sext i32 [[TMP6]] to i64
1795 // CHECK5-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM1]]
1796 // CHECK5-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[VAR]], i64 4, i1 false), !llvm.access.group [[ACC_GRP2]]
1797 // CHECK5-NEXT:    [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]]
1798 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP2]]
1799 // CHECK5-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP8]], [[TMP7]]
1800 // CHECK5-NEXT:    store i32 [[ADD3]], ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP2]]
1801 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1802 // CHECK5:       omp.body.continue:
1803 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1804 // CHECK5:       omp.inner.for.inc:
1805 // CHECK5-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
1806 // CHECK5-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP9]], 1
1807 // CHECK5-NEXT:    store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]]
1808 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]]
1809 // CHECK5:       omp.inner.for.end:
1810 // CHECK5-NEXT:    store i32 2, ptr [[I]], align 4
1811 // CHECK5-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
1812 // CHECK5-NEXT:    [[ARRAY_BEGIN5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
1813 // CHECK5-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN5]], i64 2
1814 // CHECK5-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1815 // CHECK5:       arraydestroy.body:
1816 // CHECK5-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP10]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1817 // CHECK5-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1818 // CHECK5-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1819 // CHECK5-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN5]]
1820 // CHECK5-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY]]
1821 // CHECK5:       arraydestroy.done6:
1822 // CHECK5-NEXT:    [[CALL:%.*]] = call noundef signext i32 @_Z5tmainIiET_v()
1823 // CHECK5-NEXT:    ret i32 [[CALL]]
1824 //
1825 //
1826 // CHECK5-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
1827 // CHECK5-SAME: () #[[ATTR5:[0-9]+]] comdat {
1828 // CHECK5-NEXT:  entry:
1829 // CHECK5-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
1830 // CHECK5-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1831 // CHECK5-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
1832 // CHECK5-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
1833 // CHECK5-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
1834 // CHECK5-NEXT:    [[VAR:%.*]] = alloca ptr, align 8
1835 // CHECK5-NEXT:    [[TMP:%.*]] = alloca i32, align 4
1836 // CHECK5-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 8
1837 // CHECK5-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
1838 // CHECK5-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
1839 // CHECK5-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
1840 // CHECK5-NEXT:    [[I:%.*]] = alloca i32, align 4
1841 // CHECK5-NEXT:    [[T_VAR2:%.*]] = alloca i32, align 4
1842 // CHECK5-NEXT:    [[VEC3:%.*]] = alloca [2 x i32], align 4
1843 // CHECK5-NEXT:    [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4
1844 // CHECK5-NEXT:    [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4
1845 // CHECK5-NEXT:    [[_TMP6:%.*]] = alloca ptr, align 8
1846 // CHECK5-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])
1847 // CHECK5-NEXT:    store i32 0, ptr [[T_VAR]], align 4
1848 // CHECK5-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i64 8, i1 false)
1849 // CHECK5-NEXT:    [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 0
1850 // CHECK5-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef signext 1)
1851 // CHECK5-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYINIT_BEGIN]], i64 1
1852 // CHECK5-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef signext 2)
1853 // CHECK5-NEXT:    store ptr [[TEST]], ptr [[VAR]], align 8
1854 // CHECK5-NEXT:    store ptr undef, ptr [[_TMP1]], align 8
1855 // CHECK5-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
1856 // CHECK5-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
1857 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
1858 // CHECK5-NEXT:    store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4
1859 // CHECK5-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0
1860 // CHECK5-NEXT:    [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 2
1861 // CHECK5-NEXT:    br label [[ARRAYCTOR_LOOP:%.*]]
1862 // CHECK5:       arrayctor.loop:
1863 // CHECK5-NEXT:    [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1864 // CHECK5-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
1865 // CHECK5-NEXT:    [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i64 1
1866 // CHECK5-NEXT:    [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1867 // CHECK5-NEXT:    br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1868 // CHECK5:       arrayctor.cont:
1869 // CHECK5-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]])
1870 // CHECK5-NEXT:    store ptr [[VAR5]], ptr [[_TMP6]], align 8
1871 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
1872 // CHECK5:       omp.inner.for.cond:
1873 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]]
1874 // CHECK5-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP6]]
1875 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
1876 // CHECK5-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
1877 // CHECK5:       omp.inner.for.cond.cleanup:
1878 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
1879 // CHECK5:       omp.inner.for.body:
1880 // CHECK5-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
1881 // CHECK5-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
1882 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
1883 // CHECK5-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]]
1884 // CHECK5-NEXT:    [[TMP4:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP6]]
1885 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]]
1886 // CHECK5-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64
1887 // CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i64 0, i64 [[IDXPROM]]
1888 // CHECK5-NEXT:    store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]]
1889 // CHECK5-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[_TMP6]], align 8, !llvm.access.group [[ACC_GRP6]]
1890 // CHECK5-NEXT:    [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]]
1891 // CHECK5-NEXT:    [[IDXPROM7:%.*]] = sext i32 [[TMP7]] to i64
1892 // CHECK5-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM7]]
1893 // CHECK5-NEXT:    call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP6]], i64 4, i1 false), !llvm.access.group [[ACC_GRP6]]
1894 // CHECK5-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
1895 // CHECK5:       omp.body.continue:
1896 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
1897 // CHECK5:       omp.inner.for.inc:
1898 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
1899 // CHECK5-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP8]], 1
1900 // CHECK5-NEXT:    store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP6]]
1901 // CHECK5-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]]
1902 // CHECK5:       omp.inner.for.end:
1903 // CHECK5-NEXT:    store i32 2, ptr [[I]], align 4
1904 // CHECK5-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]
1905 // CHECK5-NEXT:    [[ARRAY_BEGIN10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0
1906 // CHECK5-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN10]], i64 2
1907 // CHECK5-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1908 // CHECK5:       arraydestroy.body:
1909 // CHECK5-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP9]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1910 // CHECK5-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1911 // CHECK5-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
1912 // CHECK5-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN10]]
1913 // CHECK5-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE11:%.*]], label [[ARRAYDESTROY_BODY]]
1914 // CHECK5:       arraydestroy.done11:
1915 // CHECK5-NEXT:    store i32 0, ptr [[RETVAL]], align 4
1916 // CHECK5-NEXT:    [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
1917 // CHECK5-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN12]], i64 2
1918 // CHECK5-NEXT:    br label [[ARRAYDESTROY_BODY13:%.*]]
1919 // CHECK5:       arraydestroy.body13:
1920 // CHECK5-NEXT:    [[ARRAYDESTROY_ELEMENTPAST14:%.*]] = phi ptr [ [[TMP10]], [[ARRAYDESTROY_DONE11]] ], [ [[ARRAYDESTROY_ELEMENT15:%.*]], [[ARRAYDESTROY_BODY13]] ]
1921 // CHECK5-NEXT:    [[ARRAYDESTROY_ELEMENT15]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST14]], i64 -1
1922 // CHECK5-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT15]]) #[[ATTR2]]
1923 // CHECK5-NEXT:    [[ARRAYDESTROY_DONE16:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT15]], [[ARRAY_BEGIN12]]
1924 // CHECK5-NEXT:    br i1 [[ARRAYDESTROY_DONE16]], label [[ARRAYDESTROY_DONE17:%.*]], label [[ARRAYDESTROY_BODY13]]
1925 // CHECK5:       arraydestroy.done17:
1926 // CHECK5-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
1927 // CHECK5-NEXT:    [[TMP11:%.*]] = load i32, ptr [[RETVAL]], align 4
1928 // CHECK5-NEXT:    ret i32 [[TMP11]]
1929 //
1930 //
1931 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
1932 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1933 // CHECK5-NEXT:  entry:
1934 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1935 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1936 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1937 // CHECK5-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
1938 // CHECK5-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
1939 // CHECK5-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
1940 // CHECK5-NEXT:    store float [[CONV]], ptr [[F]], align 4
1941 // CHECK5-NEXT:    ret void
1942 //
1943 //
1944 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
1945 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1946 // CHECK5-NEXT:  entry:
1947 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1948 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1949 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1950 // CHECK5-NEXT:    ret void
1951 //
1952 //
1953 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
1954 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1955 // CHECK5-NEXT:  entry:
1956 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1957 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
1958 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1959 // CHECK5-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
1960 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1961 // CHECK5-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
1962 // CHECK5-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
1963 // CHECK5-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
1964 // CHECK5-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
1965 // CHECK5-NEXT:    [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
1966 // CHECK5-NEXT:    store float [[ADD]], ptr [[F]], align 4
1967 // CHECK5-NEXT:    ret void
1968 //
1969 //
1970 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
1971 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1972 // CHECK5-NEXT:  entry:
1973 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1974 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1975 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1976 // CHECK5-NEXT:    call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
1977 // CHECK5-NEXT:    ret void
1978 //
1979 //
1980 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
1981 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1982 // CHECK5-NEXT:  entry:
1983 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1984 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
1985 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1986 // CHECK5-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
1987 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1988 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
1989 // CHECK5-NEXT:    call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef signext [[TMP0]])
1990 // CHECK5-NEXT:    ret void
1991 //
1992 //
1993 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
1994 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
1995 // CHECK5-NEXT:  entry:
1996 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1997 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1998 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1999 // CHECK5-NEXT:    call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
2000 // CHECK5-NEXT:    ret void
2001 //
2002 //
2003 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
2004 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
2005 // CHECK5-NEXT:  entry:
2006 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2007 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2008 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2009 // CHECK5-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
2010 // CHECK5-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
2011 // CHECK5-NEXT:    store i32 [[TMP0]], ptr [[F]], align 4
2012 // CHECK5-NEXT:    ret void
2013 //
2014 //
2015 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
2016 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
2017 // CHECK5-NEXT:  entry:
2018 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2019 // CHECK5-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2020 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2021 // CHECK5-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
2022 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2023 // CHECK5-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
2024 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
2025 // CHECK5-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
2026 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
2027 // CHECK5-NEXT:    store i32 [[ADD]], ptr [[F]], align 4
2028 // CHECK5-NEXT:    ret void
2029 //
2030 //
2031 // CHECK5-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
2032 // CHECK5-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
2033 // CHECK5-NEXT:  entry:
2034 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2035 // CHECK5-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2036 // CHECK5-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2037 // CHECK5-NEXT:    ret void
2038 //
2039 //
2040 // CHECK5-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_simd_private_codegen.cpp
2041 // CHECK5-SAME: () #[[ATTR0]] {
2042 // CHECK5-NEXT:  entry:
2043 // CHECK5-NEXT:    call void @__cxx_global_var_init()
2044 // CHECK5-NEXT:    call void @__cxx_global_var_init.1()
2045 // CHECK5-NEXT:    call void @__cxx_global_var_init.2()
2046 // CHECK5-NEXT:    ret void
2047 //
2048 //
2049 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init
2050 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] {
2051 // CHECK7-NEXT:  entry:
2052 // CHECK7-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
2053 // CHECK7-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
2054 // CHECK7-NEXT:    ret void
2055 //
2056 //
2057 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
2058 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
2059 // CHECK7-NEXT:  entry:
2060 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2061 // CHECK7-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2062 // CHECK7-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2063 // CHECK7-NEXT:    call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
2064 // CHECK7-NEXT:    ret void
2065 //
2066 //
2067 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
2068 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2069 // CHECK7-NEXT:  entry:
2070 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2071 // CHECK7-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2072 // CHECK7-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2073 // CHECK7-NEXT:    call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
2074 // CHECK7-NEXT:    ret void
2075 //
2076 //
2077 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
2078 // CHECK7-SAME: () #[[ATTR0]] {
2079 // CHECK7-NEXT:  entry:
2080 // CHECK7-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
2081 // CHECK7-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 1), float noundef 2.000000e+00)
2082 // CHECK7-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
2083 // CHECK7-NEXT:    ret void
2084 //
2085 //
2086 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
2087 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2088 // CHECK7-NEXT:  entry:
2089 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2090 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
2091 // CHECK7-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2092 // CHECK7-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
2093 // CHECK7-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2094 // CHECK7-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
2095 // CHECK7-NEXT:    call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
2096 // CHECK7-NEXT:    ret void
2097 //
2098 //
2099 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
2100 // CHECK7-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {
2101 // CHECK7-NEXT:  entry:
2102 // CHECK7-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 4
2103 // CHECK7-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 4
2104 // CHECK7-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
2105 // CHECK7:       arraydestroy.body:
2106 // CHECK7-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i32 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2107 // CHECK7-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2108 // CHECK7-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2109 // CHECK7-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr
2110 // CHECK7-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
2111 // CHECK7:       arraydestroy.done1:
2112 // CHECK7-NEXT:    ret void
2113 //
2114 //
2115 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
2116 // CHECK7-SAME: () #[[ATTR0]] {
2117 // CHECK7-NEXT:  entry:
2118 // CHECK7-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)
2119 // CHECK7-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]
2120 // CHECK7-NEXT:    ret void
2121 //
2122 //
2123 // CHECK7-LABEL: define {{[^@]+}}@main
2124 // CHECK7-SAME: () #[[ATTR3:[0-9]+]] {
2125 // CHECK7-NEXT:  entry:
2126 // CHECK7-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
2127 // CHECK7-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2128 // CHECK7-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2129 // CHECK7-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2130 // CHECK7-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2131 // CHECK7-NEXT:    [[I:%.*]] = alloca i32, align 4
2132 // CHECK7-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
2133 // CHECK7-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
2134 // CHECK7-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4
2135 // CHECK7-NEXT:    [[VAR:%.*]] = alloca [[STRUCT_S:%.*]], align 4
2136 // CHECK7-NEXT:    [[SIVAR:%.*]] = alloca i32, align 4
2137 // CHECK7-NEXT:    store i32 0, ptr [[RETVAL]], align 4
2138 // CHECK7-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
2139 // CHECK7-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
2140 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
2141 // CHECK7-NEXT:    store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4
2142 // CHECK7-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
2143 // CHECK7-NEXT:    [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN]], i32 2
2144 // CHECK7-NEXT:    br label [[ARRAYCTOR_LOOP:%.*]]
2145 // CHECK7:       arrayctor.loop:
2146 // CHECK7-NEXT:    [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
2147 // CHECK7-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
2148 // CHECK7-NEXT:    [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYCTOR_CUR]], i32 1
2149 // CHECK7-NEXT:    [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
2150 // CHECK7-NEXT:    br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
2151 // CHECK7:       arrayctor.cont:
2152 // CHECK7-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]])
2153 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2154 // CHECK7:       omp.inner.for.cond:
2155 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3:![0-9]+]]
2156 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP3]]
2157 // CHECK7-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
2158 // CHECK7-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2159 // CHECK7:       omp.inner.for.cond.cleanup:
2160 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
2161 // CHECK7:       omp.inner.for.body:
2162 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]
2163 // CHECK7-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
2164 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2165 // CHECK7-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]]
2166 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP3]]
2167 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]]
2168 // CHECK7-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP5]]
2169 // CHECK7-NEXT:    store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]]
2170 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]]
2171 // CHECK7-NEXT:    [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP6]]
2172 // CHECK7-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX1]], ptr align 4 [[VAR]], i32 4, i1 false), !llvm.access.group [[ACC_GRP3]]
2173 // CHECK7-NEXT:    [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]]
2174 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP3]]
2175 // CHECK7-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP8]], [[TMP7]]
2176 // CHECK7-NEXT:    store i32 [[ADD2]], ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP3]]
2177 // CHECK7-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2178 // CHECK7:       omp.body.continue:
2179 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2180 // CHECK7:       omp.inner.for.inc:
2181 // CHECK7-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]
2182 // CHECK7-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1
2183 // CHECK7-NEXT:    store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]]
2184 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
2185 // CHECK7:       omp.inner.for.end:
2186 // CHECK7-NEXT:    store i32 2, ptr [[I]], align 4
2187 // CHECK7-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]]
2188 // CHECK7-NEXT:    [[ARRAY_BEGIN4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0
2189 // CHECK7-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAY_BEGIN4]], i32 2
2190 // CHECK7-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
2191 // CHECK7:       arraydestroy.body:
2192 // CHECK7-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP10]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2193 // CHECK7-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2194 // CHECK7-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2195 // CHECK7-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN4]]
2196 // CHECK7-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE5:%.*]], label [[ARRAYDESTROY_BODY]]
2197 // CHECK7:       arraydestroy.done5:
2198 // CHECK7-NEXT:    [[CALL:%.*]] = call noundef i32 @_Z5tmainIiET_v()
2199 // CHECK7-NEXT:    ret i32 [[CALL]]
2200 //
2201 //
2202 // CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
2203 // CHECK7-SAME: () #[[ATTR5:[0-9]+]] comdat {
2204 // CHECK7-NEXT:  entry:
2205 // CHECK7-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
2206 // CHECK7-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
2207 // CHECK7-NEXT:    [[T_VAR:%.*]] = alloca i32, align 4
2208 // CHECK7-NEXT:    [[VEC:%.*]] = alloca [2 x i32], align 4
2209 // CHECK7-NEXT:    [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4
2210 // CHECK7-NEXT:    [[VAR:%.*]] = alloca ptr, align 4
2211 // CHECK7-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2212 // CHECK7-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 4
2213 // CHECK7-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2214 // CHECK7-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2215 // CHECK7-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2216 // CHECK7-NEXT:    [[I:%.*]] = alloca i32, align 4
2217 // CHECK7-NEXT:    [[T_VAR2:%.*]] = alloca i32, align 4
2218 // CHECK7-NEXT:    [[VEC3:%.*]] = alloca [2 x i32], align 4
2219 // CHECK7-NEXT:    [[S_ARR4:%.*]] = alloca [2 x %struct.S.0], align 4
2220 // CHECK7-NEXT:    [[VAR5:%.*]] = alloca [[STRUCT_S_0]], align 4
2221 // CHECK7-NEXT:    [[_TMP6:%.*]] = alloca ptr, align 4
2222 // CHECK7-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]])
2223 // CHECK7-NEXT:    store i32 0, ptr [[T_VAR]], align 4
2224 // CHECK7-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[VEC]], ptr align 4 @__const._Z5tmainIiET_v.vec, i32 8, i1 false)
2225 // CHECK7-NEXT:    [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
2226 // CHECK7-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 noundef 1)
2227 // CHECK7-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYINIT_BEGIN]], i32 1
2228 // CHECK7-NEXT:    call void @_ZN1SIiEC1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)
2229 // CHECK7-NEXT:    store ptr [[TEST]], ptr [[VAR]], align 4
2230 // CHECK7-NEXT:    store ptr undef, ptr [[_TMP1]], align 4
2231 // CHECK7-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
2232 // CHECK7-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
2233 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
2234 // CHECK7-NEXT:    store i32 [[TMP0]], ptr [[DOTOMP_IV]], align 4
2235 // CHECK7-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0
2236 // CHECK7-NEXT:    [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i32 2
2237 // CHECK7-NEXT:    br label [[ARRAYCTOR_LOOP:%.*]]
2238 // CHECK7:       arrayctor.loop:
2239 // CHECK7-NEXT:    [[ARRAYCTOR_CUR:%.*]] = phi ptr [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
2240 // CHECK7-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYCTOR_CUR]])
2241 // CHECK7-NEXT:    [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYCTOR_CUR]], i32 1
2242 // CHECK7-NEXT:    [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
2243 // CHECK7-NEXT:    br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
2244 // CHECK7:       arrayctor.cont:
2245 // CHECK7-NEXT:    call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]])
2246 // CHECK7-NEXT:    store ptr [[VAR5]], ptr [[_TMP6]], align 4
2247 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2248 // CHECK7:       omp.inner.for.cond:
2249 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7:![0-9]+]]
2250 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP7]]
2251 // CHECK7-NEXT:    [[CMP:%.*]] = icmp sle i32 [[TMP1]], [[TMP2]]
2252 // CHECK7-NEXT:    br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]]
2253 // CHECK7:       omp.inner.for.cond.cleanup:
2254 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_END:%.*]]
2255 // CHECK7:       omp.inner.for.body:
2256 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]]
2257 // CHECK7-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
2258 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2259 // CHECK7-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]]
2260 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP7]]
2261 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]]
2262 // CHECK7-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i32 0, i32 [[TMP5]]
2263 // CHECK7-NEXT:    store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP7]]
2264 // CHECK7-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[_TMP6]], align 4, !llvm.access.group [[ACC_GRP7]]
2265 // CHECK7-NEXT:    [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]]
2266 // CHECK7-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 [[TMP7]]
2267 // CHECK7-NEXT:    call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[TMP6]], i32 4, i1 false), !llvm.access.group [[ACC_GRP7]]
2268 // CHECK7-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2269 // CHECK7:       omp.body.continue:
2270 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2271 // CHECK7:       omp.inner.for.inc:
2272 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]]
2273 // CHECK7-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP8]], 1
2274 // CHECK7-NEXT:    store i32 [[ADD8]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP7]]
2275 // CHECK7-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
2276 // CHECK7:       omp.inner.for.end:
2277 // CHECK7-NEXT:    store i32 2, ptr [[I]], align 4
2278 // CHECK7-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]]
2279 // CHECK7-NEXT:    [[ARRAY_BEGIN9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 0
2280 // CHECK7-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN9]], i32 2
2281 // CHECK7-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
2282 // CHECK7:       arraydestroy.body:
2283 // CHECK7-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP9]], [[OMP_INNER_FOR_END]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2284 // CHECK7-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i32 -1
2285 // CHECK7-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2286 // CHECK7-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN9]]
2287 // CHECK7-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE10:%.*]], label [[ARRAYDESTROY_BODY]]
2288 // CHECK7:       arraydestroy.done10:
2289 // CHECK7-NEXT:    store i32 0, ptr [[RETVAL]], align 4
2290 // CHECK7-NEXT:    [[ARRAY_BEGIN11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0
2291 // CHECK7-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAY_BEGIN11]], i32 2
2292 // CHECK7-NEXT:    br label [[ARRAYDESTROY_BODY12:%.*]]
2293 // CHECK7:       arraydestroy.body12:
2294 // CHECK7-NEXT:    [[ARRAYDESTROY_ELEMENTPAST13:%.*]] = phi ptr [ [[TMP10]], [[ARRAYDESTROY_DONE10]] ], [ [[ARRAYDESTROY_ELEMENT14:%.*]], [[ARRAYDESTROY_BODY12]] ]
2295 // CHECK7-NEXT:    [[ARRAYDESTROY_ELEMENT14]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDESTROY_ELEMENTPAST13]], i32 -1
2296 // CHECK7-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT14]]) #[[ATTR2]]
2297 // CHECK7-NEXT:    [[ARRAYDESTROY_DONE15:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT14]], [[ARRAY_BEGIN11]]
2298 // CHECK7-NEXT:    br i1 [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_DONE16:%.*]], label [[ARRAYDESTROY_BODY12]]
2299 // CHECK7:       arraydestroy.done16:
2300 // CHECK7-NEXT:    call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR2]]
2301 // CHECK7-NEXT:    [[TMP11:%.*]] = load i32, ptr [[RETVAL]], align 4
2302 // CHECK7-NEXT:    ret i32 [[TMP11]]
2303 //
2304 //
2305 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
2306 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2307 // CHECK7-NEXT:  entry:
2308 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2309 // CHECK7-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2310 // CHECK7-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2311 // CHECK7-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
2312 // CHECK7-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
2313 // CHECK7-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
2314 // CHECK7-NEXT:    store float [[CONV]], ptr [[F]], align 4
2315 // CHECK7-NEXT:    ret void
2316 //
2317 //
2318 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
2319 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2320 // CHECK7-NEXT:  entry:
2321 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2322 // CHECK7-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2323 // CHECK7-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2324 // CHECK7-NEXT:    ret void
2325 //
2326 //
2327 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
2328 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2329 // CHECK7-NEXT:  entry:
2330 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2331 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
2332 // CHECK7-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2333 // CHECK7-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
2334 // CHECK7-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2335 // CHECK7-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
2336 // CHECK7-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
2337 // CHECK7-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
2338 // CHECK7-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
2339 // CHECK7-NEXT:    [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
2340 // CHECK7-NEXT:    store float [[ADD]], ptr [[F]], align 4
2341 // CHECK7-NEXT:    ret void
2342 //
2343 //
2344 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
2345 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2346 // CHECK7-NEXT:  entry:
2347 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2348 // CHECK7-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2349 // CHECK7-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2350 // CHECK7-NEXT:    call void @_ZN1SIiEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
2351 // CHECK7-NEXT:    ret void
2352 //
2353 //
2354 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
2355 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2356 // CHECK7-NEXT:  entry:
2357 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2358 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2359 // CHECK7-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2360 // CHECK7-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
2361 // CHECK7-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2362 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
2363 // CHECK7-NEXT:    call void @_ZN1SIiEC2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])
2364 // CHECK7-NEXT:    ret void
2365 //
2366 //
2367 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
2368 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2369 // CHECK7-NEXT:  entry:
2370 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2371 // CHECK7-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2372 // CHECK7-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2373 // CHECK7-NEXT:    call void @_ZN1SIiED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
2374 // CHECK7-NEXT:    ret void
2375 //
2376 //
2377 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
2378 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2379 // CHECK7-NEXT:  entry:
2380 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2381 // CHECK7-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2382 // CHECK7-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2383 // CHECK7-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
2384 // CHECK7-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
2385 // CHECK7-NEXT:    store i32 [[TMP0]], ptr [[F]], align 4
2386 // CHECK7-NEXT:    ret void
2387 //
2388 //
2389 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
2390 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2391 // CHECK7-NEXT:  entry:
2392 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2393 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2394 // CHECK7-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2395 // CHECK7-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
2396 // CHECK7-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2397 // CHECK7-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[THIS1]], i32 0, i32 0
2398 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
2399 // CHECK7-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
2400 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
2401 // CHECK7-NEXT:    store i32 [[ADD]], ptr [[F]], align 4
2402 // CHECK7-NEXT:    ret void
2403 //
2404 //
2405 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
2406 // CHECK7-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2407 // CHECK7-NEXT:  entry:
2408 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 4
2409 // CHECK7-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
2410 // CHECK7-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
2411 // CHECK7-NEXT:    ret void
2412 //
2413 //
2414 // CHECK7-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_simd_private_codegen.cpp
2415 // CHECK7-SAME: () #[[ATTR0]] {
2416 // CHECK7-NEXT:  entry:
2417 // CHECK7-NEXT:    call void @__cxx_global_var_init()
2418 // CHECK7-NEXT:    call void @__cxx_global_var_init.1()
2419 // CHECK7-NEXT:    call void @__cxx_global_var_init.2()
2420 // CHECK7-NEXT:    ret void
2421 //
2422 //
2423 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init
2424 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] {
2425 // CHECK9-NEXT:  entry:
2426 // CHECK9-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
2427 // CHECK9-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
2428 // CHECK9-NEXT:    ret void
2429 //
2430 //
2431 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
2432 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
2433 // CHECK9-NEXT:  entry:
2434 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2435 // CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2436 // CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2437 // CHECK9-NEXT:    call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
2438 // CHECK9-NEXT:    ret void
2439 //
2440 //
2441 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
2442 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
2443 // CHECK9-NEXT:  entry:
2444 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2445 // CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2446 // CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2447 // CHECK9-NEXT:    call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
2448 // CHECK9-NEXT:    ret void
2449 //
2450 //
2451 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
2452 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
2453 // CHECK9-NEXT:  entry:
2454 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2455 // CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2456 // CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2457 // CHECK9-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
2458 // CHECK9-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
2459 // CHECK9-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
2460 // CHECK9-NEXT:    store float [[CONV]], ptr [[F]], align 4
2461 // CHECK9-NEXT:    ret void
2462 //
2463 //
2464 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
2465 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
2466 // CHECK9-NEXT:  entry:
2467 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2468 // CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2469 // CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2470 // CHECK9-NEXT:    ret void
2471 //
2472 //
2473 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
2474 // CHECK9-SAME: () #[[ATTR0]] {
2475 // CHECK9-NEXT:  entry:
2476 // CHECK9-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
2477 // CHECK9-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)
2478 // CHECK9-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
2479 // CHECK9-NEXT:    ret void
2480 //
2481 //
2482 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
2483 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
2484 // CHECK9-NEXT:  entry:
2485 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2486 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
2487 // CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2488 // CHECK9-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
2489 // CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2490 // CHECK9-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
2491 // CHECK9-NEXT:    call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
2492 // CHECK9-NEXT:    ret void
2493 //
2494 //
2495 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
2496 // CHECK9-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {
2497 // CHECK9-NEXT:  entry:
2498 // CHECK9-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
2499 // CHECK9-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
2500 // CHECK9-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
2501 // CHECK9:       arraydestroy.body:
2502 // CHECK9-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2503 // CHECK9-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
2504 // CHECK9-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2505 // CHECK9-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr
2506 // CHECK9-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
2507 // CHECK9:       arraydestroy.done1:
2508 // CHECK9-NEXT:    ret void
2509 //
2510 //
2511 // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
2512 // CHECK9-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
2513 // CHECK9-NEXT:  entry:
2514 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2515 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
2516 // CHECK9-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2517 // CHECK9-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
2518 // CHECK9-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2519 // CHECK9-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
2520 // CHECK9-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
2521 // CHECK9-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
2522 // CHECK9-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
2523 // CHECK9-NEXT:    [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
2524 // CHECK9-NEXT:    store float [[ADD]], ptr [[F]], align 4
2525 // CHECK9-NEXT:    ret void
2526 //
2527 //
2528 // CHECK9-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
2529 // CHECK9-SAME: () #[[ATTR0]] {
2530 // CHECK9-NEXT:  entry:
2531 // CHECK9-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)
2532 // CHECK9-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]
2533 // CHECK9-NEXT:    ret void
2534 //
2535 //
2536 // CHECK9-LABEL: define {{[^@]+}}@main
2537 // CHECK9-SAME: () #[[ATTR3:[0-9]+]] {
2538 // CHECK9-NEXT:  entry:
2539 // CHECK9-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
2540 // CHECK9-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
2541 // CHECK9-NEXT:    store i32 0, ptr [[RETVAL]], align 4
2542 // CHECK9-NEXT:    call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])
2543 // CHECK9-NEXT:    ret i32 0
2544 //
2545 //
2546 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75
2547 // CHECK9-SAME: (i64 noundef [[G1:%.*]]) #[[ATTR5:[0-9]+]] {
2548 // CHECK9-NEXT:  entry:
2549 // CHECK9-NEXT:    [[G1_ADDR:%.*]] = alloca i64, align 8
2550 // CHECK9-NEXT:    [[TMP:%.*]] = alloca ptr, align 8
2551 // CHECK9-NEXT:    store i64 [[G1]], ptr [[G1_ADDR]], align 8
2552 // CHECK9-NEXT:    store ptr [[G1_ADDR]], ptr [[TMP]], align 8
2553 // CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_teams(ptr @[[GLOB3:[0-9]+]], i32 0, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75.omp_outlined)
2554 // CHECK9-NEXT:    ret void
2555 //
2556 //
2557 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75.omp_outlined
2558 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR6:[0-9]+]] {
2559 // CHECK9-NEXT:  entry:
2560 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
2561 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
2562 // CHECK9-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2563 // CHECK9-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2564 // CHECK9-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 8
2565 // CHECK9-NEXT:    [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
2566 // CHECK9-NEXT:    [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
2567 // CHECK9-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2568 // CHECK9-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2569 // CHECK9-NEXT:    [[G:%.*]] = alloca i32, align 4
2570 // CHECK9-NEXT:    [[G1:%.*]] = alloca i32, align 4
2571 // CHECK9-NEXT:    [[_TMP2:%.*]] = alloca ptr, align 8
2572 // CHECK9-NEXT:    [[SIVAR:%.*]] = alloca i32, align 4
2573 // CHECK9-NEXT:    [[I:%.*]] = alloca i32, align 4
2574 // CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
2575 // CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
2576 // CHECK9-NEXT:    store ptr undef, ptr [[_TMP1]], align 8
2577 // CHECK9-NEXT:    store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
2578 // CHECK9-NEXT:    store i32 1, ptr [[DOTOMP_COMB_UB]], align 4
2579 // CHECK9-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
2580 // CHECK9-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2581 // CHECK9-NEXT:    store ptr [[G1]], ptr [[_TMP2]], align 8
2582 // CHECK9-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
2583 // CHECK9-NEXT:    [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
2584 // CHECK9-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 92, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
2585 // CHECK9-NEXT:    [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2586 // CHECK9-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 1
2587 // CHECK9-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2588 // CHECK9:       cond.true:
2589 // CHECK9-NEXT:    br label [[COND_END:%.*]]
2590 // CHECK9:       cond.false:
2591 // CHECK9-NEXT:    [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
2592 // CHECK9-NEXT:    br label [[COND_END]]
2593 // CHECK9:       cond.end:
2594 // CHECK9-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
2595 // CHECK9-NEXT:    store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
2596 // CHECK9-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
2597 // CHECK9-NEXT:    store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
2598 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2599 // CHECK9:       omp.inner.for.cond:
2600 // CHECK9-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4:![0-9]+]]
2601 // CHECK9-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP4]]
2602 // CHECK9-NEXT:    [[CMP3:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
2603 // CHECK9-NEXT:    br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2604 // CHECK9:       omp.inner.for.body:
2605 // CHECK9-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP4]]
2606 // CHECK9-NEXT:    [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
2607 // CHECK9-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP4]]
2608 // CHECK9-NEXT:    [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
2609 // CHECK9-NEXT:    call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3]], i32 2, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75.omp_outlined.omp_outlined, i64 [[TMP8]], i64 [[TMP10]]), !llvm.access.group [[ACC_GRP4]]
2610 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2611 // CHECK9:       omp.inner.for.inc:
2612 // CHECK9-NEXT:    [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]]
2613 // CHECK9-NEXT:    [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP4]]
2614 // CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
2615 // CHECK9-NEXT:    store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP4]]
2616 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]]
2617 // CHECK9:       omp.inner.for.end:
2618 // CHECK9-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2619 // CHECK9:       omp.loop.exit:
2620 // CHECK9-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
2621 // CHECK9-NEXT:    [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
2622 // CHECK9-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
2623 // CHECK9-NEXT:    br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2624 // CHECK9:       .omp.final.then:
2625 // CHECK9-NEXT:    store i32 2, ptr [[I]], align 4
2626 // CHECK9-NEXT:    br label [[DOTOMP_FINAL_DONE]]
2627 // CHECK9:       .omp.final.done:
2628 // CHECK9-NEXT:    ret void
2629 //
2630 //
2631 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l75.omp_outlined.omp_outlined
2632 // CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR6]] {
2633 // CHECK9-NEXT:  entry:
2634 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
2635 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
2636 // CHECK9-NEXT:    [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
2637 // CHECK9-NEXT:    [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
2638 // CHECK9-NEXT:    [[DOTOMP_IV:%.*]] = alloca i32, align 4
2639 // CHECK9-NEXT:    [[TMP:%.*]] = alloca i32, align 4
2640 // CHECK9-NEXT:    [[_TMP1:%.*]] = alloca ptr, align 8
2641 // CHECK9-NEXT:    [[DOTOMP_LB:%.*]] = alloca i32, align 4
2642 // CHECK9-NEXT:    [[DOTOMP_UB:%.*]] = alloca i32, align 4
2643 // CHECK9-NEXT:    [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
2644 // CHECK9-NEXT:    [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
2645 // CHECK9-NEXT:    [[G:%.*]] = alloca i32, align 4
2646 // CHECK9-NEXT:    [[G1:%.*]] = alloca i32, align 4
2647 // CHECK9-NEXT:    [[_TMP3:%.*]] = alloca ptr, align 8
2648 // CHECK9-NEXT:    [[SIVAR:%.*]] = alloca i32, align 4
2649 // CHECK9-NEXT:    [[I:%.*]] = alloca i32, align 4
2650 // CHECK9-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8
2651 // CHECK9-NEXT:    store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
2652 // CHECK9-NEXT:    store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
2653 // CHECK9-NEXT:    store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
2654 // CHECK9-NEXT:    store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
2655 // CHECK9-NEXT:    store ptr undef, ptr [[_TMP1]], align 8
2656 // CHECK9-NEXT:    store i32 0, ptr [[DOTOMP_LB]], align 4
2657 // CHECK9-NEXT:    store i32 1, ptr [[DOTOMP_UB]], align 4
2658 // CHECK9-NEXT:    [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
2659 // CHECK9-NEXT:    [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
2660 // CHECK9-NEXT:    [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
2661 // CHECK9-NEXT:    [[CONV2:%.*]] = trunc i64 [[TMP1]] to i32
2662 // CHECK9-NEXT:    store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
2663 // CHECK9-NEXT:    store i32 [[CONV2]], ptr [[DOTOMP_UB]], align 4
2664 // CHECK9-NEXT:    store i32 1, ptr [[DOTOMP_STRIDE]], align 4
2665 // CHECK9-NEXT:    store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
2666 // CHECK9-NEXT:    store ptr [[G1]], ptr [[_TMP3]], align 8
2667 // CHECK9-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
2668 // CHECK9-NEXT:    [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
2669 // CHECK9-NEXT:    call void @__kmpc_for_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
2670 // CHECK9-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2671 // CHECK9-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 1
2672 // CHECK9-NEXT:    br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
2673 // CHECK9:       cond.true:
2674 // CHECK9-NEXT:    br label [[COND_END:%.*]]
2675 // CHECK9:       cond.false:
2676 // CHECK9-NEXT:    [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
2677 // CHECK9-NEXT:    br label [[COND_END]]
2678 // CHECK9:       cond.end:
2679 // CHECK9-NEXT:    [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
2680 // CHECK9-NEXT:    store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
2681 // CHECK9-NEXT:    [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
2682 // CHECK9-NEXT:    store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4
2683 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND:%.*]]
2684 // CHECK9:       omp.inner.for.cond:
2685 // CHECK9-NEXT:    [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8:![0-9]+]]
2686 // CHECK9-NEXT:    [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP8]]
2687 // CHECK9-NEXT:    [[CMP4:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
2688 // CHECK9-NEXT:    br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
2689 // CHECK9:       omp.inner.for.body:
2690 // CHECK9-NEXT:    [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]]
2691 // CHECK9-NEXT:    [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
2692 // CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 0, [[MUL]]
2693 // CHECK9-NEXT:    store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]]
2694 // CHECK9-NEXT:    store i32 1, ptr [[G]], align 4, !llvm.access.group [[ACC_GRP8]]
2695 // CHECK9-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[_TMP3]], align 8, !llvm.access.group [[ACC_GRP8]]
2696 // CHECK9-NEXT:    store volatile i32 1, ptr [[TMP10]], align 4, !llvm.access.group [[ACC_GRP8]]
2697 // CHECK9-NEXT:    store i32 2, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP8]]
2698 // CHECK9-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0
2699 // CHECK9-NEXT:    store ptr [[G]], ptr [[TMP11]], align 8, !llvm.access.group [[ACC_GRP8]]
2700 // CHECK9-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 1
2701 // CHECK9-NEXT:    [[TMP13:%.*]] = load ptr, ptr [[_TMP3]], align 8, !llvm.access.group [[ACC_GRP8]]
2702 // CHECK9-NEXT:    store ptr [[TMP13]], ptr [[TMP12]], align 8, !llvm.access.group [[ACC_GRP8]]
2703 // CHECK9-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 2
2704 // CHECK9-NEXT:    store ptr [[SIVAR]], ptr [[TMP14]], align 8, !llvm.access.group [[ACC_GRP8]]
2705 // CHECK9-NEXT:    call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(ptr noundef nonnull align 8 dereferenceable(24) [[REF_TMP]]), !llvm.access.group [[ACC_GRP8]]
2706 // CHECK9-NEXT:    br label [[OMP_BODY_CONTINUE:%.*]]
2707 // CHECK9:       omp.body.continue:
2708 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_INC:%.*]]
2709 // CHECK9:       omp.inner.for.inc:
2710 // CHECK9-NEXT:    [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]]
2711 // CHECK9-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP15]], 1
2712 // CHECK9-NEXT:    store i32 [[ADD5]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP8]]
2713 // CHECK9-NEXT:    br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
2714 // CHECK9:       omp.inner.for.end:
2715 // CHECK9-NEXT:    br label [[OMP_LOOP_EXIT:%.*]]
2716 // CHECK9:       omp.loop.exit:
2717 // CHECK9-NEXT:    call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]])
2718 // CHECK9-NEXT:    [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
2719 // CHECK9-NEXT:    [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
2720 // CHECK9-NEXT:    br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
2721 // CHECK9:       .omp.final.then:
2722 // CHECK9-NEXT:    store i32 2, ptr [[I]], align 4
2723 // CHECK9-NEXT:    br label [[DOTOMP_FINAL_DONE]]
2724 // CHECK9:       .omp.final.done:
2725 // CHECK9-NEXT:    ret void
2726 //
2727 //
2728 // CHECK9-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_simd_private_codegen.cpp
2729 // CHECK9-SAME: () #[[ATTR0]] {
2730 // CHECK9-NEXT:  entry:
2731 // CHECK9-NEXT:    call void @__cxx_global_var_init()
2732 // CHECK9-NEXT:    call void @__cxx_global_var_init.1()
2733 // CHECK9-NEXT:    call void @__cxx_global_var_init.2()
2734 // CHECK9-NEXT:    ret void
2735 //
2736 //
2737 // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
2738 // CHECK9-SAME: () #[[ATTR0]] {
2739 // CHECK9-NEXT:  entry:
2740 // CHECK9-NEXT:    call void @__tgt_register_requires(i64 1)
2741 // CHECK9-NEXT:    ret void
2742 //
2743 //
2744 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init
2745 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] {
2746 // CHECK11-NEXT:  entry:
2747 // CHECK11-NEXT:    call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) @test)
2748 // CHECK11-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @test, ptr @__dso_handle) #[[ATTR2:[0-9]+]]
2749 // CHECK11-NEXT:    ret void
2750 //
2751 //
2752 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
2753 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat {
2754 // CHECK11-NEXT:  entry:
2755 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2756 // CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2757 // CHECK11-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2758 // CHECK11-NEXT:    call void @_ZN1SIfEC2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]])
2759 // CHECK11-NEXT:    ret void
2760 //
2761 //
2762 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
2763 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
2764 // CHECK11-NEXT:  entry:
2765 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2766 // CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2767 // CHECK11-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2768 // CHECK11-NEXT:    call void @_ZN1SIfED2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR2]]
2769 // CHECK11-NEXT:    ret void
2770 //
2771 //
2772 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
2773 // CHECK11-SAME: () #[[ATTR0]] {
2774 // CHECK11-NEXT:  entry:
2775 // CHECK11-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @s_arr, float noundef 1.000000e+00)
2776 // CHECK11-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 1), float noundef 2.000000e+00)
2777 // CHECK11-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR2]]
2778 // CHECK11-NEXT:    ret void
2779 //
2780 //
2781 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
2782 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
2783 // CHECK11-NEXT:  entry:
2784 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2785 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
2786 // CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2787 // CHECK11-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
2788 // CHECK11-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2789 // CHECK11-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
2790 // CHECK11-NEXT:    call void @_ZN1SIfEC2Ef(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], float noundef [[TMP0]])
2791 // CHECK11-NEXT:    ret void
2792 //
2793 //
2794 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
2795 // CHECK11-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {
2796 // CHECK11-NEXT:  entry:
2797 // CHECK11-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
2798 // CHECK11-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
2799 // CHECK11-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
2800 // CHECK11:       arraydestroy.body:
2801 // CHECK11-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S:%.*]], ptr @s_arr, i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2802 // CHECK11-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
2803 // CHECK11-NEXT:    call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR2]]
2804 // CHECK11-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @s_arr
2805 // CHECK11-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
2806 // CHECK11:       arraydestroy.done1:
2807 // CHECK11-NEXT:    ret void
2808 //
2809 //
2810 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
2811 // CHECK11-SAME: () #[[ATTR0]] {
2812 // CHECK11-NEXT:  entry:
2813 // CHECK11-NEXT:    call void @_ZN1SIfEC1Ef(ptr noundef nonnull align 4 dereferenceable(4) @var, float noundef 3.000000e+00)
2814 // CHECK11-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN1SIfED1Ev, ptr @var, ptr @__dso_handle) #[[ATTR2]]
2815 // CHECK11-NEXT:    ret void
2816 //
2817 //
2818 // CHECK11-LABEL: define {{[^@]+}}@main
2819 // CHECK11-SAME: () #[[ATTR3:[0-9]+]] {
2820 // CHECK11-NEXT:  entry:
2821 // CHECK11-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
2822 // CHECK11-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
2823 // CHECK11-NEXT:    store i32 0, ptr [[RETVAL]], align 4
2824 // CHECK11-NEXT:    call void @"_ZZ4mainENK3$_0clEv"(ptr noundef nonnull align 1 dereferenceable(1) [[REF_TMP]])
2825 // CHECK11-NEXT:    ret i32 0
2826 //
2827 //
2828 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
2829 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
2830 // CHECK11-NEXT:  entry:
2831 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2832 // CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2833 // CHECK11-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2834 // CHECK11-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
2835 // CHECK11-NEXT:    [[TMP0:%.*]] = load volatile i32, ptr @g, align 4
2836 // CHECK11-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
2837 // CHECK11-NEXT:    store float [[CONV]], ptr [[F]], align 4
2838 // CHECK11-NEXT:    ret void
2839 //
2840 //
2841 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
2842 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat {
2843 // CHECK11-NEXT:  entry:
2844 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2845 // CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2846 // CHECK11-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2847 // CHECK11-NEXT:    ret void
2848 //
2849 //
2850 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
2851 // CHECK11-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], float noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat {
2852 // CHECK11-NEXT:  entry:
2853 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2854 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
2855 // CHECK11-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2856 // CHECK11-NEXT:    store float [[A]], ptr [[A_ADDR]], align 4
2857 // CHECK11-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2858 // CHECK11-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[THIS1]], i32 0, i32 0
2859 // CHECK11-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
2860 // CHECK11-NEXT:    [[TMP1:%.*]] = load volatile i32, ptr @g, align 4
2861 // CHECK11-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
2862 // CHECK11-NEXT:    [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
2863 // CHECK11-NEXT:    store float [[ADD]], ptr [[F]], align 4
2864 // CHECK11-NEXT:    ret void
2865 //
2866 //
2867 // CHECK11-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_teams_distribute_parallel_for_simd_private_codegen.cpp
2868 // CHECK11-SAME: () #[[ATTR0]] {
2869 // CHECK11-NEXT:  entry:
2870 // CHECK11-NEXT:    call void @__cxx_global_var_init()
2871 // CHECK11-NEXT:    call void @__cxx_global_var_init.1()
2872 // CHECK11-NEXT:    call void @__cxx_global_var_init.2()
2873 // CHECK11-NEXT:    ret void
2874 //