clang/test/OpenMP/threadprivate_codegen.cpp

   1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
   2 // RUN: %clang_cc1 -verify -fopenmp -fnoopenmp-use-tls -DBODY -triple x86_64-unknown-unknown -x c++ -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefixes=CHECK1
   3 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fnoopenmp-use-tls -DBODY -triple x86_64-unknown-unknown -x c++ -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefixes=CHECK2
   4
   5 // RUN: %clang_cc1 -verify -fopenmp-simd -fnoopenmp-use-tls -DBODY -triple x86_64-unknown-unknown -x c++ -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck --check-prefix SIMD1 %s
   6 // RUN: %clang_cc1 -fopenmp-simd -fnoopenmp-use-tls -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s
   7 // RUN: %clang_cc1 -fopenmp-simd -fnoopenmp-use-tls -DBODY -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD2 %s
   8 // RUN: %clang_cc1 -verify -fopenmp -DBODY -triple x86_64-unknown-unknown -x c++ -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefixes=CHECK-TLS1
   9 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -DBODY -triple x86_64-unknown-unknown -x c++ -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefixes=CHECK-TLS2
  10 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s
  11 // RUN: %clang_cc1 -fopenmp -DBODY -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefixes=CHECK-TLS3 %s
  12 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s
  13 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -DBODY -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefixes=CHECK-TLS4 %s
  14
  15 // RUN: %clang_cc1 -verify -fopenmp-simd -DBODY -triple x86_64-unknown-unknown -x c++ -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck --check-prefix SIMD3 %s
  16 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s
  17 // RUN: %clang_cc1 -fopenmp-simd -DBODY -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD4 %s
  18
  19 // RUN: %clang_cc1 -fopenmp -fnoopenmp-use-tls -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s
  20 // RUN: %clang_cc1 -fopenmp -fnoopenmp-use-tls -DBODY -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefixes=DEBUG1 %s
  21 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -fnoopenmp-use-tls -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s
  22 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -fnoopenmp-use-tls -DBODY -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -debug-info-kind=limited -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefixes=DEBUG2 %s
  23
  24 // expected-no-diagnostics
  25 #ifndef HEADER
  26 #define HEADER
  27 struct S1 {
  28   int a;
  29   S1()
  30       : a(0) {
  31   }
  32   S1(int a)
  33       : a(a) {
  34   }
  35   S1(const S1 &s) {
  36     a = 12 + s.a;
  37   }
  38   ~S1() {
  39     a = 0;
  40   }
  41 };
  42
  43 struct S2 {
  44   int a;
  45   double b;
  46   S2()
  47       : a(0) {
  48   }
  49   S2(int a)
  50       : a(a) {
  51   }
  52   S2(const S2 &s) {
  53     a = 12 + s.a;
  54   }
  55   ~S2() {
  56     a = 0;
  57   }
  58 };
  59
  60 struct S3 {
  61   int a;
  62   float b;
  63   S3()
  64       : a(0) {
  65   }
  66   S3(int a)
  67       : a(a) {
  68   }
  69   S3(const S3 &s) {
  70     a = 12 + s.a;
  71   }
  72   ~S3() {
  73     a = 0;
  74   }
  75 };
  76
  77 struct S4 {
  78   int a, b;
  79   S4()
  80       : a(0) {
  81   }
  82   S4(int a)
  83       : a(a) {
  84   }
  85   S4(const S4 &s) {
  86     a = 12 + s.a;
  87   }
  88   ~S4() {
  89     a = 0;
  90   }
  91 };
  92
  93 struct S5 {
  94   int a, b, c;
  95   S5()
  96       : a(0) {
  97   }
  98   S5(int a)
  99       : a(a) {
 100   }
 101   S5(const S5 &s) {
 102     a = 12 + s.a;
 103   }
 104   ~S5() {
 105     a = 0;
 106   }
 107 };
 108
 109 // CHECK-DAG:  [[GS1:@.+]] = internal global [[S1]] zeroinitializer
 110 // CHECK-DAG:  [[GS1]].cache. = common{{.*}} global ptr null
 111 // CHECK-DAG:  [[DEFAULT_LOC:@.+]] = private unnamed_addr constant [[IDENT]] { i32 0, i32 2, i32 0, i32 0, ptr {{@.+}} }
 112 // CHECK-DAG:  [[GS2:@.+]] = internal global [[S2]] zeroinitializer
 113 // CHECK-DAG:  [[ARR_X:@.+]] ={{.*}} global [2 x [3 x [[S1]]]] zeroinitializer
 114 // CHECK-DAG:  [[ARR_X]].cache. = common{{.*}} global ptr null
 115 // CHECK-DAG:  [[SM:@.+]] = internal global [[SMAIN]] zeroinitializer
 116 // CHECK-DAG:  [[SM]].cache. = common{{.*}} global ptr null
 117 // CHECK-DAG:  [[STATIC_S:@.+]] = external global [[S3]]
 118 // CHECK-DAG:  [[STATIC_S]].cache. = common{{.*}} global ptr null
 119 // CHECK-DAG:  [[GS3:@.+]] = external global [[S5]]
 120 // CHECK-DAG:  [[GS3]].cache. = common{{.*}} global ptr null
 121 // CHECK-DAG:  [[ST_INT_ST:@.+]] = linkonce_odr global i32 23
 122 // CHECK-DAG:  [[ST_INT_ST]].cache. = common{{.*}} global ptr null
 123 // CHECK-DAG:  [[ST_FLOAT_ST:@.+]] = linkonce_odr global float 2.300000e+01
 124 // CHECK-DAG:  [[ST_FLOAT_ST]].cache. = common{{.*}} global ptr null
 125 // CHECK-DAG:  [[ST_S4_ST:@.+]] = linkonce_odr global %struct.S4 zeroinitializer
 126 // CHECK-DAG:  [[ST_S4_ST]].cache. = common{{.*}} global ptr null
 127 // CHECK-NOT:  .cache. = common{{.*}} global ptr null
 128 // There is no cache for gs2 - it is not threadprivate. Check that there is only
 129 // 8 caches created (for Static::s, gs1, gs3, arr_x, main::sm, ST<int>::st,
 130 // ST<float>::st, ST<S4>::st)
 131 // CHECK-DEBUG-DAG: [[GS1:@.+]] = internal global [[S1]] zeroinitializer
 132 // CHECK-DEBUG-DAG: [[GS2:@.+]] = internal global [[S2]] zeroinitializer
 133 // CHECK-DEBUG-DAG: [[ARR_X:@.+]] ={{.*}} global [2 x [3 x [[S1]]]] zeroinitializer
 134 // CHECK-DEBUG-DAG: [[SM:@.+]] = internal global [[SMAIN]] zeroinitializer
 135 // CHECK-DEBUG-DAG: [[STATIC_S:@.+]] = external global [[S3]]
 136 // CHECK-DEBUG-DAG: [[GS3:@.+]] = external global [[S5]]
 137 // CHECK-DEBUG-DAG: [[ST_INT_ST:@.+]] = linkonce_odr global i32 23
 138 // CHECK-DEBUG-DAG: [[ST_FLOAT_ST:@.+]] = linkonce_odr global float 2.300000e+01
 139 // CHECK-DEBUG-DAG: [[ST_S4_ST:@.+]] = linkonce_odr global %struct.S4 zeroinitializer
 140
 141 // CHECK-DEBUG-DAG: [[LOC1:@.*]] = private unnamed_addr constant [{{[0-9]+}} x i8] c";{{.*}}threadprivate_codegen.cpp;;249;1;;\00"
 142 // CHECK-DEBUG-DAG: [[ID1:@.*]] = private unnamed_addr constant %struct.ident_t { {{.*}} [[LOC1]]
 143 // CHECK-DEBUG-DAG: [[LOC2:@.*]] = private unnamed_addr constant [{{[0-9]+}} x i8] c";{{.*}}threadprivate_codegen.cpp;;304;1;;\00"
 144 // CHECK-DEBUG-DAG: [[ID2:@.*]] = private unnamed_addr constant %struct.ident_t { {{.*}} [[LOC2]]
 145 // CHECK-DEBUG-DAG: [[LOC3:@.*]] = private unnamed_addr constant [{{[0-9]+}} x i8] c";{{.*}}threadprivate_codegen.cpp;;422;19;;\00"
 146 // CHECK-DEBUG-DAG: [[LOC4:@.*]] = private unnamed_addr constant [{{[0-9]+}} x i8] c";{{.*}}threadprivate_codegen.cpp;main;459;1;;\00"
 147 // CHECK-DEBUG-DAG: [[LOC5:@.*]] = private unnamed_addr constant [{{[0-9]+}} x i8] c";{{.*}}threadprivate_codegen.cpp;main;476;9;;\00"
 148 // CHECK-DEBUG-DAG: [[LOC6:@.*]] = private unnamed_addr constant [{{[0-9]+}} x i8] c";{{.*}}threadprivate_codegen.cpp;main;498;10;;\00"
 149 // CHECK-DEBUG-DAG: [[LOC7:@.*]] = private unnamed_addr constant [{{[0-9]+}} x i8] c";{{.*}}threadprivate_codegen.cpp;main;521;10;;\00"
 150 // CHECK-DEBUG-DAG: [[LOC8:@.*]] = private unnamed_addr constant [{{[0-9]+}} x i8] c";{{.*}}threadprivate_codegen.cpp;main;557;10;;\00"
 151 // CHECK-DEBUG-DAG: [[LOC9:@.*]] = private unnamed_addr constant [{{[0-9]+}} x i8] c";{{.*}}threadprivate_codegen.cpp;main;586;10;;\00"
 152 // CHECK-DEBUG-DAG: [[LOC10:@.*]] = private unnamed_addr constant [{{[0-9]+}} x i8] c";{{.*}}threadprivate_codegen.cpp;main;606;10;;\00"
 153 // CHECK-DEBUG-DAG: [[LOC11:@.*]] = private unnamed_addr constant [{{[0-9]+}} x i8] c";{{.*}}threadprivate_codegen.cpp;main;629;27;;\00"
 154 // CHECK-DEBUG-DAG: [[LOC12:@.*]] = private unnamed_addr constant [{{[0-9]+}} x i8] c";{{.*}}threadprivate_codegen.cpp;main;652;10;;\00"
 155 // CHECK-DEBUG-DAG: [[LOC13:@.*]] = private unnamed_addr constant [{{[0-9]+}} x i8] c";{{.*}}threadprivate_codegen.cpp;foobar;774;9;;\00"
 156 // CHECK-DEBUG-DAG: [[LOC14:@.*]] = private unnamed_addr constant [{{[0-9]+}} x i8] c";{{.*}}threadprivate_codegen.cpp;foobar;797;10;;\00"
 157 // CHECK-DEBUG-DAG: [[LOC15:@.*]] = private unnamed_addr constant [{{[0-9]+}} x i8] c";{{.*}}threadprivate_codegen.cpp;foobar;833;10;;\00"
 158 // CHECK-DEBUG-DAG: [[LOC16:@.*]] = private unnamed_addr constant [{{[0-9]+}} x i8] c";{{.*}}threadprivate_codegen.cpp;foobar;862;10;;\00"
 159 // CHECK-DEBUG-DAG: [[LOC17:@.*]] = private unnamed_addr constant [{{[0-9]+}} x i8] c";{{.*}}threadprivate_codegen.cpp;foobar;882;10;;\00"
 160 // CHECK-DEBUG-DAG: [[LOC18:@.*]] = private unnamed_addr constant [{{[0-9]+}} x i8] c";{{.*}}threadprivate_codegen.cpp;foobar;905;27;;\00"
 161 // CHECK-DEBUG-DAG: [[LOC19:@.*]] = private unnamed_addr constant [{{[0-9]+}} x i8] c";{{.*}}threadprivate_codegen.cpp;foobar;928;10;;\00"
 162 // CHECK-DEBUG-DAG: [[LOC20:@.*]] = private unnamed_addr constant [{{[0-9]+}} x i8] c";{{.*}}threadprivate_codegen.cpp;;363;1;;\00"
 163
 164 // CHECK-TLS-DAG:  [[GS1:@.+]] = internal thread_local global [[S1]] zeroinitializer
 165 // CHECK-TLS-DAG:  [[GS2:@.+]] = internal global [[S2]] zeroinitializer
 166 // CHECK-TLS-DAG:  [[ARR_X:@.+]] ={{.*}} thread_local global [2 x [3 x [[S1]]]] zeroinitializer
 167 // CHECK-TLS-DAG:  [[SM:@.+]] = internal thread_local global [[SMAIN]] zeroinitializer
 168 // CHECK-TLS-DAG:  [[SM_GUARD:@_ZGVZ4mainE2sm]] = internal thread_local global i8 0
 169 // CHECK-TLS-DAG:  [[STATIC_S:@.+]] = external thread_local global [[S3]]
 170 // CHECK-TLS-DAG:  [[GS3:@.+]] = external thread_local global [[S5]]
 171 // CHECK-TLS-DAG:  [[ST_INT_ST:@.+]] = linkonce_odr thread_local global i32 23
 172 // CHECK-TLS-DAG:  [[ST_FLOAT_ST:@.+]] = linkonce_odr thread_local global float 2.300000e+01
 173 // CHECK-TLS-DAG:  [[ST_S4_ST:@.+]] = linkonce_odr thread_local global %struct.S4 zeroinitializer
 174 // CHECK-TLS-DAG:  [[ST_S4_ST_GUARD:@_ZGVN2STI2S4E2stE]] = linkonce_odr thread_local global i64 0
 175 // CHECK-TLS-DAG:  @__tls_guard = internal thread_local global i8 0
 176 // CHECK-TLS-DAG:  @__dso_handle = external hidden global i8
 177 // CHECK-TLS-DAG:  [[GS1_TLS_INIT:@_ZTHL3gs1]] = internal alias void (), ptr @__tls_init
 178 // CHECK-TLS-DAG:  [[ARR_X_TLS_INIT:@_ZTH5arr_x]] ={{.*}} alias void (), ptr @__tls_init
 179 // CHECK-TLS-DAG:  [[ST_S4_ST_TLS_INIT:@_ZTHN2STI2S4E2stE]] = linkonce_odr alias void (), ptr [[ST_S4_ST_CXX_INIT:@[^, ]*]]
 180
 181 // OMP50-TLS: define internal void [[GS1_CXX_INIT:@.*]]()
 182 // OMP50-TLS: call void [[GS1_CTOR1:@.*]](ptr {{[^,]*}} [[GS1]], i32 5)
 183 // OMP50-TLS: call i32 @__cxa_thread_atexit(ptr [[GS1_DTOR1:.*]], ptr [[GS1]]
 184 // OMP50-TLS: }
 185 // OMP50-TLS: define {{.*}}void [[GS1_CTOR1]](ptr {{.*}}, i32 {{.*}})
 186 // OMP50-TLS: call void [[GS1_CTOR2:@.*]](ptr {{.*}}, i32 {{.*}})
 187 // OMP50-TLS: }
 188 // OMP50-TLS: define {{.*}}void [[GS1_DTOR1]](ptr {{.*}})
 189 // OMP50-TLS: call void [[GS1_DTOR2:@.*]](ptr {{.*}})
 190 // OMP50-TLS: }
 191 // OMP50-TLS: define {{.*}}void [[GS1_CTOR2]](ptr {{.*}}, i32 {{.*}})
 192 // OMP50-TLS: define {{.*}}void [[GS1_DTOR2]](ptr {{.*}})
 193
 194 // OMP50-TLS: define internal void [[GS2_CXX_INIT:@.*]]()
 195 // OMP50-TLS: call void [[GS2_CTOR1:@.*]](ptr {{[^,]*}} [[GS2]], i32 27)
 196 // OMP50-TLS: call i32 @__cxa_atexit(ptr [[GS2_DTOR1:.*]], ptr [[GS2]]
 197 // OMP50-TLS: }
 198 // OMP50-TLS: define {{.*}}void [[GS2_CTOR1]](ptr {{.*}}, i32 {{.*}})
 199 // OMP50-TLS: call void [[GS2_CTOR2:@.*]](ptr {{.*}}, i32 {{.*}})
 200 // OMP50-TLS: }
 201 // OMP50-TLS: define {{.*}}void [[GS2_DTOR1]](ptr {{.*}})
 202 // OMP50-TLS: call void [[GS2_DTOR2:@.*]](ptr {{.*}})
 203 // OMP50-TLS: }
 204 // OMP50-TLS: define {{.*}}void [[GS2_CTOR2]](ptr {{.*}}, i32 {{.*}})
 205 // OMP50-TLS: define {{.*}}void [[GS2_DTOR2]](ptr {{.*}})
 206
 207 // OMP50-TLS: define internal void [[ARR_X_CXX_INIT:@.*]]()
 208 // OMP50-TLS: invoke void [[GS1_CTOR1]](ptr {{[^,]*}} getelementptr inbounds ([2 x [3 x [[S1]]]], ptr [[ARR_X]], i{{.*}} 0, i{{.*}} 0, i{{.*}} 0), i{{.*}} 1)
 209 // OMP50-TLS: invoke void [[GS1_CTOR1]](ptr {{[^,]*}} getelementptr inbounds ([2 x [3 x [[S1]]]], ptr [[ARR_X]], i{{.*}} 0, i{{.*}} 0, i{{.*}} 1), i{{.*}} 2)
 210 // OMP50-TLS: invoke void [[GS1_CTOR1]](ptr {{[^,]*}} getelementptr inbounds ([2 x [3 x [[S1]]]], ptr [[ARR_X]], i{{.*}} 0, i{{.*}} 0, i{{.*}} 2), i{{.*}} 3)
 211 // OMP50-TLS: invoke void [[GS1_CTOR1]](ptr {{[^,]*}} getelementptr inbounds ([2 x [3 x [[S1]]]], ptr [[ARR_X]], i{{.*}} 0, i{{.*}} 1, i{{.*}} 0), i{{.*}} 4)
 212 // OMP50-TLS: invoke void [[GS1_CTOR1]](ptr {{[^,]*}} getelementptr inbounds ([2 x [3 x [[S1]]]], ptr [[ARR_X]], i{{.*}} 0, i{{.*}} 1, i{{.*}} 1), i{{.*}} 5)
 213 // OMP50-TLS: invoke void [[GS1_CTOR1]](ptr {{[^,]*}} getelementptr inbounds ([2 x [3 x [[S1]]]], ptr [[ARR_X]], i{{.*}} 0, i{{.*}} 1, i{{.*}} 2), i{{.*}} 6)
 214 // OMP50-TLS: call i32 @__cxa_thread_atexit(ptr [[ARR_X_CXX_DTOR:@[^,]+]]
 215 // OMP50-TLS: define internal void [[ARR_X_CXX_DTOR]](ptr %0)
 216 // OMP50-TLS: void [[GS1_DTOR1]](ptr {{.*}})
 217
 218 struct Static {
 219   static S3 s;
 220 #pragma omp threadprivate(s)
 221 };
 222
 223 static S1 gs1(5);
 224 #pragma omp threadprivate(gs1)
 225 #pragma omp threadprivate(gs1)
 226 // CHECK:      define {{.*}} [[S1_CTOR:@.*]](ptr {{.*}},
 227 // CHECK:      define {{.*}} [[S1_DTOR:@.*]](ptr {{.*}})
 228 // CHECK:      define internal {{.*}}ptr [[GS1_CTOR:@\.__kmpc_global_ctor_\..*]](ptr %0)
 229 // CHECK:      store ptr %0, ptr [[ARG_ADDR:%.*]],
 230 // CHECK:      [[ARG:%.+]] = load ptr, ptr [[ARG_ADDR]]
 231 // CHECK-NEXT: call {{.*}} [[S1_CTOR]](ptr {{[^,]*}} [[ARG]], {{.*}} 5)
 232 // CHECK:      [[ARG:%.+]] = load ptr, ptr [[ARG_ADDR]]
 233 // CHECK:      ret ptr [[ARG]]
 234 // CHECK-NEXT: }
 235 // CHECK:      define internal {{.*}}void [[GS1_DTOR:@\.__kmpc_global_dtor_\..*]](ptr %0)
 236 // CHECK:      store ptr %0, ptr [[ARG_ADDR:%.*]],
 237 // CHECK:      [[ARG:%.+]] = load ptr, ptr [[ARG_ADDR]]
 238 // CHECK-NEXT: call {{.*}} [[S1_DTOR]](ptr {{[^,]*}} [[ARG]])
 239 // CHECK-NEXT: ret void
 240 // CHECK-NEXT: }
 241 // CHECK:      define internal {{.*}}void [[GS1_INIT:@\.__omp_threadprivate_init_\..*]]()
 242 // CHECK:      call {{.*}}void @__kmpc_threadprivate_register(ptr [[DEFAULT_LOC]], ptr [[GS1]], ptr [[GS1_CTOR]], ptr null, ptr [[GS1_DTOR]])
 243 // CHECK-NEXT: ret void
 244 // CHECK-NEXT: }
 245
 246
 247
 248 // CHECK-DEBUG:      @__kmpc_global_thread_num
 249 // CHECK-DEBUG:      call {{.*}}void @__kmpc_threadprivate_register(ptr [[ID1]], ptr [[GS1]], ptr [[GS1_CTOR:@\.__kmpc_global_ctor_\..*]], ptr null, ptr [[GS1_DTOR:@\.__kmpc_global_dtor_\..*]])
 250 // CHECK-DEBUG:      define internal {{.*}}ptr [[GS1_CTOR]](ptr %0)
 251 // CHECK-DEBUG:      store ptr %0, ptr [[ARG_ADDR:%.*]],
 252 // CHECK-DEBUG:      [[ARG:%.+]] = load ptr, ptr [[ARG_ADDR]]
 253 // CHECK-DEBUG-NEXT: call {{.*}} [[S1_CTOR:@.+]](ptr {{[^,]*}} [[ARG]], {{.*}} 5){{.*}}, !dbg
 254 // CHECK-DEBUG:      [[ARG:%.+]] = load ptr, ptr [[ARG_ADDR]]
 255 // CHECK-DEBUG:      ret ptr [[ARG]]
 256 // CHECK-DEBUG-NEXT: }
 257 // CHECK-DEBUG:      define {{.*}} [[S1_CTOR]](ptr {{.*}},
 258 // CHECK-DEBUG:      define internal {{.*}}void [[GS1_DTOR]](ptr %0)
 259 // CHECK-DEBUG:      store ptr %0, ptr [[ARG_ADDR:%.*]],
 260 // CHECK-DEBUG:      [[ARG:%.+]] = load ptr, ptr [[ARG_ADDR]]
 261 // CHECK-DEBUG-NEXT: call {{.*}} [[S1_DTOR:@.+]](ptr {{[^,]*}} [[ARG]]){{.*}}, !dbg
 262 // CHECK-DEBUG-NEXT: ret void
 263 // CHECK-DEBUG-NEXT: }
 264 // CHECK-DEBUG:      define {{.*}} [[S1_DTOR]](ptr {{.*}})
 265 static S2 gs2(27);
 266 // CHECK:      define {{.*}} [[S2_CTOR:@.*]](ptr {{.*}},
 267 // CHECK:      define {{.*}} [[S2_DTOR:@.*]](ptr {{.*}})
 268 // No another call for S2 constructor because it is not threadprivate
 269 // CHECK-NOT:  call {{.*}} [[S2_CTOR]](ptr
 270 // CHECK-DEBUG:      define {{.*}} [[S2_CTOR:@.*]](ptr {{.*}},
 271 // CHECK-DEBUG:      define {{.*}} [[S2_DTOR:@.*]](ptr {{.*}})
 272 // No another call for S2 constructor because it is not threadprivate
 273 // CHECK-DEBUG-NOT:  call {{.*}} [[S2_CTOR]](ptr
 274 S1 arr_x[2][3] = { { 1, 2, 3 }, { 4, 5, 6 } };
 275 #pragma omp threadprivate(arr_x)
 276 // CHECK:      define internal {{.*}}ptr [[ARR_X_CTOR:@\.__kmpc_global_ctor_\..*]](ptr %0)
 277 // CHECK:      store ptr %0, ptr [[ARG_ADDR:%.*]],
 278 // CHECK:      [[ARG:%.+]] = load ptr, ptr [[ARG_ADDR]]
 279 // CHECK:      [[ARR1:%.*]] = getelementptr inbounds [2 x [3 x [[S1]]]], ptr [[ARG]], i{{.*}} 0, i{{.*}} 0
 280 // CHECK:      [[ARR:%.*]] = getelementptr inbounds [3 x [[S1]]], ptr [[ARR1]], i{{.*}} 0, i{{.*}} 0
 281 // CHECK:      invoke {{.*}} [[S1_CTOR]](ptr {{[^,]*}} [[ARR]], [[INT]] {{.*}}1)
 282 // CHECK:      [[ARR_ELEMENT:%.*]] = getelementptr inbounds [[S1]], ptr [[ARR]], i{{.*}} 1
 283 // CHECK:      invoke {{.*}} [[S1_CTOR]](ptr {{[^,]*}} [[ARR_ELEMENT]], [[INT]] {{.*}}2)
 284 // CHECK:      [[ARR_ELEMENT2:%.*]] = getelementptr inbounds [[S1]], ptr [[ARR_ELEMENT]], i{{.*}} 1
 285 // CHECK:      invoke {{.*}} [[S1_CTOR]](ptr {{[^,]*}} [[ARR_ELEMENT2]], [[INT]] {{.*}}3)
 286 // CHECK:      [[ARR_ELEMENT3:%.*]] = getelementptr inbounds [3 x [[S1]]], ptr [[ARR1]], i{{.*}} 1
 287 // CHECK:      [[ARR_:%.*]] = getelementptr inbounds [3 x [[S1]]], ptr [[ARR_ELEMENT3]], i{{.*}} 0, i{{.*}} 0
 288 // CHECK:      invoke {{.*}} [[S1_CTOR]](ptr {{[^,]*}} [[ARR_]], [[INT]] {{.*}}4)
 289 // CHECK:      [[ARR_ELEMENT:%.*]] = getelementptr inbounds [[S1]], ptr [[ARR_]], i{{.*}} 1
 290 // CHECK:      invoke {{.*}} [[S1_CTOR]](ptr {{[^,]*}} [[ARR_ELEMENT]], [[INT]] {{.*}}5)
 291 // CHECK:      [[ARR_ELEMENT2:%.*]] = getelementptr inbounds [[S1]], ptr [[ARR_ELEMENT]], i{{.*}} 1
 292 // CHECK:      invoke {{.*}} [[S1_CTOR]](ptr {{[^,]*}} [[ARR_ELEMENT2]], [[INT]] {{.*}}6)
 293 // CHECK:      [[ARG:%.+]] = load ptr, ptr [[ARG_ADDR]]
 294 // CHECK:      ret ptr [[ARG]]
 295 // CHECK:      }
 296 // CHECK:      define internal {{.*}}void [[ARR_X_DTOR:@\.__kmpc_global_dtor_\..*]](ptr %0)
 297 // CHECK:      store ptr %0, ptr [[ARG_ADDR:%.*]],
 298 // CHECK:      [[ARG:%.+]] = load ptr, ptr [[ARG_ADDR]]
 299 // CHECK-NEXT: [[ARR_CUR:%.*]] = getelementptr inbounds [[S1]], ptr [[ARG]], i{{.*}} 6
 300 // CHECK-NEXT: br label %[[ARR_LOOP:.*]]
 301 // CHECK:      {{.*}}[[ARR_LOOP]]{{.*}}
 302 // CHECK-NEXT: [[ARR_ELEMENTPAST:%.*]] = phi ptr [ [[ARR_CUR]], {{.*}} ], [ [[ARR_ELEMENT:%.*]], {{.*}} ]
 303 // CHECK-NEXT: [[ARR_ELEMENT:%.*]] = getelementptr inbounds [[S1]], ptr [[ARR_ELEMENTPAST]], i{{.*}} -1
 304 // CHECK-NEXT: {{call|invoke}} {{.*}} [[S1_DTOR]](ptr {{[^,]*}} [[ARR_ELEMENT]])
 305 // CHECK:      [[ARR_DONE:%.*]] = icmp eq ptr [[ARR_ELEMENT]], [[ARG]]
 306 // CHECK-NEXT: br i1 [[ARR_DONE]], label %[[ARR_EXIT:.*]], label %[[ARR_LOOP]]
 307 // CHECK:      {{.*}}[[ARR_EXIT]]{{.*}}
 308 // CHECK-NEXT: ret void
 309 // CHECK:      }
 310 // CHECK:      define internal {{.*}}void [[ARR_X_INIT:@\.__omp_threadprivate_init_\..*]]()
 311 // CHECK:      call {{.*}}void @__kmpc_threadprivate_register(ptr [[DEFAULT_LOC]], ptr [[ARR_X]], ptr [[ARR_X_CTOR]], ptr null, ptr [[ARR_X_DTOR]])
 312 // CHECK-NEXT: ret void
 313 // CHECK-NEXT: }
 314
 315
 316
 317 // CHECK-DEBUG:      @__kmpc_global_thread_num
 318 // CHECK-DEBUG:      call {{.*}}void @__kmpc_threadprivate_register(ptr [[ID2]], ptr [[ARR_X]], ptr [[ARR_X_CTOR:@\.__kmpc_global_ctor_\..*]], ptr null, ptr [[ARR_X_DTOR:@\.__kmpc_global_dtor_\..*]])
 319 // CHECK-DEBUG:      define internal {{.*}}ptr [[ARR_X_CTOR]](ptr %0)
 320 // CHECK-DEBUG:      }
 321 // CHECK-DEBUG:      define internal {{.*}}void [[ARR_X_DTOR]](ptr %0)
 322 // CHECK-DEBUG:      }
 323 extern S5 gs3;
 324 #pragma omp threadprivate(gs3)
 325 // No call for S5 constructor because gs3 has just declaration, not a definition.
 326 // CHECK-NOT:  call {{.*}}(ptr
 327 // CHECK-DEBUG-NOT:  call {{.*}}(ptr
 328
 329 template <class T>
 330 struct ST {
 331   static T st;
 332 #pragma omp threadprivate(st)
 333 };
 334
 335
 336
 337
 338
 339 // OMP50-DEBUG:      @__kmpc_global_thread_num
 340 // OMP50-DEBUG:      call {{.*}}void @__kmpc_threadprivate_register(ptr {{.*}}, ptr [[ST_S4_ST]], ptr [[ST_S4_ST_CTOR:@\.__kmpc_global_ctor_\..+]], ptr null, ptr [[ST_S4_ST_DTOR:@\.__kmpc_global_dtor_\..+]])
 341 // OMP50-DEBUG:      define internal {{.*}}ptr [[ST_S4_ST_CTOR]](ptr %0)
 342 // OMP50-DEBUG:      }
 343 // OMP50-DEBUG:      define {{.*}} [[S4_CTOR:@.*]](ptr {{.*}},
 344 // OMP50-DEBUG:      define internal {{.*}}void [[ST_S4_ST_DTOR]](ptr %0)
 345 // OMP50-DEBUG:      }
 346 // OMP50-DEBUG:      define {{.*}} [[S4_DTOR:@.*]](ptr {{.*}})
 347
 348 // OMP50:      call {{.*}}void @__kmpc_threadprivate_register(ptr [[DEFAULT_LOC]], ptr [[ST_S4_ST]], ptr [[ST_S4_ST_CTOR:@\.__kmpc_global_ctor_\..+]], ptr null, ptr [[ST_S4_ST_DTOR:@\.__kmpc_global_dtor_\..+]])
 349 // OMP50:      define internal {{.*}}ptr [[ST_S4_ST_CTOR]](ptr %0)
 350 // OMP50:      store ptr %0, ptr [[ARG_ADDR:%.*]],
 351 // OMP50:      [[ARG:%.+]] = load ptr, ptr [[ARG_ADDR]]
 352 // OMP50-NEXT: call {{.*}} [[S4_CTOR:@.+]](ptr {{[^,]*}} [[ARG]], {{.*}} 23)
 353 // OMP50:      [[ARG:%.+]] = load ptr, ptr [[ARG_ADDR]]
 354 // OMP50-NEXT: ret ptr [[ARG]]
 355 // OMP50-NEXT: }
 356 // OMP50:      define {{.*}} [[S4_CTOR]](ptr {{.*}},
 357 // OMP50:      define internal {{.*}}void [[ST_S4_ST_DTOR]](ptr %0)
 358 // OMP50:      store ptr %0, ptr [[ARG_ADDR:%.*]],
 359 // OMP50:      [[ARG:%.+]] = load ptr, ptr [[ARG_ADDR]]
 360 // OMP50-NEXT: call {{.*}} [[S4_DTOR:@.+]](ptr {{[^,]*}} [[ARG]])
 361 // OMP50-NEXT: ret void
 362 // OMP50-NEXT: }
 363 // OMP50:      define {{.*}} [[S4_DTOR]](ptr {{[^,]*}} {{.*}})
 364 template <class T>
 365 T ST<T>::st(23);
 366
 367 // CHECK-LABEL:  @main()
 368 // CHECK-DEBUG-LABEL: @main()
 369 int main() {
 370
 371   int Res;
 372   struct Smain {
 373     int a;
 374     double b, c;
 375     Smain()
 376         : a(0) {
 377     }
 378     Smain(int a)
 379         : a(a) {
 380     }
 381     Smain(const Smain &s) {
 382       a = 12 + s.a;
 383     }
 384     ~Smain() {
 385       a = 0;
 386     }
 387   };
 388
 389   static Smain sm(gs1.a);
 390 // CHECK:      [[THREAD_NUM:%.+]] = call {{.*}}i32 @__kmpc_global_thread_num(ptr [[DEFAULT_LOC]])
 391 // CHECK:      call {{.*}}i{{.*}} @__cxa_guard_acquire
 392 // CHECK:      call {{.*}}i32 @__kmpc_global_thread_num(ptr [[DEFAULT_LOC]])
 393 // CHECK:      call {{.*}}void @__kmpc_threadprivate_register(ptr [[DEFAULT_LOC]], ptr [[SM]], ptr [[SM_CTOR:@\.__kmpc_global_ctor_\..+]], ptr null, ptr [[SM_DTOR:@\.__kmpc_global_dtor_\..+]])
 394 // CHECK:      [[GS1_TEMP_ADDR:%.*]] = call {{.*}}ptr @__kmpc_threadprivate_cached(ptr [[DEFAULT_LOC]], i32 {{.*}}, ptr [[GS1]], i{{.*}} {{[0-9]+}}, ptr [[GS1]].cache.)
 395 // CHECK-NEXT: [[GS1_A_ADDR:%.*]] = getelementptr inbounds [[S1]], ptr [[GS1_TEMP_ADDR]], i{{.*}} 0, i{{.*}} 0
 396 // CHECK-NEXT: [[GS1_A:%.*]] = load [[INT]], ptr [[GS1_A_ADDR]]
 397 // CHECK-NEXT: invoke {{.*}} [[SMAIN_CTOR:.*]](ptr {{[^,]*}} [[SM]], [[INT]] {{.*}}[[GS1_A]])
 398 // CHECK:      call {{.*}}void @__cxa_guard_release
 399
 400
 401
 402 // CHECK-DEBUG:      call {{.*}}i{{.*}} @__cxa_guard_acquire
 403 // CHECK-DEBUG:      call {{.*}}i32 @__kmpc_global_thread_num(ptr [[KMPC_LOC:@.+]])
 404 // CHECK-DEBUG:      call {{.*}}void @__kmpc_threadprivate_register(ptr [[KMPC_LOC]], ptr [[SM]], ptr [[SM_CTOR:@\.__kmpc_global_ctor_\..+]], ptr null, ptr [[SM_DTOR:@\.__kmpc_global_dtor_\..+]])
 405 // CHECK-DEBUG:      [[GS1_TEMP_ADDR:%.*]] = call {{.*}}ptr @__kmpc_threadprivate_cached(ptr {{.*}}, i32 {{.*}}, ptr [[GS1]], i{{.*}} {{[0-9]+}}, ptr
 406
 407
 408 // CHECK-DEBUG-NEXT: [[GS1_A_ADDR:%.*]] = getelementptr inbounds [[S1]], ptr [[GS1_TEMP_ADDR]], i{{.*}} 0, i{{.*}} 0
 409 // CHECK-DEBUG-NEXT: [[GS1_A:%.*]] = load [[INT]], ptr [[GS1_A_ADDR]]
 410 // CHECK-DEBUG-NEXT: invoke {{.*}} [[SMAIN_CTOR:.*]](ptr {{[^,]*}} [[SM]], [[INT]] {{.*}}[[GS1_A]])
 411 // CHECK-DEBUG:      call {{.*}}void @__cxa_guard_release
 412 // CHECK-TLS:      [[IS_INIT_INT:%.*]] = load i8, ptr [[SM_GUARD]]
 413 // CHECK-TLS-NEXT: [[IS_INIT_BOOL:%.*]] = icmp eq i8 [[IS_INIT_INT]], 0
 414 // CHECK-TLS-NEXT: br i1 [[IS_INIT_BOOL]], label %[[INIT_LABEL:.*]], label %[[INIT_DONE:[^,]+]]{{.*}}
 415 // CHECK-TLS:      [[INIT_LABEL]]
 416 // CHECK-TLS-NEXT: [[GS1_ADDR:%.*]] = call ptr [[GS1_TLS_INITD:@[^,]+]]
 417 // CHECK-TLS-NEXT: [[GS1_A_ADDR:%.*]] = getelementptr inbounds [[S1]], ptr [[GS1_ADDR]], i32 0, i32 0
 418 // CHECK-TLS-NEXT: [[GS1_A_VAL:%.*]] = load i32, ptr [[GS1_A_ADDR]]
 419 // CHECK-TLS-NEXT: call void [[SM_CTOR1:@.*]](ptr {{[^,]*}} [[SM]], i32 [[GS1_A_VAL]])
 420 // CHECK-TLS-NEXT: call i32 @__cxa_thread_atexit(ptr [[SM_DTOR1:@.*]], ptr [[SM]], ptr @__dso_handle)
 421 // CHECK-TLS-NEXT: store i8 1, ptr [[SM_GUARD]]
 422 // CHECK-TLS-NEXT: br label %[[INIT_DONE]]
 423 // CHECK-TLS:      [[INIT_DONE]]
 424 #pragma omp threadprivate(sm)
 425   // CHECK:      [[STATIC_S_TEMP_ADDR:%.*]] = call {{.*}}ptr @__kmpc_threadprivate_cached(ptr [[DEFAULT_LOC]], i32 {{.*}}, ptr [[STATIC_S]], i{{.*}} {{[0-9]+}}, ptr [[STATIC_S]].cache.)
 426   // CHECK-NEXT: [[STATIC_S_A_ADDR:%.*]] = getelementptr inbounds [[S3]], ptr [[STATIC_S_TEMP_ADDR]], i{{.*}} 0, i{{.*}} 0
 427   // CHECK-NEXT: [[STATIC_S_A:%.*]] = load [[INT]], ptr [[STATIC_S_A_ADDR]]
 428   // CHECK-NEXT: store [[INT]] [[STATIC_S_A]], ptr [[RES_ADDR:[^,]+]]
 429   // CHECK-DEBUG:[[STATIC_S_TEMP_ADDR:%.*]] = call {{.*}}ptr @__kmpc_threadprivate_cached(ptr {{.*}}, i32 {{.*}}, ptr [[STATIC_S]], i{{.*}} {{[0-9]+}}, ptr
 430
 431
 432   // CHECK-DEBUG-NEXT: [[STATIC_S_A_ADDR:%.*]] = getelementptr inbounds [[S3]], ptr [[STATIC_S_TEMP_ADDR]], i{{.*}} 0, i{{.*}} 0
 433   // CHECK-DEBUG-NEXT: [[STATIC_S_A:%.*]] = load [[INT]], ptr [[STATIC_S_A_ADDR]]
 434   // CHECK-DEBUG-NEXT: store [[INT]] [[STATIC_S_A]], ptr [[RES_ADDR:[^,]+]]
 435   // CHECK-TLS:      [[STATIC_S_ADDR:%.*]] = call ptr [[STATIC_S_TLS_INITD:@[^,]+]]
 436   // CHECK-TLS-NEXT: [[STATIC_S_A_ADDR:%.*]] = getelementptr inbounds [[S3]], ptr [[STATIC_S_ADDR]], i{{.*}} 0, i{{.*}} 0
 437   // CHECK-TLS-NEXT: [[STATIC_S_A:%.*]] = load i32, ptr [[STATIC_S_A_ADDR]]
 438   // CHECK-TLS-NEXT: store i32 [[STATIC_S_A]], ptr [[RES_ADDR:[^,]+]]
 439   Res = Static::s.a;
 440   // CHECK:      [[SM_TEMP_ADDR:%.*]] = call {{.*}}ptr @__kmpc_threadprivate_cached(ptr [[DEFAULT_LOC]], i32 {{.*}}, ptr [[SM]], i{{.*}} {{[0-9]+}}, ptr [[SM]].cache.)
 441   // CHECK-NEXT: [[SM_A_ADDR:%.*]] = getelementptr inbounds [[SMAIN]], ptr [[SM_TEMP_ADDR]], i{{.*}} 0, i{{.*}} 0
 442   // CHECK-NEXT: [[SM_A:%.*]] = load [[INT]], ptr [[SM_A_ADDR]]
 443   // CHECK-NEXT: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]]
 444   // CHECK-NEXT: [[ADD:%.*]] = add {{.*}} [[INT]] [[RES]], [[SM_A]]
 445   // CHECK-NEXT: store [[INT]] [[ADD]], ptr [[RES:.+]]
 446   // CHECK-DEBUG-NEXT: [[SM_TEMP_ADDR:%.*]] = call {{.*}}ptr @__kmpc_threadprivate_cached(ptr {{.*}}, i32 {{.*}}, ptr [[SM]], i{{.*}} {{[0-9]+}}, ptr
 447
 448
 449   // CHECK-DEBUG-NEXT: [[SM_A_ADDR:%.*]] = getelementptr inbounds [[SMAIN]], ptr [[SM_TEMP_ADDR]], i{{.*}} 0, i{{.*}} 0
 450   // CHECK-DEBUG-NEXT: [[SM_A:%.*]] = load [[INT]], ptr [[SM_A_ADDR]]
 451   // CHECK-DEBUG-NEXT: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]]
 452   // CHECK-DEBUG-NEXT: [[ADD:%.*]] = add {{.*}} [[INT]] [[RES]], [[SM_A]]
 453   // CHECK-DEBUG-NEXT: store [[INT]] [[ADD]], ptr [[RES:.+]]
 454   // [[SM]] was initialized already, so it can be used directly
 455   // CHECK-TLS:      [[SM_A:%.*]] = load i32, ptr getelementptr inbounds ([[SMAIN]], ptr [[SM]], i{{.*}} 0, i{{.*}} 0)
 456   // CHECK-TLS-NEXT: [[RES:%.*]] = load i32, ptr [[RES_ADDR]]
 457   // CHECK-TLS-NEXT: [[ADD:%.*]] = add {{.*}} i32 [[RES]], [[SM_A]]
 458   // CHECK-TLS-NEXT: store i32 [[ADD]], ptr [[RES_ADDR]]
 459   Res += sm.a;
 460   // CHECK:      [[GS1_TEMP_ADDR:%.*]] = call {{.*}}ptr @__kmpc_threadprivate_cached(ptr [[DEFAULT_LOC]], i32 {{.*}}, ptr [[GS1]], i{{.*}} {{[0-9]+}}, ptr [[GS1]].cache.)
 461   // CHECK-NEXT: [[GS1_A_ADDR:%.*]] = getelementptr inbounds [[S1]], ptr [[GS1_TEMP_ADDR]], i{{.*}} 0, i{{.*}} 0
 462   // CHECK-NEXT: [[GS1_A:%.*]] = load [[INT]], ptr [[GS1_A_ADDR]]
 463   // CHECK-NEXT: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]]
 464   // CHECK-NEXT: [[ADD:%.*]] = add {{.*}} [[INT]] [[RES]], [[GS1_A]]
 465   // CHECK-NEXT: store [[INT]] [[ADD]], ptr [[RES:.+]]
 466   // CHECK-DEBUG-NEXT: [[GS1_TEMP_ADDR:%.*]] = call {{.*}}ptr @__kmpc_threadprivate_cached(ptr {{.*}}, i32 {{.*}}, ptr [[GS1]], i{{.*}} {{[0-9]+}}, ptr
 467
 468
 469   // CHECK-DEBUG-NEXT: [[GS1_A_ADDR:%.*]] = getelementptr inbounds [[S1]], ptr [[GS1_TEMP_ADDR]], i{{.*}} 0, i{{.*}} 0
 470   // CHECK-DEBUG-NEXT: [[GS1_A:%.*]] = load [[INT]], ptr [[GS1_A_ADDR]]
 471   // CHECK-DEBUG-NEXT: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]]
 472   // CHECK-DEBUG-NEXT: [[ADD:%.*]] = add {{.*}} [[INT]] [[RES]], [[GS1_A]]
 473   // CHECK-DEBUG-NEXT: store [[INT]] [[ADD]], ptr [[RES:.+]]
 474   // CHECK-TLS:      [[GS1_ADDR:%.*]] = call ptr [[GS1_TLS_INITD]]
 475   // CHECK-TLS-NEXT: [[GS1_A_ADDR:%.*]] = getelementptr inbounds [[S1]], ptr [[GS1_ADDR]], i{{.*}} 0, i{{.*}} 0
 476   // CHECK-TLS-NEXT: [[GS1_A:%.*]] = load i32, ptr [[GS1_A_ADDR]]
 477   // CHECK-TLS-NEXT: [[RES:%.*]] = load i32, ptr [[RES_ADDR]]
 478   // CHECK-TLS-NEXT: [[ADD:%.*]] = add {{.*}} i32 [[RES]], [[GS1_A]]
 479   // CHECK-TLS-NEXT: store i32 [[ADD]], ptr [[RES_ADDR]]
 480   Res += gs1.a;
 481   // CHECK:      [[GS2_A:%.*]] = load [[INT]], ptr getelementptr inbounds ([[S2]], ptr [[GS2]], i{{.*}} 0, i{{.*}} 0)
 482   // CHECK-NEXT: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]]
 483   // CHECK-NEXT: [[ADD:%.*]] = add {{.*}} [[INT]] [[RES]], [[GS2_A]]
 484   // CHECK-NEXT: store [[INT]] [[ADD]], ptr [[RES:.+]]
 485   // CHECK-DEBUG:      [[GS2_A:%.*]] = load [[INT]], ptr getelementptr inbounds ([[S2]], ptr [[GS2]], i{{.*}} 0, i{{.*}} 0)
 486   // CHECK-DEBUG-NEXT: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]]
 487   // CHECK-DEBUG-NEXT: [[ADD:%.*]] = add {{.*}} [[INT]] [[RES]], [[GS2_A]]
 488   // CHECK-DEBUG-NEXT: store [[INT]] [[ADD]], ptr [[RES:.+]]
 489   // CHECK-TLS:      [[GS2_A:%.*]] = load [[INT]], ptr getelementptr inbounds ([[S2]], ptr [[GS2]], i{{.*}} 0, i{{.*}} 0)
 490   // CHECK-TLS-NEXT: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]]
 491   // CHECK-TLS-NEXT: [[ADD:%.*]] = add {{.*}} [[INT]] [[RES]], [[GS2_A]]
 492   // CHECK-TLS-NEXT: store [[INT]] [[ADD]], ptr [[RES:.+]]
 493   Res += gs2.a;
 494   // CHECK:      [[GS3_TEMP_ADDR:%.*]] = call {{.*}}ptr @__kmpc_threadprivate_cached(ptr [[DEFAULT_LOC]], i32 {{.*}}, ptr [[GS3]], i{{.*}} {{[0-9]+}}, ptr [[GS3]].cache.)
 495   // CHECK-NEXT: [[GS3_A_ADDR:%.*]] = getelementptr inbounds [[S5]], ptr [[GS3_TEMP_ADDR]], i{{.*}} 0, i{{.*}} 0
 496   // CHECK-NEXT: [[GS3_A:%.*]] = load [[INT]], ptr [[GS3_A_ADDR]]
 497   // CHECK-NEXT: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]]
 498   // CHECK-NEXT: [[ADD:%.*]] = add {{.*}} [[INT]] [[RES]], [[GS3_A]]
 499   // CHECK-NEXT: store [[INT]] [[ADD]], ptr [[RES:.+]]
 500   // CHECK-DEBUG-NEXT: [[GS3_TEMP_ADDR:%.*]] = call {{.*}}ptr @__kmpc_threadprivate_cached(ptr {{.*}}, i32 {{.*}}, ptr [[GS3]], i{{.*}} {{[0-9]+}}, ptr
 501
 502
 503   // CHECK-DEBUG-NEXT: [[GS3_A_ADDR:%.*]] = getelementptr inbounds [[S5]], ptr [[GS3_TEMP_ADDR]], i{{.*}} 0, i{{.*}} 0
 504   // CHECK-DEBUG-NEXT: [[GS3_A:%.*]] = load [[INT]], ptr [[GS3_A_ADDR]]
 505   // CHECK-DEBUG-NEXT: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]]
 506   // CHECK-DEBUG-NEXT: [[ADD:%.*]] = add {{.*}} [[INT]] [[RES]], [[GS3_A]]
 507   // CHECK-DEBUG-NEXT: store [[INT]] [[ADD]], ptr [[RES:.+]]
 508   // CHECK-TLS:      [[GS3_ADDR:%.*]] = call ptr [[GS3_TLS_INITD:[^,]+]]
 509   // CHECK-TLS-NEXT: [[GS3_A_ADDR:%.*]] = getelementptr inbounds [[S5]], ptr [[GS3_ADDR]], i{{.*}} 0, i{{.*}} 0
 510   // CHECK-TLS-NEXT: [[GS3_A:%.*]] = load i32, ptr [[GS3_A_ADDR]]
 511   // CHECK-TLS-NEXT: [[RES:%.*]] = load i32, ptr [[RES_ADDR]]
 512   // CHECK-TLS-NEXT: [[ADD:%.*]] = add nsw i32 [[RES]], [[GS3_A]]
 513   // CHECK-TLS-NEXT: store i32 [[ADD]], ptr [[RES_ADDR]]
 514   Res += gs3.a;
 515   // CHECK:      [[ARR_X_TEMP_ADDR:%.*]] = call {{.*}}ptr @__kmpc_threadprivate_cached(ptr [[DEFAULT_LOC]], i32 {{.*}}, ptr [[ARR_X]], i{{.*}} {{[0-9]+}}, ptr [[ARR_X]].cache.)
 516   // CHECK-NEXT: [[ARR_X_1_ADDR:%.*]] = getelementptr inbounds [2 x [3 x [[S1]]]], ptr [[ARR_X_TEMP_ADDR]], i{{.*}} 0, i{{.*}} 1
 517   // CHECK-NEXT: [[ARR_X_1_1_ADDR:%.*]] = getelementptr inbounds [3 x [[S1]]], ptr [[ARR_X_1_ADDR]], i{{.*}} 0, i{{.*}} 1
 518   // CHECK-NEXT: [[ARR_X_1_1_A_ADDR:%.*]] = getelementptr inbounds [[S1]], ptr [[ARR_X_1_1_ADDR]], i{{.*}} 0, i{{.*}} 0
 519   // CHECK-NEXT: [[ARR_X_1_1_A:%.*]] = load [[INT]], ptr [[ARR_X_1_1_A_ADDR]]
 520   // CHECK-NEXT: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]]
 521   // CHECK-NEXT: [[ADD:%.*]] = add {{.*}} [[INT]] [[RES]], [[ARR_X_1_1_A]]
 522   // CHECK-NEXT: store [[INT]] [[ADD]], ptr [[RES:.+]]
 523   // CHECK-DEBUG-NEXT:      [[ARR_X_TEMP_ADDR:%.*]] = call {{.*}}ptr @__kmpc_threadprivate_cached(ptr {{.*}}, i32 {{.*}}, ptr [[ARR_X]], i{{.*}} {{[0-9]+}}, ptr
 524
 525
 526   // CHECK-DEBUG-NEXT: [[ARR_X_1_ADDR:%.*]] = getelementptr inbounds [2 x [3 x [[S1]]]], ptr [[ARR_X_TEMP_ADDR]], i{{.*}} 0, i{{.*}} 1
 527   // CHECK-DEBUG-NEXT: [[ARR_X_1_1_ADDR:%.*]] = getelementptr inbounds [3 x [[S1]]], ptr [[ARR_X_1_ADDR]], i{{.*}} 0, i{{.*}} 1
 528   // CHECK-DEBUG-NEXT: [[ARR_X_1_1_A_ADDR:%.*]] = getelementptr inbounds [[S1]], ptr [[ARR_X_1_1_ADDR]], i{{.*}} 0, i{{.*}} 0
 529   // CHECK-DEBUG-NEXT: [[ARR_X_1_1_A:%.*]] = load [[INT]], ptr [[ARR_X_1_1_A_ADDR]]
 530   // CHECK-DEBUG-NEXT: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]]
 531   // CHECK-DEBUG-NEXT: [[ADD:%.*]] = add {{.*}} [[INT]] [[RES]], [[ARR_X_1_1_A]]
 532   // CHECK-DEBUG-NEXT: store [[INT]] [[ADD]], ptr [[RES:.+]]
 533   // CHECK-TLS:       [[ARR_X_ADDR:%.*]] = call ptr [[ARR_X_TLS_INITD:[^,]+]]
 534   // CHECK-TLS-NEXT:  [[ARR_X_1_ADDR:%.*]] = getelementptr inbounds [2 x [3 x [[S1]]]], ptr [[ARR_X_ADDR]], i{{.*}} 0, i{{.*}} 1
 535   // CHECK-TLS-NEXT:  [[ARR_X_1_1_ADDR:%.*]] = getelementptr inbounds [3 x [[S1]]], ptr [[ARR_X_1_ADDR]], i{{.*}} 0, i{{.*}} 1
 536   // CHECK-TLS-NEXT:  [[ARR_X_1_1_A_ADDR:%.*]] = getelementptr inbounds [[S1]], ptr [[ARR_X_1_1_ADDR]], i{{.*}} 0, i{{.*}} 0
 537   // CHECK-TLS-NEXT:  [[ARR_X_1_1_A:%.*]] = load i32, ptr [[ARR_X_1_1_A_ADDR]]
 538   // CHECK-TLS-NEXT:  [[RES:%.*]] = load i32, ptr [[RES_ADDR]]
 539   // CHECK-TLS-NEXT:  [[ADD:%.*]] = add {{.*}} i32 [[RES]], [[ARR_X_1_1_A]]
 540   // CHECK-TLS-NEXT:  store i32 [[ADD]], ptr [[RES_ADDR]]
 541   Res += arr_x[1][1].a;
 542   // CHECK:      [[ST_INT_ST_TEMP_ADDR:%.*]] = call {{.*}}ptr @__kmpc_threadprivate_cached(ptr [[DEFAULT_LOC]], i32 {{.*}}, ptr [[ST_INT_ST]], i{{.*}} {{[0-9]+}}, ptr [[ST_INT_ST]].cache.)
 543   // CHECK-NEXT: [[ST_INT_ST_VAL:%.*]] = load [[INT]], ptr [[ST_INT_ST_TEMP_ADDR]]
 544   // CHECK-NEXT: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]]
 545   // CHECK-NEXT: [[ADD:%.*]] = add {{.*}} [[INT]] [[RES]], [[ST_INT_ST_VAL]]
 546   // CHECK-NEXT: store [[INT]] [[ADD]], ptr [[RES:.+]]
 547   // CHECK-DEBUG-NEXT: [[ST_INT_ST_TEMP_ADDR:%.*]] = call {{.*}}ptr @__kmpc_threadprivate_cached(ptr {{.*}}, i32 {{.*}}, ptr [[ST_INT_ST]], i{{.*}} {{[0-9]+}}, ptr
 548
 549
 550   // CHECK-DEBUG-NEXT: [[ST_INT_ST_VAL:%.*]] = load [[INT]], ptr [[ST_INT_ST_TEMP_ADDR]]
 551   // CHECK-DEBUG-NEXT: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]]
 552   // CHECK-DEBUG-NEXT: [[ADD:%.*]] = add {{.*}} [[INT]] [[RES]], [[ST_INT_ST_VAL]]
 553   // CHECK-DEBUG-NEXT: store [[INT]] [[ADD]], ptr [[RES:.+]]
 554   // CHECK-TLS:       [[ST_INT_ST_VAL:%.*]] = load i32, ptr [[ST_INT_ST_ADDR:[^,]+]]
 555   // CHECK-TLS-NEXT:  [[RES:%.*]] = load i32, ptr [[RES_ADDR]]
 556   // CHECK-TLS-NEXT:  [[ADD:%.*]] = add {{.*}} i32 [[RES]], [[ST_INT_ST_VAL]]
 557   // CHECK-TLS-NEXT:  store i32 [[ADD]], ptr [[RES_ADDR]]
 558   Res += ST<int>::st;
 559   // CHECK:      [[ST_FLOAT_ST_TEMP_ADDR:%.*]] = call {{.*}}ptr @__kmpc_threadprivate_cached(ptr [[DEFAULT_LOC]], i32 {{.*}}, ptr [[ST_FLOAT_ST]], i{{.*}} {{[0-9]+}}, ptr [[ST_FLOAT_ST]].cache.)
 560   // CHECK-NEXT: [[ST_FLOAT_ST_VAL:%.*]] = load float, ptr [[ST_FLOAT_ST_TEMP_ADDR]]
 561   // CHECK-NEXT: [[FLOAT_TO_INT_CONV:%.*]] = fptosi float [[ST_FLOAT_ST_VAL]] to [[INT]]
 562   // CHECK-NEXT: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]]
 563   // CHECK-NEXT: [[ADD:%.*]] = add {{.*}} [[INT]] [[RES]], [[FLOAT_TO_INT_CONV]]
 564   // CHECK-NEXT: store [[INT]] [[ADD]], ptr [[RES:.+]]
 565   // CHECK-DEBUG-NEXT: [[ST_FLOAT_ST_TEMP_ADDR:%.*]] = call {{.*}}ptr @__kmpc_threadprivate_cached(ptr {{.*}}, i32 {{.*}}, ptr [[ST_FLOAT_ST]], i{{.*}} {{[0-9]+}}, ptr
 566
 567
 568   // CHECK-DEBUG-NEXT: [[ST_FLOAT_ST_VAL:%.*]] = load float, ptr [[ST_FLOAT_ST_TEMP_ADDR]]
 569   // CHECK-DEBUG-NEXT: [[FLOAT_TO_INT_CONV:%.*]] = fptosi float [[ST_FLOAT_ST_VAL]] to [[INT]]
 570   // CHECK-DEBUG-NEXT: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]]
 571   // CHECK-DEBUG-NEXT: [[ADD:%.*]] = add {{.*}} [[INT]] [[RES]], [[FLOAT_TO_INT_CONV]]
 572   // CHECK-DEBUG-NEXT: store [[INT]] [[ADD]], ptr [[RES:.+]]
 573   // CHECK-TLS:      [[ST_FLOAT_ST_VAL:%.*]]  = load float, ptr [[ST_FLOAT_ST_ADDR:[^,]+]]
 574   // CHECK-TLS-NEXT: [[FLOAT_TO_INT_CONV:%.*]] = fptosi float [[ST_FLOAT_ST_VAL]]  to i32
 575   // CHECK-TLS-NEXT: [[RES:%.*]] = load i32, ptr [[RES_ADDR]]
 576   // CHECK-TLS-NEXT: [[ADD:%.*]] = add {{.*}} i32 [[RES]], [[FLOAT_TO_INT_CONV]]
 577   // CHECK-TLS-NEXT: store i32 [[ADD]], ptr [[RES_ADDR]]
 578   Res += static_cast<int>(ST<float>::st);
 579   // CHECK:      [[ST_S4_ST_TEMP_ADDR:%.*]] = call {{.*}}ptr @__kmpc_threadprivate_cached(ptr [[DEFAULT_LOC]], i32 {{.*}}, ptr [[ST_S4_ST]], i{{.*}} {{[0-9]+}}, ptr [[ST_S4_ST]].cache.)
 580   // CHECK-NEXT: [[ST_S4_ST_A_ADDR:%.*]] = getelementptr inbounds [[S4]], ptr [[ST_S4_ST_TEMP_ADDR]], i{{.*}} 0, i{{.*}} 0
 581   // CHECK-NEXT: [[ST_S4_ST_A:%.*]] = load [[INT]], ptr [[ST_S4_ST_A_ADDR]]
 582   // CHECK-NEXT: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]]
 583   // CHECK-NEXT: [[ADD:%.*]] = add {{.*}} [[INT]] [[RES]], [[ST_S4_ST_A]]
 584   // CHECK-NEXT: store [[INT]] [[ADD]], ptr [[RES:.+]]
 585   // CHECK-DEBUG-NEXT: [[ST_S4_ST_TEMP_ADDR:%.*]] = call {{.*}}ptr @__kmpc_threadprivate_cached(ptr {{.*}}, i32 {{.*}}, ptr [[ST_S4_ST]], i{{.*}} {{[0-9]+}}, ptr
 586
 587
 588   // CHECK-DEBUG-NEXT: [[ST_S4_ST_A_ADDR:%.*]] = getelementptr inbounds [[S4]], ptr [[ST_S4_ST_TEMP_ADDR]], i{{.*}} 0, i{{.*}} 0
 589   // CHECK-DEBUG-NEXT: [[ST_S4_ST_A:%.*]] = load [[INT]], ptr [[ST_S4_ST_A_ADDR]]
 590   // CHECK-DEBUG-NEXT: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]]
 591   // CHECK-DEBUG-NEXT: [[ADD:%.*]] = add {{.*}} [[INT]] [[RES]], [[ST_S4_ST_A]]
 592   // CHECK-DEBUG-NEXT: store [[INT]] [[ADD]], ptr [[RES:.+]]
 593   // CHECK-TLS:       [[ST_S4_ST_ADDR:%.*]] = call ptr [[ST_S4_ST_TLS_INITD:[^,]+]]
 594   // CHECK-TLS-NEXT:  [[ST_S4_ST_A_ADDR:%.*]] = getelementptr inbounds [[S4]], ptr [[ST_S4_ST_ADDR]], i{{.*}} 0, i{{.*}} 0
 595   // CHECK-TLS-NEXT:  [[ST_S4_ST_A:%.*]] = load i32, ptr [[ST_S4_ST_A_ADDR]]
 596   // CHECK-TLS-NEXT:  [[RES:%.*]] = load i32, ptr [[RES_ADDR]]
 597   // CHECK-TLS-NEXT:  [[ADD:%.*]] = add {{.*}} i32 [[RES]], [[ST_S4_ST_A]]
 598   // CHECK-TLS-NEXT:  store i32 [[ADD]], ptr [[RES_ADDR]]
 599   Res += ST<S4>::st.a;
 600   // CHECK:      [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]]
 601   // CHECK-NEXT: ret [[INT]] [[RES]]
 602   // CHECK-DEBUG:      [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]]
 603   // CHECK-DEBUG-NEXT: ret [[INT]] [[RES]]
 604   // CHECK-TLS:      [[RES:%.*]] = load i32, ptr [[RES_ADDR]]
 605   // CHECK-TLS-NEXT: ret i32 [[RES]]
 606   return Res;
 607 }
 608 // CHECK: }
 609
 610 // CHECK:      define internal {{.*}}ptr [[SM_CTOR]](ptr %0)
 611 // CHECK:      [[THREAD_NUM:%.+]] = call {{.*}}i32 @__kmpc_global_thread_num(ptr [[DEFAULT_LOC]])
 612 // CHECK:      store ptr %0, ptr [[ARG_ADDR:%.*]],
 613 // CHECK:      [[ARG:%.+]] = load ptr, ptr [[ARG_ADDR]]
 614 // CHECK:      [[GS1_TEMP_ADDR:%.*]] = call {{.*}}ptr @__kmpc_threadprivate_cached(ptr [[DEFAULT_LOC]], i32 {{.*}}, ptr [[GS1]], i{{.*}} {{[0-9]+}}, ptr [[GS1]].cache.)
 615 // CHECK-NEXT: [[GS1_A_ADDR:%.*]] = getelementptr inbounds [[S1]], ptr [[GS1_TEMP_ADDR]], i{{.*}} 0, i{{.*}} 0
 616 // CHECK-NEXT: [[GS1_A:%.*]] = load [[INT]], ptr [[GS1_A_ADDR]]
 617 // CHECK-NEXT: call {{.*}} [[SMAIN_CTOR:@.+]](ptr {{[^,]*}} [[ARG]], [[INT]] {{.*}}[[GS1_A]])
 618 // CHECK:      [[ARG:%.+]] = load ptr, ptr [[ARG_ADDR]]
 619 // CHECK-NEXT: ret ptr [[ARG]]
 620 // CHECK-NEXT: }
 621 // CHECK:      define {{.*}} [[SMAIN_CTOR]](ptr {{.*}},
 622 // CHECK:      define internal {{.*}}void [[SM_DTOR]](ptr %0)
 623 // CHECK:      store ptr %0, ptr [[ARG_ADDR:%.*]],
 624 // CHECK:      [[ARG:%.+]] = load ptr, ptr [[ARG_ADDR]]
 625 // CHECK-NEXT: call {{.*}} [[SMAIN_DTOR:@.+]](ptr {{[^,]*}} [[ARG]])
 626 // CHECK-NEXT: ret void
 627 // CHECK-NEXT: }
 628 // CHECK:      define {{.*}} [[SMAIN_DTOR]](ptr {{.*}})
 629 // CHECK-DEBUG:      define internal {{.*}}ptr [[SM_CTOR]](ptr %0)
 630 // CHECK-DEBUG:      [[THREAD_NUM:%.+]] = call {{.*}}i32 @__kmpc_global_thread_num(ptr {{.*}})
 631
 632
 633
 634 // CHECK-DEBUG:      store ptr %0, ptr [[ARG_ADDR:%.*]],
 635 // CHECK-DEBUG:      [[ARG:%.+]] = load ptr, ptr [[ARG_ADDR]]
 636 // CHECK-DEBUG:      [[GS1_TEMP_ADDR:%.*]] = call {{.*}}ptr @__kmpc_threadprivate_cached(ptr {{.*}}, i32 {{.*}}, ptr [[GS1]], i{{.*}} {{[0-9]+}}, ptr
 637
 638
 639 // CHECK-DEBUG-NEXT: [[GS1_A_ADDR:%.*]] = getelementptr inbounds [[S1]], ptr [[GS1_TEMP_ADDR]], i{{.*}} 0, i{{.*}} 0
 640 // CHECK-DEBUG-NEXT: [[GS1_A:%.*]] = load [[INT]], ptr [[GS1_A_ADDR]]
 641 // CHECK-DEBUG-NEXT: call {{.*}} [[SMAIN_CTOR:@.+]](ptr {{[^,]*}} [[ARG]], [[INT]] {{.*}}[[GS1_A]])
 642 // CHECK-DEBUG:      [[ARG:%.+]] = load ptr, ptr [[ARG_ADDR]]
 643 // CHECK-DEBUG-NEXT: ret ptr [[ARG]]
 644 // CHECK-DEBUG-NEXT: }
 645 // CHECK-DEBUG:      define {{.*}} [[SMAIN_CTOR]](ptr {{.*}},
 646 // CHECK-DEBUG:      define internal {{.*}} [[SM_DTOR:@.+]](ptr %0)
 647 // CHECK-DEBUG:      call {{.*}} [[SMAIN_DTOR:@.+]](ptr
 648 // CHECK-DEBUG:      }
 649 // CHECK-DEBUG:      define {{.*}} [[SMAIN_DTOR]](ptr {{.*}})
 650 // CHECK-TLS:      define internal ptr [[GS1_TLS_INITD]] {{#[0-9]+}} {
 651 // CHECK-TLS-NEXT: call void [[GS1_TLS_INIT]]
 652 // CHECK-TLS-NEXT: ret ptr [[GS1]]
 653 // CHECK-TLS-NEXT: }
 654 // CHECK-TLS: define internal void [[SM_CTOR1]](ptr {{[^,]*}} %this, i32 {{.*}}) {{.*}} {
 655 // CHECK-TLS: void [[SM_CTOR2:@.*]](ptr {{.*}}, i32 {{.*}})
 656 // CHECK-TLS: }
 657 // CHECK-TLS: define internal void [[SM_DTOR1]](ptr {{[^,]*}} %this) {{.*}} {
 658 // CHECK-TLS: void [[SM_DTOR2:@.*]](ptr {{.*}})
 659 // CHECK-TLS: }
 660 // CHECK-TLS: define {{.*}} ptr [[STATIC_S_TLS_INITD]]
 661 // CHECK-TLS: call void [[STATIC_S_TLS_INIT:[^,]+]]
 662 // CHECK-TLS: ret ptr [[STATIC_S]]
 663 // CHECK-TLS: }
 664 // CHECK-TLS: define {{.*}} ptr [[GS3_TLS_INITD]]
 665 // CHECK-TLS:   call void [[GS3_TLS_INIT:@[^,]+]]
 666 // CHECK-TLS:   ret ptr [[GS3]]
 667 // CHECK-TLS: }
 668 // CHECK-TLS: define {{.*}} ptr [[ARR_X_TLS_INITD]]
 669 // CHECK-TLS:   call void [[ARR_X_TLS_INIT]]
 670 // CHECK-TLS:   ret ptr [[ARR_X]]
 671 // CHECK-TLS: }
 672 // CHECK-TLS: define {{.*}} ptr [[ST_S4_ST_TLS_INITD]] {{#[0-9]+}} comdat {
 673 // CHECK-TLS:   call void [[ST_S4_ST_TLS_INIT]]
 674 // CHECK-TLS:   ret ptr [[ST_S4_ST]]
 675 // CHECK-TLS: }
 676
 677 #endif
 678 // OMP50-TLS: define {{.*}}void [[SM_CTOR2]](ptr {{.*}}, i32 {{.*}})
 679 // OMP50-TLS: define {{.*}}void [[SM_DTOR2]](ptr {{.*}})
 680
 681 #ifdef BODY
 682 // CHECK-LABEL:  @{{.*}}foobar{{.*}}()
 683 // CHECK-DEBUG-LABEL: @{{.*}}foobar{{.*}}()
 684 // CHECK-TLS-LABEL: @{{.*}}foobar{{.*}}()
 685 int foobar() {
 686
 687   int Res;
 688   // CHECK:      [[THREAD_NUM:%.+]] = call {{.*}}i32 @__kmpc_global_thread_num(ptr [[DEFAULT_LOC]])
 689   // CHECK:      [[STATIC_S_TEMP_ADDR:%.*]] = call {{.*}}ptr @__kmpc_threadprivate_cached(ptr [[DEFAULT_LOC]], i32 {{.*}}, ptr [[STATIC_S]], i{{.*}} {{[0-9]+}}, ptr [[STATIC_S]].cache.)
 690   // CHECK-NEXT: [[STATIC_S_A_ADDR:%.*]] = getelementptr inbounds [[S3]], ptr [[STATIC_S_TEMP_ADDR]], i{{.*}} 0, i{{.*}} 0
 691   // CHECK-NEXT: [[STATIC_S_A:%.*]] = load [[INT]], ptr [[STATIC_S_A_ADDR]]
 692   // CHECK-NEXT: store [[INT]] [[STATIC_S_A]], ptr [[RES_ADDR:[^,]+]]
 693   // CHECK-DEBUG:      [[THREAD_NUM:%.+]] = call {{.*}}i32 @__kmpc_global_thread_num(ptr {{.*}})
 694   // CHECK-DEBUG:      [[STATIC_S_TEMP_ADDR:%.*]] = call {{.*}}ptr @__kmpc_threadprivate_cached(ptr {{.*}}, i32 {{.*}}, ptr [[STATIC_S]], i{{.*}} {{[0-9]+}}, ptr
 695
 696
 697
 698
 699   // CHECK-DEBUG-NEXT: [[STATIC_S_A_ADDR:%.*]] = getelementptr inbounds [[S3]], ptr [[STATIC_S_TEMP_ADDR]], i{{.*}} 0, i{{.*}} 0
 700   // CHECK-DEBUG-NEXT: [[STATIC_S_A:%.*]] = load [[INT]], ptr [[STATIC_S_A_ADDR]]
 701   // CHECK-DEBUG-NEXT: store [[INT]] [[STATIC_S_A]], ptr [[RES_ADDR:[^,]+]]
 702   // CHECK-TLS:      [[STATIC_S_ADDR:%.*]]  = call ptr [[STATIC_S_TLS_INITD]]
 703   // CHECK-TLS-NEXT: [[STATIC_S_A_ADDR:%.*]] = getelementptr inbounds [[S3]], ptr [[STATIC_S_ADDR]], i{{.*}} 0, i{{.*}} 0
 704   // CHECK-TLS-NEXT: [[STATIC_S_A:%.*]] = load i32, ptr [[STATIC_S_A_ADDR]]
 705   // CHECK-TLS-NEXT: store i32 [[STATIC_S_A]], ptr [[RES_ADDR:[^,]+]]
 706   Res = Static::s.a;
 707   // CHECK:      [[GS1_TEMP_ADDR:%.*]] = call {{.*}}ptr @__kmpc_threadprivate_cached(ptr [[DEFAULT_LOC]], i32 {{.*}}, ptr [[GS1]], i{{.*}} {{[0-9]+}}, ptr [[GS1]].cache.)
 708   // CHECK-NEXT: [[GS1_A_ADDR:%.*]] = getelementptr inbounds [[S1]], ptr [[GS1_TEMP_ADDR]], i{{.*}} 0, i{{.*}} 0
 709   // CHECK-NEXT: [[GS1_A:%.*]] = load [[INT]], ptr [[GS1_A_ADDR]]
 710   // CHECK-NEXT: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]]
 711   // CHECK-NEXT: [[ADD:%.*]] = add {{.*}} [[INT]] [[RES]], [[GS1_A]]
 712   // CHECK-NEXT: store [[INT]] [[ADD]], ptr [[RES:.+]]
 713   // CHECK-DEBUG-NEXT: [[GS1_TEMP_ADDR:%.*]] = call {{.*}}ptr @__kmpc_threadprivate_cached(ptr {{.*}}, i32 {{.*}}, ptr [[GS1]], i{{.*}} {{[0-9]+}}, ptr
 714
 715
 716   // CHECK-DEBUG-NEXT: [[GS1_A_ADDR:%.*]] = getelementptr inbounds [[S1]], ptr [[GS1_TEMP_ADDR]], i{{.*}} 0, i{{.*}} 0
 717   // CHECK-DEBUG-NEXT: [[GS1_A:%.*]] = load [[INT]], ptr [[GS1_A_ADDR]]
 718   // CHECK-DEBUG-NEXT: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]]
 719   // CHECK-DEBUG-NEXT: [[ADD:%.*]] = add {{.*}} [[INT]] [[RES]], [[GS1_A]]
 720   // CHECK-DEBUG-NEXT: store [[INT]] [[ADD]], ptr [[RES:.+]]
 721   // CHECK-TLS:      [[GS1_ADDR:%.*]] = call ptr [[GS1_TLS_INITD]]
 722   // CHECK-TLS-NEXT: [[GS1_A_ADDR:%.*]] = getelementptr inbounds [[S1]], ptr [[GS1_ADDR]], i{{.*}} 0, i{{.*}} 0
 723   // CHECK-TLS-NEXT: [[GS1_A:%.*]] = load i32, ptr [[GS1_A_ADDR]]
 724   // CHECK-TLS-NEXT: [[RES:%.*]] = load i32, ptr [[RES_ADDR]]
 725   // CHECK-TLS-NEXT: [[ADD:%.*]] = add {{.*}} i32 [[RES]], [[GS1_A]]
 726   // CHECK-TLS-NEXT: store i32 [[ADD]], ptr [[RES_ADDR]]
 727   Res += gs1.a;
 728   // CHECK:      [[GS2_A:%.*]] = load [[INT]], ptr getelementptr inbounds ([[S2]], ptr [[GS2]], i{{.*}} 0, i{{.*}} 0)
 729   // CHECK-NEXT: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]]
 730   // CHECK-NEXT: [[ADD:%.*]] = add {{.*}} [[INT]] [[RES]], [[GS2_A]]
 731   // CHECK-NEXT: store [[INT]] [[ADD]], ptr [[RES:.+]]
 732   // CHECK-DEBUG:      [[GS2_A:%.*]] = load [[INT]], ptr getelementptr inbounds ([[S2]], ptr [[GS2]], i{{.*}} 0, i{{.*}} 0)
 733   // CHECK-DEBUG-NEXT: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]]
 734   // CHECK-DEBUG-NEXT: [[ADD:%.*]] = add {{.*}} [[INT]] [[RES]], [[GS2_A]]
 735   // CHECK-DEBUG-NEXT: store [[INT]] [[ADD]], ptr [[RES:.+]]
 736   // CHECK-TLS:      [[GS2_A:%.*]] = load i32, ptr getelementptr inbounds ([[S2]], ptr [[GS2]], i{{.*}} 0, i{{.*}} 0)
 737   // CHECK-TLS-NEXT: [[RES:%.*]] = load i32, ptr [[RES_ADDR]]
 738   // CHECK-TLS-NEXT: [[ADD:%.*]] = add {{.*}} i32 [[RES]], [[GS2_A]]
 739   // CHECK-TLS-NEXT: store i32 [[ADD]], ptr [[RES:.+]]
 740   Res += gs2.a;
 741   // CHECK:      [[GS3_TEMP_ADDR:%.*]] = call {{.*}}ptr @__kmpc_threadprivate_cached(ptr [[DEFAULT_LOC]], i32 {{.*}}, ptr [[GS3]], i{{.*}} {{[0-9]+}}, ptr [[GS3]].cache.)
 742   // CHECK-NEXT: [[GS3_A_ADDR:%.*]] = getelementptr inbounds [[S5]], ptr [[GS3_TEMP_ADDR]], i{{.*}} 0, i{{.*}} 0
 743   // CHECK-NEXT: [[GS3_A:%.*]] = load [[INT]], ptr [[GS3_A_ADDR]]
 744   // CHECK-NEXT: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]]
 745   // CHECK-NEXT: [[ADD:%.*]] = add {{.*}} [[INT]] [[RES]], [[GS3_A]]
 746   // CHECK-NEXT: store [[INT]] [[ADD]], ptr [[RES:.+]]
 747   // CHECK-DEBUG-NEXT: [[GS3_TEMP_ADDR:%.*]] = call {{.*}}ptr @__kmpc_threadprivate_cached(ptr {{.*}}, i32 {{.*}}, ptr [[GS3]], i{{.*}} {{[0-9]+}}, ptr
 748
 749
 750   // CHECK-DEBUG-NEXT: [[GS3_A_ADDR:%.*]] = getelementptr inbounds [[S5]], ptr [[GS3_TEMP_ADDR]], i{{.*}} 0, i{{.*}} 0
 751   // CHECK-DEBUG-NEXT: [[GS3_A:%.*]] = load [[INT]], ptr [[GS3_A_ADDR]]
 752   // CHECK-DEBUG-NEXT: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]]
 753   // CHECK-DEBUG-NEXT: [[ADD:%.*]] = add {{.*}} [[INT]] [[RES]], [[GS3_A]]
 754   // CHECK-DEBUG-NEXT: store [[INT]] [[ADD]], ptr [[RES:.+]]
 755   // CHECK-TLS:       [[GS3_ADDR:%.*]] = call ptr [[GS3_TLS_INITD]]
 756   // CHECK-TLS-DEBUG: [[GS3_A_ADDR:%.*]] = getelementptr inbounds [[S5]], ptr [[GS3_ADDR]], i{{.*}} 0, i{{.*}} 0
 757   // CHECK-TLS-DEBUG: [[GS3_A:%.*]] = load i32, ptr [[GS3_A_ADDR]]
 758   // CHECK-TLS-DEBUG: [[RES:%.*]] = load i32, ptr [[RES_ADDR]]
 759   // CHECK-TLS-DEBUG: [[ADD:%.*]]= add nsw i32 [[RES]], [[GS3_A]]
 760   // CHECK-TLS-DEBUG: store i32 [[ADD]], ptr [[RES_ADDR]]
 761   Res += gs3.a;
 762   // CHECK:      [[ARR_X_TEMP_ADDR:%.*]] = call {{.*}}ptr @__kmpc_threadprivate_cached(ptr [[DEFAULT_LOC]], i32 {{.*}}, ptr [[ARR_X]], i{{.*}} {{[0-9]+}}, ptr [[ARR_X]].cache.)
 763   // CHECK-NEXT: [[ARR_X_1_ADDR:%.*]] = getelementptr inbounds [2 x [3 x [[S1]]]], ptr [[ARR_X_TEMP_ADDR]], i{{.*}} 0, i{{.*}} 1
 764   // CHECK-NEXT: [[ARR_X_1_1_ADDR:%.*]] = getelementptr inbounds [3 x [[S1]]], ptr [[ARR_X_1_ADDR]], i{{.*}} 0, i{{.*}} 1
 765   // CHECK-NEXT: [[ARR_X_1_1_A_ADDR:%.*]] = getelementptr inbounds [[S1]], ptr [[ARR_X_1_1_ADDR]], i{{.*}} 0, i{{.*}} 0
 766   // CHECK-NEXT: [[ARR_X_1_1_A:%.*]] = load [[INT]], ptr [[ARR_X_1_1_A_ADDR]]
 767   // CHECK-NEXT: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]]
 768   // CHECK-NEXT: [[ADD:%.*]] = add {{.*}} [[INT]] [[RES]], [[ARR_X_1_1_A]]
 769   // CHECK-NEXT: store [[INT]] [[ADD]], ptr [[RES:.+]]
 770   // CHECK-DEBUG-NEXT:      [[ARR_X_TEMP_ADDR:%.*]] = call {{.*}}ptr @__kmpc_threadprivate_cached(ptr {{.*}}, i32 {{.*}}, ptr [[ARR_X]], i{{.*}} {{[0-9]+}}, ptr
 771
 772
 773   // CHECK-DEBUG-NEXT: [[ARR_X_1_ADDR:%.*]] = getelementptr inbounds [2 x [3 x [[S1]]]], ptr [[ARR_X_TEMP_ADDR]], i{{.*}} 0, i{{.*}} 1
 774   // CHECK-DEBUG-NEXT: [[ARR_X_1_1_ADDR:%.*]] = getelementptr inbounds [3 x [[S1]]], ptr [[ARR_X_1_ADDR]], i{{.*}} 0, i{{.*}} 1
 775   // CHECK-DEBUG-NEXT: [[ARR_X_1_1_A_ADDR:%.*]] = getelementptr inbounds [[S1]], ptr [[ARR_X_1_1_ADDR]], i{{.*}} 0, i{{.*}} 0
 776   // CHECK-DEBUG-NEXT: [[ARR_X_1_1_A:%.*]] = load [[INT]], ptr [[ARR_X_1_1_A_ADDR]]
 777   // CHECK-DEBUG-NEXT: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]]
 778   // CHECK-DEBUG-NEXT: [[ADD:%.*]] = add {{.*}} [[INT]] [[RES]], [[ARR_X_1_1_A]]
 779   // CHECK-DEBUG-NEXT: store [[INT]] [[ADD]], ptr [[RES:.+]]
 780   // CHECK-TLS:      [[ARR_X_ADDR:%.*]] = call ptr [[ARR_X_TLS_INITD]]
 781   // CHECK-TLS-NEXT: [[ARR_X_1_ADDR:%.*]] = getelementptr inbounds [2 x [3 x [[S1]]]], ptr [[ARR_X_ADDR]], i{{.*}} 0, i{{.*}} 1
 782   // CHECK-TLS-NEXT: [[ARR_X_1_1_ADDR:%.*]] = getelementptr inbounds [3 x [[S1]]], ptr [[ARR_X_1_ADDR]], i{{.*}} 0, i{{.*}} 1
 783   // CHECK-TLS-NEXT: [[ARR_X_1_1_A_ADDR:%.*]] = getelementptr inbounds [[S1]], ptr [[ARR_X_1_1_ADDR]], i{{.*}} 0, i{{.*}} 0
 784   // CHECK-TLS-NEXT: [[ARR_X_1_1_A:%.*]] = load [[INT]], ptr [[ARR_X_1_1_A_ADDR]]
 785   // CHECK-TLS-NEXT: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]]
 786   // CHECK-TLS-NEXT: [[ADD:%.*]] = add {{.*}} [[INT]] [[RES]], [[ARR_X_1_1_A]]
 787   // CHECK-TLS-NEXT: store [[INT]] [[ADD]], ptr [[RES:.+]]
 788   Res += arr_x[1][1].a;
 789   // CHECK:      [[ST_INT_ST_TEMP_ADDR:%.*]] = call {{.*}}ptr @__kmpc_threadprivate_cached(ptr [[DEFAULT_LOC]], i32 {{.*}}, ptr [[ST_INT_ST]], i{{.*}} {{[0-9]+}}, ptr [[ST_INT_ST]].cache.)
 790   // CHECK-NEXT: [[ST_INT_ST_VAL:%.*]] = load [[INT]], ptr [[ST_INT_ST_TEMP_ADDR]]
 791   // CHECK-NEXT: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]]
 792   // CHECK-NEXT: [[ADD:%.*]] = add {{.*}} [[INT]] [[RES]], [[ST_INT_ST_VAL]]
 793   // CHECK-NEXT: store [[INT]] [[ADD]], ptr [[RES:.+]]
 794   // CHECK-DEBUG-NEXT: [[ST_INT_ST_TEMP_ADDR:%.*]] = call {{.*}}ptr @__kmpc_threadprivate_cached(ptr {{.*}}, i32 {{.*}}, ptr [[ST_INT_ST]], i{{.*}} {{[0-9]+}}, ptr
 795
 796
 797   // CHECK-DEBUG-NEXT: [[ST_INT_ST_VAL:%.*]] = load [[INT]], ptr [[ST_INT_ST_TEMP_ADDR]]
 798   // CHECK-DEBUG-NEXT: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]]
 799   // CHECK-DEBUG-NEXT: [[ADD:%.*]] = add {{.*}} [[INT]] [[RES]], [[ST_INT_ST_VAL]]
 800   // CHECK-DEBUG-NEXT: store [[INT]] [[ADD]], ptr [[RES:.+]]
 801   // OMP45-TLS:      [[ST_INT_ST_VAL:%.*]] = load [[INT]], ptr [[ST_INT_ST_ADDR:[^,]+]]
 802   // OMP45-TLS-NEXT: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]]
 803   // OMP45-TLS-NEXT: [[ADD:%.*]] = add {{.*}} [[INT]] [[RES]], [[ST_INT_ST_VAL]]
 804   // OMP45-TLS-NEXT: store [[INT]] [[ADD]], ptr [[RES:.+]]
 805   Res += ST<int>::st;
 806   // CHECK:      [[ST_FLOAT_ST_TEMP_ADDR:%.*]] = call {{.*}}ptr @__kmpc_threadprivate_cached(ptr [[DEFAULT_LOC]], i32 {{.*}}, ptr [[ST_FLOAT_ST]], i{{.*}} {{[0-9]+}}, ptr [[ST_FLOAT_ST]].cache.)
 807   // CHECK-NEXT: [[ST_FLOAT_ST_VAL:%.*]] = load float, ptr [[ST_FLOAT_ST_TEMP_ADDR]]
 808   // CHECK-NEXT: [[FLOAT_TO_INT_CONV:%.*]] = fptosi float [[ST_FLOAT_ST_VAL]] to [[INT]]
 809   // CHECK-NEXT: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]]
 810   // CHECK-NEXT: [[ADD:%.*]] = add {{.*}} [[INT]] [[RES]], [[FLOAT_TO_INT_CONV]]
 811   // CHECK-NEXT: store [[INT]] [[ADD]], ptr [[RES:.+]]
 812   // CHECK-DEBUG-NEXT: [[ST_FLOAT_ST_TEMP_ADDR:%.*]] = call {{.*}}ptr @__kmpc_threadprivate_cached(ptr {{.*}}, i32 {{.*}}, ptr [[ST_FLOAT_ST]], i{{.*}} {{[0-9]+}}, ptr
 813
 814
 815   // CHECK-DEBUG-NEXT: [[ST_FLOAT_ST_VAL:%.*]] = load float, ptr [[ST_FLOAT_ST_TEMP_ADDR]]
 816   // CHECK-DEBUG-NEXT: [[FLOAT_TO_INT_CONV:%.*]] = fptosi float [[ST_FLOAT_ST_VAL]] to [[INT]]
 817   // CHECK-DEBUG-NEXT: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]]
 818   // CHECK-DEBUG-NEXT: [[ADD:%.*]] = add {{.*}} [[INT]] [[RES]], [[FLOAT_TO_INT_CONV]]
 819   // CHECK-DEBUG-NEXT: store [[INT]] [[ADD]], ptr [[RES:.+]]
 820   // OMP45-TLS:      [[ST_FLOAT_ST_VAL:%.*]] = load float, ptr [[ST_FLOAT_ST_ADDR:[^,]+]]
 821   // OMP45-TLS-NEXT: [[FLOAT_TO_INT_CONV:%.*]] = fptosi float [[ST_FLOAT_ST_VAL]] to [[INT]]
 822   // OMP45-TLS-NEXT: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]]
 823   // OMP45-TLS-NEXT: [[ADD:%.*]] = add {{.*}} [[INT]] [[RES]], [[FLOAT_TO_INT_CONV]]
 824   // OMP45-TLS-NEXT: store [[INT]] [[ADD]], ptr [[RES:.+]]
 825   Res += static_cast<int>(ST<float>::st);
 826   // CHECK:      [[ST_S4_ST_TEMP_ADDR:%.*]] = call {{.*}}ptr @__kmpc_threadprivate_cached(ptr [[DEFAULT_LOC]], i32 {{.*}}, ptr [[ST_S4_ST]], i{{.*}} {{[0-9]+}}, ptr [[ST_S4_ST]].cache.)
 827   // CHECK-NEXT: [[ST_S4_ST_A_ADDR:%.*]] = getelementptr inbounds [[S4]], ptr [[ST_S4_ST_TEMP_ADDR]], i{{.*}} 0, i{{.*}} 0
 828   // CHECK-NEXT: [[ST_S4_ST_A:%.*]] = load [[INT]], ptr [[ST_S4_ST_A_ADDR]]
 829   // CHECK-NEXT: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]]
 830   // CHECK-NEXT: [[ADD:%.*]] = add {{.*}} [[INT]] [[RES]], [[ST_S4_ST_A]]
 831   // CHECK-NEXT: store [[INT]] [[ADD]], ptr [[RES:.+]]
 832   // CHECK-DEBUG-NEXT: [[ST_S4_ST_TEMP_ADDR:%.*]] = call {{.*}}ptr @__kmpc_threadprivate_cached(ptr {{.*}}, i32 {{.*}}, ptr [[ST_S4_ST]], i{{.*}} {{[0-9]+}}, ptr
 833
 834
 835   // CHECK-DEBUG-NEXT: [[ST_S4_ST_A_ADDR:%.*]] = getelementptr inbounds [[S4]], ptr [[ST_S4_ST_TEMP_ADDR]], i{{.*}} 0, i{{.*}} 0
 836   // CHECK-DEBUG-NEXT: [[ST_S4_ST_A:%.*]] = load [[INT]], ptr [[ST_S4_ST_A_ADDR]]
 837   // CHECK-DEBUG-NEXT: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]]
 838   // CHECK-DEBUG-NEXT: [[ADD:%.*]] = add {{.*}} [[INT]] [[RES]], [[ST_S4_ST_A]]
 839   // CHECK-DEBUG-NEXT: store [[INT]] [[ADD]], ptr [[RES:.+]]
 840   // CHECK-TLS:      [[ST_S4_ST_ADDR:%.*]] = call ptr [[ST_S4_ST_TLS_INITD]]
 841   // CHECK-TLS-NEXT: [[ST_S4_ST_A_ADDR:%.*]] = getelementptr inbounds [[S4]], ptr [[ST_S4_ST_ADDR]], i{{.*}} 0, i{{.*}} 0
 842   // CHECK-TLS-NEXT: [[ST_S4_ST_A:%.*]] = load [[INT]], ptr [[ST_S4_ST_A_ADDR]]
 843   // CHECK-TLS-NEXT: [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]]
 844   // CHECK-TLS-NEXT: [[ADD:%.*]] = add {{.*}} [[INT]] [[RES]], [[ST_S4_ST_A]]
 845   // CHECK-TLS-NEXT: store [[INT]] [[ADD]], ptr [[RES:.+]]
 846   Res += ST<S4>::st.a;
 847   // CHECK:      [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]]
 848   // CHECK-NEXT: ret [[INT]] [[RES]]
 849   // CHECK-DEBUG:      [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]]
 850   // CHECK-DEBUG-NEXT: ret [[INT]] [[RES]]
 851   // CHECK-TLS:      [[RES:%.*]] = load [[INT]], ptr [[RES_ADDR]]
 852   // CHECK-TLS-NEXT: ret [[INT]] [[RES]]
 853   return Res;
 854 }
 855 #endif
 856
 857 // OMP45:      call {{.*}}void @__kmpc_threadprivate_register(ptr [[DEFAULT_LOC]], ptr [[ST_S4_ST]], ptr [[ST_S4_ST_CTOR:@\.__kmpc_global_ctor_\..+]], ptr null, ptr [[ST_S4_ST_DTOR:@\.__kmpc_global_dtor_\..+]])
 858 // OMP45:      define internal {{.*}}ptr [[ST_S4_ST_CTOR]](ptr %0)
 859 // OMP45:      store ptr %0, ptr [[ARG_ADDR:%.*]],
 860 // OMP45:      [[ARG:%.+]] = load ptr, ptr [[ARG_ADDR]]
 861 // OMP45-NEXT: call {{.*}} [[S4_CTOR:@.+]](ptr {{[^,]*}} [[ARG]], {{.*}} 23)
 862 // OMP45:      [[ARG:%.+]] = load ptr, ptr [[ARG_ADDR]]
 863 // OMP45-NEXT: ret ptr [[ARG]]
 864 // OMP45-NEXT: }
 865 // OMP45:      define {{.*}} [[S4_CTOR]](ptr {{.*}},
 866 // OMP45:      define internal {{.*}}void [[ST_S4_ST_DTOR]](ptr %0)
 867 // OMP45:      store ptr %0, ptr [[ARG_ADDR:%.*]],
 868 // OMP45:      [[ARG:%.+]] = load ptr, ptr [[ARG_ADDR]]
 869 // OMP45-NEXT: call {{.*}} [[S4_DTOR:@.+]](ptr {{[^,]*}} [[ARG]])
 870 // OMP45-NEXT: ret void
 871 // OMP45-NEXT: }
 872 // OMP45:      define {{.*}} [[S4_DTOR]](ptr {{.*}})
 873
 874
 875
 876
 877 // OMP45-DEBUG:      @__kmpc_global_thread_num
 878 // OMP45-DEBUG:      call {{.*}}void @__kmpc_threadprivate_register(ptr {{.*}}, ptr [[ST_S4_ST]], ptr [[ST_S4_ST_CTOR:@\.__kmpc_global_ctor_\..+]], ptr null, ptr [[ST_S4_ST_DTOR:@\.__kmpc_global_dtor_\..+]])
 879 // OMP45-DEBUG:      define internal {{.*}}ptr [[ST_S4_ST_CTOR]](ptr %0)
 880 // OMP45-DEBUG:      }
 881 // OMP45-DEBUG:      define {{.*}} [[S4_CTOR:@.*]](ptr {{.*}},
 882 // OMP45-DEBUG:      define internal {{.*}}void [[ST_S4_ST_DTOR]](ptr %0)
 883 // OMP45-DEBUG:      }
 884 // OMP45-DEBUG:      define {{.*}} [[S4_DTOR:@.*]](ptr {{.*}})
 885
 886 // CHECK:      define internal {{.*}}void {{@.*}}()
 887 // CHECK-DAG:  call {{.*}}void [[GS1_INIT]]()
 888 // CHECK-DAG:  call {{.*}}void [[ARR_X_INIT]]()
 889 // CHECK:      ret void
 890 // CHECK-DEBUG:      define internal {{.*}}void {{@.*}}()
 891 // CHECK-DEBUG:      ret void
 892
 893 // OMP45-TLS: define internal void [[GS1_CXX_INIT:@.*]]()
 894 // OMP45-TLS: call void [[GS1_CTOR1:@.*]](ptr {{[^,]*}} [[GS1]], i32 5)
 895 // OMP45-TLS: call i32 @__cxa_thread_atexit(ptr [[GS1_DTOR1:.*]], ptr [[GS1]]
 896 // OMP45-TLS: }
 897 // OMP45-TLS: define {{.*}}void [[GS1_CTOR1]](ptr {{.*}}, i32 {{.*}})
 898 // OMP45-TLS: call void [[GS1_CTOR2:@.*]](ptr {{.*}}, i32 {{.*}})
 899 // OMP45-TLS: }
 900 // OMP45-TLS: define {{.*}}void [[GS1_DTOR1]](ptr {{.*}})
 901 // OMP45-TLS: call void [[GS1_DTOR2:@.*]](ptr {{.*}})
 902 // OMP45-TLS: }
 903 // OMP45-TLS: define {{.*}}void [[GS1_CTOR2]](ptr {{.*}}, i32 {{.*}})
 904 // OMP45-TLS: define {{.*}}void [[GS1_DTOR2]](ptr {{.*}})
 905
 906 // OMP45-TLS: define internal void [[GS2_CXX_INIT:@.*]]()
 907 // OMP45-TLS: call void [[GS2_CTOR1:@.*]](ptr {{[^,]*}} [[GS2]], i32 27)
 908 // OMP45-TLS: call i32 @__cxa_atexit(ptr [[GS2_DTOR1:.*]], ptr [[GS2]]
 909 // OMP45-TLS: }
 910 // OMP45-TLS: define {{.*}}void [[GS2_CTOR1]](ptr {{.*}}, i32 {{.*}})
 911 // OMP45-TLS: call void [[GS2_CTOR2:@.*]](ptr {{.*}}, i32 {{.*}})
 912 // OMP45-TLS: }
 913 // OMP45-TLS: define {{.*}}void [[GS2_DTOR1]](ptr {{.*}})
 914 // OMP45-TLS: call void [[GS2_DTOR2:@.*]](ptr {{.*}})
 915 // OMP45-TLS: }
 916 // OMP45-TLS: define {{.*}}void [[GS2_CTOR2]](ptr {{.*}}, i32 {{.*}})
 917 // OMP45-TLS: define {{.*}}void [[GS2_DTOR2]](ptr {{.*}})
 918
 919 // OMP45-TLS: define internal void [[ARR_X_CXX_INIT:@.*]]()
 920 // OMP45-TLS: invoke void [[GS1_CTOR1]](ptr {{[^,]*}} getelementptr inbounds ([2 x [3 x [[S1]]]], ptr [[ARR_X]], i{{.*}} 0, i{{.*}} 0, i{{.*}} 0), i{{.*}} 1)
 921 // OMP45-TLS: invoke void [[GS1_CTOR1]](ptr {{[^,]*}} getelementptr inbounds ([2 x [3 x [[S1]]]], ptr [[ARR_X]], i{{.*}} 0, i{{.*}} 0, i{{.*}} 1), i{{.*}} 2)
 922 // OMP45-TLS: invoke void [[GS1_CTOR1]](ptr {{[^,]*}} getelementptr inbounds ([2 x [3 x [[S1]]]], ptr [[ARR_X]], i{{.*}} 0, i{{.*}} 0, i{{.*}} 2), i{{.*}} 3)
 923 // OMP45-TLS: invoke void [[GS1_CTOR1]](ptr {{[^,]*}} getelementptr inbounds ([2 x [3 x [[S1]]]], ptr [[ARR_X]], i{{.*}} 0, i{{.*}} 1, i{{.*}} 0), i{{.*}} 4)
 924 // OMP45-TLS: invoke void [[GS1_CTOR1]](ptr {{[^,]*}} getelementptr inbounds ([2 x [3 x [[S1]]]], ptr [[ARR_X]], i{{.*}} 0, i{{.*}} 1, i{{.*}} 1), i{{.*}} 5)
 925 // OMP45-TLS: invoke void [[GS1_CTOR1]](ptr {{[^,]*}} getelementptr inbounds ([2 x [3 x [[S1]]]], ptr [[ARR_X]], i{{.*}} 0, i{{.*}} 1, i{{.*}} 2), i{{.*}} 6)
 926 // OMP45-TLS: call i32 @__cxa_thread_atexit(ptr [[ARR_X_CXX_DTOR:@[^,]+]]
 927 // OMP45-TLS: define internal void [[ARR_X_CXX_DTOR]](ptr %0)
 928 // OMP45-TLS: void [[GS1_DTOR1]](ptr {{.*}})
 929
 930 // OMP45-TLS: define {{.*}}void [[SM_CTOR2]](ptr {{.*}}, i32 {{.*}})
 931 // OMP45-TLS: define {{.*}}void [[SM_DTOR2]](ptr {{.*}})
 932
 933 // OMP45-TLS: define internal void [[ST_S4_ST_CXX_INIT]]()
 934 // OMP45-TLS: call void [[ST_S4_ST_CTOR1:@.*]](ptr {{[^,]*}} [[ST_S4_ST]], i32 23)
 935 // OMP45-TLS: call i32 @__cxa_thread_atexit(ptr [[ST_S4_ST_DTOR1:.*]], ptr [[ST_S4_ST]]
 936 // OMP45-TLS: }
 937 // OMP45-TLS: define {{.*}}void [[ST_S4_ST_CTOR1]](ptr {{.*}}, i32 {{.*}})
 938 // OMP45-TLS: call void [[ST_S4_ST_CTOR2:@.*]](ptr {{.*}}, i32 {{.*}})
 939 // OMP45-TLS: }
 940 // OMP45-TLS: define {{.*}}void [[ST_S4_ST_DTOR1]](ptr {{.*}})
 941 // OMP45-TLS: call void [[ST_S4_ST_DTOR2:@.*]](ptr {{.*}})
 942 // OMP45-TLS: }
 943 // OMP45-TLS: define {{.*}}void [[ST_S4_ST_CTOR2]](ptr {{.*}}, i32 {{.*}})
 944 // OMP45-TLS: define {{.*}}void [[ST_S4_ST_DTOR2]](ptr {{.*}})
 945
 946 // OMP50-TLS: define internal void [[ST_S4_ST_CXX_INIT]]()
 947 // OMP50-TLS: call void [[ST_S4_ST_CTOR1:@.*]](ptr {{[^,]*}} [[ST_S4_ST]], i32 23)
 948
 949 // OMP50-TLS: call i32 @__cxa_thread_atexit(ptr [[ST_S4_ST_DTOR1:.*]], ptr [[ST_S4_ST]]
 950 // OMP50-TLS: }
 951 // OMP50-TLS: define {{.*}}void [[ST_S4_ST_CTOR1]](ptr {{.*}}, i32 {{.*}})
 952 // OMP50-TLS: call void [[ST_S4_ST_CTOR2:@.*]](ptr {{.*}}, i32 {{.*}})
 953 // OMP50-TLS: }
 954 // OMP50-TLS: define {{.*}}void [[ST_S4_ST_DTOR1]](ptr {{.*}})
 955 // OMP50-TLS: call void [[ST_S4_ST_DTOR2:@.*]](ptr {{.*}})
 956 // OMP50-TLS: }
 957 // OMP50-TLS: define {{.*}}void [[ST_S4_ST_CTOR2]](ptr {{.*}}, i32 {{.*}})
 958 // OMP50-TLS: define {{.*}}void [[ST_S4_ST_DTOR2]](ptr {{.*}})
 959
 960 // CHECK-TLS:      define internal void @__tls_init()
 961 // CHECK-TLS:      [[GRD:%.*]] = load i8, ptr @__tls_guard
 962 // CHECK-TLS-NEXT: [[IS_INIT:%.*]] = icmp eq i8 [[GRD]], 0
 963 // CHECK-TLS-NEXT: br i1 [[IS_INIT]], label %[[INIT_LABEL:[^,]+]], label %[[DONE_LABEL:[^,]+]]{{.*}}
 964 // CHECK-TLS:      [[INIT_LABEL]]
 965 // CHECK-TLS-NEXT: store i8 1, ptr @__tls_guard
 966 // CHECK-TLS:      call void [[GS1_CXX_INIT]]
 967 // CHECK-TLS-NOT:  call void [[GS2_CXX_INIT]]
 968 // CHECK-TLS:      call void [[ARR_X_CXX_INIT]]
 969 // CHECK-TLS-NOT:  call void [[ST_S4_ST_CXX_INIT]]
 970 // CHECK-TLS:      [[DONE_LABEL]]
 971
 972 // CHECK-TLS-DAG:      declare {{.*}} void [[GS3_TLS_INIT]]
 973 // CHECK-TLS-DAG:      declare {{.*}} void [[STATIC_S_TLS_INIT]]
 974 // CHECK1-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_.
 975 // CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0:[0-9]+]] {
 976 // CHECK1-NEXT:  entry:
 977 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
 978 // CHECK1-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
 979 // CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8
 980 // CHECK1-NEXT:    call void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[TMP1]], i32 noundef 5)
 981 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8
 982 // CHECK1-NEXT:    ret ptr [[TMP2]]
 983 //
 984 //
 985 // CHECK1-LABEL: define {{[^@]+}}@_ZN2S1C1Ei
 986 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
 987 // CHECK1-NEXT:  entry:
 988 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
 989 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
 990 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
 991 // CHECK1-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
 992 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
 993 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
 994 // CHECK1-NEXT:    call void @_ZN2S1C2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])
 995 // CHECK1-NEXT:    ret void
 996 //
 997 //
 998 // CHECK1-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_.
 999 // CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {
1000 // CHECK1-NEXT:  entry:
1001 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
1002 // CHECK1-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
1003 // CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8
1004 // CHECK1-NEXT:    call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP1]]) #[[ATTR3:[0-9]+]]
1005 // CHECK1-NEXT:    ret void
1006 //
1007 //
1008 // CHECK1-LABEL: define {{[^@]+}}@_ZN2S1D1Ev
1009 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 {
1010 // CHECK1-NEXT:  entry:
1011 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1012 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1013 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1014 // CHECK1-NEXT:    call void @_ZN2S1D2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]]
1015 // CHECK1-NEXT:    ret void
1016 //
1017 //
1018 // CHECK1-LABEL: define {{[^@]+}}@.__omp_threadprivate_init_.
1019 // CHECK1-SAME: () #[[ATTR0]] {
1020 // CHECK1-NEXT:  entry:
1021 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
1022 // CHECK1-NEXT:    call void @__kmpc_threadprivate_register(ptr @[[GLOB1]], ptr @_ZL3gs1, ptr @.__kmpc_global_ctor_., ptr null, ptr @.__kmpc_global_dtor_.)
1023 // CHECK1-NEXT:    ret void
1024 //
1025 //
1026 // CHECK1-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_..1
1027 // CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] personality ptr @__gxx_personality_v0 {
1028 // CHECK1-NEXT:  entry:
1029 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
1030 // CHECK1-NEXT:    [[ARRAYINIT_ENDOFINIT:%.*]] = alloca ptr, align 8
1031 // CHECK1-NEXT:    [[ARRAYINIT_ENDOFINIT2:%.*]] = alloca ptr, align 8
1032 // CHECK1-NEXT:    [[EXN_SLOT:%.*]] = alloca ptr, align 8
1033 // CHECK1-NEXT:    [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4
1034 // CHECK1-NEXT:    [[ARRAYINIT_ENDOFINIT9:%.*]] = alloca ptr, align 8
1035 // CHECK1-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
1036 // CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8
1037 // CHECK1-NEXT:    [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP1]], i64 0, i64 0
1038 // CHECK1-NEXT:    store ptr [[ARRAYINIT_BEGIN]], ptr [[ARRAYINIT_ENDOFINIT]], align 8
1039 // CHECK1-NEXT:    [[ARRAYINIT_BEGIN1:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYINIT_BEGIN]], i64 0, i64 0
1040 // CHECK1-NEXT:    store ptr [[ARRAYINIT_BEGIN1]], ptr [[ARRAYINIT_ENDOFINIT2]], align 8
1041 // CHECK1-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN1]], i32 noundef 1)
1042 // CHECK1-NEXT:    to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]]
1043 // CHECK1:       invoke.cont:
1044 // CHECK1-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[ARRAYINIT_BEGIN1]], i64 1
1045 // CHECK1-NEXT:    store ptr [[ARRAYINIT_ELEMENT]], ptr [[ARRAYINIT_ENDOFINIT2]], align 8
1046 // CHECK1-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)
1047 // CHECK1-NEXT:    to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]]
1048 // CHECK1:       invoke.cont3:
1049 // CHECK1-NEXT:    [[ARRAYINIT_ELEMENT4:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYINIT_ELEMENT]], i64 1
1050 // CHECK1-NEXT:    store ptr [[ARRAYINIT_ELEMENT4]], ptr [[ARRAYINIT_ENDOFINIT2]], align 8
1051 // CHECK1-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT4]], i32 noundef 3)
1052 // CHECK1-NEXT:    to label [[INVOKE_CONT5:%.*]] unwind label [[LPAD]]
1053 // CHECK1:       invoke.cont5:
1054 // CHECK1-NEXT:    [[ARRAYINIT_ELEMENT7:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYINIT_BEGIN]], i64 1
1055 // CHECK1-NEXT:    store ptr [[ARRAYINIT_ELEMENT7]], ptr [[ARRAYINIT_ENDOFINIT]], align 8
1056 // CHECK1-NEXT:    [[ARRAYINIT_BEGIN8:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYINIT_ELEMENT7]], i64 0, i64 0
1057 // CHECK1-NEXT:    store ptr [[ARRAYINIT_BEGIN8]], ptr [[ARRAYINIT_ENDOFINIT9]], align 8
1058 // CHECK1-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN8]], i32 noundef 4)
1059 // CHECK1-NEXT:    to label [[INVOKE_CONT11:%.*]] unwind label [[LPAD10:%.*]]
1060 // CHECK1:       invoke.cont11:
1061 // CHECK1-NEXT:    [[ARRAYINIT_ELEMENT12:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYINIT_BEGIN8]], i64 1
1062 // CHECK1-NEXT:    store ptr [[ARRAYINIT_ELEMENT12]], ptr [[ARRAYINIT_ENDOFINIT9]], align 8
1063 // CHECK1-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT12]], i32 noundef 5)
1064 // CHECK1-NEXT:    to label [[INVOKE_CONT13:%.*]] unwind label [[LPAD10]]
1065 // CHECK1:       invoke.cont13:
1066 // CHECK1-NEXT:    [[ARRAYINIT_ELEMENT14:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYINIT_ELEMENT12]], i64 1
1067 // CHECK1-NEXT:    store ptr [[ARRAYINIT_ELEMENT14]], ptr [[ARRAYINIT_ENDOFINIT9]], align 8
1068 // CHECK1-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT14]], i32 noundef 6)
1069 // CHECK1-NEXT:    to label [[INVOKE_CONT15:%.*]] unwind label [[LPAD10]]
1070 // CHECK1:       invoke.cont15:
1071 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8
1072 // CHECK1-NEXT:    ret ptr [[TMP2]]
1073 // CHECK1:       lpad:
1074 // CHECK1-NEXT:    [[TMP3:%.*]] = landingpad { ptr, i32 }
1075 // CHECK1-NEXT:    cleanup
1076 // CHECK1-NEXT:    [[TMP4:%.*]] = extractvalue { ptr, i32 } [[TMP3]], 0
1077 // CHECK1-NEXT:    store ptr [[TMP4]], ptr [[EXN_SLOT]], align 8
1078 // CHECK1-NEXT:    [[TMP5:%.*]] = extractvalue { ptr, i32 } [[TMP3]], 1
1079 // CHECK1-NEXT:    store i32 [[TMP5]], ptr [[EHSELECTOR_SLOT]], align 4
1080 // CHECK1-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT2]], align 8
1081 // CHECK1-NEXT:    [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAYINIT_BEGIN1]], [[TMP6]]
1082 // CHECK1-NEXT:    br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY:%.*]]
1083 // CHECK1:       arraydestroy.body:
1084 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP6]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1085 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1086 // CHECK1-NEXT:    call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]]
1087 // CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAYINIT_BEGIN1]]
1088 // CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6]], label [[ARRAYDESTROY_BODY]]
1089 // CHECK1:       arraydestroy.done6:
1090 // CHECK1-NEXT:    br label [[EHCLEANUP:%.*]]
1091 // CHECK1:       lpad10:
1092 // CHECK1-NEXT:    [[TMP7:%.*]] = landingpad { ptr, i32 }
1093 // CHECK1-NEXT:    cleanup
1094 // CHECK1-NEXT:    [[TMP8:%.*]] = extractvalue { ptr, i32 } [[TMP7]], 0
1095 // CHECK1-NEXT:    store ptr [[TMP8]], ptr [[EXN_SLOT]], align 8
1096 // CHECK1-NEXT:    [[TMP9:%.*]] = extractvalue { ptr, i32 } [[TMP7]], 1
1097 // CHECK1-NEXT:    store i32 [[TMP9]], ptr [[EHSELECTOR_SLOT]], align 4
1098 // CHECK1-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT9]], align 8
1099 // CHECK1-NEXT:    [[ARRAYDESTROY_ISEMPTY16:%.*]] = icmp eq ptr [[ARRAYINIT_BEGIN8]], [[TMP10]]
1100 // CHECK1-NEXT:    br i1 [[ARRAYDESTROY_ISEMPTY16]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17:%.*]]
1101 // CHECK1:       arraydestroy.body17:
1102 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi ptr [ [[TMP10]], [[LPAD10]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ]
1103 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1
1104 // CHECK1-NEXT:    call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]]
1105 // CHECK1-NEXT:    [[ARRAYDESTROY_DONE20:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT19]], [[ARRAYINIT_BEGIN8]]
1106 // CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]]
1107 // CHECK1:       arraydestroy.done21:
1108 // CHECK1-NEXT:    br label [[EHCLEANUP]]
1109 // CHECK1:       ehcleanup:
1110 // CHECK1-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT]], align 8
1111 // CHECK1-NEXT:    [[PAD_ARRAYBEGIN:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYINIT_BEGIN]], i64 0, i64 0
1112 // CHECK1-NEXT:    [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP11]], i64 0, i64 0
1113 // CHECK1-NEXT:    [[ARRAYDESTROY_ISEMPTY22:%.*]] = icmp eq ptr [[PAD_ARRAYBEGIN]], [[PAD_ARRAYEND]]
1114 // CHECK1-NEXT:    br i1 [[ARRAYDESTROY_ISEMPTY22]], label [[ARRAYDESTROY_DONE27:%.*]], label [[ARRAYDESTROY_BODY23:%.*]]
1115 // CHECK1:       arraydestroy.body23:
1116 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST24:%.*]] = phi ptr [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT25:%.*]], [[ARRAYDESTROY_BODY23]] ]
1117 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT25]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST24]], i64 -1
1118 // CHECK1-NEXT:    call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT25]]) #[[ATTR3]]
1119 // CHECK1-NEXT:    [[ARRAYDESTROY_DONE26:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT25]], [[PAD_ARRAYBEGIN]]
1120 // CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE26]], label [[ARRAYDESTROY_DONE27]], label [[ARRAYDESTROY_BODY23]]
1121 // CHECK1:       arraydestroy.done27:
1122 // CHECK1-NEXT:    br label [[EH_RESUME:%.*]]
1123 // CHECK1:       eh.resume:
1124 // CHECK1-NEXT:    [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8
1125 // CHECK1-NEXT:    [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4
1126 // CHECK1-NEXT:    [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0
1127 // CHECK1-NEXT:    [[LPAD_VAL28:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1
1128 // CHECK1-NEXT:    resume { ptr, i32 } [[LPAD_VAL28]]
1129 //
1130 //
1131 // CHECK1-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_..2
1132 // CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {
1133 // CHECK1-NEXT:  entry:
1134 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
1135 // CHECK1-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
1136 // CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8
1137 // CHECK1-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP1]], i64 6
1138 // CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1139 // CHECK1:       arraydestroy.body:
1140 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1141 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1142 // CHECK1-NEXT:    call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]]
1143 // CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[TMP1]]
1144 // CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
1145 // CHECK1:       arraydestroy.done1:
1146 // CHECK1-NEXT:    ret void
1147 //
1148 //
1149 // CHECK1-LABEL: define {{[^@]+}}@.__omp_threadprivate_init_..3
1150 // CHECK1-SAME: () #[[ATTR0]] {
1151 // CHECK1-NEXT:  entry:
1152 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
1153 // CHECK1-NEXT:    call void @__kmpc_threadprivate_register(ptr @[[GLOB1]], ptr @arr_x, ptr @.__kmpc_global_ctor_..1, ptr null, ptr @.__kmpc_global_dtor_..2)
1154 // CHECK1-NEXT:    ret void
1155 //
1156 //
1157 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init
1158 // CHECK1-SAME: () #[[ATTR0]] {
1159 // CHECK1-NEXT:  entry:
1160 // CHECK1-NEXT:    call void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @_ZL3gs1, i32 noundef 5)
1161 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S1D1Ev, ptr @_ZL3gs1, ptr @__dso_handle) #[[ATTR3]]
1162 // CHECK1-NEXT:    ret void
1163 //
1164 //
1165 // CHECK1-LABEL: define {{[^@]+}}@_ZN2S1C2Ei
1166 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
1167 // CHECK1-NEXT:  entry:
1168 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1169 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
1170 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1171 // CHECK1-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
1172 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1173 // CHECK1-NEXT:    [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0
1174 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
1175 // CHECK1-NEXT:    store i32 [[TMP0]], ptr [[A2]], align 4
1176 // CHECK1-NEXT:    ret void
1177 //
1178 //
1179 // CHECK1-LABEL: define {{[^@]+}}@_ZN2S1D2Ev
1180 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
1181 // CHECK1-NEXT:  entry:
1182 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1183 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1184 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1185 // CHECK1-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0
1186 // CHECK1-NEXT:    store i32 0, ptr [[A]], align 4
1187 // CHECK1-NEXT:    ret void
1188 //
1189 //
1190 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.4
1191 // CHECK1-SAME: () #[[ATTR0]] {
1192 // CHECK1-NEXT:  entry:
1193 // CHECK1-NEXT:    call void @_ZN2S2C1Ei(ptr noundef nonnull align 8 dereferenceable(16) @_ZL3gs2, i32 noundef 27)
1194 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S2D1Ev, ptr @_ZL3gs2, ptr @__dso_handle) #[[ATTR3]]
1195 // CHECK1-NEXT:    ret void
1196 //
1197 //
1198 // CHECK1-LABEL: define {{[^@]+}}@_ZN2S2C1Ei
1199 // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1200 // CHECK1-NEXT:  entry:
1201 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1202 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
1203 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1204 // CHECK1-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
1205 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1206 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
1207 // CHECK1-NEXT:    call void @_ZN2S2C2Ei(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], i32 noundef [[TMP0]])
1208 // CHECK1-NEXT:    ret void
1209 //
1210 //
1211 // CHECK1-LABEL: define {{[^@]+}}@_ZN2S2D1Ev
1212 // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
1213 // CHECK1-NEXT:  entry:
1214 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1215 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1216 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1217 // CHECK1-NEXT:    call void @_ZN2S2D2Ev(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]]) #[[ATTR3]]
1218 // CHECK1-NEXT:    ret void
1219 //
1220 //
1221 // CHECK1-LABEL: define {{[^@]+}}@_ZN2S2C2Ei
1222 // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
1223 // CHECK1-NEXT:  entry:
1224 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1225 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
1226 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1227 // CHECK1-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
1228 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1229 // CHECK1-NEXT:    [[A2:%.*]] = getelementptr inbounds [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0
1230 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
1231 // CHECK1-NEXT:    store i32 [[TMP0]], ptr [[A2]], align 8
1232 // CHECK1-NEXT:    ret void
1233 //
1234 //
1235 // CHECK1-LABEL: define {{[^@]+}}@_ZN2S2D2Ev
1236 // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
1237 // CHECK1-NEXT:  entry:
1238 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1239 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1240 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1241 // CHECK1-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0
1242 // CHECK1-NEXT:    store i32 0, ptr [[A]], align 8
1243 // CHECK1-NEXT:    ret void
1244 //
1245 //
1246 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.5
1247 // CHECK1-SAME: () #[[ATTR0]] personality ptr @__gxx_personality_v0 {
1248 // CHECK1-NEXT:  entry:
1249 // CHECK1-NEXT:    [[ARRAYINIT_ENDOFINIT:%.*]] = alloca ptr, align 8
1250 // CHECK1-NEXT:    [[ARRAYINIT_ENDOFINIT1:%.*]] = alloca ptr, align 8
1251 // CHECK1-NEXT:    [[EXN_SLOT:%.*]] = alloca ptr, align 8
1252 // CHECK1-NEXT:    [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4
1253 // CHECK1-NEXT:    [[ARRAYINIT_ENDOFINIT5:%.*]] = alloca ptr, align 8
1254 // CHECK1-NEXT:    store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT]], align 8
1255 // CHECK1-NEXT:    store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT1]], align 8
1256 // CHECK1-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @arr_x, i32 noundef 1)
1257 // CHECK1-NEXT:    to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]]
1258 // CHECK1:       invoke.cont:
1259 // CHECK1-NEXT:    store ptr getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT1]], align 8
1260 // CHECK1-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 1), i32 noundef 2)
1261 // CHECK1-NEXT:    to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD]]
1262 // CHECK1:       invoke.cont2:
1263 // CHECK1-NEXT:    store ptr getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), ptr [[ARRAYINIT_ENDOFINIT1]], align 8
1264 // CHECK1-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), i32 noundef 3)
1265 // CHECK1-NEXT:    to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]]
1266 // CHECK1:       invoke.cont3:
1267 // CHECK1-NEXT:    store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT]], align 8
1268 // CHECK1-NEXT:    store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8
1269 // CHECK1-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i32 noundef 4)
1270 // CHECK1-NEXT:    to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD6:%.*]]
1271 // CHECK1:       invoke.cont7:
1272 // CHECK1-NEXT:    store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8
1273 // CHECK1-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), i32 noundef 5)
1274 // CHECK1-NEXT:    to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD6]]
1275 // CHECK1:       invoke.cont8:
1276 // CHECK1-NEXT:    store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), ptr [[ARRAYINIT_ENDOFINIT5]], align 8
1277 // CHECK1-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), i32 noundef 6)
1278 // CHECK1-NEXT:    to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD6]]
1279 // CHECK1:       invoke.cont9:
1280 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR3]]
1281 // CHECK1-NEXT:    ret void
1282 // CHECK1:       lpad:
1283 // CHECK1-NEXT:    [[TMP1:%.*]] = landingpad { ptr, i32 }
1284 // CHECK1-NEXT:    cleanup
1285 // CHECK1-NEXT:    [[TMP2:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 0
1286 // CHECK1-NEXT:    store ptr [[TMP2]], ptr [[EXN_SLOT]], align 8
1287 // CHECK1-NEXT:    [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 1
1288 // CHECK1-NEXT:    store i32 [[TMP3]], ptr [[EHSELECTOR_SLOT]], align 4
1289 // CHECK1-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT1]], align 8
1290 // CHECK1-NEXT:    [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr @arr_x, [[TMP4]]
1291 // CHECK1-NEXT:    br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY:%.*]]
1292 // CHECK1:       arraydestroy.body:
1293 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP4]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1294 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1295 // CHECK1-NEXT:    call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]]
1296 // CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x
1297 // CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4]], label [[ARRAYDESTROY_BODY]]
1298 // CHECK1:       arraydestroy.done4:
1299 // CHECK1-NEXT:    br label [[EHCLEANUP:%.*]]
1300 // CHECK1:       lpad6:
1301 // CHECK1-NEXT:    [[TMP5:%.*]] = landingpad { ptr, i32 }
1302 // CHECK1-NEXT:    cleanup
1303 // CHECK1-NEXT:    [[TMP6:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 0
1304 // CHECK1-NEXT:    store ptr [[TMP6]], ptr [[EXN_SLOT]], align 8
1305 // CHECK1-NEXT:    [[TMP7:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 1
1306 // CHECK1-NEXT:    store i32 [[TMP7]], ptr [[EHSELECTOR_SLOT]], align 4
1307 // CHECK1-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT5]], align 8
1308 // CHECK1-NEXT:    [[ARRAYDESTROY_ISEMPTY10:%.*]] = icmp eq ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), [[TMP8]]
1309 // CHECK1-NEXT:    br i1 [[ARRAYDESTROY_ISEMPTY10]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY11:%.*]]
1310 // CHECK1:       arraydestroy.body11:
1311 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST12:%.*]] = phi ptr [ [[TMP8]], [[LPAD6]] ], [ [[ARRAYDESTROY_ELEMENT13:%.*]], [[ARRAYDESTROY_BODY11]] ]
1312 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT13]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST12]], i64 -1
1313 // CHECK1-NEXT:    call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR3]]
1314 // CHECK1-NEXT:    [[ARRAYDESTROY_DONE14:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1)
1315 // CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE14]], label [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_BODY11]]
1316 // CHECK1:       arraydestroy.done15:
1317 // CHECK1-NEXT:    br label [[EHCLEANUP]]
1318 // CHECK1:       ehcleanup:
1319 // CHECK1-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT]], align 8
1320 // CHECK1-NEXT:    [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP9]], i64 0, i64 0
1321 // CHECK1-NEXT:    [[ARRAYDESTROY_ISEMPTY16:%.*]] = icmp eq ptr @arr_x, [[PAD_ARRAYEND]]
1322 // CHECK1-NEXT:    br i1 [[ARRAYDESTROY_ISEMPTY16]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17:%.*]]
1323 // CHECK1:       arraydestroy.body17:
1324 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi ptr [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ]
1325 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1
1326 // CHECK1-NEXT:    call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]]
1327 // CHECK1-NEXT:    [[ARRAYDESTROY_DONE20:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT19]], @arr_x
1328 // CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]]
1329 // CHECK1:       arraydestroy.done21:
1330 // CHECK1-NEXT:    br label [[EH_RESUME:%.*]]
1331 // CHECK1:       eh.resume:
1332 // CHECK1-NEXT:    [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8
1333 // CHECK1-NEXT:    [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4
1334 // CHECK1-NEXT:    [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0
1335 // CHECK1-NEXT:    [[LPAD_VAL22:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1
1336 // CHECK1-NEXT:    resume { ptr, i32 } [[LPAD_VAL22]]
1337 //
1338 //
1339 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
1340 // CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {
1341 // CHECK1-NEXT:  entry:
1342 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
1343 // CHECK1-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
1344 // CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1345 // CHECK1:       arraydestroy.body:
1346 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 6), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1347 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1348 // CHECK1-NEXT:    call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]]
1349 // CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x
1350 // CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
1351 // CHECK1:       arraydestroy.done1:
1352 // CHECK1-NEXT:    ret void
1353 //
1354 //
1355 // CHECK1-LABEL: define {{[^@]+}}@main
1356 // CHECK1-SAME: () #[[ATTR4:[0-9]+]] personality ptr @__gxx_personality_v0 {
1357 // CHECK1-NEXT:  entry:
1358 // CHECK1-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
1359 // CHECK1-NEXT:    [[RES:%.*]] = alloca i32, align 4
1360 // CHECK1-NEXT:    [[EXN_SLOT:%.*]] = alloca ptr, align 8
1361 // CHECK1-NEXT:    [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4
1362 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
1363 // CHECK1-NEXT:    store i32 0, ptr [[RETVAL]], align 4
1364 // CHECK1-NEXT:    [[TMP1:%.*]] = load atomic i8, ptr @_ZGVZ4mainE2sm acquire, align 8
1365 // CHECK1-NEXT:    [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP1]], 0
1366 // CHECK1-NEXT:    br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF3:![0-9]+]]
1367 // CHECK1:       init.check:
1368 // CHECK1-NEXT:    [[TMP2:%.*]] = call i32 @__cxa_guard_acquire(ptr @_ZGVZ4mainE2sm) #[[ATTR3]]
1369 // CHECK1-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0
1370 // CHECK1-NEXT:    br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]]
1371 // CHECK1:       init:
1372 // CHECK1-NEXT:    [[TMP3:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
1373 // CHECK1-NEXT:    call void @__kmpc_threadprivate_register(ptr @[[GLOB1]], ptr @_ZZ4mainE2sm, ptr @.__kmpc_global_ctor_..6, ptr null, ptr @.__kmpc_global_dtor_..7)
1374 // CHECK1-NEXT:    [[TMP4:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @_ZL3gs1, i64 4, ptr @_ZL3gs1.cache.)
1375 // CHECK1-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP4]], i32 0, i32 0
1376 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[A]], align 4
1377 // CHECK1-NEXT:    invoke void @_ZZ4mainEN5SmainC1Ei(ptr noundef nonnull align 8 dereferenceable(24) @_ZZ4mainE2sm, i32 noundef [[TMP5]])
1378 // CHECK1-NEXT:    to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]]
1379 // CHECK1:       invoke.cont:
1380 // CHECK1-NEXT:    [[TMP6:%.*]] = call i32 @__cxa_atexit(ptr @_ZZ4mainEN5SmainD1Ev, ptr @_ZZ4mainE2sm, ptr @__dso_handle) #[[ATTR3]]
1381 // CHECK1-NEXT:    call void @__cxa_guard_release(ptr @_ZGVZ4mainE2sm) #[[ATTR3]]
1382 // CHECK1-NEXT:    br label [[INIT_END]]
1383 // CHECK1:       init.end:
1384 // CHECK1-NEXT:    [[TMP7:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @_ZN6Static1sE, i64 8, ptr @_ZN6Static1sE.cache.)
1385 // CHECK1-NEXT:    [[A1:%.*]] = getelementptr inbounds [[STRUCT_S3:%.*]], ptr [[TMP7]], i32 0, i32 0
1386 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A1]], align 4
1387 // CHECK1-NEXT:    store i32 [[TMP8]], ptr [[RES]], align 4
1388 // CHECK1-NEXT:    [[TMP9:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @_ZZ4mainE2sm, i64 24, ptr @_ZZ4mainE2sm.cache.)
1389 // CHECK1-NEXT:    [[A2:%.*]] = getelementptr inbounds [[STRUCT_SMAIN:%.*]], ptr [[TMP9]], i32 0, i32 0
1390 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[A2]], align 8
1391 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[RES]], align 4
1392 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP10]]
1393 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[RES]], align 4
1394 // CHECK1-NEXT:    [[TMP12:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @_ZL3gs1, i64 4, ptr @_ZL3gs1.cache.)
1395 // CHECK1-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP12]], i32 0, i32 0
1396 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, ptr [[A3]], align 4
1397 // CHECK1-NEXT:    [[TMP14:%.*]] = load i32, ptr [[RES]], align 4
1398 // CHECK1-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP14]], [[TMP13]]
1399 // CHECK1-NEXT:    store i32 [[ADD4]], ptr [[RES]], align 4
1400 // CHECK1-NEXT:    [[TMP15:%.*]] = load i32, ptr @_ZL3gs2, align 8
1401 // CHECK1-NEXT:    [[TMP16:%.*]] = load i32, ptr [[RES]], align 4
1402 // CHECK1-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP16]], [[TMP15]]
1403 // CHECK1-NEXT:    store i32 [[ADD5]], ptr [[RES]], align 4
1404 // CHECK1-NEXT:    [[TMP17:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @gs3, i64 12, ptr @gs3.cache.)
1405 // CHECK1-NEXT:    [[A6:%.*]] = getelementptr inbounds [[STRUCT_S5:%.*]], ptr [[TMP17]], i32 0, i32 0
1406 // CHECK1-NEXT:    [[TMP18:%.*]] = load i32, ptr [[A6]], align 4
1407 // CHECK1-NEXT:    [[TMP19:%.*]] = load i32, ptr [[RES]], align 4
1408 // CHECK1-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP19]], [[TMP18]]
1409 // CHECK1-NEXT:    store i32 [[ADD7]], ptr [[RES]], align 4
1410 // CHECK1-NEXT:    [[TMP20:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @arr_x, i64 24, ptr @arr_x.cache.)
1411 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP20]], i64 0, i64 1
1412 // CHECK1-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], i64 0, i64 1
1413 // CHECK1-NEXT:    [[A9:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYIDX8]], i32 0, i32 0
1414 // CHECK1-NEXT:    [[TMP21:%.*]] = load i32, ptr [[A9]], align 4
1415 // CHECK1-NEXT:    [[TMP22:%.*]] = load i32, ptr [[RES]], align 4
1416 // CHECK1-NEXT:    [[ADD10:%.*]] = add nsw i32 [[TMP22]], [[TMP21]]
1417 // CHECK1-NEXT:    store i32 [[ADD10]], ptr [[RES]], align 4
1418 // CHECK1-NEXT:    [[TMP23:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @_ZN2STIiE2stE, i64 4, ptr @_ZN2STIiE2stE.cache.)
1419 // CHECK1-NEXT:    [[TMP24:%.*]] = load i32, ptr [[TMP23]], align 4
1420 // CHECK1-NEXT:    [[TMP25:%.*]] = load i32, ptr [[RES]], align 4
1421 // CHECK1-NEXT:    [[ADD11:%.*]] = add nsw i32 [[TMP25]], [[TMP24]]
1422 // CHECK1-NEXT:    store i32 [[ADD11]], ptr [[RES]], align 4
1423 // CHECK1-NEXT:    [[TMP26:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @_ZN2STIfE2stE, i64 4, ptr @_ZN2STIfE2stE.cache.)
1424 // CHECK1-NEXT:    [[TMP27:%.*]] = load float, ptr [[TMP26]], align 4
1425 // CHECK1-NEXT:    [[CONV:%.*]] = fptosi float [[TMP27]] to i32
1426 // CHECK1-NEXT:    [[TMP28:%.*]] = load i32, ptr [[RES]], align 4
1427 // CHECK1-NEXT:    [[ADD12:%.*]] = add nsw i32 [[TMP28]], [[CONV]]
1428 // CHECK1-NEXT:    store i32 [[ADD12]], ptr [[RES]], align 4
1429 // CHECK1-NEXT:    [[TMP29:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @_ZN2STI2S4E2stE, i64 8, ptr @_ZN2STI2S4E2stE.cache.)
1430 // CHECK1-NEXT:    [[A13:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[TMP29]], i32 0, i32 0
1431 // CHECK1-NEXT:    [[TMP30:%.*]] = load i32, ptr [[A13]], align 4
1432 // CHECK1-NEXT:    [[TMP31:%.*]] = load i32, ptr [[RES]], align 4
1433 // CHECK1-NEXT:    [[ADD14:%.*]] = add nsw i32 [[TMP31]], [[TMP30]]
1434 // CHECK1-NEXT:    store i32 [[ADD14]], ptr [[RES]], align 4
1435 // CHECK1-NEXT:    [[TMP32:%.*]] = load i32, ptr [[RES]], align 4
1436 // CHECK1-NEXT:    ret i32 [[TMP32]]
1437 // CHECK1:       lpad:
1438 // CHECK1-NEXT:    [[TMP33:%.*]] = landingpad { ptr, i32 }
1439 // CHECK1-NEXT:    cleanup
1440 // CHECK1-NEXT:    [[TMP34:%.*]] = extractvalue { ptr, i32 } [[TMP33]], 0
1441 // CHECK1-NEXT:    store ptr [[TMP34]], ptr [[EXN_SLOT]], align 8
1442 // CHECK1-NEXT:    [[TMP35:%.*]] = extractvalue { ptr, i32 } [[TMP33]], 1
1443 // CHECK1-NEXT:    store i32 [[TMP35]], ptr [[EHSELECTOR_SLOT]], align 4
1444 // CHECK1-NEXT:    call void @__cxa_guard_abort(ptr @_ZGVZ4mainE2sm) #[[ATTR3]]
1445 // CHECK1-NEXT:    br label [[EH_RESUME:%.*]]
1446 // CHECK1:       eh.resume:
1447 // CHECK1-NEXT:    [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8
1448 // CHECK1-NEXT:    [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4
1449 // CHECK1-NEXT:    [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0
1450 // CHECK1-NEXT:    [[LPAD_VAL15:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1
1451 // CHECK1-NEXT:    resume { ptr, i32 } [[LPAD_VAL15]]
1452 //
1453 //
1454 // CHECK1-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_..6
1455 // CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {
1456 // CHECK1-NEXT:  entry:
1457 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
1458 // CHECK1-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
1459 // CHECK1-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
1460 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8
1461 // CHECK1-NEXT:    [[TMP3:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP1]], ptr @_ZL3gs1, i64 4, ptr @_ZL3gs1.cache.)
1462 // CHECK1-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP3]], i32 0, i32 0
1463 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[A]], align 4
1464 // CHECK1-NEXT:    call void @_ZZ4mainEN5SmainC1Ei(ptr noundef nonnull align 8 dereferenceable(24) [[TMP2]], i32 noundef [[TMP4]])
1465 // CHECK1-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[DOTADDR]], align 8
1466 // CHECK1-NEXT:    ret ptr [[TMP5]]
1467 //
1468 //
1469 // CHECK1-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC1Ei
1470 // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
1471 // CHECK1-NEXT:  entry:
1472 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1473 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
1474 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1475 // CHECK1-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
1476 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1477 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
1478 // CHECK1-NEXT:    call void @_ZZ4mainEN5SmainC2Ei(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]], i32 noundef [[TMP0]])
1479 // CHECK1-NEXT:    ret void
1480 //
1481 //
1482 // CHECK1-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_..7
1483 // CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {
1484 // CHECK1-NEXT:  entry:
1485 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
1486 // CHECK1-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
1487 // CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8
1488 // CHECK1-NEXT:    call void @_ZZ4mainEN5SmainD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[TMP1]]) #[[ATTR3]]
1489 // CHECK1-NEXT:    ret void
1490 //
1491 //
1492 // CHECK1-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD1Ev
1493 // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 {
1494 // CHECK1-NEXT:  entry:
1495 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1496 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1497 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1498 // CHECK1-NEXT:    call void @_ZZ4mainEN5SmainD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR3]]
1499 // CHECK1-NEXT:    ret void
1500 //
1501 //
1502 // CHECK1-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC2Ei
1503 // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 {
1504 // CHECK1-NEXT:  entry:
1505 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1506 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
1507 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1508 // CHECK1-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
1509 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1510 // CHECK1-NEXT:    [[A2:%.*]] = getelementptr inbounds [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0
1511 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
1512 // CHECK1-NEXT:    store i32 [[TMP0]], ptr [[A2]], align 8
1513 // CHECK1-NEXT:    ret void
1514 //
1515 //
1516 // CHECK1-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD2Ev
1517 // CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 {
1518 // CHECK1-NEXT:  entry:
1519 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1520 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1521 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1522 // CHECK1-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0
1523 // CHECK1-NEXT:    store i32 0, ptr [[A]], align 8
1524 // CHECK1-NEXT:    ret void
1525 //
1526 //
1527 // CHECK1-LABEL: define {{[^@]+}}@_Z6foobarv
1528 // CHECK1-SAME: () #[[ATTR5:[0-9]+]] {
1529 // CHECK1-NEXT:  entry:
1530 // CHECK1-NEXT:    [[RES:%.*]] = alloca i32, align 4
1531 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
1532 // CHECK1-NEXT:    [[TMP1:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @_ZN6Static1sE, i64 8, ptr @_ZN6Static1sE.cache.)
1533 // CHECK1-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S3:%.*]], ptr [[TMP1]], i32 0, i32 0
1534 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 4
1535 // CHECK1-NEXT:    store i32 [[TMP2]], ptr [[RES]], align 4
1536 // CHECK1-NEXT:    [[TMP3:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @_ZL3gs1, i64 4, ptr @_ZL3gs1.cache.)
1537 // CHECK1-NEXT:    [[A1:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP3]], i32 0, i32 0
1538 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[A1]], align 4
1539 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[RES]], align 4
1540 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP5]], [[TMP4]]
1541 // CHECK1-NEXT:    store i32 [[ADD]], ptr [[RES]], align 4
1542 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, ptr @_ZL3gs2, align 8
1543 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[RES]], align 4
1544 // CHECK1-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP7]], [[TMP6]]
1545 // CHECK1-NEXT:    store i32 [[ADD2]], ptr [[RES]], align 4
1546 // CHECK1-NEXT:    [[TMP8:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @gs3, i64 12, ptr @gs3.cache.)
1547 // CHECK1-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S5:%.*]], ptr [[TMP8]], i32 0, i32 0
1548 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[A3]], align 4
1549 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[RES]], align 4
1550 // CHECK1-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]
1551 // CHECK1-NEXT:    store i32 [[ADD4]], ptr [[RES]], align 4
1552 // CHECK1-NEXT:    [[TMP11:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @arr_x, i64 24, ptr @arr_x.cache.)
1553 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP11]], i64 0, i64 1
1554 // CHECK1-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], i64 0, i64 1
1555 // CHECK1-NEXT:    [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYIDX5]], i32 0, i32 0
1556 // CHECK1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[A6]], align 4
1557 // CHECK1-NEXT:    [[TMP13:%.*]] = load i32, ptr [[RES]], align 4
1558 // CHECK1-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP13]], [[TMP12]]
1559 // CHECK1-NEXT:    store i32 [[ADD7]], ptr [[RES]], align 4
1560 // CHECK1-NEXT:    [[TMP14:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @_ZN2STIiE2stE, i64 4, ptr @_ZN2STIiE2stE.cache.)
1561 // CHECK1-NEXT:    [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4
1562 // CHECK1-NEXT:    [[TMP16:%.*]] = load i32, ptr [[RES]], align 4
1563 // CHECK1-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP16]], [[TMP15]]
1564 // CHECK1-NEXT:    store i32 [[ADD8]], ptr [[RES]], align 4
1565 // CHECK1-NEXT:    [[TMP17:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @_ZN2STIfE2stE, i64 4, ptr @_ZN2STIfE2stE.cache.)
1566 // CHECK1-NEXT:    [[TMP18:%.*]] = load float, ptr [[TMP17]], align 4
1567 // CHECK1-NEXT:    [[CONV:%.*]] = fptosi float [[TMP18]] to i32
1568 // CHECK1-NEXT:    [[TMP19:%.*]] = load i32, ptr [[RES]], align 4
1569 // CHECK1-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP19]], [[CONV]]
1570 // CHECK1-NEXT:    store i32 [[ADD9]], ptr [[RES]], align 4
1571 // CHECK1-NEXT:    [[TMP20:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @_ZN2STI2S4E2stE, i64 8, ptr @_ZN2STI2S4E2stE.cache.)
1572 // CHECK1-NEXT:    [[A10:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[TMP20]], i32 0, i32 0
1573 // CHECK1-NEXT:    [[TMP21:%.*]] = load i32, ptr [[A10]], align 4
1574 // CHECK1-NEXT:    [[TMP22:%.*]] = load i32, ptr [[RES]], align 4
1575 // CHECK1-NEXT:    [[ADD11:%.*]] = add nsw i32 [[TMP22]], [[TMP21]]
1576 // CHECK1-NEXT:    store i32 [[ADD11]], ptr [[RES]], align 4
1577 // CHECK1-NEXT:    [[TMP23:%.*]] = load i32, ptr [[RES]], align 4
1578 // CHECK1-NEXT:    ret i32 [[TMP23]]
1579 //
1580 //
1581 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_var_init.8
1582 // CHECK1-SAME: () #[[ATTR0]] comdat($_ZN2STI2S4E2stE) {
1583 // CHECK1-NEXT:  entry:
1584 // CHECK1-NEXT:    [[TMP0:%.*]] = load i8, ptr @_ZGVN2STI2S4E2stE, align 8
1585 // CHECK1-NEXT:    [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0
1586 // CHECK1-NEXT:    br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]]
1587 // CHECK1:       init.check:
1588 // CHECK1-NEXT:    store i8 1, ptr @_ZGVN2STI2S4E2stE, align 8
1589 // CHECK1-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
1590 // CHECK1-NEXT:    call void @__kmpc_threadprivate_register(ptr @[[GLOB1]], ptr @_ZN2STI2S4E2stE, ptr @.__kmpc_global_ctor_..9, ptr null, ptr @.__kmpc_global_dtor_..10)
1591 // CHECK1-NEXT:    call void @_ZN2S4C1Ei(ptr noundef nonnull align 4 dereferenceable(8) @_ZN2STI2S4E2stE, i32 noundef 23)
1592 // CHECK1-NEXT:    [[TMP2:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S4D1Ev, ptr @_ZN2STI2S4E2stE, ptr @__dso_handle) #[[ATTR3]]
1593 // CHECK1-NEXT:    br label [[INIT_END]]
1594 // CHECK1:       init.end:
1595 // CHECK1-NEXT:    ret void
1596 //
1597 //
1598 // CHECK1-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_..9
1599 // CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {
1600 // CHECK1-NEXT:  entry:
1601 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
1602 // CHECK1-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
1603 // CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8
1604 // CHECK1-NEXT:    call void @_ZN2S4C1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[TMP1]], i32 noundef 23)
1605 // CHECK1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8
1606 // CHECK1-NEXT:    ret ptr [[TMP2]]
1607 //
1608 //
1609 // CHECK1-LABEL: define {{[^@]+}}@_ZN2S4C1Ei
1610 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1611 // CHECK1-NEXT:  entry:
1612 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1613 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
1614 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1615 // CHECK1-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
1616 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1617 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
1618 // CHECK1-NEXT:    call void @_ZN2S4C2Ei(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]], i32 noundef [[TMP0]])
1619 // CHECK1-NEXT:    ret void
1620 //
1621 //
1622 // CHECK1-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_..10
1623 // CHECK1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {
1624 // CHECK1-NEXT:  entry:
1625 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
1626 // CHECK1-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
1627 // CHECK1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8
1628 // CHECK1-NEXT:    call void @_ZN2S4D1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[TMP1]]) #[[ATTR3]]
1629 // CHECK1-NEXT:    ret void
1630 //
1631 //
1632 // CHECK1-LABEL: define {{[^@]+}}@_ZN2S4D1Ev
1633 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
1634 // CHECK1-NEXT:  entry:
1635 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1636 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1637 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1638 // CHECK1-NEXT:    call void @_ZN2S4D2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR3]]
1639 // CHECK1-NEXT:    ret void
1640 //
1641 //
1642 // CHECK1-LABEL: define {{[^@]+}}@_ZN2S4C2Ei
1643 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
1644 // CHECK1-NEXT:  entry:
1645 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1646 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
1647 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1648 // CHECK1-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
1649 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1650 // CHECK1-NEXT:    [[A2:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0
1651 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
1652 // CHECK1-NEXT:    store i32 [[TMP0]], ptr [[A2]], align 4
1653 // CHECK1-NEXT:    ret void
1654 //
1655 //
1656 // CHECK1-LABEL: define {{[^@]+}}@_ZN2S4D2Ev
1657 // CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
1658 // CHECK1-NEXT:  entry:
1659 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1660 // CHECK1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1661 // CHECK1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1662 // CHECK1-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0
1663 // CHECK1-NEXT:    store i32 0, ptr [[A]], align 4
1664 // CHECK1-NEXT:    ret void
1665 //
1666 //
1667 // CHECK1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_threadprivate_codegen.cpp
1668 // CHECK1-SAME: () #[[ATTR0]] {
1669 // CHECK1-NEXT:  entry:
1670 // CHECK1-NEXT:    call void @__cxx_global_var_init()
1671 // CHECK1-NEXT:    call void @.__omp_threadprivate_init_.()
1672 // CHECK1-NEXT:    call void @__cxx_global_var_init.4()
1673 // CHECK1-NEXT:    call void @__cxx_global_var_init.5()
1674 // CHECK1-NEXT:    call void @.__omp_threadprivate_init_..3()
1675 // CHECK1-NEXT:    ret void
1676 //
1677 //
1678 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init
1679 // CHECK2-SAME: () #[[ATTR0:[0-9]+]] {
1680 // CHECK2-NEXT:  entry:
1681 // CHECK2-NEXT:    call void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @_ZL3gs1, i32 noundef 5)
1682 // CHECK2-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S1D1Ev, ptr @_ZL3gs1, ptr @__dso_handle) #[[ATTR3:[0-9]+]]
1683 // CHECK2-NEXT:    ret void
1684 //
1685 //
1686 // CHECK2-LABEL: define {{[^@]+}}@_ZN2S1C1Ei
1687 // CHECK2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
1688 // CHECK2-NEXT:  entry:
1689 // CHECK2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1690 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
1691 // CHECK2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1692 // CHECK2-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
1693 // CHECK2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1694 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
1695 // CHECK2-NEXT:    call void @_ZN2S1C2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])
1696 // CHECK2-NEXT:    ret void
1697 //
1698 //
1699 // CHECK2-LABEL: define {{[^@]+}}@_ZN2S1D1Ev
1700 // CHECK2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 {
1701 // CHECK2-NEXT:  entry:
1702 // CHECK2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1703 // CHECK2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1704 // CHECK2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1705 // CHECK2-NEXT:    call void @_ZN2S1D2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]]
1706 // CHECK2-NEXT:    ret void
1707 //
1708 //
1709 // CHECK2-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_.
1710 // CHECK2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {
1711 // CHECK2-NEXT:  entry:
1712 // CHECK2-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
1713 // CHECK2-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
1714 // CHECK2-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8
1715 // CHECK2-NEXT:    call void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[TMP1]], i32 noundef 5)
1716 // CHECK2-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8
1717 // CHECK2-NEXT:    ret ptr [[TMP2]]
1718 //
1719 //
1720 // CHECK2-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_.
1721 // CHECK2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {
1722 // CHECK2-NEXT:  entry:
1723 // CHECK2-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
1724 // CHECK2-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
1725 // CHECK2-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8
1726 // CHECK2-NEXT:    call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP1]]) #[[ATTR3]]
1727 // CHECK2-NEXT:    ret void
1728 //
1729 //
1730 // CHECK2-LABEL: define {{[^@]+}}@.__omp_threadprivate_init_.
1731 // CHECK2-SAME: () #[[ATTR0]] {
1732 // CHECK2-NEXT:  entry:
1733 // CHECK2-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
1734 // CHECK2-NEXT:    call void @__kmpc_threadprivate_register(ptr @[[GLOB1]], ptr @_ZL3gs1, ptr @.__kmpc_global_ctor_., ptr null, ptr @.__kmpc_global_dtor_.)
1735 // CHECK2-NEXT:    ret void
1736 //
1737 //
1738 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
1739 // CHECK2-SAME: () #[[ATTR0]] {
1740 // CHECK2-NEXT:  entry:
1741 // CHECK2-NEXT:    call void @_ZN2S2C1Ei(ptr noundef nonnull align 8 dereferenceable(16) @_ZL3gs2, i32 noundef 27)
1742 // CHECK2-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S2D1Ev, ptr @_ZL3gs2, ptr @__dso_handle) #[[ATTR3]]
1743 // CHECK2-NEXT:    ret void
1744 //
1745 //
1746 // CHECK2-LABEL: define {{[^@]+}}@_ZN2S2C1Ei
1747 // CHECK2-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1748 // CHECK2-NEXT:  entry:
1749 // CHECK2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1750 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
1751 // CHECK2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1752 // CHECK2-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
1753 // CHECK2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1754 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
1755 // CHECK2-NEXT:    call void @_ZN2S2C2Ei(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], i32 noundef [[TMP0]])
1756 // CHECK2-NEXT:    ret void
1757 //
1758 //
1759 // CHECK2-LABEL: define {{[^@]+}}@_ZN2S2D1Ev
1760 // CHECK2-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
1761 // CHECK2-NEXT:  entry:
1762 // CHECK2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
1763 // CHECK2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
1764 // CHECK2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
1765 // CHECK2-NEXT:    call void @_ZN2S2D2Ev(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]]) #[[ATTR3]]
1766 // CHECK2-NEXT:    ret void
1767 //
1768 //
1769 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
1770 // CHECK2-SAME: () #[[ATTR0]] personality ptr @__gxx_personality_v0 {
1771 // CHECK2-NEXT:  entry:
1772 // CHECK2-NEXT:    [[ARRAYINIT_ENDOFINIT:%.*]] = alloca ptr, align 8
1773 // CHECK2-NEXT:    [[ARRAYINIT_ENDOFINIT1:%.*]] = alloca ptr, align 8
1774 // CHECK2-NEXT:    [[EXN_SLOT:%.*]] = alloca ptr, align 8
1775 // CHECK2-NEXT:    [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4
1776 // CHECK2-NEXT:    [[ARRAYINIT_ENDOFINIT5:%.*]] = alloca ptr, align 8
1777 // CHECK2-NEXT:    store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT]], align 8
1778 // CHECK2-NEXT:    store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT1]], align 8
1779 // CHECK2-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @arr_x, i32 noundef 1)
1780 // CHECK2-NEXT:    to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]]
1781 // CHECK2:       invoke.cont:
1782 // CHECK2-NEXT:    store ptr getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT1]], align 8
1783 // CHECK2-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 1), i32 noundef 2)
1784 // CHECK2-NEXT:    to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD]]
1785 // CHECK2:       invoke.cont2:
1786 // CHECK2-NEXT:    store ptr getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), ptr [[ARRAYINIT_ENDOFINIT1]], align 8
1787 // CHECK2-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), i32 noundef 3)
1788 // CHECK2-NEXT:    to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]]
1789 // CHECK2:       invoke.cont3:
1790 // CHECK2-NEXT:    store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT]], align 8
1791 // CHECK2-NEXT:    store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8
1792 // CHECK2-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i32 noundef 4)
1793 // CHECK2-NEXT:    to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD6:%.*]]
1794 // CHECK2:       invoke.cont7:
1795 // CHECK2-NEXT:    store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8
1796 // CHECK2-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), i32 noundef 5)
1797 // CHECK2-NEXT:    to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD6]]
1798 // CHECK2:       invoke.cont8:
1799 // CHECK2-NEXT:    store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), ptr [[ARRAYINIT_ENDOFINIT5]], align 8
1800 // CHECK2-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), i32 noundef 6)
1801 // CHECK2-NEXT:    to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD6]]
1802 // CHECK2:       invoke.cont9:
1803 // CHECK2-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR3]]
1804 // CHECK2-NEXT:    ret void
1805 // CHECK2:       lpad:
1806 // CHECK2-NEXT:    [[TMP1:%.*]] = landingpad { ptr, i32 }
1807 // CHECK2-NEXT:    cleanup
1808 // CHECK2-NEXT:    [[TMP2:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 0
1809 // CHECK2-NEXT:    store ptr [[TMP2]], ptr [[EXN_SLOT]], align 8
1810 // CHECK2-NEXT:    [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 1
1811 // CHECK2-NEXT:    store i32 [[TMP3]], ptr [[EHSELECTOR_SLOT]], align 4
1812 // CHECK2-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT1]], align 8
1813 // CHECK2-NEXT:    [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr @arr_x, [[TMP4]]
1814 // CHECK2-NEXT:    br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY:%.*]]
1815 // CHECK2:       arraydestroy.body:
1816 // CHECK2-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP4]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1817 // CHECK2-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1818 // CHECK2-NEXT:    call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]]
1819 // CHECK2-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x
1820 // CHECK2-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4]], label [[ARRAYDESTROY_BODY]]
1821 // CHECK2:       arraydestroy.done4:
1822 // CHECK2-NEXT:    br label [[EHCLEANUP:%.*]]
1823 // CHECK2:       lpad6:
1824 // CHECK2-NEXT:    [[TMP5:%.*]] = landingpad { ptr, i32 }
1825 // CHECK2-NEXT:    cleanup
1826 // CHECK2-NEXT:    [[TMP6:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 0
1827 // CHECK2-NEXT:    store ptr [[TMP6]], ptr [[EXN_SLOT]], align 8
1828 // CHECK2-NEXT:    [[TMP7:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 1
1829 // CHECK2-NEXT:    store i32 [[TMP7]], ptr [[EHSELECTOR_SLOT]], align 4
1830 // CHECK2-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT5]], align 8
1831 // CHECK2-NEXT:    [[ARRAYDESTROY_ISEMPTY10:%.*]] = icmp eq ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), [[TMP8]]
1832 // CHECK2-NEXT:    br i1 [[ARRAYDESTROY_ISEMPTY10]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY11:%.*]]
1833 // CHECK2:       arraydestroy.body11:
1834 // CHECK2-NEXT:    [[ARRAYDESTROY_ELEMENTPAST12:%.*]] = phi ptr [ [[TMP8]], [[LPAD6]] ], [ [[ARRAYDESTROY_ELEMENT13:%.*]], [[ARRAYDESTROY_BODY11]] ]
1835 // CHECK2-NEXT:    [[ARRAYDESTROY_ELEMENT13]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST12]], i64 -1
1836 // CHECK2-NEXT:    call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR3]]
1837 // CHECK2-NEXT:    [[ARRAYDESTROY_DONE14:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1)
1838 // CHECK2-NEXT:    br i1 [[ARRAYDESTROY_DONE14]], label [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_BODY11]]
1839 // CHECK2:       arraydestroy.done15:
1840 // CHECK2-NEXT:    br label [[EHCLEANUP]]
1841 // CHECK2:       ehcleanup:
1842 // CHECK2-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT]], align 8
1843 // CHECK2-NEXT:    [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP9]], i64 0, i64 0
1844 // CHECK2-NEXT:    [[ARRAYDESTROY_ISEMPTY16:%.*]] = icmp eq ptr @arr_x, [[PAD_ARRAYEND]]
1845 // CHECK2-NEXT:    br i1 [[ARRAYDESTROY_ISEMPTY16]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17:%.*]]
1846 // CHECK2:       arraydestroy.body17:
1847 // CHECK2-NEXT:    [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi ptr [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ]
1848 // CHECK2-NEXT:    [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1
1849 // CHECK2-NEXT:    call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]]
1850 // CHECK2-NEXT:    [[ARRAYDESTROY_DONE20:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT19]], @arr_x
1851 // CHECK2-NEXT:    br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]]
1852 // CHECK2:       arraydestroy.done21:
1853 // CHECK2-NEXT:    br label [[EH_RESUME:%.*]]
1854 // CHECK2:       eh.resume:
1855 // CHECK2-NEXT:    [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8
1856 // CHECK2-NEXT:    [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4
1857 // CHECK2-NEXT:    [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0
1858 // CHECK2-NEXT:    [[LPAD_VAL22:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1
1859 // CHECK2-NEXT:    resume { ptr, i32 } [[LPAD_VAL22]]
1860 //
1861 //
1862 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
1863 // CHECK2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {
1864 // CHECK2-NEXT:  entry:
1865 // CHECK2-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
1866 // CHECK2-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
1867 // CHECK2-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1868 // CHECK2:       arraydestroy.body:
1869 // CHECK2-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 6), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1870 // CHECK2-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1871 // CHECK2-NEXT:    call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]]
1872 // CHECK2-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x
1873 // CHECK2-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
1874 // CHECK2:       arraydestroy.done1:
1875 // CHECK2-NEXT:    ret void
1876 //
1877 //
1878 // CHECK2-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_..3
1879 // CHECK2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] personality ptr @__gxx_personality_v0 {
1880 // CHECK2-NEXT:  entry:
1881 // CHECK2-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
1882 // CHECK2-NEXT:    [[ARRAYINIT_ENDOFINIT:%.*]] = alloca ptr, align 8
1883 // CHECK2-NEXT:    [[ARRAYINIT_ENDOFINIT2:%.*]] = alloca ptr, align 8
1884 // CHECK2-NEXT:    [[EXN_SLOT:%.*]] = alloca ptr, align 8
1885 // CHECK2-NEXT:    [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4
1886 // CHECK2-NEXT:    [[ARRAYINIT_ENDOFINIT9:%.*]] = alloca ptr, align 8
1887 // CHECK2-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
1888 // CHECK2-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8
1889 // CHECK2-NEXT:    [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP1]], i64 0, i64 0
1890 // CHECK2-NEXT:    store ptr [[ARRAYINIT_BEGIN]], ptr [[ARRAYINIT_ENDOFINIT]], align 8
1891 // CHECK2-NEXT:    [[ARRAYINIT_BEGIN1:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYINIT_BEGIN]], i64 0, i64 0
1892 // CHECK2-NEXT:    store ptr [[ARRAYINIT_BEGIN1]], ptr [[ARRAYINIT_ENDOFINIT2]], align 8
1893 // CHECK2-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN1]], i32 noundef 1)
1894 // CHECK2-NEXT:    to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]]
1895 // CHECK2:       invoke.cont:
1896 // CHECK2-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[ARRAYINIT_BEGIN1]], i64 1
1897 // CHECK2-NEXT:    store ptr [[ARRAYINIT_ELEMENT]], ptr [[ARRAYINIT_ENDOFINIT2]], align 8
1898 // CHECK2-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)
1899 // CHECK2-NEXT:    to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]]
1900 // CHECK2:       invoke.cont3:
1901 // CHECK2-NEXT:    [[ARRAYINIT_ELEMENT4:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYINIT_ELEMENT]], i64 1
1902 // CHECK2-NEXT:    store ptr [[ARRAYINIT_ELEMENT4]], ptr [[ARRAYINIT_ENDOFINIT2]], align 8
1903 // CHECK2-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT4]], i32 noundef 3)
1904 // CHECK2-NEXT:    to label [[INVOKE_CONT5:%.*]] unwind label [[LPAD]]
1905 // CHECK2:       invoke.cont5:
1906 // CHECK2-NEXT:    [[ARRAYINIT_ELEMENT7:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYINIT_BEGIN]], i64 1
1907 // CHECK2-NEXT:    store ptr [[ARRAYINIT_ELEMENT7]], ptr [[ARRAYINIT_ENDOFINIT]], align 8
1908 // CHECK2-NEXT:    [[ARRAYINIT_BEGIN8:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYINIT_ELEMENT7]], i64 0, i64 0
1909 // CHECK2-NEXT:    store ptr [[ARRAYINIT_BEGIN8]], ptr [[ARRAYINIT_ENDOFINIT9]], align 8
1910 // CHECK2-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN8]], i32 noundef 4)
1911 // CHECK2-NEXT:    to label [[INVOKE_CONT11:%.*]] unwind label [[LPAD10:%.*]]
1912 // CHECK2:       invoke.cont11:
1913 // CHECK2-NEXT:    [[ARRAYINIT_ELEMENT12:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYINIT_BEGIN8]], i64 1
1914 // CHECK2-NEXT:    store ptr [[ARRAYINIT_ELEMENT12]], ptr [[ARRAYINIT_ENDOFINIT9]], align 8
1915 // CHECK2-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT12]], i32 noundef 5)
1916 // CHECK2-NEXT:    to label [[INVOKE_CONT13:%.*]] unwind label [[LPAD10]]
1917 // CHECK2:       invoke.cont13:
1918 // CHECK2-NEXT:    [[ARRAYINIT_ELEMENT14:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYINIT_ELEMENT12]], i64 1
1919 // CHECK2-NEXT:    store ptr [[ARRAYINIT_ELEMENT14]], ptr [[ARRAYINIT_ENDOFINIT9]], align 8
1920 // CHECK2-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT14]], i32 noundef 6)
1921 // CHECK2-NEXT:    to label [[INVOKE_CONT15:%.*]] unwind label [[LPAD10]]
1922 // CHECK2:       invoke.cont15:
1923 // CHECK2-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8
1924 // CHECK2-NEXT:    ret ptr [[TMP2]]
1925 // CHECK2:       lpad:
1926 // CHECK2-NEXT:    [[TMP3:%.*]] = landingpad { ptr, i32 }
1927 // CHECK2-NEXT:    cleanup
1928 // CHECK2-NEXT:    [[TMP4:%.*]] = extractvalue { ptr, i32 } [[TMP3]], 0
1929 // CHECK2-NEXT:    store ptr [[TMP4]], ptr [[EXN_SLOT]], align 8
1930 // CHECK2-NEXT:    [[TMP5:%.*]] = extractvalue { ptr, i32 } [[TMP3]], 1
1931 // CHECK2-NEXT:    store i32 [[TMP5]], ptr [[EHSELECTOR_SLOT]], align 4
1932 // CHECK2-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT2]], align 8
1933 // CHECK2-NEXT:    [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAYINIT_BEGIN1]], [[TMP6]]
1934 // CHECK2-NEXT:    br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY:%.*]]
1935 // CHECK2:       arraydestroy.body:
1936 // CHECK2-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP6]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1937 // CHECK2-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1938 // CHECK2-NEXT:    call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]]
1939 // CHECK2-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAYINIT_BEGIN1]]
1940 // CHECK2-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6]], label [[ARRAYDESTROY_BODY]]
1941 // CHECK2:       arraydestroy.done6:
1942 // CHECK2-NEXT:    br label [[EHCLEANUP:%.*]]
1943 // CHECK2:       lpad10:
1944 // CHECK2-NEXT:    [[TMP7:%.*]] = landingpad { ptr, i32 }
1945 // CHECK2-NEXT:    cleanup
1946 // CHECK2-NEXT:    [[TMP8:%.*]] = extractvalue { ptr, i32 } [[TMP7]], 0
1947 // CHECK2-NEXT:    store ptr [[TMP8]], ptr [[EXN_SLOT]], align 8
1948 // CHECK2-NEXT:    [[TMP9:%.*]] = extractvalue { ptr, i32 } [[TMP7]], 1
1949 // CHECK2-NEXT:    store i32 [[TMP9]], ptr [[EHSELECTOR_SLOT]], align 4
1950 // CHECK2-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT9]], align 8
1951 // CHECK2-NEXT:    [[ARRAYDESTROY_ISEMPTY16:%.*]] = icmp eq ptr [[ARRAYINIT_BEGIN8]], [[TMP10]]
1952 // CHECK2-NEXT:    br i1 [[ARRAYDESTROY_ISEMPTY16]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17:%.*]]
1953 // CHECK2:       arraydestroy.body17:
1954 // CHECK2-NEXT:    [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi ptr [ [[TMP10]], [[LPAD10]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ]
1955 // CHECK2-NEXT:    [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1
1956 // CHECK2-NEXT:    call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]]
1957 // CHECK2-NEXT:    [[ARRAYDESTROY_DONE20:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT19]], [[ARRAYINIT_BEGIN8]]
1958 // CHECK2-NEXT:    br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]]
1959 // CHECK2:       arraydestroy.done21:
1960 // CHECK2-NEXT:    br label [[EHCLEANUP]]
1961 // CHECK2:       ehcleanup:
1962 // CHECK2-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT]], align 8
1963 // CHECK2-NEXT:    [[PAD_ARRAYBEGIN:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYINIT_BEGIN]], i64 0, i64 0
1964 // CHECK2-NEXT:    [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP11]], i64 0, i64 0
1965 // CHECK2-NEXT:    [[ARRAYDESTROY_ISEMPTY22:%.*]] = icmp eq ptr [[PAD_ARRAYBEGIN]], [[PAD_ARRAYEND]]
1966 // CHECK2-NEXT:    br i1 [[ARRAYDESTROY_ISEMPTY22]], label [[ARRAYDESTROY_DONE27:%.*]], label [[ARRAYDESTROY_BODY23:%.*]]
1967 // CHECK2:       arraydestroy.body23:
1968 // CHECK2-NEXT:    [[ARRAYDESTROY_ELEMENTPAST24:%.*]] = phi ptr [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT25:%.*]], [[ARRAYDESTROY_BODY23]] ]
1969 // CHECK2-NEXT:    [[ARRAYDESTROY_ELEMENT25]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST24]], i64 -1
1970 // CHECK2-NEXT:    call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT25]]) #[[ATTR3]]
1971 // CHECK2-NEXT:    [[ARRAYDESTROY_DONE26:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT25]], [[PAD_ARRAYBEGIN]]
1972 // CHECK2-NEXT:    br i1 [[ARRAYDESTROY_DONE26]], label [[ARRAYDESTROY_DONE27]], label [[ARRAYDESTROY_BODY23]]
1973 // CHECK2:       arraydestroy.done27:
1974 // CHECK2-NEXT:    br label [[EH_RESUME:%.*]]
1975 // CHECK2:       eh.resume:
1976 // CHECK2-NEXT:    [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8
1977 // CHECK2-NEXT:    [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4
1978 // CHECK2-NEXT:    [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0
1979 // CHECK2-NEXT:    [[LPAD_VAL28:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1
1980 // CHECK2-NEXT:    resume { ptr, i32 } [[LPAD_VAL28]]
1981 //
1982 //
1983 // CHECK2-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_..4
1984 // CHECK2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {
1985 // CHECK2-NEXT:  entry:
1986 // CHECK2-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
1987 // CHECK2-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
1988 // CHECK2-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8
1989 // CHECK2-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP1]], i64 6
1990 // CHECK2-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1991 // CHECK2:       arraydestroy.body:
1992 // CHECK2-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1993 // CHECK2-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1994 // CHECK2-NEXT:    call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]]
1995 // CHECK2-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[TMP1]]
1996 // CHECK2-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
1997 // CHECK2:       arraydestroy.done1:
1998 // CHECK2-NEXT:    ret void
1999 //
2000 //
2001 // CHECK2-LABEL: define {{[^@]+}}@.__omp_threadprivate_init_..5
2002 // CHECK2-SAME: () #[[ATTR0]] {
2003 // CHECK2-NEXT:  entry:
2004 // CHECK2-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
2005 // CHECK2-NEXT:    call void @__kmpc_threadprivate_register(ptr @[[GLOB1]], ptr @arr_x, ptr @.__kmpc_global_ctor_..3, ptr null, ptr @.__kmpc_global_dtor_..4)
2006 // CHECK2-NEXT:    ret void
2007 //
2008 //
2009 // CHECK2-LABEL: define {{[^@]+}}@main
2010 // CHECK2-SAME: () #[[ATTR4:[0-9]+]] personality ptr @__gxx_personality_v0 {
2011 // CHECK2-NEXT:  entry:
2012 // CHECK2-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
2013 // CHECK2-NEXT:    [[RES:%.*]] = alloca i32, align 4
2014 // CHECK2-NEXT:    [[EXN_SLOT:%.*]] = alloca ptr, align 8
2015 // CHECK2-NEXT:    [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4
2016 // CHECK2-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
2017 // CHECK2-NEXT:    store i32 0, ptr [[RETVAL]], align 4
2018 // CHECK2-NEXT:    [[TMP1:%.*]] = load atomic i8, ptr @_ZGVZ4mainE2sm acquire, align 8
2019 // CHECK2-NEXT:    [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP1]], 0
2020 // CHECK2-NEXT:    br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF3:![0-9]+]]
2021 // CHECK2:       init.check:
2022 // CHECK2-NEXT:    [[TMP2:%.*]] = call i32 @__cxa_guard_acquire(ptr @_ZGVZ4mainE2sm) #[[ATTR3]]
2023 // CHECK2-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0
2024 // CHECK2-NEXT:    br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]]
2025 // CHECK2:       init:
2026 // CHECK2-NEXT:    [[TMP3:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
2027 // CHECK2-NEXT:    call void @__kmpc_threadprivate_register(ptr @[[GLOB1]], ptr @_ZZ4mainE2sm, ptr @.__kmpc_global_ctor_..6, ptr null, ptr @.__kmpc_global_dtor_..7)
2028 // CHECK2-NEXT:    [[TMP4:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @_ZL3gs1, i64 4, ptr @_ZL3gs1.cache.)
2029 // CHECK2-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP4]], i32 0, i32 0
2030 // CHECK2-NEXT:    [[TMP5:%.*]] = load i32, ptr [[A]], align 4
2031 // CHECK2-NEXT:    invoke void @_ZZ4mainEN5SmainC1Ei(ptr noundef nonnull align 8 dereferenceable(24) @_ZZ4mainE2sm, i32 noundef [[TMP5]])
2032 // CHECK2-NEXT:    to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]]
2033 // CHECK2:       invoke.cont:
2034 // CHECK2-NEXT:    [[TMP6:%.*]] = call i32 @__cxa_atexit(ptr @_ZZ4mainEN5SmainD1Ev, ptr @_ZZ4mainE2sm, ptr @__dso_handle) #[[ATTR3]]
2035 // CHECK2-NEXT:    call void @__cxa_guard_release(ptr @_ZGVZ4mainE2sm) #[[ATTR3]]
2036 // CHECK2-NEXT:    br label [[INIT_END]]
2037 // CHECK2:       init.end:
2038 // CHECK2-NEXT:    [[TMP7:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @_ZN6Static1sE, i64 8, ptr @_ZN6Static1sE.cache.)
2039 // CHECK2-NEXT:    [[A1:%.*]] = getelementptr inbounds [[STRUCT_S3:%.*]], ptr [[TMP7]], i32 0, i32 0
2040 // CHECK2-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A1]], align 4
2041 // CHECK2-NEXT:    store i32 [[TMP8]], ptr [[RES]], align 4
2042 // CHECK2-NEXT:    [[TMP9:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @_ZZ4mainE2sm, i64 24, ptr @_ZZ4mainE2sm.cache.)
2043 // CHECK2-NEXT:    [[A2:%.*]] = getelementptr inbounds [[STRUCT_SMAIN:%.*]], ptr [[TMP9]], i32 0, i32 0
2044 // CHECK2-NEXT:    [[TMP10:%.*]] = load i32, ptr [[A2]], align 8
2045 // CHECK2-NEXT:    [[TMP11:%.*]] = load i32, ptr [[RES]], align 4
2046 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP10]]
2047 // CHECK2-NEXT:    store i32 [[ADD]], ptr [[RES]], align 4
2048 // CHECK2-NEXT:    [[TMP12:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @_ZL3gs1, i64 4, ptr @_ZL3gs1.cache.)
2049 // CHECK2-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP12]], i32 0, i32 0
2050 // CHECK2-NEXT:    [[TMP13:%.*]] = load i32, ptr [[A3]], align 4
2051 // CHECK2-NEXT:    [[TMP14:%.*]] = load i32, ptr [[RES]], align 4
2052 // CHECK2-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP14]], [[TMP13]]
2053 // CHECK2-NEXT:    store i32 [[ADD4]], ptr [[RES]], align 4
2054 // CHECK2-NEXT:    [[TMP15:%.*]] = load i32, ptr @_ZL3gs2, align 8
2055 // CHECK2-NEXT:    [[TMP16:%.*]] = load i32, ptr [[RES]], align 4
2056 // CHECK2-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP16]], [[TMP15]]
2057 // CHECK2-NEXT:    store i32 [[ADD5]], ptr [[RES]], align 4
2058 // CHECK2-NEXT:    [[TMP17:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @gs3, i64 12, ptr @gs3.cache.)
2059 // CHECK2-NEXT:    [[A6:%.*]] = getelementptr inbounds [[STRUCT_S5:%.*]], ptr [[TMP17]], i32 0, i32 0
2060 // CHECK2-NEXT:    [[TMP18:%.*]] = load i32, ptr [[A6]], align 4
2061 // CHECK2-NEXT:    [[TMP19:%.*]] = load i32, ptr [[RES]], align 4
2062 // CHECK2-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP19]], [[TMP18]]
2063 // CHECK2-NEXT:    store i32 [[ADD7]], ptr [[RES]], align 4
2064 // CHECK2-NEXT:    [[TMP20:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @arr_x, i64 24, ptr @arr_x.cache.)
2065 // CHECK2-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP20]], i64 0, i64 1
2066 // CHECK2-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], i64 0, i64 1
2067 // CHECK2-NEXT:    [[A9:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYIDX8]], i32 0, i32 0
2068 // CHECK2-NEXT:    [[TMP21:%.*]] = load i32, ptr [[A9]], align 4
2069 // CHECK2-NEXT:    [[TMP22:%.*]] = load i32, ptr [[RES]], align 4
2070 // CHECK2-NEXT:    [[ADD10:%.*]] = add nsw i32 [[TMP22]], [[TMP21]]
2071 // CHECK2-NEXT:    store i32 [[ADD10]], ptr [[RES]], align 4
2072 // CHECK2-NEXT:    [[TMP23:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @_ZN2STIiE2stE, i64 4, ptr @_ZN2STIiE2stE.cache.)
2073 // CHECK2-NEXT:    [[TMP24:%.*]] = load i32, ptr [[TMP23]], align 4
2074 // CHECK2-NEXT:    [[TMP25:%.*]] = load i32, ptr [[RES]], align 4
2075 // CHECK2-NEXT:    [[ADD11:%.*]] = add nsw i32 [[TMP25]], [[TMP24]]
2076 // CHECK2-NEXT:    store i32 [[ADD11]], ptr [[RES]], align 4
2077 // CHECK2-NEXT:    [[TMP26:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @_ZN2STIfE2stE, i64 4, ptr @_ZN2STIfE2stE.cache.)
2078 // CHECK2-NEXT:    [[TMP27:%.*]] = load float, ptr [[TMP26]], align 4
2079 // CHECK2-NEXT:    [[CONV:%.*]] = fptosi float [[TMP27]] to i32
2080 // CHECK2-NEXT:    [[TMP28:%.*]] = load i32, ptr [[RES]], align 4
2081 // CHECK2-NEXT:    [[ADD12:%.*]] = add nsw i32 [[TMP28]], [[CONV]]
2082 // CHECK2-NEXT:    store i32 [[ADD12]], ptr [[RES]], align 4
2083 // CHECK2-NEXT:    [[TMP29:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @_ZN2STI2S4E2stE, i64 8, ptr @_ZN2STI2S4E2stE.cache.)
2084 // CHECK2-NEXT:    [[A13:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[TMP29]], i32 0, i32 0
2085 // CHECK2-NEXT:    [[TMP30:%.*]] = load i32, ptr [[A13]], align 4
2086 // CHECK2-NEXT:    [[TMP31:%.*]] = load i32, ptr [[RES]], align 4
2087 // CHECK2-NEXT:    [[ADD14:%.*]] = add nsw i32 [[TMP31]], [[TMP30]]
2088 // CHECK2-NEXT:    store i32 [[ADD14]], ptr [[RES]], align 4
2089 // CHECK2-NEXT:    [[TMP32:%.*]] = load i32, ptr [[RES]], align 4
2090 // CHECK2-NEXT:    ret i32 [[TMP32]]
2091 // CHECK2:       lpad:
2092 // CHECK2-NEXT:    [[TMP33:%.*]] = landingpad { ptr, i32 }
2093 // CHECK2-NEXT:    cleanup
2094 // CHECK2-NEXT:    [[TMP34:%.*]] = extractvalue { ptr, i32 } [[TMP33]], 0
2095 // CHECK2-NEXT:    store ptr [[TMP34]], ptr [[EXN_SLOT]], align 8
2096 // CHECK2-NEXT:    [[TMP35:%.*]] = extractvalue { ptr, i32 } [[TMP33]], 1
2097 // CHECK2-NEXT:    store i32 [[TMP35]], ptr [[EHSELECTOR_SLOT]], align 4
2098 // CHECK2-NEXT:    call void @__cxa_guard_abort(ptr @_ZGVZ4mainE2sm) #[[ATTR3]]
2099 // CHECK2-NEXT:    br label [[EH_RESUME:%.*]]
2100 // CHECK2:       eh.resume:
2101 // CHECK2-NEXT:    [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8
2102 // CHECK2-NEXT:    [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4
2103 // CHECK2-NEXT:    [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0
2104 // CHECK2-NEXT:    [[LPAD_VAL15:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1
2105 // CHECK2-NEXT:    resume { ptr, i32 } [[LPAD_VAL15]]
2106 //
2107 //
2108 // CHECK2-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_..6
2109 // CHECK2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {
2110 // CHECK2-NEXT:  entry:
2111 // CHECK2-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
2112 // CHECK2-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
2113 // CHECK2-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
2114 // CHECK2-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8
2115 // CHECK2-NEXT:    [[TMP3:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP1]], ptr @_ZL3gs1, i64 4, ptr @_ZL3gs1.cache.)
2116 // CHECK2-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP3]], i32 0, i32 0
2117 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, ptr [[A]], align 4
2118 // CHECK2-NEXT:    call void @_ZZ4mainEN5SmainC1Ei(ptr noundef nonnull align 8 dereferenceable(24) [[TMP2]], i32 noundef [[TMP4]])
2119 // CHECK2-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[DOTADDR]], align 8
2120 // CHECK2-NEXT:    ret ptr [[TMP5]]
2121 //
2122 //
2123 // CHECK2-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC1Ei
2124 // CHECK2-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
2125 // CHECK2-NEXT:  entry:
2126 // CHECK2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2127 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2128 // CHECK2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2129 // CHECK2-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
2130 // CHECK2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2131 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
2132 // CHECK2-NEXT:    call void @_ZZ4mainEN5SmainC2Ei(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]], i32 noundef [[TMP0]])
2133 // CHECK2-NEXT:    ret void
2134 //
2135 //
2136 // CHECK2-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_..7
2137 // CHECK2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {
2138 // CHECK2-NEXT:  entry:
2139 // CHECK2-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
2140 // CHECK2-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
2141 // CHECK2-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8
2142 // CHECK2-NEXT:    call void @_ZZ4mainEN5SmainD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[TMP1]]) #[[ATTR3]]
2143 // CHECK2-NEXT:    ret void
2144 //
2145 //
2146 // CHECK2-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD1Ev
2147 // CHECK2-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 {
2148 // CHECK2-NEXT:  entry:
2149 // CHECK2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2150 // CHECK2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2151 // CHECK2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2152 // CHECK2-NEXT:    call void @_ZZ4mainEN5SmainD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR3]]
2153 // CHECK2-NEXT:    ret void
2154 //
2155 //
2156 // CHECK2-LABEL: define {{[^@]+}}@_Z6foobarv
2157 // CHECK2-SAME: () #[[ATTR5:[0-9]+]] {
2158 // CHECK2-NEXT:  entry:
2159 // CHECK2-NEXT:    [[RES:%.*]] = alloca i32, align 4
2160 // CHECK2-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
2161 // CHECK2-NEXT:    [[TMP1:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @_ZN6Static1sE, i64 8, ptr @_ZN6Static1sE.cache.)
2162 // CHECK2-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S3:%.*]], ptr [[TMP1]], i32 0, i32 0
2163 // CHECK2-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 4
2164 // CHECK2-NEXT:    store i32 [[TMP2]], ptr [[RES]], align 4
2165 // CHECK2-NEXT:    [[TMP3:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @_ZL3gs1, i64 4, ptr @_ZL3gs1.cache.)
2166 // CHECK2-NEXT:    [[A1:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP3]], i32 0, i32 0
2167 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, ptr [[A1]], align 4
2168 // CHECK2-NEXT:    [[TMP5:%.*]] = load i32, ptr [[RES]], align 4
2169 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP5]], [[TMP4]]
2170 // CHECK2-NEXT:    store i32 [[ADD]], ptr [[RES]], align 4
2171 // CHECK2-NEXT:    [[TMP6:%.*]] = load i32, ptr @_ZL3gs2, align 8
2172 // CHECK2-NEXT:    [[TMP7:%.*]] = load i32, ptr [[RES]], align 4
2173 // CHECK2-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP7]], [[TMP6]]
2174 // CHECK2-NEXT:    store i32 [[ADD2]], ptr [[RES]], align 4
2175 // CHECK2-NEXT:    [[TMP8:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @gs3, i64 12, ptr @gs3.cache.)
2176 // CHECK2-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S5:%.*]], ptr [[TMP8]], i32 0, i32 0
2177 // CHECK2-NEXT:    [[TMP9:%.*]] = load i32, ptr [[A3]], align 4
2178 // CHECK2-NEXT:    [[TMP10:%.*]] = load i32, ptr [[RES]], align 4
2179 // CHECK2-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]
2180 // CHECK2-NEXT:    store i32 [[ADD4]], ptr [[RES]], align 4
2181 // CHECK2-NEXT:    [[TMP11:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @arr_x, i64 24, ptr @arr_x.cache.)
2182 // CHECK2-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP11]], i64 0, i64 1
2183 // CHECK2-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], i64 0, i64 1
2184 // CHECK2-NEXT:    [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYIDX5]], i32 0, i32 0
2185 // CHECK2-NEXT:    [[TMP12:%.*]] = load i32, ptr [[A6]], align 4
2186 // CHECK2-NEXT:    [[TMP13:%.*]] = load i32, ptr [[RES]], align 4
2187 // CHECK2-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP13]], [[TMP12]]
2188 // CHECK2-NEXT:    store i32 [[ADD7]], ptr [[RES]], align 4
2189 // CHECK2-NEXT:    [[TMP14:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @_ZN2STIiE2stE, i64 4, ptr @_ZN2STIiE2stE.cache.)
2190 // CHECK2-NEXT:    [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4
2191 // CHECK2-NEXT:    [[TMP16:%.*]] = load i32, ptr [[RES]], align 4
2192 // CHECK2-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP16]], [[TMP15]]
2193 // CHECK2-NEXT:    store i32 [[ADD8]], ptr [[RES]], align 4
2194 // CHECK2-NEXT:    [[TMP17:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @_ZN2STIfE2stE, i64 4, ptr @_ZN2STIfE2stE.cache.)
2195 // CHECK2-NEXT:    [[TMP18:%.*]] = load float, ptr [[TMP17]], align 4
2196 // CHECK2-NEXT:    [[CONV:%.*]] = fptosi float [[TMP18]] to i32
2197 // CHECK2-NEXT:    [[TMP19:%.*]] = load i32, ptr [[RES]], align 4
2198 // CHECK2-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP19]], [[CONV]]
2199 // CHECK2-NEXT:    store i32 [[ADD9]], ptr [[RES]], align 4
2200 // CHECK2-NEXT:    [[TMP20:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @_ZN2STI2S4E2stE, i64 8, ptr @_ZN2STI2S4E2stE.cache.)
2201 // CHECK2-NEXT:    [[A10:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[TMP20]], i32 0, i32 0
2202 // CHECK2-NEXT:    [[TMP21:%.*]] = load i32, ptr [[A10]], align 4
2203 // CHECK2-NEXT:    [[TMP22:%.*]] = load i32, ptr [[RES]], align 4
2204 // CHECK2-NEXT:    [[ADD11:%.*]] = add nsw i32 [[TMP22]], [[TMP21]]
2205 // CHECK2-NEXT:    store i32 [[ADD11]], ptr [[RES]], align 4
2206 // CHECK2-NEXT:    [[TMP23:%.*]] = load i32, ptr [[RES]], align 4
2207 // CHECK2-NEXT:    ret i32 [[TMP23]]
2208 //
2209 //
2210 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_var_init.8
2211 // CHECK2-SAME: () #[[ATTR0]] comdat($_ZN2STI2S4E2stE) {
2212 // CHECK2-NEXT:  entry:
2213 // CHECK2-NEXT:    [[TMP0:%.*]] = load i8, ptr @_ZGVN2STI2S4E2stE, align 8
2214 // CHECK2-NEXT:    [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0
2215 // CHECK2-NEXT:    br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]]
2216 // CHECK2:       init.check:
2217 // CHECK2-NEXT:    store i8 1, ptr @_ZGVN2STI2S4E2stE, align 8
2218 // CHECK2-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
2219 // CHECK2-NEXT:    call void @__kmpc_threadprivate_register(ptr @[[GLOB1]], ptr @_ZN2STI2S4E2stE, ptr @.__kmpc_global_ctor_..9, ptr null, ptr @.__kmpc_global_dtor_..10)
2220 // CHECK2-NEXT:    call void @_ZN2S4C1Ei(ptr noundef nonnull align 4 dereferenceable(8) @_ZN2STI2S4E2stE, i32 noundef 23)
2221 // CHECK2-NEXT:    [[TMP2:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S4D1Ev, ptr @_ZN2STI2S4E2stE, ptr @__dso_handle) #[[ATTR3]]
2222 // CHECK2-NEXT:    br label [[INIT_END]]
2223 // CHECK2:       init.end:
2224 // CHECK2-NEXT:    ret void
2225 //
2226 //
2227 // CHECK2-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_..9
2228 // CHECK2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {
2229 // CHECK2-NEXT:  entry:
2230 // CHECK2-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
2231 // CHECK2-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
2232 // CHECK2-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8
2233 // CHECK2-NEXT:    call void @_ZN2S4C1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[TMP1]], i32 noundef 23)
2234 // CHECK2-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8
2235 // CHECK2-NEXT:    ret ptr [[TMP2]]
2236 //
2237 //
2238 // CHECK2-LABEL: define {{[^@]+}}@_ZN2S4C1Ei
2239 // CHECK2-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2240 // CHECK2-NEXT:  entry:
2241 // CHECK2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2242 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2243 // CHECK2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2244 // CHECK2-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
2245 // CHECK2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2246 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
2247 // CHECK2-NEXT:    call void @_ZN2S4C2Ei(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]], i32 noundef [[TMP0]])
2248 // CHECK2-NEXT:    ret void
2249 //
2250 //
2251 // CHECK2-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_..10
2252 // CHECK2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {
2253 // CHECK2-NEXT:  entry:
2254 // CHECK2-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
2255 // CHECK2-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
2256 // CHECK2-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8
2257 // CHECK2-NEXT:    call void @_ZN2S4D1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[TMP1]]) #[[ATTR3]]
2258 // CHECK2-NEXT:    ret void
2259 //
2260 //
2261 // CHECK2-LABEL: define {{[^@]+}}@_ZN2S4D1Ev
2262 // CHECK2-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
2263 // CHECK2-NEXT:  entry:
2264 // CHECK2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2265 // CHECK2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2266 // CHECK2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2267 // CHECK2-NEXT:    call void @_ZN2S4D2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR3]]
2268 // CHECK2-NEXT:    ret void
2269 //
2270 //
2271 // CHECK2-LABEL: define {{[^@]+}}@_ZN2S1C2Ei
2272 // CHECK2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
2273 // CHECK2-NEXT:  entry:
2274 // CHECK2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2275 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2276 // CHECK2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2277 // CHECK2-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
2278 // CHECK2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2279 // CHECK2-NEXT:    [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0
2280 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
2281 // CHECK2-NEXT:    store i32 [[TMP0]], ptr [[A2]], align 4
2282 // CHECK2-NEXT:    ret void
2283 //
2284 //
2285 // CHECK2-LABEL: define {{[^@]+}}@_ZN2S1D2Ev
2286 // CHECK2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
2287 // CHECK2-NEXT:  entry:
2288 // CHECK2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2289 // CHECK2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2290 // CHECK2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2291 // CHECK2-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0
2292 // CHECK2-NEXT:    store i32 0, ptr [[A]], align 4
2293 // CHECK2-NEXT:    ret void
2294 //
2295 //
2296 // CHECK2-LABEL: define {{[^@]+}}@_ZN2S2C2Ei
2297 // CHECK2-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
2298 // CHECK2-NEXT:  entry:
2299 // CHECK2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2300 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2301 // CHECK2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2302 // CHECK2-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
2303 // CHECK2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2304 // CHECK2-NEXT:    [[A2:%.*]] = getelementptr inbounds [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0
2305 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
2306 // CHECK2-NEXT:    store i32 [[TMP0]], ptr [[A2]], align 8
2307 // CHECK2-NEXT:    ret void
2308 //
2309 //
2310 // CHECK2-LABEL: define {{[^@]+}}@_ZN2S2D2Ev
2311 // CHECK2-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
2312 // CHECK2-NEXT:  entry:
2313 // CHECK2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2314 // CHECK2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2315 // CHECK2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2316 // CHECK2-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0
2317 // CHECK2-NEXT:    store i32 0, ptr [[A]], align 8
2318 // CHECK2-NEXT:    ret void
2319 //
2320 //
2321 // CHECK2-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC2Ei
2322 // CHECK2-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 {
2323 // CHECK2-NEXT:  entry:
2324 // CHECK2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2325 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2326 // CHECK2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2327 // CHECK2-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
2328 // CHECK2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2329 // CHECK2-NEXT:    [[A2:%.*]] = getelementptr inbounds [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0
2330 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
2331 // CHECK2-NEXT:    store i32 [[TMP0]], ptr [[A2]], align 8
2332 // CHECK2-NEXT:    ret void
2333 //
2334 //
2335 // CHECK2-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD2Ev
2336 // CHECK2-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 {
2337 // CHECK2-NEXT:  entry:
2338 // CHECK2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2339 // CHECK2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2340 // CHECK2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2341 // CHECK2-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0
2342 // CHECK2-NEXT:    store i32 0, ptr [[A]], align 8
2343 // CHECK2-NEXT:    ret void
2344 //
2345 //
2346 // CHECK2-LABEL: define {{[^@]+}}@_ZN2S4C2Ei
2347 // CHECK2-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
2348 // CHECK2-NEXT:  entry:
2349 // CHECK2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2350 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2351 // CHECK2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2352 // CHECK2-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
2353 // CHECK2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2354 // CHECK2-NEXT:    [[A2:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0
2355 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
2356 // CHECK2-NEXT:    store i32 [[TMP0]], ptr [[A2]], align 4
2357 // CHECK2-NEXT:    ret void
2358 //
2359 //
2360 // CHECK2-LABEL: define {{[^@]+}}@_ZN2S4D2Ev
2361 // CHECK2-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
2362 // CHECK2-NEXT:  entry:
2363 // CHECK2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2364 // CHECK2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2365 // CHECK2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2366 // CHECK2-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0
2367 // CHECK2-NEXT:    store i32 0, ptr [[A]], align 4
2368 // CHECK2-NEXT:    ret void
2369 //
2370 //
2371 // CHECK2-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_threadprivate_codegen.cpp
2372 // CHECK2-SAME: () #[[ATTR0]] {
2373 // CHECK2-NEXT:  entry:
2374 // CHECK2-NEXT:    call void @__cxx_global_var_init()
2375 // CHECK2-NEXT:    call void @.__omp_threadprivate_init_.()
2376 // CHECK2-NEXT:    call void @__cxx_global_var_init.1()
2377 // CHECK2-NEXT:    call void @__cxx_global_var_init.2()
2378 // CHECK2-NEXT:    call void @.__omp_threadprivate_init_..5()
2379 // CHECK2-NEXT:    ret void
2380 //
2381 //
2382 // SIMD1-LABEL: define {{[^@]+}}@__cxx_global_var_init
2383 // SIMD1-SAME: () #[[ATTR0:[0-9]+]] {
2384 // SIMD1-NEXT:  entry:
2385 // SIMD1-NEXT:    call void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @_ZL3gs1, i32 noundef 5)
2386 // SIMD1-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S1D1Ev, ptr @_ZL3gs1, ptr @__dso_handle) #[[ATTR3:[0-9]+]]
2387 // SIMD1-NEXT:    ret void
2388 //
2389 //
2390 // SIMD1-LABEL: define {{[^@]+}}@_ZN2S1C1Ei
2391 // SIMD1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
2392 // SIMD1-NEXT:  entry:
2393 // SIMD1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2394 // SIMD1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2395 // SIMD1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2396 // SIMD1-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
2397 // SIMD1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2398 // SIMD1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
2399 // SIMD1-NEXT:    call void @_ZN2S1C2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])
2400 // SIMD1-NEXT:    ret void
2401 //
2402 //
2403 // SIMD1-LABEL: define {{[^@]+}}@_ZN2S1D1Ev
2404 // SIMD1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 {
2405 // SIMD1-NEXT:  entry:
2406 // SIMD1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2407 // SIMD1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2408 // SIMD1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2409 // SIMD1-NEXT:    call void @_ZN2S1D2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]]
2410 // SIMD1-NEXT:    ret void
2411 //
2412 //
2413 // SIMD1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
2414 // SIMD1-SAME: () #[[ATTR0]] {
2415 // SIMD1-NEXT:  entry:
2416 // SIMD1-NEXT:    call void @_ZN2S2C1Ei(ptr noundef nonnull align 8 dereferenceable(16) @_ZL3gs2, i32 noundef 27)
2417 // SIMD1-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S2D1Ev, ptr @_ZL3gs2, ptr @__dso_handle) #[[ATTR3]]
2418 // SIMD1-NEXT:    ret void
2419 //
2420 //
2421 // SIMD1-LABEL: define {{[^@]+}}@_ZN2S2C1Ei
2422 // SIMD1-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2423 // SIMD1-NEXT:  entry:
2424 // SIMD1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2425 // SIMD1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2426 // SIMD1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2427 // SIMD1-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
2428 // SIMD1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2429 // SIMD1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
2430 // SIMD1-NEXT:    call void @_ZN2S2C2Ei(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], i32 noundef [[TMP0]])
2431 // SIMD1-NEXT:    ret void
2432 //
2433 //
2434 // SIMD1-LABEL: define {{[^@]+}}@_ZN2S2D1Ev
2435 // SIMD1-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
2436 // SIMD1-NEXT:  entry:
2437 // SIMD1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2438 // SIMD1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2439 // SIMD1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2440 // SIMD1-NEXT:    call void @_ZN2S2D2Ev(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]]) #[[ATTR3]]
2441 // SIMD1-NEXT:    ret void
2442 //
2443 //
2444 // SIMD1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
2445 // SIMD1-SAME: () #[[ATTR0]] personality ptr @__gxx_personality_v0 {
2446 // SIMD1-NEXT:  entry:
2447 // SIMD1-NEXT:    [[ARRAYINIT_ENDOFINIT:%.*]] = alloca ptr, align 8
2448 // SIMD1-NEXT:    [[ARRAYINIT_ENDOFINIT1:%.*]] = alloca ptr, align 8
2449 // SIMD1-NEXT:    [[EXN_SLOT:%.*]] = alloca ptr, align 8
2450 // SIMD1-NEXT:    [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4
2451 // SIMD1-NEXT:    [[ARRAYINIT_ENDOFINIT5:%.*]] = alloca ptr, align 8
2452 // SIMD1-NEXT:    store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT]], align 8
2453 // SIMD1-NEXT:    store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT1]], align 8
2454 // SIMD1-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @arr_x, i32 noundef 1)
2455 // SIMD1-NEXT:    to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]]
2456 // SIMD1:       invoke.cont:
2457 // SIMD1-NEXT:    store ptr getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT1]], align 8
2458 // SIMD1-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 1), i32 noundef 2)
2459 // SIMD1-NEXT:    to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD]]
2460 // SIMD1:       invoke.cont2:
2461 // SIMD1-NEXT:    store ptr getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), ptr [[ARRAYINIT_ENDOFINIT1]], align 8
2462 // SIMD1-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), i32 noundef 3)
2463 // SIMD1-NEXT:    to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]]
2464 // SIMD1:       invoke.cont3:
2465 // SIMD1-NEXT:    store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT]], align 8
2466 // SIMD1-NEXT:    store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8
2467 // SIMD1-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i32 noundef 4)
2468 // SIMD1-NEXT:    to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD6:%.*]]
2469 // SIMD1:       invoke.cont7:
2470 // SIMD1-NEXT:    store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8
2471 // SIMD1-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), i32 noundef 5)
2472 // SIMD1-NEXT:    to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD6]]
2473 // SIMD1:       invoke.cont8:
2474 // SIMD1-NEXT:    store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), ptr [[ARRAYINIT_ENDOFINIT5]], align 8
2475 // SIMD1-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), i32 noundef 6)
2476 // SIMD1-NEXT:    to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD6]]
2477 // SIMD1:       invoke.cont9:
2478 // SIMD1-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR3]]
2479 // SIMD1-NEXT:    ret void
2480 // SIMD1:       lpad:
2481 // SIMD1-NEXT:    [[TMP1:%.*]] = landingpad { ptr, i32 }
2482 // SIMD1-NEXT:    cleanup
2483 // SIMD1-NEXT:    [[TMP2:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 0
2484 // SIMD1-NEXT:    store ptr [[TMP2]], ptr [[EXN_SLOT]], align 8
2485 // SIMD1-NEXT:    [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 1
2486 // SIMD1-NEXT:    store i32 [[TMP3]], ptr [[EHSELECTOR_SLOT]], align 4
2487 // SIMD1-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT1]], align 8
2488 // SIMD1-NEXT:    [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr @arr_x, [[TMP4]]
2489 // SIMD1-NEXT:    br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY:%.*]]
2490 // SIMD1:       arraydestroy.body:
2491 // SIMD1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP4]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2492 // SIMD1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
2493 // SIMD1-NEXT:    call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]]
2494 // SIMD1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x
2495 // SIMD1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4]], label [[ARRAYDESTROY_BODY]]
2496 // SIMD1:       arraydestroy.done4:
2497 // SIMD1-NEXT:    br label [[EHCLEANUP:%.*]]
2498 // SIMD1:       lpad6:
2499 // SIMD1-NEXT:    [[TMP5:%.*]] = landingpad { ptr, i32 }
2500 // SIMD1-NEXT:    cleanup
2501 // SIMD1-NEXT:    [[TMP6:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 0
2502 // SIMD1-NEXT:    store ptr [[TMP6]], ptr [[EXN_SLOT]], align 8
2503 // SIMD1-NEXT:    [[TMP7:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 1
2504 // SIMD1-NEXT:    store i32 [[TMP7]], ptr [[EHSELECTOR_SLOT]], align 4
2505 // SIMD1-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT5]], align 8
2506 // SIMD1-NEXT:    [[ARRAYDESTROY_ISEMPTY10:%.*]] = icmp eq ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), [[TMP8]]
2507 // SIMD1-NEXT:    br i1 [[ARRAYDESTROY_ISEMPTY10]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY11:%.*]]
2508 // SIMD1:       arraydestroy.body11:
2509 // SIMD1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST12:%.*]] = phi ptr [ [[TMP8]], [[LPAD6]] ], [ [[ARRAYDESTROY_ELEMENT13:%.*]], [[ARRAYDESTROY_BODY11]] ]
2510 // SIMD1-NEXT:    [[ARRAYDESTROY_ELEMENT13]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST12]], i64 -1
2511 // SIMD1-NEXT:    call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR3]]
2512 // SIMD1-NEXT:    [[ARRAYDESTROY_DONE14:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1)
2513 // SIMD1-NEXT:    br i1 [[ARRAYDESTROY_DONE14]], label [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_BODY11]]
2514 // SIMD1:       arraydestroy.done15:
2515 // SIMD1-NEXT:    br label [[EHCLEANUP]]
2516 // SIMD1:       ehcleanup:
2517 // SIMD1-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT]], align 8
2518 // SIMD1-NEXT:    [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP9]], i64 0, i64 0
2519 // SIMD1-NEXT:    [[ARRAYDESTROY_ISEMPTY16:%.*]] = icmp eq ptr @arr_x, [[PAD_ARRAYEND]]
2520 // SIMD1-NEXT:    br i1 [[ARRAYDESTROY_ISEMPTY16]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17:%.*]]
2521 // SIMD1:       arraydestroy.body17:
2522 // SIMD1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi ptr [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ]
2523 // SIMD1-NEXT:    [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1
2524 // SIMD1-NEXT:    call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]]
2525 // SIMD1-NEXT:    [[ARRAYDESTROY_DONE20:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT19]], @arr_x
2526 // SIMD1-NEXT:    br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]]
2527 // SIMD1:       arraydestroy.done21:
2528 // SIMD1-NEXT:    br label [[EH_RESUME:%.*]]
2529 // SIMD1:       eh.resume:
2530 // SIMD1-NEXT:    [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8
2531 // SIMD1-NEXT:    [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4
2532 // SIMD1-NEXT:    [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0
2533 // SIMD1-NEXT:    [[LPAD_VAL22:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1
2534 // SIMD1-NEXT:    resume { ptr, i32 } [[LPAD_VAL22]]
2535 //
2536 //
2537 // SIMD1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
2538 // SIMD1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {
2539 // SIMD1-NEXT:  entry:
2540 // SIMD1-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
2541 // SIMD1-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
2542 // SIMD1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
2543 // SIMD1:       arraydestroy.body:
2544 // SIMD1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 6), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2545 // SIMD1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
2546 // SIMD1-NEXT:    call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]]
2547 // SIMD1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x
2548 // SIMD1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
2549 // SIMD1:       arraydestroy.done1:
2550 // SIMD1-NEXT:    ret void
2551 //
2552 //
2553 // SIMD1-LABEL: define {{[^@]+}}@main
2554 // SIMD1-SAME: () #[[ATTR4:[0-9]+]] personality ptr @__gxx_personality_v0 {
2555 // SIMD1-NEXT:  entry:
2556 // SIMD1-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
2557 // SIMD1-NEXT:    [[RES:%.*]] = alloca i32, align 4
2558 // SIMD1-NEXT:    [[EXN_SLOT:%.*]] = alloca ptr, align 8
2559 // SIMD1-NEXT:    [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4
2560 // SIMD1-NEXT:    store i32 0, ptr [[RETVAL]], align 4
2561 // SIMD1-NEXT:    [[TMP0:%.*]] = load atomic i8, ptr @_ZGVZ4mainE2sm acquire, align 8
2562 // SIMD1-NEXT:    [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0
2563 // SIMD1-NEXT:    br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF2:![0-9]+]]
2564 // SIMD1:       init.check:
2565 // SIMD1-NEXT:    [[TMP1:%.*]] = call i32 @__cxa_guard_acquire(ptr @_ZGVZ4mainE2sm) #[[ATTR3]]
2566 // SIMD1-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0
2567 // SIMD1-NEXT:    br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]]
2568 // SIMD1:       init:
2569 // SIMD1-NEXT:    [[TMP2:%.*]] = load i32, ptr @_ZL3gs1, align 4
2570 // SIMD1-NEXT:    invoke void @_ZZ4mainEN5SmainC1Ei(ptr noundef nonnull align 8 dereferenceable(24) @_ZZ4mainE2sm, i32 noundef [[TMP2]])
2571 // SIMD1-NEXT:    to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]]
2572 // SIMD1:       invoke.cont:
2573 // SIMD1-NEXT:    [[TMP3:%.*]] = call i32 @__cxa_atexit(ptr @_ZZ4mainEN5SmainD1Ev, ptr @_ZZ4mainE2sm, ptr @__dso_handle) #[[ATTR3]]
2574 // SIMD1-NEXT:    call void @__cxa_guard_release(ptr @_ZGVZ4mainE2sm) #[[ATTR3]]
2575 // SIMD1-NEXT:    br label [[INIT_END]]
2576 // SIMD1:       init.end:
2577 // SIMD1-NEXT:    [[TMP4:%.*]] = load i32, ptr @_ZN6Static1sE, align 4
2578 // SIMD1-NEXT:    store i32 [[TMP4]], ptr [[RES]], align 4
2579 // SIMD1-NEXT:    [[TMP5:%.*]] = load i32, ptr @_ZZ4mainE2sm, align 8
2580 // SIMD1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[RES]], align 4
2581 // SIMD1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]]
2582 // SIMD1-NEXT:    store i32 [[ADD]], ptr [[RES]], align 4
2583 // SIMD1-NEXT:    [[TMP7:%.*]] = load i32, ptr @_ZL3gs1, align 4
2584 // SIMD1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[RES]], align 4
2585 // SIMD1-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP8]], [[TMP7]]
2586 // SIMD1-NEXT:    store i32 [[ADD1]], ptr [[RES]], align 4
2587 // SIMD1-NEXT:    [[TMP9:%.*]] = load i32, ptr @_ZL3gs2, align 8
2588 // SIMD1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[RES]], align 4
2589 // SIMD1-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]
2590 // SIMD1-NEXT:    store i32 [[ADD2]], ptr [[RES]], align 4
2591 // SIMD1-NEXT:    [[TMP11:%.*]] = load i32, ptr @gs3, align 4
2592 // SIMD1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[RES]], align 4
2593 // SIMD1-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]]
2594 // SIMD1-NEXT:    store i32 [[ADD3]], ptr [[RES]], align 4
2595 // SIMD1-NEXT:    [[TMP13:%.*]] = load i32, ptr getelementptr inbounds ([2 x [3 x %struct.S1]], ptr @arr_x, i64 0, i64 1, i64 1), align 4
2596 // SIMD1-NEXT:    [[TMP14:%.*]] = load i32, ptr [[RES]], align 4
2597 // SIMD1-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP14]], [[TMP13]]
2598 // SIMD1-NEXT:    store i32 [[ADD4]], ptr [[RES]], align 4
2599 // SIMD1-NEXT:    [[TMP15:%.*]] = load i32, ptr @_ZN2STIiE2stE, align 4
2600 // SIMD1-NEXT:    [[TMP16:%.*]] = load i32, ptr [[RES]], align 4
2601 // SIMD1-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP16]], [[TMP15]]
2602 // SIMD1-NEXT:    store i32 [[ADD5]], ptr [[RES]], align 4
2603 // SIMD1-NEXT:    [[TMP17:%.*]] = load float, ptr @_ZN2STIfE2stE, align 4
2604 // SIMD1-NEXT:    [[CONV:%.*]] = fptosi float [[TMP17]] to i32
2605 // SIMD1-NEXT:    [[TMP18:%.*]] = load i32, ptr [[RES]], align 4
2606 // SIMD1-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP18]], [[CONV]]
2607 // SIMD1-NEXT:    store i32 [[ADD6]], ptr [[RES]], align 4
2608 // SIMD1-NEXT:    [[TMP19:%.*]] = load i32, ptr @_ZN2STI2S4E2stE, align 4
2609 // SIMD1-NEXT:    [[TMP20:%.*]] = load i32, ptr [[RES]], align 4
2610 // SIMD1-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP20]], [[TMP19]]
2611 // SIMD1-NEXT:    store i32 [[ADD7]], ptr [[RES]], align 4
2612 // SIMD1-NEXT:    [[TMP21:%.*]] = load i32, ptr [[RES]], align 4
2613 // SIMD1-NEXT:    ret i32 [[TMP21]]
2614 // SIMD1:       lpad:
2615 // SIMD1-NEXT:    [[TMP22:%.*]] = landingpad { ptr, i32 }
2616 // SIMD1-NEXT:    cleanup
2617 // SIMD1-NEXT:    [[TMP23:%.*]] = extractvalue { ptr, i32 } [[TMP22]], 0
2618 // SIMD1-NEXT:    store ptr [[TMP23]], ptr [[EXN_SLOT]], align 8
2619 // SIMD1-NEXT:    [[TMP24:%.*]] = extractvalue { ptr, i32 } [[TMP22]], 1
2620 // SIMD1-NEXT:    store i32 [[TMP24]], ptr [[EHSELECTOR_SLOT]], align 4
2621 // SIMD1-NEXT:    call void @__cxa_guard_abort(ptr @_ZGVZ4mainE2sm) #[[ATTR3]]
2622 // SIMD1-NEXT:    br label [[EH_RESUME:%.*]]
2623 // SIMD1:       eh.resume:
2624 // SIMD1-NEXT:    [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8
2625 // SIMD1-NEXT:    [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4
2626 // SIMD1-NEXT:    [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0
2627 // SIMD1-NEXT:    [[LPAD_VAL8:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1
2628 // SIMD1-NEXT:    resume { ptr, i32 } [[LPAD_VAL8]]
2629 //
2630 //
2631 // SIMD1-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC1Ei
2632 // SIMD1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
2633 // SIMD1-NEXT:  entry:
2634 // SIMD1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2635 // SIMD1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2636 // SIMD1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2637 // SIMD1-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
2638 // SIMD1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2639 // SIMD1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
2640 // SIMD1-NEXT:    call void @_ZZ4mainEN5SmainC2Ei(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]], i32 noundef [[TMP0]])
2641 // SIMD1-NEXT:    ret void
2642 //
2643 //
2644 // SIMD1-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD1Ev
2645 // SIMD1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 {
2646 // SIMD1-NEXT:  entry:
2647 // SIMD1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2648 // SIMD1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2649 // SIMD1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2650 // SIMD1-NEXT:    call void @_ZZ4mainEN5SmainD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR3]]
2651 // SIMD1-NEXT:    ret void
2652 //
2653 //
2654 // SIMD1-LABEL: define {{[^@]+}}@_Z6foobarv
2655 // SIMD1-SAME: () #[[ATTR5:[0-9]+]] {
2656 // SIMD1-NEXT:  entry:
2657 // SIMD1-NEXT:    [[RES:%.*]] = alloca i32, align 4
2658 // SIMD1-NEXT:    [[TMP0:%.*]] = load i32, ptr @_ZN6Static1sE, align 4
2659 // SIMD1-NEXT:    store i32 [[TMP0]], ptr [[RES]], align 4
2660 // SIMD1-NEXT:    [[TMP1:%.*]] = load i32, ptr @_ZL3gs1, align 4
2661 // SIMD1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[RES]], align 4
2662 // SIMD1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP2]], [[TMP1]]
2663 // SIMD1-NEXT:    store i32 [[ADD]], ptr [[RES]], align 4
2664 // SIMD1-NEXT:    [[TMP3:%.*]] = load i32, ptr @_ZL3gs2, align 8
2665 // SIMD1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[RES]], align 4
2666 // SIMD1-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP4]], [[TMP3]]
2667 // SIMD1-NEXT:    store i32 [[ADD1]], ptr [[RES]], align 4
2668 // SIMD1-NEXT:    [[TMP5:%.*]] = load i32, ptr @gs3, align 4
2669 // SIMD1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[RES]], align 4
2670 // SIMD1-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP6]], [[TMP5]]
2671 // SIMD1-NEXT:    store i32 [[ADD2]], ptr [[RES]], align 4
2672 // SIMD1-NEXT:    [[TMP7:%.*]] = load i32, ptr getelementptr inbounds ([2 x [3 x %struct.S1]], ptr @arr_x, i64 0, i64 1, i64 1), align 4
2673 // SIMD1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[RES]], align 4
2674 // SIMD1-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP8]], [[TMP7]]
2675 // SIMD1-NEXT:    store i32 [[ADD3]], ptr [[RES]], align 4
2676 // SIMD1-NEXT:    [[TMP9:%.*]] = load i32, ptr @_ZN2STIiE2stE, align 4
2677 // SIMD1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[RES]], align 4
2678 // SIMD1-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]
2679 // SIMD1-NEXT:    store i32 [[ADD4]], ptr [[RES]], align 4
2680 // SIMD1-NEXT:    [[TMP11:%.*]] = load float, ptr @_ZN2STIfE2stE, align 4
2681 // SIMD1-NEXT:    [[CONV:%.*]] = fptosi float [[TMP11]] to i32
2682 // SIMD1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[RES]], align 4
2683 // SIMD1-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP12]], [[CONV]]
2684 // SIMD1-NEXT:    store i32 [[ADD5]], ptr [[RES]], align 4
2685 // SIMD1-NEXT:    [[TMP13:%.*]] = load i32, ptr @_ZN2STI2S4E2stE, align 4
2686 // SIMD1-NEXT:    [[TMP14:%.*]] = load i32, ptr [[RES]], align 4
2687 // SIMD1-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP14]], [[TMP13]]
2688 // SIMD1-NEXT:    store i32 [[ADD6]], ptr [[RES]], align 4
2689 // SIMD1-NEXT:    [[TMP15:%.*]] = load i32, ptr [[RES]], align 4
2690 // SIMD1-NEXT:    ret i32 [[TMP15]]
2691 //
2692 //
2693 // SIMD1-LABEL: define {{[^@]+}}@__cxx_global_var_init.3
2694 // SIMD1-SAME: () #[[ATTR0]] comdat($_ZN2STI2S4E2stE) {
2695 // SIMD1-NEXT:  entry:
2696 // SIMD1-NEXT:    [[TMP0:%.*]] = load i8, ptr @_ZGVN2STI2S4E2stE, align 8
2697 // SIMD1-NEXT:    [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0
2698 // SIMD1-NEXT:    br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]]
2699 // SIMD1:       init.check:
2700 // SIMD1-NEXT:    store i8 1, ptr @_ZGVN2STI2S4E2stE, align 8
2701 // SIMD1-NEXT:    call void @_ZN2S4C1Ei(ptr noundef nonnull align 4 dereferenceable(8) @_ZN2STI2S4E2stE, i32 noundef 23)
2702 // SIMD1-NEXT:    [[TMP1:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S4D1Ev, ptr @_ZN2STI2S4E2stE, ptr @__dso_handle) #[[ATTR3]]
2703 // SIMD1-NEXT:    br label [[INIT_END]]
2704 // SIMD1:       init.end:
2705 // SIMD1-NEXT:    ret void
2706 //
2707 //
2708 // SIMD1-LABEL: define {{[^@]+}}@_ZN2S4C1Ei
2709 // SIMD1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2710 // SIMD1-NEXT:  entry:
2711 // SIMD1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2712 // SIMD1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2713 // SIMD1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2714 // SIMD1-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
2715 // SIMD1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2716 // SIMD1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
2717 // SIMD1-NEXT:    call void @_ZN2S4C2Ei(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]], i32 noundef [[TMP0]])
2718 // SIMD1-NEXT:    ret void
2719 //
2720 //
2721 // SIMD1-LABEL: define {{[^@]+}}@_ZN2S4D1Ev
2722 // SIMD1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
2723 // SIMD1-NEXT:  entry:
2724 // SIMD1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2725 // SIMD1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2726 // SIMD1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2727 // SIMD1-NEXT:    call void @_ZN2S4D2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR3]]
2728 // SIMD1-NEXT:    ret void
2729 //
2730 //
2731 // SIMD1-LABEL: define {{[^@]+}}@_ZN2S1C2Ei
2732 // SIMD1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
2733 // SIMD1-NEXT:  entry:
2734 // SIMD1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2735 // SIMD1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2736 // SIMD1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2737 // SIMD1-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
2738 // SIMD1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2739 // SIMD1-NEXT:    [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0
2740 // SIMD1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
2741 // SIMD1-NEXT:    store i32 [[TMP0]], ptr [[A2]], align 4
2742 // SIMD1-NEXT:    ret void
2743 //
2744 //
2745 // SIMD1-LABEL: define {{[^@]+}}@_ZN2S1D2Ev
2746 // SIMD1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
2747 // SIMD1-NEXT:  entry:
2748 // SIMD1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2749 // SIMD1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2750 // SIMD1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2751 // SIMD1-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0
2752 // SIMD1-NEXT:    store i32 0, ptr [[A]], align 4
2753 // SIMD1-NEXT:    ret void
2754 //
2755 //
2756 // SIMD1-LABEL: define {{[^@]+}}@_ZN2S2C2Ei
2757 // SIMD1-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
2758 // SIMD1-NEXT:  entry:
2759 // SIMD1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2760 // SIMD1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2761 // SIMD1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2762 // SIMD1-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
2763 // SIMD1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2764 // SIMD1-NEXT:    [[A2:%.*]] = getelementptr inbounds [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0
2765 // SIMD1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
2766 // SIMD1-NEXT:    store i32 [[TMP0]], ptr [[A2]], align 8
2767 // SIMD1-NEXT:    ret void
2768 //
2769 //
2770 // SIMD1-LABEL: define {{[^@]+}}@_ZN2S2D2Ev
2771 // SIMD1-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
2772 // SIMD1-NEXT:  entry:
2773 // SIMD1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2774 // SIMD1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2775 // SIMD1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2776 // SIMD1-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0
2777 // SIMD1-NEXT:    store i32 0, ptr [[A]], align 8
2778 // SIMD1-NEXT:    ret void
2779 //
2780 //
2781 // SIMD1-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC2Ei
2782 // SIMD1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 {
2783 // SIMD1-NEXT:  entry:
2784 // SIMD1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2785 // SIMD1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2786 // SIMD1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2787 // SIMD1-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
2788 // SIMD1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2789 // SIMD1-NEXT:    [[A2:%.*]] = getelementptr inbounds [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0
2790 // SIMD1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
2791 // SIMD1-NEXT:    store i32 [[TMP0]], ptr [[A2]], align 8
2792 // SIMD1-NEXT:    ret void
2793 //
2794 //
2795 // SIMD1-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD2Ev
2796 // SIMD1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 {
2797 // SIMD1-NEXT:  entry:
2798 // SIMD1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2799 // SIMD1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2800 // SIMD1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2801 // SIMD1-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0
2802 // SIMD1-NEXT:    store i32 0, ptr [[A]], align 8
2803 // SIMD1-NEXT:    ret void
2804 //
2805 //
2806 // SIMD1-LABEL: define {{[^@]+}}@_ZN2S4C2Ei
2807 // SIMD1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
2808 // SIMD1-NEXT:  entry:
2809 // SIMD1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2810 // SIMD1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2811 // SIMD1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2812 // SIMD1-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
2813 // SIMD1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2814 // SIMD1-NEXT:    [[A2:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0
2815 // SIMD1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
2816 // SIMD1-NEXT:    store i32 [[TMP0]], ptr [[A2]], align 4
2817 // SIMD1-NEXT:    ret void
2818 //
2819 //
2820 // SIMD1-LABEL: define {{[^@]+}}@_ZN2S4D2Ev
2821 // SIMD1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
2822 // SIMD1-NEXT:  entry:
2823 // SIMD1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2824 // SIMD1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2825 // SIMD1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2826 // SIMD1-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0
2827 // SIMD1-NEXT:    store i32 0, ptr [[A]], align 4
2828 // SIMD1-NEXT:    ret void
2829 //
2830 //
2831 // SIMD1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_threadprivate_codegen.cpp
2832 // SIMD1-SAME: () #[[ATTR0]] {
2833 // SIMD1-NEXT:  entry:
2834 // SIMD1-NEXT:    call void @__cxx_global_var_init()
2835 // SIMD1-NEXT:    call void @__cxx_global_var_init.1()
2836 // SIMD1-NEXT:    call void @__cxx_global_var_init.2()
2837 // SIMD1-NEXT:    ret void
2838 //
2839 //
2840 // SIMD2-LABEL: define {{[^@]+}}@__cxx_global_var_init
2841 // SIMD2-SAME: () #[[ATTR0:[0-9]+]] !dbg [[DBG115:![0-9]+]] {
2842 // SIMD2-NEXT:  entry:
2843 // SIMD2-NEXT:    call void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @_ZL3gs1, i32 noundef 5), !dbg [[DBG119:![0-9]+]]
2844 // SIMD2-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S1D1Ev, ptr @_ZL3gs1, ptr @__dso_handle) #[[ATTR3:[0-9]+]], !dbg [[DBG121:![0-9]+]]
2845 // SIMD2-NEXT:    ret void, !dbg [[DBG122:![0-9]+]]
2846 //
2847 //
2848 // SIMD2-LABEL: define {{[^@]+}}@_ZN2S1C1Ei
2849 // SIMD2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 !dbg [[DBG123:![0-9]+]] {
2850 // SIMD2-NEXT:  entry:
2851 // SIMD2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2852 // SIMD2-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2853 // SIMD2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2854 // SIMD2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META124:![0-9]+]], metadata !DIExpression()), !dbg [[DBG126:![0-9]+]]
2855 // SIMD2-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
2856 // SIMD2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META127:![0-9]+]], metadata !DIExpression()), !dbg [[DBG128:![0-9]+]]
2857 // SIMD2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2858 // SIMD2-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG129:![0-9]+]]
2859 // SIMD2-NEXT:    call void @_ZN2S1C2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG129]]
2860 // SIMD2-NEXT:    ret void, !dbg [[DBG130:![0-9]+]]
2861 //
2862 //
2863 // SIMD2-LABEL: define {{[^@]+}}@_ZN2S1D1Ev
2864 // SIMD2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 !dbg [[DBG131:![0-9]+]] {
2865 // SIMD2-NEXT:  entry:
2866 // SIMD2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2867 // SIMD2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2868 // SIMD2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META132:![0-9]+]], metadata !DIExpression()), !dbg [[DBG133:![0-9]+]]
2869 // SIMD2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2870 // SIMD2-NEXT:    call void @_ZN2S1D2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]], !dbg [[DBG134:![0-9]+]]
2871 // SIMD2-NEXT:    ret void, !dbg [[DBG135:![0-9]+]]
2872 //
2873 //
2874 // SIMD2-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
2875 // SIMD2-SAME: () #[[ATTR0]] !dbg [[DBG136:![0-9]+]] {
2876 // SIMD2-NEXT:  entry:
2877 // SIMD2-NEXT:    call void @_ZN2S2C1Ei(ptr noundef nonnull align 8 dereferenceable(16) @_ZL3gs2, i32 noundef 27), !dbg [[DBG137:![0-9]+]]
2878 // SIMD2-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S2D1Ev, ptr @_ZL3gs2, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG139:![0-9]+]]
2879 // SIMD2-NEXT:    ret void, !dbg [[DBG140:![0-9]+]]
2880 //
2881 //
2882 // SIMD2-LABEL: define {{[^@]+}}@_ZN2S2C1Ei
2883 // SIMD2-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 !dbg [[DBG141:![0-9]+]] {
2884 // SIMD2-NEXT:  entry:
2885 // SIMD2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2886 // SIMD2-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2887 // SIMD2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2888 // SIMD2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META142:![0-9]+]], metadata !DIExpression()), !dbg [[DBG144:![0-9]+]]
2889 // SIMD2-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
2890 // SIMD2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META145:![0-9]+]], metadata !DIExpression()), !dbg [[DBG146:![0-9]+]]
2891 // SIMD2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2892 // SIMD2-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG147:![0-9]+]]
2893 // SIMD2-NEXT:    call void @_ZN2S2C2Ei(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG147]]
2894 // SIMD2-NEXT:    ret void, !dbg [[DBG148:![0-9]+]]
2895 //
2896 //
2897 // SIMD2-LABEL: define {{[^@]+}}@_ZN2S2D1Ev
2898 // SIMD2-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG149:![0-9]+]] {
2899 // SIMD2-NEXT:  entry:
2900 // SIMD2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
2901 // SIMD2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
2902 // SIMD2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META150:![0-9]+]], metadata !DIExpression()), !dbg [[DBG151:![0-9]+]]
2903 // SIMD2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
2904 // SIMD2-NEXT:    call void @_ZN2S2D2Ev(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]]) #[[ATTR3]], !dbg [[DBG152:![0-9]+]]
2905 // SIMD2-NEXT:    ret void, !dbg [[DBG153:![0-9]+]]
2906 //
2907 //
2908 // SIMD2-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
2909 // SIMD2-SAME: () #[[ATTR0]] personality ptr @__gxx_personality_v0 !dbg [[DBG154:![0-9]+]] {
2910 // SIMD2-NEXT:  entry:
2911 // SIMD2-NEXT:    [[ARRAYINIT_ENDOFINIT:%.*]] = alloca ptr, align 8
2912 // SIMD2-NEXT:    [[ARRAYINIT_ENDOFINIT1:%.*]] = alloca ptr, align 8
2913 // SIMD2-NEXT:    [[EXN_SLOT:%.*]] = alloca ptr, align 8
2914 // SIMD2-NEXT:    [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4
2915 // SIMD2-NEXT:    [[ARRAYINIT_ENDOFINIT5:%.*]] = alloca ptr, align 8
2916 // SIMD2-NEXT:    store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG155:![0-9]+]]
2917 // SIMD2-NEXT:    store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG157:![0-9]+]]
2918 // SIMD2-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @arr_x, i32 noundef 1)
2919 // SIMD2-NEXT:    to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG158:![0-9]+]]
2920 // SIMD2:       invoke.cont:
2921 // SIMD2-NEXT:    store ptr getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG157]]
2922 // SIMD2-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 1), i32 noundef 2)
2923 // SIMD2-NEXT:    to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD]], !dbg [[DBG159:![0-9]+]]
2924 // SIMD2:       invoke.cont2:
2925 // SIMD2-NEXT:    store ptr getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG157]]
2926 // SIMD2-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), i32 noundef 3)
2927 // SIMD2-NEXT:    to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]], !dbg [[DBG160:![0-9]+]]
2928 // SIMD2:       invoke.cont3:
2929 // SIMD2-NEXT:    store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG155]]
2930 // SIMD2-NEXT:    store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG161:![0-9]+]]
2931 // SIMD2-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i32 noundef 4)
2932 // SIMD2-NEXT:    to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD6:%.*]], !dbg [[DBG162:![0-9]+]]
2933 // SIMD2:       invoke.cont7:
2934 // SIMD2-NEXT:    store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG161]]
2935 // SIMD2-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), i32 noundef 5)
2936 // SIMD2-NEXT:    to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD6]], !dbg [[DBG163:![0-9]+]]
2937 // SIMD2:       invoke.cont8:
2938 // SIMD2-NEXT:    store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG161]]
2939 // SIMD2-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), i32 noundef 6)
2940 // SIMD2-NEXT:    to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD6]], !dbg [[DBG164:![0-9]+]]
2941 // SIMD2:       invoke.cont9:
2942 // SIMD2-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG165:![0-9]+]]
2943 // SIMD2-NEXT:    ret void, !dbg [[DBG165]]
2944 // SIMD2:       lpad:
2945 // SIMD2-NEXT:    [[TMP1:%.*]] = landingpad { ptr, i32 }
2946 // SIMD2-NEXT:    cleanup, !dbg [[DBG166:![0-9]+]]
2947 // SIMD2-NEXT:    [[TMP2:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 0, !dbg [[DBG166]]
2948 // SIMD2-NEXT:    store ptr [[TMP2]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG166]]
2949 // SIMD2-NEXT:    [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 1, !dbg [[DBG166]]
2950 // SIMD2-NEXT:    store i32 [[TMP3]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG166]]
2951 // SIMD2-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG157]]
2952 // SIMD2-NEXT:    [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr @arr_x, [[TMP4]], !dbg [[DBG157]]
2953 // SIMD2-NEXT:    br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG157]]
2954 // SIMD2:       arraydestroy.body:
2955 // SIMD2-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP4]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG157]]
2956 // SIMD2-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG157]]
2957 // SIMD2-NEXT:    call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG157]]
2958 // SIMD2-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[DBG157]]
2959 // SIMD2-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG157]]
2960 // SIMD2:       arraydestroy.done4:
2961 // SIMD2-NEXT:    br label [[EHCLEANUP:%.*]], !dbg [[DBG157]]
2962 // SIMD2:       lpad6:
2963 // SIMD2-NEXT:    [[TMP5:%.*]] = landingpad { ptr, i32 }
2964 // SIMD2-NEXT:    cleanup, !dbg [[DBG166]]
2965 // SIMD2-NEXT:    [[TMP6:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 0, !dbg [[DBG166]]
2966 // SIMD2-NEXT:    store ptr [[TMP6]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG166]]
2967 // SIMD2-NEXT:    [[TMP7:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 1, !dbg [[DBG166]]
2968 // SIMD2-NEXT:    store i32 [[TMP7]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG166]]
2969 // SIMD2-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG161]]
2970 // SIMD2-NEXT:    [[ARRAYDESTROY_ISEMPTY10:%.*]] = icmp eq ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), [[TMP8]], !dbg [[DBG161]]
2971 // SIMD2-NEXT:    br i1 [[ARRAYDESTROY_ISEMPTY10]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY11:%.*]], !dbg [[DBG161]]
2972 // SIMD2:       arraydestroy.body11:
2973 // SIMD2-NEXT:    [[ARRAYDESTROY_ELEMENTPAST12:%.*]] = phi ptr [ [[TMP8]], [[LPAD6]] ], [ [[ARRAYDESTROY_ELEMENT13:%.*]], [[ARRAYDESTROY_BODY11]] ], !dbg [[DBG161]]
2974 // SIMD2-NEXT:    [[ARRAYDESTROY_ELEMENT13]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST12]], i64 -1, !dbg [[DBG161]]
2975 // SIMD2-NEXT:    call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR3]], !dbg [[DBG161]]
2976 // SIMD2-NEXT:    [[ARRAYDESTROY_DONE14:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), !dbg [[DBG161]]
2977 // SIMD2-NEXT:    br i1 [[ARRAYDESTROY_DONE14]], label [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_BODY11]], !dbg [[DBG161]]
2978 // SIMD2:       arraydestroy.done15:
2979 // SIMD2-NEXT:    br label [[EHCLEANUP]], !dbg [[DBG161]]
2980 // SIMD2:       ehcleanup:
2981 // SIMD2-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG155]]
2982 // SIMD2-NEXT:    [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP9]], i64 0, i64 0, !dbg [[DBG155]]
2983 // SIMD2-NEXT:    [[ARRAYDESTROY_ISEMPTY16:%.*]] = icmp eq ptr @arr_x, [[PAD_ARRAYEND]], !dbg [[DBG155]]
2984 // SIMD2-NEXT:    br i1 [[ARRAYDESTROY_ISEMPTY16]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17:%.*]], !dbg [[DBG155]]
2985 // SIMD2:       arraydestroy.body17:
2986 // SIMD2-NEXT:    [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi ptr [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ], !dbg [[DBG155]]
2987 // SIMD2-NEXT:    [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1, !dbg [[DBG155]]
2988 // SIMD2-NEXT:    call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]], !dbg [[DBG155]]
2989 // SIMD2-NEXT:    [[ARRAYDESTROY_DONE20:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT19]], @arr_x, !dbg [[DBG155]]
2990 // SIMD2-NEXT:    br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]], !dbg [[DBG155]]
2991 // SIMD2:       arraydestroy.done21:
2992 // SIMD2-NEXT:    br label [[EH_RESUME:%.*]], !dbg [[DBG155]]
2993 // SIMD2:       eh.resume:
2994 // SIMD2-NEXT:    [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG155]]
2995 // SIMD2-NEXT:    [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG155]]
2996 // SIMD2-NEXT:    [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG155]]
2997 // SIMD2-NEXT:    [[LPAD_VAL22:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG155]]
2998 // SIMD2-NEXT:    resume { ptr, i32 } [[LPAD_VAL22]], !dbg [[DBG155]]
2999 //
3000 //
3001 // SIMD2-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
3002 // SIMD2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG167:![0-9]+]] {
3003 // SIMD2-NEXT:  entry:
3004 // SIMD2-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
3005 // SIMD2-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
3006 // SIMD2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[DOTADDR]], metadata [[META171:![0-9]+]], metadata !DIExpression()), !dbg [[DBG172:![0-9]+]]
3007 // SIMD2-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG172]]
3008 // SIMD2:       arraydestroy.body:
3009 // SIMD2-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 6), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG172]]
3010 // SIMD2-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG172]]
3011 // SIMD2-NEXT:    call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG172]]
3012 // SIMD2-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[DBG172]]
3013 // SIMD2-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG172]]
3014 // SIMD2:       arraydestroy.done1:
3015 // SIMD2-NEXT:    ret void, !dbg [[DBG172]]
3016 //
3017 //
3018 // SIMD2-LABEL: define {{[^@]+}}@main
3019 // SIMD2-SAME: () #[[ATTR5:[0-9]+]] personality ptr @__gxx_personality_v0 !dbg [[DBG52:![0-9]+]] {
3020 // SIMD2-NEXT:  entry:
3021 // SIMD2-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
3022 // SIMD2-NEXT:    [[RES:%.*]] = alloca i32, align 4
3023 // SIMD2-NEXT:    [[EXN_SLOT:%.*]] = alloca ptr, align 8
3024 // SIMD2-NEXT:    [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4
3025 // SIMD2-NEXT:    store i32 0, ptr [[RETVAL]], align 4
3026 // SIMD2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[RES]], metadata [[META173:![0-9]+]], metadata !DIExpression()), !dbg [[DBG174:![0-9]+]]
3027 // SIMD2-NEXT:    [[TMP0:%.*]] = load atomic i8, ptr @_ZGVZ4mainE2sm acquire, align 8, !dbg [[DBG175:![0-9]+]]
3028 // SIMD2-NEXT:    [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG175]]
3029 // SIMD2-NEXT:    br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG175]], !prof [[PROF176:![0-9]+]]
3030 // SIMD2:       init.check:
3031 // SIMD2-NEXT:    [[TMP1:%.*]] = call i32 @__cxa_guard_acquire(ptr @_ZGVZ4mainE2sm) #[[ATTR3]], !dbg [[DBG175]]
3032 // SIMD2-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0, !dbg [[DBG175]]
3033 // SIMD2-NEXT:    br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]], !dbg [[DBG175]]
3034 // SIMD2:       init:
3035 // SIMD2-NEXT:    [[TMP2:%.*]] = load i32, ptr @_ZL3gs1, align 4, !dbg [[DBG177:![0-9]+]]
3036 // SIMD2-NEXT:    invoke void @_ZZ4mainEN5SmainC1Ei(ptr noundef nonnull align 8 dereferenceable(24) @_ZZ4mainE2sm, i32 noundef [[TMP2]])
3037 // SIMD2-NEXT:    to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG178:![0-9]+]]
3038 // SIMD2:       invoke.cont:
3039 // SIMD2-NEXT:    [[TMP3:%.*]] = call i32 @__cxa_atexit(ptr @_ZZ4mainEN5SmainD1Ev, ptr @_ZZ4mainE2sm, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG175]]
3040 // SIMD2-NEXT:    call void @__cxa_guard_release(ptr @_ZGVZ4mainE2sm) #[[ATTR3]], !dbg [[DBG175]]
3041 // SIMD2-NEXT:    br label [[INIT_END]], !dbg [[DBG175]]
3042 // SIMD2:       init.end:
3043 // SIMD2-NEXT:    [[TMP4:%.*]] = load i32, ptr @_ZN6Static1sE, align 4, !dbg [[DBG179:![0-9]+]]
3044 // SIMD2-NEXT:    store i32 [[TMP4]], ptr [[RES]], align 4, !dbg [[DBG180:![0-9]+]]
3045 // SIMD2-NEXT:    [[TMP5:%.*]] = load i32, ptr @_ZZ4mainE2sm, align 8, !dbg [[DBG181:![0-9]+]]
3046 // SIMD2-NEXT:    [[TMP6:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG182:![0-9]+]]
3047 // SIMD2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]], !dbg [[DBG182]]
3048 // SIMD2-NEXT:    store i32 [[ADD]], ptr [[RES]], align 4, !dbg [[DBG182]]
3049 // SIMD2-NEXT:    [[TMP7:%.*]] = load i32, ptr @_ZL3gs1, align 4, !dbg [[DBG183:![0-9]+]]
3050 // SIMD2-NEXT:    [[TMP8:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG184:![0-9]+]]
3051 // SIMD2-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP8]], [[TMP7]], !dbg [[DBG184]]
3052 // SIMD2-NEXT:    store i32 [[ADD1]], ptr [[RES]], align 4, !dbg [[DBG184]]
3053 // SIMD2-NEXT:    [[TMP9:%.*]] = load i32, ptr @_ZL3gs2, align 8, !dbg [[DBG185:![0-9]+]]
3054 // SIMD2-NEXT:    [[TMP10:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG186:![0-9]+]]
3055 // SIMD2-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP10]], [[TMP9]], !dbg [[DBG186]]
3056 // SIMD2-NEXT:    store i32 [[ADD2]], ptr [[RES]], align 4, !dbg [[DBG186]]
3057 // SIMD2-NEXT:    [[TMP11:%.*]] = load i32, ptr @gs3, align 4, !dbg [[DBG187:![0-9]+]]
3058 // SIMD2-NEXT:    [[TMP12:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG188:![0-9]+]]
3059 // SIMD2-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]], !dbg [[DBG188]]
3060 // SIMD2-NEXT:    store i32 [[ADD3]], ptr [[RES]], align 4, !dbg [[DBG188]]
3061 // SIMD2-NEXT:    [[TMP13:%.*]] = load i32, ptr getelementptr inbounds ([2 x [3 x %struct.S1]], ptr @arr_x, i64 0, i64 1, i64 1), align 4, !dbg [[DBG189:![0-9]+]]
3062 // SIMD2-NEXT:    [[TMP14:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG190:![0-9]+]]
3063 // SIMD2-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP14]], [[TMP13]], !dbg [[DBG190]]
3064 // SIMD2-NEXT:    store i32 [[ADD4]], ptr [[RES]], align 4, !dbg [[DBG190]]
3065 // SIMD2-NEXT:    [[TMP15:%.*]] = load i32, ptr @_ZN2STIiE2stE, align 4, !dbg [[DBG191:![0-9]+]]
3066 // SIMD2-NEXT:    [[TMP16:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG192:![0-9]+]]
3067 // SIMD2-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP16]], [[TMP15]], !dbg [[DBG192]]
3068 // SIMD2-NEXT:    store i32 [[ADD5]], ptr [[RES]], align 4, !dbg [[DBG192]]
3069 // SIMD2-NEXT:    [[TMP17:%.*]] = load float, ptr @_ZN2STIfE2stE, align 4, !dbg [[DBG193:![0-9]+]]
3070 // SIMD2-NEXT:    [[CONV:%.*]] = fptosi float [[TMP17]] to i32, !dbg [[DBG193]]
3071 // SIMD2-NEXT:    [[TMP18:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG194:![0-9]+]]
3072 // SIMD2-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP18]], [[CONV]], !dbg [[DBG194]]
3073 // SIMD2-NEXT:    store i32 [[ADD6]], ptr [[RES]], align 4, !dbg [[DBG194]]
3074 // SIMD2-NEXT:    [[TMP19:%.*]] = load i32, ptr @_ZN2STI2S4E2stE, align 4, !dbg [[DBG195:![0-9]+]]
3075 // SIMD2-NEXT:    [[TMP20:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG196:![0-9]+]]
3076 // SIMD2-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP20]], [[TMP19]], !dbg [[DBG196]]
3077 // SIMD2-NEXT:    store i32 [[ADD7]], ptr [[RES]], align 4, !dbg [[DBG196]]
3078 // SIMD2-NEXT:    [[TMP21:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG197:![0-9]+]]
3079 // SIMD2-NEXT:    ret i32 [[TMP21]], !dbg [[DBG198:![0-9]+]]
3080 // SIMD2:       lpad:
3081 // SIMD2-NEXT:    [[TMP22:%.*]] = landingpad { ptr, i32 }
3082 // SIMD2-NEXT:    cleanup, !dbg [[DBG199:![0-9]+]]
3083 // SIMD2-NEXT:    [[TMP23:%.*]] = extractvalue { ptr, i32 } [[TMP22]], 0, !dbg [[DBG199]]
3084 // SIMD2-NEXT:    store ptr [[TMP23]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG199]]
3085 // SIMD2-NEXT:    [[TMP24:%.*]] = extractvalue { ptr, i32 } [[TMP22]], 1, !dbg [[DBG199]]
3086 // SIMD2-NEXT:    store i32 [[TMP24]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG199]]
3087 // SIMD2-NEXT:    call void @__cxa_guard_abort(ptr @_ZGVZ4mainE2sm) #[[ATTR3]], !dbg [[DBG175]]
3088 // SIMD2-NEXT:    br label [[EH_RESUME:%.*]], !dbg [[DBG175]]
3089 // SIMD2:       eh.resume:
3090 // SIMD2-NEXT:    [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG175]]
3091 // SIMD2-NEXT:    [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG175]]
3092 // SIMD2-NEXT:    [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG175]]
3093 // SIMD2-NEXT:    [[LPAD_VAL8:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG175]]
3094 // SIMD2-NEXT:    resume { ptr, i32 } [[LPAD_VAL8]], !dbg [[DBG175]]
3095 //
3096 //
3097 // SIMD2-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC1Ei
3098 // SIMD2-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 !dbg [[DBG200:![0-9]+]] {
3099 // SIMD2-NEXT:  entry:
3100 // SIMD2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
3101 // SIMD2-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
3102 // SIMD2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
3103 // SIMD2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META201:![0-9]+]], metadata !DIExpression()), !dbg [[DBG203:![0-9]+]]
3104 // SIMD2-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
3105 // SIMD2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META204:![0-9]+]], metadata !DIExpression()), !dbg [[DBG205:![0-9]+]]
3106 // SIMD2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
3107 // SIMD2-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG206:![0-9]+]]
3108 // SIMD2-NEXT:    call void @_ZZ4mainEN5SmainC2Ei(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG206]]
3109 // SIMD2-NEXT:    ret void, !dbg [[DBG207:![0-9]+]]
3110 //
3111 //
3112 // SIMD2-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD1Ev
3113 // SIMD2-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG208:![0-9]+]] {
3114 // SIMD2-NEXT:  entry:
3115 // SIMD2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
3116 // SIMD2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
3117 // SIMD2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META209:![0-9]+]], metadata !DIExpression()), !dbg [[DBG210:![0-9]+]]
3118 // SIMD2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
3119 // SIMD2-NEXT:    call void @_ZZ4mainEN5SmainD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR3]], !dbg [[DBG211:![0-9]+]]
3120 // SIMD2-NEXT:    ret void, !dbg [[DBG212:![0-9]+]]
3121 //
3122 //
3123 // SIMD2-LABEL: define {{[^@]+}}@_Z6foobarv
3124 // SIMD2-SAME: () #[[ATTR6:[0-9]+]] !dbg [[DBG213:![0-9]+]] {
3125 // SIMD2-NEXT:  entry:
3126 // SIMD2-NEXT:    [[RES:%.*]] = alloca i32, align 4
3127 // SIMD2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[RES]], metadata [[META214:![0-9]+]], metadata !DIExpression()), !dbg [[DBG215:![0-9]+]]
3128 // SIMD2-NEXT:    [[TMP0:%.*]] = load i32, ptr @_ZN6Static1sE, align 4, !dbg [[DBG216:![0-9]+]]
3129 // SIMD2-NEXT:    store i32 [[TMP0]], ptr [[RES]], align 4, !dbg [[DBG217:![0-9]+]]
3130 // SIMD2-NEXT:    [[TMP1:%.*]] = load i32, ptr @_ZL3gs1, align 4, !dbg [[DBG218:![0-9]+]]
3131 // SIMD2-NEXT:    [[TMP2:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG219:![0-9]+]]
3132 // SIMD2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP2]], [[TMP1]], !dbg [[DBG219]]
3133 // SIMD2-NEXT:    store i32 [[ADD]], ptr [[RES]], align 4, !dbg [[DBG219]]
3134 // SIMD2-NEXT:    [[TMP3:%.*]] = load i32, ptr @_ZL3gs2, align 8, !dbg [[DBG220:![0-9]+]]
3135 // SIMD2-NEXT:    [[TMP4:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG221:![0-9]+]]
3136 // SIMD2-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP4]], [[TMP3]], !dbg [[DBG221]]
3137 // SIMD2-NEXT:    store i32 [[ADD1]], ptr [[RES]], align 4, !dbg [[DBG221]]
3138 // SIMD2-NEXT:    [[TMP5:%.*]] = load i32, ptr @gs3, align 4, !dbg [[DBG222:![0-9]+]]
3139 // SIMD2-NEXT:    [[TMP6:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG223:![0-9]+]]
3140 // SIMD2-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP6]], [[TMP5]], !dbg [[DBG223]]
3141 // SIMD2-NEXT:    store i32 [[ADD2]], ptr [[RES]], align 4, !dbg [[DBG223]]
3142 // SIMD2-NEXT:    [[TMP7:%.*]] = load i32, ptr getelementptr inbounds ([2 x [3 x %struct.S1]], ptr @arr_x, i64 0, i64 1, i64 1), align 4, !dbg [[DBG224:![0-9]+]]
3143 // SIMD2-NEXT:    [[TMP8:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG225:![0-9]+]]
3144 // SIMD2-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP8]], [[TMP7]], !dbg [[DBG225]]
3145 // SIMD2-NEXT:    store i32 [[ADD3]], ptr [[RES]], align 4, !dbg [[DBG225]]
3146 // SIMD2-NEXT:    [[TMP9:%.*]] = load i32, ptr @_ZN2STIiE2stE, align 4, !dbg [[DBG226:![0-9]+]]
3147 // SIMD2-NEXT:    [[TMP10:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG227:![0-9]+]]
3148 // SIMD2-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP10]], [[TMP9]], !dbg [[DBG227]]
3149 // SIMD2-NEXT:    store i32 [[ADD4]], ptr [[RES]], align 4, !dbg [[DBG227]]
3150 // SIMD2-NEXT:    [[TMP11:%.*]] = load float, ptr @_ZN2STIfE2stE, align 4, !dbg [[DBG228:![0-9]+]]
3151 // SIMD2-NEXT:    [[CONV:%.*]] = fptosi float [[TMP11]] to i32, !dbg [[DBG228]]
3152 // SIMD2-NEXT:    [[TMP12:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG229:![0-9]+]]
3153 // SIMD2-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP12]], [[CONV]], !dbg [[DBG229]]
3154 // SIMD2-NEXT:    store i32 [[ADD5]], ptr [[RES]], align 4, !dbg [[DBG229]]
3155 // SIMD2-NEXT:    [[TMP13:%.*]] = load i32, ptr @_ZN2STI2S4E2stE, align 4, !dbg [[DBG230:![0-9]+]]
3156 // SIMD2-NEXT:    [[TMP14:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG231:![0-9]+]]
3157 // SIMD2-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP14]], [[TMP13]], !dbg [[DBG231]]
3158 // SIMD2-NEXT:    store i32 [[ADD6]], ptr [[RES]], align 4, !dbg [[DBG231]]
3159 // SIMD2-NEXT:    [[TMP15:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG232:![0-9]+]]
3160 // SIMD2-NEXT:    ret i32 [[TMP15]], !dbg [[DBG233:![0-9]+]]
3161 //
3162 //
3163 // SIMD2-LABEL: define {{[^@]+}}@__cxx_global_var_init.3
3164 // SIMD2-SAME: () #[[ATTR0]] comdat($_ZN2STI2S4E2stE) !dbg [[DBG234:![0-9]+]] {
3165 // SIMD2-NEXT:  entry:
3166 // SIMD2-NEXT:    [[TMP0:%.*]] = load i8, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG235:![0-9]+]]
3167 // SIMD2-NEXT:    [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG235]]
3168 // SIMD2-NEXT:    br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG235]]
3169 // SIMD2:       init.check:
3170 // SIMD2-NEXT:    store i8 1, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG235]]
3171 // SIMD2-NEXT:    call void @_ZN2S4C1Ei(ptr noundef nonnull align 4 dereferenceable(8) @_ZN2STI2S4E2stE, i32 noundef 23), !dbg [[DBG236:![0-9]+]]
3172 // SIMD2-NEXT:    [[TMP1:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S4D1Ev, ptr @_ZN2STI2S4E2stE, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG235]]
3173 // SIMD2-NEXT:    br label [[INIT_END]], !dbg [[DBG235]]
3174 // SIMD2:       init.end:
3175 // SIMD2-NEXT:    ret void, !dbg [[DBG238:![0-9]+]]
3176 //
3177 //
3178 // SIMD2-LABEL: define {{[^@]+}}@_ZN2S4C1Ei
3179 // SIMD2-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 !dbg [[DBG239:![0-9]+]] {
3180 // SIMD2-NEXT:  entry:
3181 // SIMD2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
3182 // SIMD2-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
3183 // SIMD2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
3184 // SIMD2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META240:![0-9]+]], metadata !DIExpression()), !dbg [[DBG242:![0-9]+]]
3185 // SIMD2-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
3186 // SIMD2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META243:![0-9]+]], metadata !DIExpression()), !dbg [[DBG244:![0-9]+]]
3187 // SIMD2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
3188 // SIMD2-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG245:![0-9]+]]
3189 // SIMD2-NEXT:    call void @_ZN2S4C2Ei(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG245]]
3190 // SIMD2-NEXT:    ret void, !dbg [[DBG246:![0-9]+]]
3191 //
3192 //
3193 // SIMD2-LABEL: define {{[^@]+}}@_ZN2S4D1Ev
3194 // SIMD2-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG247:![0-9]+]] {
3195 // SIMD2-NEXT:  entry:
3196 // SIMD2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
3197 // SIMD2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
3198 // SIMD2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META248:![0-9]+]], metadata !DIExpression()), !dbg [[DBG249:![0-9]+]]
3199 // SIMD2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
3200 // SIMD2-NEXT:    call void @_ZN2S4D2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR3]], !dbg [[DBG250:![0-9]+]]
3201 // SIMD2-NEXT:    ret void, !dbg [[DBG251:![0-9]+]]
3202 //
3203 //
3204 // SIMD2-LABEL: define {{[^@]+}}@_ZN2S1C2Ei
3205 // SIMD2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG252:![0-9]+]] {
3206 // SIMD2-NEXT:  entry:
3207 // SIMD2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
3208 // SIMD2-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
3209 // SIMD2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
3210 // SIMD2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META253:![0-9]+]], metadata !DIExpression()), !dbg [[DBG254:![0-9]+]]
3211 // SIMD2-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
3212 // SIMD2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META255:![0-9]+]], metadata !DIExpression()), !dbg [[DBG256:![0-9]+]]
3213 // SIMD2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
3214 // SIMD2-NEXT:    [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG257:![0-9]+]]
3215 // SIMD2-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG258:![0-9]+]]
3216 // SIMD2-NEXT:    store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG257]]
3217 // SIMD2-NEXT:    ret void, !dbg [[DBG259:![0-9]+]]
3218 //
3219 //
3220 // SIMD2-LABEL: define {{[^@]+}}@_ZN2S1D2Ev
3221 // SIMD2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG260:![0-9]+]] {
3222 // SIMD2-NEXT:  entry:
3223 // SIMD2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
3224 // SIMD2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
3225 // SIMD2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META261:![0-9]+]], metadata !DIExpression()), !dbg [[DBG262:![0-9]+]]
3226 // SIMD2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
3227 // SIMD2-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG263:![0-9]+]]
3228 // SIMD2-NEXT:    store i32 0, ptr [[A]], align 4, !dbg [[DBG265:![0-9]+]]
3229 // SIMD2-NEXT:    ret void, !dbg [[DBG266:![0-9]+]]
3230 //
3231 //
3232 // SIMD2-LABEL: define {{[^@]+}}@_ZN2S2C2Ei
3233 // SIMD2-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG267:![0-9]+]] {
3234 // SIMD2-NEXT:  entry:
3235 // SIMD2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
3236 // SIMD2-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
3237 // SIMD2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
3238 // SIMD2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META268:![0-9]+]], metadata !DIExpression()), !dbg [[DBG269:![0-9]+]]
3239 // SIMD2-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
3240 // SIMD2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META270:![0-9]+]], metadata !DIExpression()), !dbg [[DBG271:![0-9]+]]
3241 // SIMD2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
3242 // SIMD2-NEXT:    [[A2:%.*]] = getelementptr inbounds [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG272:![0-9]+]]
3243 // SIMD2-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG273:![0-9]+]]
3244 // SIMD2-NEXT:    store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG272]]
3245 // SIMD2-NEXT:    ret void, !dbg [[DBG274:![0-9]+]]
3246 //
3247 //
3248 // SIMD2-LABEL: define {{[^@]+}}@_ZN2S2D2Ev
3249 // SIMD2-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG275:![0-9]+]] {
3250 // SIMD2-NEXT:  entry:
3251 // SIMD2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
3252 // SIMD2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
3253 // SIMD2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META276:![0-9]+]], metadata !DIExpression()), !dbg [[DBG277:![0-9]+]]
3254 // SIMD2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
3255 // SIMD2-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG278:![0-9]+]]
3256 // SIMD2-NEXT:    store i32 0, ptr [[A]], align 8, !dbg [[DBG280:![0-9]+]]
3257 // SIMD2-NEXT:    ret void, !dbg [[DBG281:![0-9]+]]
3258 //
3259 //
3260 // SIMD2-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC2Ei
3261 // SIMD2-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG282:![0-9]+]] {
3262 // SIMD2-NEXT:  entry:
3263 // SIMD2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
3264 // SIMD2-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
3265 // SIMD2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
3266 // SIMD2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META283:![0-9]+]], metadata !DIExpression()), !dbg [[DBG284:![0-9]+]]
3267 // SIMD2-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
3268 // SIMD2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META285:![0-9]+]], metadata !DIExpression()), !dbg [[DBG286:![0-9]+]]
3269 // SIMD2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
3270 // SIMD2-NEXT:    [[A2:%.*]] = getelementptr inbounds [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG287:![0-9]+]]
3271 // SIMD2-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG288:![0-9]+]]
3272 // SIMD2-NEXT:    store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG287]]
3273 // SIMD2-NEXT:    ret void, !dbg [[DBG289:![0-9]+]]
3274 //
3275 //
3276 // SIMD2-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD2Ev
3277 // SIMD2-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG290:![0-9]+]] {
3278 // SIMD2-NEXT:  entry:
3279 // SIMD2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
3280 // SIMD2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
3281 // SIMD2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META291:![0-9]+]], metadata !DIExpression()), !dbg [[DBG292:![0-9]+]]
3282 // SIMD2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
3283 // SIMD2-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG293:![0-9]+]]
3284 // SIMD2-NEXT:    store i32 0, ptr [[A]], align 8, !dbg [[DBG295:![0-9]+]]
3285 // SIMD2-NEXT:    ret void, !dbg [[DBG296:![0-9]+]]
3286 //
3287 //
3288 // SIMD2-LABEL: define {{[^@]+}}@_ZN2S4C2Ei
3289 // SIMD2-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG297:![0-9]+]] {
3290 // SIMD2-NEXT:  entry:
3291 // SIMD2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
3292 // SIMD2-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
3293 // SIMD2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
3294 // SIMD2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META298:![0-9]+]], metadata !DIExpression()), !dbg [[DBG299:![0-9]+]]
3295 // SIMD2-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
3296 // SIMD2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META300:![0-9]+]], metadata !DIExpression()), !dbg [[DBG301:![0-9]+]]
3297 // SIMD2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
3298 // SIMD2-NEXT:    [[A2:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG302:![0-9]+]]
3299 // SIMD2-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG303:![0-9]+]]
3300 // SIMD2-NEXT:    store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG302]]
3301 // SIMD2-NEXT:    ret void, !dbg [[DBG304:![0-9]+]]
3302 //
3303 //
3304 // SIMD2-LABEL: define {{[^@]+}}@_ZN2S4D2Ev
3305 // SIMD2-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG305:![0-9]+]] {
3306 // SIMD2-NEXT:  entry:
3307 // SIMD2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
3308 // SIMD2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
3309 // SIMD2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META306:![0-9]+]], metadata !DIExpression()), !dbg [[DBG307:![0-9]+]]
3310 // SIMD2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
3311 // SIMD2-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG308:![0-9]+]]
3312 // SIMD2-NEXT:    store i32 0, ptr [[A]], align 4, !dbg [[DBG310:![0-9]+]]
3313 // SIMD2-NEXT:    ret void, !dbg [[DBG311:![0-9]+]]
3314 //
3315 //
3316 // SIMD2-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_threadprivate_codegen.cpp
3317 // SIMD2-SAME: () #[[ATTR0]] !dbg [[DBG312:![0-9]+]] {
3318 // SIMD2-NEXT:  entry:
3319 // SIMD2-NEXT:    call void @__cxx_global_var_init(), !dbg [[DBG314:![0-9]+]]
3320 // SIMD2-NEXT:    call void @__cxx_global_var_init.1(), !dbg [[DBG314]]
3321 // SIMD2-NEXT:    call void @__cxx_global_var_init.2(), !dbg [[DBG314]]
3322 // SIMD2-NEXT:    ret void
3323 //
3324 //
3325 // CHECK-TLS1-LABEL: define {{[^@]+}}@__cxx_global_var_init
3326 // CHECK-TLS1-SAME: () #[[ATTR0:[0-9]+]] {
3327 // CHECK-TLS1-NEXT:  entry:
3328 // CHECK-TLS1-NEXT:    call void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @_ZL3gs1, i32 noundef 5)
3329 // CHECK-TLS1-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_thread_atexit(ptr @_ZN2S1D1Ev, ptr @_ZL3gs1, ptr @__dso_handle) #[[ATTR3:[0-9]+]]
3330 // CHECK-TLS1-NEXT:    ret void
3331 //
3332 //
3333 // CHECK-TLS1-LABEL: define {{[^@]+}}@_ZN2S1C1Ei
3334 // CHECK-TLS1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
3335 // CHECK-TLS1-NEXT:  entry:
3336 // CHECK-TLS1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
3337 // CHECK-TLS1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
3338 // CHECK-TLS1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
3339 // CHECK-TLS1-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
3340 // CHECK-TLS1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
3341 // CHECK-TLS1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
3342 // CHECK-TLS1-NEXT:    call void @_ZN2S1C2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])
3343 // CHECK-TLS1-NEXT:    ret void
3344 //
3345 //
3346 // CHECK-TLS1-LABEL: define {{[^@]+}}@_ZN2S1D1Ev
3347 // CHECK-TLS1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 {
3348 // CHECK-TLS1-NEXT:  entry:
3349 // CHECK-TLS1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
3350 // CHECK-TLS1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
3351 // CHECK-TLS1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
3352 // CHECK-TLS1-NEXT:    call void @_ZN2S1D2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]]
3353 // CHECK-TLS1-NEXT:    ret void
3354 //
3355 //
3356 // CHECK-TLS1-LABEL: define {{[^@]+}}@_ZN2S1C2Ei
3357 // CHECK-TLS1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
3358 // CHECK-TLS1-NEXT:  entry:
3359 // CHECK-TLS1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
3360 // CHECK-TLS1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
3361 // CHECK-TLS1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
3362 // CHECK-TLS1-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
3363 // CHECK-TLS1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
3364 // CHECK-TLS1-NEXT:    [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0
3365 // CHECK-TLS1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
3366 // CHECK-TLS1-NEXT:    store i32 [[TMP0]], ptr [[A2]], align 4
3367 // CHECK-TLS1-NEXT:    ret void
3368 //
3369 //
3370 // CHECK-TLS1-LABEL: define {{[^@]+}}@_ZN2S1D2Ev
3371 // CHECK-TLS1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
3372 // CHECK-TLS1-NEXT:  entry:
3373 // CHECK-TLS1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
3374 // CHECK-TLS1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
3375 // CHECK-TLS1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
3376 // CHECK-TLS1-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0
3377 // CHECK-TLS1-NEXT:    store i32 0, ptr [[A]], align 4
3378 // CHECK-TLS1-NEXT:    ret void
3379 //
3380 //
3381 // CHECK-TLS1-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
3382 // CHECK-TLS1-SAME: () #[[ATTR0]] {
3383 // CHECK-TLS1-NEXT:  entry:
3384 // CHECK-TLS1-NEXT:    call void @_ZN2S2C1Ei(ptr noundef nonnull align 8 dereferenceable(16) @_ZL3gs2, i32 noundef 27)
3385 // CHECK-TLS1-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S2D1Ev, ptr @_ZL3gs2, ptr @__dso_handle) #[[ATTR3]]
3386 // CHECK-TLS1-NEXT:    ret void
3387 //
3388 //
3389 // CHECK-TLS1-LABEL: define {{[^@]+}}@_ZN2S2C1Ei
3390 // CHECK-TLS1-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3391 // CHECK-TLS1-NEXT:  entry:
3392 // CHECK-TLS1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
3393 // CHECK-TLS1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
3394 // CHECK-TLS1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
3395 // CHECK-TLS1-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
3396 // CHECK-TLS1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
3397 // CHECK-TLS1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
3398 // CHECK-TLS1-NEXT:    call void @_ZN2S2C2Ei(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], i32 noundef [[TMP0]])
3399 // CHECK-TLS1-NEXT:    ret void
3400 //
3401 //
3402 // CHECK-TLS1-LABEL: define {{[^@]+}}@_ZN2S2D1Ev
3403 // CHECK-TLS1-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
3404 // CHECK-TLS1-NEXT:  entry:
3405 // CHECK-TLS1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
3406 // CHECK-TLS1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
3407 // CHECK-TLS1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
3408 // CHECK-TLS1-NEXT:    call void @_ZN2S2D2Ev(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]]) #[[ATTR3]]
3409 // CHECK-TLS1-NEXT:    ret void
3410 //
3411 //
3412 // CHECK-TLS1-LABEL: define {{[^@]+}}@_ZN2S2C2Ei
3413 // CHECK-TLS1-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
3414 // CHECK-TLS1-NEXT:  entry:
3415 // CHECK-TLS1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
3416 // CHECK-TLS1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
3417 // CHECK-TLS1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
3418 // CHECK-TLS1-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
3419 // CHECK-TLS1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
3420 // CHECK-TLS1-NEXT:    [[A2:%.*]] = getelementptr inbounds [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0
3421 // CHECK-TLS1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
3422 // CHECK-TLS1-NEXT:    store i32 [[TMP0]], ptr [[A2]], align 8
3423 // CHECK-TLS1-NEXT:    ret void
3424 //
3425 //
3426 // CHECK-TLS1-LABEL: define {{[^@]+}}@_ZN2S2D2Ev
3427 // CHECK-TLS1-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
3428 // CHECK-TLS1-NEXT:  entry:
3429 // CHECK-TLS1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
3430 // CHECK-TLS1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
3431 // CHECK-TLS1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
3432 // CHECK-TLS1-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0
3433 // CHECK-TLS1-NEXT:    store i32 0, ptr [[A]], align 8
3434 // CHECK-TLS1-NEXT:    ret void
3435 //
3436 //
3437 // CHECK-TLS1-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
3438 // CHECK-TLS1-SAME: () #[[ATTR0]] personality ptr @__gxx_personality_v0 {
3439 // CHECK-TLS1-NEXT:  entry:
3440 // CHECK-TLS1-NEXT:    [[ARRAYINIT_ENDOFINIT:%.*]] = alloca ptr, align 8
3441 // CHECK-TLS1-NEXT:    [[ARRAYINIT_ENDOFINIT1:%.*]] = alloca ptr, align 8
3442 // CHECK-TLS1-NEXT:    [[EXN_SLOT:%.*]] = alloca ptr, align 8
3443 // CHECK-TLS1-NEXT:    [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4
3444 // CHECK-TLS1-NEXT:    [[ARRAYINIT_ENDOFINIT5:%.*]] = alloca ptr, align 8
3445 // CHECK-TLS1-NEXT:    store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT]], align 8
3446 // CHECK-TLS1-NEXT:    store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT1]], align 8
3447 // CHECK-TLS1-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @arr_x, i32 noundef 1)
3448 // CHECK-TLS1-NEXT:    to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]]
3449 // CHECK-TLS1:       invoke.cont:
3450 // CHECK-TLS1-NEXT:    store ptr getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT1]], align 8
3451 // CHECK-TLS1-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 1), i32 noundef 2)
3452 // CHECK-TLS1-NEXT:    to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD]]
3453 // CHECK-TLS1:       invoke.cont2:
3454 // CHECK-TLS1-NEXT:    store ptr getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), ptr [[ARRAYINIT_ENDOFINIT1]], align 8
3455 // CHECK-TLS1-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), i32 noundef 3)
3456 // CHECK-TLS1-NEXT:    to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]]
3457 // CHECK-TLS1:       invoke.cont3:
3458 // CHECK-TLS1-NEXT:    store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT]], align 8
3459 // CHECK-TLS1-NEXT:    store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8
3460 // CHECK-TLS1-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i32 noundef 4)
3461 // CHECK-TLS1-NEXT:    to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD6:%.*]]
3462 // CHECK-TLS1:       invoke.cont7:
3463 // CHECK-TLS1-NEXT:    store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8
3464 // CHECK-TLS1-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), i32 noundef 5)
3465 // CHECK-TLS1-NEXT:    to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD6]]
3466 // CHECK-TLS1:       invoke.cont8:
3467 // CHECK-TLS1-NEXT:    store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), ptr [[ARRAYINIT_ENDOFINIT5]], align 8
3468 // CHECK-TLS1-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), i32 noundef 6)
3469 // CHECK-TLS1-NEXT:    to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD6]]
3470 // CHECK-TLS1:       invoke.cont9:
3471 // CHECK-TLS1-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_thread_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR3]]
3472 // CHECK-TLS1-NEXT:    ret void
3473 // CHECK-TLS1:       lpad:
3474 // CHECK-TLS1-NEXT:    [[TMP1:%.*]] = landingpad { ptr, i32 }
3475 // CHECK-TLS1-NEXT:    cleanup
3476 // CHECK-TLS1-NEXT:    [[TMP2:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 0
3477 // CHECK-TLS1-NEXT:    store ptr [[TMP2]], ptr [[EXN_SLOT]], align 8
3478 // CHECK-TLS1-NEXT:    [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 1
3479 // CHECK-TLS1-NEXT:    store i32 [[TMP3]], ptr [[EHSELECTOR_SLOT]], align 4
3480 // CHECK-TLS1-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT1]], align 8
3481 // CHECK-TLS1-NEXT:    [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr @arr_x, [[TMP4]]
3482 // CHECK-TLS1-NEXT:    br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY:%.*]]
3483 // CHECK-TLS1:       arraydestroy.body:
3484 // CHECK-TLS1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP4]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
3485 // CHECK-TLS1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
3486 // CHECK-TLS1-NEXT:    call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]]
3487 // CHECK-TLS1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x
3488 // CHECK-TLS1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4]], label [[ARRAYDESTROY_BODY]]
3489 // CHECK-TLS1:       arraydestroy.done4:
3490 // CHECK-TLS1-NEXT:    br label [[EHCLEANUP:%.*]]
3491 // CHECK-TLS1:       lpad6:
3492 // CHECK-TLS1-NEXT:    [[TMP5:%.*]] = landingpad { ptr, i32 }
3493 // CHECK-TLS1-NEXT:    cleanup
3494 // CHECK-TLS1-NEXT:    [[TMP6:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 0
3495 // CHECK-TLS1-NEXT:    store ptr [[TMP6]], ptr [[EXN_SLOT]], align 8
3496 // CHECK-TLS1-NEXT:    [[TMP7:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 1
3497 // CHECK-TLS1-NEXT:    store i32 [[TMP7]], ptr [[EHSELECTOR_SLOT]], align 4
3498 // CHECK-TLS1-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT5]], align 8
3499 // CHECK-TLS1-NEXT:    [[ARRAYDESTROY_ISEMPTY10:%.*]] = icmp eq ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), [[TMP8]]
3500 // CHECK-TLS1-NEXT:    br i1 [[ARRAYDESTROY_ISEMPTY10]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY11:%.*]]
3501 // CHECK-TLS1:       arraydestroy.body11:
3502 // CHECK-TLS1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST12:%.*]] = phi ptr [ [[TMP8]], [[LPAD6]] ], [ [[ARRAYDESTROY_ELEMENT13:%.*]], [[ARRAYDESTROY_BODY11]] ]
3503 // CHECK-TLS1-NEXT:    [[ARRAYDESTROY_ELEMENT13]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST12]], i64 -1
3504 // CHECK-TLS1-NEXT:    call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR3]]
3505 // CHECK-TLS1-NEXT:    [[ARRAYDESTROY_DONE14:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1)
3506 // CHECK-TLS1-NEXT:    br i1 [[ARRAYDESTROY_DONE14]], label [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_BODY11]]
3507 // CHECK-TLS1:       arraydestroy.done15:
3508 // CHECK-TLS1-NEXT:    br label [[EHCLEANUP]]
3509 // CHECK-TLS1:       ehcleanup:
3510 // CHECK-TLS1-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT]], align 8
3511 // CHECK-TLS1-NEXT:    [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP9]], i64 0, i64 0
3512 // CHECK-TLS1-NEXT:    [[ARRAYDESTROY_ISEMPTY16:%.*]] = icmp eq ptr @arr_x, [[PAD_ARRAYEND]]
3513 // CHECK-TLS1-NEXT:    br i1 [[ARRAYDESTROY_ISEMPTY16]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17:%.*]]
3514 // CHECK-TLS1:       arraydestroy.body17:
3515 // CHECK-TLS1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi ptr [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ]
3516 // CHECK-TLS1-NEXT:    [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1
3517 // CHECK-TLS1-NEXT:    call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]]
3518 // CHECK-TLS1-NEXT:    [[ARRAYDESTROY_DONE20:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT19]], @arr_x
3519 // CHECK-TLS1-NEXT:    br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]]
3520 // CHECK-TLS1:       arraydestroy.done21:
3521 // CHECK-TLS1-NEXT:    br label [[EH_RESUME:%.*]]
3522 // CHECK-TLS1:       eh.resume:
3523 // CHECK-TLS1-NEXT:    [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8
3524 // CHECK-TLS1-NEXT:    [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4
3525 // CHECK-TLS1-NEXT:    [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0
3526 // CHECK-TLS1-NEXT:    [[LPAD_VAL22:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1
3527 // CHECK-TLS1-NEXT:    resume { ptr, i32 } [[LPAD_VAL22]]
3528 //
3529 //
3530 // CHECK-TLS1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
3531 // CHECK-TLS1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {
3532 // CHECK-TLS1-NEXT:  entry:
3533 // CHECK-TLS1-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
3534 // CHECK-TLS1-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
3535 // CHECK-TLS1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
3536 // CHECK-TLS1:       arraydestroy.body:
3537 // CHECK-TLS1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 6), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
3538 // CHECK-TLS1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
3539 // CHECK-TLS1-NEXT:    call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]]
3540 // CHECK-TLS1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x
3541 // CHECK-TLS1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
3542 // CHECK-TLS1:       arraydestroy.done1:
3543 // CHECK-TLS1-NEXT:    ret void
3544 //
3545 //
3546 // CHECK-TLS1-LABEL: define {{[^@]+}}@main
3547 // CHECK-TLS1-SAME: () #[[ATTR4:[0-9]+]] {
3548 // CHECK-TLS1-NEXT:  entry:
3549 // CHECK-TLS1-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
3550 // CHECK-TLS1-NEXT:    [[RES:%.*]] = alloca i32, align 4
3551 // CHECK-TLS1-NEXT:    store i32 0, ptr [[RETVAL]], align 4
3552 // CHECK-TLS1-NEXT:    [[TMP0:%.*]] = load i8, ptr @_ZGVZ4mainE2sm, align 1
3553 // CHECK-TLS1-NEXT:    [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0
3554 // CHECK-TLS1-NEXT:    br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF3:![0-9]+]]
3555 // CHECK-TLS1:       init.check:
3556 // CHECK-TLS1-NEXT:    [[TMP1:%.*]] = call ptr @_ZTWL3gs1()
3557 // CHECK-TLS1-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP1]], i32 0, i32 0
3558 // CHECK-TLS1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 4
3559 // CHECK-TLS1-NEXT:    call void @_ZZ4mainEN5SmainC1Ei(ptr noundef nonnull align 8 dereferenceable(24) @_ZZ4mainE2sm, i32 noundef [[TMP2]])
3560 // CHECK-TLS1-NEXT:    [[TMP3:%.*]] = call i32 @__cxa_thread_atexit(ptr @_ZZ4mainEN5SmainD1Ev, ptr @_ZZ4mainE2sm, ptr @__dso_handle) #[[ATTR3]]
3561 // CHECK-TLS1-NEXT:    store i8 1, ptr @_ZGVZ4mainE2sm, align 1
3562 // CHECK-TLS1-NEXT:    br label [[INIT_END]]
3563 // CHECK-TLS1:       init.end:
3564 // CHECK-TLS1-NEXT:    [[TMP4:%.*]] = call ptr @_ZTWN6Static1sE()
3565 // CHECK-TLS1-NEXT:    [[A1:%.*]] = getelementptr inbounds [[STRUCT_S3:%.*]], ptr [[TMP4]], i32 0, i32 0
3566 // CHECK-TLS1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[A1]], align 4
3567 // CHECK-TLS1-NEXT:    store i32 [[TMP5]], ptr [[RES]], align 4
3568 // CHECK-TLS1-NEXT:    [[TMP6:%.*]] = call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @_ZZ4mainE2sm)
3569 // CHECK-TLS1-NEXT:    [[A2:%.*]] = getelementptr inbounds [[STRUCT_SMAIN:%.*]], ptr [[TMP6]], i32 0, i32 0
3570 // CHECK-TLS1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[A2]], align 8
3571 // CHECK-TLS1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[RES]], align 4
3572 // CHECK-TLS1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP8]], [[TMP7]]
3573 // CHECK-TLS1-NEXT:    store i32 [[ADD]], ptr [[RES]], align 4
3574 // CHECK-TLS1-NEXT:    [[TMP9:%.*]] = call ptr @_ZTWL3gs1()
3575 // CHECK-TLS1-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP9]], i32 0, i32 0
3576 // CHECK-TLS1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[A3]], align 4
3577 // CHECK-TLS1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[RES]], align 4
3578 // CHECK-TLS1-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP11]], [[TMP10]]
3579 // CHECK-TLS1-NEXT:    store i32 [[ADD4]], ptr [[RES]], align 4
3580 // CHECK-TLS1-NEXT:    [[TMP12:%.*]] = load i32, ptr @_ZL3gs2, align 8
3581 // CHECK-TLS1-NEXT:    [[TMP13:%.*]] = load i32, ptr [[RES]], align 4
3582 // CHECK-TLS1-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP13]], [[TMP12]]
3583 // CHECK-TLS1-NEXT:    store i32 [[ADD5]], ptr [[RES]], align 4
3584 // CHECK-TLS1-NEXT:    [[TMP14:%.*]] = call ptr @_ZTW3gs3()
3585 // CHECK-TLS1-NEXT:    [[A6:%.*]] = getelementptr inbounds [[STRUCT_S5:%.*]], ptr [[TMP14]], i32 0, i32 0
3586 // CHECK-TLS1-NEXT:    [[TMP15:%.*]] = load i32, ptr [[A6]], align 4
3587 // CHECK-TLS1-NEXT:    [[TMP16:%.*]] = load i32, ptr [[RES]], align 4
3588 // CHECK-TLS1-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP16]], [[TMP15]]
3589 // CHECK-TLS1-NEXT:    store i32 [[ADD7]], ptr [[RES]], align 4
3590 // CHECK-TLS1-NEXT:    [[TMP17:%.*]] = call ptr @_ZTW5arr_x()
3591 // CHECK-TLS1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP17]], i64 0, i64 1
3592 // CHECK-TLS1-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], i64 0, i64 1
3593 // CHECK-TLS1-NEXT:    [[A9:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYIDX8]], i32 0, i32 0
3594 // CHECK-TLS1-NEXT:    [[TMP18:%.*]] = load i32, ptr [[A9]], align 4
3595 // CHECK-TLS1-NEXT:    [[TMP19:%.*]] = load i32, ptr [[RES]], align 4
3596 // CHECK-TLS1-NEXT:    [[ADD10:%.*]] = add nsw i32 [[TMP19]], [[TMP18]]
3597 // CHECK-TLS1-NEXT:    store i32 [[ADD10]], ptr [[RES]], align 4
3598 // CHECK-TLS1-NEXT:    [[TMP20:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZN2STIiE2stE)
3599 // CHECK-TLS1-NEXT:    [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4
3600 // CHECK-TLS1-NEXT:    [[TMP22:%.*]] = load i32, ptr [[RES]], align 4
3601 // CHECK-TLS1-NEXT:    [[ADD11:%.*]] = add nsw i32 [[TMP22]], [[TMP21]]
3602 // CHECK-TLS1-NEXT:    store i32 [[ADD11]], ptr [[RES]], align 4
3603 // CHECK-TLS1-NEXT:    [[TMP23:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZN2STIfE2stE)
3604 // CHECK-TLS1-NEXT:    [[TMP24:%.*]] = load float, ptr [[TMP23]], align 4
3605 // CHECK-TLS1-NEXT:    [[CONV:%.*]] = fptosi float [[TMP24]] to i32
3606 // CHECK-TLS1-NEXT:    [[TMP25:%.*]] = load i32, ptr [[RES]], align 4
3607 // CHECK-TLS1-NEXT:    [[ADD12:%.*]] = add nsw i32 [[TMP25]], [[CONV]]
3608 // CHECK-TLS1-NEXT:    store i32 [[ADD12]], ptr [[RES]], align 4
3609 // CHECK-TLS1-NEXT:    [[TMP26:%.*]] = call ptr @_ZTWN2STI2S4E2stE()
3610 // CHECK-TLS1-NEXT:    [[A13:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[TMP26]], i32 0, i32 0
3611 // CHECK-TLS1-NEXT:    [[TMP27:%.*]] = load i32, ptr [[A13]], align 4
3612 // CHECK-TLS1-NEXT:    [[TMP28:%.*]] = load i32, ptr [[RES]], align 4
3613 // CHECK-TLS1-NEXT:    [[ADD14:%.*]] = add nsw i32 [[TMP28]], [[TMP27]]
3614 // CHECK-TLS1-NEXT:    store i32 [[ADD14]], ptr [[RES]], align 4
3615 // CHECK-TLS1-NEXT:    [[TMP29:%.*]] = load i32, ptr [[RES]], align 4
3616 // CHECK-TLS1-NEXT:    ret i32 [[TMP29]]
3617 //
3618 //
3619 // CHECK-TLS1-LABEL: define {{[^@]+}}@_ZTWL3gs1
3620 // CHECK-TLS1-SAME: () #[[ATTR5:[0-9]+]] {
3621 // CHECK-TLS1-NEXT:    call void @_ZTHL3gs1()
3622 // CHECK-TLS1-NEXT:    [[TMP1:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZL3gs1)
3623 // CHECK-TLS1-NEXT:    ret ptr [[TMP1]]
3624 //
3625 //
3626 // CHECK-TLS1-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC1Ei
3627 // CHECK-TLS1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
3628 // CHECK-TLS1-NEXT:  entry:
3629 // CHECK-TLS1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
3630 // CHECK-TLS1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
3631 // CHECK-TLS1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
3632 // CHECK-TLS1-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
3633 // CHECK-TLS1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
3634 // CHECK-TLS1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
3635 // CHECK-TLS1-NEXT:    call void @_ZZ4mainEN5SmainC2Ei(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]], i32 noundef [[TMP0]])
3636 // CHECK-TLS1-NEXT:    ret void
3637 //
3638 //
3639 // CHECK-TLS1-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD1Ev
3640 // CHECK-TLS1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 {
3641 // CHECK-TLS1-NEXT:  entry:
3642 // CHECK-TLS1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
3643 // CHECK-TLS1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
3644 // CHECK-TLS1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
3645 // CHECK-TLS1-NEXT:    call void @_ZZ4mainEN5SmainD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR3]]
3646 // CHECK-TLS1-NEXT:    ret void
3647 //
3648 //
3649 // CHECK-TLS1-LABEL: define {{[^@]+}}@_ZTWN6Static1sE
3650 // CHECK-TLS1-SAME: () #[[ATTR5]] comdat {
3651 // CHECK-TLS1-NEXT:    br i1 icmp ne (ptr @_ZTHN6Static1sE, ptr null), label [[TMP1:%.*]], label [[TMP2:%.*]]
3652 // CHECK-TLS1:       1:
3653 // CHECK-TLS1-NEXT:    call void @_ZTHN6Static1sE()
3654 // CHECK-TLS1-NEXT:    br label [[TMP2]]
3655 // CHECK-TLS1:       2:
3656 // CHECK-TLS1-NEXT:    [[TMP3:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZN6Static1sE)
3657 // CHECK-TLS1-NEXT:    ret ptr [[TMP3]]
3658 //
3659 //
3660 // CHECK-TLS1-LABEL: define {{[^@]+}}@_ZTW3gs3
3661 // CHECK-TLS1-SAME: () #[[ATTR5]] comdat {
3662 // CHECK-TLS1-NEXT:    br i1 icmp ne (ptr @_ZTH3gs3, ptr null), label [[TMP1:%.*]], label [[TMP2:%.*]]
3663 // CHECK-TLS1:       1:
3664 // CHECK-TLS1-NEXT:    call void @_ZTH3gs3()
3665 // CHECK-TLS1-NEXT:    br label [[TMP2]]
3666 // CHECK-TLS1:       2:
3667 // CHECK-TLS1-NEXT:    [[TMP3:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @gs3)
3668 // CHECK-TLS1-NEXT:    ret ptr [[TMP3]]
3669 //
3670 //
3671 // CHECK-TLS1-LABEL: define {{[^@]+}}@_ZTW5arr_x
3672 // CHECK-TLS1-SAME: () #[[ATTR5]] comdat {
3673 // CHECK-TLS1-NEXT:    call void @_ZTH5arr_x()
3674 // CHECK-TLS1-NEXT:    [[TMP1:%.*]] = call align 16 ptr @llvm.threadlocal.address.p0(ptr align 16 @arr_x)
3675 // CHECK-TLS1-NEXT:    ret ptr [[TMP1]]
3676 //
3677 //
3678 // CHECK-TLS1-LABEL: define {{[^@]+}}@_ZTWN2STI2S4E2stE
3679 // CHECK-TLS1-SAME: () #[[ATTR5]] comdat {
3680 // CHECK-TLS1-NEXT:    call void @_ZTHN2STI2S4E2stE()
3681 // CHECK-TLS1-NEXT:    [[TMP1:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZN2STI2S4E2stE)
3682 // CHECK-TLS1-NEXT:    ret ptr [[TMP1]]
3683 //
3684 //
3685 // CHECK-TLS1-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC2Ei
3686 // CHECK-TLS1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 {
3687 // CHECK-TLS1-NEXT:  entry:
3688 // CHECK-TLS1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
3689 // CHECK-TLS1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
3690 // CHECK-TLS1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
3691 // CHECK-TLS1-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
3692 // CHECK-TLS1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
3693 // CHECK-TLS1-NEXT:    [[A2:%.*]] = getelementptr inbounds [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0
3694 // CHECK-TLS1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
3695 // CHECK-TLS1-NEXT:    store i32 [[TMP0]], ptr [[A2]], align 8
3696 // CHECK-TLS1-NEXT:    ret void
3697 //
3698 //
3699 // CHECK-TLS1-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD2Ev
3700 // CHECK-TLS1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 {
3701 // CHECK-TLS1-NEXT:  entry:
3702 // CHECK-TLS1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
3703 // CHECK-TLS1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
3704 // CHECK-TLS1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
3705 // CHECK-TLS1-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0
3706 // CHECK-TLS1-NEXT:    store i32 0, ptr [[A]], align 8
3707 // CHECK-TLS1-NEXT:    ret void
3708 //
3709 //
3710 // CHECK-TLS1-LABEL: define {{[^@]+}}@_Z6foobarv
3711 // CHECK-TLS1-SAME: () #[[ATTR7:[0-9]+]] {
3712 // CHECK-TLS1-NEXT:  entry:
3713 // CHECK-TLS1-NEXT:    [[RES:%.*]] = alloca i32, align 4
3714 // CHECK-TLS1-NEXT:    [[TMP0:%.*]] = call ptr @_ZTWN6Static1sE()
3715 // CHECK-TLS1-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S3:%.*]], ptr [[TMP0]], i32 0, i32 0
3716 // CHECK-TLS1-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A]], align 4
3717 // CHECK-TLS1-NEXT:    store i32 [[TMP1]], ptr [[RES]], align 4
3718 // CHECK-TLS1-NEXT:    [[TMP2:%.*]] = call ptr @_ZTWL3gs1()
3719 // CHECK-TLS1-NEXT:    [[A1:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP2]], i32 0, i32 0
3720 // CHECK-TLS1-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A1]], align 4
3721 // CHECK-TLS1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[RES]], align 4
3722 // CHECK-TLS1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP4]], [[TMP3]]
3723 // CHECK-TLS1-NEXT:    store i32 [[ADD]], ptr [[RES]], align 4
3724 // CHECK-TLS1-NEXT:    [[TMP5:%.*]] = load i32, ptr @_ZL3gs2, align 8
3725 // CHECK-TLS1-NEXT:    [[TMP6:%.*]] = load i32, ptr [[RES]], align 4
3726 // CHECK-TLS1-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP6]], [[TMP5]]
3727 // CHECK-TLS1-NEXT:    store i32 [[ADD2]], ptr [[RES]], align 4
3728 // CHECK-TLS1-NEXT:    [[TMP7:%.*]] = call ptr @_ZTW3gs3()
3729 // CHECK-TLS1-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S5:%.*]], ptr [[TMP7]], i32 0, i32 0
3730 // CHECK-TLS1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A3]], align 4
3731 // CHECK-TLS1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[RES]], align 4
3732 // CHECK-TLS1-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP9]], [[TMP8]]
3733 // CHECK-TLS1-NEXT:    store i32 [[ADD4]], ptr [[RES]], align 4
3734 // CHECK-TLS1-NEXT:    [[TMP10:%.*]] = call ptr @_ZTW5arr_x()
3735 // CHECK-TLS1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP10]], i64 0, i64 1
3736 // CHECK-TLS1-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], i64 0, i64 1
3737 // CHECK-TLS1-NEXT:    [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYIDX5]], i32 0, i32 0
3738 // CHECK-TLS1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[A6]], align 4
3739 // CHECK-TLS1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[RES]], align 4
3740 // CHECK-TLS1-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP12]], [[TMP11]]
3741 // CHECK-TLS1-NEXT:    store i32 [[ADD7]], ptr [[RES]], align 4
3742 // CHECK-TLS1-NEXT:    [[TMP13:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZN2STIiE2stE)
3743 // CHECK-TLS1-NEXT:    [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4
3744 // CHECK-TLS1-NEXT:    [[TMP15:%.*]] = load i32, ptr [[RES]], align 4
3745 // CHECK-TLS1-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP15]], [[TMP14]]
3746 // CHECK-TLS1-NEXT:    store i32 [[ADD8]], ptr [[RES]], align 4
3747 // CHECK-TLS1-NEXT:    [[TMP16:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZN2STIfE2stE)
3748 // CHECK-TLS1-NEXT:    [[TMP17:%.*]] = load float, ptr [[TMP16]], align 4
3749 // CHECK-TLS1-NEXT:    [[CONV:%.*]] = fptosi float [[TMP17]] to i32
3750 // CHECK-TLS1-NEXT:    [[TMP18:%.*]] = load i32, ptr [[RES]], align 4
3751 // CHECK-TLS1-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP18]], [[CONV]]
3752 // CHECK-TLS1-NEXT:    store i32 [[ADD9]], ptr [[RES]], align 4
3753 // CHECK-TLS1-NEXT:    [[TMP19:%.*]] = call ptr @_ZTWN2STI2S4E2stE()
3754 // CHECK-TLS1-NEXT:    [[A10:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[TMP19]], i32 0, i32 0
3755 // CHECK-TLS1-NEXT:    [[TMP20:%.*]] = load i32, ptr [[A10]], align 4
3756 // CHECK-TLS1-NEXT:    [[TMP21:%.*]] = load i32, ptr [[RES]], align 4
3757 // CHECK-TLS1-NEXT:    [[ADD11:%.*]] = add nsw i32 [[TMP21]], [[TMP20]]
3758 // CHECK-TLS1-NEXT:    store i32 [[ADD11]], ptr [[RES]], align 4
3759 // CHECK-TLS1-NEXT:    [[TMP22:%.*]] = load i32, ptr [[RES]], align 4
3760 // CHECK-TLS1-NEXT:    ret i32 [[TMP22]]
3761 //
3762 //
3763 // CHECK-TLS1-LABEL: define {{[^@]+}}@__cxx_global_var_init.3
3764 // CHECK-TLS1-SAME: () #[[ATTR0]] {
3765 // CHECK-TLS1-NEXT:  entry:
3766 // CHECK-TLS1-NEXT:    [[TMP0:%.*]] = load i8, ptr @_ZGVN2STI2S4E2stE, align 8
3767 // CHECK-TLS1-NEXT:    [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0
3768 // CHECK-TLS1-NEXT:    br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]]
3769 // CHECK-TLS1:       init.check:
3770 // CHECK-TLS1-NEXT:    store i8 1, ptr @_ZGVN2STI2S4E2stE, align 8
3771 // CHECK-TLS1-NEXT:    call void @_ZN2S4C1Ei(ptr noundef nonnull align 4 dereferenceable(8) @_ZN2STI2S4E2stE, i32 noundef 23)
3772 // CHECK-TLS1-NEXT:    [[TMP1:%.*]] = call i32 @__cxa_thread_atexit(ptr @_ZN2S4D1Ev, ptr @_ZN2STI2S4E2stE, ptr @__dso_handle) #[[ATTR3]]
3773 // CHECK-TLS1-NEXT:    br label [[INIT_END]]
3774 // CHECK-TLS1:       init.end:
3775 // CHECK-TLS1-NEXT:    ret void
3776 //
3777 //
3778 // CHECK-TLS1-LABEL: define {{[^@]+}}@_ZN2S4C1Ei
3779 // CHECK-TLS1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3780 // CHECK-TLS1-NEXT:  entry:
3781 // CHECK-TLS1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
3782 // CHECK-TLS1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
3783 // CHECK-TLS1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
3784 // CHECK-TLS1-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
3785 // CHECK-TLS1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
3786 // CHECK-TLS1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
3787 // CHECK-TLS1-NEXT:    call void @_ZN2S4C2Ei(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]], i32 noundef [[TMP0]])
3788 // CHECK-TLS1-NEXT:    ret void
3789 //
3790 //
3791 // CHECK-TLS1-LABEL: define {{[^@]+}}@_ZN2S4D1Ev
3792 // CHECK-TLS1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
3793 // CHECK-TLS1-NEXT:  entry:
3794 // CHECK-TLS1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
3795 // CHECK-TLS1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
3796 // CHECK-TLS1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
3797 // CHECK-TLS1-NEXT:    call void @_ZN2S4D2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR3]]
3798 // CHECK-TLS1-NEXT:    ret void
3799 //
3800 //
3801 // CHECK-TLS1-LABEL: define {{[^@]+}}@_ZN2S4C2Ei
3802 // CHECK-TLS1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
3803 // CHECK-TLS1-NEXT:  entry:
3804 // CHECK-TLS1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
3805 // CHECK-TLS1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
3806 // CHECK-TLS1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
3807 // CHECK-TLS1-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
3808 // CHECK-TLS1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
3809 // CHECK-TLS1-NEXT:    [[A2:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0
3810 // CHECK-TLS1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
3811 // CHECK-TLS1-NEXT:    store i32 [[TMP0]], ptr [[A2]], align 4
3812 // CHECK-TLS1-NEXT:    ret void
3813 //
3814 //
3815 // CHECK-TLS1-LABEL: define {{[^@]+}}@_ZN2S4D2Ev
3816 // CHECK-TLS1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
3817 // CHECK-TLS1-NEXT:  entry:
3818 // CHECK-TLS1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
3819 // CHECK-TLS1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
3820 // CHECK-TLS1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
3821 // CHECK-TLS1-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0
3822 // CHECK-TLS1-NEXT:    store i32 0, ptr [[A]], align 4
3823 // CHECK-TLS1-NEXT:    ret void
3824 //
3825 //
3826 // CHECK-TLS1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_threadprivate_codegen.cpp
3827 // CHECK-TLS1-SAME: () #[[ATTR0]] {
3828 // CHECK-TLS1-NEXT:  entry:
3829 // CHECK-TLS1-NEXT:    call void @__cxx_global_var_init.1()
3830 // CHECK-TLS1-NEXT:    ret void
3831 //
3832 //
3833 // CHECK-TLS1-LABEL: define {{[^@]+}}@__tls_init
3834 // CHECK-TLS1-SAME: () #[[ATTR0]] {
3835 // CHECK-TLS1-NEXT:  entry:
3836 // CHECK-TLS1-NEXT:    [[TMP0:%.*]] = load i8, ptr @__tls_guard, align 1
3837 // CHECK-TLS1-NEXT:    [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0
3838 // CHECK-TLS1-NEXT:    br i1 [[GUARD_UNINITIALIZED]], label [[INIT:%.*]], label [[EXIT:%.*]], !prof [[PROF3]]
3839 // CHECK-TLS1:       init:
3840 // CHECK-TLS1-NEXT:    store i8 1, ptr @__tls_guard, align 1
3841 // CHECK-TLS1-NEXT:    call void @__cxx_global_var_init()
3842 // CHECK-TLS1-NEXT:    call void @__cxx_global_var_init.2()
3843 // CHECK-TLS1-NEXT:    br label [[EXIT]]
3844 // CHECK-TLS1:       exit:
3845 // CHECK-TLS1-NEXT:    ret void
3846 //
3847 //
3848 // CHECK-TLS2-LABEL: define {{[^@]+}}@main
3849 // CHECK-TLS2-SAME: () #[[ATTR0:[0-9]+]] {
3850 // CHECK-TLS2-NEXT:  entry:
3851 // CHECK-TLS2-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
3852 // CHECK-TLS2-NEXT:    [[RES:%.*]] = alloca i32, align 4
3853 // CHECK-TLS2-NEXT:    store i32 0, ptr [[RETVAL]], align 4
3854 // CHECK-TLS2-NEXT:    [[TMP0:%.*]] = load i8, ptr @_ZGVZ4mainE2sm, align 1
3855 // CHECK-TLS2-NEXT:    [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0
3856 // CHECK-TLS2-NEXT:    br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF3:![0-9]+]]
3857 // CHECK-TLS2:       init.check:
3858 // CHECK-TLS2-NEXT:    [[TMP1:%.*]] = call ptr @_ZTWL3gs1()
3859 // CHECK-TLS2-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP1]], i32 0, i32 0
3860 // CHECK-TLS2-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 4
3861 // CHECK-TLS2-NEXT:    call void @_ZZ4mainEN5SmainC1Ei(ptr noundef nonnull align 8 dereferenceable(24) @_ZZ4mainE2sm, i32 noundef [[TMP2]])
3862 // CHECK-TLS2-NEXT:    [[TMP3:%.*]] = call i32 @__cxa_thread_atexit(ptr @_ZZ4mainEN5SmainD1Ev, ptr @_ZZ4mainE2sm, ptr @__dso_handle) #[[ATTR4:[0-9]+]]
3863 // CHECK-TLS2-NEXT:    store i8 1, ptr @_ZGVZ4mainE2sm, align 1
3864 // CHECK-TLS2-NEXT:    br label [[INIT_END]]
3865 // CHECK-TLS2:       init.end:
3866 // CHECK-TLS2-NEXT:    [[TMP4:%.*]] = call ptr @_ZTWN6Static1sE()
3867 // CHECK-TLS2-NEXT:    [[A1:%.*]] = getelementptr inbounds [[STRUCT_S3:%.*]], ptr [[TMP4]], i32 0, i32 0
3868 // CHECK-TLS2-NEXT:    [[TMP5:%.*]] = load i32, ptr [[A1]], align 4
3869 // CHECK-TLS2-NEXT:    store i32 [[TMP5]], ptr [[RES]], align 4
3870 // CHECK-TLS2-NEXT:    [[TMP6:%.*]] = call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @_ZZ4mainE2sm)
3871 // CHECK-TLS2-NEXT:    [[A2:%.*]] = getelementptr inbounds [[STRUCT_SMAIN:%.*]], ptr [[TMP6]], i32 0, i32 0
3872 // CHECK-TLS2-NEXT:    [[TMP7:%.*]] = load i32, ptr [[A2]], align 8
3873 // CHECK-TLS2-NEXT:    [[TMP8:%.*]] = load i32, ptr [[RES]], align 4
3874 // CHECK-TLS2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP8]], [[TMP7]]
3875 // CHECK-TLS2-NEXT:    store i32 [[ADD]], ptr [[RES]], align 4
3876 // CHECK-TLS2-NEXT:    [[TMP9:%.*]] = call ptr @_ZTWL3gs1()
3877 // CHECK-TLS2-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP9]], i32 0, i32 0
3878 // CHECK-TLS2-NEXT:    [[TMP10:%.*]] = load i32, ptr [[A3]], align 4
3879 // CHECK-TLS2-NEXT:    [[TMP11:%.*]] = load i32, ptr [[RES]], align 4
3880 // CHECK-TLS2-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP11]], [[TMP10]]
3881 // CHECK-TLS2-NEXT:    store i32 [[ADD4]], ptr [[RES]], align 4
3882 // CHECK-TLS2-NEXT:    [[TMP12:%.*]] = load i32, ptr @_ZL3gs2, align 8
3883 // CHECK-TLS2-NEXT:    [[TMP13:%.*]] = load i32, ptr [[RES]], align 4
3884 // CHECK-TLS2-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP13]], [[TMP12]]
3885 // CHECK-TLS2-NEXT:    store i32 [[ADD5]], ptr [[RES]], align 4
3886 // CHECK-TLS2-NEXT:    [[TMP14:%.*]] = call ptr @_ZTW3gs3()
3887 // CHECK-TLS2-NEXT:    [[A6:%.*]] = getelementptr inbounds [[STRUCT_S5:%.*]], ptr [[TMP14]], i32 0, i32 0
3888 // CHECK-TLS2-NEXT:    [[TMP15:%.*]] = load i32, ptr [[A6]], align 4
3889 // CHECK-TLS2-NEXT:    [[TMP16:%.*]] = load i32, ptr [[RES]], align 4
3890 // CHECK-TLS2-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP16]], [[TMP15]]
3891 // CHECK-TLS2-NEXT:    store i32 [[ADD7]], ptr [[RES]], align 4
3892 // CHECK-TLS2-NEXT:    [[TMP17:%.*]] = call ptr @_ZTW5arr_x()
3893 // CHECK-TLS2-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP17]], i64 0, i64 1
3894 // CHECK-TLS2-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], i64 0, i64 1
3895 // CHECK-TLS2-NEXT:    [[A9:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYIDX8]], i32 0, i32 0
3896 // CHECK-TLS2-NEXT:    [[TMP18:%.*]] = load i32, ptr [[A9]], align 4
3897 // CHECK-TLS2-NEXT:    [[TMP19:%.*]] = load i32, ptr [[RES]], align 4
3898 // CHECK-TLS2-NEXT:    [[ADD10:%.*]] = add nsw i32 [[TMP19]], [[TMP18]]
3899 // CHECK-TLS2-NEXT:    store i32 [[ADD10]], ptr [[RES]], align 4
3900 // CHECK-TLS2-NEXT:    [[TMP20:%.*]] = call ptr @_ZTWN2STIiE2stE()
3901 // CHECK-TLS2-NEXT:    [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4
3902 // CHECK-TLS2-NEXT:    [[TMP22:%.*]] = load i32, ptr [[RES]], align 4
3903 // CHECK-TLS2-NEXT:    [[ADD11:%.*]] = add nsw i32 [[TMP22]], [[TMP21]]
3904 // CHECK-TLS2-NEXT:    store i32 [[ADD11]], ptr [[RES]], align 4
3905 // CHECK-TLS2-NEXT:    [[TMP23:%.*]] = call ptr @_ZTWN2STIfE2stE()
3906 // CHECK-TLS2-NEXT:    [[TMP24:%.*]] = load float, ptr [[TMP23]], align 4
3907 // CHECK-TLS2-NEXT:    [[CONV:%.*]] = fptosi float [[TMP24]] to i32
3908 // CHECK-TLS2-NEXT:    [[TMP25:%.*]] = load i32, ptr [[RES]], align 4
3909 // CHECK-TLS2-NEXT:    [[ADD12:%.*]] = add nsw i32 [[TMP25]], [[CONV]]
3910 // CHECK-TLS2-NEXT:    store i32 [[ADD12]], ptr [[RES]], align 4
3911 // CHECK-TLS2-NEXT:    [[TMP26:%.*]] = call ptr @_ZTWN2STI2S4E2stE()
3912 // CHECK-TLS2-NEXT:    [[A13:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[TMP26]], i32 0, i32 0
3913 // CHECK-TLS2-NEXT:    [[TMP27:%.*]] = load i32, ptr [[A13]], align 4
3914 // CHECK-TLS2-NEXT:    [[TMP28:%.*]] = load i32, ptr [[RES]], align 4
3915 // CHECK-TLS2-NEXT:    [[ADD14:%.*]] = add nsw i32 [[TMP28]], [[TMP27]]
3916 // CHECK-TLS2-NEXT:    store i32 [[ADD14]], ptr [[RES]], align 4
3917 // CHECK-TLS2-NEXT:    [[TMP29:%.*]] = load i32, ptr [[RES]], align 4
3918 // CHECK-TLS2-NEXT:    ret i32 [[TMP29]]
3919 //
3920 //
3921 // CHECK-TLS2-LABEL: define {{[^@]+}}@_ZTWL3gs1
3922 // CHECK-TLS2-SAME: () #[[ATTR1:[0-9]+]] {
3923 // CHECK-TLS2-NEXT:    call void @_ZTHL3gs1()
3924 // CHECK-TLS2-NEXT:    [[TMP1:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZL3gs1)
3925 // CHECK-TLS2-NEXT:    ret ptr [[TMP1]]
3926 //
3927 //
3928 // CHECK-TLS2-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC1Ei
3929 // CHECK-TLS2-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] align 2 {
3930 // CHECK-TLS2-NEXT:  entry:
3931 // CHECK-TLS2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
3932 // CHECK-TLS2-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
3933 // CHECK-TLS2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
3934 // CHECK-TLS2-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
3935 // CHECK-TLS2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
3936 // CHECK-TLS2-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
3937 // CHECK-TLS2-NEXT:    call void @_ZZ4mainEN5SmainC2Ei(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]], i32 noundef [[TMP0]])
3938 // CHECK-TLS2-NEXT:    ret void
3939 //
3940 //
3941 // CHECK-TLS2-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD1Ev
3942 // CHECK-TLS2-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR3:[0-9]+]] align 2 {
3943 // CHECK-TLS2-NEXT:  entry:
3944 // CHECK-TLS2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
3945 // CHECK-TLS2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
3946 // CHECK-TLS2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
3947 // CHECK-TLS2-NEXT:    call void @_ZZ4mainEN5SmainD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR4]]
3948 // CHECK-TLS2-NEXT:    ret void
3949 //
3950 //
3951 // CHECK-TLS2-LABEL: define {{[^@]+}}@_ZTWN6Static1sE
3952 // CHECK-TLS2-SAME: () #[[ATTR1]] comdat {
3953 // CHECK-TLS2-NEXT:    br i1 icmp ne (ptr @_ZTHN6Static1sE, ptr null), label [[TMP1:%.*]], label [[TMP2:%.*]]
3954 // CHECK-TLS2:       1:
3955 // CHECK-TLS2-NEXT:    call void @_ZTHN6Static1sE()
3956 // CHECK-TLS2-NEXT:    br label [[TMP2]]
3957 // CHECK-TLS2:       2:
3958 // CHECK-TLS2-NEXT:    [[TMP3:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZN6Static1sE)
3959 // CHECK-TLS2-NEXT:    ret ptr [[TMP3]]
3960 //
3961 //
3962 // CHECK-TLS2-LABEL: define {{[^@]+}}@_ZTW3gs3
3963 // CHECK-TLS2-SAME: () #[[ATTR1]] comdat {
3964 // CHECK-TLS2-NEXT:    br i1 icmp ne (ptr @_ZTH3gs3, ptr null), label [[TMP1:%.*]], label [[TMP2:%.*]]
3965 // CHECK-TLS2:       1:
3966 // CHECK-TLS2-NEXT:    call void @_ZTH3gs3()
3967 // CHECK-TLS2-NEXT:    br label [[TMP2]]
3968 // CHECK-TLS2:       2:
3969 // CHECK-TLS2-NEXT:    [[TMP3:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @gs3)
3970 // CHECK-TLS2-NEXT:    ret ptr [[TMP3]]
3971 //
3972 //
3973 // CHECK-TLS2-LABEL: define {{[^@]+}}@_ZTW5arr_x
3974 // CHECK-TLS2-SAME: () #[[ATTR1]] comdat {
3975 // CHECK-TLS2-NEXT:    call void @_ZTH5arr_x()
3976 // CHECK-TLS2-NEXT:    [[TMP1:%.*]] = call align 16 ptr @llvm.threadlocal.address.p0(ptr align 16 @arr_x)
3977 // CHECK-TLS2-NEXT:    ret ptr [[TMP1]]
3978 //
3979 //
3980 // CHECK-TLS2-LABEL: define {{[^@]+}}@_ZTWN2STIiE2stE
3981 // CHECK-TLS2-SAME: () #[[ATTR1]] comdat {
3982 // CHECK-TLS2-NEXT:    [[TMP1:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZN2STIiE2stE)
3983 // CHECK-TLS2-NEXT:    ret ptr [[TMP1]]
3984 //
3985 //
3986 // CHECK-TLS2-LABEL: define {{[^@]+}}@_ZTWN2STIfE2stE
3987 // CHECK-TLS2-SAME: () #[[ATTR1]] comdat {
3988 // CHECK-TLS2-NEXT:    [[TMP1:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZN2STIfE2stE)
3989 // CHECK-TLS2-NEXT:    ret ptr [[TMP1]]
3990 //
3991 //
3992 // CHECK-TLS2-LABEL: define {{[^@]+}}@_ZTWN2STI2S4E2stE
3993 // CHECK-TLS2-SAME: () #[[ATTR1]] comdat {
3994 // CHECK-TLS2-NEXT:    call void @_ZTHN2STI2S4E2stE()
3995 // CHECK-TLS2-NEXT:    [[TMP1:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZN2STI2S4E2stE)
3996 // CHECK-TLS2-NEXT:    ret ptr [[TMP1]]
3997 //
3998 //
3999 // CHECK-TLS2-LABEL: define {{[^@]+}}@_Z6foobarv
4000 // CHECK-TLS2-SAME: () #[[ATTR6:[0-9]+]] {
4001 // CHECK-TLS2-NEXT:  entry:
4002 // CHECK-TLS2-NEXT:    [[RES:%.*]] = alloca i32, align 4
4003 // CHECK-TLS2-NEXT:    [[TMP0:%.*]] = call ptr @_ZTWN6Static1sE()
4004 // CHECK-TLS2-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S3:%.*]], ptr [[TMP0]], i32 0, i32 0
4005 // CHECK-TLS2-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A]], align 4
4006 // CHECK-TLS2-NEXT:    store i32 [[TMP1]], ptr [[RES]], align 4
4007 // CHECK-TLS2-NEXT:    [[TMP2:%.*]] = call ptr @_ZTWL3gs1()
4008 // CHECK-TLS2-NEXT:    [[A1:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP2]], i32 0, i32 0
4009 // CHECK-TLS2-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A1]], align 4
4010 // CHECK-TLS2-NEXT:    [[TMP4:%.*]] = load i32, ptr [[RES]], align 4
4011 // CHECK-TLS2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP4]], [[TMP3]]
4012 // CHECK-TLS2-NEXT:    store i32 [[ADD]], ptr [[RES]], align 4
4013 // CHECK-TLS2-NEXT:    [[TMP5:%.*]] = load i32, ptr @_ZL3gs2, align 8
4014 // CHECK-TLS2-NEXT:    [[TMP6:%.*]] = load i32, ptr [[RES]], align 4
4015 // CHECK-TLS2-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP6]], [[TMP5]]
4016 // CHECK-TLS2-NEXT:    store i32 [[ADD2]], ptr [[RES]], align 4
4017 // CHECK-TLS2-NEXT:    [[TMP7:%.*]] = call ptr @_ZTW3gs3()
4018 // CHECK-TLS2-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S5:%.*]], ptr [[TMP7]], i32 0, i32 0
4019 // CHECK-TLS2-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A3]], align 4
4020 // CHECK-TLS2-NEXT:    [[TMP9:%.*]] = load i32, ptr [[RES]], align 4
4021 // CHECK-TLS2-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP9]], [[TMP8]]
4022 // CHECK-TLS2-NEXT:    store i32 [[ADD4]], ptr [[RES]], align 4
4023 // CHECK-TLS2-NEXT:    [[TMP10:%.*]] = call ptr @_ZTW5arr_x()
4024 // CHECK-TLS2-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP10]], i64 0, i64 1
4025 // CHECK-TLS2-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], i64 0, i64 1
4026 // CHECK-TLS2-NEXT:    [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYIDX5]], i32 0, i32 0
4027 // CHECK-TLS2-NEXT:    [[TMP11:%.*]] = load i32, ptr [[A6]], align 4
4028 // CHECK-TLS2-NEXT:    [[TMP12:%.*]] = load i32, ptr [[RES]], align 4
4029 // CHECK-TLS2-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP12]], [[TMP11]]
4030 // CHECK-TLS2-NEXT:    store i32 [[ADD7]], ptr [[RES]], align 4
4031 // CHECK-TLS2-NEXT:    [[TMP13:%.*]] = call ptr @_ZTWN2STIiE2stE()
4032 // CHECK-TLS2-NEXT:    [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4
4033 // CHECK-TLS2-NEXT:    [[TMP15:%.*]] = load i32, ptr [[RES]], align 4
4034 // CHECK-TLS2-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP15]], [[TMP14]]
4035 // CHECK-TLS2-NEXT:    store i32 [[ADD8]], ptr [[RES]], align 4
4036 // CHECK-TLS2-NEXT:    [[TMP16:%.*]] = call ptr @_ZTWN2STIfE2stE()
4037 // CHECK-TLS2-NEXT:    [[TMP17:%.*]] = load float, ptr [[TMP16]], align 4
4038 // CHECK-TLS2-NEXT:    [[CONV:%.*]] = fptosi float [[TMP17]] to i32
4039 // CHECK-TLS2-NEXT:    [[TMP18:%.*]] = load i32, ptr [[RES]], align 4
4040 // CHECK-TLS2-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP18]], [[CONV]]
4041 // CHECK-TLS2-NEXT:    store i32 [[ADD9]], ptr [[RES]], align 4
4042 // CHECK-TLS2-NEXT:    [[TMP19:%.*]] = call ptr @_ZTWN2STI2S4E2stE()
4043 // CHECK-TLS2-NEXT:    [[A10:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[TMP19]], i32 0, i32 0
4044 // CHECK-TLS2-NEXT:    [[TMP20:%.*]] = load i32, ptr [[A10]], align 4
4045 // CHECK-TLS2-NEXT:    [[TMP21:%.*]] = load i32, ptr [[RES]], align 4
4046 // CHECK-TLS2-NEXT:    [[ADD11:%.*]] = add nsw i32 [[TMP21]], [[TMP20]]
4047 // CHECK-TLS2-NEXT:    store i32 [[ADD11]], ptr [[RES]], align 4
4048 // CHECK-TLS2-NEXT:    [[TMP22:%.*]] = load i32, ptr [[RES]], align 4
4049 // CHECK-TLS2-NEXT:    ret i32 [[TMP22]]
4050 //
4051 //
4052 // CHECK-TLS2-LABEL: define {{[^@]+}}@__cxx_global_var_init
4053 // CHECK-TLS2-SAME: () #[[ATTR7:[0-9]+]] {
4054 // CHECK-TLS2-NEXT:  entry:
4055 // CHECK-TLS2-NEXT:    call void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @_ZL3gs1, i32 noundef 5)
4056 // CHECK-TLS2-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_thread_atexit(ptr @_ZN2S1D1Ev, ptr @_ZL3gs1, ptr @__dso_handle) #[[ATTR4]]
4057 // CHECK-TLS2-NEXT:    ret void
4058 //
4059 //
4060 // CHECK-TLS2-LABEL: define {{[^@]+}}@_ZN2S1C1Ei
4061 // CHECK-TLS2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
4062 // CHECK-TLS2-NEXT:  entry:
4063 // CHECK-TLS2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
4064 // CHECK-TLS2-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
4065 // CHECK-TLS2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
4066 // CHECK-TLS2-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
4067 // CHECK-TLS2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
4068 // CHECK-TLS2-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
4069 // CHECK-TLS2-NEXT:    call void @_ZN2S1C2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])
4070 // CHECK-TLS2-NEXT:    ret void
4071 //
4072 //
4073 // CHECK-TLS2-LABEL: define {{[^@]+}}@_ZN2S1D1Ev
4074 // CHECK-TLS2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 {
4075 // CHECK-TLS2-NEXT:  entry:
4076 // CHECK-TLS2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
4077 // CHECK-TLS2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
4078 // CHECK-TLS2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
4079 // CHECK-TLS2-NEXT:    call void @_ZN2S1D2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
4080 // CHECK-TLS2-NEXT:    ret void
4081 //
4082 //
4083 // CHECK-TLS2-LABEL: define {{[^@]+}}@_ZN2S1C2Ei
4084 // CHECK-TLS2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 {
4085 // CHECK-TLS2-NEXT:  entry:
4086 // CHECK-TLS2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
4087 // CHECK-TLS2-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
4088 // CHECK-TLS2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
4089 // CHECK-TLS2-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
4090 // CHECK-TLS2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
4091 // CHECK-TLS2-NEXT:    [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0
4092 // CHECK-TLS2-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
4093 // CHECK-TLS2-NEXT:    store i32 [[TMP0]], ptr [[A2]], align 4
4094 // CHECK-TLS2-NEXT:    ret void
4095 //
4096 //
4097 // CHECK-TLS2-LABEL: define {{[^@]+}}@_ZN2S1D2Ev
4098 // CHECK-TLS2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 {
4099 // CHECK-TLS2-NEXT:  entry:
4100 // CHECK-TLS2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
4101 // CHECK-TLS2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
4102 // CHECK-TLS2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
4103 // CHECK-TLS2-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0
4104 // CHECK-TLS2-NEXT:    store i32 0, ptr [[A]], align 4
4105 // CHECK-TLS2-NEXT:    ret void
4106 //
4107 //
4108 // CHECK-TLS2-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
4109 // CHECK-TLS2-SAME: () #[[ATTR7]] {
4110 // CHECK-TLS2-NEXT:  entry:
4111 // CHECK-TLS2-NEXT:    call void @_ZN2S2C1Ei(ptr noundef nonnull align 8 dereferenceable(16) @_ZL3gs2, i32 noundef 27)
4112 // CHECK-TLS2-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S2D1Ev, ptr @_ZL3gs2, ptr @__dso_handle) #[[ATTR4]]
4113 // CHECK-TLS2-NEXT:    ret void
4114 //
4115 //
4116 // CHECK-TLS2-LABEL: define {{[^@]+}}@_ZN2S2C1Ei
4117 // CHECK-TLS2-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
4118 // CHECK-TLS2-NEXT:  entry:
4119 // CHECK-TLS2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
4120 // CHECK-TLS2-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
4121 // CHECK-TLS2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
4122 // CHECK-TLS2-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
4123 // CHECK-TLS2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
4124 // CHECK-TLS2-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
4125 // CHECK-TLS2-NEXT:    call void @_ZN2S2C2Ei(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], i32 noundef [[TMP0]])
4126 // CHECK-TLS2-NEXT:    ret void
4127 //
4128 //
4129 // CHECK-TLS2-LABEL: define {{[^@]+}}@_ZN2S2D1Ev
4130 // CHECK-TLS2-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 {
4131 // CHECK-TLS2-NEXT:  entry:
4132 // CHECK-TLS2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
4133 // CHECK-TLS2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
4134 // CHECK-TLS2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
4135 // CHECK-TLS2-NEXT:    call void @_ZN2S2D2Ev(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]]) #[[ATTR4]]
4136 // CHECK-TLS2-NEXT:    ret void
4137 //
4138 //
4139 // CHECK-TLS2-LABEL: define {{[^@]+}}@_ZN2S2C2Ei
4140 // CHECK-TLS2-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 {
4141 // CHECK-TLS2-NEXT:  entry:
4142 // CHECK-TLS2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
4143 // CHECK-TLS2-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
4144 // CHECK-TLS2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
4145 // CHECK-TLS2-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
4146 // CHECK-TLS2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
4147 // CHECK-TLS2-NEXT:    [[A2:%.*]] = getelementptr inbounds [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0
4148 // CHECK-TLS2-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
4149 // CHECK-TLS2-NEXT:    store i32 [[TMP0]], ptr [[A2]], align 8
4150 // CHECK-TLS2-NEXT:    ret void
4151 //
4152 //
4153 // CHECK-TLS2-LABEL: define {{[^@]+}}@_ZN2S2D2Ev
4154 // CHECK-TLS2-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 {
4155 // CHECK-TLS2-NEXT:  entry:
4156 // CHECK-TLS2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
4157 // CHECK-TLS2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
4158 // CHECK-TLS2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
4159 // CHECK-TLS2-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0
4160 // CHECK-TLS2-NEXT:    store i32 0, ptr [[A]], align 8
4161 // CHECK-TLS2-NEXT:    ret void
4162 //
4163 //
4164 // CHECK-TLS2-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
4165 // CHECK-TLS2-SAME: () #[[ATTR7]] personality ptr @__gxx_personality_v0 {
4166 // CHECK-TLS2-NEXT:  entry:
4167 // CHECK-TLS2-NEXT:    [[ARRAYINIT_ENDOFINIT:%.*]] = alloca ptr, align 8
4168 // CHECK-TLS2-NEXT:    [[ARRAYINIT_ENDOFINIT1:%.*]] = alloca ptr, align 8
4169 // CHECK-TLS2-NEXT:    [[EXN_SLOT:%.*]] = alloca ptr, align 8
4170 // CHECK-TLS2-NEXT:    [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4
4171 // CHECK-TLS2-NEXT:    [[ARRAYINIT_ENDOFINIT5:%.*]] = alloca ptr, align 8
4172 // CHECK-TLS2-NEXT:    store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT]], align 8
4173 // CHECK-TLS2-NEXT:    store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT1]], align 8
4174 // CHECK-TLS2-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @arr_x, i32 noundef 1)
4175 // CHECK-TLS2-NEXT:    to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]]
4176 // CHECK-TLS2:       invoke.cont:
4177 // CHECK-TLS2-NEXT:    store ptr getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT1]], align 8
4178 // CHECK-TLS2-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 1), i32 noundef 2)
4179 // CHECK-TLS2-NEXT:    to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD]]
4180 // CHECK-TLS2:       invoke.cont2:
4181 // CHECK-TLS2-NEXT:    store ptr getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), ptr [[ARRAYINIT_ENDOFINIT1]], align 8
4182 // CHECK-TLS2-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), i32 noundef 3)
4183 // CHECK-TLS2-NEXT:    to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]]
4184 // CHECK-TLS2:       invoke.cont3:
4185 // CHECK-TLS2-NEXT:    store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT]], align 8
4186 // CHECK-TLS2-NEXT:    store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8
4187 // CHECK-TLS2-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i32 noundef 4)
4188 // CHECK-TLS2-NEXT:    to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD6:%.*]]
4189 // CHECK-TLS2:       invoke.cont7:
4190 // CHECK-TLS2-NEXT:    store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8
4191 // CHECK-TLS2-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), i32 noundef 5)
4192 // CHECK-TLS2-NEXT:    to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD6]]
4193 // CHECK-TLS2:       invoke.cont8:
4194 // CHECK-TLS2-NEXT:    store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), ptr [[ARRAYINIT_ENDOFINIT5]], align 8
4195 // CHECK-TLS2-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), i32 noundef 6)
4196 // CHECK-TLS2-NEXT:    to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD6]]
4197 // CHECK-TLS2:       invoke.cont9:
4198 // CHECK-TLS2-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_thread_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR4]]
4199 // CHECK-TLS2-NEXT:    ret void
4200 // CHECK-TLS2:       lpad:
4201 // CHECK-TLS2-NEXT:    [[TMP1:%.*]] = landingpad { ptr, i32 }
4202 // CHECK-TLS2-NEXT:    cleanup
4203 // CHECK-TLS2-NEXT:    [[TMP2:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 0
4204 // CHECK-TLS2-NEXT:    store ptr [[TMP2]], ptr [[EXN_SLOT]], align 8
4205 // CHECK-TLS2-NEXT:    [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 1
4206 // CHECK-TLS2-NEXT:    store i32 [[TMP3]], ptr [[EHSELECTOR_SLOT]], align 4
4207 // CHECK-TLS2-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT1]], align 8
4208 // CHECK-TLS2-NEXT:    [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr @arr_x, [[TMP4]]
4209 // CHECK-TLS2-NEXT:    br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY:%.*]]
4210 // CHECK-TLS2:       arraydestroy.body:
4211 // CHECK-TLS2-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP4]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
4212 // CHECK-TLS2-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
4213 // CHECK-TLS2-NEXT:    call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
4214 // CHECK-TLS2-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x
4215 // CHECK-TLS2-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4]], label [[ARRAYDESTROY_BODY]]
4216 // CHECK-TLS2:       arraydestroy.done4:
4217 // CHECK-TLS2-NEXT:    br label [[EHCLEANUP:%.*]]
4218 // CHECK-TLS2:       lpad6:
4219 // CHECK-TLS2-NEXT:    [[TMP5:%.*]] = landingpad { ptr, i32 }
4220 // CHECK-TLS2-NEXT:    cleanup
4221 // CHECK-TLS2-NEXT:    [[TMP6:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 0
4222 // CHECK-TLS2-NEXT:    store ptr [[TMP6]], ptr [[EXN_SLOT]], align 8
4223 // CHECK-TLS2-NEXT:    [[TMP7:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 1
4224 // CHECK-TLS2-NEXT:    store i32 [[TMP7]], ptr [[EHSELECTOR_SLOT]], align 4
4225 // CHECK-TLS2-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT5]], align 8
4226 // CHECK-TLS2-NEXT:    [[ARRAYDESTROY_ISEMPTY10:%.*]] = icmp eq ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), [[TMP8]]
4227 // CHECK-TLS2-NEXT:    br i1 [[ARRAYDESTROY_ISEMPTY10]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY11:%.*]]
4228 // CHECK-TLS2:       arraydestroy.body11:
4229 // CHECK-TLS2-NEXT:    [[ARRAYDESTROY_ELEMENTPAST12:%.*]] = phi ptr [ [[TMP8]], [[LPAD6]] ], [ [[ARRAYDESTROY_ELEMENT13:%.*]], [[ARRAYDESTROY_BODY11]] ]
4230 // CHECK-TLS2-NEXT:    [[ARRAYDESTROY_ELEMENT13]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST12]], i64 -1
4231 // CHECK-TLS2-NEXT:    call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR4]]
4232 // CHECK-TLS2-NEXT:    [[ARRAYDESTROY_DONE14:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1)
4233 // CHECK-TLS2-NEXT:    br i1 [[ARRAYDESTROY_DONE14]], label [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_BODY11]]
4234 // CHECK-TLS2:       arraydestroy.done15:
4235 // CHECK-TLS2-NEXT:    br label [[EHCLEANUP]]
4236 // CHECK-TLS2:       ehcleanup:
4237 // CHECK-TLS2-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT]], align 8
4238 // CHECK-TLS2-NEXT:    [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP9]], i64 0, i64 0
4239 // CHECK-TLS2-NEXT:    [[ARRAYDESTROY_ISEMPTY16:%.*]] = icmp eq ptr @arr_x, [[PAD_ARRAYEND]]
4240 // CHECK-TLS2-NEXT:    br i1 [[ARRAYDESTROY_ISEMPTY16]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17:%.*]]
4241 // CHECK-TLS2:       arraydestroy.body17:
4242 // CHECK-TLS2-NEXT:    [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi ptr [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ]
4243 // CHECK-TLS2-NEXT:    [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1
4244 // CHECK-TLS2-NEXT:    call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR4]]
4245 // CHECK-TLS2-NEXT:    [[ARRAYDESTROY_DONE20:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT19]], @arr_x
4246 // CHECK-TLS2-NEXT:    br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]]
4247 // CHECK-TLS2:       arraydestroy.done21:
4248 // CHECK-TLS2-NEXT:    br label [[EH_RESUME:%.*]]
4249 // CHECK-TLS2:       eh.resume:
4250 // CHECK-TLS2-NEXT:    [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8
4251 // CHECK-TLS2-NEXT:    [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4
4252 // CHECK-TLS2-NEXT:    [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0
4253 // CHECK-TLS2-NEXT:    [[LPAD_VAL22:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1
4254 // CHECK-TLS2-NEXT:    resume { ptr, i32 } [[LPAD_VAL22]]
4255 //
4256 //
4257 // CHECK-TLS2-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
4258 // CHECK-TLS2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR7]] {
4259 // CHECK-TLS2-NEXT:  entry:
4260 // CHECK-TLS2-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
4261 // CHECK-TLS2-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
4262 // CHECK-TLS2-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
4263 // CHECK-TLS2:       arraydestroy.body:
4264 // CHECK-TLS2-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 6), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
4265 // CHECK-TLS2-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
4266 // CHECK-TLS2-NEXT:    call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
4267 // CHECK-TLS2-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x
4268 // CHECK-TLS2-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
4269 // CHECK-TLS2:       arraydestroy.done1:
4270 // CHECK-TLS2-NEXT:    ret void
4271 //
4272 //
4273 // CHECK-TLS2-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC2Ei
4274 // CHECK-TLS2-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR3]] align 2 {
4275 // CHECK-TLS2-NEXT:  entry:
4276 // CHECK-TLS2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
4277 // CHECK-TLS2-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
4278 // CHECK-TLS2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
4279 // CHECK-TLS2-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
4280 // CHECK-TLS2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
4281 // CHECK-TLS2-NEXT:    [[A2:%.*]] = getelementptr inbounds [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0
4282 // CHECK-TLS2-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
4283 // CHECK-TLS2-NEXT:    store i32 [[TMP0]], ptr [[A2]], align 8
4284 // CHECK-TLS2-NEXT:    ret void
4285 //
4286 //
4287 // CHECK-TLS2-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD2Ev
4288 // CHECK-TLS2-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] align 2 {
4289 // CHECK-TLS2-NEXT:  entry:
4290 // CHECK-TLS2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
4291 // CHECK-TLS2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
4292 // CHECK-TLS2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
4293 // CHECK-TLS2-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0
4294 // CHECK-TLS2-NEXT:    store i32 0, ptr [[A]], align 8
4295 // CHECK-TLS2-NEXT:    ret void
4296 //
4297 //
4298 // CHECK-TLS2-LABEL: define {{[^@]+}}@__cxx_global_var_init.3
4299 // CHECK-TLS2-SAME: () #[[ATTR7]] {
4300 // CHECK-TLS2-NEXT:  entry:
4301 // CHECK-TLS2-NEXT:    [[TMP0:%.*]] = load i8, ptr @_ZGVN2STI2S4E2stE, align 8
4302 // CHECK-TLS2-NEXT:    [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0
4303 // CHECK-TLS2-NEXT:    br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]]
4304 // CHECK-TLS2:       init.check:
4305 // CHECK-TLS2-NEXT:    store i8 1, ptr @_ZGVN2STI2S4E2stE, align 8
4306 // CHECK-TLS2-NEXT:    call void @_ZN2S4C1Ei(ptr noundef nonnull align 4 dereferenceable(8) @_ZN2STI2S4E2stE, i32 noundef 23)
4307 // CHECK-TLS2-NEXT:    [[TMP1:%.*]] = call i32 @__cxa_thread_atexit(ptr @_ZN2S4D1Ev, ptr @_ZN2STI2S4E2stE, ptr @__dso_handle) #[[ATTR4]]
4308 // CHECK-TLS2-NEXT:    br label [[INIT_END]]
4309 // CHECK-TLS2:       init.end:
4310 // CHECK-TLS2-NEXT:    ret void
4311 //
4312 //
4313 // CHECK-TLS2-LABEL: define {{[^@]+}}@_ZN2S4C1Ei
4314 // CHECK-TLS2-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
4315 // CHECK-TLS2-NEXT:  entry:
4316 // CHECK-TLS2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
4317 // CHECK-TLS2-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
4318 // CHECK-TLS2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
4319 // CHECK-TLS2-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
4320 // CHECK-TLS2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
4321 // CHECK-TLS2-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
4322 // CHECK-TLS2-NEXT:    call void @_ZN2S4C2Ei(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]], i32 noundef [[TMP0]])
4323 // CHECK-TLS2-NEXT:    ret void
4324 //
4325 //
4326 // CHECK-TLS2-LABEL: define {{[^@]+}}@_ZN2S4D1Ev
4327 // CHECK-TLS2-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 {
4328 // CHECK-TLS2-NEXT:  entry:
4329 // CHECK-TLS2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
4330 // CHECK-TLS2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
4331 // CHECK-TLS2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
4332 // CHECK-TLS2-NEXT:    call void @_ZN2S4D2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]]
4333 // CHECK-TLS2-NEXT:    ret void
4334 //
4335 //
4336 // CHECK-TLS2-LABEL: define {{[^@]+}}@_ZN2S4C2Ei
4337 // CHECK-TLS2-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 {
4338 // CHECK-TLS2-NEXT:  entry:
4339 // CHECK-TLS2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
4340 // CHECK-TLS2-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
4341 // CHECK-TLS2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
4342 // CHECK-TLS2-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
4343 // CHECK-TLS2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
4344 // CHECK-TLS2-NEXT:    [[A2:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0
4345 // CHECK-TLS2-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
4346 // CHECK-TLS2-NEXT:    store i32 [[TMP0]], ptr [[A2]], align 4
4347 // CHECK-TLS2-NEXT:    ret void
4348 //
4349 //
4350 // CHECK-TLS2-LABEL: define {{[^@]+}}@_ZN2S4D2Ev
4351 // CHECK-TLS2-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 {
4352 // CHECK-TLS2-NEXT:  entry:
4353 // CHECK-TLS2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
4354 // CHECK-TLS2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
4355 // CHECK-TLS2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
4356 // CHECK-TLS2-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0
4357 // CHECK-TLS2-NEXT:    store i32 0, ptr [[A]], align 4
4358 // CHECK-TLS2-NEXT:    ret void
4359 //
4360 //
4361 // CHECK-TLS2-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_threadprivate_codegen.cpp
4362 // CHECK-TLS2-SAME: () #[[ATTR7]] {
4363 // CHECK-TLS2-NEXT:  entry:
4364 // CHECK-TLS2-NEXT:    call void @__cxx_global_var_init.1()
4365 // CHECK-TLS2-NEXT:    ret void
4366 //
4367 //
4368 // CHECK-TLS2-LABEL: define {{[^@]+}}@__tls_init
4369 // CHECK-TLS2-SAME: () #[[ATTR7]] {
4370 // CHECK-TLS2-NEXT:  entry:
4371 // CHECK-TLS2-NEXT:    [[TMP0:%.*]] = load i8, ptr @__tls_guard, align 1
4372 // CHECK-TLS2-NEXT:    [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0
4373 // CHECK-TLS2-NEXT:    br i1 [[GUARD_UNINITIALIZED]], label [[INIT:%.*]], label [[EXIT:%.*]], !prof [[PROF3]]
4374 // CHECK-TLS2:       init:
4375 // CHECK-TLS2-NEXT:    store i8 1, ptr @__tls_guard, align 1
4376 // CHECK-TLS2-NEXT:    call void @__cxx_global_var_init()
4377 // CHECK-TLS2-NEXT:    call void @__cxx_global_var_init.2()
4378 // CHECK-TLS2-NEXT:    br label [[EXIT]]
4379 // CHECK-TLS2:       exit:
4380 // CHECK-TLS2-NEXT:    ret void
4381 //
4382 //
4383 // CHECK-TLS3-LABEL: define {{[^@]+}}@__cxx_global_var_init
4384 // CHECK-TLS3-SAME: () #[[ATTR0:[0-9]+]] !dbg [[DBG116:![0-9]+]] {
4385 // CHECK-TLS3-NEXT:  entry:
4386 // CHECK-TLS3-NEXT:    call void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @_ZL3gs1, i32 noundef 5), !dbg [[DBG120:![0-9]+]]
4387 // CHECK-TLS3-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_thread_atexit(ptr @_ZN2S1D1Ev, ptr @_ZL3gs1, ptr @__dso_handle) #[[ATTR3:[0-9]+]], !dbg [[DBG122:![0-9]+]]
4388 // CHECK-TLS3-NEXT:    ret void, !dbg [[DBG123:![0-9]+]]
4389 //
4390 //
4391 // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZN2S1C1Ei
4392 // CHECK-TLS3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 !dbg [[DBG124:![0-9]+]] {
4393 // CHECK-TLS3-NEXT:  entry:
4394 // CHECK-TLS3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
4395 // CHECK-TLS3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
4396 // CHECK-TLS3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
4397 // CHECK-TLS3-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META125:![0-9]+]], metadata !DIExpression()), !dbg [[DBG127:![0-9]+]]
4398 // CHECK-TLS3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
4399 // CHECK-TLS3-NEXT:    call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META128:![0-9]+]], metadata !DIExpression()), !dbg [[DBG129:![0-9]+]]
4400 // CHECK-TLS3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
4401 // CHECK-TLS3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG130:![0-9]+]]
4402 // CHECK-TLS3-NEXT:    call void @_ZN2S1C2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG130]]
4403 // CHECK-TLS3-NEXT:    ret void, !dbg [[DBG131:![0-9]+]]
4404 //
4405 //
4406 // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZN2S1D1Ev
4407 // CHECK-TLS3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 !dbg [[DBG132:![0-9]+]] {
4408 // CHECK-TLS3-NEXT:  entry:
4409 // CHECK-TLS3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
4410 // CHECK-TLS3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
4411 // CHECK-TLS3-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META133:![0-9]+]], metadata !DIExpression()), !dbg [[DBG134:![0-9]+]]
4412 // CHECK-TLS3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
4413 // CHECK-TLS3-NEXT:    call void @_ZN2S1D2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]], !dbg [[DBG135:![0-9]+]]
4414 // CHECK-TLS3-NEXT:    ret void, !dbg [[DBG136:![0-9]+]]
4415 //
4416 //
4417 // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZN2S1C2Ei
4418 // CHECK-TLS3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG137:![0-9]+]] {
4419 // CHECK-TLS3-NEXT:  entry:
4420 // CHECK-TLS3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
4421 // CHECK-TLS3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
4422 // CHECK-TLS3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
4423 // CHECK-TLS3-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META138:![0-9]+]], metadata !DIExpression()), !dbg [[DBG139:![0-9]+]]
4424 // CHECK-TLS3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
4425 // CHECK-TLS3-NEXT:    call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META140:![0-9]+]], metadata !DIExpression()), !dbg [[DBG141:![0-9]+]]
4426 // CHECK-TLS3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
4427 // CHECK-TLS3-NEXT:    [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG142:![0-9]+]]
4428 // CHECK-TLS3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG143:![0-9]+]]
4429 // CHECK-TLS3-NEXT:    store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG142]]
4430 // CHECK-TLS3-NEXT:    ret void, !dbg [[DBG144:![0-9]+]]
4431 //
4432 //
4433 // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZN2S1D2Ev
4434 // CHECK-TLS3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG145:![0-9]+]] {
4435 // CHECK-TLS3-NEXT:  entry:
4436 // CHECK-TLS3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
4437 // CHECK-TLS3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
4438 // CHECK-TLS3-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META146:![0-9]+]], metadata !DIExpression()), !dbg [[DBG147:![0-9]+]]
4439 // CHECK-TLS3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
4440 // CHECK-TLS3-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG148:![0-9]+]]
4441 // CHECK-TLS3-NEXT:    store i32 0, ptr [[A]], align 4, !dbg [[DBG150:![0-9]+]]
4442 // CHECK-TLS3-NEXT:    ret void, !dbg [[DBG151:![0-9]+]]
4443 //
4444 //
4445 // CHECK-TLS3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
4446 // CHECK-TLS3-SAME: () #[[ATTR0]] !dbg [[DBG152:![0-9]+]] {
4447 // CHECK-TLS3-NEXT:  entry:
4448 // CHECK-TLS3-NEXT:    call void @_ZN2S2C1Ei(ptr noundef nonnull align 8 dereferenceable(16) @_ZL3gs2, i32 noundef 27), !dbg [[DBG153:![0-9]+]]
4449 // CHECK-TLS3-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S2D1Ev, ptr @_ZL3gs2, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG155:![0-9]+]]
4450 // CHECK-TLS3-NEXT:    ret void, !dbg [[DBG156:![0-9]+]]
4451 //
4452 //
4453 // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZN2S2C1Ei
4454 // CHECK-TLS3-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 !dbg [[DBG157:![0-9]+]] {
4455 // CHECK-TLS3-NEXT:  entry:
4456 // CHECK-TLS3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
4457 // CHECK-TLS3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
4458 // CHECK-TLS3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
4459 // CHECK-TLS3-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META158:![0-9]+]], metadata !DIExpression()), !dbg [[DBG160:![0-9]+]]
4460 // CHECK-TLS3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
4461 // CHECK-TLS3-NEXT:    call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META161:![0-9]+]], metadata !DIExpression()), !dbg [[DBG162:![0-9]+]]
4462 // CHECK-TLS3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
4463 // CHECK-TLS3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG163:![0-9]+]]
4464 // CHECK-TLS3-NEXT:    call void @_ZN2S2C2Ei(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG163]]
4465 // CHECK-TLS3-NEXT:    ret void, !dbg [[DBG164:![0-9]+]]
4466 //
4467 //
4468 // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZN2S2D1Ev
4469 // CHECK-TLS3-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG165:![0-9]+]] {
4470 // CHECK-TLS3-NEXT:  entry:
4471 // CHECK-TLS3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
4472 // CHECK-TLS3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
4473 // CHECK-TLS3-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META166:![0-9]+]], metadata !DIExpression()), !dbg [[DBG167:![0-9]+]]
4474 // CHECK-TLS3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
4475 // CHECK-TLS3-NEXT:    call void @_ZN2S2D2Ev(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]]) #[[ATTR3]], !dbg [[DBG168:![0-9]+]]
4476 // CHECK-TLS3-NEXT:    ret void, !dbg [[DBG169:![0-9]+]]
4477 //
4478 //
4479 // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZN2S2C2Ei
4480 // CHECK-TLS3-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG170:![0-9]+]] {
4481 // CHECK-TLS3-NEXT:  entry:
4482 // CHECK-TLS3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
4483 // CHECK-TLS3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
4484 // CHECK-TLS3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
4485 // CHECK-TLS3-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META171:![0-9]+]], metadata !DIExpression()), !dbg [[DBG172:![0-9]+]]
4486 // CHECK-TLS3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
4487 // CHECK-TLS3-NEXT:    call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META173:![0-9]+]], metadata !DIExpression()), !dbg [[DBG174:![0-9]+]]
4488 // CHECK-TLS3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
4489 // CHECK-TLS3-NEXT:    [[A2:%.*]] = getelementptr inbounds [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG175:![0-9]+]]
4490 // CHECK-TLS3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG176:![0-9]+]]
4491 // CHECK-TLS3-NEXT:    store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG175]]
4492 // CHECK-TLS3-NEXT:    ret void, !dbg [[DBG177:![0-9]+]]
4493 //
4494 //
4495 // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZN2S2D2Ev
4496 // CHECK-TLS3-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG178:![0-9]+]] {
4497 // CHECK-TLS3-NEXT:  entry:
4498 // CHECK-TLS3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
4499 // CHECK-TLS3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
4500 // CHECK-TLS3-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META179:![0-9]+]], metadata !DIExpression()), !dbg [[DBG180:![0-9]+]]
4501 // CHECK-TLS3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
4502 // CHECK-TLS3-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG181:![0-9]+]]
4503 // CHECK-TLS3-NEXT:    store i32 0, ptr [[A]], align 8, !dbg [[DBG183:![0-9]+]]
4504 // CHECK-TLS3-NEXT:    ret void, !dbg [[DBG184:![0-9]+]]
4505 //
4506 //
4507 // CHECK-TLS3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
4508 // CHECK-TLS3-SAME: () #[[ATTR0]] personality ptr @__gxx_personality_v0 !dbg [[DBG185:![0-9]+]] {
4509 // CHECK-TLS3-NEXT:  entry:
4510 // CHECK-TLS3-NEXT:    [[ARRAYINIT_ENDOFINIT:%.*]] = alloca ptr, align 8
4511 // CHECK-TLS3-NEXT:    [[ARRAYINIT_ENDOFINIT1:%.*]] = alloca ptr, align 8
4512 // CHECK-TLS3-NEXT:    [[EXN_SLOT:%.*]] = alloca ptr, align 8
4513 // CHECK-TLS3-NEXT:    [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4
4514 // CHECK-TLS3-NEXT:    [[ARRAYINIT_ENDOFINIT5:%.*]] = alloca ptr, align 8
4515 // CHECK-TLS3-NEXT:    store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG186:![0-9]+]]
4516 // CHECK-TLS3-NEXT:    store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG188:![0-9]+]]
4517 // CHECK-TLS3-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @arr_x, i32 noundef 1)
4518 // CHECK-TLS3-NEXT:    to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG189:![0-9]+]]
4519 // CHECK-TLS3:       invoke.cont:
4520 // CHECK-TLS3-NEXT:    store ptr getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG188]]
4521 // CHECK-TLS3-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 1), i32 noundef 2)
4522 // CHECK-TLS3-NEXT:    to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD]], !dbg [[DBG190:![0-9]+]]
4523 // CHECK-TLS3:       invoke.cont2:
4524 // CHECK-TLS3-NEXT:    store ptr getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG188]]
4525 // CHECK-TLS3-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), i32 noundef 3)
4526 // CHECK-TLS3-NEXT:    to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]], !dbg [[DBG191:![0-9]+]]
4527 // CHECK-TLS3:       invoke.cont3:
4528 // CHECK-TLS3-NEXT:    store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG186]]
4529 // CHECK-TLS3-NEXT:    store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG192:![0-9]+]]
4530 // CHECK-TLS3-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i32 noundef 4)
4531 // CHECK-TLS3-NEXT:    to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD6:%.*]], !dbg [[DBG193:![0-9]+]]
4532 // CHECK-TLS3:       invoke.cont7:
4533 // CHECK-TLS3-NEXT:    store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG192]]
4534 // CHECK-TLS3-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), i32 noundef 5)
4535 // CHECK-TLS3-NEXT:    to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD6]], !dbg [[DBG194:![0-9]+]]
4536 // CHECK-TLS3:       invoke.cont8:
4537 // CHECK-TLS3-NEXT:    store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG192]]
4538 // CHECK-TLS3-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), i32 noundef 6)
4539 // CHECK-TLS3-NEXT:    to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD6]], !dbg [[DBG195:![0-9]+]]
4540 // CHECK-TLS3:       invoke.cont9:
4541 // CHECK-TLS3-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_thread_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG196:![0-9]+]]
4542 // CHECK-TLS3-NEXT:    ret void, !dbg [[DBG196]]
4543 // CHECK-TLS3:       lpad:
4544 // CHECK-TLS3-NEXT:    [[TMP1:%.*]] = landingpad { ptr, i32 }
4545 // CHECK-TLS3-NEXT:    cleanup, !dbg [[DBG197:![0-9]+]]
4546 // CHECK-TLS3-NEXT:    [[TMP2:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 0, !dbg [[DBG197]]
4547 // CHECK-TLS3-NEXT:    store ptr [[TMP2]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG197]]
4548 // CHECK-TLS3-NEXT:    [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 1, !dbg [[DBG197]]
4549 // CHECK-TLS3-NEXT:    store i32 [[TMP3]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG197]]
4550 // CHECK-TLS3-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG188]]
4551 // CHECK-TLS3-NEXT:    [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr @arr_x, [[TMP4]], !dbg [[DBG188]]
4552 // CHECK-TLS3-NEXT:    br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG188]]
4553 // CHECK-TLS3:       arraydestroy.body:
4554 // CHECK-TLS3-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP4]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG188]]
4555 // CHECK-TLS3-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG188]]
4556 // CHECK-TLS3-NEXT:    call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG188]]
4557 // CHECK-TLS3-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[DBG188]]
4558 // CHECK-TLS3-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG188]]
4559 // CHECK-TLS3:       arraydestroy.done4:
4560 // CHECK-TLS3-NEXT:    br label [[EHCLEANUP:%.*]], !dbg [[DBG188]]
4561 // CHECK-TLS3:       lpad6:
4562 // CHECK-TLS3-NEXT:    [[TMP5:%.*]] = landingpad { ptr, i32 }
4563 // CHECK-TLS3-NEXT:    cleanup, !dbg [[DBG197]]
4564 // CHECK-TLS3-NEXT:    [[TMP6:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 0, !dbg [[DBG197]]
4565 // CHECK-TLS3-NEXT:    store ptr [[TMP6]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG197]]
4566 // CHECK-TLS3-NEXT:    [[TMP7:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 1, !dbg [[DBG197]]
4567 // CHECK-TLS3-NEXT:    store i32 [[TMP7]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG197]]
4568 // CHECK-TLS3-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG192]]
4569 // CHECK-TLS3-NEXT:    [[ARRAYDESTROY_ISEMPTY10:%.*]] = icmp eq ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), [[TMP8]], !dbg [[DBG192]]
4570 // CHECK-TLS3-NEXT:    br i1 [[ARRAYDESTROY_ISEMPTY10]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY11:%.*]], !dbg [[DBG192]]
4571 // CHECK-TLS3:       arraydestroy.body11:
4572 // CHECK-TLS3-NEXT:    [[ARRAYDESTROY_ELEMENTPAST12:%.*]] = phi ptr [ [[TMP8]], [[LPAD6]] ], [ [[ARRAYDESTROY_ELEMENT13:%.*]], [[ARRAYDESTROY_BODY11]] ], !dbg [[DBG192]]
4573 // CHECK-TLS3-NEXT:    [[ARRAYDESTROY_ELEMENT13]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST12]], i64 -1, !dbg [[DBG192]]
4574 // CHECK-TLS3-NEXT:    call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR3]], !dbg [[DBG192]]
4575 // CHECK-TLS3-NEXT:    [[ARRAYDESTROY_DONE14:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), !dbg [[DBG192]]
4576 // CHECK-TLS3-NEXT:    br i1 [[ARRAYDESTROY_DONE14]], label [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_BODY11]], !dbg [[DBG192]]
4577 // CHECK-TLS3:       arraydestroy.done15:
4578 // CHECK-TLS3-NEXT:    br label [[EHCLEANUP]], !dbg [[DBG192]]
4579 // CHECK-TLS3:       ehcleanup:
4580 // CHECK-TLS3-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG186]]
4581 // CHECK-TLS3-NEXT:    [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP9]], i64 0, i64 0, !dbg [[DBG186]]
4582 // CHECK-TLS3-NEXT:    [[ARRAYDESTROY_ISEMPTY16:%.*]] = icmp eq ptr @arr_x, [[PAD_ARRAYEND]], !dbg [[DBG186]]
4583 // CHECK-TLS3-NEXT:    br i1 [[ARRAYDESTROY_ISEMPTY16]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17:%.*]], !dbg [[DBG186]]
4584 // CHECK-TLS3:       arraydestroy.body17:
4585 // CHECK-TLS3-NEXT:    [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi ptr [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ], !dbg [[DBG186]]
4586 // CHECK-TLS3-NEXT:    [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1, !dbg [[DBG186]]
4587 // CHECK-TLS3-NEXT:    call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]], !dbg [[DBG186]]
4588 // CHECK-TLS3-NEXT:    [[ARRAYDESTROY_DONE20:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT19]], @arr_x, !dbg [[DBG186]]
4589 // CHECK-TLS3-NEXT:    br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]], !dbg [[DBG186]]
4590 // CHECK-TLS3:       arraydestroy.done21:
4591 // CHECK-TLS3-NEXT:    br label [[EH_RESUME:%.*]], !dbg [[DBG186]]
4592 // CHECK-TLS3:       eh.resume:
4593 // CHECK-TLS3-NEXT:    [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG186]]
4594 // CHECK-TLS3-NEXT:    [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG186]]
4595 // CHECK-TLS3-NEXT:    [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG186]]
4596 // CHECK-TLS3-NEXT:    [[LPAD_VAL22:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG186]]
4597 // CHECK-TLS3-NEXT:    resume { ptr, i32 } [[LPAD_VAL22]], !dbg [[DBG186]]
4598 //
4599 //
4600 // CHECK-TLS3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
4601 // CHECK-TLS3-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG198:![0-9]+]] {
4602 // CHECK-TLS3-NEXT:  entry:
4603 // CHECK-TLS3-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
4604 // CHECK-TLS3-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
4605 // CHECK-TLS3-NEXT:    call void @llvm.dbg.declare(metadata ptr [[DOTADDR]], metadata [[META202:![0-9]+]], metadata !DIExpression()), !dbg [[DBG203:![0-9]+]]
4606 // CHECK-TLS3-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG203]]
4607 // CHECK-TLS3:       arraydestroy.body:
4608 // CHECK-TLS3-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 6), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG203]]
4609 // CHECK-TLS3-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG203]]
4610 // CHECK-TLS3-NEXT:    call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG203]]
4611 // CHECK-TLS3-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[DBG203]]
4612 // CHECK-TLS3-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG203]]
4613 // CHECK-TLS3:       arraydestroy.done1:
4614 // CHECK-TLS3-NEXT:    ret void, !dbg [[DBG203]]
4615 //
4616 //
4617 // CHECK-TLS3-LABEL: define {{[^@]+}}@main
4618 // CHECK-TLS3-SAME: () #[[ATTR5:[0-9]+]] !dbg [[DBG52:![0-9]+]] {
4619 // CHECK-TLS3-NEXT:  entry:
4620 // CHECK-TLS3-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
4621 // CHECK-TLS3-NEXT:    [[RES:%.*]] = alloca i32, align 4
4622 // CHECK-TLS3-NEXT:    store i32 0, ptr [[RETVAL]], align 4
4623 // CHECK-TLS3-NEXT:    call void @llvm.dbg.declare(metadata ptr [[RES]], metadata [[META204:![0-9]+]], metadata !DIExpression()), !dbg [[DBG205:![0-9]+]]
4624 // CHECK-TLS3-NEXT:    [[TMP0:%.*]] = load i8, ptr @_ZGVZ4mainE2sm, align 1, !dbg [[DBG206:![0-9]+]]
4625 // CHECK-TLS3-NEXT:    [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG206]]
4626 // CHECK-TLS3-NEXT:    br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG206]], !prof [[PROF207:![0-9]+]]
4627 // CHECK-TLS3:       init.check:
4628 // CHECK-TLS3-NEXT:    [[TMP1:%.*]] = call ptr @_ZTWL3gs1(), !dbg [[DBG208:![0-9]+]]
4629 // CHECK-TLS3-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP1]], i32 0, i32 0, !dbg [[DBG209:![0-9]+]]
4630 // CHECK-TLS3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 4, !dbg [[DBG209]]
4631 // CHECK-TLS3-NEXT:    call void @_ZZ4mainEN5SmainC1Ei(ptr noundef nonnull align 8 dereferenceable(24) @_ZZ4mainE2sm, i32 noundef [[TMP2]]), !dbg [[DBG210:![0-9]+]]
4632 // CHECK-TLS3-NEXT:    [[TMP3:%.*]] = call i32 @__cxa_thread_atexit(ptr @_ZZ4mainEN5SmainD1Ev, ptr @_ZZ4mainE2sm, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG206]]
4633 // CHECK-TLS3-NEXT:    store i8 1, ptr @_ZGVZ4mainE2sm, align 1, !dbg [[DBG206]]
4634 // CHECK-TLS3-NEXT:    br label [[INIT_END]], !dbg [[DBG206]]
4635 // CHECK-TLS3:       init.end:
4636 // CHECK-TLS3-NEXT:    [[TMP4:%.*]] = call ptr @_ZTWN6Static1sE(), !dbg [[DBG211:![0-9]+]]
4637 // CHECK-TLS3-NEXT:    [[A1:%.*]] = getelementptr inbounds [[STRUCT_S3:%.*]], ptr [[TMP4]], i32 0, i32 0, !dbg [[DBG212:![0-9]+]]
4638 // CHECK-TLS3-NEXT:    [[TMP5:%.*]] = load i32, ptr [[A1]], align 4, !dbg [[DBG212]]
4639 // CHECK-TLS3-NEXT:    store i32 [[TMP5]], ptr [[RES]], align 4, !dbg [[DBG213:![0-9]+]]
4640 // CHECK-TLS3-NEXT:    [[TMP6:%.*]] = call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @_ZZ4mainE2sm), !dbg [[DBG214:![0-9]+]]
4641 // CHECK-TLS3-NEXT:    [[A2:%.*]] = getelementptr inbounds [[STRUCT_SMAIN:%.*]], ptr [[TMP6]], i32 0, i32 0, !dbg [[DBG215:![0-9]+]]
4642 // CHECK-TLS3-NEXT:    [[TMP7:%.*]] = load i32, ptr [[A2]], align 8, !dbg [[DBG215]]
4643 // CHECK-TLS3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG216:![0-9]+]]
4644 // CHECK-TLS3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP8]], [[TMP7]], !dbg [[DBG216]]
4645 // CHECK-TLS3-NEXT:    store i32 [[ADD]], ptr [[RES]], align 4, !dbg [[DBG216]]
4646 // CHECK-TLS3-NEXT:    [[TMP9:%.*]] = call ptr @_ZTWL3gs1(), !dbg [[DBG217:![0-9]+]]
4647 // CHECK-TLS3-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP9]], i32 0, i32 0, !dbg [[DBG218:![0-9]+]]
4648 // CHECK-TLS3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[A3]], align 4, !dbg [[DBG218]]
4649 // CHECK-TLS3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG219:![0-9]+]]
4650 // CHECK-TLS3-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP11]], [[TMP10]], !dbg [[DBG219]]
4651 // CHECK-TLS3-NEXT:    store i32 [[ADD4]], ptr [[RES]], align 4, !dbg [[DBG219]]
4652 // CHECK-TLS3-NEXT:    [[TMP12:%.*]] = load i32, ptr @_ZL3gs2, align 8, !dbg [[DBG220:![0-9]+]]
4653 // CHECK-TLS3-NEXT:    [[TMP13:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG221:![0-9]+]]
4654 // CHECK-TLS3-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP13]], [[TMP12]], !dbg [[DBG221]]
4655 // CHECK-TLS3-NEXT:    store i32 [[ADD5]], ptr [[RES]], align 4, !dbg [[DBG221]]
4656 // CHECK-TLS3-NEXT:    [[TMP14:%.*]] = call ptr @_ZTW3gs3(), !dbg [[DBG222:![0-9]+]]
4657 // CHECK-TLS3-NEXT:    [[A6:%.*]] = getelementptr inbounds [[STRUCT_S5:%.*]], ptr [[TMP14]], i32 0, i32 0, !dbg [[DBG223:![0-9]+]]
4658 // CHECK-TLS3-NEXT:    [[TMP15:%.*]] = load i32, ptr [[A6]], align 4, !dbg [[DBG223]]
4659 // CHECK-TLS3-NEXT:    [[TMP16:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG224:![0-9]+]]
4660 // CHECK-TLS3-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP16]], [[TMP15]], !dbg [[DBG224]]
4661 // CHECK-TLS3-NEXT:    store i32 [[ADD7]], ptr [[RES]], align 4, !dbg [[DBG224]]
4662 // CHECK-TLS3-NEXT:    [[TMP17:%.*]] = call ptr @_ZTW5arr_x(), !dbg [[DBG225:![0-9]+]]
4663 // CHECK-TLS3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP17]], i64 0, i64 1, !dbg [[DBG225]]
4664 // CHECK-TLS3-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG225]]
4665 // CHECK-TLS3-NEXT:    [[A9:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYIDX8]], i32 0, i32 0, !dbg [[DBG226:![0-9]+]]
4666 // CHECK-TLS3-NEXT:    [[TMP18:%.*]] = load i32, ptr [[A9]], align 4, !dbg [[DBG226]]
4667 // CHECK-TLS3-NEXT:    [[TMP19:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG227:![0-9]+]]
4668 // CHECK-TLS3-NEXT:    [[ADD10:%.*]] = add nsw i32 [[TMP19]], [[TMP18]], !dbg [[DBG227]]
4669 // CHECK-TLS3-NEXT:    store i32 [[ADD10]], ptr [[RES]], align 4, !dbg [[DBG227]]
4670 // CHECK-TLS3-NEXT:    [[TMP20:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZN2STIiE2stE), !dbg [[DBG228:![0-9]+]]
4671 // CHECK-TLS3-NEXT:    [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4, !dbg [[DBG228]]
4672 // CHECK-TLS3-NEXT:    [[TMP22:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG229:![0-9]+]]
4673 // CHECK-TLS3-NEXT:    [[ADD11:%.*]] = add nsw i32 [[TMP22]], [[TMP21]], !dbg [[DBG229]]
4674 // CHECK-TLS3-NEXT:    store i32 [[ADD11]], ptr [[RES]], align 4, !dbg [[DBG229]]
4675 // CHECK-TLS3-NEXT:    [[TMP23:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZN2STIfE2stE), !dbg [[DBG230:![0-9]+]]
4676 // CHECK-TLS3-NEXT:    [[TMP24:%.*]] = load float, ptr [[TMP23]], align 4, !dbg [[DBG230]]
4677 // CHECK-TLS3-NEXT:    [[CONV:%.*]] = fptosi float [[TMP24]] to i32, !dbg [[DBG230]]
4678 // CHECK-TLS3-NEXT:    [[TMP25:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG231:![0-9]+]]
4679 // CHECK-TLS3-NEXT:    [[ADD12:%.*]] = add nsw i32 [[TMP25]], [[CONV]], !dbg [[DBG231]]
4680 // CHECK-TLS3-NEXT:    store i32 [[ADD12]], ptr [[RES]], align 4, !dbg [[DBG231]]
4681 // CHECK-TLS3-NEXT:    [[TMP26:%.*]] = call ptr @_ZTWN2STI2S4E2stE(), !dbg [[DBG232:![0-9]+]]
4682 // CHECK-TLS3-NEXT:    [[A13:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[TMP26]], i32 0, i32 0, !dbg [[DBG233:![0-9]+]]
4683 // CHECK-TLS3-NEXT:    [[TMP27:%.*]] = load i32, ptr [[A13]], align 4, !dbg [[DBG233]]
4684 // CHECK-TLS3-NEXT:    [[TMP28:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG234:![0-9]+]]
4685 // CHECK-TLS3-NEXT:    [[ADD14:%.*]] = add nsw i32 [[TMP28]], [[TMP27]], !dbg [[DBG234]]
4686 // CHECK-TLS3-NEXT:    store i32 [[ADD14]], ptr [[RES]], align 4, !dbg [[DBG234]]
4687 // CHECK-TLS3-NEXT:    [[TMP29:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG235:![0-9]+]]
4688 // CHECK-TLS3-NEXT:    ret i32 [[TMP29]], !dbg [[DBG236:![0-9]+]]
4689 //
4690 //
4691 // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZTWL3gs1
4692 // CHECK-TLS3-SAME: () #[[ATTR6:[0-9]+]] {
4693 // CHECK-TLS3-NEXT:    call void @_ZTHL3gs1()
4694 // CHECK-TLS3-NEXT:    [[TMP1:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZL3gs1)
4695 // CHECK-TLS3-NEXT:    ret ptr [[TMP1]]
4696 //
4697 //
4698 // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC1Ei
4699 // CHECK-TLS3-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 !dbg [[DBG237:![0-9]+]] {
4700 // CHECK-TLS3-NEXT:  entry:
4701 // CHECK-TLS3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
4702 // CHECK-TLS3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
4703 // CHECK-TLS3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
4704 // CHECK-TLS3-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META238:![0-9]+]], metadata !DIExpression()), !dbg [[DBG240:![0-9]+]]
4705 // CHECK-TLS3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
4706 // CHECK-TLS3-NEXT:    call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META241:![0-9]+]], metadata !DIExpression()), !dbg [[DBG242:![0-9]+]]
4707 // CHECK-TLS3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
4708 // CHECK-TLS3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG243:![0-9]+]]
4709 // CHECK-TLS3-NEXT:    call void @_ZZ4mainEN5SmainC2Ei(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG243]]
4710 // CHECK-TLS3-NEXT:    ret void, !dbg [[DBG244:![0-9]+]]
4711 //
4712 //
4713 // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD1Ev
4714 // CHECK-TLS3-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG245:![0-9]+]] {
4715 // CHECK-TLS3-NEXT:  entry:
4716 // CHECK-TLS3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
4717 // CHECK-TLS3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
4718 // CHECK-TLS3-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META246:![0-9]+]], metadata !DIExpression()), !dbg [[DBG247:![0-9]+]]
4719 // CHECK-TLS3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
4720 // CHECK-TLS3-NEXT:    call void @_ZZ4mainEN5SmainD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR3]], !dbg [[DBG248:![0-9]+]]
4721 // CHECK-TLS3-NEXT:    ret void, !dbg [[DBG249:![0-9]+]]
4722 //
4723 //
4724 // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZTWN6Static1sE
4725 // CHECK-TLS3-SAME: () #[[ATTR6]] comdat {
4726 // CHECK-TLS3-NEXT:    br i1 icmp ne (ptr @_ZTHN6Static1sE, ptr null), label [[TMP1:%.*]], label [[TMP2:%.*]]
4727 // CHECK-TLS3:       1:
4728 // CHECK-TLS3-NEXT:    call void @_ZTHN6Static1sE()
4729 // CHECK-TLS3-NEXT:    br label [[TMP2]]
4730 // CHECK-TLS3:       2:
4731 // CHECK-TLS3-NEXT:    [[TMP3:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZN6Static1sE)
4732 // CHECK-TLS3-NEXT:    ret ptr [[TMP3]]
4733 //
4734 //
4735 // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZTW3gs3
4736 // CHECK-TLS3-SAME: () #[[ATTR6]] comdat {
4737 // CHECK-TLS3-NEXT:    br i1 icmp ne (ptr @_ZTH3gs3, ptr null), label [[TMP1:%.*]], label [[TMP2:%.*]]
4738 // CHECK-TLS3:       1:
4739 // CHECK-TLS3-NEXT:    call void @_ZTH3gs3()
4740 // CHECK-TLS3-NEXT:    br label [[TMP2]]
4741 // CHECK-TLS3:       2:
4742 // CHECK-TLS3-NEXT:    [[TMP3:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @gs3)
4743 // CHECK-TLS3-NEXT:    ret ptr [[TMP3]]
4744 //
4745 //
4746 // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZTW5arr_x
4747 // CHECK-TLS3-SAME: () #[[ATTR6]] comdat {
4748 // CHECK-TLS3-NEXT:    call void @_ZTH5arr_x()
4749 // CHECK-TLS3-NEXT:    [[TMP1:%.*]] = call align 16 ptr @llvm.threadlocal.address.p0(ptr align 16 @arr_x)
4750 // CHECK-TLS3-NEXT:    ret ptr [[TMP1]]
4751 //
4752 //
4753 // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZTWN2STI2S4E2stE
4754 // CHECK-TLS3-SAME: () #[[ATTR6]] comdat {
4755 // CHECK-TLS3-NEXT:    call void @_ZTHN2STI2S4E2stE()
4756 // CHECK-TLS3-NEXT:    [[TMP1:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZN2STI2S4E2stE)
4757 // CHECK-TLS3-NEXT:    ret ptr [[TMP1]]
4758 //
4759 //
4760 // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC2Ei
4761 // CHECK-TLS3-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG250:![0-9]+]] {
4762 // CHECK-TLS3-NEXT:  entry:
4763 // CHECK-TLS3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
4764 // CHECK-TLS3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
4765 // CHECK-TLS3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
4766 // CHECK-TLS3-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META251:![0-9]+]], metadata !DIExpression()), !dbg [[DBG252:![0-9]+]]
4767 // CHECK-TLS3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
4768 // CHECK-TLS3-NEXT:    call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META253:![0-9]+]], metadata !DIExpression()), !dbg [[DBG254:![0-9]+]]
4769 // CHECK-TLS3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
4770 // CHECK-TLS3-NEXT:    [[A2:%.*]] = getelementptr inbounds [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG255:![0-9]+]]
4771 // CHECK-TLS3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG256:![0-9]+]]
4772 // CHECK-TLS3-NEXT:    store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG255]]
4773 // CHECK-TLS3-NEXT:    ret void, !dbg [[DBG257:![0-9]+]]
4774 //
4775 //
4776 // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD2Ev
4777 // CHECK-TLS3-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG258:![0-9]+]] {
4778 // CHECK-TLS3-NEXT:  entry:
4779 // CHECK-TLS3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
4780 // CHECK-TLS3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
4781 // CHECK-TLS3-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META259:![0-9]+]], metadata !DIExpression()), !dbg [[DBG260:![0-9]+]]
4782 // CHECK-TLS3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
4783 // CHECK-TLS3-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG261:![0-9]+]]
4784 // CHECK-TLS3-NEXT:    store i32 0, ptr [[A]], align 8, !dbg [[DBG263:![0-9]+]]
4785 // CHECK-TLS3-NEXT:    ret void, !dbg [[DBG264:![0-9]+]]
4786 //
4787 //
4788 // CHECK-TLS3-LABEL: define {{[^@]+}}@_Z6foobarv
4789 // CHECK-TLS3-SAME: () #[[ATTR7:[0-9]+]] !dbg [[DBG265:![0-9]+]] {
4790 // CHECK-TLS3-NEXT:  entry:
4791 // CHECK-TLS3-NEXT:    [[RES:%.*]] = alloca i32, align 4
4792 // CHECK-TLS3-NEXT:    call void @llvm.dbg.declare(metadata ptr [[RES]], metadata [[META266:![0-9]+]], metadata !DIExpression()), !dbg [[DBG267:![0-9]+]]
4793 // CHECK-TLS3-NEXT:    [[TMP0:%.*]] = call ptr @_ZTWN6Static1sE(), !dbg [[DBG268:![0-9]+]]
4794 // CHECK-TLS3-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S3:%.*]], ptr [[TMP0]], i32 0, i32 0, !dbg [[DBG269:![0-9]+]]
4795 // CHECK-TLS3-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A]], align 4, !dbg [[DBG269]]
4796 // CHECK-TLS3-NEXT:    store i32 [[TMP1]], ptr [[RES]], align 4, !dbg [[DBG270:![0-9]+]]
4797 // CHECK-TLS3-NEXT:    [[TMP2:%.*]] = call ptr @_ZTWL3gs1(), !dbg [[DBG271:![0-9]+]]
4798 // CHECK-TLS3-NEXT:    [[A1:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP2]], i32 0, i32 0, !dbg [[DBG272:![0-9]+]]
4799 // CHECK-TLS3-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A1]], align 4, !dbg [[DBG272]]
4800 // CHECK-TLS3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG273:![0-9]+]]
4801 // CHECK-TLS3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP4]], [[TMP3]], !dbg [[DBG273]]
4802 // CHECK-TLS3-NEXT:    store i32 [[ADD]], ptr [[RES]], align 4, !dbg [[DBG273]]
4803 // CHECK-TLS3-NEXT:    [[TMP5:%.*]] = load i32, ptr @_ZL3gs2, align 8, !dbg [[DBG274:![0-9]+]]
4804 // CHECK-TLS3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG275:![0-9]+]]
4805 // CHECK-TLS3-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP6]], [[TMP5]], !dbg [[DBG275]]
4806 // CHECK-TLS3-NEXT:    store i32 [[ADD2]], ptr [[RES]], align 4, !dbg [[DBG275]]
4807 // CHECK-TLS3-NEXT:    [[TMP7:%.*]] = call ptr @_ZTW3gs3(), !dbg [[DBG276:![0-9]+]]
4808 // CHECK-TLS3-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S5:%.*]], ptr [[TMP7]], i32 0, i32 0, !dbg [[DBG277:![0-9]+]]
4809 // CHECK-TLS3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A3]], align 4, !dbg [[DBG277]]
4810 // CHECK-TLS3-NEXT:    [[TMP9:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG278:![0-9]+]]
4811 // CHECK-TLS3-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP9]], [[TMP8]], !dbg [[DBG278]]
4812 // CHECK-TLS3-NEXT:    store i32 [[ADD4]], ptr [[RES]], align 4, !dbg [[DBG278]]
4813 // CHECK-TLS3-NEXT:    [[TMP10:%.*]] = call ptr @_ZTW5arr_x(), !dbg [[DBG279:![0-9]+]]
4814 // CHECK-TLS3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP10]], i64 0, i64 1, !dbg [[DBG279]]
4815 // CHECK-TLS3-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG279]]
4816 // CHECK-TLS3-NEXT:    [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYIDX5]], i32 0, i32 0, !dbg [[DBG280:![0-9]+]]
4817 // CHECK-TLS3-NEXT:    [[TMP11:%.*]] = load i32, ptr [[A6]], align 4, !dbg [[DBG280]]
4818 // CHECK-TLS3-NEXT:    [[TMP12:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG281:![0-9]+]]
4819 // CHECK-TLS3-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP12]], [[TMP11]], !dbg [[DBG281]]
4820 // CHECK-TLS3-NEXT:    store i32 [[ADD7]], ptr [[RES]], align 4, !dbg [[DBG281]]
4821 // CHECK-TLS3-NEXT:    [[TMP13:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZN2STIiE2stE), !dbg [[DBG282:![0-9]+]]
4822 // CHECK-TLS3-NEXT:    [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4, !dbg [[DBG282]]
4823 // CHECK-TLS3-NEXT:    [[TMP15:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG283:![0-9]+]]
4824 // CHECK-TLS3-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP15]], [[TMP14]], !dbg [[DBG283]]
4825 // CHECK-TLS3-NEXT:    store i32 [[ADD8]], ptr [[RES]], align 4, !dbg [[DBG283]]
4826 // CHECK-TLS3-NEXT:    [[TMP16:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZN2STIfE2stE), !dbg [[DBG284:![0-9]+]]
4827 // CHECK-TLS3-NEXT:    [[TMP17:%.*]] = load float, ptr [[TMP16]], align 4, !dbg [[DBG284]]
4828 // CHECK-TLS3-NEXT:    [[CONV:%.*]] = fptosi float [[TMP17]] to i32, !dbg [[DBG284]]
4829 // CHECK-TLS3-NEXT:    [[TMP18:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG285:![0-9]+]]
4830 // CHECK-TLS3-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP18]], [[CONV]], !dbg [[DBG285]]
4831 // CHECK-TLS3-NEXT:    store i32 [[ADD9]], ptr [[RES]], align 4, !dbg [[DBG285]]
4832 // CHECK-TLS3-NEXT:    [[TMP19:%.*]] = call ptr @_ZTWN2STI2S4E2stE(), !dbg [[DBG286:![0-9]+]]
4833 // CHECK-TLS3-NEXT:    [[A10:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[TMP19]], i32 0, i32 0, !dbg [[DBG287:![0-9]+]]
4834 // CHECK-TLS3-NEXT:    [[TMP20:%.*]] = load i32, ptr [[A10]], align 4, !dbg [[DBG287]]
4835 // CHECK-TLS3-NEXT:    [[TMP21:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG288:![0-9]+]]
4836 // CHECK-TLS3-NEXT:    [[ADD11:%.*]] = add nsw i32 [[TMP21]], [[TMP20]], !dbg [[DBG288]]
4837 // CHECK-TLS3-NEXT:    store i32 [[ADD11]], ptr [[RES]], align 4, !dbg [[DBG288]]
4838 // CHECK-TLS3-NEXT:    [[TMP22:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG289:![0-9]+]]
4839 // CHECK-TLS3-NEXT:    ret i32 [[TMP22]], !dbg [[DBG290:![0-9]+]]
4840 //
4841 //
4842 // CHECK-TLS3-LABEL: define {{[^@]+}}@__cxx_global_var_init.3
4843 // CHECK-TLS3-SAME: () #[[ATTR0]] !dbg [[DBG291:![0-9]+]] {
4844 // CHECK-TLS3-NEXT:  entry:
4845 // CHECK-TLS3-NEXT:    [[TMP0:%.*]] = load i8, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG292:![0-9]+]]
4846 // CHECK-TLS3-NEXT:    [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG292]]
4847 // CHECK-TLS3-NEXT:    br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG292]]
4848 // CHECK-TLS3:       init.check:
4849 // CHECK-TLS3-NEXT:    store i8 1, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG292]]
4850 // CHECK-TLS3-NEXT:    call void @_ZN2S4C1Ei(ptr noundef nonnull align 4 dereferenceable(8) @_ZN2STI2S4E2stE, i32 noundef 23), !dbg [[DBG293:![0-9]+]]
4851 // CHECK-TLS3-NEXT:    [[TMP1:%.*]] = call i32 @__cxa_thread_atexit(ptr @_ZN2S4D1Ev, ptr @_ZN2STI2S4E2stE, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG292]]
4852 // CHECK-TLS3-NEXT:    br label [[INIT_END]], !dbg [[DBG292]]
4853 // CHECK-TLS3:       init.end:
4854 // CHECK-TLS3-NEXT:    ret void, !dbg [[DBG295:![0-9]+]]
4855 //
4856 //
4857 // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZN2S4C1Ei
4858 // CHECK-TLS3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 !dbg [[DBG296:![0-9]+]] {
4859 // CHECK-TLS3-NEXT:  entry:
4860 // CHECK-TLS3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
4861 // CHECK-TLS3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
4862 // CHECK-TLS3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
4863 // CHECK-TLS3-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META297:![0-9]+]], metadata !DIExpression()), !dbg [[DBG299:![0-9]+]]
4864 // CHECK-TLS3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
4865 // CHECK-TLS3-NEXT:    call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META300:![0-9]+]], metadata !DIExpression()), !dbg [[DBG301:![0-9]+]]
4866 // CHECK-TLS3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
4867 // CHECK-TLS3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG302:![0-9]+]]
4868 // CHECK-TLS3-NEXT:    call void @_ZN2S4C2Ei(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG302]]
4869 // CHECK-TLS3-NEXT:    ret void, !dbg [[DBG303:![0-9]+]]
4870 //
4871 //
4872 // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZN2S4D1Ev
4873 // CHECK-TLS3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG304:![0-9]+]] {
4874 // CHECK-TLS3-NEXT:  entry:
4875 // CHECK-TLS3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
4876 // CHECK-TLS3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
4877 // CHECK-TLS3-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META305:![0-9]+]], metadata !DIExpression()), !dbg [[DBG306:![0-9]+]]
4878 // CHECK-TLS3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
4879 // CHECK-TLS3-NEXT:    call void @_ZN2S4D2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR3]], !dbg [[DBG307:![0-9]+]]
4880 // CHECK-TLS3-NEXT:    ret void, !dbg [[DBG308:![0-9]+]]
4881 //
4882 //
4883 // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZN2S4C2Ei
4884 // CHECK-TLS3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG309:![0-9]+]] {
4885 // CHECK-TLS3-NEXT:  entry:
4886 // CHECK-TLS3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
4887 // CHECK-TLS3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
4888 // CHECK-TLS3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
4889 // CHECK-TLS3-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META310:![0-9]+]], metadata !DIExpression()), !dbg [[DBG311:![0-9]+]]
4890 // CHECK-TLS3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
4891 // CHECK-TLS3-NEXT:    call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META312:![0-9]+]], metadata !DIExpression()), !dbg [[DBG313:![0-9]+]]
4892 // CHECK-TLS3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
4893 // CHECK-TLS3-NEXT:    [[A2:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG314:![0-9]+]]
4894 // CHECK-TLS3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG315:![0-9]+]]
4895 // CHECK-TLS3-NEXT:    store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG314]]
4896 // CHECK-TLS3-NEXT:    ret void, !dbg [[DBG316:![0-9]+]]
4897 //
4898 //
4899 // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZN2S4D2Ev
4900 // CHECK-TLS3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG317:![0-9]+]] {
4901 // CHECK-TLS3-NEXT:  entry:
4902 // CHECK-TLS3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
4903 // CHECK-TLS3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
4904 // CHECK-TLS3-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META318:![0-9]+]], metadata !DIExpression()), !dbg [[DBG319:![0-9]+]]
4905 // CHECK-TLS3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
4906 // CHECK-TLS3-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG320:![0-9]+]]
4907 // CHECK-TLS3-NEXT:    store i32 0, ptr [[A]], align 4, !dbg [[DBG322:![0-9]+]]
4908 // CHECK-TLS3-NEXT:    ret void, !dbg [[DBG323:![0-9]+]]
4909 //
4910 //
4911 // CHECK-TLS3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_threadprivate_codegen.cpp
4912 // CHECK-TLS3-SAME: () #[[ATTR0]] !dbg [[DBG324:![0-9]+]] {
4913 // CHECK-TLS3-NEXT:  entry:
4914 // CHECK-TLS3-NEXT:    call void @__cxx_global_var_init.1(), !dbg [[DBG326:![0-9]+]]
4915 // CHECK-TLS3-NEXT:    ret void
4916 //
4917 //
4918 // CHECK-TLS3-LABEL: define {{[^@]+}}@__tls_init
4919 // CHECK-TLS3-SAME: () #[[ATTR0]] !dbg [[DBG327:![0-9]+]] {
4920 // CHECK-TLS3-NEXT:  entry:
4921 // CHECK-TLS3-NEXT:    [[TMP0:%.*]] = load i8, ptr @__tls_guard, align 1, !dbg [[DBG328:![0-9]+]]
4922 // CHECK-TLS3-NEXT:    [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG328]]
4923 // CHECK-TLS3-NEXT:    br i1 [[GUARD_UNINITIALIZED]], label [[INIT:%.*]], label [[EXIT:%.*]], !dbg [[DBG328]], !prof [[PROF207]]
4924 // CHECK-TLS3:       init:
4925 // CHECK-TLS3-NEXT:    store i8 1, ptr @__tls_guard, align 1, !dbg [[DBG328]]
4926 // CHECK-TLS3-NEXT:    call void @__cxx_global_var_init(), !dbg [[DBG328]]
4927 // CHECK-TLS3-NEXT:    call void @__cxx_global_var_init.2(), !dbg [[DBG328]]
4928 // CHECK-TLS3-NEXT:    br label [[EXIT]], !dbg [[DBG328]]
4929 // CHECK-TLS3:       exit:
4930 // CHECK-TLS3-NEXT:    ret void
4931 //
4932 //
4933 // CHECK-TLS4-LABEL: define {{[^@]+}}@main
4934 // CHECK-TLS4-SAME: () #[[ATTR0:[0-9]+]] !dbg [[DBG9:![0-9]+]] {
4935 // CHECK-TLS4-NEXT:  entry:
4936 // CHECK-TLS4-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
4937 // CHECK-TLS4-NEXT:    [[RES:%.*]] = alloca i32, align 4
4938 // CHECK-TLS4-NEXT:    store i32 0, ptr [[RETVAL]], align 4
4939 // CHECK-TLS4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[RES]], metadata [[META116:![0-9]+]], metadata !DIExpression()), !dbg [[DBG117:![0-9]+]]
4940 // CHECK-TLS4-NEXT:    [[TMP0:%.*]] = load i8, ptr @_ZGVZ4mainE2sm, align 1, !dbg [[DBG118:![0-9]+]]
4941 // CHECK-TLS4-NEXT:    [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG118]]
4942 // CHECK-TLS4-NEXT:    br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG118]], !prof [[PROF119:![0-9]+]]
4943 // CHECK-TLS4:       init.check:
4944 // CHECK-TLS4-NEXT:    [[TMP1:%.*]] = call ptr @_ZTWL3gs1(), !dbg [[DBG120:![0-9]+]]
4945 // CHECK-TLS4-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP1]], i32 0, i32 0, !dbg [[DBG121:![0-9]+]]
4946 // CHECK-TLS4-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 4, !dbg [[DBG121]]
4947 // CHECK-TLS4-NEXT:    call void @_ZZ4mainEN5SmainC1Ei(ptr noundef nonnull align 8 dereferenceable(24) @_ZZ4mainE2sm, i32 noundef [[TMP2]]), !dbg [[DBG122:![0-9]+]]
4948 // CHECK-TLS4-NEXT:    [[TMP3:%.*]] = call i32 @__cxa_thread_atexit(ptr @_ZZ4mainEN5SmainD1Ev, ptr @_ZZ4mainE2sm, ptr @__dso_handle) #[[ATTR5:[0-9]+]], !dbg [[DBG118]]
4949 // CHECK-TLS4-NEXT:    store i8 1, ptr @_ZGVZ4mainE2sm, align 1, !dbg [[DBG118]]
4950 // CHECK-TLS4-NEXT:    br label [[INIT_END]], !dbg [[DBG118]]
4951 // CHECK-TLS4:       init.end:
4952 // CHECK-TLS4-NEXT:    [[TMP4:%.*]] = call ptr @_ZTWN6Static1sE(), !dbg [[DBG123:![0-9]+]]
4953 // CHECK-TLS4-NEXT:    [[A1:%.*]] = getelementptr inbounds [[STRUCT_S3:%.*]], ptr [[TMP4]], i32 0, i32 0, !dbg [[DBG124:![0-9]+]]
4954 // CHECK-TLS4-NEXT:    [[TMP5:%.*]] = load i32, ptr [[A1]], align 4, !dbg [[DBG124]]
4955 // CHECK-TLS4-NEXT:    store i32 [[TMP5]], ptr [[RES]], align 4, !dbg [[DBG125:![0-9]+]]
4956 // CHECK-TLS4-NEXT:    [[TMP6:%.*]] = call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @_ZZ4mainE2sm), !dbg [[DBG126:![0-9]+]]
4957 // CHECK-TLS4-NEXT:    [[A2:%.*]] = getelementptr inbounds [[STRUCT_SMAIN:%.*]], ptr [[TMP6]], i32 0, i32 0, !dbg [[DBG127:![0-9]+]]
4958 // CHECK-TLS4-NEXT:    [[TMP7:%.*]] = load i32, ptr [[A2]], align 8, !dbg [[DBG127]]
4959 // CHECK-TLS4-NEXT:    [[TMP8:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG128:![0-9]+]]
4960 // CHECK-TLS4-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP8]], [[TMP7]], !dbg [[DBG128]]
4961 // CHECK-TLS4-NEXT:    store i32 [[ADD]], ptr [[RES]], align 4, !dbg [[DBG128]]
4962 // CHECK-TLS4-NEXT:    [[TMP9:%.*]] = call ptr @_ZTWL3gs1(), !dbg [[DBG129:![0-9]+]]
4963 // CHECK-TLS4-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP9]], i32 0, i32 0, !dbg [[DBG130:![0-9]+]]
4964 // CHECK-TLS4-NEXT:    [[TMP10:%.*]] = load i32, ptr [[A3]], align 4, !dbg [[DBG130]]
4965 // CHECK-TLS4-NEXT:    [[TMP11:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG131:![0-9]+]]
4966 // CHECK-TLS4-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP11]], [[TMP10]], !dbg [[DBG131]]
4967 // CHECK-TLS4-NEXT:    store i32 [[ADD4]], ptr [[RES]], align 4, !dbg [[DBG131]]
4968 // CHECK-TLS4-NEXT:    [[TMP12:%.*]] = load i32, ptr @_ZL3gs2, align 8, !dbg [[DBG132:![0-9]+]]
4969 // CHECK-TLS4-NEXT:    [[TMP13:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG133:![0-9]+]]
4970 // CHECK-TLS4-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP13]], [[TMP12]], !dbg [[DBG133]]
4971 // CHECK-TLS4-NEXT:    store i32 [[ADD5]], ptr [[RES]], align 4, !dbg [[DBG133]]
4972 // CHECK-TLS4-NEXT:    [[TMP14:%.*]] = call ptr @_ZTW3gs3(), !dbg [[DBG134:![0-9]+]]
4973 // CHECK-TLS4-NEXT:    [[A6:%.*]] = getelementptr inbounds [[STRUCT_S5:%.*]], ptr [[TMP14]], i32 0, i32 0, !dbg [[DBG135:![0-9]+]]
4974 // CHECK-TLS4-NEXT:    [[TMP15:%.*]] = load i32, ptr [[A6]], align 4, !dbg [[DBG135]]
4975 // CHECK-TLS4-NEXT:    [[TMP16:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG136:![0-9]+]]
4976 // CHECK-TLS4-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP16]], [[TMP15]], !dbg [[DBG136]]
4977 // CHECK-TLS4-NEXT:    store i32 [[ADD7]], ptr [[RES]], align 4, !dbg [[DBG136]]
4978 // CHECK-TLS4-NEXT:    [[TMP17:%.*]] = call ptr @_ZTW5arr_x(), !dbg [[DBG137:![0-9]+]]
4979 // CHECK-TLS4-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP17]], i64 0, i64 1, !dbg [[DBG137]]
4980 // CHECK-TLS4-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG137]]
4981 // CHECK-TLS4-NEXT:    [[A9:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYIDX8]], i32 0, i32 0, !dbg [[DBG138:![0-9]+]]
4982 // CHECK-TLS4-NEXT:    [[TMP18:%.*]] = load i32, ptr [[A9]], align 4, !dbg [[DBG138]]
4983 // CHECK-TLS4-NEXT:    [[TMP19:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG139:![0-9]+]]
4984 // CHECK-TLS4-NEXT:    [[ADD10:%.*]] = add nsw i32 [[TMP19]], [[TMP18]], !dbg [[DBG139]]
4985 // CHECK-TLS4-NEXT:    store i32 [[ADD10]], ptr [[RES]], align 4, !dbg [[DBG139]]
4986 // CHECK-TLS4-NEXT:    [[TMP20:%.*]] = call ptr @_ZTWN2STIiE2stE(), !dbg [[DBG140:![0-9]+]]
4987 // CHECK-TLS4-NEXT:    [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4, !dbg [[DBG140]]
4988 // CHECK-TLS4-NEXT:    [[TMP22:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG141:![0-9]+]]
4989 // CHECK-TLS4-NEXT:    [[ADD11:%.*]] = add nsw i32 [[TMP22]], [[TMP21]], !dbg [[DBG141]]
4990 // CHECK-TLS4-NEXT:    store i32 [[ADD11]], ptr [[RES]], align 4, !dbg [[DBG141]]
4991 // CHECK-TLS4-NEXT:    [[TMP23:%.*]] = call ptr @_ZTWN2STIfE2stE(), !dbg [[DBG142:![0-9]+]]
4992 // CHECK-TLS4-NEXT:    [[TMP24:%.*]] = load float, ptr [[TMP23]], align 4, !dbg [[DBG142]]
4993 // CHECK-TLS4-NEXT:    [[CONV:%.*]] = fptosi float [[TMP24]] to i32, !dbg [[DBG142]]
4994 // CHECK-TLS4-NEXT:    [[TMP25:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG143:![0-9]+]]
4995 // CHECK-TLS4-NEXT:    [[ADD12:%.*]] = add nsw i32 [[TMP25]], [[CONV]], !dbg [[DBG143]]
4996 // CHECK-TLS4-NEXT:    store i32 [[ADD12]], ptr [[RES]], align 4, !dbg [[DBG143]]
4997 // CHECK-TLS4-NEXT:    [[TMP26:%.*]] = call ptr @_ZTWN2STI2S4E2stE(), !dbg [[DBG144:![0-9]+]]
4998 // CHECK-TLS4-NEXT:    [[A13:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[TMP26]], i32 0, i32 0, !dbg [[DBG145:![0-9]+]]
4999 // CHECK-TLS4-NEXT:    [[TMP27:%.*]] = load i32, ptr [[A13]], align 4, !dbg [[DBG145]]
5000 // CHECK-TLS4-NEXT:    [[TMP28:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG146:![0-9]+]]
5001 // CHECK-TLS4-NEXT:    [[ADD14:%.*]] = add nsw i32 [[TMP28]], [[TMP27]], !dbg [[DBG146]]
5002 // CHECK-TLS4-NEXT:    store i32 [[ADD14]], ptr [[RES]], align 4, !dbg [[DBG146]]
5003 // CHECK-TLS4-NEXT:    [[TMP29:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG147:![0-9]+]]
5004 // CHECK-TLS4-NEXT:    ret i32 [[TMP29]], !dbg [[DBG148:![0-9]+]]
5005 //
5006 //
5007 // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZTWL3gs1
5008 // CHECK-TLS4-SAME: () #[[ATTR2:[0-9]+]] {
5009 // CHECK-TLS4-NEXT:    call void @_ZTHL3gs1()
5010 // CHECK-TLS4-NEXT:    [[TMP1:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZL3gs1)
5011 // CHECK-TLS4-NEXT:    ret ptr [[TMP1]]
5012 //
5013 //
5014 // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC1Ei
5015 // CHECK-TLS4-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR3:[0-9]+]] align 2 !dbg [[DBG149:![0-9]+]] {
5016 // CHECK-TLS4-NEXT:  entry:
5017 // CHECK-TLS4-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
5018 // CHECK-TLS4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
5019 // CHECK-TLS4-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
5020 // CHECK-TLS4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META150:![0-9]+]], metadata !DIExpression()), !dbg [[DBG152:![0-9]+]]
5021 // CHECK-TLS4-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
5022 // CHECK-TLS4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META153:![0-9]+]], metadata !DIExpression()), !dbg [[DBG154:![0-9]+]]
5023 // CHECK-TLS4-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
5024 // CHECK-TLS4-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG155:![0-9]+]]
5025 // CHECK-TLS4-NEXT:    call void @_ZZ4mainEN5SmainC2Ei(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG155]]
5026 // CHECK-TLS4-NEXT:    ret void, !dbg [[DBG156:![0-9]+]]
5027 //
5028 //
5029 // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD1Ev
5030 // CHECK-TLS4-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR4:[0-9]+]] align 2 !dbg [[DBG157:![0-9]+]] {
5031 // CHECK-TLS4-NEXT:  entry:
5032 // CHECK-TLS4-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
5033 // CHECK-TLS4-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
5034 // CHECK-TLS4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META158:![0-9]+]], metadata !DIExpression()), !dbg [[DBG159:![0-9]+]]
5035 // CHECK-TLS4-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
5036 // CHECK-TLS4-NEXT:    call void @_ZZ4mainEN5SmainD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR5]], !dbg [[DBG160:![0-9]+]]
5037 // CHECK-TLS4-NEXT:    ret void, !dbg [[DBG161:![0-9]+]]
5038 //
5039 //
5040 // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZTWN6Static1sE
5041 // CHECK-TLS4-SAME: () #[[ATTR2]] comdat {
5042 // CHECK-TLS4-NEXT:    br i1 icmp ne (ptr @_ZTHN6Static1sE, ptr null), label [[TMP1:%.*]], label [[TMP2:%.*]]
5043 // CHECK-TLS4:       1:
5044 // CHECK-TLS4-NEXT:    call void @_ZTHN6Static1sE()
5045 // CHECK-TLS4-NEXT:    br label [[TMP2]]
5046 // CHECK-TLS4:       2:
5047 // CHECK-TLS4-NEXT:    [[TMP3:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZN6Static1sE)
5048 // CHECK-TLS4-NEXT:    ret ptr [[TMP3]]
5049 //
5050 //
5051 // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZTW3gs3
5052 // CHECK-TLS4-SAME: () #[[ATTR2]] comdat {
5053 // CHECK-TLS4-NEXT:    br i1 icmp ne (ptr @_ZTH3gs3, ptr null), label [[TMP1:%.*]], label [[TMP2:%.*]]
5054 // CHECK-TLS4:       1:
5055 // CHECK-TLS4-NEXT:    call void @_ZTH3gs3()
5056 // CHECK-TLS4-NEXT:    br label [[TMP2]]
5057 // CHECK-TLS4:       2:
5058 // CHECK-TLS4-NEXT:    [[TMP3:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @gs3)
5059 // CHECK-TLS4-NEXT:    ret ptr [[TMP3]]
5060 //
5061 //
5062 // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZTW5arr_x
5063 // CHECK-TLS4-SAME: () #[[ATTR2]] comdat {
5064 // CHECK-TLS4-NEXT:    call void @_ZTH5arr_x()
5065 // CHECK-TLS4-NEXT:    [[TMP1:%.*]] = call align 16 ptr @llvm.threadlocal.address.p0(ptr align 16 @arr_x)
5066 // CHECK-TLS4-NEXT:    ret ptr [[TMP1]]
5067 //
5068 //
5069 // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZTWN2STIiE2stE
5070 // CHECK-TLS4-SAME: () #[[ATTR2]] comdat {
5071 // CHECK-TLS4-NEXT:    [[TMP1:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZN2STIiE2stE)
5072 // CHECK-TLS4-NEXT:    ret ptr [[TMP1]]
5073 //
5074 //
5075 // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZTWN2STIfE2stE
5076 // CHECK-TLS4-SAME: () #[[ATTR2]] comdat {
5077 // CHECK-TLS4-NEXT:    [[TMP1:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZN2STIfE2stE)
5078 // CHECK-TLS4-NEXT:    ret ptr [[TMP1]]
5079 //
5080 //
5081 // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZTWN2STI2S4E2stE
5082 // CHECK-TLS4-SAME: () #[[ATTR2]] comdat {
5083 // CHECK-TLS4-NEXT:    call void @_ZTHN2STI2S4E2stE()
5084 // CHECK-TLS4-NEXT:    [[TMP1:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZN2STI2S4E2stE)
5085 // CHECK-TLS4-NEXT:    ret ptr [[TMP1]]
5086 //
5087 //
5088 // CHECK-TLS4-LABEL: define {{[^@]+}}@_Z6foobarv
5089 // CHECK-TLS4-SAME: () #[[ATTR6:[0-9]+]] !dbg [[DBG162:![0-9]+]] {
5090 // CHECK-TLS4-NEXT:  entry:
5091 // CHECK-TLS4-NEXT:    [[RES:%.*]] = alloca i32, align 4
5092 // CHECK-TLS4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[RES]], metadata [[META163:![0-9]+]], metadata !DIExpression()), !dbg [[DBG164:![0-9]+]]
5093 // CHECK-TLS4-NEXT:    [[TMP0:%.*]] = call ptr @_ZTWN6Static1sE(), !dbg [[DBG165:![0-9]+]]
5094 // CHECK-TLS4-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S3:%.*]], ptr [[TMP0]], i32 0, i32 0, !dbg [[DBG166:![0-9]+]]
5095 // CHECK-TLS4-NEXT:    [[TMP1:%.*]] = load i32, ptr [[A]], align 4, !dbg [[DBG166]]
5096 // CHECK-TLS4-NEXT:    store i32 [[TMP1]], ptr [[RES]], align 4, !dbg [[DBG167:![0-9]+]]
5097 // CHECK-TLS4-NEXT:    [[TMP2:%.*]] = call ptr @_ZTWL3gs1(), !dbg [[DBG168:![0-9]+]]
5098 // CHECK-TLS4-NEXT:    [[A1:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP2]], i32 0, i32 0, !dbg [[DBG169:![0-9]+]]
5099 // CHECK-TLS4-NEXT:    [[TMP3:%.*]] = load i32, ptr [[A1]], align 4, !dbg [[DBG169]]
5100 // CHECK-TLS4-NEXT:    [[TMP4:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG170:![0-9]+]]
5101 // CHECK-TLS4-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP4]], [[TMP3]], !dbg [[DBG170]]
5102 // CHECK-TLS4-NEXT:    store i32 [[ADD]], ptr [[RES]], align 4, !dbg [[DBG170]]
5103 // CHECK-TLS4-NEXT:    [[TMP5:%.*]] = load i32, ptr @_ZL3gs2, align 8, !dbg [[DBG171:![0-9]+]]
5104 // CHECK-TLS4-NEXT:    [[TMP6:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG172:![0-9]+]]
5105 // CHECK-TLS4-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP6]], [[TMP5]], !dbg [[DBG172]]
5106 // CHECK-TLS4-NEXT:    store i32 [[ADD2]], ptr [[RES]], align 4, !dbg [[DBG172]]
5107 // CHECK-TLS4-NEXT:    [[TMP7:%.*]] = call ptr @_ZTW3gs3(), !dbg [[DBG173:![0-9]+]]
5108 // CHECK-TLS4-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S5:%.*]], ptr [[TMP7]], i32 0, i32 0, !dbg [[DBG174:![0-9]+]]
5109 // CHECK-TLS4-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A3]], align 4, !dbg [[DBG174]]
5110 // CHECK-TLS4-NEXT:    [[TMP9:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG175:![0-9]+]]
5111 // CHECK-TLS4-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP9]], [[TMP8]], !dbg [[DBG175]]
5112 // CHECK-TLS4-NEXT:    store i32 [[ADD4]], ptr [[RES]], align 4, !dbg [[DBG175]]
5113 // CHECK-TLS4-NEXT:    [[TMP10:%.*]] = call ptr @_ZTW5arr_x(), !dbg [[DBG176:![0-9]+]]
5114 // CHECK-TLS4-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP10]], i64 0, i64 1, !dbg [[DBG176]]
5115 // CHECK-TLS4-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG176]]
5116 // CHECK-TLS4-NEXT:    [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYIDX5]], i32 0, i32 0, !dbg [[DBG177:![0-9]+]]
5117 // CHECK-TLS4-NEXT:    [[TMP11:%.*]] = load i32, ptr [[A6]], align 4, !dbg [[DBG177]]
5118 // CHECK-TLS4-NEXT:    [[TMP12:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG178:![0-9]+]]
5119 // CHECK-TLS4-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP12]], [[TMP11]], !dbg [[DBG178]]
5120 // CHECK-TLS4-NEXT:    store i32 [[ADD7]], ptr [[RES]], align 4, !dbg [[DBG178]]
5121 // CHECK-TLS4-NEXT:    [[TMP13:%.*]] = call ptr @_ZTWN2STIiE2stE(), !dbg [[DBG179:![0-9]+]]
5122 // CHECK-TLS4-NEXT:    [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4, !dbg [[DBG179]]
5123 // CHECK-TLS4-NEXT:    [[TMP15:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG180:![0-9]+]]
5124 // CHECK-TLS4-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP15]], [[TMP14]], !dbg [[DBG180]]
5125 // CHECK-TLS4-NEXT:    store i32 [[ADD8]], ptr [[RES]], align 4, !dbg [[DBG180]]
5126 // CHECK-TLS4-NEXT:    [[TMP16:%.*]] = call ptr @_ZTWN2STIfE2stE(), !dbg [[DBG181:![0-9]+]]
5127 // CHECK-TLS4-NEXT:    [[TMP17:%.*]] = load float, ptr [[TMP16]], align 4, !dbg [[DBG181]]
5128 // CHECK-TLS4-NEXT:    [[CONV:%.*]] = fptosi float [[TMP17]] to i32, !dbg [[DBG181]]
5129 // CHECK-TLS4-NEXT:    [[TMP18:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG182:![0-9]+]]
5130 // CHECK-TLS4-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP18]], [[CONV]], !dbg [[DBG182]]
5131 // CHECK-TLS4-NEXT:    store i32 [[ADD9]], ptr [[RES]], align 4, !dbg [[DBG182]]
5132 // CHECK-TLS4-NEXT:    [[TMP19:%.*]] = call ptr @_ZTWN2STI2S4E2stE(), !dbg [[DBG183:![0-9]+]]
5133 // CHECK-TLS4-NEXT:    [[A10:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[TMP19]], i32 0, i32 0, !dbg [[DBG184:![0-9]+]]
5134 // CHECK-TLS4-NEXT:    [[TMP20:%.*]] = load i32, ptr [[A10]], align 4, !dbg [[DBG184]]
5135 // CHECK-TLS4-NEXT:    [[TMP21:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG185:![0-9]+]]
5136 // CHECK-TLS4-NEXT:    [[ADD11:%.*]] = add nsw i32 [[TMP21]], [[TMP20]], !dbg [[DBG185]]
5137 // CHECK-TLS4-NEXT:    store i32 [[ADD11]], ptr [[RES]], align 4, !dbg [[DBG185]]
5138 // CHECK-TLS4-NEXT:    [[TMP22:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG186:![0-9]+]]
5139 // CHECK-TLS4-NEXT:    ret i32 [[TMP22]], !dbg [[DBG187:![0-9]+]]
5140 //
5141 //
5142 // CHECK-TLS4-LABEL: define {{[^@]+}}@__cxx_global_var_init
5143 // CHECK-TLS4-SAME: () #[[ATTR7:[0-9]+]] !dbg [[DBG188:![0-9]+]] {
5144 // CHECK-TLS4-NEXT:  entry:
5145 // CHECK-TLS4-NEXT:    call void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @_ZL3gs1, i32 noundef 5), !dbg [[DBG192:![0-9]+]]
5146 // CHECK-TLS4-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_thread_atexit(ptr @_ZN2S1D1Ev, ptr @_ZL3gs1, ptr @__dso_handle) #[[ATTR5]], !dbg [[DBG194:![0-9]+]]
5147 // CHECK-TLS4-NEXT:    ret void, !dbg [[DBG195:![0-9]+]]
5148 //
5149 //
5150 // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZN2S1C1Ei
5151 // CHECK-TLS4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG196:![0-9]+]] {
5152 // CHECK-TLS4-NEXT:  entry:
5153 // CHECK-TLS4-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
5154 // CHECK-TLS4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
5155 // CHECK-TLS4-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
5156 // CHECK-TLS4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META197:![0-9]+]], metadata !DIExpression()), !dbg [[DBG199:![0-9]+]]
5157 // CHECK-TLS4-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
5158 // CHECK-TLS4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META200:![0-9]+]], metadata !DIExpression()), !dbg [[DBG201:![0-9]+]]
5159 // CHECK-TLS4-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
5160 // CHECK-TLS4-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG202:![0-9]+]]
5161 // CHECK-TLS4-NEXT:    call void @_ZN2S1C2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG202]]
5162 // CHECK-TLS4-NEXT:    ret void, !dbg [[DBG203:![0-9]+]]
5163 //
5164 //
5165 // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZN2S1D1Ev
5166 // CHECK-TLS4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 !dbg [[DBG204:![0-9]+]] {
5167 // CHECK-TLS4-NEXT:  entry:
5168 // CHECK-TLS4-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
5169 // CHECK-TLS4-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
5170 // CHECK-TLS4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META205:![0-9]+]], metadata !DIExpression()), !dbg [[DBG206:![0-9]+]]
5171 // CHECK-TLS4-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
5172 // CHECK-TLS4-NEXT:    call void @_ZN2S1D2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]], !dbg [[DBG207:![0-9]+]]
5173 // CHECK-TLS4-NEXT:    ret void, !dbg [[DBG208:![0-9]+]]
5174 //
5175 //
5176 // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZN2S1C2Ei
5177 // CHECK-TLS4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 !dbg [[DBG209:![0-9]+]] {
5178 // CHECK-TLS4-NEXT:  entry:
5179 // CHECK-TLS4-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
5180 // CHECK-TLS4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
5181 // CHECK-TLS4-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
5182 // CHECK-TLS4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META210:![0-9]+]], metadata !DIExpression()), !dbg [[DBG211:![0-9]+]]
5183 // CHECK-TLS4-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
5184 // CHECK-TLS4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META212:![0-9]+]], metadata !DIExpression()), !dbg [[DBG213:![0-9]+]]
5185 // CHECK-TLS4-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
5186 // CHECK-TLS4-NEXT:    [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG214:![0-9]+]]
5187 // CHECK-TLS4-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG215:![0-9]+]]
5188 // CHECK-TLS4-NEXT:    store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG214]]
5189 // CHECK-TLS4-NEXT:    ret void, !dbg [[DBG216:![0-9]+]]
5190 //
5191 //
5192 // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZN2S1D2Ev
5193 // CHECK-TLS4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 !dbg [[DBG217:![0-9]+]] {
5194 // CHECK-TLS4-NEXT:  entry:
5195 // CHECK-TLS4-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
5196 // CHECK-TLS4-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
5197 // CHECK-TLS4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META218:![0-9]+]], metadata !DIExpression()), !dbg [[DBG219:![0-9]+]]
5198 // CHECK-TLS4-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
5199 // CHECK-TLS4-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG220:![0-9]+]]
5200 // CHECK-TLS4-NEXT:    store i32 0, ptr [[A]], align 4, !dbg [[DBG222:![0-9]+]]
5201 // CHECK-TLS4-NEXT:    ret void, !dbg [[DBG223:![0-9]+]]
5202 //
5203 //
5204 // CHECK-TLS4-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
5205 // CHECK-TLS4-SAME: () #[[ATTR7]] !dbg [[DBG224:![0-9]+]] {
5206 // CHECK-TLS4-NEXT:  entry:
5207 // CHECK-TLS4-NEXT:    call void @_ZN2S2C1Ei(ptr noundef nonnull align 8 dereferenceable(16) @_ZL3gs2, i32 noundef 27), !dbg [[DBG225:![0-9]+]]
5208 // CHECK-TLS4-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S2D1Ev, ptr @_ZL3gs2, ptr @__dso_handle) #[[ATTR5]], !dbg [[DBG227:![0-9]+]]
5209 // CHECK-TLS4-NEXT:    ret void, !dbg [[DBG228:![0-9]+]]
5210 //
5211 //
5212 // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZN2S2C1Ei
5213 // CHECK-TLS4-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG229:![0-9]+]] {
5214 // CHECK-TLS4-NEXT:  entry:
5215 // CHECK-TLS4-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
5216 // CHECK-TLS4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
5217 // CHECK-TLS4-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
5218 // CHECK-TLS4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META230:![0-9]+]], metadata !DIExpression()), !dbg [[DBG232:![0-9]+]]
5219 // CHECK-TLS4-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
5220 // CHECK-TLS4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META233:![0-9]+]], metadata !DIExpression()), !dbg [[DBG234:![0-9]+]]
5221 // CHECK-TLS4-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
5222 // CHECK-TLS4-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG235:![0-9]+]]
5223 // CHECK-TLS4-NEXT:    call void @_ZN2S2C2Ei(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG235]]
5224 // CHECK-TLS4-NEXT:    ret void, !dbg [[DBG236:![0-9]+]]
5225 //
5226 //
5227 // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZN2S2D1Ev
5228 // CHECK-TLS4-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 !dbg [[DBG237:![0-9]+]] {
5229 // CHECK-TLS4-NEXT:  entry:
5230 // CHECK-TLS4-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
5231 // CHECK-TLS4-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
5232 // CHECK-TLS4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META238:![0-9]+]], metadata !DIExpression()), !dbg [[DBG239:![0-9]+]]
5233 // CHECK-TLS4-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
5234 // CHECK-TLS4-NEXT:    call void @_ZN2S2D2Ev(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]]) #[[ATTR5]], !dbg [[DBG240:![0-9]+]]
5235 // CHECK-TLS4-NEXT:    ret void, !dbg [[DBG241:![0-9]+]]
5236 //
5237 //
5238 // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZN2S2C2Ei
5239 // CHECK-TLS4-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 !dbg [[DBG242:![0-9]+]] {
5240 // CHECK-TLS4-NEXT:  entry:
5241 // CHECK-TLS4-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
5242 // CHECK-TLS4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
5243 // CHECK-TLS4-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
5244 // CHECK-TLS4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META243:![0-9]+]], metadata !DIExpression()), !dbg [[DBG244:![0-9]+]]
5245 // CHECK-TLS4-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
5246 // CHECK-TLS4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META245:![0-9]+]], metadata !DIExpression()), !dbg [[DBG246:![0-9]+]]
5247 // CHECK-TLS4-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
5248 // CHECK-TLS4-NEXT:    [[A2:%.*]] = getelementptr inbounds [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG247:![0-9]+]]
5249 // CHECK-TLS4-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG248:![0-9]+]]
5250 // CHECK-TLS4-NEXT:    store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG247]]
5251 // CHECK-TLS4-NEXT:    ret void, !dbg [[DBG249:![0-9]+]]
5252 //
5253 //
5254 // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZN2S2D2Ev
5255 // CHECK-TLS4-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 !dbg [[DBG250:![0-9]+]] {
5256 // CHECK-TLS4-NEXT:  entry:
5257 // CHECK-TLS4-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
5258 // CHECK-TLS4-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
5259 // CHECK-TLS4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META251:![0-9]+]], metadata !DIExpression()), !dbg [[DBG252:![0-9]+]]
5260 // CHECK-TLS4-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
5261 // CHECK-TLS4-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG253:![0-9]+]]
5262 // CHECK-TLS4-NEXT:    store i32 0, ptr [[A]], align 8, !dbg [[DBG255:![0-9]+]]
5263 // CHECK-TLS4-NEXT:    ret void, !dbg [[DBG256:![0-9]+]]
5264 //
5265 //
5266 // CHECK-TLS4-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
5267 // CHECK-TLS4-SAME: () #[[ATTR7]] personality ptr @__gxx_personality_v0 !dbg [[DBG257:![0-9]+]] {
5268 // CHECK-TLS4-NEXT:  entry:
5269 // CHECK-TLS4-NEXT:    [[ARRAYINIT_ENDOFINIT:%.*]] = alloca ptr, align 8
5270 // CHECK-TLS4-NEXT:    [[ARRAYINIT_ENDOFINIT1:%.*]] = alloca ptr, align 8
5271 // CHECK-TLS4-NEXT:    [[EXN_SLOT:%.*]] = alloca ptr, align 8
5272 // CHECK-TLS4-NEXT:    [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4
5273 // CHECK-TLS4-NEXT:    [[ARRAYINIT_ENDOFINIT5:%.*]] = alloca ptr, align 8
5274 // CHECK-TLS4-NEXT:    store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG258:![0-9]+]]
5275 // CHECK-TLS4-NEXT:    store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG260:![0-9]+]]
5276 // CHECK-TLS4-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @arr_x, i32 noundef 1)
5277 // CHECK-TLS4-NEXT:    to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG261:![0-9]+]]
5278 // CHECK-TLS4:       invoke.cont:
5279 // CHECK-TLS4-NEXT:    store ptr getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG260]]
5280 // CHECK-TLS4-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 1), i32 noundef 2)
5281 // CHECK-TLS4-NEXT:    to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD]], !dbg [[DBG262:![0-9]+]]
5282 // CHECK-TLS4:       invoke.cont2:
5283 // CHECK-TLS4-NEXT:    store ptr getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG260]]
5284 // CHECK-TLS4-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), i32 noundef 3)
5285 // CHECK-TLS4-NEXT:    to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]], !dbg [[DBG263:![0-9]+]]
5286 // CHECK-TLS4:       invoke.cont3:
5287 // CHECK-TLS4-NEXT:    store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG258]]
5288 // CHECK-TLS4-NEXT:    store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG264:![0-9]+]]
5289 // CHECK-TLS4-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i32 noundef 4)
5290 // CHECK-TLS4-NEXT:    to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD6:%.*]], !dbg [[DBG265:![0-9]+]]
5291 // CHECK-TLS4:       invoke.cont7:
5292 // CHECK-TLS4-NEXT:    store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG264]]
5293 // CHECK-TLS4-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), i32 noundef 5)
5294 // CHECK-TLS4-NEXT:    to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD6]], !dbg [[DBG266:![0-9]+]]
5295 // CHECK-TLS4:       invoke.cont8:
5296 // CHECK-TLS4-NEXT:    store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG264]]
5297 // CHECK-TLS4-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), i32 noundef 6)
5298 // CHECK-TLS4-NEXT:    to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD6]], !dbg [[DBG267:![0-9]+]]
5299 // CHECK-TLS4:       invoke.cont9:
5300 // CHECK-TLS4-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_thread_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR5]], !dbg [[DBG268:![0-9]+]]
5301 // CHECK-TLS4-NEXT:    ret void, !dbg [[DBG268]]
5302 // CHECK-TLS4:       lpad:
5303 // CHECK-TLS4-NEXT:    [[TMP1:%.*]] = landingpad { ptr, i32 }
5304 // CHECK-TLS4-NEXT:    cleanup, !dbg [[DBG269:![0-9]+]]
5305 // CHECK-TLS4-NEXT:    [[TMP2:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 0, !dbg [[DBG269]]
5306 // CHECK-TLS4-NEXT:    store ptr [[TMP2]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG269]]
5307 // CHECK-TLS4-NEXT:    [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 1, !dbg [[DBG269]]
5308 // CHECK-TLS4-NEXT:    store i32 [[TMP3]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG269]]
5309 // CHECK-TLS4-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG260]]
5310 // CHECK-TLS4-NEXT:    [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr @arr_x, [[TMP4]], !dbg [[DBG260]]
5311 // CHECK-TLS4-NEXT:    br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG260]]
5312 // CHECK-TLS4:       arraydestroy.body:
5313 // CHECK-TLS4-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP4]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG260]]
5314 // CHECK-TLS4-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG260]]
5315 // CHECK-TLS4-NEXT:    call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]], !dbg [[DBG260]]
5316 // CHECK-TLS4-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[DBG260]]
5317 // CHECK-TLS4-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG260]]
5318 // CHECK-TLS4:       arraydestroy.done4:
5319 // CHECK-TLS4-NEXT:    br label [[EHCLEANUP:%.*]], !dbg [[DBG260]]
5320 // CHECK-TLS4:       lpad6:
5321 // CHECK-TLS4-NEXT:    [[TMP5:%.*]] = landingpad { ptr, i32 }
5322 // CHECK-TLS4-NEXT:    cleanup, !dbg [[DBG269]]
5323 // CHECK-TLS4-NEXT:    [[TMP6:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 0, !dbg [[DBG269]]
5324 // CHECK-TLS4-NEXT:    store ptr [[TMP6]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG269]]
5325 // CHECK-TLS4-NEXT:    [[TMP7:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 1, !dbg [[DBG269]]
5326 // CHECK-TLS4-NEXT:    store i32 [[TMP7]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG269]]
5327 // CHECK-TLS4-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG264]]
5328 // CHECK-TLS4-NEXT:    [[ARRAYDESTROY_ISEMPTY10:%.*]] = icmp eq ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), [[TMP8]], !dbg [[DBG264]]
5329 // CHECK-TLS4-NEXT:    br i1 [[ARRAYDESTROY_ISEMPTY10]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY11:%.*]], !dbg [[DBG264]]
5330 // CHECK-TLS4:       arraydestroy.body11:
5331 // CHECK-TLS4-NEXT:    [[ARRAYDESTROY_ELEMENTPAST12:%.*]] = phi ptr [ [[TMP8]], [[LPAD6]] ], [ [[ARRAYDESTROY_ELEMENT13:%.*]], [[ARRAYDESTROY_BODY11]] ], !dbg [[DBG264]]
5332 // CHECK-TLS4-NEXT:    [[ARRAYDESTROY_ELEMENT13]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST12]], i64 -1, !dbg [[DBG264]]
5333 // CHECK-TLS4-NEXT:    call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR5]], !dbg [[DBG264]]
5334 // CHECK-TLS4-NEXT:    [[ARRAYDESTROY_DONE14:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), !dbg [[DBG264]]
5335 // CHECK-TLS4-NEXT:    br i1 [[ARRAYDESTROY_DONE14]], label [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_BODY11]], !dbg [[DBG264]]
5336 // CHECK-TLS4:       arraydestroy.done15:
5337 // CHECK-TLS4-NEXT:    br label [[EHCLEANUP]], !dbg [[DBG264]]
5338 // CHECK-TLS4:       ehcleanup:
5339 // CHECK-TLS4-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG258]]
5340 // CHECK-TLS4-NEXT:    [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP9]], i64 0, i64 0, !dbg [[DBG258]]
5341 // CHECK-TLS4-NEXT:    [[ARRAYDESTROY_ISEMPTY16:%.*]] = icmp eq ptr @arr_x, [[PAD_ARRAYEND]], !dbg [[DBG258]]
5342 // CHECK-TLS4-NEXT:    br i1 [[ARRAYDESTROY_ISEMPTY16]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17:%.*]], !dbg [[DBG258]]
5343 // CHECK-TLS4:       arraydestroy.body17:
5344 // CHECK-TLS4-NEXT:    [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi ptr [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ], !dbg [[DBG258]]
5345 // CHECK-TLS4-NEXT:    [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1, !dbg [[DBG258]]
5346 // CHECK-TLS4-NEXT:    call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR5]], !dbg [[DBG258]]
5347 // CHECK-TLS4-NEXT:    [[ARRAYDESTROY_DONE20:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT19]], @arr_x, !dbg [[DBG258]]
5348 // CHECK-TLS4-NEXT:    br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]], !dbg [[DBG258]]
5349 // CHECK-TLS4:       arraydestroy.done21:
5350 // CHECK-TLS4-NEXT:    br label [[EH_RESUME:%.*]], !dbg [[DBG258]]
5351 // CHECK-TLS4:       eh.resume:
5352 // CHECK-TLS4-NEXT:    [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG258]]
5353 // CHECK-TLS4-NEXT:    [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG258]]
5354 // CHECK-TLS4-NEXT:    [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG258]]
5355 // CHECK-TLS4-NEXT:    [[LPAD_VAL22:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG258]]
5356 // CHECK-TLS4-NEXT:    resume { ptr, i32 } [[LPAD_VAL22]], !dbg [[DBG258]]
5357 //
5358 //
5359 // CHECK-TLS4-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
5360 // CHECK-TLS4-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR7]] !dbg [[DBG270:![0-9]+]] {
5361 // CHECK-TLS4-NEXT:  entry:
5362 // CHECK-TLS4-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
5363 // CHECK-TLS4-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
5364 // CHECK-TLS4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[DOTADDR]], metadata [[META274:![0-9]+]], metadata !DIExpression()), !dbg [[DBG275:![0-9]+]]
5365 // CHECK-TLS4-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG275]]
5366 // CHECK-TLS4:       arraydestroy.body:
5367 // CHECK-TLS4-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 6), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG275]]
5368 // CHECK-TLS4-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG275]]
5369 // CHECK-TLS4-NEXT:    call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]], !dbg [[DBG275]]
5370 // CHECK-TLS4-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[DBG275]]
5371 // CHECK-TLS4-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG275]]
5372 // CHECK-TLS4:       arraydestroy.done1:
5373 // CHECK-TLS4-NEXT:    ret void, !dbg [[DBG275]]
5374 //
5375 //
5376 // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC2Ei
5377 // CHECK-TLS4-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR4]] align 2 !dbg [[DBG276:![0-9]+]] {
5378 // CHECK-TLS4-NEXT:  entry:
5379 // CHECK-TLS4-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
5380 // CHECK-TLS4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
5381 // CHECK-TLS4-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
5382 // CHECK-TLS4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META277:![0-9]+]], metadata !DIExpression()), !dbg [[DBG278:![0-9]+]]
5383 // CHECK-TLS4-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
5384 // CHECK-TLS4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META279:![0-9]+]], metadata !DIExpression()), !dbg [[DBG280:![0-9]+]]
5385 // CHECK-TLS4-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
5386 // CHECK-TLS4-NEXT:    [[A2:%.*]] = getelementptr inbounds [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG281:![0-9]+]]
5387 // CHECK-TLS4-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG282:![0-9]+]]
5388 // CHECK-TLS4-NEXT:    store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG281]]
5389 // CHECK-TLS4-NEXT:    ret void, !dbg [[DBG283:![0-9]+]]
5390 //
5391 //
5392 // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD2Ev
5393 // CHECK-TLS4-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR4]] align 2 !dbg [[DBG284:![0-9]+]] {
5394 // CHECK-TLS4-NEXT:  entry:
5395 // CHECK-TLS4-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
5396 // CHECK-TLS4-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
5397 // CHECK-TLS4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META285:![0-9]+]], metadata !DIExpression()), !dbg [[DBG286:![0-9]+]]
5398 // CHECK-TLS4-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
5399 // CHECK-TLS4-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG287:![0-9]+]]
5400 // CHECK-TLS4-NEXT:    store i32 0, ptr [[A]], align 8, !dbg [[DBG289:![0-9]+]]
5401 // CHECK-TLS4-NEXT:    ret void, !dbg [[DBG290:![0-9]+]]
5402 //
5403 //
5404 // CHECK-TLS4-LABEL: define {{[^@]+}}@__cxx_global_var_init.3
5405 // CHECK-TLS4-SAME: () #[[ATTR7]] !dbg [[DBG291:![0-9]+]] {
5406 // CHECK-TLS4-NEXT:  entry:
5407 // CHECK-TLS4-NEXT:    [[TMP0:%.*]] = load i8, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG292:![0-9]+]]
5408 // CHECK-TLS4-NEXT:    [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG292]]
5409 // CHECK-TLS4-NEXT:    br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG292]]
5410 // CHECK-TLS4:       init.check:
5411 // CHECK-TLS4-NEXT:    store i8 1, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG292]]
5412 // CHECK-TLS4-NEXT:    call void @_ZN2S4C1Ei(ptr noundef nonnull align 4 dereferenceable(8) @_ZN2STI2S4E2stE, i32 noundef 23), !dbg [[DBG293:![0-9]+]]
5413 // CHECK-TLS4-NEXT:    [[TMP1:%.*]] = call i32 @__cxa_thread_atexit(ptr @_ZN2S4D1Ev, ptr @_ZN2STI2S4E2stE, ptr @__dso_handle) #[[ATTR5]], !dbg [[DBG292]]
5414 // CHECK-TLS4-NEXT:    br label [[INIT_END]], !dbg [[DBG292]]
5415 // CHECK-TLS4:       init.end:
5416 // CHECK-TLS4-NEXT:    ret void, !dbg [[DBG295:![0-9]+]]
5417 //
5418 //
5419 // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZN2S4C1Ei
5420 // CHECK-TLS4-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG296:![0-9]+]] {
5421 // CHECK-TLS4-NEXT:  entry:
5422 // CHECK-TLS4-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
5423 // CHECK-TLS4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
5424 // CHECK-TLS4-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
5425 // CHECK-TLS4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META297:![0-9]+]], metadata !DIExpression()), !dbg [[DBG299:![0-9]+]]
5426 // CHECK-TLS4-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
5427 // CHECK-TLS4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META300:![0-9]+]], metadata !DIExpression()), !dbg [[DBG301:![0-9]+]]
5428 // CHECK-TLS4-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
5429 // CHECK-TLS4-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG302:![0-9]+]]
5430 // CHECK-TLS4-NEXT:    call void @_ZN2S4C2Ei(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG302]]
5431 // CHECK-TLS4-NEXT:    ret void, !dbg [[DBG303:![0-9]+]]
5432 //
5433 //
5434 // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZN2S4D1Ev
5435 // CHECK-TLS4-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 !dbg [[DBG304:![0-9]+]] {
5436 // CHECK-TLS4-NEXT:  entry:
5437 // CHECK-TLS4-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
5438 // CHECK-TLS4-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
5439 // CHECK-TLS4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META305:![0-9]+]], metadata !DIExpression()), !dbg [[DBG306:![0-9]+]]
5440 // CHECK-TLS4-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
5441 // CHECK-TLS4-NEXT:    call void @_ZN2S4D2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR5]], !dbg [[DBG307:![0-9]+]]
5442 // CHECK-TLS4-NEXT:    ret void, !dbg [[DBG308:![0-9]+]]
5443 //
5444 //
5445 // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZN2S4C2Ei
5446 // CHECK-TLS4-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 !dbg [[DBG309:![0-9]+]] {
5447 // CHECK-TLS4-NEXT:  entry:
5448 // CHECK-TLS4-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
5449 // CHECK-TLS4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
5450 // CHECK-TLS4-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
5451 // CHECK-TLS4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META310:![0-9]+]], metadata !DIExpression()), !dbg [[DBG311:![0-9]+]]
5452 // CHECK-TLS4-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
5453 // CHECK-TLS4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META312:![0-9]+]], metadata !DIExpression()), !dbg [[DBG313:![0-9]+]]
5454 // CHECK-TLS4-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
5455 // CHECK-TLS4-NEXT:    [[A2:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG314:![0-9]+]]
5456 // CHECK-TLS4-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG315:![0-9]+]]
5457 // CHECK-TLS4-NEXT:    store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG314]]
5458 // CHECK-TLS4-NEXT:    ret void, !dbg [[DBG316:![0-9]+]]
5459 //
5460 //
5461 // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZN2S4D2Ev
5462 // CHECK-TLS4-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 !dbg [[DBG317:![0-9]+]] {
5463 // CHECK-TLS4-NEXT:  entry:
5464 // CHECK-TLS4-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
5465 // CHECK-TLS4-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
5466 // CHECK-TLS4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META318:![0-9]+]], metadata !DIExpression()), !dbg [[DBG319:![0-9]+]]
5467 // CHECK-TLS4-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
5468 // CHECK-TLS4-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG320:![0-9]+]]
5469 // CHECK-TLS4-NEXT:    store i32 0, ptr [[A]], align 4, !dbg [[DBG322:![0-9]+]]
5470 // CHECK-TLS4-NEXT:    ret void, !dbg [[DBG323:![0-9]+]]
5471 //
5472 //
5473 // CHECK-TLS4-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_threadprivate_codegen.cpp
5474 // CHECK-TLS4-SAME: () #[[ATTR7]] !dbg [[DBG324:![0-9]+]] {
5475 // CHECK-TLS4-NEXT:  entry:
5476 // CHECK-TLS4-NEXT:    call void @__cxx_global_var_init.1(), !dbg [[DBG326:![0-9]+]]
5477 // CHECK-TLS4-NEXT:    ret void
5478 //
5479 //
5480 // CHECK-TLS4-LABEL: define {{[^@]+}}@__tls_init
5481 // CHECK-TLS4-SAME: () #[[ATTR7]] !dbg [[DBG327:![0-9]+]] {
5482 // CHECK-TLS4-NEXT:  entry:
5483 // CHECK-TLS4-NEXT:    [[TMP0:%.*]] = load i8, ptr @__tls_guard, align 1, !dbg [[DBG328:![0-9]+]]
5484 // CHECK-TLS4-NEXT:    [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG328]]
5485 // CHECK-TLS4-NEXT:    br i1 [[GUARD_UNINITIALIZED]], label [[INIT:%.*]], label [[EXIT:%.*]], !dbg [[DBG328]], !prof [[PROF119]]
5486 // CHECK-TLS4:       init:
5487 // CHECK-TLS4-NEXT:    store i8 1, ptr @__tls_guard, align 1, !dbg [[DBG328]]
5488 // CHECK-TLS4-NEXT:    call void @__cxx_global_var_init(), !dbg [[DBG328]]
5489 // CHECK-TLS4-NEXT:    call void @__cxx_global_var_init.2(), !dbg [[DBG328]]
5490 // CHECK-TLS4-NEXT:    br label [[EXIT]], !dbg [[DBG328]]
5491 // CHECK-TLS4:       exit:
5492 // CHECK-TLS4-NEXT:    ret void
5493 //
5494 //
5495 // SIMD3-LABEL: define {{[^@]+}}@__cxx_global_var_init
5496 // SIMD3-SAME: () #[[ATTR0:[0-9]+]] {
5497 // SIMD3-NEXT:  entry:
5498 // SIMD3-NEXT:    call void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @_ZL3gs1, i32 noundef 5)
5499 // SIMD3-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S1D1Ev, ptr @_ZL3gs1, ptr @__dso_handle) #[[ATTR3:[0-9]+]]
5500 // SIMD3-NEXT:    ret void
5501 //
5502 //
5503 // SIMD3-LABEL: define {{[^@]+}}@_ZN2S1C1Ei
5504 // SIMD3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
5505 // SIMD3-NEXT:  entry:
5506 // SIMD3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
5507 // SIMD3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
5508 // SIMD3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
5509 // SIMD3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
5510 // SIMD3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
5511 // SIMD3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
5512 // SIMD3-NEXT:    call void @_ZN2S1C2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]])
5513 // SIMD3-NEXT:    ret void
5514 //
5515 //
5516 // SIMD3-LABEL: define {{[^@]+}}@_ZN2S1D1Ev
5517 // SIMD3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 {
5518 // SIMD3-NEXT:  entry:
5519 // SIMD3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
5520 // SIMD3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
5521 // SIMD3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
5522 // SIMD3-NEXT:    call void @_ZN2S1D2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]]
5523 // SIMD3-NEXT:    ret void
5524 //
5525 //
5526 // SIMD3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
5527 // SIMD3-SAME: () #[[ATTR0]] {
5528 // SIMD3-NEXT:  entry:
5529 // SIMD3-NEXT:    call void @_ZN2S2C1Ei(ptr noundef nonnull align 8 dereferenceable(16) @_ZL3gs2, i32 noundef 27)
5530 // SIMD3-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S2D1Ev, ptr @_ZL3gs2, ptr @__dso_handle) #[[ATTR3]]
5531 // SIMD3-NEXT:    ret void
5532 //
5533 //
5534 // SIMD3-LABEL: define {{[^@]+}}@_ZN2S2C1Ei
5535 // SIMD3-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
5536 // SIMD3-NEXT:  entry:
5537 // SIMD3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
5538 // SIMD3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
5539 // SIMD3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
5540 // SIMD3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
5541 // SIMD3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
5542 // SIMD3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
5543 // SIMD3-NEXT:    call void @_ZN2S2C2Ei(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], i32 noundef [[TMP0]])
5544 // SIMD3-NEXT:    ret void
5545 //
5546 //
5547 // SIMD3-LABEL: define {{[^@]+}}@_ZN2S2D1Ev
5548 // SIMD3-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
5549 // SIMD3-NEXT:  entry:
5550 // SIMD3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
5551 // SIMD3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
5552 // SIMD3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
5553 // SIMD3-NEXT:    call void @_ZN2S2D2Ev(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]]) #[[ATTR3]]
5554 // SIMD3-NEXT:    ret void
5555 //
5556 //
5557 // SIMD3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
5558 // SIMD3-SAME: () #[[ATTR0]] personality ptr @__gxx_personality_v0 {
5559 // SIMD3-NEXT:  entry:
5560 // SIMD3-NEXT:    [[ARRAYINIT_ENDOFINIT:%.*]] = alloca ptr, align 8
5561 // SIMD3-NEXT:    [[ARRAYINIT_ENDOFINIT1:%.*]] = alloca ptr, align 8
5562 // SIMD3-NEXT:    [[EXN_SLOT:%.*]] = alloca ptr, align 8
5563 // SIMD3-NEXT:    [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4
5564 // SIMD3-NEXT:    [[ARRAYINIT_ENDOFINIT5:%.*]] = alloca ptr, align 8
5565 // SIMD3-NEXT:    store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT]], align 8
5566 // SIMD3-NEXT:    store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT1]], align 8
5567 // SIMD3-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @arr_x, i32 noundef 1)
5568 // SIMD3-NEXT:    to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]]
5569 // SIMD3:       invoke.cont:
5570 // SIMD3-NEXT:    store ptr getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT1]], align 8
5571 // SIMD3-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 1), i32 noundef 2)
5572 // SIMD3-NEXT:    to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD]]
5573 // SIMD3:       invoke.cont2:
5574 // SIMD3-NEXT:    store ptr getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), ptr [[ARRAYINIT_ENDOFINIT1]], align 8
5575 // SIMD3-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), i32 noundef 3)
5576 // SIMD3-NEXT:    to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]]
5577 // SIMD3:       invoke.cont3:
5578 // SIMD3-NEXT:    store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT]], align 8
5579 // SIMD3-NEXT:    store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8
5580 // SIMD3-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i32 noundef 4)
5581 // SIMD3-NEXT:    to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD6:%.*]]
5582 // SIMD3:       invoke.cont7:
5583 // SIMD3-NEXT:    store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8
5584 // SIMD3-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), i32 noundef 5)
5585 // SIMD3-NEXT:    to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD6]]
5586 // SIMD3:       invoke.cont8:
5587 // SIMD3-NEXT:    store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), ptr [[ARRAYINIT_ENDOFINIT5]], align 8
5588 // SIMD3-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), i32 noundef 6)
5589 // SIMD3-NEXT:    to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD6]]
5590 // SIMD3:       invoke.cont9:
5591 // SIMD3-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR3]]
5592 // SIMD3-NEXT:    ret void
5593 // SIMD3:       lpad:
5594 // SIMD3-NEXT:    [[TMP1:%.*]] = landingpad { ptr, i32 }
5595 // SIMD3-NEXT:    cleanup
5596 // SIMD3-NEXT:    [[TMP2:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 0
5597 // SIMD3-NEXT:    store ptr [[TMP2]], ptr [[EXN_SLOT]], align 8
5598 // SIMD3-NEXT:    [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 1
5599 // SIMD3-NEXT:    store i32 [[TMP3]], ptr [[EHSELECTOR_SLOT]], align 4
5600 // SIMD3-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT1]], align 8
5601 // SIMD3-NEXT:    [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr @arr_x, [[TMP4]]
5602 // SIMD3-NEXT:    br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY:%.*]]
5603 // SIMD3:       arraydestroy.body:
5604 // SIMD3-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP4]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
5605 // SIMD3-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
5606 // SIMD3-NEXT:    call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]]
5607 // SIMD3-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x
5608 // SIMD3-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4]], label [[ARRAYDESTROY_BODY]]
5609 // SIMD3:       arraydestroy.done4:
5610 // SIMD3-NEXT:    br label [[EHCLEANUP:%.*]]
5611 // SIMD3:       lpad6:
5612 // SIMD3-NEXT:    [[TMP5:%.*]] = landingpad { ptr, i32 }
5613 // SIMD3-NEXT:    cleanup
5614 // SIMD3-NEXT:    [[TMP6:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 0
5615 // SIMD3-NEXT:    store ptr [[TMP6]], ptr [[EXN_SLOT]], align 8
5616 // SIMD3-NEXT:    [[TMP7:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 1
5617 // SIMD3-NEXT:    store i32 [[TMP7]], ptr [[EHSELECTOR_SLOT]], align 4
5618 // SIMD3-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT5]], align 8
5619 // SIMD3-NEXT:    [[ARRAYDESTROY_ISEMPTY10:%.*]] = icmp eq ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), [[TMP8]]
5620 // SIMD3-NEXT:    br i1 [[ARRAYDESTROY_ISEMPTY10]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY11:%.*]]
5621 // SIMD3:       arraydestroy.body11:
5622 // SIMD3-NEXT:    [[ARRAYDESTROY_ELEMENTPAST12:%.*]] = phi ptr [ [[TMP8]], [[LPAD6]] ], [ [[ARRAYDESTROY_ELEMENT13:%.*]], [[ARRAYDESTROY_BODY11]] ]
5623 // SIMD3-NEXT:    [[ARRAYDESTROY_ELEMENT13]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST12]], i64 -1
5624 // SIMD3-NEXT:    call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR3]]
5625 // SIMD3-NEXT:    [[ARRAYDESTROY_DONE14:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1)
5626 // SIMD3-NEXT:    br i1 [[ARRAYDESTROY_DONE14]], label [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_BODY11]]
5627 // SIMD3:       arraydestroy.done15:
5628 // SIMD3-NEXT:    br label [[EHCLEANUP]]
5629 // SIMD3:       ehcleanup:
5630 // SIMD3-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT]], align 8
5631 // SIMD3-NEXT:    [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP9]], i64 0, i64 0
5632 // SIMD3-NEXT:    [[ARRAYDESTROY_ISEMPTY16:%.*]] = icmp eq ptr @arr_x, [[PAD_ARRAYEND]]
5633 // SIMD3-NEXT:    br i1 [[ARRAYDESTROY_ISEMPTY16]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17:%.*]]
5634 // SIMD3:       arraydestroy.body17:
5635 // SIMD3-NEXT:    [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi ptr [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ]
5636 // SIMD3-NEXT:    [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1
5637 // SIMD3-NEXT:    call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]]
5638 // SIMD3-NEXT:    [[ARRAYDESTROY_DONE20:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT19]], @arr_x
5639 // SIMD3-NEXT:    br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]]
5640 // SIMD3:       arraydestroy.done21:
5641 // SIMD3-NEXT:    br label [[EH_RESUME:%.*]]
5642 // SIMD3:       eh.resume:
5643 // SIMD3-NEXT:    [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8
5644 // SIMD3-NEXT:    [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4
5645 // SIMD3-NEXT:    [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0
5646 // SIMD3-NEXT:    [[LPAD_VAL22:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1
5647 // SIMD3-NEXT:    resume { ptr, i32 } [[LPAD_VAL22]]
5648 //
5649 //
5650 // SIMD3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
5651 // SIMD3-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] {
5652 // SIMD3-NEXT:  entry:
5653 // SIMD3-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
5654 // SIMD3-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
5655 // SIMD3-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
5656 // SIMD3:       arraydestroy.body:
5657 // SIMD3-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 6), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
5658 // SIMD3-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
5659 // SIMD3-NEXT:    call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]]
5660 // SIMD3-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x
5661 // SIMD3-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
5662 // SIMD3:       arraydestroy.done1:
5663 // SIMD3-NEXT:    ret void
5664 //
5665 //
5666 // SIMD3-LABEL: define {{[^@]+}}@main
5667 // SIMD3-SAME: () #[[ATTR4:[0-9]+]] personality ptr @__gxx_personality_v0 {
5668 // SIMD3-NEXT:  entry:
5669 // SIMD3-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
5670 // SIMD3-NEXT:    [[RES:%.*]] = alloca i32, align 4
5671 // SIMD3-NEXT:    [[EXN_SLOT:%.*]] = alloca ptr, align 8
5672 // SIMD3-NEXT:    [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4
5673 // SIMD3-NEXT:    store i32 0, ptr [[RETVAL]], align 4
5674 // SIMD3-NEXT:    [[TMP0:%.*]] = load atomic i8, ptr @_ZGVZ4mainE2sm acquire, align 8
5675 // SIMD3-NEXT:    [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0
5676 // SIMD3-NEXT:    br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF2:![0-9]+]]
5677 // SIMD3:       init.check:
5678 // SIMD3-NEXT:    [[TMP1:%.*]] = call i32 @__cxa_guard_acquire(ptr @_ZGVZ4mainE2sm) #[[ATTR3]]
5679 // SIMD3-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0
5680 // SIMD3-NEXT:    br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]]
5681 // SIMD3:       init:
5682 // SIMD3-NEXT:    [[TMP2:%.*]] = load i32, ptr @_ZL3gs1, align 4
5683 // SIMD3-NEXT:    invoke void @_ZZ4mainEN5SmainC1Ei(ptr noundef nonnull align 8 dereferenceable(24) @_ZZ4mainE2sm, i32 noundef [[TMP2]])
5684 // SIMD3-NEXT:    to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]]
5685 // SIMD3:       invoke.cont:
5686 // SIMD3-NEXT:    [[TMP3:%.*]] = call i32 @__cxa_atexit(ptr @_ZZ4mainEN5SmainD1Ev, ptr @_ZZ4mainE2sm, ptr @__dso_handle) #[[ATTR3]]
5687 // SIMD3-NEXT:    call void @__cxa_guard_release(ptr @_ZGVZ4mainE2sm) #[[ATTR3]]
5688 // SIMD3-NEXT:    br label [[INIT_END]]
5689 // SIMD3:       init.end:
5690 // SIMD3-NEXT:    [[TMP4:%.*]] = load i32, ptr @_ZN6Static1sE, align 4
5691 // SIMD3-NEXT:    store i32 [[TMP4]], ptr [[RES]], align 4
5692 // SIMD3-NEXT:    [[TMP5:%.*]] = load i32, ptr @_ZZ4mainE2sm, align 8
5693 // SIMD3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[RES]], align 4
5694 // SIMD3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]]
5695 // SIMD3-NEXT:    store i32 [[ADD]], ptr [[RES]], align 4
5696 // SIMD3-NEXT:    [[TMP7:%.*]] = load i32, ptr @_ZL3gs1, align 4
5697 // SIMD3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[RES]], align 4
5698 // SIMD3-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP8]], [[TMP7]]
5699 // SIMD3-NEXT:    store i32 [[ADD1]], ptr [[RES]], align 4
5700 // SIMD3-NEXT:    [[TMP9:%.*]] = load i32, ptr @_ZL3gs2, align 8
5701 // SIMD3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[RES]], align 4
5702 // SIMD3-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]
5703 // SIMD3-NEXT:    store i32 [[ADD2]], ptr [[RES]], align 4
5704 // SIMD3-NEXT:    [[TMP11:%.*]] = load i32, ptr @gs3, align 4
5705 // SIMD3-NEXT:    [[TMP12:%.*]] = load i32, ptr [[RES]], align 4
5706 // SIMD3-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]]
5707 // SIMD3-NEXT:    store i32 [[ADD3]], ptr [[RES]], align 4
5708 // SIMD3-NEXT:    [[TMP13:%.*]] = load i32, ptr getelementptr inbounds ([2 x [3 x %struct.S1]], ptr @arr_x, i64 0, i64 1, i64 1), align 4
5709 // SIMD3-NEXT:    [[TMP14:%.*]] = load i32, ptr [[RES]], align 4
5710 // SIMD3-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP14]], [[TMP13]]
5711 // SIMD3-NEXT:    store i32 [[ADD4]], ptr [[RES]], align 4
5712 // SIMD3-NEXT:    [[TMP15:%.*]] = load i32, ptr @_ZN2STIiE2stE, align 4
5713 // SIMD3-NEXT:    [[TMP16:%.*]] = load i32, ptr [[RES]], align 4
5714 // SIMD3-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP16]], [[TMP15]]
5715 // SIMD3-NEXT:    store i32 [[ADD5]], ptr [[RES]], align 4
5716 // SIMD3-NEXT:    [[TMP17:%.*]] = load float, ptr @_ZN2STIfE2stE, align 4
5717 // SIMD3-NEXT:    [[CONV:%.*]] = fptosi float [[TMP17]] to i32
5718 // SIMD3-NEXT:    [[TMP18:%.*]] = load i32, ptr [[RES]], align 4
5719 // SIMD3-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP18]], [[CONV]]
5720 // SIMD3-NEXT:    store i32 [[ADD6]], ptr [[RES]], align 4
5721 // SIMD3-NEXT:    [[TMP19:%.*]] = load i32, ptr @_ZN2STI2S4E2stE, align 4
5722 // SIMD3-NEXT:    [[TMP20:%.*]] = load i32, ptr [[RES]], align 4
5723 // SIMD3-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP20]], [[TMP19]]
5724 // SIMD3-NEXT:    store i32 [[ADD7]], ptr [[RES]], align 4
5725 // SIMD3-NEXT:    [[TMP21:%.*]] = load i32, ptr [[RES]], align 4
5726 // SIMD3-NEXT:    ret i32 [[TMP21]]
5727 // SIMD3:       lpad:
5728 // SIMD3-NEXT:    [[TMP22:%.*]] = landingpad { ptr, i32 }
5729 // SIMD3-NEXT:    cleanup
5730 // SIMD3-NEXT:    [[TMP23:%.*]] = extractvalue { ptr, i32 } [[TMP22]], 0
5731 // SIMD3-NEXT:    store ptr [[TMP23]], ptr [[EXN_SLOT]], align 8
5732 // SIMD3-NEXT:    [[TMP24:%.*]] = extractvalue { ptr, i32 } [[TMP22]], 1
5733 // SIMD3-NEXT:    store i32 [[TMP24]], ptr [[EHSELECTOR_SLOT]], align 4
5734 // SIMD3-NEXT:    call void @__cxa_guard_abort(ptr @_ZGVZ4mainE2sm) #[[ATTR3]]
5735 // SIMD3-NEXT:    br label [[EH_RESUME:%.*]]
5736 // SIMD3:       eh.resume:
5737 // SIMD3-NEXT:    [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8
5738 // SIMD3-NEXT:    [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4
5739 // SIMD3-NEXT:    [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0
5740 // SIMD3-NEXT:    [[LPAD_VAL8:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1
5741 // SIMD3-NEXT:    resume { ptr, i32 } [[LPAD_VAL8]]
5742 //
5743 //
5744 // SIMD3-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC1Ei
5745 // SIMD3-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 {
5746 // SIMD3-NEXT:  entry:
5747 // SIMD3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
5748 // SIMD3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
5749 // SIMD3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
5750 // SIMD3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
5751 // SIMD3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
5752 // SIMD3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
5753 // SIMD3-NEXT:    call void @_ZZ4mainEN5SmainC2Ei(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]], i32 noundef [[TMP0]])
5754 // SIMD3-NEXT:    ret void
5755 //
5756 //
5757 // SIMD3-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD1Ev
5758 // SIMD3-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 {
5759 // SIMD3-NEXT:  entry:
5760 // SIMD3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
5761 // SIMD3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
5762 // SIMD3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
5763 // SIMD3-NEXT:    call void @_ZZ4mainEN5SmainD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR3]]
5764 // SIMD3-NEXT:    ret void
5765 //
5766 //
5767 // SIMD3-LABEL: define {{[^@]+}}@_Z6foobarv
5768 // SIMD3-SAME: () #[[ATTR5:[0-9]+]] {
5769 // SIMD3-NEXT:  entry:
5770 // SIMD3-NEXT:    [[RES:%.*]] = alloca i32, align 4
5771 // SIMD3-NEXT:    [[TMP0:%.*]] = load i32, ptr @_ZN6Static1sE, align 4
5772 // SIMD3-NEXT:    store i32 [[TMP0]], ptr [[RES]], align 4
5773 // SIMD3-NEXT:    [[TMP1:%.*]] = load i32, ptr @_ZL3gs1, align 4
5774 // SIMD3-NEXT:    [[TMP2:%.*]] = load i32, ptr [[RES]], align 4
5775 // SIMD3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP2]], [[TMP1]]
5776 // SIMD3-NEXT:    store i32 [[ADD]], ptr [[RES]], align 4
5777 // SIMD3-NEXT:    [[TMP3:%.*]] = load i32, ptr @_ZL3gs2, align 8
5778 // SIMD3-NEXT:    [[TMP4:%.*]] = load i32, ptr [[RES]], align 4
5779 // SIMD3-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP4]], [[TMP3]]
5780 // SIMD3-NEXT:    store i32 [[ADD1]], ptr [[RES]], align 4
5781 // SIMD3-NEXT:    [[TMP5:%.*]] = load i32, ptr @gs3, align 4
5782 // SIMD3-NEXT:    [[TMP6:%.*]] = load i32, ptr [[RES]], align 4
5783 // SIMD3-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP6]], [[TMP5]]
5784 // SIMD3-NEXT:    store i32 [[ADD2]], ptr [[RES]], align 4
5785 // SIMD3-NEXT:    [[TMP7:%.*]] = load i32, ptr getelementptr inbounds ([2 x [3 x %struct.S1]], ptr @arr_x, i64 0, i64 1, i64 1), align 4
5786 // SIMD3-NEXT:    [[TMP8:%.*]] = load i32, ptr [[RES]], align 4
5787 // SIMD3-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP8]], [[TMP7]]
5788 // SIMD3-NEXT:    store i32 [[ADD3]], ptr [[RES]], align 4
5789 // SIMD3-NEXT:    [[TMP9:%.*]] = load i32, ptr @_ZN2STIiE2stE, align 4
5790 // SIMD3-NEXT:    [[TMP10:%.*]] = load i32, ptr [[RES]], align 4
5791 // SIMD3-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP10]], [[TMP9]]
5792 // SIMD3-NEXT:    store i32 [[ADD4]], ptr [[RES]], align 4
5793 // SIMD3-NEXT:    [[TMP11:%.*]] = load float, ptr @_ZN2STIfE2stE, align 4
5794 // SIMD3-NEXT:    [[CONV:%.*]] = fptosi float [[TMP11]] to i32
5795 // SIMD3-NEXT:    [[TMP12:%.*]] = load i32, ptr [[RES]], align 4
5796 // SIMD3-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP12]], [[CONV]]
5797 // SIMD3-NEXT:    store i32 [[ADD5]], ptr [[RES]], align 4
5798 // SIMD3-NEXT:    [[TMP13:%.*]] = load i32, ptr @_ZN2STI2S4E2stE, align 4
5799 // SIMD3-NEXT:    [[TMP14:%.*]] = load i32, ptr [[RES]], align 4
5800 // SIMD3-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP14]], [[TMP13]]
5801 // SIMD3-NEXT:    store i32 [[ADD6]], ptr [[RES]], align 4
5802 // SIMD3-NEXT:    [[TMP15:%.*]] = load i32, ptr [[RES]], align 4
5803 // SIMD3-NEXT:    ret i32 [[TMP15]]
5804 //
5805 //
5806 // SIMD3-LABEL: define {{[^@]+}}@__cxx_global_var_init.3
5807 // SIMD3-SAME: () #[[ATTR0]] comdat($_ZN2STI2S4E2stE) {
5808 // SIMD3-NEXT:  entry:
5809 // SIMD3-NEXT:    [[TMP0:%.*]] = load i8, ptr @_ZGVN2STI2S4E2stE, align 8
5810 // SIMD3-NEXT:    [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0
5811 // SIMD3-NEXT:    br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]]
5812 // SIMD3:       init.check:
5813 // SIMD3-NEXT:    store i8 1, ptr @_ZGVN2STI2S4E2stE, align 8
5814 // SIMD3-NEXT:    call void @_ZN2S4C1Ei(ptr noundef nonnull align 4 dereferenceable(8) @_ZN2STI2S4E2stE, i32 noundef 23)
5815 // SIMD3-NEXT:    [[TMP1:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S4D1Ev, ptr @_ZN2STI2S4E2stE, ptr @__dso_handle) #[[ATTR3]]
5816 // SIMD3-NEXT:    br label [[INIT_END]]
5817 // SIMD3:       init.end:
5818 // SIMD3-NEXT:    ret void
5819 //
5820 //
5821 // SIMD3-LABEL: define {{[^@]+}}@_ZN2S4C1Ei
5822 // SIMD3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
5823 // SIMD3-NEXT:  entry:
5824 // SIMD3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
5825 // SIMD3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
5826 // SIMD3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
5827 // SIMD3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
5828 // SIMD3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
5829 // SIMD3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
5830 // SIMD3-NEXT:    call void @_ZN2S4C2Ei(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]], i32 noundef [[TMP0]])
5831 // SIMD3-NEXT:    ret void
5832 //
5833 //
5834 // SIMD3-LABEL: define {{[^@]+}}@_ZN2S4D1Ev
5835 // SIMD3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
5836 // SIMD3-NEXT:  entry:
5837 // SIMD3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
5838 // SIMD3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
5839 // SIMD3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
5840 // SIMD3-NEXT:    call void @_ZN2S4D2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR3]]
5841 // SIMD3-NEXT:    ret void
5842 //
5843 //
5844 // SIMD3-LABEL: define {{[^@]+}}@_ZN2S1C2Ei
5845 // SIMD3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
5846 // SIMD3-NEXT:  entry:
5847 // SIMD3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
5848 // SIMD3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
5849 // SIMD3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
5850 // SIMD3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
5851 // SIMD3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
5852 // SIMD3-NEXT:    [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0
5853 // SIMD3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
5854 // SIMD3-NEXT:    store i32 [[TMP0]], ptr [[A2]], align 4
5855 // SIMD3-NEXT:    ret void
5856 //
5857 //
5858 // SIMD3-LABEL: define {{[^@]+}}@_ZN2S1D2Ev
5859 // SIMD3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
5860 // SIMD3-NEXT:  entry:
5861 // SIMD3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
5862 // SIMD3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
5863 // SIMD3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
5864 // SIMD3-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0
5865 // SIMD3-NEXT:    store i32 0, ptr [[A]], align 4
5866 // SIMD3-NEXT:    ret void
5867 //
5868 //
5869 // SIMD3-LABEL: define {{[^@]+}}@_ZN2S2C2Ei
5870 // SIMD3-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
5871 // SIMD3-NEXT:  entry:
5872 // SIMD3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
5873 // SIMD3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
5874 // SIMD3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
5875 // SIMD3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
5876 // SIMD3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
5877 // SIMD3-NEXT:    [[A2:%.*]] = getelementptr inbounds [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0
5878 // SIMD3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
5879 // SIMD3-NEXT:    store i32 [[TMP0]], ptr [[A2]], align 8
5880 // SIMD3-NEXT:    ret void
5881 //
5882 //
5883 // SIMD3-LABEL: define {{[^@]+}}@_ZN2S2D2Ev
5884 // SIMD3-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
5885 // SIMD3-NEXT:  entry:
5886 // SIMD3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
5887 // SIMD3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
5888 // SIMD3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
5889 // SIMD3-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0
5890 // SIMD3-NEXT:    store i32 0, ptr [[A]], align 8
5891 // SIMD3-NEXT:    ret void
5892 //
5893 //
5894 // SIMD3-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC2Ei
5895 // SIMD3-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 {
5896 // SIMD3-NEXT:  entry:
5897 // SIMD3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
5898 // SIMD3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
5899 // SIMD3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
5900 // SIMD3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
5901 // SIMD3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
5902 // SIMD3-NEXT:    [[A2:%.*]] = getelementptr inbounds [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0
5903 // SIMD3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
5904 // SIMD3-NEXT:    store i32 [[TMP0]], ptr [[A2]], align 8
5905 // SIMD3-NEXT:    ret void
5906 //
5907 //
5908 // SIMD3-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD2Ev
5909 // SIMD3-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 {
5910 // SIMD3-NEXT:  entry:
5911 // SIMD3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
5912 // SIMD3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
5913 // SIMD3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
5914 // SIMD3-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0
5915 // SIMD3-NEXT:    store i32 0, ptr [[A]], align 8
5916 // SIMD3-NEXT:    ret void
5917 //
5918 //
5919 // SIMD3-LABEL: define {{[^@]+}}@_ZN2S4C2Ei
5920 // SIMD3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
5921 // SIMD3-NEXT:  entry:
5922 // SIMD3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
5923 // SIMD3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
5924 // SIMD3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
5925 // SIMD3-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
5926 // SIMD3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
5927 // SIMD3-NEXT:    [[A2:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0
5928 // SIMD3-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
5929 // SIMD3-NEXT:    store i32 [[TMP0]], ptr [[A2]], align 4
5930 // SIMD3-NEXT:    ret void
5931 //
5932 //
5933 // SIMD3-LABEL: define {{[^@]+}}@_ZN2S4D2Ev
5934 // SIMD3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
5935 // SIMD3-NEXT:  entry:
5936 // SIMD3-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
5937 // SIMD3-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
5938 // SIMD3-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
5939 // SIMD3-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0
5940 // SIMD3-NEXT:    store i32 0, ptr [[A]], align 4
5941 // SIMD3-NEXT:    ret void
5942 //
5943 //
5944 // SIMD3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_threadprivate_codegen.cpp
5945 // SIMD3-SAME: () #[[ATTR0]] {
5946 // SIMD3-NEXT:  entry:
5947 // SIMD3-NEXT:    call void @__cxx_global_var_init()
5948 // SIMD3-NEXT:    call void @__cxx_global_var_init.1()
5949 // SIMD3-NEXT:    call void @__cxx_global_var_init.2()
5950 // SIMD3-NEXT:    ret void
5951 //
5952 //
5953 // SIMD4-LABEL: define {{[^@]+}}@__cxx_global_var_init
5954 // SIMD4-SAME: () #[[ATTR0:[0-9]+]] !dbg [[DBG115:![0-9]+]] {
5955 // SIMD4-NEXT:  entry:
5956 // SIMD4-NEXT:    call void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @_ZL3gs1, i32 noundef 5), !dbg [[DBG119:![0-9]+]]
5957 // SIMD4-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S1D1Ev, ptr @_ZL3gs1, ptr @__dso_handle) #[[ATTR3:[0-9]+]], !dbg [[DBG121:![0-9]+]]
5958 // SIMD4-NEXT:    ret void, !dbg [[DBG122:![0-9]+]]
5959 //
5960 //
5961 // SIMD4-LABEL: define {{[^@]+}}@_ZN2S1C1Ei
5962 // SIMD4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 !dbg [[DBG123:![0-9]+]] {
5963 // SIMD4-NEXT:  entry:
5964 // SIMD4-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
5965 // SIMD4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
5966 // SIMD4-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
5967 // SIMD4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META124:![0-9]+]], metadata !DIExpression()), !dbg [[DBG126:![0-9]+]]
5968 // SIMD4-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
5969 // SIMD4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META127:![0-9]+]], metadata !DIExpression()), !dbg [[DBG128:![0-9]+]]
5970 // SIMD4-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
5971 // SIMD4-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG129:![0-9]+]]
5972 // SIMD4-NEXT:    call void @_ZN2S1C2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG129]]
5973 // SIMD4-NEXT:    ret void, !dbg [[DBG130:![0-9]+]]
5974 //
5975 //
5976 // SIMD4-LABEL: define {{[^@]+}}@_ZN2S1D1Ev
5977 // SIMD4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 !dbg [[DBG131:![0-9]+]] {
5978 // SIMD4-NEXT:  entry:
5979 // SIMD4-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
5980 // SIMD4-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
5981 // SIMD4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META132:![0-9]+]], metadata !DIExpression()), !dbg [[DBG133:![0-9]+]]
5982 // SIMD4-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
5983 // SIMD4-NEXT:    call void @_ZN2S1D2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]], !dbg [[DBG134:![0-9]+]]
5984 // SIMD4-NEXT:    ret void, !dbg [[DBG135:![0-9]+]]
5985 //
5986 //
5987 // SIMD4-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
5988 // SIMD4-SAME: () #[[ATTR0]] !dbg [[DBG136:![0-9]+]] {
5989 // SIMD4-NEXT:  entry:
5990 // SIMD4-NEXT:    call void @_ZN2S2C1Ei(ptr noundef nonnull align 8 dereferenceable(16) @_ZL3gs2, i32 noundef 27), !dbg [[DBG137:![0-9]+]]
5991 // SIMD4-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S2D1Ev, ptr @_ZL3gs2, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG139:![0-9]+]]
5992 // SIMD4-NEXT:    ret void, !dbg [[DBG140:![0-9]+]]
5993 //
5994 //
5995 // SIMD4-LABEL: define {{[^@]+}}@_ZN2S2C1Ei
5996 // SIMD4-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 !dbg [[DBG141:![0-9]+]] {
5997 // SIMD4-NEXT:  entry:
5998 // SIMD4-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
5999 // SIMD4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
6000 // SIMD4-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
6001 // SIMD4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META142:![0-9]+]], metadata !DIExpression()), !dbg [[DBG144:![0-9]+]]
6002 // SIMD4-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
6003 // SIMD4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META145:![0-9]+]], metadata !DIExpression()), !dbg [[DBG146:![0-9]+]]
6004 // SIMD4-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
6005 // SIMD4-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG147:![0-9]+]]
6006 // SIMD4-NEXT:    call void @_ZN2S2C2Ei(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG147]]
6007 // SIMD4-NEXT:    ret void, !dbg [[DBG148:![0-9]+]]
6008 //
6009 //
6010 // SIMD4-LABEL: define {{[^@]+}}@_ZN2S2D1Ev
6011 // SIMD4-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG149:![0-9]+]] {
6012 // SIMD4-NEXT:  entry:
6013 // SIMD4-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
6014 // SIMD4-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
6015 // SIMD4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META150:![0-9]+]], metadata !DIExpression()), !dbg [[DBG151:![0-9]+]]
6016 // SIMD4-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
6017 // SIMD4-NEXT:    call void @_ZN2S2D2Ev(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]]) #[[ATTR3]], !dbg [[DBG152:![0-9]+]]
6018 // SIMD4-NEXT:    ret void, !dbg [[DBG153:![0-9]+]]
6019 //
6020 //
6021 // SIMD4-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
6022 // SIMD4-SAME: () #[[ATTR0]] personality ptr @__gxx_personality_v0 !dbg [[DBG154:![0-9]+]] {
6023 // SIMD4-NEXT:  entry:
6024 // SIMD4-NEXT:    [[ARRAYINIT_ENDOFINIT:%.*]] = alloca ptr, align 8
6025 // SIMD4-NEXT:    [[ARRAYINIT_ENDOFINIT1:%.*]] = alloca ptr, align 8
6026 // SIMD4-NEXT:    [[EXN_SLOT:%.*]] = alloca ptr, align 8
6027 // SIMD4-NEXT:    [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4
6028 // SIMD4-NEXT:    [[ARRAYINIT_ENDOFINIT5:%.*]] = alloca ptr, align 8
6029 // SIMD4-NEXT:    store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG155:![0-9]+]]
6030 // SIMD4-NEXT:    store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG157:![0-9]+]]
6031 // SIMD4-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @arr_x, i32 noundef 1)
6032 // SIMD4-NEXT:    to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG158:![0-9]+]]
6033 // SIMD4:       invoke.cont:
6034 // SIMD4-NEXT:    store ptr getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG157]]
6035 // SIMD4-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 1), i32 noundef 2)
6036 // SIMD4-NEXT:    to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD]], !dbg [[DBG159:![0-9]+]]
6037 // SIMD4:       invoke.cont2:
6038 // SIMD4-NEXT:    store ptr getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG157]]
6039 // SIMD4-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), i32 noundef 3)
6040 // SIMD4-NEXT:    to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]], !dbg [[DBG160:![0-9]+]]
6041 // SIMD4:       invoke.cont3:
6042 // SIMD4-NEXT:    store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG155]]
6043 // SIMD4-NEXT:    store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG161:![0-9]+]]
6044 // SIMD4-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i32 noundef 4)
6045 // SIMD4-NEXT:    to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD6:%.*]], !dbg [[DBG162:![0-9]+]]
6046 // SIMD4:       invoke.cont7:
6047 // SIMD4-NEXT:    store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG161]]
6048 // SIMD4-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), i32 noundef 5)
6049 // SIMD4-NEXT:    to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD6]], !dbg [[DBG163:![0-9]+]]
6050 // SIMD4:       invoke.cont8:
6051 // SIMD4-NEXT:    store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG161]]
6052 // SIMD4-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), i32 noundef 6)
6053 // SIMD4-NEXT:    to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD6]], !dbg [[DBG164:![0-9]+]]
6054 // SIMD4:       invoke.cont9:
6055 // SIMD4-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG165:![0-9]+]]
6056 // SIMD4-NEXT:    ret void, !dbg [[DBG165]]
6057 // SIMD4:       lpad:
6058 // SIMD4-NEXT:    [[TMP1:%.*]] = landingpad { ptr, i32 }
6059 // SIMD4-NEXT:    cleanup, !dbg [[DBG166:![0-9]+]]
6060 // SIMD4-NEXT:    [[TMP2:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 0, !dbg [[DBG166]]
6061 // SIMD4-NEXT:    store ptr [[TMP2]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG166]]
6062 // SIMD4-NEXT:    [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 1, !dbg [[DBG166]]
6063 // SIMD4-NEXT:    store i32 [[TMP3]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG166]]
6064 // SIMD4-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG157]]
6065 // SIMD4-NEXT:    [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr @arr_x, [[TMP4]], !dbg [[DBG157]]
6066 // SIMD4-NEXT:    br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG157]]
6067 // SIMD4:       arraydestroy.body:
6068 // SIMD4-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP4]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG157]]
6069 // SIMD4-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG157]]
6070 // SIMD4-NEXT:    call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG157]]
6071 // SIMD4-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[DBG157]]
6072 // SIMD4-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG157]]
6073 // SIMD4:       arraydestroy.done4:
6074 // SIMD4-NEXT:    br label [[EHCLEANUP:%.*]], !dbg [[DBG157]]
6075 // SIMD4:       lpad6:
6076 // SIMD4-NEXT:    [[TMP5:%.*]] = landingpad { ptr, i32 }
6077 // SIMD4-NEXT:    cleanup, !dbg [[DBG166]]
6078 // SIMD4-NEXT:    [[TMP6:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 0, !dbg [[DBG166]]
6079 // SIMD4-NEXT:    store ptr [[TMP6]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG166]]
6080 // SIMD4-NEXT:    [[TMP7:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 1, !dbg [[DBG166]]
6081 // SIMD4-NEXT:    store i32 [[TMP7]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG166]]
6082 // SIMD4-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG161]]
6083 // SIMD4-NEXT:    [[ARRAYDESTROY_ISEMPTY10:%.*]] = icmp eq ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), [[TMP8]], !dbg [[DBG161]]
6084 // SIMD4-NEXT:    br i1 [[ARRAYDESTROY_ISEMPTY10]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY11:%.*]], !dbg [[DBG161]]
6085 // SIMD4:       arraydestroy.body11:
6086 // SIMD4-NEXT:    [[ARRAYDESTROY_ELEMENTPAST12:%.*]] = phi ptr [ [[TMP8]], [[LPAD6]] ], [ [[ARRAYDESTROY_ELEMENT13:%.*]], [[ARRAYDESTROY_BODY11]] ], !dbg [[DBG161]]
6087 // SIMD4-NEXT:    [[ARRAYDESTROY_ELEMENT13]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST12]], i64 -1, !dbg [[DBG161]]
6088 // SIMD4-NEXT:    call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR3]], !dbg [[DBG161]]
6089 // SIMD4-NEXT:    [[ARRAYDESTROY_DONE14:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), !dbg [[DBG161]]
6090 // SIMD4-NEXT:    br i1 [[ARRAYDESTROY_DONE14]], label [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_BODY11]], !dbg [[DBG161]]
6091 // SIMD4:       arraydestroy.done15:
6092 // SIMD4-NEXT:    br label [[EHCLEANUP]], !dbg [[DBG161]]
6093 // SIMD4:       ehcleanup:
6094 // SIMD4-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG155]]
6095 // SIMD4-NEXT:    [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP9]], i64 0, i64 0, !dbg [[DBG155]]
6096 // SIMD4-NEXT:    [[ARRAYDESTROY_ISEMPTY16:%.*]] = icmp eq ptr @arr_x, [[PAD_ARRAYEND]], !dbg [[DBG155]]
6097 // SIMD4-NEXT:    br i1 [[ARRAYDESTROY_ISEMPTY16]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17:%.*]], !dbg [[DBG155]]
6098 // SIMD4:       arraydestroy.body17:
6099 // SIMD4-NEXT:    [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi ptr [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ], !dbg [[DBG155]]
6100 // SIMD4-NEXT:    [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1, !dbg [[DBG155]]
6101 // SIMD4-NEXT:    call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]], !dbg [[DBG155]]
6102 // SIMD4-NEXT:    [[ARRAYDESTROY_DONE20:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT19]], @arr_x, !dbg [[DBG155]]
6103 // SIMD4-NEXT:    br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]], !dbg [[DBG155]]
6104 // SIMD4:       arraydestroy.done21:
6105 // SIMD4-NEXT:    br label [[EH_RESUME:%.*]], !dbg [[DBG155]]
6106 // SIMD4:       eh.resume:
6107 // SIMD4-NEXT:    [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG155]]
6108 // SIMD4-NEXT:    [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG155]]
6109 // SIMD4-NEXT:    [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG155]]
6110 // SIMD4-NEXT:    [[LPAD_VAL22:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG155]]
6111 // SIMD4-NEXT:    resume { ptr, i32 } [[LPAD_VAL22]], !dbg [[DBG155]]
6112 //
6113 //
6114 // SIMD4-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
6115 // SIMD4-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG167:![0-9]+]] {
6116 // SIMD4-NEXT:  entry:
6117 // SIMD4-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
6118 // SIMD4-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
6119 // SIMD4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[DOTADDR]], metadata [[META171:![0-9]+]], metadata !DIExpression()), !dbg [[DBG172:![0-9]+]]
6120 // SIMD4-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG172]]
6121 // SIMD4:       arraydestroy.body:
6122 // SIMD4-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 6), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG172]]
6123 // SIMD4-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG172]]
6124 // SIMD4-NEXT:    call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG172]]
6125 // SIMD4-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[DBG172]]
6126 // SIMD4-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG172]]
6127 // SIMD4:       arraydestroy.done1:
6128 // SIMD4-NEXT:    ret void, !dbg [[DBG172]]
6129 //
6130 //
6131 // SIMD4-LABEL: define {{[^@]+}}@main
6132 // SIMD4-SAME: () #[[ATTR5:[0-9]+]] personality ptr @__gxx_personality_v0 !dbg [[DBG52:![0-9]+]] {
6133 // SIMD4-NEXT:  entry:
6134 // SIMD4-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
6135 // SIMD4-NEXT:    [[RES:%.*]] = alloca i32, align 4
6136 // SIMD4-NEXT:    [[EXN_SLOT:%.*]] = alloca ptr, align 8
6137 // SIMD4-NEXT:    [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4
6138 // SIMD4-NEXT:    store i32 0, ptr [[RETVAL]], align 4
6139 // SIMD4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[RES]], metadata [[META173:![0-9]+]], metadata !DIExpression()), !dbg [[DBG174:![0-9]+]]
6140 // SIMD4-NEXT:    [[TMP0:%.*]] = load atomic i8, ptr @_ZGVZ4mainE2sm acquire, align 8, !dbg [[DBG175:![0-9]+]]
6141 // SIMD4-NEXT:    [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG175]]
6142 // SIMD4-NEXT:    br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG175]], !prof [[PROF176:![0-9]+]]
6143 // SIMD4:       init.check:
6144 // SIMD4-NEXT:    [[TMP1:%.*]] = call i32 @__cxa_guard_acquire(ptr @_ZGVZ4mainE2sm) #[[ATTR3]], !dbg [[DBG175]]
6145 // SIMD4-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0, !dbg [[DBG175]]
6146 // SIMD4-NEXT:    br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]], !dbg [[DBG175]]
6147 // SIMD4:       init:
6148 // SIMD4-NEXT:    [[TMP2:%.*]] = load i32, ptr @_ZL3gs1, align 4, !dbg [[DBG177:![0-9]+]]
6149 // SIMD4-NEXT:    invoke void @_ZZ4mainEN5SmainC1Ei(ptr noundef nonnull align 8 dereferenceable(24) @_ZZ4mainE2sm, i32 noundef [[TMP2]])
6150 // SIMD4-NEXT:    to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG178:![0-9]+]]
6151 // SIMD4:       invoke.cont:
6152 // SIMD4-NEXT:    [[TMP3:%.*]] = call i32 @__cxa_atexit(ptr @_ZZ4mainEN5SmainD1Ev, ptr @_ZZ4mainE2sm, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG175]]
6153 // SIMD4-NEXT:    call void @__cxa_guard_release(ptr @_ZGVZ4mainE2sm) #[[ATTR3]], !dbg [[DBG175]]
6154 // SIMD4-NEXT:    br label [[INIT_END]], !dbg [[DBG175]]
6155 // SIMD4:       init.end:
6156 // SIMD4-NEXT:    [[TMP4:%.*]] = load i32, ptr @_ZN6Static1sE, align 4, !dbg [[DBG179:![0-9]+]]
6157 // SIMD4-NEXT:    store i32 [[TMP4]], ptr [[RES]], align 4, !dbg [[DBG180:![0-9]+]]
6158 // SIMD4-NEXT:    [[TMP5:%.*]] = load i32, ptr @_ZZ4mainE2sm, align 8, !dbg [[DBG181:![0-9]+]]
6159 // SIMD4-NEXT:    [[TMP6:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG182:![0-9]+]]
6160 // SIMD4-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]], !dbg [[DBG182]]
6161 // SIMD4-NEXT:    store i32 [[ADD]], ptr [[RES]], align 4, !dbg [[DBG182]]
6162 // SIMD4-NEXT:    [[TMP7:%.*]] = load i32, ptr @_ZL3gs1, align 4, !dbg [[DBG183:![0-9]+]]
6163 // SIMD4-NEXT:    [[TMP8:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG184:![0-9]+]]
6164 // SIMD4-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP8]], [[TMP7]], !dbg [[DBG184]]
6165 // SIMD4-NEXT:    store i32 [[ADD1]], ptr [[RES]], align 4, !dbg [[DBG184]]
6166 // SIMD4-NEXT:    [[TMP9:%.*]] = load i32, ptr @_ZL3gs2, align 8, !dbg [[DBG185:![0-9]+]]
6167 // SIMD4-NEXT:    [[TMP10:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG186:![0-9]+]]
6168 // SIMD4-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP10]], [[TMP9]], !dbg [[DBG186]]
6169 // SIMD4-NEXT:    store i32 [[ADD2]], ptr [[RES]], align 4, !dbg [[DBG186]]
6170 // SIMD4-NEXT:    [[TMP11:%.*]] = load i32, ptr @gs3, align 4, !dbg [[DBG187:![0-9]+]]
6171 // SIMD4-NEXT:    [[TMP12:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG188:![0-9]+]]
6172 // SIMD4-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]], !dbg [[DBG188]]
6173 // SIMD4-NEXT:    store i32 [[ADD3]], ptr [[RES]], align 4, !dbg [[DBG188]]
6174 // SIMD4-NEXT:    [[TMP13:%.*]] = load i32, ptr getelementptr inbounds ([2 x [3 x %struct.S1]], ptr @arr_x, i64 0, i64 1, i64 1), align 4, !dbg [[DBG189:![0-9]+]]
6175 // SIMD4-NEXT:    [[TMP14:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG190:![0-9]+]]
6176 // SIMD4-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP14]], [[TMP13]], !dbg [[DBG190]]
6177 // SIMD4-NEXT:    store i32 [[ADD4]], ptr [[RES]], align 4, !dbg [[DBG190]]
6178 // SIMD4-NEXT:    [[TMP15:%.*]] = load i32, ptr @_ZN2STIiE2stE, align 4, !dbg [[DBG191:![0-9]+]]
6179 // SIMD4-NEXT:    [[TMP16:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG192:![0-9]+]]
6180 // SIMD4-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP16]], [[TMP15]], !dbg [[DBG192]]
6181 // SIMD4-NEXT:    store i32 [[ADD5]], ptr [[RES]], align 4, !dbg [[DBG192]]
6182 // SIMD4-NEXT:    [[TMP17:%.*]] = load float, ptr @_ZN2STIfE2stE, align 4, !dbg [[DBG193:![0-9]+]]
6183 // SIMD4-NEXT:    [[CONV:%.*]] = fptosi float [[TMP17]] to i32, !dbg [[DBG193]]
6184 // SIMD4-NEXT:    [[TMP18:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG194:![0-9]+]]
6185 // SIMD4-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP18]], [[CONV]], !dbg [[DBG194]]
6186 // SIMD4-NEXT:    store i32 [[ADD6]], ptr [[RES]], align 4, !dbg [[DBG194]]
6187 // SIMD4-NEXT:    [[TMP19:%.*]] = load i32, ptr @_ZN2STI2S4E2stE, align 4, !dbg [[DBG195:![0-9]+]]
6188 // SIMD4-NEXT:    [[TMP20:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG196:![0-9]+]]
6189 // SIMD4-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP20]], [[TMP19]], !dbg [[DBG196]]
6190 // SIMD4-NEXT:    store i32 [[ADD7]], ptr [[RES]], align 4, !dbg [[DBG196]]
6191 // SIMD4-NEXT:    [[TMP21:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG197:![0-9]+]]
6192 // SIMD4-NEXT:    ret i32 [[TMP21]], !dbg [[DBG198:![0-9]+]]
6193 // SIMD4:       lpad:
6194 // SIMD4-NEXT:    [[TMP22:%.*]] = landingpad { ptr, i32 }
6195 // SIMD4-NEXT:    cleanup, !dbg [[DBG199:![0-9]+]]
6196 // SIMD4-NEXT:    [[TMP23:%.*]] = extractvalue { ptr, i32 } [[TMP22]], 0, !dbg [[DBG199]]
6197 // SIMD4-NEXT:    store ptr [[TMP23]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG199]]
6198 // SIMD4-NEXT:    [[TMP24:%.*]] = extractvalue { ptr, i32 } [[TMP22]], 1, !dbg [[DBG199]]
6199 // SIMD4-NEXT:    store i32 [[TMP24]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG199]]
6200 // SIMD4-NEXT:    call void @__cxa_guard_abort(ptr @_ZGVZ4mainE2sm) #[[ATTR3]], !dbg [[DBG175]]
6201 // SIMD4-NEXT:    br label [[EH_RESUME:%.*]], !dbg [[DBG175]]
6202 // SIMD4:       eh.resume:
6203 // SIMD4-NEXT:    [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG175]]
6204 // SIMD4-NEXT:    [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG175]]
6205 // SIMD4-NEXT:    [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG175]]
6206 // SIMD4-NEXT:    [[LPAD_VAL8:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG175]]
6207 // SIMD4-NEXT:    resume { ptr, i32 } [[LPAD_VAL8]], !dbg [[DBG175]]
6208 //
6209 //
6210 // SIMD4-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC1Ei
6211 // SIMD4-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 !dbg [[DBG200:![0-9]+]] {
6212 // SIMD4-NEXT:  entry:
6213 // SIMD4-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
6214 // SIMD4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
6215 // SIMD4-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
6216 // SIMD4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META201:![0-9]+]], metadata !DIExpression()), !dbg [[DBG203:![0-9]+]]
6217 // SIMD4-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
6218 // SIMD4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META204:![0-9]+]], metadata !DIExpression()), !dbg [[DBG205:![0-9]+]]
6219 // SIMD4-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
6220 // SIMD4-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG206:![0-9]+]]
6221 // SIMD4-NEXT:    call void @_ZZ4mainEN5SmainC2Ei(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG206]]
6222 // SIMD4-NEXT:    ret void, !dbg [[DBG207:![0-9]+]]
6223 //
6224 //
6225 // SIMD4-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD1Ev
6226 // SIMD4-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG208:![0-9]+]] {
6227 // SIMD4-NEXT:  entry:
6228 // SIMD4-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
6229 // SIMD4-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
6230 // SIMD4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META209:![0-9]+]], metadata !DIExpression()), !dbg [[DBG210:![0-9]+]]
6231 // SIMD4-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
6232 // SIMD4-NEXT:    call void @_ZZ4mainEN5SmainD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR3]], !dbg [[DBG211:![0-9]+]]
6233 // SIMD4-NEXT:    ret void, !dbg [[DBG212:![0-9]+]]
6234 //
6235 //
6236 // SIMD4-LABEL: define {{[^@]+}}@_Z6foobarv
6237 // SIMD4-SAME: () #[[ATTR6:[0-9]+]] !dbg [[DBG213:![0-9]+]] {
6238 // SIMD4-NEXT:  entry:
6239 // SIMD4-NEXT:    [[RES:%.*]] = alloca i32, align 4
6240 // SIMD4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[RES]], metadata [[META214:![0-9]+]], metadata !DIExpression()), !dbg [[DBG215:![0-9]+]]
6241 // SIMD4-NEXT:    [[TMP0:%.*]] = load i32, ptr @_ZN6Static1sE, align 4, !dbg [[DBG216:![0-9]+]]
6242 // SIMD4-NEXT:    store i32 [[TMP0]], ptr [[RES]], align 4, !dbg [[DBG217:![0-9]+]]
6243 // SIMD4-NEXT:    [[TMP1:%.*]] = load i32, ptr @_ZL3gs1, align 4, !dbg [[DBG218:![0-9]+]]
6244 // SIMD4-NEXT:    [[TMP2:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG219:![0-9]+]]
6245 // SIMD4-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP2]], [[TMP1]], !dbg [[DBG219]]
6246 // SIMD4-NEXT:    store i32 [[ADD]], ptr [[RES]], align 4, !dbg [[DBG219]]
6247 // SIMD4-NEXT:    [[TMP3:%.*]] = load i32, ptr @_ZL3gs2, align 8, !dbg [[DBG220:![0-9]+]]
6248 // SIMD4-NEXT:    [[TMP4:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG221:![0-9]+]]
6249 // SIMD4-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP4]], [[TMP3]], !dbg [[DBG221]]
6250 // SIMD4-NEXT:    store i32 [[ADD1]], ptr [[RES]], align 4, !dbg [[DBG221]]
6251 // SIMD4-NEXT:    [[TMP5:%.*]] = load i32, ptr @gs3, align 4, !dbg [[DBG222:![0-9]+]]
6252 // SIMD4-NEXT:    [[TMP6:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG223:![0-9]+]]
6253 // SIMD4-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP6]], [[TMP5]], !dbg [[DBG223]]
6254 // SIMD4-NEXT:    store i32 [[ADD2]], ptr [[RES]], align 4, !dbg [[DBG223]]
6255 // SIMD4-NEXT:    [[TMP7:%.*]] = load i32, ptr getelementptr inbounds ([2 x [3 x %struct.S1]], ptr @arr_x, i64 0, i64 1, i64 1), align 4, !dbg [[DBG224:![0-9]+]]
6256 // SIMD4-NEXT:    [[TMP8:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG225:![0-9]+]]
6257 // SIMD4-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP8]], [[TMP7]], !dbg [[DBG225]]
6258 // SIMD4-NEXT:    store i32 [[ADD3]], ptr [[RES]], align 4, !dbg [[DBG225]]
6259 // SIMD4-NEXT:    [[TMP9:%.*]] = load i32, ptr @_ZN2STIiE2stE, align 4, !dbg [[DBG226:![0-9]+]]
6260 // SIMD4-NEXT:    [[TMP10:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG227:![0-9]+]]
6261 // SIMD4-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP10]], [[TMP9]], !dbg [[DBG227]]
6262 // SIMD4-NEXT:    store i32 [[ADD4]], ptr [[RES]], align 4, !dbg [[DBG227]]
6263 // SIMD4-NEXT:    [[TMP11:%.*]] = load float, ptr @_ZN2STIfE2stE, align 4, !dbg [[DBG228:![0-9]+]]
6264 // SIMD4-NEXT:    [[CONV:%.*]] = fptosi float [[TMP11]] to i32, !dbg [[DBG228]]
6265 // SIMD4-NEXT:    [[TMP12:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG229:![0-9]+]]
6266 // SIMD4-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP12]], [[CONV]], !dbg [[DBG229]]
6267 // SIMD4-NEXT:    store i32 [[ADD5]], ptr [[RES]], align 4, !dbg [[DBG229]]
6268 // SIMD4-NEXT:    [[TMP13:%.*]] = load i32, ptr @_ZN2STI2S4E2stE, align 4, !dbg [[DBG230:![0-9]+]]
6269 // SIMD4-NEXT:    [[TMP14:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG231:![0-9]+]]
6270 // SIMD4-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP14]], [[TMP13]], !dbg [[DBG231]]
6271 // SIMD4-NEXT:    store i32 [[ADD6]], ptr [[RES]], align 4, !dbg [[DBG231]]
6272 // SIMD4-NEXT:    [[TMP15:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG232:![0-9]+]]
6273 // SIMD4-NEXT:    ret i32 [[TMP15]], !dbg [[DBG233:![0-9]+]]
6274 //
6275 //
6276 // SIMD4-LABEL: define {{[^@]+}}@__cxx_global_var_init.3
6277 // SIMD4-SAME: () #[[ATTR0]] comdat($_ZN2STI2S4E2stE) !dbg [[DBG234:![0-9]+]] {
6278 // SIMD4-NEXT:  entry:
6279 // SIMD4-NEXT:    [[TMP0:%.*]] = load i8, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG235:![0-9]+]]
6280 // SIMD4-NEXT:    [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG235]]
6281 // SIMD4-NEXT:    br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG235]]
6282 // SIMD4:       init.check:
6283 // SIMD4-NEXT:    store i8 1, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG235]]
6284 // SIMD4-NEXT:    call void @_ZN2S4C1Ei(ptr noundef nonnull align 4 dereferenceable(8) @_ZN2STI2S4E2stE, i32 noundef 23), !dbg [[DBG236:![0-9]+]]
6285 // SIMD4-NEXT:    [[TMP1:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S4D1Ev, ptr @_ZN2STI2S4E2stE, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG235]]
6286 // SIMD4-NEXT:    br label [[INIT_END]], !dbg [[DBG235]]
6287 // SIMD4:       init.end:
6288 // SIMD4-NEXT:    ret void, !dbg [[DBG238:![0-9]+]]
6289 //
6290 //
6291 // SIMD4-LABEL: define {{[^@]+}}@_ZN2S4C1Ei
6292 // SIMD4-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 !dbg [[DBG239:![0-9]+]] {
6293 // SIMD4-NEXT:  entry:
6294 // SIMD4-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
6295 // SIMD4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
6296 // SIMD4-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
6297 // SIMD4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META240:![0-9]+]], metadata !DIExpression()), !dbg [[DBG242:![0-9]+]]
6298 // SIMD4-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
6299 // SIMD4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META243:![0-9]+]], metadata !DIExpression()), !dbg [[DBG244:![0-9]+]]
6300 // SIMD4-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
6301 // SIMD4-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG245:![0-9]+]]
6302 // SIMD4-NEXT:    call void @_ZN2S4C2Ei(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG245]]
6303 // SIMD4-NEXT:    ret void, !dbg [[DBG246:![0-9]+]]
6304 //
6305 //
6306 // SIMD4-LABEL: define {{[^@]+}}@_ZN2S4D1Ev
6307 // SIMD4-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG247:![0-9]+]] {
6308 // SIMD4-NEXT:  entry:
6309 // SIMD4-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
6310 // SIMD4-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
6311 // SIMD4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META248:![0-9]+]], metadata !DIExpression()), !dbg [[DBG249:![0-9]+]]
6312 // SIMD4-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
6313 // SIMD4-NEXT:    call void @_ZN2S4D2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR3]], !dbg [[DBG250:![0-9]+]]
6314 // SIMD4-NEXT:    ret void, !dbg [[DBG251:![0-9]+]]
6315 //
6316 //
6317 // SIMD4-LABEL: define {{[^@]+}}@_ZN2S1C2Ei
6318 // SIMD4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG252:![0-9]+]] {
6319 // SIMD4-NEXT:  entry:
6320 // SIMD4-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
6321 // SIMD4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
6322 // SIMD4-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
6323 // SIMD4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META253:![0-9]+]], metadata !DIExpression()), !dbg [[DBG254:![0-9]+]]
6324 // SIMD4-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
6325 // SIMD4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META255:![0-9]+]], metadata !DIExpression()), !dbg [[DBG256:![0-9]+]]
6326 // SIMD4-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
6327 // SIMD4-NEXT:    [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG257:![0-9]+]]
6328 // SIMD4-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG258:![0-9]+]]
6329 // SIMD4-NEXT:    store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG257]]
6330 // SIMD4-NEXT:    ret void, !dbg [[DBG259:![0-9]+]]
6331 //
6332 //
6333 // SIMD4-LABEL: define {{[^@]+}}@_ZN2S1D2Ev
6334 // SIMD4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG260:![0-9]+]] {
6335 // SIMD4-NEXT:  entry:
6336 // SIMD4-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
6337 // SIMD4-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
6338 // SIMD4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META261:![0-9]+]], metadata !DIExpression()), !dbg [[DBG262:![0-9]+]]
6339 // SIMD4-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
6340 // SIMD4-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG263:![0-9]+]]
6341 // SIMD4-NEXT:    store i32 0, ptr [[A]], align 4, !dbg [[DBG265:![0-9]+]]
6342 // SIMD4-NEXT:    ret void, !dbg [[DBG266:![0-9]+]]
6343 //
6344 //
6345 // SIMD4-LABEL: define {{[^@]+}}@_ZN2S2C2Ei
6346 // SIMD4-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG267:![0-9]+]] {
6347 // SIMD4-NEXT:  entry:
6348 // SIMD4-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
6349 // SIMD4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
6350 // SIMD4-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
6351 // SIMD4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META268:![0-9]+]], metadata !DIExpression()), !dbg [[DBG269:![0-9]+]]
6352 // SIMD4-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
6353 // SIMD4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META270:![0-9]+]], metadata !DIExpression()), !dbg [[DBG271:![0-9]+]]
6354 // SIMD4-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
6355 // SIMD4-NEXT:    [[A2:%.*]] = getelementptr inbounds [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG272:![0-9]+]]
6356 // SIMD4-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG273:![0-9]+]]
6357 // SIMD4-NEXT:    store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG272]]
6358 // SIMD4-NEXT:    ret void, !dbg [[DBG274:![0-9]+]]
6359 //
6360 //
6361 // SIMD4-LABEL: define {{[^@]+}}@_ZN2S2D2Ev
6362 // SIMD4-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG275:![0-9]+]] {
6363 // SIMD4-NEXT:  entry:
6364 // SIMD4-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
6365 // SIMD4-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
6366 // SIMD4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META276:![0-9]+]], metadata !DIExpression()), !dbg [[DBG277:![0-9]+]]
6367 // SIMD4-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
6368 // SIMD4-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG278:![0-9]+]]
6369 // SIMD4-NEXT:    store i32 0, ptr [[A]], align 8, !dbg [[DBG280:![0-9]+]]
6370 // SIMD4-NEXT:    ret void, !dbg [[DBG281:![0-9]+]]
6371 //
6372 //
6373 // SIMD4-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC2Ei
6374 // SIMD4-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG282:![0-9]+]] {
6375 // SIMD4-NEXT:  entry:
6376 // SIMD4-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
6377 // SIMD4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
6378 // SIMD4-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
6379 // SIMD4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META283:![0-9]+]], metadata !DIExpression()), !dbg [[DBG284:![0-9]+]]
6380 // SIMD4-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
6381 // SIMD4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META285:![0-9]+]], metadata !DIExpression()), !dbg [[DBG286:![0-9]+]]
6382 // SIMD4-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
6383 // SIMD4-NEXT:    [[A2:%.*]] = getelementptr inbounds [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG287:![0-9]+]]
6384 // SIMD4-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG288:![0-9]+]]
6385 // SIMD4-NEXT:    store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG287]]
6386 // SIMD4-NEXT:    ret void, !dbg [[DBG289:![0-9]+]]
6387 //
6388 //
6389 // SIMD4-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD2Ev
6390 // SIMD4-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG290:![0-9]+]] {
6391 // SIMD4-NEXT:  entry:
6392 // SIMD4-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
6393 // SIMD4-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
6394 // SIMD4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META291:![0-9]+]], metadata !DIExpression()), !dbg [[DBG292:![0-9]+]]
6395 // SIMD4-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
6396 // SIMD4-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG293:![0-9]+]]
6397 // SIMD4-NEXT:    store i32 0, ptr [[A]], align 8, !dbg [[DBG295:![0-9]+]]
6398 // SIMD4-NEXT:    ret void, !dbg [[DBG296:![0-9]+]]
6399 //
6400 //
6401 // SIMD4-LABEL: define {{[^@]+}}@_ZN2S4C2Ei
6402 // SIMD4-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG297:![0-9]+]] {
6403 // SIMD4-NEXT:  entry:
6404 // SIMD4-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
6405 // SIMD4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
6406 // SIMD4-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
6407 // SIMD4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META298:![0-9]+]], metadata !DIExpression()), !dbg [[DBG299:![0-9]+]]
6408 // SIMD4-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
6409 // SIMD4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META300:![0-9]+]], metadata !DIExpression()), !dbg [[DBG301:![0-9]+]]
6410 // SIMD4-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
6411 // SIMD4-NEXT:    [[A2:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG302:![0-9]+]]
6412 // SIMD4-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG303:![0-9]+]]
6413 // SIMD4-NEXT:    store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG302]]
6414 // SIMD4-NEXT:    ret void, !dbg [[DBG304:![0-9]+]]
6415 //
6416 //
6417 // SIMD4-LABEL: define {{[^@]+}}@_ZN2S4D2Ev
6418 // SIMD4-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG305:![0-9]+]] {
6419 // SIMD4-NEXT:  entry:
6420 // SIMD4-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
6421 // SIMD4-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
6422 // SIMD4-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META306:![0-9]+]], metadata !DIExpression()), !dbg [[DBG307:![0-9]+]]
6423 // SIMD4-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
6424 // SIMD4-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG308:![0-9]+]]
6425 // SIMD4-NEXT:    store i32 0, ptr [[A]], align 4, !dbg [[DBG310:![0-9]+]]
6426 // SIMD4-NEXT:    ret void, !dbg [[DBG311:![0-9]+]]
6427 //
6428 //
6429 // SIMD4-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_threadprivate_codegen.cpp
6430 // SIMD4-SAME: () #[[ATTR0]] !dbg [[DBG312:![0-9]+]] {
6431 // SIMD4-NEXT:  entry:
6432 // SIMD4-NEXT:    call void @__cxx_global_var_init(), !dbg [[DBG314:![0-9]+]]
6433 // SIMD4-NEXT:    call void @__cxx_global_var_init.1(), !dbg [[DBG314]]
6434 // SIMD4-NEXT:    call void @__cxx_global_var_init.2(), !dbg [[DBG314]]
6435 // SIMD4-NEXT:    ret void
6436 //
6437 //
6438 // DEBUG1-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_.
6439 // DEBUG1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0:[0-9]+]] !dbg [[DBG116:![0-9]+]] {
6440 // DEBUG1-NEXT:  entry:
6441 // DEBUG1-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
6442 // DEBUG1-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
6443 // DEBUG1-NEXT:    call void @llvm.dbg.declare(metadata ptr [[DOTADDR]], metadata [[META118:![0-9]+]], metadata !DIExpression()), !dbg [[DBG120:![0-9]+]]
6444 // DEBUG1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG121:![0-9]+]]
6445 // DEBUG1-NEXT:    call void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[TMP1]], i32 noundef 5), !dbg [[DBG122:![0-9]+]]
6446 // DEBUG1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG121]]
6447 // DEBUG1-NEXT:    ret ptr [[TMP2]], !dbg [[DBG121]]
6448 //
6449 //
6450 // DEBUG1-LABEL: define {{[^@]+}}@_ZN2S1C1Ei
6451 // DEBUG1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 !dbg [[DBG123:![0-9]+]] {
6452 // DEBUG1-NEXT:  entry:
6453 // DEBUG1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
6454 // DEBUG1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
6455 // DEBUG1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
6456 // DEBUG1-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META124:![0-9]+]], metadata !DIExpression()), !dbg [[DBG126:![0-9]+]]
6457 // DEBUG1-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
6458 // DEBUG1-NEXT:    call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META127:![0-9]+]], metadata !DIExpression()), !dbg [[DBG128:![0-9]+]]
6459 // DEBUG1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
6460 // DEBUG1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG129:![0-9]+]]
6461 // DEBUG1-NEXT:    call void @_ZN2S1C2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG129]]
6462 // DEBUG1-NEXT:    ret void, !dbg [[DBG130:![0-9]+]]
6463 //
6464 //
6465 // DEBUG1-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_.
6466 // DEBUG1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG131:![0-9]+]] {
6467 // DEBUG1-NEXT:  entry:
6468 // DEBUG1-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
6469 // DEBUG1-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
6470 // DEBUG1-NEXT:    call void @llvm.dbg.declare(metadata ptr [[DOTADDR]], metadata [[META132:![0-9]+]], metadata !DIExpression()), !dbg [[DBG133:![0-9]+]]
6471 // DEBUG1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG133]]
6472 // DEBUG1-NEXT:    call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP1]]) #[[ATTR4:[0-9]+]], !dbg [[DBG133]]
6473 // DEBUG1-NEXT:    ret void, !dbg [[DBG134:![0-9]+]]
6474 //
6475 //
6476 // DEBUG1-LABEL: define {{[^@]+}}@_ZN2S1D1Ev
6477 // DEBUG1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR3:[0-9]+]] comdat align 2 !dbg [[DBG135:![0-9]+]] {
6478 // DEBUG1-NEXT:  entry:
6479 // DEBUG1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
6480 // DEBUG1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
6481 // DEBUG1-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META136:![0-9]+]], metadata !DIExpression()), !dbg [[DBG137:![0-9]+]]
6482 // DEBUG1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
6483 // DEBUG1-NEXT:    call void @_ZN2S1D2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]], !dbg [[DBG138:![0-9]+]]
6484 // DEBUG1-NEXT:    ret void, !dbg [[DBG139:![0-9]+]]
6485 //
6486 //
6487 // DEBUG1-LABEL: define {{[^@]+}}@.__omp_threadprivate_init_.
6488 // DEBUG1-SAME: () #[[ATTR0]] !dbg [[DBG140:![0-9]+]] {
6489 // DEBUG1-NEXT:  entry:
6490 // DEBUG1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]]), !dbg [[DBG141:![0-9]+]]
6491 // DEBUG1-NEXT:    call void @__kmpc_threadprivate_register(ptr @[[GLOB1]], ptr @_ZL3gs1, ptr @.__kmpc_global_ctor_., ptr null, ptr @.__kmpc_global_dtor_.), !dbg [[DBG141]]
6492 // DEBUG1-NEXT:    ret void, !dbg [[DBG141]]
6493 //
6494 //
6495 // DEBUG1-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_..1
6496 // DEBUG1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] personality ptr @__gxx_personality_v0 !dbg [[DBG142:![0-9]+]] {
6497 // DEBUG1-NEXT:  entry:
6498 // DEBUG1-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
6499 // DEBUG1-NEXT:    [[ARRAYINIT_ENDOFINIT:%.*]] = alloca ptr, align 8
6500 // DEBUG1-NEXT:    [[ARRAYINIT_ENDOFINIT2:%.*]] = alloca ptr, align 8
6501 // DEBUG1-NEXT:    [[EXN_SLOT:%.*]] = alloca ptr, align 8
6502 // DEBUG1-NEXT:    [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4
6503 // DEBUG1-NEXT:    [[ARRAYINIT_ENDOFINIT9:%.*]] = alloca ptr, align 8
6504 // DEBUG1-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
6505 // DEBUG1-NEXT:    call void @llvm.dbg.declare(metadata ptr [[DOTADDR]], metadata [[META143:![0-9]+]], metadata !DIExpression()), !dbg [[DBG144:![0-9]+]]
6506 // DEBUG1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG145:![0-9]+]]
6507 // DEBUG1-NEXT:    [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP1]], i64 0, i64 0, !dbg [[DBG146:![0-9]+]]
6508 // DEBUG1-NEXT:    store ptr [[ARRAYINIT_BEGIN]], ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG146]]
6509 // DEBUG1-NEXT:    [[ARRAYINIT_BEGIN1:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYINIT_BEGIN]], i64 0, i64 0, !dbg [[DBG147:![0-9]+]]
6510 // DEBUG1-NEXT:    store ptr [[ARRAYINIT_BEGIN1]], ptr [[ARRAYINIT_ENDOFINIT2]], align 8, !dbg [[DBG147]]
6511 // DEBUG1-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN1]], i32 noundef 1)
6512 // DEBUG1-NEXT:    to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG148:![0-9]+]]
6513 // DEBUG1:       invoke.cont:
6514 // DEBUG1-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[ARRAYINIT_BEGIN1]], i64 1, !dbg [[DBG147]]
6515 // DEBUG1-NEXT:    store ptr [[ARRAYINIT_ELEMENT]], ptr [[ARRAYINIT_ENDOFINIT2]], align 8, !dbg [[DBG147]]
6516 // DEBUG1-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)
6517 // DEBUG1-NEXT:    to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]], !dbg [[DBG149:![0-9]+]]
6518 // DEBUG1:       invoke.cont3:
6519 // DEBUG1-NEXT:    [[ARRAYINIT_ELEMENT4:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYINIT_ELEMENT]], i64 1, !dbg [[DBG147]]
6520 // DEBUG1-NEXT:    store ptr [[ARRAYINIT_ELEMENT4]], ptr [[ARRAYINIT_ENDOFINIT2]], align 8, !dbg [[DBG147]]
6521 // DEBUG1-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT4]], i32 noundef 3)
6522 // DEBUG1-NEXT:    to label [[INVOKE_CONT5:%.*]] unwind label [[LPAD]], !dbg [[DBG150:![0-9]+]]
6523 // DEBUG1:       invoke.cont5:
6524 // DEBUG1-NEXT:    [[ARRAYINIT_ELEMENT7:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYINIT_BEGIN]], i64 1, !dbg [[DBG146]]
6525 // DEBUG1-NEXT:    store ptr [[ARRAYINIT_ELEMENT7]], ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG146]]
6526 // DEBUG1-NEXT:    [[ARRAYINIT_BEGIN8:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYINIT_ELEMENT7]], i64 0, i64 0, !dbg [[DBG151:![0-9]+]]
6527 // DEBUG1-NEXT:    store ptr [[ARRAYINIT_BEGIN8]], ptr [[ARRAYINIT_ENDOFINIT9]], align 8, !dbg [[DBG151]]
6528 // DEBUG1-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN8]], i32 noundef 4)
6529 // DEBUG1-NEXT:    to label [[INVOKE_CONT11:%.*]] unwind label [[LPAD10:%.*]], !dbg [[DBG152:![0-9]+]]
6530 // DEBUG1:       invoke.cont11:
6531 // DEBUG1-NEXT:    [[ARRAYINIT_ELEMENT12:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYINIT_BEGIN8]], i64 1, !dbg [[DBG151]]
6532 // DEBUG1-NEXT:    store ptr [[ARRAYINIT_ELEMENT12]], ptr [[ARRAYINIT_ENDOFINIT9]], align 8, !dbg [[DBG151]]
6533 // DEBUG1-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT12]], i32 noundef 5)
6534 // DEBUG1-NEXT:    to label [[INVOKE_CONT13:%.*]] unwind label [[LPAD10]], !dbg [[DBG153:![0-9]+]]
6535 // DEBUG1:       invoke.cont13:
6536 // DEBUG1-NEXT:    [[ARRAYINIT_ELEMENT14:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYINIT_ELEMENT12]], i64 1, !dbg [[DBG151]]
6537 // DEBUG1-NEXT:    store ptr [[ARRAYINIT_ELEMENT14]], ptr [[ARRAYINIT_ENDOFINIT9]], align 8, !dbg [[DBG151]]
6538 // DEBUG1-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT14]], i32 noundef 6)
6539 // DEBUG1-NEXT:    to label [[INVOKE_CONT15:%.*]] unwind label [[LPAD10]], !dbg [[DBG154:![0-9]+]]
6540 // DEBUG1:       invoke.cont15:
6541 // DEBUG1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG145]]
6542 // DEBUG1-NEXT:    ret ptr [[TMP2]], !dbg [[DBG145]]
6543 // DEBUG1:       lpad:
6544 // DEBUG1-NEXT:    [[TMP3:%.*]] = landingpad { ptr, i32 }
6545 // DEBUG1-NEXT:    cleanup, !dbg [[DBG144]]
6546 // DEBUG1-NEXT:    [[TMP4:%.*]] = extractvalue { ptr, i32 } [[TMP3]], 0, !dbg [[DBG144]]
6547 // DEBUG1-NEXT:    store ptr [[TMP4]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG144]]
6548 // DEBUG1-NEXT:    [[TMP5:%.*]] = extractvalue { ptr, i32 } [[TMP3]], 1, !dbg [[DBG144]]
6549 // DEBUG1-NEXT:    store i32 [[TMP5]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG144]]
6550 // DEBUG1-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT2]], align 8, !dbg [[DBG147]]
6551 // DEBUG1-NEXT:    [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAYINIT_BEGIN1]], [[TMP6]], !dbg [[DBG147]]
6552 // DEBUG1-NEXT:    br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG147]]
6553 // DEBUG1:       arraydestroy.body:
6554 // DEBUG1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP6]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG147]]
6555 // DEBUG1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG147]]
6556 // DEBUG1-NEXT:    call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]], !dbg [[DBG147]]
6557 // DEBUG1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAYINIT_BEGIN1]], !dbg [[DBG147]]
6558 // DEBUG1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG147]]
6559 // DEBUG1:       arraydestroy.done6:
6560 // DEBUG1-NEXT:    br label [[EHCLEANUP:%.*]], !dbg [[DBG147]]
6561 // DEBUG1:       lpad10:
6562 // DEBUG1-NEXT:    [[TMP7:%.*]] = landingpad { ptr, i32 }
6563 // DEBUG1-NEXT:    cleanup, !dbg [[DBG144]]
6564 // DEBUG1-NEXT:    [[TMP8:%.*]] = extractvalue { ptr, i32 } [[TMP7]], 0, !dbg [[DBG144]]
6565 // DEBUG1-NEXT:    store ptr [[TMP8]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG144]]
6566 // DEBUG1-NEXT:    [[TMP9:%.*]] = extractvalue { ptr, i32 } [[TMP7]], 1, !dbg [[DBG144]]
6567 // DEBUG1-NEXT:    store i32 [[TMP9]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG144]]
6568 // DEBUG1-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT9]], align 8, !dbg [[DBG151]]
6569 // DEBUG1-NEXT:    [[ARRAYDESTROY_ISEMPTY16:%.*]] = icmp eq ptr [[ARRAYINIT_BEGIN8]], [[TMP10]], !dbg [[DBG151]]
6570 // DEBUG1-NEXT:    br i1 [[ARRAYDESTROY_ISEMPTY16]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17:%.*]], !dbg [[DBG151]]
6571 // DEBUG1:       arraydestroy.body17:
6572 // DEBUG1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi ptr [ [[TMP10]], [[LPAD10]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ], !dbg [[DBG151]]
6573 // DEBUG1-NEXT:    [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1, !dbg [[DBG151]]
6574 // DEBUG1-NEXT:    call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR4]], !dbg [[DBG151]]
6575 // DEBUG1-NEXT:    [[ARRAYDESTROY_DONE20:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT19]], [[ARRAYINIT_BEGIN8]], !dbg [[DBG151]]
6576 // DEBUG1-NEXT:    br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]], !dbg [[DBG151]]
6577 // DEBUG1:       arraydestroy.done21:
6578 // DEBUG1-NEXT:    br label [[EHCLEANUP]], !dbg [[DBG151]]
6579 // DEBUG1:       ehcleanup:
6580 // DEBUG1-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG146]]
6581 // DEBUG1-NEXT:    [[PAD_ARRAYBEGIN:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYINIT_BEGIN]], i64 0, i64 0, !dbg [[DBG146]]
6582 // DEBUG1-NEXT:    [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP11]], i64 0, i64 0, !dbg [[DBG146]]
6583 // DEBUG1-NEXT:    [[ARRAYDESTROY_ISEMPTY22:%.*]] = icmp eq ptr [[PAD_ARRAYBEGIN]], [[PAD_ARRAYEND]], !dbg [[DBG146]]
6584 // DEBUG1-NEXT:    br i1 [[ARRAYDESTROY_ISEMPTY22]], label [[ARRAYDESTROY_DONE27:%.*]], label [[ARRAYDESTROY_BODY23:%.*]], !dbg [[DBG146]]
6585 // DEBUG1:       arraydestroy.body23:
6586 // DEBUG1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST24:%.*]] = phi ptr [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT25:%.*]], [[ARRAYDESTROY_BODY23]] ], !dbg [[DBG146]]
6587 // DEBUG1-NEXT:    [[ARRAYDESTROY_ELEMENT25]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST24]], i64 -1, !dbg [[DBG146]]
6588 // DEBUG1-NEXT:    call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT25]]) #[[ATTR4]], !dbg [[DBG146]]
6589 // DEBUG1-NEXT:    [[ARRAYDESTROY_DONE26:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT25]], [[PAD_ARRAYBEGIN]], !dbg [[DBG146]]
6590 // DEBUG1-NEXT:    br i1 [[ARRAYDESTROY_DONE26]], label [[ARRAYDESTROY_DONE27]], label [[ARRAYDESTROY_BODY23]], !dbg [[DBG146]]
6591 // DEBUG1:       arraydestroy.done27:
6592 // DEBUG1-NEXT:    br label [[EH_RESUME:%.*]], !dbg [[DBG146]]
6593 // DEBUG1:       eh.resume:
6594 // DEBUG1-NEXT:    [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG146]]
6595 // DEBUG1-NEXT:    [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG146]]
6596 // DEBUG1-NEXT:    [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG146]]
6597 // DEBUG1-NEXT:    [[LPAD_VAL28:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG146]]
6598 // DEBUG1-NEXT:    resume { ptr, i32 } [[LPAD_VAL28]], !dbg [[DBG146]]
6599 //
6600 //
6601 // DEBUG1-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_..2
6602 // DEBUG1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG155:![0-9]+]] {
6603 // DEBUG1-NEXT:  entry:
6604 // DEBUG1-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
6605 // DEBUG1-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
6606 // DEBUG1-NEXT:    call void @llvm.dbg.declare(metadata ptr [[DOTADDR]], metadata [[META156:![0-9]+]], metadata !DIExpression()), !dbg [[DBG157:![0-9]+]]
6607 // DEBUG1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG157]]
6608 // DEBUG1-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP1]], i64 6, !dbg [[DBG157]]
6609 // DEBUG1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG157]]
6610 // DEBUG1:       arraydestroy.body:
6611 // DEBUG1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG157]]
6612 // DEBUG1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG157]]
6613 // DEBUG1-NEXT:    call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]], !dbg [[DBG157]]
6614 // DEBUG1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[TMP1]], !dbg [[DBG157]]
6615 // DEBUG1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG157]]
6616 // DEBUG1:       arraydestroy.done1:
6617 // DEBUG1-NEXT:    ret void, !dbg [[DBG158:![0-9]+]]
6618 //
6619 //
6620 // DEBUG1-LABEL: define {{[^@]+}}@.__omp_threadprivate_init_..3
6621 // DEBUG1-SAME: () #[[ATTR0]] !dbg [[DBG159:![0-9]+]] {
6622 // DEBUG1-NEXT:  entry:
6623 // DEBUG1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3:[0-9]+]]), !dbg [[DBG160:![0-9]+]]
6624 // DEBUG1-NEXT:    call void @__kmpc_threadprivate_register(ptr @[[GLOB3]], ptr @arr_x, ptr @.__kmpc_global_ctor_..1, ptr null, ptr @.__kmpc_global_dtor_..2), !dbg [[DBG160]]
6625 // DEBUG1-NEXT:    ret void, !dbg [[DBG160]]
6626 //
6627 //
6628 // DEBUG1-LABEL: define {{[^@]+}}@__cxx_global_var_init
6629 // DEBUG1-SAME: () #[[ATTR0]] !dbg [[DBG161:![0-9]+]] {
6630 // DEBUG1-NEXT:  entry:
6631 // DEBUG1-NEXT:    call void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @_ZL3gs1, i32 noundef 5), !dbg [[DBG165:![0-9]+]]
6632 // DEBUG1-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S1D1Ev, ptr @_ZL3gs1, ptr @__dso_handle) #[[ATTR4]], !dbg [[DBG167:![0-9]+]]
6633 // DEBUG1-NEXT:    ret void, !dbg [[DBG168:![0-9]+]]
6634 //
6635 //
6636 // DEBUG1-LABEL: define {{[^@]+}}@_ZN2S1C2Ei
6637 // DEBUG1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG169:![0-9]+]] {
6638 // DEBUG1-NEXT:  entry:
6639 // DEBUG1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
6640 // DEBUG1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
6641 // DEBUG1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
6642 // DEBUG1-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META170:![0-9]+]], metadata !DIExpression()), !dbg [[DBG171:![0-9]+]]
6643 // DEBUG1-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
6644 // DEBUG1-NEXT:    call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META172:![0-9]+]], metadata !DIExpression()), !dbg [[DBG173:![0-9]+]]
6645 // DEBUG1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
6646 // DEBUG1-NEXT:    [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG174:![0-9]+]]
6647 // DEBUG1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG175:![0-9]+]]
6648 // DEBUG1-NEXT:    store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG174]]
6649 // DEBUG1-NEXT:    ret void, !dbg [[DBG176:![0-9]+]]
6650 //
6651 //
6652 // DEBUG1-LABEL: define {{[^@]+}}@_ZN2S1D2Ev
6653 // DEBUG1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG177:![0-9]+]] {
6654 // DEBUG1-NEXT:  entry:
6655 // DEBUG1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
6656 // DEBUG1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
6657 // DEBUG1-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META178:![0-9]+]], metadata !DIExpression()), !dbg [[DBG179:![0-9]+]]
6658 // DEBUG1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
6659 // DEBUG1-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG180:![0-9]+]]
6660 // DEBUG1-NEXT:    store i32 0, ptr [[A]], align 4, !dbg [[DBG182:![0-9]+]]
6661 // DEBUG1-NEXT:    ret void, !dbg [[DBG183:![0-9]+]]
6662 //
6663 //
6664 // DEBUG1-LABEL: define {{[^@]+}}@__cxx_global_var_init.4
6665 // DEBUG1-SAME: () #[[ATTR0]] !dbg [[DBG184:![0-9]+]] {
6666 // DEBUG1-NEXT:  entry:
6667 // DEBUG1-NEXT:    call void @_ZN2S2C1Ei(ptr noundef nonnull align 8 dereferenceable(16) @_ZL3gs2, i32 noundef 27), !dbg [[DBG185:![0-9]+]]
6668 // DEBUG1-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S2D1Ev, ptr @_ZL3gs2, ptr @__dso_handle) #[[ATTR4]], !dbg [[DBG187:![0-9]+]]
6669 // DEBUG1-NEXT:    ret void, !dbg [[DBG188:![0-9]+]]
6670 //
6671 //
6672 // DEBUG1-LABEL: define {{[^@]+}}@_ZN2S2C1Ei
6673 // DEBUG1-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG189:![0-9]+]] {
6674 // DEBUG1-NEXT:  entry:
6675 // DEBUG1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
6676 // DEBUG1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
6677 // DEBUG1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
6678 // DEBUG1-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META190:![0-9]+]], metadata !DIExpression()), !dbg [[DBG192:![0-9]+]]
6679 // DEBUG1-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
6680 // DEBUG1-NEXT:    call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META193:![0-9]+]], metadata !DIExpression()), !dbg [[DBG194:![0-9]+]]
6681 // DEBUG1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
6682 // DEBUG1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG195:![0-9]+]]
6683 // DEBUG1-NEXT:    call void @_ZN2S2C2Ei(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG195]]
6684 // DEBUG1-NEXT:    ret void, !dbg [[DBG196:![0-9]+]]
6685 //
6686 //
6687 // DEBUG1-LABEL: define {{[^@]+}}@_ZN2S2D1Ev
6688 // DEBUG1-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG197:![0-9]+]] {
6689 // DEBUG1-NEXT:  entry:
6690 // DEBUG1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
6691 // DEBUG1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
6692 // DEBUG1-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META198:![0-9]+]], metadata !DIExpression()), !dbg [[DBG199:![0-9]+]]
6693 // DEBUG1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
6694 // DEBUG1-NEXT:    call void @_ZN2S2D2Ev(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]]) #[[ATTR4]], !dbg [[DBG200:![0-9]+]]
6695 // DEBUG1-NEXT:    ret void, !dbg [[DBG201:![0-9]+]]
6696 //
6697 //
6698 // DEBUG1-LABEL: define {{[^@]+}}@_ZN2S2C2Ei
6699 // DEBUG1-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG202:![0-9]+]] {
6700 // DEBUG1-NEXT:  entry:
6701 // DEBUG1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
6702 // DEBUG1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
6703 // DEBUG1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
6704 // DEBUG1-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META203:![0-9]+]], metadata !DIExpression()), !dbg [[DBG204:![0-9]+]]
6705 // DEBUG1-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
6706 // DEBUG1-NEXT:    call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META205:![0-9]+]], metadata !DIExpression()), !dbg [[DBG206:![0-9]+]]
6707 // DEBUG1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
6708 // DEBUG1-NEXT:    [[A2:%.*]] = getelementptr inbounds [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG207:![0-9]+]]
6709 // DEBUG1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG208:![0-9]+]]
6710 // DEBUG1-NEXT:    store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG207]]
6711 // DEBUG1-NEXT:    ret void, !dbg [[DBG209:![0-9]+]]
6712 //
6713 //
6714 // DEBUG1-LABEL: define {{[^@]+}}@_ZN2S2D2Ev
6715 // DEBUG1-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG210:![0-9]+]] {
6716 // DEBUG1-NEXT:  entry:
6717 // DEBUG1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
6718 // DEBUG1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
6719 // DEBUG1-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META211:![0-9]+]], metadata !DIExpression()), !dbg [[DBG212:![0-9]+]]
6720 // DEBUG1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
6721 // DEBUG1-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG213:![0-9]+]]
6722 // DEBUG1-NEXT:    store i32 0, ptr [[A]], align 8, !dbg [[DBG215:![0-9]+]]
6723 // DEBUG1-NEXT:    ret void, !dbg [[DBG216:![0-9]+]]
6724 //
6725 //
6726 // DEBUG1-LABEL: define {{[^@]+}}@__cxx_global_var_init.5
6727 // DEBUG1-SAME: () #[[ATTR0]] personality ptr @__gxx_personality_v0 !dbg [[DBG217:![0-9]+]] {
6728 // DEBUG1-NEXT:  entry:
6729 // DEBUG1-NEXT:    [[ARRAYINIT_ENDOFINIT:%.*]] = alloca ptr, align 8
6730 // DEBUG1-NEXT:    [[ARRAYINIT_ENDOFINIT1:%.*]] = alloca ptr, align 8
6731 // DEBUG1-NEXT:    [[EXN_SLOT:%.*]] = alloca ptr, align 8
6732 // DEBUG1-NEXT:    [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4
6733 // DEBUG1-NEXT:    [[ARRAYINIT_ENDOFINIT5:%.*]] = alloca ptr, align 8
6734 // DEBUG1-NEXT:    store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG218:![0-9]+]]
6735 // DEBUG1-NEXT:    store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG220:![0-9]+]]
6736 // DEBUG1-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @arr_x, i32 noundef 1)
6737 // DEBUG1-NEXT:    to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG221:![0-9]+]]
6738 // DEBUG1:       invoke.cont:
6739 // DEBUG1-NEXT:    store ptr getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG220]]
6740 // DEBUG1-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 1), i32 noundef 2)
6741 // DEBUG1-NEXT:    to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD]], !dbg [[DBG222:![0-9]+]]
6742 // DEBUG1:       invoke.cont2:
6743 // DEBUG1-NEXT:    store ptr getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG220]]
6744 // DEBUG1-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), i32 noundef 3)
6745 // DEBUG1-NEXT:    to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]], !dbg [[DBG223:![0-9]+]]
6746 // DEBUG1:       invoke.cont3:
6747 // DEBUG1-NEXT:    store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG218]]
6748 // DEBUG1-NEXT:    store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG224:![0-9]+]]
6749 // DEBUG1-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i32 noundef 4)
6750 // DEBUG1-NEXT:    to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD6:%.*]], !dbg [[DBG225:![0-9]+]]
6751 // DEBUG1:       invoke.cont7:
6752 // DEBUG1-NEXT:    store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG224]]
6753 // DEBUG1-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), i32 noundef 5)
6754 // DEBUG1-NEXT:    to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD6]], !dbg [[DBG226:![0-9]+]]
6755 // DEBUG1:       invoke.cont8:
6756 // DEBUG1-NEXT:    store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG224]]
6757 // DEBUG1-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), i32 noundef 6)
6758 // DEBUG1-NEXT:    to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD6]], !dbg [[DBG227:![0-9]+]]
6759 // DEBUG1:       invoke.cont9:
6760 // DEBUG1-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR4]], !dbg [[DBG228:![0-9]+]]
6761 // DEBUG1-NEXT:    ret void, !dbg [[DBG228]]
6762 // DEBUG1:       lpad:
6763 // DEBUG1-NEXT:    [[TMP1:%.*]] = landingpad { ptr, i32 }
6764 // DEBUG1-NEXT:    cleanup, !dbg [[DBG229:![0-9]+]]
6765 // DEBUG1-NEXT:    [[TMP2:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 0, !dbg [[DBG229]]
6766 // DEBUG1-NEXT:    store ptr [[TMP2]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG229]]
6767 // DEBUG1-NEXT:    [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 1, !dbg [[DBG229]]
6768 // DEBUG1-NEXT:    store i32 [[TMP3]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG229]]
6769 // DEBUG1-NEXT:    [[TMP4:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG220]]
6770 // DEBUG1-NEXT:    [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr @arr_x, [[TMP4]], !dbg [[DBG220]]
6771 // DEBUG1-NEXT:    br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG220]]
6772 // DEBUG1:       arraydestroy.body:
6773 // DEBUG1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP4]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG220]]
6774 // DEBUG1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG220]]
6775 // DEBUG1-NEXT:    call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]], !dbg [[DBG220]]
6776 // DEBUG1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[DBG220]]
6777 // DEBUG1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG220]]
6778 // DEBUG1:       arraydestroy.done4:
6779 // DEBUG1-NEXT:    br label [[EHCLEANUP:%.*]], !dbg [[DBG220]]
6780 // DEBUG1:       lpad6:
6781 // DEBUG1-NEXT:    [[TMP5:%.*]] = landingpad { ptr, i32 }
6782 // DEBUG1-NEXT:    cleanup, !dbg [[DBG229]]
6783 // DEBUG1-NEXT:    [[TMP6:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 0, !dbg [[DBG229]]
6784 // DEBUG1-NEXT:    store ptr [[TMP6]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG229]]
6785 // DEBUG1-NEXT:    [[TMP7:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 1, !dbg [[DBG229]]
6786 // DEBUG1-NEXT:    store i32 [[TMP7]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG229]]
6787 // DEBUG1-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG224]]
6788 // DEBUG1-NEXT:    [[ARRAYDESTROY_ISEMPTY10:%.*]] = icmp eq ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), [[TMP8]], !dbg [[DBG224]]
6789 // DEBUG1-NEXT:    br i1 [[ARRAYDESTROY_ISEMPTY10]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY11:%.*]], !dbg [[DBG224]]
6790 // DEBUG1:       arraydestroy.body11:
6791 // DEBUG1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST12:%.*]] = phi ptr [ [[TMP8]], [[LPAD6]] ], [ [[ARRAYDESTROY_ELEMENT13:%.*]], [[ARRAYDESTROY_BODY11]] ], !dbg [[DBG224]]
6792 // DEBUG1-NEXT:    [[ARRAYDESTROY_ELEMENT13]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST12]], i64 -1, !dbg [[DBG224]]
6793 // DEBUG1-NEXT:    call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR4]], !dbg [[DBG224]]
6794 // DEBUG1-NEXT:    [[ARRAYDESTROY_DONE14:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), !dbg [[DBG224]]
6795 // DEBUG1-NEXT:    br i1 [[ARRAYDESTROY_DONE14]], label [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_BODY11]], !dbg [[DBG224]]
6796 // DEBUG1:       arraydestroy.done15:
6797 // DEBUG1-NEXT:    br label [[EHCLEANUP]], !dbg [[DBG224]]
6798 // DEBUG1:       ehcleanup:
6799 // DEBUG1-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG218]]
6800 // DEBUG1-NEXT:    [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP9]], i64 0, i64 0, !dbg [[DBG218]]
6801 // DEBUG1-NEXT:    [[ARRAYDESTROY_ISEMPTY16:%.*]] = icmp eq ptr @arr_x, [[PAD_ARRAYEND]], !dbg [[DBG218]]
6802 // DEBUG1-NEXT:    br i1 [[ARRAYDESTROY_ISEMPTY16]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17:%.*]], !dbg [[DBG218]]
6803 // DEBUG1:       arraydestroy.body17:
6804 // DEBUG1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi ptr [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ], !dbg [[DBG218]]
6805 // DEBUG1-NEXT:    [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1, !dbg [[DBG218]]
6806 // DEBUG1-NEXT:    call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR4]], !dbg [[DBG218]]
6807 // DEBUG1-NEXT:    [[ARRAYDESTROY_DONE20:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT19]], @arr_x, !dbg [[DBG218]]
6808 // DEBUG1-NEXT:    br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]], !dbg [[DBG218]]
6809 // DEBUG1:       arraydestroy.done21:
6810 // DEBUG1-NEXT:    br label [[EH_RESUME:%.*]], !dbg [[DBG218]]
6811 // DEBUG1:       eh.resume:
6812 // DEBUG1-NEXT:    [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG218]]
6813 // DEBUG1-NEXT:    [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG218]]
6814 // DEBUG1-NEXT:    [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG218]]
6815 // DEBUG1-NEXT:    [[LPAD_VAL22:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG218]]
6816 // DEBUG1-NEXT:    resume { ptr, i32 } [[LPAD_VAL22]], !dbg [[DBG218]]
6817 //
6818 //
6819 // DEBUG1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
6820 // DEBUG1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG230:![0-9]+]] {
6821 // DEBUG1-NEXT:  entry:
6822 // DEBUG1-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
6823 // DEBUG1-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
6824 // DEBUG1-NEXT:    call void @llvm.dbg.declare(metadata ptr [[DOTADDR]], metadata [[META233:![0-9]+]], metadata !DIExpression()), !dbg [[DBG234:![0-9]+]]
6825 // DEBUG1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG234]]
6826 // DEBUG1:       arraydestroy.body:
6827 // DEBUG1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 6), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG234]]
6828 // DEBUG1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG234]]
6829 // DEBUG1-NEXT:    call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]], !dbg [[DBG234]]
6830 // DEBUG1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[DBG234]]
6831 // DEBUG1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG234]]
6832 // DEBUG1:       arraydestroy.done1:
6833 // DEBUG1-NEXT:    ret void, !dbg [[DBG234]]
6834 //
6835 //
6836 // DEBUG1-LABEL: define {{[^@]+}}@main
6837 // DEBUG1-SAME: () #[[ATTR5:[0-9]+]] personality ptr @__gxx_personality_v0 !dbg [[DBG52:![0-9]+]] {
6838 // DEBUG1-NEXT:  entry:
6839 // DEBUG1-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
6840 // DEBUG1-NEXT:    [[RES:%.*]] = alloca i32, align 4
6841 // DEBUG1-NEXT:    [[EXN_SLOT:%.*]] = alloca ptr, align 8
6842 // DEBUG1-NEXT:    [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4
6843 // DEBUG1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB9:[0-9]+]])
6844 // DEBUG1-NEXT:    store i32 0, ptr [[RETVAL]], align 4
6845 // DEBUG1-NEXT:    call void @llvm.dbg.declare(metadata ptr [[RES]], metadata [[META235:![0-9]+]], metadata !DIExpression()), !dbg [[DBG236:![0-9]+]]
6846 // DEBUG1-NEXT:    [[TMP1:%.*]] = load atomic i8, ptr @_ZGVZ4mainE2sm acquire, align 8, !dbg [[DBG237:![0-9]+]]
6847 // DEBUG1-NEXT:    [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP1]], 0, !dbg [[DBG237]]
6848 // DEBUG1-NEXT:    br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG237]], !prof [[PROF238:![0-9]+]]
6849 // DEBUG1:       init.check:
6850 // DEBUG1-NEXT:    [[TMP2:%.*]] = call i32 @__cxa_guard_acquire(ptr @_ZGVZ4mainE2sm) #[[ATTR4]], !dbg [[DBG237]]
6851 // DEBUG1-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0, !dbg [[DBG237]]
6852 // DEBUG1-NEXT:    br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]], !dbg [[DBG237]]
6853 // DEBUG1:       init:
6854 // DEBUG1-NEXT:    [[TMP3:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB7:[0-9]+]]), !dbg [[DBG237]]
6855 // DEBUG1-NEXT:    call void @__kmpc_threadprivate_register(ptr @[[GLOB7]], ptr @_ZZ4mainE2sm, ptr @.__kmpc_global_ctor_..6, ptr null, ptr @.__kmpc_global_dtor_..7), !dbg [[DBG237]]
6856 // DEBUG1-NEXT:    [[TMP4:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB9]], i32 [[TMP0]], ptr @_ZL3gs1, i64 4, ptr @_ZL3gs1.cache.), !dbg [[DBG239:![0-9]+]]
6857 // DEBUG1-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP4]], i32 0, i32 0, !dbg [[DBG240:![0-9]+]]
6858 // DEBUG1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[A]], align 4, !dbg [[DBG240]]
6859 // DEBUG1-NEXT:    invoke void @_ZZ4mainEN5SmainC1Ei(ptr noundef nonnull align 8 dereferenceable(24) @_ZZ4mainE2sm, i32 noundef [[TMP5]])
6860 // DEBUG1-NEXT:    to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG241:![0-9]+]]
6861 // DEBUG1:       invoke.cont:
6862 // DEBUG1-NEXT:    [[TMP6:%.*]] = call i32 @__cxa_atexit(ptr @_ZZ4mainEN5SmainD1Ev, ptr @_ZZ4mainE2sm, ptr @__dso_handle) #[[ATTR4]], !dbg [[DBG237]]
6863 // DEBUG1-NEXT:    call void @__cxa_guard_release(ptr @_ZGVZ4mainE2sm) #[[ATTR4]], !dbg [[DBG237]]
6864 // DEBUG1-NEXT:    br label [[INIT_END]], !dbg [[DBG237]]
6865 // DEBUG1:       init.end:
6866 // DEBUG1-NEXT:    [[TMP7:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB11:[0-9]+]], i32 [[TMP0]], ptr @_ZN6Static1sE, i64 8, ptr @_ZN6Static1sE.cache.), !dbg [[DBG242:![0-9]+]]
6867 // DEBUG1-NEXT:    [[A1:%.*]] = getelementptr inbounds [[STRUCT_S3:%.*]], ptr [[TMP7]], i32 0, i32 0, !dbg [[DBG243:![0-9]+]]
6868 // DEBUG1-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A1]], align 4, !dbg [[DBG243]]
6869 // DEBUG1-NEXT:    store i32 [[TMP8]], ptr [[RES]], align 4, !dbg [[DBG244:![0-9]+]]
6870 // DEBUG1-NEXT:    [[TMP9:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB13:[0-9]+]], i32 [[TMP0]], ptr @_ZZ4mainE2sm, i64 24, ptr @_ZZ4mainE2sm.cache.), !dbg [[DBG245:![0-9]+]]
6871 // DEBUG1-NEXT:    [[A2:%.*]] = getelementptr inbounds [[STRUCT_SMAIN:%.*]], ptr [[TMP9]], i32 0, i32 0, !dbg [[DBG246:![0-9]+]]
6872 // DEBUG1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[A2]], align 8, !dbg [[DBG246]]
6873 // DEBUG1-NEXT:    [[TMP11:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG247:![0-9]+]]
6874 // DEBUG1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP10]], !dbg [[DBG247]]
6875 // DEBUG1-NEXT:    store i32 [[ADD]], ptr [[RES]], align 4, !dbg [[DBG247]]
6876 // DEBUG1-NEXT:    [[TMP12:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB15:[0-9]+]], i32 [[TMP0]], ptr @_ZL3gs1, i64 4, ptr @_ZL3gs1.cache.), !dbg [[DBG248:![0-9]+]]
6877 // DEBUG1-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP12]], i32 0, i32 0, !dbg [[DBG249:![0-9]+]]
6878 // DEBUG1-NEXT:    [[TMP13:%.*]] = load i32, ptr [[A3]], align 4, !dbg [[DBG249]]
6879 // DEBUG1-NEXT:    [[TMP14:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG250:![0-9]+]]
6880 // DEBUG1-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP14]], [[TMP13]], !dbg [[DBG250]]
6881 // DEBUG1-NEXT:    store i32 [[ADD4]], ptr [[RES]], align 4, !dbg [[DBG250]]
6882 // DEBUG1-NEXT:    [[TMP15:%.*]] = load i32, ptr @_ZL3gs2, align 8, !dbg [[DBG251:![0-9]+]]
6883 // DEBUG1-NEXT:    [[TMP16:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG252:![0-9]+]]
6884 // DEBUG1-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP16]], [[TMP15]], !dbg [[DBG252]]
6885 // DEBUG1-NEXT:    store i32 [[ADD5]], ptr [[RES]], align 4, !dbg [[DBG252]]
6886 // DEBUG1-NEXT:    [[TMP17:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB17:[0-9]+]], i32 [[TMP0]], ptr @gs3, i64 12, ptr @gs3.cache.), !dbg [[DBG253:![0-9]+]]
6887 // DEBUG1-NEXT:    [[A6:%.*]] = getelementptr inbounds [[STRUCT_S5:%.*]], ptr [[TMP17]], i32 0, i32 0, !dbg [[DBG254:![0-9]+]]
6888 // DEBUG1-NEXT:    [[TMP18:%.*]] = load i32, ptr [[A6]], align 4, !dbg [[DBG254]]
6889 // DEBUG1-NEXT:    [[TMP19:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG255:![0-9]+]]
6890 // DEBUG1-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP19]], [[TMP18]], !dbg [[DBG255]]
6891 // DEBUG1-NEXT:    store i32 [[ADD7]], ptr [[RES]], align 4, !dbg [[DBG255]]
6892 // DEBUG1-NEXT:    [[TMP20:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB19:[0-9]+]], i32 [[TMP0]], ptr @arr_x, i64 24, ptr @arr_x.cache.), !dbg [[DBG256:![0-9]+]]
6893 // DEBUG1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP20]], i64 0, i64 1, !dbg [[DBG256]]
6894 // DEBUG1-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG256]]
6895 // DEBUG1-NEXT:    [[A9:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYIDX8]], i32 0, i32 0, !dbg [[DBG257:![0-9]+]]
6896 // DEBUG1-NEXT:    [[TMP21:%.*]] = load i32, ptr [[A9]], align 4, !dbg [[DBG257]]
6897 // DEBUG1-NEXT:    [[TMP22:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG258:![0-9]+]]
6898 // DEBUG1-NEXT:    [[ADD10:%.*]] = add nsw i32 [[TMP22]], [[TMP21]], !dbg [[DBG258]]
6899 // DEBUG1-NEXT:    store i32 [[ADD10]], ptr [[RES]], align 4, !dbg [[DBG258]]
6900 // DEBUG1-NEXT:    [[TMP23:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB21:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STIiE2stE, i64 4, ptr @_ZN2STIiE2stE.cache.), !dbg [[DBG259:![0-9]+]]
6901 // DEBUG1-NEXT:    [[TMP24:%.*]] = load i32, ptr [[TMP23]], align 4, !dbg [[DBG259]]
6902 // DEBUG1-NEXT:    [[TMP25:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG260:![0-9]+]]
6903 // DEBUG1-NEXT:    [[ADD11:%.*]] = add nsw i32 [[TMP25]], [[TMP24]], !dbg [[DBG260]]
6904 // DEBUG1-NEXT:    store i32 [[ADD11]], ptr [[RES]], align 4, !dbg [[DBG260]]
6905 // DEBUG1-NEXT:    [[TMP26:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB23:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STIfE2stE, i64 4, ptr @_ZN2STIfE2stE.cache.), !dbg [[DBG261:![0-9]+]]
6906 // DEBUG1-NEXT:    [[TMP27:%.*]] = load float, ptr [[TMP26]], align 4, !dbg [[DBG261]]
6907 // DEBUG1-NEXT:    [[CONV:%.*]] = fptosi float [[TMP27]] to i32, !dbg [[DBG261]]
6908 // DEBUG1-NEXT:    [[TMP28:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG262:![0-9]+]]
6909 // DEBUG1-NEXT:    [[ADD12:%.*]] = add nsw i32 [[TMP28]], [[CONV]], !dbg [[DBG262]]
6910 // DEBUG1-NEXT:    store i32 [[ADD12]], ptr [[RES]], align 4, !dbg [[DBG262]]
6911 // DEBUG1-NEXT:    [[TMP29:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB25:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STI2S4E2stE, i64 8, ptr @_ZN2STI2S4E2stE.cache.), !dbg [[DBG263:![0-9]+]]
6912 // DEBUG1-NEXT:    [[A13:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[TMP29]], i32 0, i32 0, !dbg [[DBG264:![0-9]+]]
6913 // DEBUG1-NEXT:    [[TMP30:%.*]] = load i32, ptr [[A13]], align 4, !dbg [[DBG264]]
6914 // DEBUG1-NEXT:    [[TMP31:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG265:![0-9]+]]
6915 // DEBUG1-NEXT:    [[ADD14:%.*]] = add nsw i32 [[TMP31]], [[TMP30]], !dbg [[DBG265]]
6916 // DEBUG1-NEXT:    store i32 [[ADD14]], ptr [[RES]], align 4, !dbg [[DBG265]]
6917 // DEBUG1-NEXT:    [[TMP32:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG266:![0-9]+]]
6918 // DEBUG1-NEXT:    ret i32 [[TMP32]], !dbg [[DBG267:![0-9]+]]
6919 // DEBUG1:       lpad:
6920 // DEBUG1-NEXT:    [[TMP33:%.*]] = landingpad { ptr, i32 }
6921 // DEBUG1-NEXT:    cleanup, !dbg [[DBG268:![0-9]+]]
6922 // DEBUG1-NEXT:    [[TMP34:%.*]] = extractvalue { ptr, i32 } [[TMP33]], 0, !dbg [[DBG268]]
6923 // DEBUG1-NEXT:    store ptr [[TMP34]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG268]]
6924 // DEBUG1-NEXT:    [[TMP35:%.*]] = extractvalue { ptr, i32 } [[TMP33]], 1, !dbg [[DBG268]]
6925 // DEBUG1-NEXT:    store i32 [[TMP35]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG268]]
6926 // DEBUG1-NEXT:    call void @__cxa_guard_abort(ptr @_ZGVZ4mainE2sm) #[[ATTR4]], !dbg [[DBG237]]
6927 // DEBUG1-NEXT:    br label [[EH_RESUME:%.*]], !dbg [[DBG237]]
6928 // DEBUG1:       eh.resume:
6929 // DEBUG1-NEXT:    [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG237]]
6930 // DEBUG1-NEXT:    [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG237]]
6931 // DEBUG1-NEXT:    [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG237]]
6932 // DEBUG1-NEXT:    [[LPAD_VAL15:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG237]]
6933 // DEBUG1-NEXT:    resume { ptr, i32 } [[LPAD_VAL15]], !dbg [[DBG237]]
6934 //
6935 //
6936 // DEBUG1-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_..6
6937 // DEBUG1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG269:![0-9]+]] {
6938 // DEBUG1-NEXT:  entry:
6939 // DEBUG1-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
6940 // DEBUG1-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB5:[0-9]+]])
6941 // DEBUG1-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
6942 // DEBUG1-NEXT:    call void @llvm.dbg.declare(metadata ptr [[DOTADDR]], metadata [[META270:![0-9]+]], metadata !DIExpression()), !dbg [[DBG271:![0-9]+]]
6943 // DEBUG1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG272:![0-9]+]]
6944 // DEBUG1-NEXT:    [[TMP3:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB5]], i32 [[TMP1]], ptr @_ZL3gs1, i64 4, ptr @_ZL3gs1.cache.), !dbg [[DBG273:![0-9]+]]
6945 // DEBUG1-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP3]], i32 0, i32 0, !dbg [[DBG274:![0-9]+]]
6946 // DEBUG1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[A]], align 4, !dbg [[DBG274]]
6947 // DEBUG1-NEXT:    call void @_ZZ4mainEN5SmainC1Ei(ptr noundef nonnull align 8 dereferenceable(24) [[TMP2]], i32 noundef [[TMP4]]), !dbg [[DBG275:![0-9]+]]
6948 // DEBUG1-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG272]]
6949 // DEBUG1-NEXT:    ret ptr [[TMP5]], !dbg [[DBG272]]
6950 //
6951 //
6952 // DEBUG1-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC1Ei
6953 // DEBUG1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG276:![0-9]+]] {
6954 // DEBUG1-NEXT:  entry:
6955 // DEBUG1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
6956 // DEBUG1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
6957 // DEBUG1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
6958 // DEBUG1-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META277:![0-9]+]], metadata !DIExpression()), !dbg [[DBG279:![0-9]+]]
6959 // DEBUG1-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
6960 // DEBUG1-NEXT:    call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META280:![0-9]+]], metadata !DIExpression()), !dbg [[DBG281:![0-9]+]]
6961 // DEBUG1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
6962 // DEBUG1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG282:![0-9]+]]
6963 // DEBUG1-NEXT:    call void @_ZZ4mainEN5SmainC2Ei(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG282]]
6964 // DEBUG1-NEXT:    ret void, !dbg [[DBG283:![0-9]+]]
6965 //
6966 //
6967 // DEBUG1-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_..7
6968 // DEBUG1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG284:![0-9]+]] {
6969 // DEBUG1-NEXT:  entry:
6970 // DEBUG1-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
6971 // DEBUG1-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
6972 // DEBUG1-NEXT:    call void @llvm.dbg.declare(metadata ptr [[DOTADDR]], metadata [[META285:![0-9]+]], metadata !DIExpression()), !dbg [[DBG286:![0-9]+]]
6973 // DEBUG1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG286]]
6974 // DEBUG1-NEXT:    call void @_ZZ4mainEN5SmainD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[TMP1]]) #[[ATTR4]], !dbg [[DBG286]]
6975 // DEBUG1-NEXT:    ret void, !dbg [[DBG287:![0-9]+]]
6976 //
6977 //
6978 // DEBUG1-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD1Ev
6979 // DEBUG1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] align 2 !dbg [[DBG288:![0-9]+]] {
6980 // DEBUG1-NEXT:  entry:
6981 // DEBUG1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
6982 // DEBUG1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
6983 // DEBUG1-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META289:![0-9]+]], metadata !DIExpression()), !dbg [[DBG290:![0-9]+]]
6984 // DEBUG1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
6985 // DEBUG1-NEXT:    call void @_ZZ4mainEN5SmainD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR4]], !dbg [[DBG291:![0-9]+]]
6986 // DEBUG1-NEXT:    ret void, !dbg [[DBG292:![0-9]+]]
6987 //
6988 //
6989 // DEBUG1-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC2Ei
6990 // DEBUG1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR3]] align 2 !dbg [[DBG293:![0-9]+]] {
6991 // DEBUG1-NEXT:  entry:
6992 // DEBUG1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
6993 // DEBUG1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
6994 // DEBUG1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
6995 // DEBUG1-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META294:![0-9]+]], metadata !DIExpression()), !dbg [[DBG295:![0-9]+]]
6996 // DEBUG1-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
6997 // DEBUG1-NEXT:    call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META296:![0-9]+]], metadata !DIExpression()), !dbg [[DBG297:![0-9]+]]
6998 // DEBUG1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
6999 // DEBUG1-NEXT:    [[A2:%.*]] = getelementptr inbounds [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG298:![0-9]+]]
7000 // DEBUG1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG299:![0-9]+]]
7001 // DEBUG1-NEXT:    store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG298]]
7002 // DEBUG1-NEXT:    ret void, !dbg [[DBG300:![0-9]+]]
7003 //
7004 //
7005 // DEBUG1-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD2Ev
7006 // DEBUG1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] align 2 !dbg [[DBG301:![0-9]+]] {
7007 // DEBUG1-NEXT:  entry:
7008 // DEBUG1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
7009 // DEBUG1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
7010 // DEBUG1-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META302:![0-9]+]], metadata !DIExpression()), !dbg [[DBG303:![0-9]+]]
7011 // DEBUG1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
7012 // DEBUG1-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG304:![0-9]+]]
7013 // DEBUG1-NEXT:    store i32 0, ptr [[A]], align 8, !dbg [[DBG306:![0-9]+]]
7014 // DEBUG1-NEXT:    ret void, !dbg [[DBG307:![0-9]+]]
7015 //
7016 //
7017 // DEBUG1-LABEL: define {{[^@]+}}@_Z6foobarv
7018 // DEBUG1-SAME: () #[[ATTR6:[0-9]+]] !dbg [[DBG308:![0-9]+]] {
7019 // DEBUG1-NEXT:  entry:
7020 // DEBUG1-NEXT:    [[RES:%.*]] = alloca i32, align 4
7021 // DEBUG1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB27:[0-9]+]])
7022 // DEBUG1-NEXT:    call void @llvm.dbg.declare(metadata ptr [[RES]], metadata [[META309:![0-9]+]], metadata !DIExpression()), !dbg [[DBG310:![0-9]+]]
7023 // DEBUG1-NEXT:    [[TMP1:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB27]], i32 [[TMP0]], ptr @_ZN6Static1sE, i64 8, ptr @_ZN6Static1sE.cache.), !dbg [[DBG311:![0-9]+]]
7024 // DEBUG1-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S3:%.*]], ptr [[TMP1]], i32 0, i32 0, !dbg [[DBG312:![0-9]+]]
7025 // DEBUG1-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 4, !dbg [[DBG312]]
7026 // DEBUG1-NEXT:    store i32 [[TMP2]], ptr [[RES]], align 4, !dbg [[DBG313:![0-9]+]]
7027 // DEBUG1-NEXT:    [[TMP3:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB29:[0-9]+]], i32 [[TMP0]], ptr @_ZL3gs1, i64 4, ptr @_ZL3gs1.cache.), !dbg [[DBG314:![0-9]+]]
7028 // DEBUG1-NEXT:    [[A1:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP3]], i32 0, i32 0, !dbg [[DBG315:![0-9]+]]
7029 // DEBUG1-NEXT:    [[TMP4:%.*]] = load i32, ptr [[A1]], align 4, !dbg [[DBG315]]
7030 // DEBUG1-NEXT:    [[TMP5:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG316:![0-9]+]]
7031 // DEBUG1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP5]], [[TMP4]], !dbg [[DBG316]]
7032 // DEBUG1-NEXT:    store i32 [[ADD]], ptr [[RES]], align 4, !dbg [[DBG316]]
7033 // DEBUG1-NEXT:    [[TMP6:%.*]] = load i32, ptr @_ZL3gs2, align 8, !dbg [[DBG317:![0-9]+]]
7034 // DEBUG1-NEXT:    [[TMP7:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG318:![0-9]+]]
7035 // DEBUG1-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP7]], [[TMP6]], !dbg [[DBG318]]
7036 // DEBUG1-NEXT:    store i32 [[ADD2]], ptr [[RES]], align 4, !dbg [[DBG318]]
7037 // DEBUG1-NEXT:    [[TMP8:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB31:[0-9]+]], i32 [[TMP0]], ptr @gs3, i64 12, ptr @gs3.cache.), !dbg [[DBG319:![0-9]+]]
7038 // DEBUG1-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S5:%.*]], ptr [[TMP8]], i32 0, i32 0, !dbg [[DBG320:![0-9]+]]
7039 // DEBUG1-NEXT:    [[TMP9:%.*]] = load i32, ptr [[A3]], align 4, !dbg [[DBG320]]
7040 // DEBUG1-NEXT:    [[TMP10:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG321:![0-9]+]]
7041 // DEBUG1-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP10]], [[TMP9]], !dbg [[DBG321]]
7042 // DEBUG1-NEXT:    store i32 [[ADD4]], ptr [[RES]], align 4, !dbg [[DBG321]]
7043 // DEBUG1-NEXT:    [[TMP11:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB33:[0-9]+]], i32 [[TMP0]], ptr @arr_x, i64 24, ptr @arr_x.cache.), !dbg [[DBG322:![0-9]+]]
7044 // DEBUG1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP11]], i64 0, i64 1, !dbg [[DBG322]]
7045 // DEBUG1-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG322]]
7046 // DEBUG1-NEXT:    [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYIDX5]], i32 0, i32 0, !dbg [[DBG323:![0-9]+]]
7047 // DEBUG1-NEXT:    [[TMP12:%.*]] = load i32, ptr [[A6]], align 4, !dbg [[DBG323]]
7048 // DEBUG1-NEXT:    [[TMP13:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG324:![0-9]+]]
7049 // DEBUG1-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP13]], [[TMP12]], !dbg [[DBG324]]
7050 // DEBUG1-NEXT:    store i32 [[ADD7]], ptr [[RES]], align 4, !dbg [[DBG324]]
7051 // DEBUG1-NEXT:    [[TMP14:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB35:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STIiE2stE, i64 4, ptr @_ZN2STIiE2stE.cache.), !dbg [[DBG325:![0-9]+]]
7052 // DEBUG1-NEXT:    [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4, !dbg [[DBG325]]
7053 // DEBUG1-NEXT:    [[TMP16:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG326:![0-9]+]]
7054 // DEBUG1-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP16]], [[TMP15]], !dbg [[DBG326]]
7055 // DEBUG1-NEXT:    store i32 [[ADD8]], ptr [[RES]], align 4, !dbg [[DBG326]]
7056 // DEBUG1-NEXT:    [[TMP17:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB37:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STIfE2stE, i64 4, ptr @_ZN2STIfE2stE.cache.), !dbg [[DBG327:![0-9]+]]
7057 // DEBUG1-NEXT:    [[TMP18:%.*]] = load float, ptr [[TMP17]], align 4, !dbg [[DBG327]]
7058 // DEBUG1-NEXT:    [[CONV:%.*]] = fptosi float [[TMP18]] to i32, !dbg [[DBG327]]
7059 // DEBUG1-NEXT:    [[TMP19:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG328:![0-9]+]]
7060 // DEBUG1-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP19]], [[CONV]], !dbg [[DBG328]]
7061 // DEBUG1-NEXT:    store i32 [[ADD9]], ptr [[RES]], align 4, !dbg [[DBG328]]
7062 // DEBUG1-NEXT:    [[TMP20:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB39:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STI2S4E2stE, i64 8, ptr @_ZN2STI2S4E2stE.cache.), !dbg [[DBG329:![0-9]+]]
7063 // DEBUG1-NEXT:    [[A10:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[TMP20]], i32 0, i32 0, !dbg [[DBG330:![0-9]+]]
7064 // DEBUG1-NEXT:    [[TMP21:%.*]] = load i32, ptr [[A10]], align 4, !dbg [[DBG330]]
7065 // DEBUG1-NEXT:    [[TMP22:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG331:![0-9]+]]
7066 // DEBUG1-NEXT:    [[ADD11:%.*]] = add nsw i32 [[TMP22]], [[TMP21]], !dbg [[DBG331]]
7067 // DEBUG1-NEXT:    store i32 [[ADD11]], ptr [[RES]], align 4, !dbg [[DBG331]]
7068 // DEBUG1-NEXT:    [[TMP23:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG332:![0-9]+]]
7069 // DEBUG1-NEXT:    ret i32 [[TMP23]], !dbg [[DBG333:![0-9]+]]
7070 //
7071 //
7072 // DEBUG1-LABEL: define {{[^@]+}}@__cxx_global_var_init.8
7073 // DEBUG1-SAME: () #[[ATTR0]] comdat($_ZN2STI2S4E2stE) !dbg [[DBG334:![0-9]+]] {
7074 // DEBUG1-NEXT:  entry:
7075 // DEBUG1-NEXT:    [[TMP0:%.*]] = load i8, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG335:![0-9]+]]
7076 // DEBUG1-NEXT:    [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG335]]
7077 // DEBUG1-NEXT:    br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG335]]
7078 // DEBUG1:       init.check:
7079 // DEBUG1-NEXT:    store i8 1, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG335]]
7080 // DEBUG1-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB41:[0-9]+]]), !dbg [[DBG335]]
7081 // DEBUG1-NEXT:    call void @__kmpc_threadprivate_register(ptr @[[GLOB41]], ptr @_ZN2STI2S4E2stE, ptr @.__kmpc_global_ctor_..9, ptr null, ptr @.__kmpc_global_dtor_..10), !dbg [[DBG335]]
7082 // DEBUG1-NEXT:    call void @_ZN2S4C1Ei(ptr noundef nonnull align 4 dereferenceable(8) @_ZN2STI2S4E2stE, i32 noundef 23), !dbg [[DBG336:![0-9]+]]
7083 // DEBUG1-NEXT:    [[TMP2:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S4D1Ev, ptr @_ZN2STI2S4E2stE, ptr @__dso_handle) #[[ATTR4]], !dbg [[DBG335]]
7084 // DEBUG1-NEXT:    br label [[INIT_END]], !dbg [[DBG335]]
7085 // DEBUG1:       init.end:
7086 // DEBUG1-NEXT:    ret void, !dbg [[DBG338:![0-9]+]]
7087 //
7088 //
7089 // DEBUG1-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_..9
7090 // DEBUG1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG339:![0-9]+]] {
7091 // DEBUG1-NEXT:  entry:
7092 // DEBUG1-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
7093 // DEBUG1-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
7094 // DEBUG1-NEXT:    call void @llvm.dbg.declare(metadata ptr [[DOTADDR]], metadata [[META340:![0-9]+]], metadata !DIExpression()), !dbg [[DBG341:![0-9]+]]
7095 // DEBUG1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG342:![0-9]+]]
7096 // DEBUG1-NEXT:    call void @_ZN2S4C1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[TMP1]], i32 noundef 23), !dbg [[DBG343:![0-9]+]]
7097 // DEBUG1-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG342]]
7098 // DEBUG1-NEXT:    ret ptr [[TMP2]], !dbg [[DBG342]]
7099 //
7100 //
7101 // DEBUG1-LABEL: define {{[^@]+}}@_ZN2S4C1Ei
7102 // DEBUG1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG344:![0-9]+]] {
7103 // DEBUG1-NEXT:  entry:
7104 // DEBUG1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
7105 // DEBUG1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
7106 // DEBUG1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
7107 // DEBUG1-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META345:![0-9]+]], metadata !DIExpression()), !dbg [[DBG347:![0-9]+]]
7108 // DEBUG1-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
7109 // DEBUG1-NEXT:    call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META348:![0-9]+]], metadata !DIExpression()), !dbg [[DBG349:![0-9]+]]
7110 // DEBUG1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
7111 // DEBUG1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG350:![0-9]+]]
7112 // DEBUG1-NEXT:    call void @_ZN2S4C2Ei(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG350]]
7113 // DEBUG1-NEXT:    ret void, !dbg [[DBG351:![0-9]+]]
7114 //
7115 //
7116 // DEBUG1-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_..10
7117 // DEBUG1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG352:![0-9]+]] {
7118 // DEBUG1-NEXT:  entry:
7119 // DEBUG1-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
7120 // DEBUG1-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
7121 // DEBUG1-NEXT:    call void @llvm.dbg.declare(metadata ptr [[DOTADDR]], metadata [[META353:![0-9]+]], metadata !DIExpression()), !dbg [[DBG354:![0-9]+]]
7122 // DEBUG1-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG354]]
7123 // DEBUG1-NEXT:    call void @_ZN2S4D1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[TMP1]]) #[[ATTR4]], !dbg [[DBG354]]
7124 // DEBUG1-NEXT:    ret void, !dbg [[DBG355:![0-9]+]]
7125 //
7126 //
7127 // DEBUG1-LABEL: define {{[^@]+}}@_ZN2S4D1Ev
7128 // DEBUG1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG356:![0-9]+]] {
7129 // DEBUG1-NEXT:  entry:
7130 // DEBUG1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
7131 // DEBUG1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
7132 // DEBUG1-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META357:![0-9]+]], metadata !DIExpression()), !dbg [[DBG358:![0-9]+]]
7133 // DEBUG1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
7134 // DEBUG1-NEXT:    call void @_ZN2S4D2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]], !dbg [[DBG359:![0-9]+]]
7135 // DEBUG1-NEXT:    ret void, !dbg [[DBG360:![0-9]+]]
7136 //
7137 //
7138 // DEBUG1-LABEL: define {{[^@]+}}@_ZN2S4C2Ei
7139 // DEBUG1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG361:![0-9]+]] {
7140 // DEBUG1-NEXT:  entry:
7141 // DEBUG1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
7142 // DEBUG1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
7143 // DEBUG1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
7144 // DEBUG1-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META362:![0-9]+]], metadata !DIExpression()), !dbg [[DBG363:![0-9]+]]
7145 // DEBUG1-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
7146 // DEBUG1-NEXT:    call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META364:![0-9]+]], metadata !DIExpression()), !dbg [[DBG365:![0-9]+]]
7147 // DEBUG1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
7148 // DEBUG1-NEXT:    [[A2:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG366:![0-9]+]]
7149 // DEBUG1-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG367:![0-9]+]]
7150 // DEBUG1-NEXT:    store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG366]]
7151 // DEBUG1-NEXT:    ret void, !dbg [[DBG368:![0-9]+]]
7152 //
7153 //
7154 // DEBUG1-LABEL: define {{[^@]+}}@_ZN2S4D2Ev
7155 // DEBUG1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG369:![0-9]+]] {
7156 // DEBUG1-NEXT:  entry:
7157 // DEBUG1-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
7158 // DEBUG1-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
7159 // DEBUG1-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META370:![0-9]+]], metadata !DIExpression()), !dbg [[DBG371:![0-9]+]]
7160 // DEBUG1-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
7161 // DEBUG1-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG372:![0-9]+]]
7162 // DEBUG1-NEXT:    store i32 0, ptr [[A]], align 4, !dbg [[DBG374:![0-9]+]]
7163 // DEBUG1-NEXT:    ret void, !dbg [[DBG375:![0-9]+]]
7164 //
7165 //
7166 // DEBUG1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_threadprivate_codegen.cpp
7167 // DEBUG1-SAME: () #[[ATTR0]] !dbg [[DBG376:![0-9]+]] {
7168 // DEBUG1-NEXT:  entry:
7169 // DEBUG1-NEXT:    call void @__cxx_global_var_init(), !dbg [[DBG377:![0-9]+]]
7170 // DEBUG1-NEXT:    call void @.__omp_threadprivate_init_.(), !dbg [[DBG377]]
7171 // DEBUG1-NEXT:    call void @__cxx_global_var_init.4(), !dbg [[DBG377]]
7172 // DEBUG1-NEXT:    call void @__cxx_global_var_init.5(), !dbg [[DBG377]]
7173 // DEBUG1-NEXT:    call void @.__omp_threadprivate_init_..3(), !dbg [[DBG377]]
7174 // DEBUG1-NEXT:    ret void
7175 //
7176 //
7177 // DEBUG2-LABEL: define {{[^@]+}}@__cxx_global_var_init
7178 // DEBUG2-SAME: () #[[ATTR0:[0-9]+]] !dbg [[DBG116:![0-9]+]] {
7179 // DEBUG2-NEXT:  entry:
7180 // DEBUG2-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]]), !dbg [[DBG120:![0-9]+]]
7181 // DEBUG2-NEXT:    call void @__kmpc_threadprivate_register(ptr @[[GLOB1]], ptr @_ZL3gs1, ptr @.__kmpc_global_ctor_., ptr null, ptr @.__kmpc_global_dtor_.), !dbg [[DBG120]]
7182 // DEBUG2-NEXT:    call void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @_ZL3gs1, i32 noundef 5), !dbg [[DBG121:![0-9]+]]
7183 // DEBUG2-NEXT:    [[TMP1:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S1D1Ev, ptr @_ZL3gs1, ptr @__dso_handle) #[[ATTR4:[0-9]+]], !dbg [[DBG120]]
7184 // DEBUG2-NEXT:    ret void, !dbg [[DBG123:![0-9]+]]
7185 //
7186 //
7187 // DEBUG2-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_.
7188 // DEBUG2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG124:![0-9]+]] {
7189 // DEBUG2-NEXT:  entry:
7190 // DEBUG2-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
7191 // DEBUG2-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
7192 // DEBUG2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[DOTADDR]], metadata [[META126:![0-9]+]], metadata !DIExpression()), !dbg [[DBG128:![0-9]+]]
7193 // DEBUG2-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG129:![0-9]+]]
7194 // DEBUG2-NEXT:    call void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[TMP1]], i32 noundef 5), !dbg [[DBG130:![0-9]+]]
7195 // DEBUG2-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG129]]
7196 // DEBUG2-NEXT:    ret ptr [[TMP2]], !dbg [[DBG129]]
7197 //
7198 //
7199 // DEBUG2-LABEL: define {{[^@]+}}@_ZN2S1C1Ei
7200 // DEBUG2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 !dbg [[DBG131:![0-9]+]] {
7201 // DEBUG2-NEXT:  entry:
7202 // DEBUG2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
7203 // DEBUG2-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
7204 // DEBUG2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
7205 // DEBUG2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META132:![0-9]+]], metadata !DIExpression()), !dbg [[DBG134:![0-9]+]]
7206 // DEBUG2-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
7207 // DEBUG2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META135:![0-9]+]], metadata !DIExpression()), !dbg [[DBG136:![0-9]+]]
7208 // DEBUG2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
7209 // DEBUG2-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG137:![0-9]+]]
7210 // DEBUG2-NEXT:    call void @_ZN2S1C2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG137]]
7211 // DEBUG2-NEXT:    ret void, !dbg [[DBG138:![0-9]+]]
7212 //
7213 //
7214 // DEBUG2-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_.
7215 // DEBUG2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG139:![0-9]+]] {
7216 // DEBUG2-NEXT:  entry:
7217 // DEBUG2-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
7218 // DEBUG2-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
7219 // DEBUG2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[DOTADDR]], metadata [[META140:![0-9]+]], metadata !DIExpression()), !dbg [[DBG141:![0-9]+]]
7220 // DEBUG2-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG141]]
7221 // DEBUG2-NEXT:    call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP1]]) #[[ATTR4]], !dbg [[DBG141]]
7222 // DEBUG2-NEXT:    ret void, !dbg [[DBG142:![0-9]+]]
7223 //
7224 //
7225 // DEBUG2-LABEL: define {{[^@]+}}@_ZN2S1D1Ev
7226 // DEBUG2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR3:[0-9]+]] comdat align 2 !dbg [[DBG143:![0-9]+]] {
7227 // DEBUG2-NEXT:  entry:
7228 // DEBUG2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
7229 // DEBUG2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
7230 // DEBUG2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META144:![0-9]+]], metadata !DIExpression()), !dbg [[DBG145:![0-9]+]]
7231 // DEBUG2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
7232 // DEBUG2-NEXT:    call void @_ZN2S1D2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]], !dbg [[DBG146:![0-9]+]]
7233 // DEBUG2-NEXT:    ret void, !dbg [[DBG147:![0-9]+]]
7234 //
7235 //
7236 // DEBUG2-LABEL: define {{[^@]+}}@__cxx_global_var_init.1
7237 // DEBUG2-SAME: () #[[ATTR0]] !dbg [[DBG148:![0-9]+]] {
7238 // DEBUG2-NEXT:  entry:
7239 // DEBUG2-NEXT:    call void @_ZN2S2C1Ei(ptr noundef nonnull align 8 dereferenceable(16) @_ZL3gs2, i32 noundef 27), !dbg [[DBG149:![0-9]+]]
7240 // DEBUG2-NEXT:    [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S2D1Ev, ptr @_ZL3gs2, ptr @__dso_handle) #[[ATTR4]], !dbg [[DBG151:![0-9]+]]
7241 // DEBUG2-NEXT:    ret void, !dbg [[DBG152:![0-9]+]]
7242 //
7243 //
7244 // DEBUG2-LABEL: define {{[^@]+}}@_ZN2S2C1Ei
7245 // DEBUG2-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG153:![0-9]+]] {
7246 // DEBUG2-NEXT:  entry:
7247 // DEBUG2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
7248 // DEBUG2-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
7249 // DEBUG2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
7250 // DEBUG2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META154:![0-9]+]], metadata !DIExpression()), !dbg [[DBG156:![0-9]+]]
7251 // DEBUG2-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
7252 // DEBUG2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META157:![0-9]+]], metadata !DIExpression()), !dbg [[DBG158:![0-9]+]]
7253 // DEBUG2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
7254 // DEBUG2-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG159:![0-9]+]]
7255 // DEBUG2-NEXT:    call void @_ZN2S2C2Ei(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG159]]
7256 // DEBUG2-NEXT:    ret void, !dbg [[DBG160:![0-9]+]]
7257 //
7258 //
7259 // DEBUG2-LABEL: define {{[^@]+}}@_ZN2S2D1Ev
7260 // DEBUG2-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG161:![0-9]+]] {
7261 // DEBUG2-NEXT:  entry:
7262 // DEBUG2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
7263 // DEBUG2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
7264 // DEBUG2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META162:![0-9]+]], metadata !DIExpression()), !dbg [[DBG163:![0-9]+]]
7265 // DEBUG2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
7266 // DEBUG2-NEXT:    call void @_ZN2S2D2Ev(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]]) #[[ATTR4]], !dbg [[DBG164:![0-9]+]]
7267 // DEBUG2-NEXT:    ret void, !dbg [[DBG165:![0-9]+]]
7268 //
7269 //
7270 // DEBUG2-LABEL: define {{[^@]+}}@__cxx_global_var_init.2
7271 // DEBUG2-SAME: () #[[ATTR0]] personality ptr @__gxx_personality_v0 !dbg [[DBG166:![0-9]+]] {
7272 // DEBUG2-NEXT:  entry:
7273 // DEBUG2-NEXT:    [[ARRAYINIT_ENDOFINIT:%.*]] = alloca ptr, align 8
7274 // DEBUG2-NEXT:    [[ARRAYINIT_ENDOFINIT1:%.*]] = alloca ptr, align 8
7275 // DEBUG2-NEXT:    [[EXN_SLOT:%.*]] = alloca ptr, align 8
7276 // DEBUG2-NEXT:    [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4
7277 // DEBUG2-NEXT:    [[ARRAYINIT_ENDOFINIT5:%.*]] = alloca ptr, align 8
7278 // DEBUG2-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3:[0-9]+]]), !dbg [[DBG167:![0-9]+]]
7279 // DEBUG2-NEXT:    call void @__kmpc_threadprivate_register(ptr @[[GLOB3]], ptr @arr_x, ptr @.__kmpc_global_ctor_..3, ptr null, ptr @.__kmpc_global_dtor_..4), !dbg [[DBG167]]
7280 // DEBUG2-NEXT:    store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG168:![0-9]+]]
7281 // DEBUG2-NEXT:    store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG170:![0-9]+]]
7282 // DEBUG2-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @arr_x, i32 noundef 1)
7283 // DEBUG2-NEXT:    to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG171:![0-9]+]]
7284 // DEBUG2:       invoke.cont:
7285 // DEBUG2-NEXT:    store ptr getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG170]]
7286 // DEBUG2-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 1), i32 noundef 2)
7287 // DEBUG2-NEXT:    to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD]], !dbg [[DBG172:![0-9]+]]
7288 // DEBUG2:       invoke.cont2:
7289 // DEBUG2-NEXT:    store ptr getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG170]]
7290 // DEBUG2-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), i32 noundef 3)
7291 // DEBUG2-NEXT:    to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]], !dbg [[DBG173:![0-9]+]]
7292 // DEBUG2:       invoke.cont3:
7293 // DEBUG2-NEXT:    store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG168]]
7294 // DEBUG2-NEXT:    store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG174:![0-9]+]]
7295 // DEBUG2-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i32 noundef 4)
7296 // DEBUG2-NEXT:    to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD6:%.*]], !dbg [[DBG175:![0-9]+]]
7297 // DEBUG2:       invoke.cont7:
7298 // DEBUG2-NEXT:    store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG174]]
7299 // DEBUG2-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), i32 noundef 5)
7300 // DEBUG2-NEXT:    to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD6]], !dbg [[DBG176:![0-9]+]]
7301 // DEBUG2:       invoke.cont8:
7302 // DEBUG2-NEXT:    store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG174]]
7303 // DEBUG2-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), i32 noundef 6)
7304 // DEBUG2-NEXT:    to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD6]], !dbg [[DBG177:![0-9]+]]
7305 // DEBUG2:       invoke.cont9:
7306 // DEBUG2-NEXT:    [[TMP1:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR4]], !dbg [[DBG167]]
7307 // DEBUG2-NEXT:    ret void, !dbg [[DBG167]]
7308 // DEBUG2:       lpad:
7309 // DEBUG2-NEXT:    [[TMP2:%.*]] = landingpad { ptr, i32 }
7310 // DEBUG2-NEXT:    cleanup, !dbg [[DBG178:![0-9]+]]
7311 // DEBUG2-NEXT:    [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP2]], 0, !dbg [[DBG178]]
7312 // DEBUG2-NEXT:    store ptr [[TMP3]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG178]]
7313 // DEBUG2-NEXT:    [[TMP4:%.*]] = extractvalue { ptr, i32 } [[TMP2]], 1, !dbg [[DBG178]]
7314 // DEBUG2-NEXT:    store i32 [[TMP4]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG178]]
7315 // DEBUG2-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG170]]
7316 // DEBUG2-NEXT:    [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr @arr_x, [[TMP5]], !dbg [[DBG170]]
7317 // DEBUG2-NEXT:    br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG170]]
7318 // DEBUG2:       arraydestroy.body:
7319 // DEBUG2-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP5]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG170]]
7320 // DEBUG2-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG170]]
7321 // DEBUG2-NEXT:    call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]], !dbg [[DBG170]]
7322 // DEBUG2-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[DBG170]]
7323 // DEBUG2-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG170]]
7324 // DEBUG2:       arraydestroy.done4:
7325 // DEBUG2-NEXT:    br label [[EHCLEANUP:%.*]], !dbg [[DBG170]]
7326 // DEBUG2:       lpad6:
7327 // DEBUG2-NEXT:    [[TMP6:%.*]] = landingpad { ptr, i32 }
7328 // DEBUG2-NEXT:    cleanup, !dbg [[DBG178]]
7329 // DEBUG2-NEXT:    [[TMP7:%.*]] = extractvalue { ptr, i32 } [[TMP6]], 0, !dbg [[DBG178]]
7330 // DEBUG2-NEXT:    store ptr [[TMP7]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG178]]
7331 // DEBUG2-NEXT:    [[TMP8:%.*]] = extractvalue { ptr, i32 } [[TMP6]], 1, !dbg [[DBG178]]
7332 // DEBUG2-NEXT:    store i32 [[TMP8]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG178]]
7333 // DEBUG2-NEXT:    [[TMP9:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG174]]
7334 // DEBUG2-NEXT:    [[ARRAYDESTROY_ISEMPTY10:%.*]] = icmp eq ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), [[TMP9]], !dbg [[DBG174]]
7335 // DEBUG2-NEXT:    br i1 [[ARRAYDESTROY_ISEMPTY10]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY11:%.*]], !dbg [[DBG174]]
7336 // DEBUG2:       arraydestroy.body11:
7337 // DEBUG2-NEXT:    [[ARRAYDESTROY_ELEMENTPAST12:%.*]] = phi ptr [ [[TMP9]], [[LPAD6]] ], [ [[ARRAYDESTROY_ELEMENT13:%.*]], [[ARRAYDESTROY_BODY11]] ], !dbg [[DBG174]]
7338 // DEBUG2-NEXT:    [[ARRAYDESTROY_ELEMENT13]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST12]], i64 -1, !dbg [[DBG174]]
7339 // DEBUG2-NEXT:    call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR4]], !dbg [[DBG174]]
7340 // DEBUG2-NEXT:    [[ARRAYDESTROY_DONE14:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), !dbg [[DBG174]]
7341 // DEBUG2-NEXT:    br i1 [[ARRAYDESTROY_DONE14]], label [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_BODY11]], !dbg [[DBG174]]
7342 // DEBUG2:       arraydestroy.done15:
7343 // DEBUG2-NEXT:    br label [[EHCLEANUP]], !dbg [[DBG174]]
7344 // DEBUG2:       ehcleanup:
7345 // DEBUG2-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG168]]
7346 // DEBUG2-NEXT:    [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP10]], i64 0, i64 0, !dbg [[DBG168]]
7347 // DEBUG2-NEXT:    [[ARRAYDESTROY_ISEMPTY16:%.*]] = icmp eq ptr @arr_x, [[PAD_ARRAYEND]], !dbg [[DBG168]]
7348 // DEBUG2-NEXT:    br i1 [[ARRAYDESTROY_ISEMPTY16]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17:%.*]], !dbg [[DBG168]]
7349 // DEBUG2:       arraydestroy.body17:
7350 // DEBUG2-NEXT:    [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi ptr [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ], !dbg [[DBG168]]
7351 // DEBUG2-NEXT:    [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1, !dbg [[DBG168]]
7352 // DEBUG2-NEXT:    call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR4]], !dbg [[DBG168]]
7353 // DEBUG2-NEXT:    [[ARRAYDESTROY_DONE20:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT19]], @arr_x, !dbg [[DBG168]]
7354 // DEBUG2-NEXT:    br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]], !dbg [[DBG168]]
7355 // DEBUG2:       arraydestroy.done21:
7356 // DEBUG2-NEXT:    br label [[EH_RESUME:%.*]], !dbg [[DBG168]]
7357 // DEBUG2:       eh.resume:
7358 // DEBUG2-NEXT:    [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG168]]
7359 // DEBUG2-NEXT:    [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG168]]
7360 // DEBUG2-NEXT:    [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG168]]
7361 // DEBUG2-NEXT:    [[LPAD_VAL22:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG168]]
7362 // DEBUG2-NEXT:    resume { ptr, i32 } [[LPAD_VAL22]], !dbg [[DBG168]]
7363 //
7364 //
7365 // DEBUG2-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_..3
7366 // DEBUG2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] personality ptr @__gxx_personality_v0 !dbg [[DBG179:![0-9]+]] {
7367 // DEBUG2-NEXT:  entry:
7368 // DEBUG2-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
7369 // DEBUG2-NEXT:    [[ARRAYINIT_ENDOFINIT:%.*]] = alloca ptr, align 8
7370 // DEBUG2-NEXT:    [[ARRAYINIT_ENDOFINIT2:%.*]] = alloca ptr, align 8
7371 // DEBUG2-NEXT:    [[EXN_SLOT:%.*]] = alloca ptr, align 8
7372 // DEBUG2-NEXT:    [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4
7373 // DEBUG2-NEXT:    [[ARRAYINIT_ENDOFINIT9:%.*]] = alloca ptr, align 8
7374 // DEBUG2-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
7375 // DEBUG2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[DOTADDR]], metadata [[META180:![0-9]+]], metadata !DIExpression()), !dbg [[DBG181:![0-9]+]]
7376 // DEBUG2-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG182:![0-9]+]]
7377 // DEBUG2-NEXT:    [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP1]], i64 0, i64 0, !dbg [[DBG183:![0-9]+]]
7378 // DEBUG2-NEXT:    store ptr [[ARRAYINIT_BEGIN]], ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG183]]
7379 // DEBUG2-NEXT:    [[ARRAYINIT_BEGIN1:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYINIT_BEGIN]], i64 0, i64 0, !dbg [[DBG184:![0-9]+]]
7380 // DEBUG2-NEXT:    store ptr [[ARRAYINIT_BEGIN1]], ptr [[ARRAYINIT_ENDOFINIT2]], align 8, !dbg [[DBG184]]
7381 // DEBUG2-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN1]], i32 noundef 1)
7382 // DEBUG2-NEXT:    to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG185:![0-9]+]]
7383 // DEBUG2:       invoke.cont:
7384 // DEBUG2-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[ARRAYINIT_BEGIN1]], i64 1, !dbg [[DBG184]]
7385 // DEBUG2-NEXT:    store ptr [[ARRAYINIT_ELEMENT]], ptr [[ARRAYINIT_ENDOFINIT2]], align 8, !dbg [[DBG184]]
7386 // DEBUG2-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2)
7387 // DEBUG2-NEXT:    to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]], !dbg [[DBG186:![0-9]+]]
7388 // DEBUG2:       invoke.cont3:
7389 // DEBUG2-NEXT:    [[ARRAYINIT_ELEMENT4:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYINIT_ELEMENT]], i64 1, !dbg [[DBG184]]
7390 // DEBUG2-NEXT:    store ptr [[ARRAYINIT_ELEMENT4]], ptr [[ARRAYINIT_ENDOFINIT2]], align 8, !dbg [[DBG184]]
7391 // DEBUG2-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT4]], i32 noundef 3)
7392 // DEBUG2-NEXT:    to label [[INVOKE_CONT5:%.*]] unwind label [[LPAD]], !dbg [[DBG187:![0-9]+]]
7393 // DEBUG2:       invoke.cont5:
7394 // DEBUG2-NEXT:    [[ARRAYINIT_ELEMENT7:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYINIT_BEGIN]], i64 1, !dbg [[DBG183]]
7395 // DEBUG2-NEXT:    store ptr [[ARRAYINIT_ELEMENT7]], ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG183]]
7396 // DEBUG2-NEXT:    [[ARRAYINIT_BEGIN8:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYINIT_ELEMENT7]], i64 0, i64 0, !dbg [[DBG188:![0-9]+]]
7397 // DEBUG2-NEXT:    store ptr [[ARRAYINIT_BEGIN8]], ptr [[ARRAYINIT_ENDOFINIT9]], align 8, !dbg [[DBG188]]
7398 // DEBUG2-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN8]], i32 noundef 4)
7399 // DEBUG2-NEXT:    to label [[INVOKE_CONT11:%.*]] unwind label [[LPAD10:%.*]], !dbg [[DBG189:![0-9]+]]
7400 // DEBUG2:       invoke.cont11:
7401 // DEBUG2-NEXT:    [[ARRAYINIT_ELEMENT12:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYINIT_BEGIN8]], i64 1, !dbg [[DBG188]]
7402 // DEBUG2-NEXT:    store ptr [[ARRAYINIT_ELEMENT12]], ptr [[ARRAYINIT_ENDOFINIT9]], align 8, !dbg [[DBG188]]
7403 // DEBUG2-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT12]], i32 noundef 5)
7404 // DEBUG2-NEXT:    to label [[INVOKE_CONT13:%.*]] unwind label [[LPAD10]], !dbg [[DBG190:![0-9]+]]
7405 // DEBUG2:       invoke.cont13:
7406 // DEBUG2-NEXT:    [[ARRAYINIT_ELEMENT14:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYINIT_ELEMENT12]], i64 1, !dbg [[DBG188]]
7407 // DEBUG2-NEXT:    store ptr [[ARRAYINIT_ELEMENT14]], ptr [[ARRAYINIT_ENDOFINIT9]], align 8, !dbg [[DBG188]]
7408 // DEBUG2-NEXT:    invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT14]], i32 noundef 6)
7409 // DEBUG2-NEXT:    to label [[INVOKE_CONT15:%.*]] unwind label [[LPAD10]], !dbg [[DBG191:![0-9]+]]
7410 // DEBUG2:       invoke.cont15:
7411 // DEBUG2-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG182]]
7412 // DEBUG2-NEXT:    ret ptr [[TMP2]], !dbg [[DBG182]]
7413 // DEBUG2:       lpad:
7414 // DEBUG2-NEXT:    [[TMP3:%.*]] = landingpad { ptr, i32 }
7415 // DEBUG2-NEXT:    cleanup, !dbg [[DBG181]]
7416 // DEBUG2-NEXT:    [[TMP4:%.*]] = extractvalue { ptr, i32 } [[TMP3]], 0, !dbg [[DBG181]]
7417 // DEBUG2-NEXT:    store ptr [[TMP4]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG181]]
7418 // DEBUG2-NEXT:    [[TMP5:%.*]] = extractvalue { ptr, i32 } [[TMP3]], 1, !dbg [[DBG181]]
7419 // DEBUG2-NEXT:    store i32 [[TMP5]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG181]]
7420 // DEBUG2-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT2]], align 8, !dbg [[DBG184]]
7421 // DEBUG2-NEXT:    [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAYINIT_BEGIN1]], [[TMP6]], !dbg [[DBG184]]
7422 // DEBUG2-NEXT:    br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG184]]
7423 // DEBUG2:       arraydestroy.body:
7424 // DEBUG2-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP6]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG184]]
7425 // DEBUG2-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG184]]
7426 // DEBUG2-NEXT:    call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]], !dbg [[DBG184]]
7427 // DEBUG2-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAYINIT_BEGIN1]], !dbg [[DBG184]]
7428 // DEBUG2-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG184]]
7429 // DEBUG2:       arraydestroy.done6:
7430 // DEBUG2-NEXT:    br label [[EHCLEANUP:%.*]], !dbg [[DBG184]]
7431 // DEBUG2:       lpad10:
7432 // DEBUG2-NEXT:    [[TMP7:%.*]] = landingpad { ptr, i32 }
7433 // DEBUG2-NEXT:    cleanup, !dbg [[DBG181]]
7434 // DEBUG2-NEXT:    [[TMP8:%.*]] = extractvalue { ptr, i32 } [[TMP7]], 0, !dbg [[DBG181]]
7435 // DEBUG2-NEXT:    store ptr [[TMP8]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG181]]
7436 // DEBUG2-NEXT:    [[TMP9:%.*]] = extractvalue { ptr, i32 } [[TMP7]], 1, !dbg [[DBG181]]
7437 // DEBUG2-NEXT:    store i32 [[TMP9]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG181]]
7438 // DEBUG2-NEXT:    [[TMP10:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT9]], align 8, !dbg [[DBG188]]
7439 // DEBUG2-NEXT:    [[ARRAYDESTROY_ISEMPTY16:%.*]] = icmp eq ptr [[ARRAYINIT_BEGIN8]], [[TMP10]], !dbg [[DBG188]]
7440 // DEBUG2-NEXT:    br i1 [[ARRAYDESTROY_ISEMPTY16]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17:%.*]], !dbg [[DBG188]]
7441 // DEBUG2:       arraydestroy.body17:
7442 // DEBUG2-NEXT:    [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi ptr [ [[TMP10]], [[LPAD10]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ], !dbg [[DBG188]]
7443 // DEBUG2-NEXT:    [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1, !dbg [[DBG188]]
7444 // DEBUG2-NEXT:    call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR4]], !dbg [[DBG188]]
7445 // DEBUG2-NEXT:    [[ARRAYDESTROY_DONE20:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT19]], [[ARRAYINIT_BEGIN8]], !dbg [[DBG188]]
7446 // DEBUG2-NEXT:    br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]], !dbg [[DBG188]]
7447 // DEBUG2:       arraydestroy.done21:
7448 // DEBUG2-NEXT:    br label [[EHCLEANUP]], !dbg [[DBG188]]
7449 // DEBUG2:       ehcleanup:
7450 // DEBUG2-NEXT:    [[TMP11:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG183]]
7451 // DEBUG2-NEXT:    [[PAD_ARRAYBEGIN:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYINIT_BEGIN]], i64 0, i64 0, !dbg [[DBG183]]
7452 // DEBUG2-NEXT:    [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP11]], i64 0, i64 0, !dbg [[DBG183]]
7453 // DEBUG2-NEXT:    [[ARRAYDESTROY_ISEMPTY22:%.*]] = icmp eq ptr [[PAD_ARRAYBEGIN]], [[PAD_ARRAYEND]], !dbg [[DBG183]]
7454 // DEBUG2-NEXT:    br i1 [[ARRAYDESTROY_ISEMPTY22]], label [[ARRAYDESTROY_DONE27:%.*]], label [[ARRAYDESTROY_BODY23:%.*]], !dbg [[DBG183]]
7455 // DEBUG2:       arraydestroy.body23:
7456 // DEBUG2-NEXT:    [[ARRAYDESTROY_ELEMENTPAST24:%.*]] = phi ptr [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT25:%.*]], [[ARRAYDESTROY_BODY23]] ], !dbg [[DBG183]]
7457 // DEBUG2-NEXT:    [[ARRAYDESTROY_ELEMENT25]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST24]], i64 -1, !dbg [[DBG183]]
7458 // DEBUG2-NEXT:    call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT25]]) #[[ATTR4]], !dbg [[DBG183]]
7459 // DEBUG2-NEXT:    [[ARRAYDESTROY_DONE26:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT25]], [[PAD_ARRAYBEGIN]], !dbg [[DBG183]]
7460 // DEBUG2-NEXT:    br i1 [[ARRAYDESTROY_DONE26]], label [[ARRAYDESTROY_DONE27]], label [[ARRAYDESTROY_BODY23]], !dbg [[DBG183]]
7461 // DEBUG2:       arraydestroy.done27:
7462 // DEBUG2-NEXT:    br label [[EH_RESUME:%.*]], !dbg [[DBG183]]
7463 // DEBUG2:       eh.resume:
7464 // DEBUG2-NEXT:    [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG183]]
7465 // DEBUG2-NEXT:    [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG183]]
7466 // DEBUG2-NEXT:    [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG183]]
7467 // DEBUG2-NEXT:    [[LPAD_VAL28:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG183]]
7468 // DEBUG2-NEXT:    resume { ptr, i32 } [[LPAD_VAL28]], !dbg [[DBG183]]
7469 //
7470 //
7471 // DEBUG2-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_..4
7472 // DEBUG2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG192:![0-9]+]] {
7473 // DEBUG2-NEXT:  entry:
7474 // DEBUG2-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
7475 // DEBUG2-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
7476 // DEBUG2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[DOTADDR]], metadata [[META193:![0-9]+]], metadata !DIExpression()), !dbg [[DBG194:![0-9]+]]
7477 // DEBUG2-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG194]]
7478 // DEBUG2-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP1]], i64 6, !dbg [[DBG194]]
7479 // DEBUG2-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG194]]
7480 // DEBUG2:       arraydestroy.body:
7481 // DEBUG2-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG194]]
7482 // DEBUG2-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG194]]
7483 // DEBUG2-NEXT:    call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]], !dbg [[DBG194]]
7484 // DEBUG2-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[TMP1]], !dbg [[DBG194]]
7485 // DEBUG2-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG194]]
7486 // DEBUG2:       arraydestroy.done1:
7487 // DEBUG2-NEXT:    ret void, !dbg [[DBG195:![0-9]+]]
7488 //
7489 //
7490 // DEBUG2-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
7491 // DEBUG2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG196:![0-9]+]] {
7492 // DEBUG2-NEXT:  entry:
7493 // DEBUG2-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
7494 // DEBUG2-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
7495 // DEBUG2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[DOTADDR]], metadata [[META199:![0-9]+]], metadata !DIExpression()), !dbg [[DBG200:![0-9]+]]
7496 // DEBUG2-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG200]]
7497 // DEBUG2:       arraydestroy.body:
7498 // DEBUG2-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 6), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG200]]
7499 // DEBUG2-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG200]]
7500 // DEBUG2-NEXT:    call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]], !dbg [[DBG200]]
7501 // DEBUG2-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[DBG200]]
7502 // DEBUG2-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG200]]
7503 // DEBUG2:       arraydestroy.done1:
7504 // DEBUG2-NEXT:    ret void, !dbg [[DBG200]]
7505 //
7506 //
7507 // DEBUG2-LABEL: define {{[^@]+}}@main
7508 // DEBUG2-SAME: () #[[ATTR5:[0-9]+]] personality ptr @__gxx_personality_v0 !dbg [[DBG52:![0-9]+]] {
7509 // DEBUG2-NEXT:  entry:
7510 // DEBUG2-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
7511 // DEBUG2-NEXT:    [[RES:%.*]] = alloca i32, align 4
7512 // DEBUG2-NEXT:    [[EXN_SLOT:%.*]] = alloca ptr, align 8
7513 // DEBUG2-NEXT:    [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4
7514 // DEBUG2-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB9:[0-9]+]])
7515 // DEBUG2-NEXT:    store i32 0, ptr [[RETVAL]], align 4
7516 // DEBUG2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[RES]], metadata [[META201:![0-9]+]], metadata !DIExpression()), !dbg [[DBG202:![0-9]+]]
7517 // DEBUG2-NEXT:    [[TMP1:%.*]] = load atomic i8, ptr @_ZGVZ4mainE2sm acquire, align 8, !dbg [[DBG203:![0-9]+]]
7518 // DEBUG2-NEXT:    [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP1]], 0, !dbg [[DBG203]]
7519 // DEBUG2-NEXT:    br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG203]], !prof [[PROF204:![0-9]+]]
7520 // DEBUG2:       init.check:
7521 // DEBUG2-NEXT:    [[TMP2:%.*]] = call i32 @__cxa_guard_acquire(ptr @_ZGVZ4mainE2sm) #[[ATTR4]], !dbg [[DBG203]]
7522 // DEBUG2-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0, !dbg [[DBG203]]
7523 // DEBUG2-NEXT:    br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]], !dbg [[DBG203]]
7524 // DEBUG2:       init:
7525 // DEBUG2-NEXT:    [[TMP3:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB7:[0-9]+]]), !dbg [[DBG203]]
7526 // DEBUG2-NEXT:    call void @__kmpc_threadprivate_register(ptr @[[GLOB7]], ptr @_ZZ4mainE2sm, ptr @.__kmpc_global_ctor_..5, ptr null, ptr @.__kmpc_global_dtor_..6), !dbg [[DBG203]]
7527 // DEBUG2-NEXT:    [[TMP4:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB9]], i32 [[TMP0]], ptr @_ZL3gs1, i64 4, ptr @_ZL3gs1.cache.), !dbg [[DBG205:![0-9]+]]
7528 // DEBUG2-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP4]], i32 0, i32 0, !dbg [[DBG206:![0-9]+]]
7529 // DEBUG2-NEXT:    [[TMP5:%.*]] = load i32, ptr [[A]], align 4, !dbg [[DBG206]]
7530 // DEBUG2-NEXT:    invoke void @_ZZ4mainEN5SmainC1Ei(ptr noundef nonnull align 8 dereferenceable(24) @_ZZ4mainE2sm, i32 noundef [[TMP5]])
7531 // DEBUG2-NEXT:    to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG207:![0-9]+]]
7532 // DEBUG2:       invoke.cont:
7533 // DEBUG2-NEXT:    [[TMP6:%.*]] = call i32 @__cxa_atexit(ptr @_ZZ4mainEN5SmainD1Ev, ptr @_ZZ4mainE2sm, ptr @__dso_handle) #[[ATTR4]], !dbg [[DBG203]]
7534 // DEBUG2-NEXT:    call void @__cxa_guard_release(ptr @_ZGVZ4mainE2sm) #[[ATTR4]], !dbg [[DBG203]]
7535 // DEBUG2-NEXT:    br label [[INIT_END]], !dbg [[DBG203]]
7536 // DEBUG2:       init.end:
7537 // DEBUG2-NEXT:    [[TMP7:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB11:[0-9]+]], i32 [[TMP0]], ptr @_ZN6Static1sE, i64 8, ptr @_ZN6Static1sE.cache.), !dbg [[DBG208:![0-9]+]]
7538 // DEBUG2-NEXT:    [[A1:%.*]] = getelementptr inbounds [[STRUCT_S3:%.*]], ptr [[TMP7]], i32 0, i32 0, !dbg [[DBG209:![0-9]+]]
7539 // DEBUG2-NEXT:    [[TMP8:%.*]] = load i32, ptr [[A1]], align 4, !dbg [[DBG209]]
7540 // DEBUG2-NEXT:    store i32 [[TMP8]], ptr [[RES]], align 4, !dbg [[DBG210:![0-9]+]]
7541 // DEBUG2-NEXT:    [[TMP9:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB13:[0-9]+]], i32 [[TMP0]], ptr @_ZZ4mainE2sm, i64 24, ptr @_ZZ4mainE2sm.cache.), !dbg [[DBG211:![0-9]+]]
7542 // DEBUG2-NEXT:    [[A2:%.*]] = getelementptr inbounds [[STRUCT_SMAIN:%.*]], ptr [[TMP9]], i32 0, i32 0, !dbg [[DBG212:![0-9]+]]
7543 // DEBUG2-NEXT:    [[TMP10:%.*]] = load i32, ptr [[A2]], align 8, !dbg [[DBG212]]
7544 // DEBUG2-NEXT:    [[TMP11:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG213:![0-9]+]]
7545 // DEBUG2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP10]], !dbg [[DBG213]]
7546 // DEBUG2-NEXT:    store i32 [[ADD]], ptr [[RES]], align 4, !dbg [[DBG213]]
7547 // DEBUG2-NEXT:    [[TMP12:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB15:[0-9]+]], i32 [[TMP0]], ptr @_ZL3gs1, i64 4, ptr @_ZL3gs1.cache.), !dbg [[DBG214:![0-9]+]]
7548 // DEBUG2-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP12]], i32 0, i32 0, !dbg [[DBG215:![0-9]+]]
7549 // DEBUG2-NEXT:    [[TMP13:%.*]] = load i32, ptr [[A3]], align 4, !dbg [[DBG215]]
7550 // DEBUG2-NEXT:    [[TMP14:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG216:![0-9]+]]
7551 // DEBUG2-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP14]], [[TMP13]], !dbg [[DBG216]]
7552 // DEBUG2-NEXT:    store i32 [[ADD4]], ptr [[RES]], align 4, !dbg [[DBG216]]
7553 // DEBUG2-NEXT:    [[TMP15:%.*]] = load i32, ptr @_ZL3gs2, align 8, !dbg [[DBG217:![0-9]+]]
7554 // DEBUG2-NEXT:    [[TMP16:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG218:![0-9]+]]
7555 // DEBUG2-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP16]], [[TMP15]], !dbg [[DBG218]]
7556 // DEBUG2-NEXT:    store i32 [[ADD5]], ptr [[RES]], align 4, !dbg [[DBG218]]
7557 // DEBUG2-NEXT:    [[TMP17:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB17:[0-9]+]], i32 [[TMP0]], ptr @gs3, i64 12, ptr @gs3.cache.), !dbg [[DBG219:![0-9]+]]
7558 // DEBUG2-NEXT:    [[A6:%.*]] = getelementptr inbounds [[STRUCT_S5:%.*]], ptr [[TMP17]], i32 0, i32 0, !dbg [[DBG220:![0-9]+]]
7559 // DEBUG2-NEXT:    [[TMP18:%.*]] = load i32, ptr [[A6]], align 4, !dbg [[DBG220]]
7560 // DEBUG2-NEXT:    [[TMP19:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG221:![0-9]+]]
7561 // DEBUG2-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP19]], [[TMP18]], !dbg [[DBG221]]
7562 // DEBUG2-NEXT:    store i32 [[ADD7]], ptr [[RES]], align 4, !dbg [[DBG221]]
7563 // DEBUG2-NEXT:    [[TMP20:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB19:[0-9]+]], i32 [[TMP0]], ptr @arr_x, i64 24, ptr @arr_x.cache.), !dbg [[DBG222:![0-9]+]]
7564 // DEBUG2-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP20]], i64 0, i64 1, !dbg [[DBG222]]
7565 // DEBUG2-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG222]]
7566 // DEBUG2-NEXT:    [[A9:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYIDX8]], i32 0, i32 0, !dbg [[DBG223:![0-9]+]]
7567 // DEBUG2-NEXT:    [[TMP21:%.*]] = load i32, ptr [[A9]], align 4, !dbg [[DBG223]]
7568 // DEBUG2-NEXT:    [[TMP22:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG224:![0-9]+]]
7569 // DEBUG2-NEXT:    [[ADD10:%.*]] = add nsw i32 [[TMP22]], [[TMP21]], !dbg [[DBG224]]
7570 // DEBUG2-NEXT:    store i32 [[ADD10]], ptr [[RES]], align 4, !dbg [[DBG224]]
7571 // DEBUG2-NEXT:    [[TMP23:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB21:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STIiE2stE, i64 4, ptr @_ZN2STIiE2stE.cache.), !dbg [[DBG225:![0-9]+]]
7572 // DEBUG2-NEXT:    [[TMP24:%.*]] = load i32, ptr [[TMP23]], align 4, !dbg [[DBG225]]
7573 // DEBUG2-NEXT:    [[TMP25:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG226:![0-9]+]]
7574 // DEBUG2-NEXT:    [[ADD11:%.*]] = add nsw i32 [[TMP25]], [[TMP24]], !dbg [[DBG226]]
7575 // DEBUG2-NEXT:    store i32 [[ADD11]], ptr [[RES]], align 4, !dbg [[DBG226]]
7576 // DEBUG2-NEXT:    [[TMP26:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB23:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STIfE2stE, i64 4, ptr @_ZN2STIfE2stE.cache.), !dbg [[DBG227:![0-9]+]]
7577 // DEBUG2-NEXT:    [[TMP27:%.*]] = load float, ptr [[TMP26]], align 4, !dbg [[DBG227]]
7578 // DEBUG2-NEXT:    [[CONV:%.*]] = fptosi float [[TMP27]] to i32, !dbg [[DBG227]]
7579 // DEBUG2-NEXT:    [[TMP28:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG228:![0-9]+]]
7580 // DEBUG2-NEXT:    [[ADD12:%.*]] = add nsw i32 [[TMP28]], [[CONV]], !dbg [[DBG228]]
7581 // DEBUG2-NEXT:    store i32 [[ADD12]], ptr [[RES]], align 4, !dbg [[DBG228]]
7582 // DEBUG2-NEXT:    [[TMP29:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB25:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STI2S4E2stE, i64 8, ptr @_ZN2STI2S4E2stE.cache.), !dbg [[DBG229:![0-9]+]]
7583 // DEBUG2-NEXT:    [[A13:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[TMP29]], i32 0, i32 0, !dbg [[DBG230:![0-9]+]]
7584 // DEBUG2-NEXT:    [[TMP30:%.*]] = load i32, ptr [[A13]], align 4, !dbg [[DBG230]]
7585 // DEBUG2-NEXT:    [[TMP31:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG231:![0-9]+]]
7586 // DEBUG2-NEXT:    [[ADD14:%.*]] = add nsw i32 [[TMP31]], [[TMP30]], !dbg [[DBG231]]
7587 // DEBUG2-NEXT:    store i32 [[ADD14]], ptr [[RES]], align 4, !dbg [[DBG231]]
7588 // DEBUG2-NEXT:    [[TMP32:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG232:![0-9]+]]
7589 // DEBUG2-NEXT:    ret i32 [[TMP32]], !dbg [[DBG233:![0-9]+]]
7590 // DEBUG2:       lpad:
7591 // DEBUG2-NEXT:    [[TMP33:%.*]] = landingpad { ptr, i32 }
7592 // DEBUG2-NEXT:    cleanup, !dbg [[DBG234:![0-9]+]]
7593 // DEBUG2-NEXT:    [[TMP34:%.*]] = extractvalue { ptr, i32 } [[TMP33]], 0, !dbg [[DBG234]]
7594 // DEBUG2-NEXT:    store ptr [[TMP34]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG234]]
7595 // DEBUG2-NEXT:    [[TMP35:%.*]] = extractvalue { ptr, i32 } [[TMP33]], 1, !dbg [[DBG234]]
7596 // DEBUG2-NEXT:    store i32 [[TMP35]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG234]]
7597 // DEBUG2-NEXT:    call void @__cxa_guard_abort(ptr @_ZGVZ4mainE2sm) #[[ATTR4]], !dbg [[DBG203]]
7598 // DEBUG2-NEXT:    br label [[EH_RESUME:%.*]], !dbg [[DBG203]]
7599 // DEBUG2:       eh.resume:
7600 // DEBUG2-NEXT:    [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG203]]
7601 // DEBUG2-NEXT:    [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG203]]
7602 // DEBUG2-NEXT:    [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG203]]
7603 // DEBUG2-NEXT:    [[LPAD_VAL15:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG203]]
7604 // DEBUG2-NEXT:    resume { ptr, i32 } [[LPAD_VAL15]], !dbg [[DBG203]]
7605 //
7606 //
7607 // DEBUG2-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_..5
7608 // DEBUG2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG235:![0-9]+]] {
7609 // DEBUG2-NEXT:  entry:
7610 // DEBUG2-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
7611 // DEBUG2-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB5:[0-9]+]])
7612 // DEBUG2-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
7613 // DEBUG2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[DOTADDR]], metadata [[META236:![0-9]+]], metadata !DIExpression()), !dbg [[DBG237:![0-9]+]]
7614 // DEBUG2-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG238:![0-9]+]]
7615 // DEBUG2-NEXT:    [[TMP3:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB5]], i32 [[TMP1]], ptr @_ZL3gs1, i64 4, ptr @_ZL3gs1.cache.), !dbg [[DBG239:![0-9]+]]
7616 // DEBUG2-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP3]], i32 0, i32 0, !dbg [[DBG240:![0-9]+]]
7617 // DEBUG2-NEXT:    [[TMP4:%.*]] = load i32, ptr [[A]], align 4, !dbg [[DBG240]]
7618 // DEBUG2-NEXT:    call void @_ZZ4mainEN5SmainC1Ei(ptr noundef nonnull align 8 dereferenceable(24) [[TMP2]], i32 noundef [[TMP4]]), !dbg [[DBG241:![0-9]+]]
7619 // DEBUG2-NEXT:    [[TMP5:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG238]]
7620 // DEBUG2-NEXT:    ret ptr [[TMP5]], !dbg [[DBG238]]
7621 //
7622 //
7623 // DEBUG2-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC1Ei
7624 // DEBUG2-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG242:![0-9]+]] {
7625 // DEBUG2-NEXT:  entry:
7626 // DEBUG2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
7627 // DEBUG2-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
7628 // DEBUG2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
7629 // DEBUG2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META243:![0-9]+]], metadata !DIExpression()), !dbg [[DBG245:![0-9]+]]
7630 // DEBUG2-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
7631 // DEBUG2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META246:![0-9]+]], metadata !DIExpression()), !dbg [[DBG247:![0-9]+]]
7632 // DEBUG2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
7633 // DEBUG2-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG248:![0-9]+]]
7634 // DEBUG2-NEXT:    call void @_ZZ4mainEN5SmainC2Ei(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG248]]
7635 // DEBUG2-NEXT:    ret void, !dbg [[DBG249:![0-9]+]]
7636 //
7637 //
7638 // DEBUG2-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_..6
7639 // DEBUG2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG250:![0-9]+]] {
7640 // DEBUG2-NEXT:  entry:
7641 // DEBUG2-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
7642 // DEBUG2-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
7643 // DEBUG2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[DOTADDR]], metadata [[META251:![0-9]+]], metadata !DIExpression()), !dbg [[DBG252:![0-9]+]]
7644 // DEBUG2-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG252]]
7645 // DEBUG2-NEXT:    call void @_ZZ4mainEN5SmainD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[TMP1]]) #[[ATTR4]], !dbg [[DBG252]]
7646 // DEBUG2-NEXT:    ret void, !dbg [[DBG253:![0-9]+]]
7647 //
7648 //
7649 // DEBUG2-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD1Ev
7650 // DEBUG2-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] align 2 !dbg [[DBG254:![0-9]+]] {
7651 // DEBUG2-NEXT:  entry:
7652 // DEBUG2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
7653 // DEBUG2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
7654 // DEBUG2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META255:![0-9]+]], metadata !DIExpression()), !dbg [[DBG256:![0-9]+]]
7655 // DEBUG2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
7656 // DEBUG2-NEXT:    call void @_ZZ4mainEN5SmainD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR4]], !dbg [[DBG257:![0-9]+]]
7657 // DEBUG2-NEXT:    ret void, !dbg [[DBG258:![0-9]+]]
7658 //
7659 //
7660 // DEBUG2-LABEL: define {{[^@]+}}@_Z6foobarv
7661 // DEBUG2-SAME: () #[[ATTR6:[0-9]+]] !dbg [[DBG259:![0-9]+]] {
7662 // DEBUG2-NEXT:  entry:
7663 // DEBUG2-NEXT:    [[RES:%.*]] = alloca i32, align 4
7664 // DEBUG2-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB27:[0-9]+]])
7665 // DEBUG2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[RES]], metadata [[META260:![0-9]+]], metadata !DIExpression()), !dbg [[DBG261:![0-9]+]]
7666 // DEBUG2-NEXT:    [[TMP1:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB27]], i32 [[TMP0]], ptr @_ZN6Static1sE, i64 8, ptr @_ZN6Static1sE.cache.), !dbg [[DBG262:![0-9]+]]
7667 // DEBUG2-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S3:%.*]], ptr [[TMP1]], i32 0, i32 0, !dbg [[DBG263:![0-9]+]]
7668 // DEBUG2-NEXT:    [[TMP2:%.*]] = load i32, ptr [[A]], align 4, !dbg [[DBG263]]
7669 // DEBUG2-NEXT:    store i32 [[TMP2]], ptr [[RES]], align 4, !dbg [[DBG264:![0-9]+]]
7670 // DEBUG2-NEXT:    [[TMP3:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB29:[0-9]+]], i32 [[TMP0]], ptr @_ZL3gs1, i64 4, ptr @_ZL3gs1.cache.), !dbg [[DBG265:![0-9]+]]
7671 // DEBUG2-NEXT:    [[A1:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP3]], i32 0, i32 0, !dbg [[DBG266:![0-9]+]]
7672 // DEBUG2-NEXT:    [[TMP4:%.*]] = load i32, ptr [[A1]], align 4, !dbg [[DBG266]]
7673 // DEBUG2-NEXT:    [[TMP5:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG267:![0-9]+]]
7674 // DEBUG2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP5]], [[TMP4]], !dbg [[DBG267]]
7675 // DEBUG2-NEXT:    store i32 [[ADD]], ptr [[RES]], align 4, !dbg [[DBG267]]
7676 // DEBUG2-NEXT:    [[TMP6:%.*]] = load i32, ptr @_ZL3gs2, align 8, !dbg [[DBG268:![0-9]+]]
7677 // DEBUG2-NEXT:    [[TMP7:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG269:![0-9]+]]
7678 // DEBUG2-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP7]], [[TMP6]], !dbg [[DBG269]]
7679 // DEBUG2-NEXT:    store i32 [[ADD2]], ptr [[RES]], align 4, !dbg [[DBG269]]
7680 // DEBUG2-NEXT:    [[TMP8:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB31:[0-9]+]], i32 [[TMP0]], ptr @gs3, i64 12, ptr @gs3.cache.), !dbg [[DBG270:![0-9]+]]
7681 // DEBUG2-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S5:%.*]], ptr [[TMP8]], i32 0, i32 0, !dbg [[DBG271:![0-9]+]]
7682 // DEBUG2-NEXT:    [[TMP9:%.*]] = load i32, ptr [[A3]], align 4, !dbg [[DBG271]]
7683 // DEBUG2-NEXT:    [[TMP10:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG272:![0-9]+]]
7684 // DEBUG2-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP10]], [[TMP9]], !dbg [[DBG272]]
7685 // DEBUG2-NEXT:    store i32 [[ADD4]], ptr [[RES]], align 4, !dbg [[DBG272]]
7686 // DEBUG2-NEXT:    [[TMP11:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB33:[0-9]+]], i32 [[TMP0]], ptr @arr_x, i64 24, ptr @arr_x.cache.), !dbg [[DBG273:![0-9]+]]
7687 // DEBUG2-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP11]], i64 0, i64 1, !dbg [[DBG273]]
7688 // DEBUG2-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG273]]
7689 // DEBUG2-NEXT:    [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYIDX5]], i32 0, i32 0, !dbg [[DBG274:![0-9]+]]
7690 // DEBUG2-NEXT:    [[TMP12:%.*]] = load i32, ptr [[A6]], align 4, !dbg [[DBG274]]
7691 // DEBUG2-NEXT:    [[TMP13:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG275:![0-9]+]]
7692 // DEBUG2-NEXT:    [[ADD7:%.*]] = add nsw i32 [[TMP13]], [[TMP12]], !dbg [[DBG275]]
7693 // DEBUG2-NEXT:    store i32 [[ADD7]], ptr [[RES]], align 4, !dbg [[DBG275]]
7694 // DEBUG2-NEXT:    [[TMP14:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB35:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STIiE2stE, i64 4, ptr @_ZN2STIiE2stE.cache.), !dbg [[DBG276:![0-9]+]]
7695 // DEBUG2-NEXT:    [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4, !dbg [[DBG276]]
7696 // DEBUG2-NEXT:    [[TMP16:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG277:![0-9]+]]
7697 // DEBUG2-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP16]], [[TMP15]], !dbg [[DBG277]]
7698 // DEBUG2-NEXT:    store i32 [[ADD8]], ptr [[RES]], align 4, !dbg [[DBG277]]
7699 // DEBUG2-NEXT:    [[TMP17:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB37:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STIfE2stE, i64 4, ptr @_ZN2STIfE2stE.cache.), !dbg [[DBG278:![0-9]+]]
7700 // DEBUG2-NEXT:    [[TMP18:%.*]] = load float, ptr [[TMP17]], align 4, !dbg [[DBG278]]
7701 // DEBUG2-NEXT:    [[CONV:%.*]] = fptosi float [[TMP18]] to i32, !dbg [[DBG278]]
7702 // DEBUG2-NEXT:    [[TMP19:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG279:![0-9]+]]
7703 // DEBUG2-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP19]], [[CONV]], !dbg [[DBG279]]
7704 // DEBUG2-NEXT:    store i32 [[ADD9]], ptr [[RES]], align 4, !dbg [[DBG279]]
7705 // DEBUG2-NEXT:    [[TMP20:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB39:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STI2S4E2stE, i64 8, ptr @_ZN2STI2S4E2stE.cache.), !dbg [[DBG280:![0-9]+]]
7706 // DEBUG2-NEXT:    [[A10:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[TMP20]], i32 0, i32 0, !dbg [[DBG281:![0-9]+]]
7707 // DEBUG2-NEXT:    [[TMP21:%.*]] = load i32, ptr [[A10]], align 4, !dbg [[DBG281]]
7708 // DEBUG2-NEXT:    [[TMP22:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG282:![0-9]+]]
7709 // DEBUG2-NEXT:    [[ADD11:%.*]] = add nsw i32 [[TMP22]], [[TMP21]], !dbg [[DBG282]]
7710 // DEBUG2-NEXT:    store i32 [[ADD11]], ptr [[RES]], align 4, !dbg [[DBG282]]
7711 // DEBUG2-NEXT:    [[TMP23:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG283:![0-9]+]]
7712 // DEBUG2-NEXT:    ret i32 [[TMP23]], !dbg [[DBG284:![0-9]+]]
7713 //
7714 //
7715 // DEBUG2-LABEL: define {{[^@]+}}@__cxx_global_var_init.7
7716 // DEBUG2-SAME: () #[[ATTR0]] comdat($_ZN2STI2S4E2stE) !dbg [[DBG285:![0-9]+]] {
7717 // DEBUG2-NEXT:  entry:
7718 // DEBUG2-NEXT:    [[TMP0:%.*]] = load i8, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG286:![0-9]+]]
7719 // DEBUG2-NEXT:    [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG286]]
7720 // DEBUG2-NEXT:    br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG286]]
7721 // DEBUG2:       init.check:
7722 // DEBUG2-NEXT:    store i8 1, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG286]]
7723 // DEBUG2-NEXT:    [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB41:[0-9]+]]), !dbg [[DBG286]]
7724 // DEBUG2-NEXT:    call void @__kmpc_threadprivate_register(ptr @[[GLOB41]], ptr @_ZN2STI2S4E2stE, ptr @.__kmpc_global_ctor_..8, ptr null, ptr @.__kmpc_global_dtor_..9), !dbg [[DBG286]]
7725 // DEBUG2-NEXT:    call void @_ZN2S4C1Ei(ptr noundef nonnull align 4 dereferenceable(8) @_ZN2STI2S4E2stE, i32 noundef 23), !dbg [[DBG287:![0-9]+]]
7726 // DEBUG2-NEXT:    [[TMP2:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S4D1Ev, ptr @_ZN2STI2S4E2stE, ptr @__dso_handle) #[[ATTR4]], !dbg [[DBG286]]
7727 // DEBUG2-NEXT:    br label [[INIT_END]], !dbg [[DBG286]]
7728 // DEBUG2:       init.end:
7729 // DEBUG2-NEXT:    ret void, !dbg [[DBG289:![0-9]+]]
7730 //
7731 //
7732 // DEBUG2-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_..8
7733 // DEBUG2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG290:![0-9]+]] {
7734 // DEBUG2-NEXT:  entry:
7735 // DEBUG2-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
7736 // DEBUG2-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
7737 // DEBUG2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[DOTADDR]], metadata [[META291:![0-9]+]], metadata !DIExpression()), !dbg [[DBG292:![0-9]+]]
7738 // DEBUG2-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG293:![0-9]+]]
7739 // DEBUG2-NEXT:    call void @_ZN2S4C1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[TMP1]], i32 noundef 23), !dbg [[DBG294:![0-9]+]]
7740 // DEBUG2-NEXT:    [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG293]]
7741 // DEBUG2-NEXT:    ret ptr [[TMP2]], !dbg [[DBG293]]
7742 //
7743 //
7744 // DEBUG2-LABEL: define {{[^@]+}}@_ZN2S4C1Ei
7745 // DEBUG2-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG295:![0-9]+]] {
7746 // DEBUG2-NEXT:  entry:
7747 // DEBUG2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
7748 // DEBUG2-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
7749 // DEBUG2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
7750 // DEBUG2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META296:![0-9]+]], metadata !DIExpression()), !dbg [[DBG298:![0-9]+]]
7751 // DEBUG2-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
7752 // DEBUG2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META299:![0-9]+]], metadata !DIExpression()), !dbg [[DBG300:![0-9]+]]
7753 // DEBUG2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
7754 // DEBUG2-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG301:![0-9]+]]
7755 // DEBUG2-NEXT:    call void @_ZN2S4C2Ei(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG301]]
7756 // DEBUG2-NEXT:    ret void, !dbg [[DBG302:![0-9]+]]
7757 //
7758 //
7759 // DEBUG2-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_..9
7760 // DEBUG2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG303:![0-9]+]] {
7761 // DEBUG2-NEXT:  entry:
7762 // DEBUG2-NEXT:    [[DOTADDR:%.*]] = alloca ptr, align 8
7763 // DEBUG2-NEXT:    store ptr [[TMP0]], ptr [[DOTADDR]], align 8
7764 // DEBUG2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[DOTADDR]], metadata [[META304:![0-9]+]], metadata !DIExpression()), !dbg [[DBG305:![0-9]+]]
7765 // DEBUG2-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG305]]
7766 // DEBUG2-NEXT:    call void @_ZN2S4D1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[TMP1]]) #[[ATTR4]], !dbg [[DBG305]]
7767 // DEBUG2-NEXT:    ret void, !dbg [[DBG306:![0-9]+]]
7768 //
7769 //
7770 // DEBUG2-LABEL: define {{[^@]+}}@_ZN2S4D1Ev
7771 // DEBUG2-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG307:![0-9]+]] {
7772 // DEBUG2-NEXT:  entry:
7773 // DEBUG2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
7774 // DEBUG2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
7775 // DEBUG2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META308:![0-9]+]], metadata !DIExpression()), !dbg [[DBG309:![0-9]+]]
7776 // DEBUG2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
7777 // DEBUG2-NEXT:    call void @_ZN2S4D2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]], !dbg [[DBG310:![0-9]+]]
7778 // DEBUG2-NEXT:    ret void, !dbg [[DBG311:![0-9]+]]
7779 //
7780 //
7781 // DEBUG2-LABEL: define {{[^@]+}}@_ZN2S1C2Ei
7782 // DEBUG2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG312:![0-9]+]] {
7783 // DEBUG2-NEXT:  entry:
7784 // DEBUG2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
7785 // DEBUG2-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
7786 // DEBUG2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
7787 // DEBUG2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META313:![0-9]+]], metadata !DIExpression()), !dbg [[DBG314:![0-9]+]]
7788 // DEBUG2-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
7789 // DEBUG2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META315:![0-9]+]], metadata !DIExpression()), !dbg [[DBG316:![0-9]+]]
7790 // DEBUG2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
7791 // DEBUG2-NEXT:    [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG317:![0-9]+]]
7792 // DEBUG2-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG318:![0-9]+]]
7793 // DEBUG2-NEXT:    store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG317]]
7794 // DEBUG2-NEXT:    ret void, !dbg [[DBG319:![0-9]+]]
7795 //
7796 //
7797 // DEBUG2-LABEL: define {{[^@]+}}@_ZN2S1D2Ev
7798 // DEBUG2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG320:![0-9]+]] {
7799 // DEBUG2-NEXT:  entry:
7800 // DEBUG2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
7801 // DEBUG2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
7802 // DEBUG2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META321:![0-9]+]], metadata !DIExpression()), !dbg [[DBG322:![0-9]+]]
7803 // DEBUG2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
7804 // DEBUG2-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG323:![0-9]+]]
7805 // DEBUG2-NEXT:    store i32 0, ptr [[A]], align 4, !dbg [[DBG325:![0-9]+]]
7806 // DEBUG2-NEXT:    ret void, !dbg [[DBG326:![0-9]+]]
7807 //
7808 //
7809 // DEBUG2-LABEL: define {{[^@]+}}@_ZN2S2C2Ei
7810 // DEBUG2-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG327:![0-9]+]] {
7811 // DEBUG2-NEXT:  entry:
7812 // DEBUG2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
7813 // DEBUG2-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
7814 // DEBUG2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
7815 // DEBUG2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META328:![0-9]+]], metadata !DIExpression()), !dbg [[DBG329:![0-9]+]]
7816 // DEBUG2-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
7817 // DEBUG2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META330:![0-9]+]], metadata !DIExpression()), !dbg [[DBG331:![0-9]+]]
7818 // DEBUG2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
7819 // DEBUG2-NEXT:    [[A2:%.*]] = getelementptr inbounds [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG332:![0-9]+]]
7820 // DEBUG2-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG333:![0-9]+]]
7821 // DEBUG2-NEXT:    store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG332]]
7822 // DEBUG2-NEXT:    ret void, !dbg [[DBG334:![0-9]+]]
7823 //
7824 //
7825 // DEBUG2-LABEL: define {{[^@]+}}@_ZN2S2D2Ev
7826 // DEBUG2-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG335:![0-9]+]] {
7827 // DEBUG2-NEXT:  entry:
7828 // DEBUG2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
7829 // DEBUG2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
7830 // DEBUG2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META336:![0-9]+]], metadata !DIExpression()), !dbg [[DBG337:![0-9]+]]
7831 // DEBUG2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
7832 // DEBUG2-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG338:![0-9]+]]
7833 // DEBUG2-NEXT:    store i32 0, ptr [[A]], align 8, !dbg [[DBG340:![0-9]+]]
7834 // DEBUG2-NEXT:    ret void, !dbg [[DBG341:![0-9]+]]
7835 //
7836 //
7837 // DEBUG2-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC2Ei
7838 // DEBUG2-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR3]] align 2 !dbg [[DBG342:![0-9]+]] {
7839 // DEBUG2-NEXT:  entry:
7840 // DEBUG2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
7841 // DEBUG2-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
7842 // DEBUG2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
7843 // DEBUG2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META343:![0-9]+]], metadata !DIExpression()), !dbg [[DBG344:![0-9]+]]
7844 // DEBUG2-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
7845 // DEBUG2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META345:![0-9]+]], metadata !DIExpression()), !dbg [[DBG346:![0-9]+]]
7846 // DEBUG2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
7847 // DEBUG2-NEXT:    [[A2:%.*]] = getelementptr inbounds [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG347:![0-9]+]]
7848 // DEBUG2-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG348:![0-9]+]]
7849 // DEBUG2-NEXT:    store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG347]]
7850 // DEBUG2-NEXT:    ret void, !dbg [[DBG349:![0-9]+]]
7851 //
7852 //
7853 // DEBUG2-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD2Ev
7854 // DEBUG2-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] align 2 !dbg [[DBG350:![0-9]+]] {
7855 // DEBUG2-NEXT:  entry:
7856 // DEBUG2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
7857 // DEBUG2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
7858 // DEBUG2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META351:![0-9]+]], metadata !DIExpression()), !dbg [[DBG352:![0-9]+]]
7859 // DEBUG2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
7860 // DEBUG2-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG353:![0-9]+]]
7861 // DEBUG2-NEXT:    store i32 0, ptr [[A]], align 8, !dbg [[DBG355:![0-9]+]]
7862 // DEBUG2-NEXT:    ret void, !dbg [[DBG356:![0-9]+]]
7863 //
7864 //
7865 // DEBUG2-LABEL: define {{[^@]+}}@_ZN2S4C2Ei
7866 // DEBUG2-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG357:![0-9]+]] {
7867 // DEBUG2-NEXT:  entry:
7868 // DEBUG2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
7869 // DEBUG2-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
7870 // DEBUG2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
7871 // DEBUG2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META358:![0-9]+]], metadata !DIExpression()), !dbg [[DBG359:![0-9]+]]
7872 // DEBUG2-NEXT:    store i32 [[A]], ptr [[A_ADDR]], align 4
7873 // DEBUG2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META360:![0-9]+]], metadata !DIExpression()), !dbg [[DBG361:![0-9]+]]
7874 // DEBUG2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
7875 // DEBUG2-NEXT:    [[A2:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG362:![0-9]+]]
7876 // DEBUG2-NEXT:    [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG363:![0-9]+]]
7877 // DEBUG2-NEXT:    store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG362]]
7878 // DEBUG2-NEXT:    ret void, !dbg [[DBG364:![0-9]+]]
7879 //
7880 //
7881 // DEBUG2-LABEL: define {{[^@]+}}@_ZN2S4D2Ev
7882 // DEBUG2-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG365:![0-9]+]] {
7883 // DEBUG2-NEXT:  entry:
7884 // DEBUG2-NEXT:    [[THIS_ADDR:%.*]] = alloca ptr, align 8
7885 // DEBUG2-NEXT:    store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
7886 // DEBUG2-NEXT:    call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META366:![0-9]+]], metadata !DIExpression()), !dbg [[DBG367:![0-9]+]]
7887 // DEBUG2-NEXT:    [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
7888 // DEBUG2-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG368:![0-9]+]]
7889 // DEBUG2-NEXT:    store i32 0, ptr [[A]], align 4, !dbg [[DBG370:![0-9]+]]
7890 // DEBUG2-NEXT:    ret void, !dbg [[DBG371:![0-9]+]]
7891 //
7892 //
7893 // DEBUG2-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_threadprivate_codegen.cpp
7894 // DEBUG2-SAME: () #[[ATTR0]] !dbg [[DBG372:![0-9]+]] {
7895 // DEBUG2-NEXT:  entry:
7896 // DEBUG2-NEXT:    call void @__cxx_global_var_init(), !dbg [[DBG373:![0-9]+]]
7897 // DEBUG2-NEXT:    call void @__cxx_global_var_init.1(), !dbg [[DBG373]]
7898 // DEBUG2-NEXT:    call void @__cxx_global_var_init.2(), !dbg [[DBG373]]
7899 // DEBUG2-NEXT:    ret void
7900 //