lld/test/ELF/arm-adr.s

   1 // REQUIRES: arm
   2 // RUN: llvm-mc --triple=armv7a-none-eabi --arm-add-build-attributes -filetype=obj -o %t.o %s
   3 // RUN: ld.lld %t.o -o %t
   4 // RUN: llvm-objdump -d --no-show-raw-insn --triple=armv7a-none-eabi %t | FileCheck %s
   5
   6 /// Test the short range cases of R_ARM_ALU_PC_G0. The range of the instruction
   7 /// depends on the number of trailing zeros of the displacement. In practice
   8 /// the maximum effective range will be 1024 bytes, which is a 4-byte aligned
   9 /// instruction to a 4-byte aligned word.
  10
  11  .arm
  12  .section .os1, "ax", %progbits
  13  .balign 1024
  14  .word 0
  15  .word 0
  16  .word 0
  17  .word 0
  18 dat1:
  19  .word 0
  20 dat2:
  21  .word 0
  22
  23  .section .os2, "ax", %progbits
  24  .balign 1024
  25  .global _start
  26  .type _start, %function
  27 _start:
  28 /// adr r0, dat1
  29  .inst 0xe24f0008
  30  .reloc 0, R_ARM_ALU_PC_G0, dat1
  31 /// adr r0, dat2
  32  .inst 0xe24f0008
  33  .reloc 4, R_ARM_ALU_PC_G0, dat2
  34 /// adr r0, dat3
  35  .inst 0xe24f0008
  36  .reloc 8, R_ARM_ALU_PC_G0, dat3
  37 /// adr r0, dat4
  38  .inst 0xe24f0008
  39  .reloc 0xc, R_ARM_ALU_PC_G0, dat4
  40
  41  .section .os3, "ax", %progbits
  42  .balign 1024
  43  .word 0
  44  .word 0
  45  .word 0
  46  .word 0
  47 dat3:
  48  .word 0
  49 dat4:
  50  .word 0
  51
  52  .section .os4, "ax", %progbits
  53  .thumb
  54  .type tfunc, %function
  55 tfunc:
  56   bx lr
  57
  58  .section .os5, "ax", %progbits
  59  .arm
  60  .type arm_func, %function
  61
  62 arm_func:
  63  .balign 4
  64 /// adr r0, tfunc
  65  .inst 0xe24f0008
  66  .reloc 0, R_ARM_ALU_PC_G0, tfunc
  67 /// adr r0, afunc
  68  .inst 0xe24f0008
  69  .reloc 4, R_ARM_ALU_PC_G0, afunc
  70  bx lr
  71
  72  .section .os6, "ax", %progbits
  73  .type afunc, %function
  74  .balign 4
  75 afunc:
  76  bx lr
  77
  78 // CHECK:      00020410 <dat1>:
  79 // CHECK-NEXT: 20410: andeq   r0, r0, r0
  80
  81 // CHECK:      00020414 <dat2>:
  82 // CHECK-NEXT: 20414: andeq   r0, r0, r0
  83
  84 // CHECK:     00020800 <_start>:
  85 /// 0x20800 + 0x8 - 0x3f8 = 0x11410 = dat1
  86 // CHECK-NEXT: 20800: sub     r0, pc, #1016
  87 /// 0x20804 + 0x8 - 0x3f8 = 0x11414 = dat2
  88 // CHECK-NEXT: 20804: sub     r0, pc, #1016
  89 /// 0x20808 + 0x8 + 0x400 = 0x11c10 = dat3
  90 // CHECK-NEXT: 20808: add     r0, pc, #64, #28
  91 /// 0x2080c + 0x8 + 0x400 = 0x11c14 = dat4
  92 // CHECK-NEXT: 2080c: add     r0, pc, #64, #28
  93
  94 // CHECK:      00020c10 <dat3>:
  95 // CHECK-NEXT: 20c10: andeq   r0, r0, r0
  96
  97 // CHECK:      00020c14 <dat4>:
  98 // CHECK-NEXT: 20c14: andeq   r0, r0, r0
  99
 100 // CHECK:      00020c18 <tfunc>:
 101 // CHECK-NEXT: 20c18: bx      lr
 102
 103 // CHECK:      00020c1c <arm_func>:
 104 /// 0x20c1c + 0x8 - 0xb = 11c19 = tfunc
 105 // CHECK-NEXT: 20c1c: sub     r0, pc, #11
 106 /// 0x20c20 + 0x8 = 0x11c28 = afunc
 107 // CHECK-NEXT: 20c20: add     r0, pc, #0
 108 // CHECK-NEXT: 20c24: bx      lr
 109
 110 // CHECK:      00020c28 <afunc>:
 111 // CHECK-NEXT: 20c28: bx      lr