2 // RUN
: llvm-mc
-filetype
=obj
-triple
=armv7a-linux-gnueabihf
--arm-add-build-attributes
%s
-o
%t.o
3 // RUN
: ld.lld
--fix-cortex-a8
-verbose
%t.o
-o
%t2
4 // RUN
: llvm-objdump
-d
%t2
--start-address
=0x21ffa --stop-address
=0x22002 --no-show-raw-insn | FileCheck
--check-prefix
=CALLSITE1
%s
5 // RUN
: llvm-objdump
-d
%t2
--start-address
=0x22ffa --stop-address
=0x23002 --no-show-raw-insn | FileCheck
--check-prefix
=CALLSITE2
%s
6 // RUN
: llvm-objdump
-d
%t2
--start-address
=0x23ffa --stop-address
=0x24002 --no-show-raw-insn | FileCheck
--check-prefix
=CALLSITE3
%s
7 // RUN
: llvm-objdump
-d
%t2
--start-address
=0x24ffa --stop-address
=0x25006 --no-show-raw-insn | FileCheck
--check-prefix
=CALLSITE4
%s
8 // RUN
: llvm-objdump
-d
%t2
--start-address
=0x25ffe --stop-address
=0x26002 --no-show-raw-insn | FileCheck
--check-prefix
=CALLSITE5
%s
9 // RUN
: llvm-objdump
-d
%t2
--start-address
=0x27000 --stop-address
=0x28004 --no-show-raw-insn | FileCheck
--check-prefix
=CALLSITE6
%s
10 // RUN
: llvm-objdump
-d
%t2
--start-address
=0x28002 --stop-address
=0x29006 --no-show-raw-insn | FileCheck
--check-prefix
=CALLSITE7
%s
12 /// Test boundary conditions of the cortex-a8 erratum. The following cases
13 /// should
not trigger the Erratum
25 /// 32-bit branch spans
2 4KiB regions
, preceded by
a 32-bit branch so no patch
30 // CALLSITE1
: 00021ffa
<target
>:
31 // CALLSITE1-NEXT
: 21ffa
: b.w
0x21ffa <target
>
32 // CALLSITE1-NEXT
: 21ffe
: b.w
0x21ffa <target
>
35 .type target2, %function
37 /// 32-bit Branch
and link spans
2 4KiB regions
, preceded by
a 16-bit
38 /// instruction so no patch expected.
43 // CALLSITE2
: 00022ffa
<target2
>:
44 // CALLSITE2-NEXT
: 22ffa
: nop
45 // CALLSITE2-NEXT
: 22ffc
: nop
46 // CALLSITE2-NEXT
: 22ffe
: bl 0x22ffa <target2
>
49 .type target3, %function
51 /// 32-bit conditional branch spans
2 4KiB regions
, preceded by
a 32-bit
52 /// non branch instruction
, branch is backwards but outside
4KiB region. So
57 // CALLSITE3
: 00023ffa
<target3
>:
58 // CALLSITE3-NEXT
: 23ffa
: nop.w
59 // CALLSITE3-NEXT
: 23ffe
: beq.w
0x22ffa <target2
>
62 .type source4, %function
64 /// 32-bit conditional branch spans
2 4KiB regions
, preceded by
a 32-bit
65 /// non branch instruction
, branch is forwards to
2nd region so expect no patch.
72 // CALLSITE4
: 00024ffa
<source4
>:
73 // CALLSITE4-NEXT
: 24ffa
: nop.w
74 // CALLSITE4-NEXT
: 24ffe
: beq.w
0x25002 <target4
>
75 // CALLSITE4
: 00025002 <target4
>:
76 // CALLSITE4-NEXT
: 25002: nop.w
79 .type target5, %function
82 /// 32-bit conditional branch spans
2 4KiB regions
, preceded by the encoding of
83 /// a 32-bit thumb instruction
, but in ARM state
(illegal instruction
), we
84 /// should
not decode
and match it as Thumb
, expect no patch.
86 .short 0xbf00 // nop encoding in Thumb for alignment
87 .inst 0xf3af8000 /// nop.w encoding in Thumb
93 // CALLSITE5
: 00025ffe
<source5
>:
94 // CALLSITE5-NEXT
: 25ffe
: beq.w
0x25ff8 <target5
>
96 /// Edge case where two word sequence starts at offset
0xffc, check that
97 /// we don
't match. In this case the branch will be completely in the 2nd
98 /// region and the branch will target the second region. This will pass a
99 /// branch destination in the same region test, but not the branch must have
100 /// and address of the form xxxxxffe.
102 .type target6, %function
104 /// Make sure target of branch is in the same 4KiB region as the branch.
108 // CALLSITE6: 00027000 <target6>:
109 // CALLSITE6-NEXT: 27000: bl 0x27000 <target6>
111 /// Edge case where two word sequence starts at offset 0xffe, check that
112 /// we don't match. In this case the branch will
be completely in the
2nd
113 /// region
and the branch will target the second region. This will pass
a
114 /// branch destination in the same region test
, but
not the branch must have
115 /// and address of the form xxxxxffe.
117 .type target7, %function
119 /// Make sure target of branch is in the same
4KiB region as the branch.
123 // CALLSITE7
: 00028002 <target7
>:
124 // CALLSITE7
: 28002: bl 0x28002 <target7
>