lld/test/ELF/mips-elf-flags.s

   1 # REQUIRES: mips
   2 # Check generation of MIPS specific ELF header flags.
   3
   4 # RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux \
   5 # RUN:         %S/Inputs/mips-dynamic.s -o %t-so.o
   6 # RUN: ld.lld %t-so.o --gc-sections -shared -o %t.so
   7 # RUN: llvm-readobj -h -A %t.so | FileCheck -check-prefix=SO %s
   8
   9 # RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux %s -o %t.o
  10 # RUN: ld.lld %t.o -o %t.exe
  11 # RUN: llvm-readobj -h -A %t.exe | FileCheck -check-prefix=EXE %s
  12
  13 # RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux \
  14 # RUN:         -mcpu=mips32r2 %s -o %t-r2.o
  15 # RUN: ld.lld %t-r2.o -o %t-r2.exe
  16 # RUN: llvm-readobj -h -A %t-r2.exe | FileCheck -check-prefix=EXE-R2 %s
  17
  18 # RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux \
  19 # RUN:         -mcpu=mips32r2 %s -o %t-r2.o
  20 # RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux \
  21 # RUN:         -mcpu=mips32r5 %S/Inputs/mips-dynamic.s -o %t-r5.o
  22 # RUN: ld.lld %t-r2.o %t-r5.o -o %t-r5.exe
  23 # RUN: llvm-readobj -h -A %t-r5.exe | FileCheck -check-prefix=EXE-R5 %s
  24
  25 # RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux \
  26 # RUN:         -mcpu=mips32r6 %s -o %t-r6.o
  27 # RUN: ld.lld %t-r6.o -o %t-r6.exe
  28 # RUN: llvm-readobj -h -A %t-r6.exe | FileCheck -check-prefix=EXE-R6 %s
  29
  30 # RUN: llvm-mc -filetype=obj -triple=mips64-unknown-linux \
  31 # RUN:         -position-independent -mcpu=octeon %s -o %t.o
  32 # RUN: ld.lld %t.o -o %t.exe
  33 # RUN: llvm-readobj -h -A %t.exe | FileCheck -check-prefix=OCTEON %s
  34
  35 # RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux %s -o %t.o
  36 # RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux \
  37 # RUN:         -mattr=micromips %S/Inputs/mips-fpic.s -o %t-mm.o
  38 # RUN: ld.lld %t.o %t-mm.o -o %t.exe
  39 # RUN: llvm-readobj -h -A %t.exe | FileCheck -check-prefix=MICRO %s
  40
  41   .text
  42   .globl  __start
  43 __start:
  44   nop
  45
  46 # SO:      Flags [
  47 # SO-NEXT:   EF_MIPS_ABI_O32
  48 # SO-NEXT:   EF_MIPS_ARCH_32
  49 # SO-NEXT:   EF_MIPS_CPIC
  50 # SO-NEXT:   EF_MIPS_PIC
  51 # SO-NEXT: ]
  52 # SO:      MIPS ABI Flags {
  53 # SO-NEXT:   Version: 0
  54 # SO-NEXT:   ISA: MIPS32
  55 # SO-NEXT:   ISA Extension: None
  56 # SO-NEXT:   ASEs [
  57 # SO-NEXT:   ]
  58 # SO-NEXT:   FP ABI: Hard float (double precision)
  59 # SO-NEXT:   GPR size: 32
  60 # SO-NEXT:   CPR1 size: 32
  61 # SO-NEXT:   CPR2 size: 0
  62 # SO-NEXT:   Flags 1 [
  63 # SO-NEXT:     ODDSPREG
  64 # SO-NEXT:   ]
  65 # SO-NEXT:   Flags 2: 0x0
  66 # SO-NEXT: }
  67
  68 # EXE:      Flags [
  69 # EXE-NEXT:   EF_MIPS_ABI_O32
  70 # EXE-NEXT:   EF_MIPS_ARCH_32
  71 # EXE-NEXT:   EF_MIPS_CPIC
  72 # EXE-NEXT: ]
  73 # EXE:      MIPS ABI Flags {
  74 # EXE-NEXT:   Version: 0
  75 # EXE-NEXT:   ISA: MIPS32
  76 # EXE-NEXT:   ISA Extension: None
  77 # EXE-NEXT:   ASEs [
  78 # EXE-NEXT:   ]
  79 # EXE-NEXT:   FP ABI: Hard float (double precision)
  80 # EXE-NEXT:   GPR size: 32
  81 # EXE-NEXT:   CPR1 size: 32
  82 # EXE-NEXT:   CPR2 size: 0
  83 # EXE-NEXT:   Flags 1 [
  84 # EXE-NEXT:     ODDSPREG
  85 # EXE-NEXT:   ]
  86 # EXE-NEXT:   Flags 2: 0x0
  87 # EXE-NEXT: }
  88
  89 # EXE-R2:      Flags [
  90 # EXE-R2-NEXT:   EF_MIPS_ABI_O32
  91 # EXE-R2-NEXT:   EF_MIPS_ARCH_32R2
  92 # EXE-R2-NEXT:   EF_MIPS_CPIC
  93 # EXE-R2-NEXT: ]
  94 # EXE-R2:      MIPS ABI Flags {
  95 # EXE-R2-NEXT:   Version: 0
  96 # EXE-R2-NEXT:   ISA: MIPS32r2
  97 # EXE-R2-NEXT:   ISA Extension: None
  98 # EXE-R2-NEXT:   ASEs [
  99 # EXE-R2-NEXT:   ]
 100 # EXE-R2-NEXT:   FP ABI: Hard float (double precision)
 101 # EXE-R2-NEXT:   GPR size: 32
 102 # EXE-R2-NEXT:   CPR1 size: 32
 103 # EXE-R2-NEXT:   CPR2 size: 0
 104 # EXE-R2-NEXT:   Flags 1 [
 105 # EXE-R2-NEXT:     ODDSPREG
 106 # EXE-R2-NEXT:   ]
 107 # EXE-R2-NEXT:   Flags 2: 0x0
 108 # EXE-R2-NEXT: }
 109
 110 # EXE-R5:      Flags [
 111 # EXE-R5-NEXT:   EF_MIPS_ABI_O32
 112 # EXE-R5-NEXT:   EF_MIPS_ARCH_32R2
 113 # EXE-R5-NEXT:   EF_MIPS_CPIC
 114 # EXE-R5-NEXT: ]
 115 # EXE-R5:      MIPS ABI Flags {
 116 # EXE-R5-NEXT:   Version: 0
 117 # EXE-R5-NEXT:   ISA: MIPS32r5
 118 # EXE-R5-NEXT:   ISA Extension: None
 119 # EXE-R5-NEXT:   ASEs [
 120 # EXE-R5-NEXT:   ]
 121 # EXE-R5-NEXT:   FP ABI: Hard float (double precision)
 122 # EXE-R5-NEXT:   GPR size: 32
 123 # EXE-R5-NEXT:   CPR1 size: 32
 124 # EXE-R5-NEXT:   CPR2 size: 0
 125 # EXE-R5-NEXT:   Flags 1 [
 126 # EXE-R5-NEXT:     ODDSPREG
 127 # EXE-R5-NEXT:   ]
 128 # EXE-R5-NEXT:   Flags 2: 0x0
 129 # EXE-R5-NEXT: }
 130
 131 # EXE-R6:      Flags [
 132 # EXE-R6-NEXT:   EF_MIPS_ABI_O32
 133 # EXE-R6-NEXT:   EF_MIPS_ARCH_32R6
 134 # EXE-R6-NEXT:   EF_MIPS_CPIC
 135 # EXE-R6-NEXT:   EF_MIPS_NAN2008
 136 # EXE-R6-NEXT: ]
 137 # EXE-R6:      MIPS ABI Flags {
 138 # EXE-R6-NEXT:   Version: 0
 139 # EXE-R6-NEXT:   ISA: MIPS32
 140 # EXE-R6-NEXT:   ISA Extension: None
 141 # EXE-R6-NEXT:   ASEs [
 142 # EXE-R6-NEXT:   ]
 143 # EXE-R6-NEXT:   FP ABI: Hard float (32-bit CPU, 64-bit FPU)
 144 # EXE-R6-NEXT:   GPR size: 32
 145 # EXE-R6-NEXT:   CPR1 size: 64
 146 # EXE-R6-NEXT:   CPR2 size: 0
 147 # EXE-R6-NEXT:   Flags 1 [
 148 # EXE-R6-NEXT:     ODDSPREG
 149 # EXE-R6-NEXT:   ]
 150 # EXE-R6-NEXT:   Flags 2: 0x0
 151 # EXE-R6-NEXT: }
 152
 153 # OCTEON:      Flags [
 154 # OCTEON-NEXT:   EF_MIPS_ARCH_64R2
 155 # OCTEON-NEXT:   EF_MIPS_CPIC
 156 # OCTEON-NEXT:   EF_MIPS_MACH_OCTEON
 157 # OCTEON-NEXT:   EF_MIPS_PIC
 158 # OCTEON-NEXT: ]
 159 # OCTEON:      MIPS ABI Flags {
 160 # OCTEON-NEXT:   Version: 0
 161 # OCTEON-NEXT:   ISA: MIPS64r2
 162 # OCTEON-NEXT:   ISA Extension: Cavium Networks Octeon
 163 # OCTEON-NEXT:   ASEs [
 164 # OCTEON-NEXT:   ]
 165 # OCTEON-NEXT:   FP ABI: Hard float (double precision)
 166 # OCTEON-NEXT:   GPR size: 64
 167 # OCTEON-NEXT:   CPR1 size: 64
 168 # OCTEON-NEXT:   CPR2 size: 0
 169 # OCTEON-NEXT:   Flags 1 [
 170 # OCTEON-NEXT:     ODDSPREG
 171 # OCTEON-NEXT:   ]
 172 # OCTEON-NEXT:   Flags 2: 0x0
 173 # OCTEON-NEXT: }
 174
 175 # MICRO:      Flags [
 176 # MICRO-NEXT:   EF_MIPS_ABI_O32
 177 # MICRO-NEXT:   EF_MIPS_ARCH_32
 178 # MICRO-NEXT:   EF_MIPS_CPIC
 179 # MICRO-NEXT:   EF_MIPS_MICROMIPS
 180 # MICRO-NEXT: ]
 181 # MICRO:      MIPS ABI Flags {
 182 # MICRO-NEXT:   Version: 0
 183 # MICRO-NEXT:   ISA: MIPS32
 184 # MICRO-NEXT:   ISA Extension: None
 185 # MICRO-NEXT:   ASEs [
 186 # MICRO-NEXT:     microMIPS
 187 # MICRO-NEXT:   ]
 188 # MICRO-NEXT:   FP ABI: Hard float (double precision)
 189 # MICRO-NEXT:   GPR size: 32
 190 # MICRO-NEXT:   CPR1 size: 32
 191 # MICRO-NEXT:   CPR2 size: 0
 192 # MICRO-NEXT:   Flags 1 [
 193 # MICRO-NEXT:     ODDSPREG
 194 # MICRO-NEXT:   ]
 195 # MICRO-NEXT:   Flags 2: 0x0
 196 # MICRO-NEXT: }