lldb/source/Plugins/Process/Utility/RegisterInfos_arm64.h

   1 //===-- RegisterInfos_arm64.h -----------------------------------*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8
   9 #ifdef DECLARE_REGISTER_INFOS_ARM64_STRUCT
  10
  11 #include <cstddef>
  12
  13 #include "lldb/lldb-defines.h"
  14 #include "lldb/lldb-enumerations.h"
  15 #include "lldb/lldb-private.h"
  16
  17 #include "Utility/ARM64_DWARF_Registers.h"
  18 #include "Utility/ARM64_ehframe_Registers.h"
  19
  20 #ifndef GPR_OFFSET
  21 #error GPR_OFFSET must be defined before including this header file
  22 #endif
  23
  24 #ifndef GPR_OFFSET_NAME
  25 #error GPR_OFFSET_NAME must be defined before including this header file
  26 #endif
  27
  28 #ifndef FPU_OFFSET
  29 #error FPU_OFFSET must be defined before including this header file
  30 #endif
  31
  32 #ifndef FPU_OFFSET_NAME
  33 #error FPU_OFFSET_NAME must be defined before including this header file
  34 #endif
  35
  36 #ifndef EXC_OFFSET_NAME
  37 #error EXC_OFFSET_NAME must be defined before including this header file
  38 #endif
  39
  40 #ifndef DBG_OFFSET_NAME
  41 #error DBG_OFFSET_NAME must be defined before including this header file
  42 #endif
  43
  44 #ifndef DEFINE_DBG
  45 #error DEFINE_DBG must be defined before including this header file
  46 #endif
  47
  48 // Offsets for a little-endian layout of the register context
  49 #define GPR_W_PSEUDO_REG_ENDIAN_OFFSET 0
  50 #define FPU_S_PSEUDO_REG_ENDIAN_OFFSET 0
  51 #define FPU_D_PSEUDO_REG_ENDIAN_OFFSET 0
  52
  53 enum {
  54   gpr_x0 = 0,
  55   gpr_x1,
  56   gpr_x2,
  57   gpr_x3,
  58   gpr_x4,
  59   gpr_x5,
  60   gpr_x6,
  61   gpr_x7,
  62   gpr_x8,
  63   gpr_x9,
  64   gpr_x10,
  65   gpr_x11,
  66   gpr_x12,
  67   gpr_x13,
  68   gpr_x14,
  69   gpr_x15,
  70   gpr_x16,
  71   gpr_x17,
  72   gpr_x18,
  73   gpr_x19,
  74   gpr_x20,
  75   gpr_x21,
  76   gpr_x22,
  77   gpr_x23,
  78   gpr_x24,
  79   gpr_x25,
  80   gpr_x26,
  81   gpr_x27,
  82   gpr_x28,
  83   gpr_x29 = 29,
  84   gpr_fp = gpr_x29,
  85   gpr_x30 = 30,
  86   gpr_lr = gpr_x30,
  87   gpr_ra = gpr_x30,
  88   gpr_x31 = 31,
  89   gpr_sp = gpr_x31,
  90   gpr_pc = 32,
  91   gpr_cpsr,
  92
  93   gpr_w0,
  94   gpr_w1,
  95   gpr_w2,
  96   gpr_w3,
  97   gpr_w4,
  98   gpr_w5,
  99   gpr_w6,
 100   gpr_w7,
 101   gpr_w8,
 102   gpr_w9,
 103   gpr_w10,
 104   gpr_w11,
 105   gpr_w12,
 106   gpr_w13,
 107   gpr_w14,
 108   gpr_w15,
 109   gpr_w16,
 110   gpr_w17,
 111   gpr_w18,
 112   gpr_w19,
 113   gpr_w20,
 114   gpr_w21,
 115   gpr_w22,
 116   gpr_w23,
 117   gpr_w24,
 118   gpr_w25,
 119   gpr_w26,
 120   gpr_w27,
 121   gpr_w28,
 122
 123   fpu_v0,
 124   fpu_v1,
 125   fpu_v2,
 126   fpu_v3,
 127   fpu_v4,
 128   fpu_v5,
 129   fpu_v6,
 130   fpu_v7,
 131   fpu_v8,
 132   fpu_v9,
 133   fpu_v10,
 134   fpu_v11,
 135   fpu_v12,
 136   fpu_v13,
 137   fpu_v14,
 138   fpu_v15,
 139   fpu_v16,
 140   fpu_v17,
 141   fpu_v18,
 142   fpu_v19,
 143   fpu_v20,
 144   fpu_v21,
 145   fpu_v22,
 146   fpu_v23,
 147   fpu_v24,
 148   fpu_v25,
 149   fpu_v26,
 150   fpu_v27,
 151   fpu_v28,
 152   fpu_v29,
 153   fpu_v30,
 154   fpu_v31,
 155
 156   fpu_s0,
 157   fpu_s1,
 158   fpu_s2,
 159   fpu_s3,
 160   fpu_s4,
 161   fpu_s5,
 162   fpu_s6,
 163   fpu_s7,
 164   fpu_s8,
 165   fpu_s9,
 166   fpu_s10,
 167   fpu_s11,
 168   fpu_s12,
 169   fpu_s13,
 170   fpu_s14,
 171   fpu_s15,
 172   fpu_s16,
 173   fpu_s17,
 174   fpu_s18,
 175   fpu_s19,
 176   fpu_s20,
 177   fpu_s21,
 178   fpu_s22,
 179   fpu_s23,
 180   fpu_s24,
 181   fpu_s25,
 182   fpu_s26,
 183   fpu_s27,
 184   fpu_s28,
 185   fpu_s29,
 186   fpu_s30,
 187   fpu_s31,
 188
 189   fpu_d0,
 190   fpu_d1,
 191   fpu_d2,
 192   fpu_d3,
 193   fpu_d4,
 194   fpu_d5,
 195   fpu_d6,
 196   fpu_d7,
 197   fpu_d8,
 198   fpu_d9,
 199   fpu_d10,
 200   fpu_d11,
 201   fpu_d12,
 202   fpu_d13,
 203   fpu_d14,
 204   fpu_d15,
 205   fpu_d16,
 206   fpu_d17,
 207   fpu_d18,
 208   fpu_d19,
 209   fpu_d20,
 210   fpu_d21,
 211   fpu_d22,
 212   fpu_d23,
 213   fpu_d24,
 214   fpu_d25,
 215   fpu_d26,
 216   fpu_d27,
 217   fpu_d28,
 218   fpu_d29,
 219   fpu_d30,
 220   fpu_d31,
 221
 222   fpu_fpsr,
 223   fpu_fpcr,
 224
 225   exc_far,
 226   exc_esr,
 227   exc_exception,
 228
 229   dbg_bvr0,
 230   dbg_bvr1,
 231   dbg_bvr2,
 232   dbg_bvr3,
 233   dbg_bvr4,
 234   dbg_bvr5,
 235   dbg_bvr6,
 236   dbg_bvr7,
 237   dbg_bvr8,
 238   dbg_bvr9,
 239   dbg_bvr10,
 240   dbg_bvr11,
 241   dbg_bvr12,
 242   dbg_bvr13,
 243   dbg_bvr14,
 244   dbg_bvr15,
 245
 246   dbg_bcr0,
 247   dbg_bcr1,
 248   dbg_bcr2,
 249   dbg_bcr3,
 250   dbg_bcr4,
 251   dbg_bcr5,
 252   dbg_bcr6,
 253   dbg_bcr7,
 254   dbg_bcr8,
 255   dbg_bcr9,
 256   dbg_bcr10,
 257   dbg_bcr11,
 258   dbg_bcr12,
 259   dbg_bcr13,
 260   dbg_bcr14,
 261   dbg_bcr15,
 262
 263   dbg_wvr0,
 264   dbg_wvr1,
 265   dbg_wvr2,
 266   dbg_wvr3,
 267   dbg_wvr4,
 268   dbg_wvr5,
 269   dbg_wvr6,
 270   dbg_wvr7,
 271   dbg_wvr8,
 272   dbg_wvr9,
 273   dbg_wvr10,
 274   dbg_wvr11,
 275   dbg_wvr12,
 276   dbg_wvr13,
 277   dbg_wvr14,
 278   dbg_wvr15,
 279
 280   dbg_wcr0,
 281   dbg_wcr1,
 282   dbg_wcr2,
 283   dbg_wcr3,
 284   dbg_wcr4,
 285   dbg_wcr5,
 286   dbg_wcr6,
 287   dbg_wcr7,
 288   dbg_wcr8,
 289   dbg_wcr9,
 290   dbg_wcr10,
 291   dbg_wcr11,
 292   dbg_wcr12,
 293   dbg_wcr13,
 294   dbg_wcr14,
 295   dbg_wcr15,
 296
 297   k_num_registers
 298 };
 299
 300 static uint32_t g_contained_x0[] = {gpr_x0, LLDB_INVALID_REGNUM};
 301 static uint32_t g_contained_x1[] = {gpr_x1, LLDB_INVALID_REGNUM};
 302 static uint32_t g_contained_x2[] = {gpr_x2, LLDB_INVALID_REGNUM};
 303 static uint32_t g_contained_x3[] = {gpr_x3, LLDB_INVALID_REGNUM};
 304 static uint32_t g_contained_x4[] = {gpr_x4, LLDB_INVALID_REGNUM};
 305 static uint32_t g_contained_x5[] = {gpr_x5, LLDB_INVALID_REGNUM};
 306 static uint32_t g_contained_x6[] = {gpr_x6, LLDB_INVALID_REGNUM};
 307 static uint32_t g_contained_x7[] = {gpr_x7, LLDB_INVALID_REGNUM};
 308 static uint32_t g_contained_x8[] = {gpr_x8, LLDB_INVALID_REGNUM};
 309 static uint32_t g_contained_x9[] = {gpr_x9, LLDB_INVALID_REGNUM};
 310 static uint32_t g_contained_x10[] = {gpr_x10, LLDB_INVALID_REGNUM};
 311 static uint32_t g_contained_x11[] = {gpr_x11, LLDB_INVALID_REGNUM};
 312 static uint32_t g_contained_x12[] = {gpr_x12, LLDB_INVALID_REGNUM};
 313 static uint32_t g_contained_x13[] = {gpr_x13, LLDB_INVALID_REGNUM};
 314 static uint32_t g_contained_x14[] = {gpr_x14, LLDB_INVALID_REGNUM};
 315 static uint32_t g_contained_x15[] = {gpr_x15, LLDB_INVALID_REGNUM};
 316 static uint32_t g_contained_x16[] = {gpr_x16, LLDB_INVALID_REGNUM};
 317 static uint32_t g_contained_x17[] = {gpr_x17, LLDB_INVALID_REGNUM};
 318 static uint32_t g_contained_x18[] = {gpr_x18, LLDB_INVALID_REGNUM};
 319 static uint32_t g_contained_x19[] = {gpr_x19, LLDB_INVALID_REGNUM};
 320 static uint32_t g_contained_x20[] = {gpr_x20, LLDB_INVALID_REGNUM};
 321 static uint32_t g_contained_x21[] = {gpr_x21, LLDB_INVALID_REGNUM};
 322 static uint32_t g_contained_x22[] = {gpr_x22, LLDB_INVALID_REGNUM};
 323 static uint32_t g_contained_x23[] = {gpr_x23, LLDB_INVALID_REGNUM};
 324 static uint32_t g_contained_x24[] = {gpr_x24, LLDB_INVALID_REGNUM};
 325 static uint32_t g_contained_x25[] = {gpr_x25, LLDB_INVALID_REGNUM};
 326 static uint32_t g_contained_x26[] = {gpr_x26, LLDB_INVALID_REGNUM};
 327 static uint32_t g_contained_x27[] = {gpr_x27, LLDB_INVALID_REGNUM};
 328 static uint32_t g_contained_x28[] = {gpr_x28, LLDB_INVALID_REGNUM};
 329
 330 static uint32_t g_w0_invalidates[] = {gpr_x0, LLDB_INVALID_REGNUM};
 331 static uint32_t g_w1_invalidates[] = {gpr_x1, LLDB_INVALID_REGNUM};
 332 static uint32_t g_w2_invalidates[] = {gpr_x2, LLDB_INVALID_REGNUM};
 333 static uint32_t g_w3_invalidates[] = {gpr_x3, LLDB_INVALID_REGNUM};
 334 static uint32_t g_w4_invalidates[] = {gpr_x4, LLDB_INVALID_REGNUM};
 335 static uint32_t g_w5_invalidates[] = {gpr_x5, LLDB_INVALID_REGNUM};
 336 static uint32_t g_w6_invalidates[] = {gpr_x6, LLDB_INVALID_REGNUM};
 337 static uint32_t g_w7_invalidates[] = {gpr_x7, LLDB_INVALID_REGNUM};
 338 static uint32_t g_w8_invalidates[] = {gpr_x8, LLDB_INVALID_REGNUM};
 339 static uint32_t g_w9_invalidates[] = {gpr_x9, LLDB_INVALID_REGNUM};
 340 static uint32_t g_w10_invalidates[] = {gpr_x10, LLDB_INVALID_REGNUM};
 341 static uint32_t g_w11_invalidates[] = {gpr_x11, LLDB_INVALID_REGNUM};
 342 static uint32_t g_w12_invalidates[] = {gpr_x12, LLDB_INVALID_REGNUM};
 343 static uint32_t g_w13_invalidates[] = {gpr_x13, LLDB_INVALID_REGNUM};
 344 static uint32_t g_w14_invalidates[] = {gpr_x14, LLDB_INVALID_REGNUM};
 345 static uint32_t g_w15_invalidates[] = {gpr_x15, LLDB_INVALID_REGNUM};
 346 static uint32_t g_w16_invalidates[] = {gpr_x16, LLDB_INVALID_REGNUM};
 347 static uint32_t g_w17_invalidates[] = {gpr_x17, LLDB_INVALID_REGNUM};
 348 static uint32_t g_w18_invalidates[] = {gpr_x18, LLDB_INVALID_REGNUM};
 349 static uint32_t g_w19_invalidates[] = {gpr_x19, LLDB_INVALID_REGNUM};
 350 static uint32_t g_w20_invalidates[] = {gpr_x20, LLDB_INVALID_REGNUM};
 351 static uint32_t g_w21_invalidates[] = {gpr_x21, LLDB_INVALID_REGNUM};
 352 static uint32_t g_w22_invalidates[] = {gpr_x22, LLDB_INVALID_REGNUM};
 353 static uint32_t g_w23_invalidates[] = {gpr_x23, LLDB_INVALID_REGNUM};
 354 static uint32_t g_w24_invalidates[] = {gpr_x24, LLDB_INVALID_REGNUM};
 355 static uint32_t g_w25_invalidates[] = {gpr_x25, LLDB_INVALID_REGNUM};
 356 static uint32_t g_w26_invalidates[] = {gpr_x26, LLDB_INVALID_REGNUM};
 357 static uint32_t g_w27_invalidates[] = {gpr_x27, LLDB_INVALID_REGNUM};
 358 static uint32_t g_w28_invalidates[] = {gpr_x28, LLDB_INVALID_REGNUM};
 359
 360 static uint32_t g_contained_v0[] = {fpu_v0, LLDB_INVALID_REGNUM};
 361 static uint32_t g_contained_v1[] = {fpu_v1, LLDB_INVALID_REGNUM};
 362 static uint32_t g_contained_v2[] = {fpu_v2, LLDB_INVALID_REGNUM};
 363 static uint32_t g_contained_v3[] = {fpu_v3, LLDB_INVALID_REGNUM};
 364 static uint32_t g_contained_v4[] = {fpu_v4, LLDB_INVALID_REGNUM};
 365 static uint32_t g_contained_v5[] = {fpu_v5, LLDB_INVALID_REGNUM};
 366 static uint32_t g_contained_v6[] = {fpu_v6, LLDB_INVALID_REGNUM};
 367 static uint32_t g_contained_v7[] = {fpu_v7, LLDB_INVALID_REGNUM};
 368 static uint32_t g_contained_v8[] = {fpu_v8, LLDB_INVALID_REGNUM};
 369 static uint32_t g_contained_v9[] = {fpu_v9, LLDB_INVALID_REGNUM};
 370 static uint32_t g_contained_v10[] = {fpu_v10, LLDB_INVALID_REGNUM};
 371 static uint32_t g_contained_v11[] = {fpu_v11, LLDB_INVALID_REGNUM};
 372 static uint32_t g_contained_v12[] = {fpu_v12, LLDB_INVALID_REGNUM};
 373 static uint32_t g_contained_v13[] = {fpu_v13, LLDB_INVALID_REGNUM};
 374 static uint32_t g_contained_v14[] = {fpu_v14, LLDB_INVALID_REGNUM};
 375 static uint32_t g_contained_v15[] = {fpu_v15, LLDB_INVALID_REGNUM};
 376 static uint32_t g_contained_v16[] = {fpu_v16, LLDB_INVALID_REGNUM};
 377 static uint32_t g_contained_v17[] = {fpu_v17, LLDB_INVALID_REGNUM};
 378 static uint32_t g_contained_v18[] = {fpu_v18, LLDB_INVALID_REGNUM};
 379 static uint32_t g_contained_v19[] = {fpu_v19, LLDB_INVALID_REGNUM};
 380 static uint32_t g_contained_v20[] = {fpu_v20, LLDB_INVALID_REGNUM};
 381 static uint32_t g_contained_v21[] = {fpu_v21, LLDB_INVALID_REGNUM};
 382 static uint32_t g_contained_v22[] = {fpu_v22, LLDB_INVALID_REGNUM};
 383 static uint32_t g_contained_v23[] = {fpu_v23, LLDB_INVALID_REGNUM};
 384 static uint32_t g_contained_v24[] = {fpu_v24, LLDB_INVALID_REGNUM};
 385 static uint32_t g_contained_v25[] = {fpu_v25, LLDB_INVALID_REGNUM};
 386 static uint32_t g_contained_v26[] = {fpu_v26, LLDB_INVALID_REGNUM};
 387 static uint32_t g_contained_v27[] = {fpu_v27, LLDB_INVALID_REGNUM};
 388 static uint32_t g_contained_v28[] = {fpu_v28, LLDB_INVALID_REGNUM};
 389 static uint32_t g_contained_v29[] = {fpu_v29, LLDB_INVALID_REGNUM};
 390 static uint32_t g_contained_v30[] = {fpu_v30, LLDB_INVALID_REGNUM};
 391 static uint32_t g_contained_v31[] = {fpu_v31, LLDB_INVALID_REGNUM};
 392
 393 static uint32_t g_s0_invalidates[] = {fpu_v0, fpu_d0, LLDB_INVALID_REGNUM};
 394 static uint32_t g_s1_invalidates[] = {fpu_v1, fpu_d1, LLDB_INVALID_REGNUM};
 395 static uint32_t g_s2_invalidates[] = {fpu_v2, fpu_d2, LLDB_INVALID_REGNUM};
 396 static uint32_t g_s3_invalidates[] = {fpu_v3, fpu_d3, LLDB_INVALID_REGNUM};
 397 static uint32_t g_s4_invalidates[] = {fpu_v4, fpu_d4, LLDB_INVALID_REGNUM};
 398 static uint32_t g_s5_invalidates[] = {fpu_v5, fpu_d5, LLDB_INVALID_REGNUM};
 399 static uint32_t g_s6_invalidates[] = {fpu_v6, fpu_d6, LLDB_INVALID_REGNUM};
 400 static uint32_t g_s7_invalidates[] = {fpu_v7, fpu_d7, LLDB_INVALID_REGNUM};
 401 static uint32_t g_s8_invalidates[] = {fpu_v8, fpu_d8, LLDB_INVALID_REGNUM};
 402 static uint32_t g_s9_invalidates[] = {fpu_v9, fpu_d9, LLDB_INVALID_REGNUM};
 403 static uint32_t g_s10_invalidates[] = {fpu_v10, fpu_d10, LLDB_INVALID_REGNUM};
 404 static uint32_t g_s11_invalidates[] = {fpu_v11, fpu_d11, LLDB_INVALID_REGNUM};
 405 static uint32_t g_s12_invalidates[] = {fpu_v12, fpu_d12, LLDB_INVALID_REGNUM};
 406 static uint32_t g_s13_invalidates[] = {fpu_v13, fpu_d13, LLDB_INVALID_REGNUM};
 407 static uint32_t g_s14_invalidates[] = {fpu_v14, fpu_d14, LLDB_INVALID_REGNUM};
 408 static uint32_t g_s15_invalidates[] = {fpu_v15, fpu_d15, LLDB_INVALID_REGNUM};
 409 static uint32_t g_s16_invalidates[] = {fpu_v16, fpu_d16, LLDB_INVALID_REGNUM};
 410 static uint32_t g_s17_invalidates[] = {fpu_v17, fpu_d17, LLDB_INVALID_REGNUM};
 411 static uint32_t g_s18_invalidates[] = {fpu_v18, fpu_d18, LLDB_INVALID_REGNUM};
 412 static uint32_t g_s19_invalidates[] = {fpu_v19, fpu_d19, LLDB_INVALID_REGNUM};
 413 static uint32_t g_s20_invalidates[] = {fpu_v20, fpu_d20, LLDB_INVALID_REGNUM};
 414 static uint32_t g_s21_invalidates[] = {fpu_v21, fpu_d21, LLDB_INVALID_REGNUM};
 415 static uint32_t g_s22_invalidates[] = {fpu_v22, fpu_d22, LLDB_INVALID_REGNUM};
 416 static uint32_t g_s23_invalidates[] = {fpu_v23, fpu_d23, LLDB_INVALID_REGNUM};
 417 static uint32_t g_s24_invalidates[] = {fpu_v24, fpu_d24, LLDB_INVALID_REGNUM};
 418 static uint32_t g_s25_invalidates[] = {fpu_v25, fpu_d25, LLDB_INVALID_REGNUM};
 419 static uint32_t g_s26_invalidates[] = {fpu_v26, fpu_d26, LLDB_INVALID_REGNUM};
 420 static uint32_t g_s27_invalidates[] = {fpu_v27, fpu_d27, LLDB_INVALID_REGNUM};
 421 static uint32_t g_s28_invalidates[] = {fpu_v28, fpu_d28, LLDB_INVALID_REGNUM};
 422 static uint32_t g_s29_invalidates[] = {fpu_v29, fpu_d29, LLDB_INVALID_REGNUM};
 423 static uint32_t g_s30_invalidates[] = {fpu_v30, fpu_d30, LLDB_INVALID_REGNUM};
 424 static uint32_t g_s31_invalidates[] = {fpu_v31, fpu_d31, LLDB_INVALID_REGNUM};
 425
 426 static uint32_t g_d0_invalidates[] = {fpu_v0, fpu_s0, LLDB_INVALID_REGNUM};
 427 static uint32_t g_d1_invalidates[] = {fpu_v1, fpu_s1, LLDB_INVALID_REGNUM};
 428 static uint32_t g_d2_invalidates[] = {fpu_v2, fpu_s2, LLDB_INVALID_REGNUM};
 429 static uint32_t g_d3_invalidates[] = {fpu_v3, fpu_s3, LLDB_INVALID_REGNUM};
 430 static uint32_t g_d4_invalidates[] = {fpu_v4, fpu_s4, LLDB_INVALID_REGNUM};
 431 static uint32_t g_d5_invalidates[] = {fpu_v5, fpu_s5, LLDB_INVALID_REGNUM};
 432 static uint32_t g_d6_invalidates[] = {fpu_v6, fpu_s6, LLDB_INVALID_REGNUM};
 433 static uint32_t g_d7_invalidates[] = {fpu_v7, fpu_s7, LLDB_INVALID_REGNUM};
 434 static uint32_t g_d8_invalidates[] = {fpu_v8, fpu_s8, LLDB_INVALID_REGNUM};
 435 static uint32_t g_d9_invalidates[] = {fpu_v9, fpu_s9, LLDB_INVALID_REGNUM};
 436 static uint32_t g_d10_invalidates[] = {fpu_v10, fpu_s10, LLDB_INVALID_REGNUM};
 437 static uint32_t g_d11_invalidates[] = {fpu_v11, fpu_s11, LLDB_INVALID_REGNUM};
 438 static uint32_t g_d12_invalidates[] = {fpu_v12, fpu_s12, LLDB_INVALID_REGNUM};
 439 static uint32_t g_d13_invalidates[] = {fpu_v13, fpu_s13, LLDB_INVALID_REGNUM};
 440 static uint32_t g_d14_invalidates[] = {fpu_v14, fpu_s14, LLDB_INVALID_REGNUM};
 441 static uint32_t g_d15_invalidates[] = {fpu_v15, fpu_s15, LLDB_INVALID_REGNUM};
 442 static uint32_t g_d16_invalidates[] = {fpu_v16, fpu_s16, LLDB_INVALID_REGNUM};
 443 static uint32_t g_d17_invalidates[] = {fpu_v17, fpu_s17, LLDB_INVALID_REGNUM};
 444 static uint32_t g_d18_invalidates[] = {fpu_v18, fpu_s18, LLDB_INVALID_REGNUM};
 445 static uint32_t g_d19_invalidates[] = {fpu_v19, fpu_s19, LLDB_INVALID_REGNUM};
 446 static uint32_t g_d20_invalidates[] = {fpu_v20, fpu_s20, LLDB_INVALID_REGNUM};
 447 static uint32_t g_d21_invalidates[] = {fpu_v21, fpu_s21, LLDB_INVALID_REGNUM};
 448 static uint32_t g_d22_invalidates[] = {fpu_v22, fpu_s22, LLDB_INVALID_REGNUM};
 449 static uint32_t g_d23_invalidates[] = {fpu_v23, fpu_s23, LLDB_INVALID_REGNUM};
 450 static uint32_t g_d24_invalidates[] = {fpu_v24, fpu_s24, LLDB_INVALID_REGNUM};
 451 static uint32_t g_d25_invalidates[] = {fpu_v25, fpu_s25, LLDB_INVALID_REGNUM};
 452 static uint32_t g_d26_invalidates[] = {fpu_v26, fpu_s26, LLDB_INVALID_REGNUM};
 453 static uint32_t g_d27_invalidates[] = {fpu_v27, fpu_s27, LLDB_INVALID_REGNUM};
 454 static uint32_t g_d28_invalidates[] = {fpu_v28, fpu_s28, LLDB_INVALID_REGNUM};
 455 static uint32_t g_d29_invalidates[] = {fpu_v29, fpu_s29, LLDB_INVALID_REGNUM};
 456 static uint32_t g_d30_invalidates[] = {fpu_v30, fpu_s30, LLDB_INVALID_REGNUM};
 457 static uint32_t g_d31_invalidates[] = {fpu_v31, fpu_s31, LLDB_INVALID_REGNUM};
 458
 459 // Generates register kinds array with DWARF, EH frame and generic kind
 460 #define MISC_KIND(reg, type, generic_kind)                                     \
 461   {                                                                            \
 462     arm64_ehframe::reg, arm64_dwarf::reg, generic_kind, LLDB_INVALID_REGNUM,   \
 463         type##_##reg                                                           \
 464   }
 465
 466 // Generates register kinds array for registers with only lldb kind
 467 #define LLDB_KIND(lldb_kind)                                                   \
 468   {                                                                            \
 469     LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,             \
 470         LLDB_INVALID_REGNUM, lldb_kind                                         \
 471   }
 472
 473 // Generates register kinds array for registers with only lldb kind
 474 #define KIND_ALL_INVALID                                                       \
 475   {                                                                            \
 476     LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,             \
 477         LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM                               \
 478   }
 479
 480 // Generates register kinds array for vector registers
 481 #define GPR64_KIND(reg, generic_kind) MISC_KIND(reg, gpr, generic_kind)
 482 #define VREG_KIND(reg) MISC_KIND(reg, fpu, LLDB_INVALID_REGNUM)
 483 #define MISC_GPR_KIND(lldb_kind) MISC_KIND(cpsr, gpr, LLDB_REGNUM_GENERIC_FLAGS)
 484 #define MISC_FPU_KIND(lldb_kind) LLDB_KIND(lldb_kind)
 485 #define MISC_EXC_KIND(lldb_kind) LLDB_KIND(lldb_kind)
 486
 487 // clang-format off
 488
 489 // Defines a 64-bit general purpose register
 490 #define DEFINE_GPR64(reg, generic_kind)                                        \
 491   {                                                                            \
 492     #reg, nullptr, 8, GPR_OFFSET(gpr_##reg), lldb::eEncodingUint,              \
 493         lldb::eFormatHex, GPR64_KIND(reg, generic_kind), nullptr, nullptr,     \
 494         nullptr,                                                               \
 495   }
 496
 497 // Defines a 64-bit general purpose register
 498 #define DEFINE_GPR64_ALT(reg, alt, generic_kind)                               \
 499   {                                                                            \
 500     #reg, #alt, 8, GPR_OFFSET(gpr_##reg), lldb::eEncodingUint,                 \
 501         lldb::eFormatHex, GPR64_KIND(reg, generic_kind), nullptr, nullptr,     \
 502         nullptr,                                                               \
 503   }
 504
 505 // Defines a 32-bit general purpose pseudo register
 506 #define DEFINE_GPR32(wreg, xreg)                                               \
 507   {                                                                            \
 508     #wreg, nullptr, 4,                                                         \
 509         GPR_OFFSET(gpr_##xreg) + GPR_W_PSEUDO_REG_ENDIAN_OFFSET,               \
 510         lldb::eEncodingUint, lldb::eFormatHex, LLDB_KIND(gpr_##wreg),          \
 511         g_contained_##xreg, g_##wreg##_invalidates, nullptr,                   \
 512   }
 513
 514 // Defines a vector register with 16-byte size
 515 #define DEFINE_VREG(reg)                                                       \
 516   {                                                                            \
 517     #reg, nullptr, 16, FPU_OFFSET(fpu_##reg - fpu_v0), lldb::eEncodingVector,  \
 518         lldb::eFormatVectorOfUInt8, VREG_KIND(reg), nullptr, nullptr, nullptr, \
 519   }
 520
 521 // Defines S and D pseudo registers mapping over corresponding vector register
 522 #define DEFINE_FPU_PSEUDO(reg, size, offset, vreg)                             \
 523   {                                                                            \
 524     #reg, nullptr, size, FPU_OFFSET(fpu_##vreg - fpu_v0) + offset,             \
 525         lldb::eEncodingIEEE754, lldb::eFormatFloat, LLDB_KIND(fpu_##reg),      \
 526         g_contained_##vreg, g_##reg##_invalidates, nullptr,                    \
 527   }
 528
 529 // Defines miscellaneous status and control registers like cpsr, fpsr etc
 530 #define DEFINE_MISC_REGS(reg, size, TYPE, lldb_kind)                           \
 531   {                                                                            \
 532     #reg, nullptr, size, TYPE##_OFFSET_NAME(reg), lldb::eEncodingUint,         \
 533         lldb::eFormatHex, MISC_##TYPE##_KIND(lldb_kind), nullptr, nullptr,     \
 534         nullptr,                                                               \
 535   }
 536
 537 // Defines pointer authentication mask registers
 538 #define DEFINE_EXTENSION_REG(reg)                                              \
 539   {                                                                            \
 540     #reg, nullptr, 8, 0, lldb::eEncodingUint, lldb::eFormatHex,                \
 541         KIND_ALL_INVALID, nullptr, nullptr, nullptr,                           \
 542   }
 543
 544 static lldb_private::RegisterInfo g_register_infos_arm64_le[] = {
 545     // DEFINE_GPR64(name, GENERIC KIND)
 546     DEFINE_GPR64(x0, LLDB_REGNUM_GENERIC_ARG1),
 547     DEFINE_GPR64(x1, LLDB_REGNUM_GENERIC_ARG2),
 548     DEFINE_GPR64(x2, LLDB_REGNUM_GENERIC_ARG3),
 549     DEFINE_GPR64(x3, LLDB_REGNUM_GENERIC_ARG4),
 550     DEFINE_GPR64(x4, LLDB_REGNUM_GENERIC_ARG5),
 551     DEFINE_GPR64(x5, LLDB_REGNUM_GENERIC_ARG6),
 552     DEFINE_GPR64(x6, LLDB_REGNUM_GENERIC_ARG7),
 553     DEFINE_GPR64(x7, LLDB_REGNUM_GENERIC_ARG8),
 554     DEFINE_GPR64(x8, LLDB_INVALID_REGNUM),
 555     DEFINE_GPR64(x9, LLDB_INVALID_REGNUM),
 556     DEFINE_GPR64(x10, LLDB_INVALID_REGNUM),
 557     DEFINE_GPR64(x11, LLDB_INVALID_REGNUM),
 558     DEFINE_GPR64(x12, LLDB_INVALID_REGNUM),
 559     DEFINE_GPR64(x13, LLDB_INVALID_REGNUM),
 560     DEFINE_GPR64(x14, LLDB_INVALID_REGNUM),
 561     DEFINE_GPR64(x15, LLDB_INVALID_REGNUM),
 562     DEFINE_GPR64(x16, LLDB_INVALID_REGNUM),
 563     DEFINE_GPR64(x17, LLDB_INVALID_REGNUM),
 564     DEFINE_GPR64(x18, LLDB_INVALID_REGNUM),
 565     DEFINE_GPR64(x19, LLDB_INVALID_REGNUM),
 566     DEFINE_GPR64(x20, LLDB_INVALID_REGNUM),
 567     DEFINE_GPR64(x21, LLDB_INVALID_REGNUM),
 568     DEFINE_GPR64(x22, LLDB_INVALID_REGNUM),
 569     DEFINE_GPR64(x23, LLDB_INVALID_REGNUM),
 570     DEFINE_GPR64(x24, LLDB_INVALID_REGNUM),
 571     DEFINE_GPR64(x25, LLDB_INVALID_REGNUM),
 572     DEFINE_GPR64(x26, LLDB_INVALID_REGNUM),
 573     DEFINE_GPR64(x27, LLDB_INVALID_REGNUM),
 574     DEFINE_GPR64(x28, LLDB_INVALID_REGNUM),
 575     // DEFINE_GPR64(name, GENERIC KIND)
 576     DEFINE_GPR64_ALT(fp, x29, LLDB_REGNUM_GENERIC_FP),
 577     DEFINE_GPR64_ALT(lr, x30, LLDB_REGNUM_GENERIC_RA),
 578     DEFINE_GPR64_ALT(sp, x31, LLDB_REGNUM_GENERIC_SP),
 579     DEFINE_GPR64(pc, LLDB_REGNUM_GENERIC_PC),
 580
 581     // DEFINE_MISC_REGS(name, size, TYPE, lldb kind)
 582     DEFINE_MISC_REGS(cpsr, 4, GPR, gpr_cpsr),
 583
 584     // DEFINE_GPR32(name, parent name)
 585     DEFINE_GPR32(w0, x0),
 586     DEFINE_GPR32(w1, x1),
 587     DEFINE_GPR32(w2, x2),
 588     DEFINE_GPR32(w3, x3),
 589     DEFINE_GPR32(w4, x4),
 590     DEFINE_GPR32(w5, x5),
 591     DEFINE_GPR32(w6, x6),
 592     DEFINE_GPR32(w7, x7),
 593     DEFINE_GPR32(w8, x8),
 594     DEFINE_GPR32(w9, x9),
 595     DEFINE_GPR32(w10, x10),
 596     DEFINE_GPR32(w11, x11),
 597     DEFINE_GPR32(w12, x12),
 598     DEFINE_GPR32(w13, x13),
 599     DEFINE_GPR32(w14, x14),
 600     DEFINE_GPR32(w15, x15),
 601     DEFINE_GPR32(w16, x16),
 602     DEFINE_GPR32(w17, x17),
 603     DEFINE_GPR32(w18, x18),
 604     DEFINE_GPR32(w19, x19),
 605     DEFINE_GPR32(w20, x20),
 606     DEFINE_GPR32(w21, x21),
 607     DEFINE_GPR32(w22, x22),
 608     DEFINE_GPR32(w23, x23),
 609     DEFINE_GPR32(w24, x24),
 610     DEFINE_GPR32(w25, x25),
 611     DEFINE_GPR32(w26, x26),
 612     DEFINE_GPR32(w27, x27),
 613     DEFINE_GPR32(w28, x28),
 614
 615     // DEFINE_VREG(name)
 616     DEFINE_VREG(v0),
 617     DEFINE_VREG(v1),
 618     DEFINE_VREG(v2),
 619     DEFINE_VREG(v3),
 620     DEFINE_VREG(v4),
 621     DEFINE_VREG(v5),
 622     DEFINE_VREG(v6),
 623     DEFINE_VREG(v7),
 624     DEFINE_VREG(v8),
 625     DEFINE_VREG(v9),
 626     DEFINE_VREG(v10),
 627     DEFINE_VREG(v11),
 628     DEFINE_VREG(v12),
 629     DEFINE_VREG(v13),
 630     DEFINE_VREG(v14),
 631     DEFINE_VREG(v15),
 632     DEFINE_VREG(v16),
 633     DEFINE_VREG(v17),
 634     DEFINE_VREG(v18),
 635     DEFINE_VREG(v19),
 636     DEFINE_VREG(v20),
 637     DEFINE_VREG(v21),
 638     DEFINE_VREG(v22),
 639     DEFINE_VREG(v23),
 640     DEFINE_VREG(v24),
 641     DEFINE_VREG(v25),
 642     DEFINE_VREG(v26),
 643     DEFINE_VREG(v27),
 644     DEFINE_VREG(v28),
 645     DEFINE_VREG(v29),
 646     DEFINE_VREG(v30),
 647     DEFINE_VREG(v31),
 648
 649     // DEFINE_FPU_PSEUDO(name, size, ENDIAN OFFSET, parent register)
 650     DEFINE_FPU_PSEUDO(s0, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v0),
 651     DEFINE_FPU_PSEUDO(s1, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v1),
 652     DEFINE_FPU_PSEUDO(s2, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v2),
 653     DEFINE_FPU_PSEUDO(s3, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v3),
 654     DEFINE_FPU_PSEUDO(s4, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v4),
 655     DEFINE_FPU_PSEUDO(s5, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v5),
 656     DEFINE_FPU_PSEUDO(s6, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v6),
 657     DEFINE_FPU_PSEUDO(s7, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v7),
 658     DEFINE_FPU_PSEUDO(s8, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v8),
 659     DEFINE_FPU_PSEUDO(s9, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v9),
 660     DEFINE_FPU_PSEUDO(s10, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v10),
 661     DEFINE_FPU_PSEUDO(s11, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v11),
 662     DEFINE_FPU_PSEUDO(s12, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v12),
 663     DEFINE_FPU_PSEUDO(s13, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v13),
 664     DEFINE_FPU_PSEUDO(s14, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v14),
 665     DEFINE_FPU_PSEUDO(s15, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v15),
 666     DEFINE_FPU_PSEUDO(s16, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v16),
 667     DEFINE_FPU_PSEUDO(s17, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v17),
 668     DEFINE_FPU_PSEUDO(s18, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v18),
 669     DEFINE_FPU_PSEUDO(s19, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v19),
 670     DEFINE_FPU_PSEUDO(s20, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v20),
 671     DEFINE_FPU_PSEUDO(s21, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v21),
 672     DEFINE_FPU_PSEUDO(s22, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v22),
 673     DEFINE_FPU_PSEUDO(s23, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v23),
 674     DEFINE_FPU_PSEUDO(s24, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v24),
 675     DEFINE_FPU_PSEUDO(s25, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v25),
 676     DEFINE_FPU_PSEUDO(s26, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v26),
 677     DEFINE_FPU_PSEUDO(s27, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v27),
 678     DEFINE_FPU_PSEUDO(s28, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v28),
 679     DEFINE_FPU_PSEUDO(s29, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v29),
 680     DEFINE_FPU_PSEUDO(s30, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v30),
 681     DEFINE_FPU_PSEUDO(s31, 4, FPU_S_PSEUDO_REG_ENDIAN_OFFSET, v31),
 682
 683     DEFINE_FPU_PSEUDO(d0, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v0),
 684     DEFINE_FPU_PSEUDO(d1, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v1),
 685     DEFINE_FPU_PSEUDO(d2, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v2),
 686     DEFINE_FPU_PSEUDO(d3, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v3),
 687     DEFINE_FPU_PSEUDO(d4, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v4),
 688     DEFINE_FPU_PSEUDO(d5, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v5),
 689     DEFINE_FPU_PSEUDO(d6, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v6),
 690     DEFINE_FPU_PSEUDO(d7, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v7),
 691     DEFINE_FPU_PSEUDO(d8, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v8),
 692     DEFINE_FPU_PSEUDO(d9, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v9),
 693     DEFINE_FPU_PSEUDO(d10, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v10),
 694     DEFINE_FPU_PSEUDO(d11, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v11),
 695     DEFINE_FPU_PSEUDO(d12, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v12),
 696     DEFINE_FPU_PSEUDO(d13, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v13),
 697     DEFINE_FPU_PSEUDO(d14, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v14),
 698     DEFINE_FPU_PSEUDO(d15, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v15),
 699     DEFINE_FPU_PSEUDO(d16, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v16),
 700     DEFINE_FPU_PSEUDO(d17, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v17),
 701     DEFINE_FPU_PSEUDO(d18, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v18),
 702     DEFINE_FPU_PSEUDO(d19, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v19),
 703     DEFINE_FPU_PSEUDO(d20, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v20),
 704     DEFINE_FPU_PSEUDO(d21, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v21),
 705     DEFINE_FPU_PSEUDO(d22, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v22),
 706     DEFINE_FPU_PSEUDO(d23, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v23),
 707     DEFINE_FPU_PSEUDO(d24, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v24),
 708     DEFINE_FPU_PSEUDO(d25, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v25),
 709     DEFINE_FPU_PSEUDO(d26, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v26),
 710     DEFINE_FPU_PSEUDO(d27, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v27),
 711     DEFINE_FPU_PSEUDO(d28, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v28),
 712     DEFINE_FPU_PSEUDO(d29, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v29),
 713     DEFINE_FPU_PSEUDO(d30, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v30),
 714     DEFINE_FPU_PSEUDO(d31, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v31),
 715
 716     // DEFINE_MISC_REGS(name, size, TYPE, lldb kind)
 717     DEFINE_MISC_REGS(fpsr, 4, FPU, fpu_fpsr),
 718     DEFINE_MISC_REGS(fpcr, 4, FPU, fpu_fpcr),
 719     DEFINE_MISC_REGS(far, 8, EXC, exc_far),
 720     DEFINE_MISC_REGS(esr, 4, EXC, exc_esr),
 721     DEFINE_MISC_REGS(exception, 4, EXC, exc_exception),
 722
 723     {DEFINE_DBG(bvr, 0)},
 724     {DEFINE_DBG(bvr, 1)},
 725     {DEFINE_DBG(bvr, 2)},
 726     {DEFINE_DBG(bvr, 3)},
 727     {DEFINE_DBG(bvr, 4)},
 728     {DEFINE_DBG(bvr, 5)},
 729     {DEFINE_DBG(bvr, 6)},
 730     {DEFINE_DBG(bvr, 7)},
 731     {DEFINE_DBG(bvr, 8)},
 732     {DEFINE_DBG(bvr, 9)},
 733     {DEFINE_DBG(bvr, 10)},
 734     {DEFINE_DBG(bvr, 11)},
 735     {DEFINE_DBG(bvr, 12)},
 736     {DEFINE_DBG(bvr, 13)},
 737     {DEFINE_DBG(bvr, 14)},
 738     {DEFINE_DBG(bvr, 15)},
 739
 740     {DEFINE_DBG(bcr, 0)},
 741     {DEFINE_DBG(bcr, 1)},
 742     {DEFINE_DBG(bcr, 2)},
 743     {DEFINE_DBG(bcr, 3)},
 744     {DEFINE_DBG(bcr, 4)},
 745     {DEFINE_DBG(bcr, 5)},
 746     {DEFINE_DBG(bcr, 6)},
 747     {DEFINE_DBG(bcr, 7)},
 748     {DEFINE_DBG(bcr, 8)},
 749     {DEFINE_DBG(bcr, 9)},
 750     {DEFINE_DBG(bcr, 10)},
 751     {DEFINE_DBG(bcr, 11)},
 752     {DEFINE_DBG(bcr, 12)},
 753     {DEFINE_DBG(bcr, 13)},
 754     {DEFINE_DBG(bcr, 14)},
 755     {DEFINE_DBG(bcr, 15)},
 756
 757     {DEFINE_DBG(wvr, 0)},
 758     {DEFINE_DBG(wvr, 1)},
 759     {DEFINE_DBG(wvr, 2)},
 760     {DEFINE_DBG(wvr, 3)},
 761     {DEFINE_DBG(wvr, 4)},
 762     {DEFINE_DBG(wvr, 5)},
 763     {DEFINE_DBG(wvr, 6)},
 764     {DEFINE_DBG(wvr, 7)},
 765     {DEFINE_DBG(wvr, 8)},
 766     {DEFINE_DBG(wvr, 9)},
 767     {DEFINE_DBG(wvr, 10)},
 768     {DEFINE_DBG(wvr, 11)},
 769     {DEFINE_DBG(wvr, 12)},
 770     {DEFINE_DBG(wvr, 13)},
 771     {DEFINE_DBG(wvr, 14)},
 772     {DEFINE_DBG(wvr, 15)},
 773
 774     {DEFINE_DBG(wcr, 0)},
 775     {DEFINE_DBG(wcr, 1)},
 776     {DEFINE_DBG(wcr, 2)},
 777     {DEFINE_DBG(wcr, 3)},
 778     {DEFINE_DBG(wcr, 4)},
 779     {DEFINE_DBG(wcr, 5)},
 780     {DEFINE_DBG(wcr, 6)},
 781     {DEFINE_DBG(wcr, 7)},
 782     {DEFINE_DBG(wcr, 8)},
 783     {DEFINE_DBG(wcr, 9)},
 784     {DEFINE_DBG(wcr, 10)},
 785     {DEFINE_DBG(wcr, 11)},
 786     {DEFINE_DBG(wcr, 12)},
 787     {DEFINE_DBG(wcr, 13)},
 788     {DEFINE_DBG(wcr, 14)},
 789     {DEFINE_DBG(wcr, 15)}
 790 };
 791 // clang-format on
 792
 793 #endif // DECLARE_REGISTER_INFOS_ARM64_STRUCT