llvm/docs/AMDGPU/gfx11_vdst_e2d005.rst

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   8 .. _amdgpu_synid_gfx11_vdst_e2d005:
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  10 vdst
  11 ====
  12
  13 Image data to be loaded by an image instruction.
  14
  15 *Size:* 4 data elements by default. Each data element occupies either 32 bits or 16 bits, depending on :ref:`d16<amdgpu_synid_d16>`.
  16
  17 :ref:`d16<amdgpu_synid_d16>` and :ref:`tfe<amdgpu_synid_tfe>` affect operand size as follows:
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  19 * :ref:`d16<amdgpu_synid_d16>` specifies that data elements in registers are packed; each value occupies 16 bits.
  20 * :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
  21
  22 *Operands:* :ref:`v<amdgpu_synid_v>`