llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp

   1 //===- llvm/CodeGen/GlobalISel/InstructionSelect.cpp - InstructionSelect ---==//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 /// \file
   9 /// This file implements the InstructionSelect class.
  10 //===----------------------------------------------------------------------===//
  11
  12 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
  13 #include "llvm/ADT/PostOrderIterator.h"
  14 #include "llvm/ADT/ScopeExit.h"
  15 #include "llvm/Analysis/LazyBlockFrequencyInfo.h"
  16 #include "llvm/Analysis/ProfileSummaryInfo.h"
  17 #include "llvm/CodeGen/GlobalISel/GISelKnownBits.h"
  18 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
  19 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
  20 #include "llvm/CodeGen/GlobalISel/Utils.h"
  21 #include "llvm/CodeGen/MachineFrameInfo.h"
  22 #include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h"
  23 #include "llvm/CodeGen/MachineRegisterInfo.h"
  24 #include "llvm/CodeGen/TargetLowering.h"
  25 #include "llvm/CodeGen/TargetOpcodes.h"
  26 #include "llvm/CodeGen/TargetPassConfig.h"
  27 #include "llvm/CodeGen/TargetSubtargetInfo.h"
  28 #include "llvm/Config/config.h"
  29 #include "llvm/IR/Function.h"
  30 #include "llvm/MC/TargetRegistry.h"
  31 #include "llvm/Support/CodeGenCoverage.h"
  32 #include "llvm/Support/CommandLine.h"
  33 #include "llvm/Support/Debug.h"
  34 #include "llvm/Target/TargetMachine.h"
  35
  36 #define DEBUG_TYPE "instruction-select"
  37
  38 using namespace llvm;
  39
  40 #ifdef LLVM_GISEL_COV_PREFIX
  41 static cl::opt<std::string>
  42     CoveragePrefix("gisel-coverage-prefix", cl::init(LLVM_GISEL_COV_PREFIX),
  43                    cl::desc("Record GlobalISel rule coverage files of this "
  44                             "prefix if instrumentation was generated"));
  45 #else
  46 static const std::string CoveragePrefix;
  47 #endif
  48
  49 char InstructionSelect::ID = 0;
  50 INITIALIZE_PASS_BEGIN(InstructionSelect, DEBUG_TYPE,
  51                       "Select target instructions out of generic instructions",
  52                       false, false)
  53 INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
  54 INITIALIZE_PASS_DEPENDENCY(GISelKnownBitsAnalysis)
  55 INITIALIZE_PASS_DEPENDENCY(ProfileSummaryInfoWrapperPass)
  56 INITIALIZE_PASS_DEPENDENCY(LazyBlockFrequencyInfoPass)
  57 INITIALIZE_PASS_END(InstructionSelect, DEBUG_TYPE,
  58                     "Select target instructions out of generic instructions",
  59                     false, false)
  60
  61 InstructionSelect::InstructionSelect(CodeGenOptLevel OL)
  62     : MachineFunctionPass(ID), OptLevel(OL) {}
  63
  64 // In order not to crash when calling getAnalysis during testing with -run-pass
  65 // we use the default opt level here instead of None, so that the addRequired()
  66 // calls are made in getAnalysisUsage().
  67 InstructionSelect::InstructionSelect()
  68     : MachineFunctionPass(ID), OptLevel(CodeGenOptLevel::Default) {}
  69
  70 void InstructionSelect::getAnalysisUsage(AnalysisUsage &AU) const {
  71   AU.addRequired<TargetPassConfig>();
  72   AU.addRequired<GISelKnownBitsAnalysis>();
  73   AU.addPreserved<GISelKnownBitsAnalysis>();
  74
  75   if (OptLevel != CodeGenOptLevel::None) {
  76     AU.addRequired<ProfileSummaryInfoWrapperPass>();
  77     LazyBlockFrequencyInfoPass::getLazyBFIAnalysisUsage(AU);
  78   }
  79   getSelectionDAGFallbackAnalysisUsage(AU);
  80   MachineFunctionPass::getAnalysisUsage(AU);
  81 }
  82
  83 bool InstructionSelect::runOnMachineFunction(MachineFunction &MF) {
  84   // If the ISel pipeline failed, do not bother running that pass.
  85   if (MF.getProperties().hasProperty(
  86           MachineFunctionProperties::Property::FailedISel))
  87     return false;
  88
  89   LLVM_DEBUG(dbgs() << "Selecting function: " << MF.getName() << '\n');
  90
  91   const TargetPassConfig &TPC = getAnalysis<TargetPassConfig>();
  92   InstructionSelector *ISel = MF.getSubtarget().getInstructionSelector();
  93   ISel->setTargetPassConfig(&TPC);
  94
  95   CodeGenOptLevel OldOptLevel = OptLevel;
  96   auto RestoreOptLevel = make_scope_exit([=]() { OptLevel = OldOptLevel; });
  97   OptLevel = MF.getFunction().hasOptNone() ? CodeGenOptLevel::None
  98                                            : MF.getTarget().getOptLevel();
  99
 100   GISelKnownBits *KB = &getAnalysis<GISelKnownBitsAnalysis>().get(MF);
 101   if (OptLevel != CodeGenOptLevel::None) {
 102     PSI = &getAnalysis<ProfileSummaryInfoWrapperPass>().getPSI();
 103     if (PSI && PSI->hasProfileSummary())
 104       BFI = &getAnalysis<LazyBlockFrequencyInfoPass>().getBFI();
 105   }
 106
 107   CodeGenCoverage CoverageInfo;
 108   assert(ISel && "Cannot work without InstructionSelector");
 109   ISel->setupMF(MF, KB, &CoverageInfo, PSI, BFI);
 110
 111   // An optimization remark emitter. Used to report failures.
 112   MachineOptimizationRemarkEmitter MORE(MF, /*MBFI=*/nullptr);
 113   ISel->setRemarkEmitter(&MORE);
 114
 115   // FIXME: There are many other MF/MFI fields we need to initialize.
 116
 117   MachineRegisterInfo &MRI = MF.getRegInfo();
 118 #ifndef NDEBUG
 119   // Check that our input is fully legal: we require the function to have the
 120   // Legalized property, so it should be.
 121   // FIXME: This should be in the MachineVerifier, as the RegBankSelected
 122   // property check already is.
 123   if (!DisableGISelLegalityCheck)
 124     if (const MachineInstr *MI = machineFunctionIsIllegal(MF)) {
 125       reportGISelFailure(MF, TPC, MORE, "gisel-select",
 126                          "instruction is not legal", *MI);
 127       return false;
 128     }
 129   // FIXME: We could introduce new blocks and will need to fix the outer loop.
 130   // Until then, keep track of the number of blocks to assert that we don't.
 131   const size_t NumBlocks = MF.size();
 132 #endif
 133   // Keep track of selected blocks, so we can delete unreachable ones later.
 134   DenseSet<MachineBasicBlock *> SelectedBlocks;
 135
 136   for (MachineBasicBlock *MBB : post_order(&MF)) {
 137     ISel->CurMBB = MBB;
 138     SelectedBlocks.insert(MBB);
 139     if (MBB->empty())
 140       continue;
 141
 142     // Select instructions in reverse block order. We permit erasing so have
 143     // to resort to manually iterating and recognizing the begin (rend) case.
 144     bool ReachedBegin = false;
 145     for (auto MII = std::prev(MBB->end()), Begin = MBB->begin();
 146          !ReachedBegin;) {
 147 #ifndef NDEBUG
 148       // Keep track of the insertion range for debug printing.
 149       const auto AfterIt = std::next(MII);
 150 #endif
 151       // Select this instruction.
 152       MachineInstr &MI = *MII;
 153
 154       // And have our iterator point to the next instruction, if there is one.
 155       if (MII == Begin)
 156         ReachedBegin = true;
 157       else
 158         --MII;
 159
 160       LLVM_DEBUG(dbgs() << "Selecting: \n  " << MI);
 161
 162       // We could have folded this instruction away already, making it dead.
 163       // If so, erase it.
 164       if (isTriviallyDead(MI, MRI)) {
 165         LLVM_DEBUG(dbgs() << "Is dead; erasing.\n");
 166         salvageDebugInfo(MRI, MI);
 167         MI.eraseFromParent();
 168         continue;
 169       }
 170
 171       // Eliminate hints or G_CONSTANT_FOLD_BARRIER.
 172       if (isPreISelGenericOptimizationHint(MI.getOpcode()) ||
 173           MI.getOpcode() == TargetOpcode::G_CONSTANT_FOLD_BARRIER) {
 174         auto [DstReg, SrcReg] = MI.getFirst2Regs();
 175
 176         // At this point, the destination register class of the op may have
 177         // been decided.
 178         //
 179         // Propagate that through to the source register.
 180         const TargetRegisterClass *DstRC = MRI.getRegClassOrNull(DstReg);
 181         if (DstRC)
 182           MRI.setRegClass(SrcReg, DstRC);
 183         assert(canReplaceReg(DstReg, SrcReg, MRI) &&
 184                "Must be able to replace dst with src!");
 185         MI.eraseFromParent();
 186         MRI.replaceRegWith(DstReg, SrcReg);
 187         continue;
 188       }
 189
 190       if (MI.getOpcode() == TargetOpcode::G_INVOKE_REGION_START) {
 191         MI.eraseFromParent();
 192         continue;
 193       }
 194
 195       if (!ISel->select(MI)) {
 196         // FIXME: It would be nice to dump all inserted instructions.  It's
 197         // not obvious how, esp. considering select() can insert after MI.
 198         reportGISelFailure(MF, TPC, MORE, "gisel-select", "cannot select", MI);
 199         return false;
 200       }
 201
 202       // Dump the range of instructions that MI expanded into.
 203       LLVM_DEBUG({
 204         auto InsertedBegin = ReachedBegin ? MBB->begin() : std::next(MII);
 205         dbgs() << "Into:\n";
 206         for (auto &InsertedMI : make_range(InsertedBegin, AfterIt))
 207           dbgs() << "  " << InsertedMI;
 208         dbgs() << '\n';
 209       });
 210     }
 211   }
 212
 213   for (MachineBasicBlock &MBB : MF) {
 214     if (MBB.empty())
 215       continue;
 216
 217     if (!SelectedBlocks.contains(&MBB)) {
 218       // This is an unreachable block and therefore hasn't been selected, since
 219       // the main selection loop above uses a postorder block traversal.
 220       // We delete all the instructions in this block since it's unreachable.
 221       MBB.clear();
 222       // Don't delete the block in case the block has it's address taken or is
 223       // still being referenced by a phi somewhere.
 224       continue;
 225     }
 226     // Try to find redundant copies b/w vregs of the same register class.
 227     bool ReachedBegin = false;
 228     for (auto MII = std::prev(MBB.end()), Begin = MBB.begin(); !ReachedBegin;) {
 229       // Select this instruction.
 230       MachineInstr &MI = *MII;
 231
 232       // And have our iterator point to the next instruction, if there is one.
 233       if (MII == Begin)
 234         ReachedBegin = true;
 235       else
 236         --MII;
 237       if (MI.getOpcode() != TargetOpcode::COPY)
 238         continue;
 239       Register SrcReg = MI.getOperand(1).getReg();
 240       Register DstReg = MI.getOperand(0).getReg();
 241       if (SrcReg.isVirtual() && DstReg.isVirtual()) {
 242         auto SrcRC = MRI.getRegClass(SrcReg);
 243         auto DstRC = MRI.getRegClass(DstReg);
 244         if (SrcRC == DstRC) {
 245           MRI.replaceRegWith(DstReg, SrcReg);
 246           MI.eraseFromParent();
 247         }
 248       }
 249     }
 250   }
 251
 252 #ifndef NDEBUG
 253   const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
 254   // Now that selection is complete, there are no more generic vregs.  Verify
 255   // that the size of the now-constrained vreg is unchanged and that it has a
 256   // register class.
 257   for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
 258     Register VReg = Register::index2VirtReg(I);
 259
 260     MachineInstr *MI = nullptr;
 261     if (!MRI.def_empty(VReg))
 262       MI = &*MRI.def_instr_begin(VReg);
 263     else if (!MRI.use_empty(VReg)) {
 264       MI = &*MRI.use_instr_begin(VReg);
 265       // Debug value instruction is permitted to use undefined vregs.
 266       if (MI->isDebugValue())
 267         continue;
 268     }
 269     if (!MI)
 270       continue;
 271
 272     const TargetRegisterClass *RC = MRI.getRegClassOrNull(VReg);
 273     if (!RC) {
 274       reportGISelFailure(MF, TPC, MORE, "gisel-select",
 275                          "VReg has no regclass after selection", *MI);
 276       return false;
 277     }
 278
 279     const LLT Ty = MRI.getType(VReg);
 280     if (Ty.isValid() && Ty.getSizeInBits() > TRI.getRegSizeInBits(*RC)) {
 281       reportGISelFailure(
 282           MF, TPC, MORE, "gisel-select",
 283           "VReg's low-level type and register class have different sizes", *MI);
 284       return false;
 285     }
 286   }
 287
 288   if (MF.size() != NumBlocks) {
 289     MachineOptimizationRemarkMissed R("gisel-select", "GISelFailure",
 290                                       MF.getFunction().getSubprogram(),
 291                                       /*MBB=*/nullptr);
 292     R << "inserting blocks is not supported yet";
 293     reportGISelFailure(MF, TPC, MORE, R);
 294     return false;
 295   }
 296 #endif
 297   // Determine if there are any calls in this machine function. Ported from
 298   // SelectionDAG.
 299   MachineFrameInfo &MFI = MF.getFrameInfo();
 300   for (const auto &MBB : MF) {
 301     if (MFI.hasCalls() && MF.hasInlineAsm())
 302       break;
 303
 304     for (const auto &MI : MBB) {
 305       if ((MI.isCall() && !MI.isReturn()) || MI.isStackAligningInlineAsm())
 306         MFI.setHasCalls(true);
 307       if (MI.isInlineAsm())
 308         MF.setHasInlineAsm(true);
 309     }
 310   }
 311
 312   // FIXME: FinalizeISel pass calls finalizeLowering, so it's called twice.
 313   auto &TLI = *MF.getSubtarget().getTargetLowering();
 314   TLI.finalizeLowering(MF);
 315
 316   LLVM_DEBUG({
 317     dbgs() << "Rules covered by selecting function: " << MF.getName() << ":";
 318     for (auto RuleID : CoverageInfo.covered())
 319       dbgs() << " id" << RuleID;
 320     dbgs() << "\n\n";
 321   });
 322   CoverageInfo.emit(CoveragePrefix,
 323                     TLI.getTargetMachine().getTarget().getBackendName());
 324
 325   // If we successfully selected the function nothing is going to use the vreg
 326   // types after us (otherwise MIRPrinter would need them). Make sure the types
 327   // disappear.
 328   MRI.clearVirtRegTypes();
 329
 330   // FIXME: Should we accurately track changes?
 331   return true;
 332 }