llvm/lib/CodeGen/MIRPrinter.cpp

   1 //===- MIRPrinter.cpp - MIR serialization format printer ------------------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file implements the class that prints out the LLVM IR and machine
  10 // functions using the MIR serialization format.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "llvm/CodeGen/MIRPrinter.h"
  15 #include "llvm/ADT/DenseMap.h"
  16 #include "llvm/ADT/STLExtras.h"
  17 #include "llvm/ADT/SmallBitVector.h"
  18 #include "llvm/ADT/SmallPtrSet.h"
  19 #include "llvm/ADT/SmallVector.h"
  20 #include "llvm/ADT/StringRef.h"
  21 #include "llvm/CodeGen/LowLevelType.h"
  22 #include "llvm/CodeGen/MIRYamlMapping.h"
  23 #include "llvm/CodeGen/MachineBasicBlock.h"
  24 #include "llvm/CodeGen/MachineConstantPool.h"
  25 #include "llvm/CodeGen/MachineFrameInfo.h"
  26 #include "llvm/CodeGen/MachineFunction.h"
  27 #include "llvm/CodeGen/MachineInstr.h"
  28 #include "llvm/CodeGen/MachineJumpTableInfo.h"
  29 #include "llvm/CodeGen/MachineMemOperand.h"
  30 #include "llvm/CodeGen/MachineModuleSlotTracker.h"
  31 #include "llvm/CodeGen/MachineOperand.h"
  32 #include "llvm/CodeGen/MachineRegisterInfo.h"
  33 #include "llvm/CodeGen/TargetFrameLowering.h"
  34 #include "llvm/CodeGen/TargetInstrInfo.h"
  35 #include "llvm/CodeGen/TargetRegisterInfo.h"
  36 #include "llvm/CodeGen/TargetSubtargetInfo.h"
  37 #include "llvm/IR/DebugInfoMetadata.h"
  38 #include "llvm/IR/DebugLoc.h"
  39 #include "llvm/IR/Function.h"
  40 #include "llvm/IR/IRPrintingPasses.h"
  41 #include "llvm/IR/Instructions.h"
  42 #include "llvm/IR/Module.h"
  43 #include "llvm/IR/ModuleSlotTracker.h"
  44 #include "llvm/IR/Value.h"
  45 #include "llvm/MC/LaneBitmask.h"
  46 #include "llvm/Support/BranchProbability.h"
  47 #include "llvm/Support/Casting.h"
  48 #include "llvm/Support/CommandLine.h"
  49 #include "llvm/Support/ErrorHandling.h"
  50 #include "llvm/Support/Format.h"
  51 #include "llvm/Support/YAMLTraits.h"
  52 #include "llvm/Support/raw_ostream.h"
  53 #include "llvm/Target/TargetMachine.h"
  54 #include <algorithm>
  55 #include <cassert>
  56 #include <cinttypes>
  57 #include <cstdint>
  58 #include <iterator>
  59 #include <string>
  60 #include <utility>
  61 #include <vector>
  62
  63 using namespace llvm;
  64
  65 static cl::opt<bool> SimplifyMIR(
  66     "simplify-mir", cl::Hidden,
  67     cl::desc("Leave out unnecessary information when printing MIR"));
  68
  69 static cl::opt<bool> PrintLocations("mir-debug-loc", cl::Hidden, cl::init(true),
  70                                     cl::desc("Print MIR debug-locations"));
  71
  72 namespace {
  73
  74 /// This structure describes how to print out stack object references.
  75 struct FrameIndexOperand {
  76   std::string Name;
  77   unsigned ID;
  78   bool IsFixed;
  79
  80   FrameIndexOperand(StringRef Name, unsigned ID, bool IsFixed)
  81       : Name(Name.str()), ID(ID), IsFixed(IsFixed) {}
  82
  83   /// Return an ordinary stack object reference.
  84   static FrameIndexOperand create(StringRef Name, unsigned ID) {
  85     return FrameIndexOperand(Name, ID, /*IsFixed=*/false);
  86   }
  87
  88   /// Return a fixed stack object reference.
  89   static FrameIndexOperand createFixed(unsigned ID) {
  90     return FrameIndexOperand("", ID, /*IsFixed=*/true);
  91   }
  92 };
  93
  94 } // end anonymous namespace
  95
  96 namespace llvm {
  97
  98 /// This class prints out the machine functions using the MIR serialization
  99 /// format.
 100 class MIRPrinter {
 101   raw_ostream &OS;
 102   DenseMap<const uint32_t *, unsigned> RegisterMaskIds;
 103   /// Maps from stack object indices to operand indices which will be used when
 104   /// printing frame index machine operands.
 105   DenseMap<int, FrameIndexOperand> StackObjectOperandMapping;
 106
 107 public:
 108   MIRPrinter(raw_ostream &OS) : OS(OS) {}
 109
 110   void print(const MachineFunction &MF);
 111
 112   void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo,
 113                const TargetRegisterInfo *TRI);
 114   void convert(ModuleSlotTracker &MST, yaml::MachineFrameInfo &YamlMFI,
 115                const MachineFrameInfo &MFI);
 116   void convert(yaml::MachineFunction &MF,
 117                const MachineConstantPool &ConstantPool);
 118   void convert(ModuleSlotTracker &MST, yaml::MachineJumpTable &YamlJTI,
 119                const MachineJumpTableInfo &JTI);
 120   void convertStackObjects(yaml::MachineFunction &YMF,
 121                            const MachineFunction &MF, ModuleSlotTracker &MST);
 122   void convertEntryValueObjects(yaml::MachineFunction &YMF,
 123                                 const MachineFunction &MF,
 124                                 ModuleSlotTracker &MST);
 125   void convertCallSiteObjects(yaml::MachineFunction &YMF,
 126                               const MachineFunction &MF,
 127                               ModuleSlotTracker &MST);
 128   void convertMachineMetadataNodes(yaml::MachineFunction &YMF,
 129                                    const MachineFunction &MF,
 130                                    MachineModuleSlotTracker &MST);
 131
 132 private:
 133   void initRegisterMaskIds(const MachineFunction &MF);
 134 };
 135
 136 /// This class prints out the machine instructions using the MIR serialization
 137 /// format.
 138 class MIPrinter {
 139   raw_ostream &OS;
 140   ModuleSlotTracker &MST;
 141   const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds;
 142   const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping;
 143   /// Synchronization scope names registered with LLVMContext.
 144   SmallVector<StringRef, 8> SSNs;
 145
 146   bool canPredictBranchProbabilities(const MachineBasicBlock &MBB) const;
 147   bool canPredictSuccessors(const MachineBasicBlock &MBB) const;
 148
 149 public:
 150   MIPrinter(raw_ostream &OS, ModuleSlotTracker &MST,
 151             const DenseMap<const uint32_t *, unsigned> &RegisterMaskIds,
 152             const DenseMap<int, FrameIndexOperand> &StackObjectOperandMapping)
 153       : OS(OS), MST(MST), RegisterMaskIds(RegisterMaskIds),
 154         StackObjectOperandMapping(StackObjectOperandMapping) {}
 155
 156   void print(const MachineBasicBlock &MBB);
 157
 158   void print(const MachineInstr &MI);
 159   void printStackObjectReference(int FrameIndex);
 160   void print(const MachineInstr &MI, unsigned OpIdx,
 161              const TargetRegisterInfo *TRI, const TargetInstrInfo *TII,
 162              bool ShouldPrintRegisterTies, LLT TypeToPrint,
 163              bool PrintDef = true);
 164 };
 165
 166 } // end namespace llvm
 167
 168 namespace llvm {
 169 namespace yaml {
 170
 171 /// This struct serializes the LLVM IR module.
 172 template <> struct BlockScalarTraits<Module> {
 173   static void output(const Module &Mod, void *Ctxt, raw_ostream &OS) {
 174     Mod.print(OS, nullptr);
 175   }
 176
 177   static StringRef input(StringRef Str, void *Ctxt, Module &Mod) {
 178     llvm_unreachable("LLVM Module is supposed to be parsed separately");
 179     return "";
 180   }
 181 };
 182
 183 } // end namespace yaml
 184 } // end namespace llvm
 185
 186 static void printRegMIR(unsigned Reg, yaml::StringValue &Dest,
 187                         const TargetRegisterInfo *TRI) {
 188   raw_string_ostream OS(Dest.Value);
 189   OS << printReg(Reg, TRI);
 190 }
 191
 192 void MIRPrinter::print(const MachineFunction &MF) {
 193   initRegisterMaskIds(MF);
 194
 195   yaml::MachineFunction YamlMF;
 196   YamlMF.Name = MF.getName();
 197   YamlMF.Alignment = MF.getAlignment();
 198   YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice();
 199   YamlMF.HasWinCFI = MF.hasWinCFI();
 200
 201   YamlMF.CallsEHReturn = MF.callsEHReturn();
 202   YamlMF.CallsUnwindInit = MF.callsUnwindInit();
 203   YamlMF.HasEHCatchret = MF.hasEHCatchret();
 204   YamlMF.HasEHScopes = MF.hasEHScopes();
 205   YamlMF.HasEHFunclets = MF.hasEHFunclets();
 206   YamlMF.IsOutlined = MF.isOutlined();
 207   YamlMF.UseDebugInstrRef = MF.useDebugInstrRef();
 208
 209   YamlMF.Legalized = MF.getProperties().hasProperty(
 210       MachineFunctionProperties::Property::Legalized);
 211   YamlMF.RegBankSelected = MF.getProperties().hasProperty(
 212       MachineFunctionProperties::Property::RegBankSelected);
 213   YamlMF.Selected = MF.getProperties().hasProperty(
 214       MachineFunctionProperties::Property::Selected);
 215   YamlMF.FailedISel = MF.getProperties().hasProperty(
 216       MachineFunctionProperties::Property::FailedISel);
 217   YamlMF.FailsVerification = MF.getProperties().hasProperty(
 218       MachineFunctionProperties::Property::FailsVerification);
 219   YamlMF.TracksDebugUserValues = MF.getProperties().hasProperty(
 220       MachineFunctionProperties::Property::TracksDebugUserValues);
 221
 222   convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
 223   MachineModuleSlotTracker MST(&MF);
 224   MST.incorporateFunction(MF.getFunction());
 225   convert(MST, YamlMF.FrameInfo, MF.getFrameInfo());
 226   convertStackObjects(YamlMF, MF, MST);
 227   convertEntryValueObjects(YamlMF, MF, MST);
 228   convertCallSiteObjects(YamlMF, MF, MST);
 229   for (const auto &Sub : MF.DebugValueSubstitutions) {
 230     const auto &SubSrc = Sub.Src;
 231     const auto &SubDest = Sub.Dest;
 232     YamlMF.DebugValueSubstitutions.push_back({SubSrc.first, SubSrc.second,
 233                                               SubDest.first,
 234                                               SubDest.second,
 235                                               Sub.Subreg});
 236   }
 237   if (const auto *ConstantPool = MF.getConstantPool())
 238     convert(YamlMF, *ConstantPool);
 239   if (const auto *JumpTableInfo = MF.getJumpTableInfo())
 240     convert(MST, YamlMF.JumpTableInfo, *JumpTableInfo);
 241
 242   const TargetMachine &TM = MF.getTarget();
 243   YamlMF.MachineFuncInfo =
 244       std::unique_ptr<yaml::MachineFunctionInfo>(TM.convertFuncInfoToYAML(MF));
 245
 246   raw_string_ostream StrOS(YamlMF.Body.Value.Value);
 247   bool IsNewlineNeeded = false;
 248   for (const auto &MBB : MF) {
 249     if (IsNewlineNeeded)
 250       StrOS << "\n";
 251     MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
 252         .print(MBB);
 253     IsNewlineNeeded = true;
 254   }
 255   StrOS.flush();
 256   // Convert machine metadata collected during the print of the machine
 257   // function.
 258   convertMachineMetadataNodes(YamlMF, MF, MST);
 259
 260   yaml::Output Out(OS);
 261   if (!SimplifyMIR)
 262       Out.setWriteDefaultValues(true);
 263   Out << YamlMF;
 264 }
 265
 266 static void printCustomRegMask(const uint32_t *RegMask, raw_ostream &OS,
 267                                const TargetRegisterInfo *TRI) {
 268   assert(RegMask && "Can't print an empty register mask");
 269   OS << StringRef("CustomRegMask(");
 270
 271   bool IsRegInRegMaskFound = false;
 272   for (int I = 0, E = TRI->getNumRegs(); I < E; I++) {
 273     // Check whether the register is asserted in regmask.
 274     if (RegMask[I / 32] & (1u << (I % 32))) {
 275       if (IsRegInRegMaskFound)
 276         OS << ',';
 277       OS << printReg(I, TRI);
 278       IsRegInRegMaskFound = true;
 279     }
 280   }
 281
 282   OS << ')';
 283 }
 284
 285 static void printRegClassOrBank(unsigned Reg, yaml::StringValue &Dest,
 286                                 const MachineRegisterInfo &RegInfo,
 287                                 const TargetRegisterInfo *TRI) {
 288   raw_string_ostream OS(Dest.Value);
 289   OS << printRegClassOrBank(Reg, RegInfo, TRI);
 290 }
 291
 292 template <typename T>
 293 static void
 294 printStackObjectDbgInfo(const MachineFunction::VariableDbgInfo &DebugVar,
 295                         T &Object, ModuleSlotTracker &MST) {
 296   std::array<std::string *, 3> Outputs{{&Object.DebugVar.Value,
 297                                         &Object.DebugExpr.Value,
 298                                         &Object.DebugLoc.Value}};
 299   std::array<const Metadata *, 3> Metas{{DebugVar.Var,
 300                                         DebugVar.Expr,
 301                                         DebugVar.Loc}};
 302   for (unsigned i = 0; i < 3; ++i) {
 303     raw_string_ostream StrOS(*Outputs[i]);
 304     Metas[i]->printAsOperand(StrOS, MST);
 305   }
 306 }
 307
 308 void MIRPrinter::convert(yaml::MachineFunction &MF,
 309                          const MachineRegisterInfo &RegInfo,
 310                          const TargetRegisterInfo *TRI) {
 311   MF.TracksRegLiveness = RegInfo.tracksLiveness();
 312
 313   // Print the virtual register definitions.
 314   for (unsigned I = 0, E = RegInfo.getNumVirtRegs(); I < E; ++I) {
 315     Register Reg = Register::index2VirtReg(I);
 316     yaml::VirtualRegisterDefinition VReg;
 317     VReg.ID = I;
 318     if (RegInfo.getVRegName(Reg) != "")
 319       continue;
 320     ::printRegClassOrBank(Reg, VReg.Class, RegInfo, TRI);
 321     Register PreferredReg = RegInfo.getSimpleHint(Reg);
 322     if (PreferredReg)
 323       printRegMIR(PreferredReg, VReg.PreferredRegister, TRI);
 324     MF.VirtualRegisters.push_back(VReg);
 325   }
 326
 327   // Print the live ins.
 328   for (std::pair<unsigned, unsigned> LI : RegInfo.liveins()) {
 329     yaml::MachineFunctionLiveIn LiveIn;
 330     printRegMIR(LI.first, LiveIn.Register, TRI);
 331     if (LI.second)
 332       printRegMIR(LI.second, LiveIn.VirtualRegister, TRI);
 333     MF.LiveIns.push_back(LiveIn);
 334   }
 335
 336   // Prints the callee saved registers.
 337   if (RegInfo.isUpdatedCSRsInitialized()) {
 338     const MCPhysReg *CalleeSavedRegs = RegInfo.getCalleeSavedRegs();
 339     std::vector<yaml::FlowStringValue> CalleeSavedRegisters;
 340     for (const MCPhysReg *I = CalleeSavedRegs; *I; ++I) {
 341       yaml::FlowStringValue Reg;
 342       printRegMIR(*I, Reg, TRI);
 343       CalleeSavedRegisters.push_back(Reg);
 344     }
 345     MF.CalleeSavedRegisters = CalleeSavedRegisters;
 346   }
 347 }
 348
 349 void MIRPrinter::convert(ModuleSlotTracker &MST,
 350                          yaml::MachineFrameInfo &YamlMFI,
 351                          const MachineFrameInfo &MFI) {
 352   YamlMFI.IsFrameAddressTaken = MFI.isFrameAddressTaken();
 353   YamlMFI.IsReturnAddressTaken = MFI.isReturnAddressTaken();
 354   YamlMFI.HasStackMap = MFI.hasStackMap();
 355   YamlMFI.HasPatchPoint = MFI.hasPatchPoint();
 356   YamlMFI.StackSize = MFI.getStackSize();
 357   YamlMFI.OffsetAdjustment = MFI.getOffsetAdjustment();
 358   YamlMFI.MaxAlignment = MFI.getMaxAlign().value();
 359   YamlMFI.AdjustsStack = MFI.adjustsStack();
 360   YamlMFI.HasCalls = MFI.hasCalls();
 361   YamlMFI.MaxCallFrameSize = MFI.isMaxCallFrameSizeComputed()
 362     ? MFI.getMaxCallFrameSize() : ~0u;
 363   YamlMFI.CVBytesOfCalleeSavedRegisters =
 364       MFI.getCVBytesOfCalleeSavedRegisters();
 365   YamlMFI.HasOpaqueSPAdjustment = MFI.hasOpaqueSPAdjustment();
 366   YamlMFI.HasVAStart = MFI.hasVAStart();
 367   YamlMFI.HasMustTailInVarArgFunc = MFI.hasMustTailInVarArgFunc();
 368   YamlMFI.HasTailCall = MFI.hasTailCall();
 369   YamlMFI.LocalFrameSize = MFI.getLocalFrameSize();
 370   if (MFI.getSavePoint()) {
 371     raw_string_ostream StrOS(YamlMFI.SavePoint.Value);
 372     StrOS << printMBBReference(*MFI.getSavePoint());
 373   }
 374   if (MFI.getRestorePoint()) {
 375     raw_string_ostream StrOS(YamlMFI.RestorePoint.Value);
 376     StrOS << printMBBReference(*MFI.getRestorePoint());
 377   }
 378 }
 379
 380 void MIRPrinter::convertEntryValueObjects(yaml::MachineFunction &YMF,
 381                                           const MachineFunction &MF,
 382                                           ModuleSlotTracker &MST) {
 383   const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
 384   for (const MachineFunction::VariableDbgInfo &DebugVar :
 385        MF.getEntryValueVariableDbgInfo()) {
 386     yaml::EntryValueObject &Obj = YMF.EntryValueObjects.emplace_back();
 387     printStackObjectDbgInfo(DebugVar, Obj, MST);
 388     MCRegister EntryValReg = DebugVar.getEntryValueRegister();
 389     printRegMIR(EntryValReg, Obj.EntryValueRegister, TRI);
 390   }
 391 }
 392
 393 void MIRPrinter::convertStackObjects(yaml::MachineFunction &YMF,
 394                                      const MachineFunction &MF,
 395                                      ModuleSlotTracker &MST) {
 396   const MachineFrameInfo &MFI = MF.getFrameInfo();
 397   const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
 398
 399   // Process fixed stack objects.
 400   assert(YMF.FixedStackObjects.empty());
 401   SmallVector<int, 32> FixedStackObjectsIdx;
 402   const int BeginIdx = MFI.getObjectIndexBegin();
 403   if (BeginIdx < 0)
 404     FixedStackObjectsIdx.reserve(-BeginIdx);
 405
 406   unsigned ID = 0;
 407   for (int I = BeginIdx; I < 0; ++I, ++ID) {
 408     FixedStackObjectsIdx.push_back(-1); // Fill index for possible dead.
 409     if (MFI.isDeadObjectIndex(I))
 410       continue;
 411
 412     yaml::FixedMachineStackObject YamlObject;
 413     YamlObject.ID = ID;
 414     YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
 415                           ? yaml::FixedMachineStackObject::SpillSlot
 416                           : yaml::FixedMachineStackObject::DefaultType;
 417     YamlObject.Offset = MFI.getObjectOffset(I);
 418     YamlObject.Size = MFI.getObjectSize(I);
 419     YamlObject.Alignment = MFI.getObjectAlign(I);
 420     YamlObject.StackID = (TargetStackID::Value)MFI.getStackID(I);
 421     YamlObject.IsImmutable = MFI.isImmutableObjectIndex(I);
 422     YamlObject.IsAliased = MFI.isAliasedObjectIndex(I);
 423     // Save the ID' position in FixedStackObjects storage vector.
 424     FixedStackObjectsIdx[ID] = YMF.FixedStackObjects.size();
 425     YMF.FixedStackObjects.push_back(YamlObject);
 426     StackObjectOperandMapping.insert(
 427         std::make_pair(I, FrameIndexOperand::createFixed(ID)));
 428   }
 429
 430   // Process ordinary stack objects.
 431   assert(YMF.StackObjects.empty());
 432   SmallVector<unsigned, 32> StackObjectsIdx;
 433   const int EndIdx = MFI.getObjectIndexEnd();
 434   if (EndIdx > 0)
 435     StackObjectsIdx.reserve(EndIdx);
 436   ID = 0;
 437   for (int I = 0; I < EndIdx; ++I, ++ID) {
 438     StackObjectsIdx.push_back(-1); // Fill index for possible dead.
 439     if (MFI.isDeadObjectIndex(I))
 440       continue;
 441
 442     yaml::MachineStackObject YamlObject;
 443     YamlObject.ID = ID;
 444     if (const auto *Alloca = MFI.getObjectAllocation(I))
 445       YamlObject.Name.Value = std::string(
 446           Alloca->hasName() ? Alloca->getName() : "");
 447     YamlObject.Type = MFI.isSpillSlotObjectIndex(I)
 448                           ? yaml::MachineStackObject::SpillSlot
 449                           : MFI.isVariableSizedObjectIndex(I)
 450                                 ? yaml::MachineStackObject::VariableSized
 451                                 : yaml::MachineStackObject::DefaultType;
 452     YamlObject.Offset = MFI.getObjectOffset(I);
 453     YamlObject.Size = MFI.getObjectSize(I);
 454     YamlObject.Alignment = MFI.getObjectAlign(I);
 455     YamlObject.StackID = (TargetStackID::Value)MFI.getStackID(I);
 456
 457     // Save the ID' position in StackObjects storage vector.
 458     StackObjectsIdx[ID] = YMF.StackObjects.size();
 459     YMF.StackObjects.push_back(YamlObject);
 460     StackObjectOperandMapping.insert(std::make_pair(
 461         I, FrameIndexOperand::create(YamlObject.Name.Value, ID)));
 462   }
 463
 464   for (const auto &CSInfo : MFI.getCalleeSavedInfo()) {
 465     const int FrameIdx = CSInfo.getFrameIdx();
 466     if (!CSInfo.isSpilledToReg() && MFI.isDeadObjectIndex(FrameIdx))
 467       continue;
 468
 469     yaml::StringValue Reg;
 470     printRegMIR(CSInfo.getReg(), Reg, TRI);
 471     if (!CSInfo.isSpilledToReg()) {
 472       assert(FrameIdx >= MFI.getObjectIndexBegin() &&
 473              FrameIdx < MFI.getObjectIndexEnd() &&
 474              "Invalid stack object index");
 475       if (FrameIdx < 0) { // Negative index means fixed objects.
 476         auto &Object =
 477             YMF.FixedStackObjects
 478                 [FixedStackObjectsIdx[FrameIdx + MFI.getNumFixedObjects()]];
 479         Object.CalleeSavedRegister = Reg;
 480         Object.CalleeSavedRestored = CSInfo.isRestored();
 481       } else {
 482         auto &Object = YMF.StackObjects[StackObjectsIdx[FrameIdx]];
 483         Object.CalleeSavedRegister = Reg;
 484         Object.CalleeSavedRestored = CSInfo.isRestored();
 485       }
 486     }
 487   }
 488   for (unsigned I = 0, E = MFI.getLocalFrameObjectCount(); I < E; ++I) {
 489     auto LocalObject = MFI.getLocalFrameObjectMap(I);
 490     assert(LocalObject.first >= 0 && "Expected a locally mapped stack object");
 491     YMF.StackObjects[StackObjectsIdx[LocalObject.first]].LocalOffset =
 492         LocalObject.second;
 493   }
 494
 495   // Print the stack object references in the frame information class after
 496   // converting the stack objects.
 497   if (MFI.hasStackProtectorIndex()) {
 498     raw_string_ostream StrOS(YMF.FrameInfo.StackProtector.Value);
 499     MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
 500         .printStackObjectReference(MFI.getStackProtectorIndex());
 501   }
 502
 503   if (MFI.hasFunctionContextIndex()) {
 504     raw_string_ostream StrOS(YMF.FrameInfo.FunctionContext.Value);
 505     MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
 506         .printStackObjectReference(MFI.getFunctionContextIndex());
 507   }
 508
 509   // Print the debug variable information.
 510   for (const MachineFunction::VariableDbgInfo &DebugVar :
 511        MF.getInStackSlotVariableDbgInfo()) {
 512     int Idx = DebugVar.getStackSlot();
 513     assert(Idx >= MFI.getObjectIndexBegin() && Idx < MFI.getObjectIndexEnd() &&
 514            "Invalid stack object index");
 515     if (Idx < 0) { // Negative index means fixed objects.
 516       auto &Object =
 517           YMF.FixedStackObjects[FixedStackObjectsIdx[Idx +
 518                                                      MFI.getNumFixedObjects()]];
 519       printStackObjectDbgInfo(DebugVar, Object, MST);
 520     } else {
 521       auto &Object = YMF.StackObjects[StackObjectsIdx[Idx]];
 522       printStackObjectDbgInfo(DebugVar, Object, MST);
 523     }
 524   }
 525 }
 526
 527 void MIRPrinter::convertCallSiteObjects(yaml::MachineFunction &YMF,
 528                                         const MachineFunction &MF,
 529                                         ModuleSlotTracker &MST) {
 530   const auto *TRI = MF.getSubtarget().getRegisterInfo();
 531   for (auto CSInfo : MF.getCallSitesInfo()) {
 532     yaml::CallSiteInfo YmlCS;
 533     yaml::CallSiteInfo::MachineInstrLoc CallLocation;
 534
 535     // Prepare instruction position.
 536     MachineBasicBlock::const_instr_iterator CallI = CSInfo.first->getIterator();
 537     CallLocation.BlockNum = CallI->getParent()->getNumber();
 538     // Get call instruction offset from the beginning of block.
 539     CallLocation.Offset =
 540         std::distance(CallI->getParent()->instr_begin(), CallI);
 541     YmlCS.CallLocation = CallLocation;
 542     // Construct call arguments and theirs forwarding register info.
 543     for (auto ArgReg : CSInfo.second) {
 544       yaml::CallSiteInfo::ArgRegPair YmlArgReg;
 545       YmlArgReg.ArgNo = ArgReg.ArgNo;
 546       printRegMIR(ArgReg.Reg, YmlArgReg.Reg, TRI);
 547       YmlCS.ArgForwardingRegs.emplace_back(YmlArgReg);
 548     }
 549     YMF.CallSitesInfo.push_back(YmlCS);
 550   }
 551
 552   // Sort call info by position of call instructions.
 553   llvm::sort(YMF.CallSitesInfo.begin(), YMF.CallSitesInfo.end(),
 554              [](yaml::CallSiteInfo A, yaml::CallSiteInfo B) {
 555                if (A.CallLocation.BlockNum == B.CallLocation.BlockNum)
 556                  return A.CallLocation.Offset < B.CallLocation.Offset;
 557                return A.CallLocation.BlockNum < B.CallLocation.BlockNum;
 558              });
 559 }
 560
 561 void MIRPrinter::convertMachineMetadataNodes(yaml::MachineFunction &YMF,
 562                                              const MachineFunction &MF,
 563                                              MachineModuleSlotTracker &MST) {
 564   MachineModuleSlotTracker::MachineMDNodeListType MDList;
 565   MST.collectMachineMDNodes(MDList);
 566   for (auto &MD : MDList) {
 567     std::string NS;
 568     raw_string_ostream StrOS(NS);
 569     MD.second->print(StrOS, MST, MF.getFunction().getParent());
 570     YMF.MachineMetadataNodes.push_back(StrOS.str());
 571   }
 572 }
 573
 574 void MIRPrinter::convert(yaml::MachineFunction &MF,
 575                          const MachineConstantPool &ConstantPool) {
 576   unsigned ID = 0;
 577   for (const MachineConstantPoolEntry &Constant : ConstantPool.getConstants()) {
 578     std::string Str;
 579     raw_string_ostream StrOS(Str);
 580     if (Constant.isMachineConstantPoolEntry()) {
 581       Constant.Val.MachineCPVal->print(StrOS);
 582     } else {
 583       Constant.Val.ConstVal->printAsOperand(StrOS);
 584     }
 585
 586     yaml::MachineConstantPoolValue YamlConstant;
 587     YamlConstant.ID = ID++;
 588     YamlConstant.Value = StrOS.str();
 589     YamlConstant.Alignment = Constant.getAlign();
 590     YamlConstant.IsTargetSpecific = Constant.isMachineConstantPoolEntry();
 591
 592     MF.Constants.push_back(YamlConstant);
 593   }
 594 }
 595
 596 void MIRPrinter::convert(ModuleSlotTracker &MST,
 597                          yaml::MachineJumpTable &YamlJTI,
 598                          const MachineJumpTableInfo &JTI) {
 599   YamlJTI.Kind = JTI.getEntryKind();
 600   unsigned ID = 0;
 601   for (const auto &Table : JTI.getJumpTables()) {
 602     std::string Str;
 603     yaml::MachineJumpTable::Entry Entry;
 604     Entry.ID = ID++;
 605     for (const auto *MBB : Table.MBBs) {
 606       raw_string_ostream StrOS(Str);
 607       StrOS << printMBBReference(*MBB);
 608       Entry.Blocks.push_back(StrOS.str());
 609       Str.clear();
 610     }
 611     YamlJTI.Entries.push_back(Entry);
 612   }
 613 }
 614
 615 void MIRPrinter::initRegisterMaskIds(const MachineFunction &MF) {
 616   const auto *TRI = MF.getSubtarget().getRegisterInfo();
 617   unsigned I = 0;
 618   for (const uint32_t *Mask : TRI->getRegMasks())
 619     RegisterMaskIds.insert(std::make_pair(Mask, I++));
 620 }
 621
 622 void llvm::guessSuccessors(const MachineBasicBlock &MBB,
 623                            SmallVectorImpl<MachineBasicBlock*> &Result,
 624                            bool &IsFallthrough) {
 625   SmallPtrSet<MachineBasicBlock*,8> Seen;
 626
 627   for (const MachineInstr &MI : MBB) {
 628     if (MI.isPHI())
 629       continue;
 630     for (const MachineOperand &MO : MI.operands()) {
 631       if (!MO.isMBB())
 632         continue;
 633       MachineBasicBlock *Succ = MO.getMBB();
 634       auto RP = Seen.insert(Succ);
 635       if (RP.second)
 636         Result.push_back(Succ);
 637     }
 638   }
 639   MachineBasicBlock::const_iterator I = MBB.getLastNonDebugInstr();
 640   IsFallthrough = I == MBB.end() || !I->isBarrier();
 641 }
 642
 643 bool
 644 MIPrinter::canPredictBranchProbabilities(const MachineBasicBlock &MBB) const {
 645   if (MBB.succ_size() <= 1)
 646     return true;
 647   if (!MBB.hasSuccessorProbabilities())
 648     return true;
 649
 650   SmallVector<BranchProbability,8> Normalized(MBB.Probs.begin(),
 651                                               MBB.Probs.end());
 652   BranchProbability::normalizeProbabilities(Normalized.begin(),
 653                                             Normalized.end());
 654   SmallVector<BranchProbability,8> Equal(Normalized.size());
 655   BranchProbability::normalizeProbabilities(Equal.begin(), Equal.end());
 656
 657   return std::equal(Normalized.begin(), Normalized.end(), Equal.begin());
 658 }
 659
 660 bool MIPrinter::canPredictSuccessors(const MachineBasicBlock &MBB) const {
 661   SmallVector<MachineBasicBlock*,8> GuessedSuccs;
 662   bool GuessedFallthrough;
 663   guessSuccessors(MBB, GuessedSuccs, GuessedFallthrough);
 664   if (GuessedFallthrough) {
 665     const MachineFunction &MF = *MBB.getParent();
 666     MachineFunction::const_iterator NextI = std::next(MBB.getIterator());
 667     if (NextI != MF.end()) {
 668       MachineBasicBlock *Next = const_cast<MachineBasicBlock*>(&*NextI);
 669       if (!is_contained(GuessedSuccs, Next))
 670         GuessedSuccs.push_back(Next);
 671     }
 672   }
 673   if (GuessedSuccs.size() != MBB.succ_size())
 674     return false;
 675   return std::equal(MBB.succ_begin(), MBB.succ_end(), GuessedSuccs.begin());
 676 }
 677
 678 void MIPrinter::print(const MachineBasicBlock &MBB) {
 679   assert(MBB.getNumber() >= 0 && "Invalid MBB number");
 680   MBB.printName(OS,
 681                 MachineBasicBlock::PrintNameIr |
 682                     MachineBasicBlock::PrintNameAttributes,
 683                 &MST);
 684   OS << ":\n";
 685
 686   bool HasLineAttributes = false;
 687   // Print the successors
 688   bool canPredictProbs = canPredictBranchProbabilities(MBB);
 689   // Even if the list of successors is empty, if we cannot guess it,
 690   // we need to print it to tell the parser that the list is empty.
 691   // This is needed, because MI model unreachable as empty blocks
 692   // with an empty successor list. If the parser would see that
 693   // without the successor list, it would guess the code would
 694   // fallthrough.
 695   if ((!MBB.succ_empty() && !SimplifyMIR) || !canPredictProbs ||
 696       !canPredictSuccessors(MBB)) {
 697     OS.indent(2) << "successors: ";
 698     for (auto I = MBB.succ_begin(), E = MBB.succ_end(); I != E; ++I) {
 699       if (I != MBB.succ_begin())
 700         OS << ", ";
 701       OS << printMBBReference(**I);
 702       if (!SimplifyMIR || !canPredictProbs)
 703         OS << '('
 704            << format("0x%08" PRIx32, MBB.getSuccProbability(I).getNumerator())
 705            << ')';
 706     }
 707     OS << "\n";
 708     HasLineAttributes = true;
 709   }
 710
 711   // Print the live in registers.
 712   const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
 713   if (!MBB.livein_empty()) {
 714     const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
 715     OS.indent(2) << "liveins: ";
 716     bool First = true;
 717     for (const auto &LI : MBB.liveins_dbg()) {
 718       if (!First)
 719         OS << ", ";
 720       First = false;
 721       OS << printReg(LI.PhysReg, &TRI);
 722       if (!LI.LaneMask.all())
 723         OS << ":0x" << PrintLaneMask(LI.LaneMask);
 724     }
 725     OS << "\n";
 726     HasLineAttributes = true;
 727   }
 728
 729   if (HasLineAttributes)
 730     OS << "\n";
 731   bool IsInBundle = false;
 732   for (auto I = MBB.instr_begin(), E = MBB.instr_end(); I != E; ++I) {
 733     const MachineInstr &MI = *I;
 734     if (IsInBundle && !MI.isInsideBundle()) {
 735       OS.indent(2) << "}\n";
 736       IsInBundle = false;
 737     }
 738     OS.indent(IsInBundle ? 4 : 2);
 739     print(MI);
 740     if (!IsInBundle && MI.getFlag(MachineInstr::BundledSucc)) {
 741       OS << " {";
 742       IsInBundle = true;
 743     }
 744     OS << "\n";
 745   }
 746   if (IsInBundle)
 747     OS.indent(2) << "}\n";
 748 }
 749
 750 void MIPrinter::print(const MachineInstr &MI) {
 751   const auto *MF = MI.getMF();
 752   const auto &MRI = MF->getRegInfo();
 753   const auto &SubTarget = MF->getSubtarget();
 754   const auto *TRI = SubTarget.getRegisterInfo();
 755   assert(TRI && "Expected target register info");
 756   const auto *TII = SubTarget.getInstrInfo();
 757   assert(TII && "Expected target instruction info");
 758   if (MI.isCFIInstruction())
 759     assert(MI.getNumOperands() == 1 && "Expected 1 operand in CFI instruction");
 760
 761   SmallBitVector PrintedTypes(8);
 762   bool ShouldPrintRegisterTies = MI.hasComplexRegisterTies();
 763   unsigned I = 0, E = MI.getNumOperands();
 764   for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() &&
 765          !MI.getOperand(I).isImplicit();
 766        ++I) {
 767     if (I)
 768       OS << ", ";
 769     print(MI, I, TRI, TII, ShouldPrintRegisterTies,
 770           MI.getTypeToPrint(I, PrintedTypes, MRI),
 771           /*PrintDef=*/false);
 772   }
 773
 774   if (I)
 775     OS << " = ";
 776   if (MI.getFlag(MachineInstr::FrameSetup))
 777     OS << "frame-setup ";
 778   if (MI.getFlag(MachineInstr::FrameDestroy))
 779     OS << "frame-destroy ";
 780   if (MI.getFlag(MachineInstr::FmNoNans))
 781     OS << "nnan ";
 782   if (MI.getFlag(MachineInstr::FmNoInfs))
 783     OS << "ninf ";
 784   if (MI.getFlag(MachineInstr::FmNsz))
 785     OS << "nsz ";
 786   if (MI.getFlag(MachineInstr::FmArcp))
 787     OS << "arcp ";
 788   if (MI.getFlag(MachineInstr::FmContract))
 789     OS << "contract ";
 790   if (MI.getFlag(MachineInstr::FmAfn))
 791     OS << "afn ";
 792   if (MI.getFlag(MachineInstr::FmReassoc))
 793     OS << "reassoc ";
 794   if (MI.getFlag(MachineInstr::NoUWrap))
 795     OS << "nuw ";
 796   if (MI.getFlag(MachineInstr::NoSWrap))
 797     OS << "nsw ";
 798   if (MI.getFlag(MachineInstr::IsExact))
 799     OS << "exact ";
 800   if (MI.getFlag(MachineInstr::NoFPExcept))
 801     OS << "nofpexcept ";
 802   if (MI.getFlag(MachineInstr::NoMerge))
 803     OS << "nomerge ";
 804   if (MI.getFlag(MachineInstr::Unpredictable))
 805     OS << "unpredictable ";
 806   if (MI.getFlag(MachineInstr::NoConvergent))
 807     OS << "noconvergent ";
 808
 809   OS << TII->getName(MI.getOpcode());
 810   if (I < E)
 811     OS << ' ';
 812
 813   bool NeedComma = false;
 814   for (; I < E; ++I) {
 815     if (NeedComma)
 816       OS << ", ";
 817     print(MI, I, TRI, TII, ShouldPrintRegisterTies,
 818           MI.getTypeToPrint(I, PrintedTypes, MRI));
 819     NeedComma = true;
 820   }
 821
 822   // Print any optional symbols attached to this instruction as-if they were
 823   // operands.
 824   if (MCSymbol *PreInstrSymbol = MI.getPreInstrSymbol()) {
 825     if (NeedComma)
 826       OS << ',';
 827     OS << " pre-instr-symbol ";
 828     MachineOperand::printSymbol(OS, *PreInstrSymbol);
 829     NeedComma = true;
 830   }
 831   if (MCSymbol *PostInstrSymbol = MI.getPostInstrSymbol()) {
 832     if (NeedComma)
 833       OS << ',';
 834     OS << " post-instr-symbol ";
 835     MachineOperand::printSymbol(OS, *PostInstrSymbol);
 836     NeedComma = true;
 837   }
 838   if (MDNode *HeapAllocMarker = MI.getHeapAllocMarker()) {
 839     if (NeedComma)
 840       OS << ',';
 841     OS << " heap-alloc-marker ";
 842     HeapAllocMarker->printAsOperand(OS, MST);
 843     NeedComma = true;
 844   }
 845   if (MDNode *PCSections = MI.getPCSections()) {
 846     if (NeedComma)
 847       OS << ',';
 848     OS << " pcsections ";
 849     PCSections->printAsOperand(OS, MST);
 850     NeedComma = true;
 851   }
 852   if (uint32_t CFIType = MI.getCFIType()) {
 853     if (NeedComma)
 854       OS << ',';
 855     OS << " cfi-type " << CFIType;
 856     NeedComma = true;
 857   }
 858
 859   if (auto Num = MI.peekDebugInstrNum()) {
 860     if (NeedComma)
 861       OS << ',';
 862     OS << " debug-instr-number " << Num;
 863     NeedComma = true;
 864   }
 865
 866   if (PrintLocations) {
 867     if (const DebugLoc &DL = MI.getDebugLoc()) {
 868       if (NeedComma)
 869         OS << ',';
 870       OS << " debug-location ";
 871       DL->printAsOperand(OS, MST);
 872     }
 873   }
 874
 875   if (!MI.memoperands_empty()) {
 876     OS << " :: ";
 877     const LLVMContext &Context = MF->getFunction().getContext();
 878     const MachineFrameInfo &MFI = MF->getFrameInfo();
 879     bool NeedComma = false;
 880     for (const auto *Op : MI.memoperands()) {
 881       if (NeedComma)
 882         OS << ", ";
 883       Op->print(OS, MST, SSNs, Context, &MFI, TII);
 884       NeedComma = true;
 885     }
 886   }
 887 }
 888
 889 void MIPrinter::printStackObjectReference(int FrameIndex) {
 890   auto ObjectInfo = StackObjectOperandMapping.find(FrameIndex);
 891   assert(ObjectInfo != StackObjectOperandMapping.end() &&
 892          "Invalid frame index");
 893   const FrameIndexOperand &Operand = ObjectInfo->second;
 894   MachineOperand::printStackObjectReference(OS, Operand.ID, Operand.IsFixed,
 895                                             Operand.Name);
 896 }
 897
 898 static std::string formatOperandComment(std::string Comment) {
 899   if (Comment.empty())
 900     return Comment;
 901   return std::string(" /* " + Comment + " */");
 902 }
 903
 904 void MIPrinter::print(const MachineInstr &MI, unsigned OpIdx,
 905                       const TargetRegisterInfo *TRI,
 906                       const TargetInstrInfo *TII,
 907                       bool ShouldPrintRegisterTies, LLT TypeToPrint,
 908                       bool PrintDef) {
 909   const MachineOperand &Op = MI.getOperand(OpIdx);
 910   std::string MOComment = TII->createMIROperandComment(MI, Op, OpIdx, TRI);
 911
 912   switch (Op.getType()) {
 913   case MachineOperand::MO_Immediate:
 914     if (MI.isOperandSubregIdx(OpIdx)) {
 915       MachineOperand::printTargetFlags(OS, Op);
 916       MachineOperand::printSubRegIdx(OS, Op.getImm(), TRI);
 917       break;
 918     }
 919     [[fallthrough]];
 920   case MachineOperand::MO_Register:
 921   case MachineOperand::MO_CImmediate:
 922   case MachineOperand::MO_FPImmediate:
 923   case MachineOperand::MO_MachineBasicBlock:
 924   case MachineOperand::MO_ConstantPoolIndex:
 925   case MachineOperand::MO_TargetIndex:
 926   case MachineOperand::MO_JumpTableIndex:
 927   case MachineOperand::MO_ExternalSymbol:
 928   case MachineOperand::MO_GlobalAddress:
 929   case MachineOperand::MO_RegisterLiveOut:
 930   case MachineOperand::MO_Metadata:
 931   case MachineOperand::MO_MCSymbol:
 932   case MachineOperand::MO_CFIIndex:
 933   case MachineOperand::MO_IntrinsicID:
 934   case MachineOperand::MO_Predicate:
 935   case MachineOperand::MO_BlockAddress:
 936   case MachineOperand::MO_DbgInstrRef:
 937   case MachineOperand::MO_ShuffleMask: {
 938     unsigned TiedOperandIdx = 0;
 939     if (ShouldPrintRegisterTies && Op.isReg() && Op.isTied() && !Op.isDef())
 940       TiedOperandIdx = Op.getParent()->findTiedOperandIdx(OpIdx);
 941     const TargetIntrinsicInfo *TII = MI.getMF()->getTarget().getIntrinsicInfo();
 942     Op.print(OS, MST, TypeToPrint, OpIdx, PrintDef, /*IsStandalone=*/false,
 943              ShouldPrintRegisterTies, TiedOperandIdx, TRI, TII);
 944       OS << formatOperandComment(MOComment);
 945     break;
 946   }
 947   case MachineOperand::MO_FrameIndex:
 948     printStackObjectReference(Op.getIndex());
 949     break;
 950   case MachineOperand::MO_RegisterMask: {
 951     auto RegMaskInfo = RegisterMaskIds.find(Op.getRegMask());
 952     if (RegMaskInfo != RegisterMaskIds.end())
 953       OS << StringRef(TRI->getRegMaskNames()[RegMaskInfo->second]).lower();
 954     else
 955       printCustomRegMask(Op.getRegMask(), OS, TRI);
 956     break;
 957   }
 958   }
 959 }
 960
 961 void MIRFormatter::printIRValue(raw_ostream &OS, const Value &V,
 962                                 ModuleSlotTracker &MST) {
 963   if (isa<GlobalValue>(V)) {
 964     V.printAsOperand(OS, /*PrintType=*/false, MST);
 965     return;
 966   }
 967   if (isa<Constant>(V)) {
 968     // Machine memory operands can load/store to/from constant value pointers.
 969     OS << '`';
 970     V.printAsOperand(OS, /*PrintType=*/true, MST);
 971     OS << '`';
 972     return;
 973   }
 974   OS << "%ir.";
 975   if (V.hasName()) {
 976     printLLVMNameWithoutPrefix(OS, V.getName());
 977     return;
 978   }
 979   int Slot = MST.getCurrentFunction() ? MST.getLocalSlot(&V) : -1;
 980   MachineOperand::printIRSlotNumber(OS, Slot);
 981 }
 982
 983 void llvm::printMIR(raw_ostream &OS, const Module &M) {
 984   yaml::Output Out(OS);
 985   Out << const_cast<Module &>(M);
 986 }
 987
 988 void llvm::printMIR(raw_ostream &OS, const MachineFunction &MF) {
 989   MIRPrinter Printer(OS);
 990   Printer.print(MF);
 991 }