llvm/lib/CodeGen/MachineOperand.cpp

   1 //===- lib/CodeGen/MachineOperand.cpp -------------------------------------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 /// \file Methods common to all machine operands.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #include "llvm/CodeGen/MachineOperand.h"
  14 #include "llvm/ADT/StableHashing.h"
  15 #include "llvm/ADT/StringExtras.h"
  16 #include "llvm/Analysis/Loads.h"
  17 #include "llvm/CodeGen/MIRFormatter.h"
  18 #include "llvm/CodeGen/MachineFrameInfo.h"
  19 #include "llvm/CodeGen/MachineJumpTableInfo.h"
  20 #include "llvm/CodeGen/MachineRegisterInfo.h"
  21 #include "llvm/CodeGen/TargetInstrInfo.h"
  22 #include "llvm/CodeGen/TargetRegisterInfo.h"
  23 #include "llvm/Config/llvm-config.h"
  24 #include "llvm/IR/Constants.h"
  25 #include "llvm/IR/IRPrintingPasses.h"
  26 #include "llvm/IR/Instructions.h"
  27 #include "llvm/IR/ModuleSlotTracker.h"
  28 #include "llvm/MC/MCDwarf.h"
  29 #include "llvm/Target/TargetIntrinsicInfo.h"
  30 #include "llvm/Target/TargetMachine.h"
  31 #include <optional>
  32
  33 using namespace llvm;
  34
  35 static cl::opt<int>
  36     PrintRegMaskNumRegs("print-regmask-num-regs",
  37                         cl::desc("Number of registers to limit to when "
  38                                  "printing regmask operands in IR dumps. "
  39                                  "unlimited = -1"),
  40                         cl::init(32), cl::Hidden);
  41
  42 static const MachineFunction *getMFIfAvailable(const MachineOperand &MO) {
  43   if (const MachineInstr *MI = MO.getParent())
  44     if (const MachineBasicBlock *MBB = MI->getParent())
  45       if (const MachineFunction *MF = MBB->getParent())
  46         return MF;
  47   return nullptr;
  48 }
  49
  50 static MachineFunction *getMFIfAvailable(MachineOperand &MO) {
  51   return const_cast<MachineFunction *>(
  52       getMFIfAvailable(const_cast<const MachineOperand &>(MO)));
  53 }
  54
  55 unsigned MachineOperand::getOperandNo() const {
  56   assert(getParent() && "Operand does not belong to any instruction!");
  57   return getParent()->getOperandNo(this);
  58 }
  59
  60 void MachineOperand::setReg(Register Reg) {
  61   if (getReg() == Reg)
  62     return; // No change.
  63
  64   // Clear the IsRenamable bit to keep it conservatively correct.
  65   IsRenamable = false;
  66
  67   // Otherwise, we have to change the register.  If this operand is embedded
  68   // into a machine function, we need to update the old and new register's
  69   // use/def lists.
  70   if (MachineFunction *MF = getMFIfAvailable(*this)) {
  71     MachineRegisterInfo &MRI = MF->getRegInfo();
  72     MRI.removeRegOperandFromUseList(this);
  73     SmallContents.RegNo = Reg;
  74     MRI.addRegOperandToUseList(this);
  75     return;
  76   }
  77
  78   // Otherwise, just change the register, no problem.  :)
  79   SmallContents.RegNo = Reg;
  80 }
  81
  82 void MachineOperand::substVirtReg(Register Reg, unsigned SubIdx,
  83                                   const TargetRegisterInfo &TRI) {
  84   assert(Reg.isVirtual());
  85   if (SubIdx && getSubReg())
  86     SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
  87   setReg(Reg);
  88   if (SubIdx)
  89     setSubReg(SubIdx);
  90 }
  91
  92 void MachineOperand::substPhysReg(MCRegister Reg, const TargetRegisterInfo &TRI) {
  93   assert(Register::isPhysicalRegister(Reg));
  94   if (getSubReg()) {
  95     Reg = TRI.getSubReg(Reg, getSubReg());
  96     // Note that getSubReg() may return 0 if the sub-register doesn't exist.
  97     // That won't happen in legal code.
  98     setSubReg(0);
  99     if (isDef())
 100       setIsUndef(false);
 101   }
 102   setReg(Reg);
 103 }
 104
 105 /// Change a def to a use, or a use to a def.
 106 void MachineOperand::setIsDef(bool Val) {
 107   assert(isReg() && "Wrong MachineOperand accessor");
 108   assert((!Val || !isDebug()) && "Marking a debug operation as def");
 109   if (IsDef == Val)
 110     return;
 111   assert(!IsDeadOrKill && "Changing def/use with dead/kill set not supported");
 112   // MRI may keep uses and defs in different list positions.
 113   if (MachineFunction *MF = getMFIfAvailable(*this)) {
 114     MachineRegisterInfo &MRI = MF->getRegInfo();
 115     MRI.removeRegOperandFromUseList(this);
 116     IsDef = Val;
 117     MRI.addRegOperandToUseList(this);
 118     return;
 119   }
 120   IsDef = Val;
 121 }
 122
 123 bool MachineOperand::isRenamable() const {
 124   assert(isReg() && "Wrong MachineOperand accessor");
 125   assert(getReg().isPhysical() &&
 126          "isRenamable should only be checked on physical registers");
 127   if (!IsRenamable)
 128     return false;
 129
 130   const MachineInstr *MI = getParent();
 131   if (!MI)
 132     return true;
 133
 134   if (isDef())
 135     return !MI->hasExtraDefRegAllocReq(MachineInstr::IgnoreBundle);
 136
 137   assert(isUse() && "Reg is not def or use");
 138   return !MI->hasExtraSrcRegAllocReq(MachineInstr::IgnoreBundle);
 139 }
 140
 141 void MachineOperand::setIsRenamable(bool Val) {
 142   assert(isReg() && "Wrong MachineOperand accessor");
 143   assert(getReg().isPhysical() &&
 144          "setIsRenamable should only be called on physical registers");
 145   IsRenamable = Val;
 146 }
 147
 148 // If this operand is currently a register operand, and if this is in a
 149 // function, deregister the operand from the register's use/def list.
 150 void MachineOperand::removeRegFromUses() {
 151   if (!isReg() || !isOnRegUseList())
 152     return;
 153
 154   if (MachineFunction *MF = getMFIfAvailable(*this))
 155     MF->getRegInfo().removeRegOperandFromUseList(this);
 156 }
 157
 158 /// ChangeToImmediate - Replace this operand with a new immediate operand of
 159 /// the specified value.  If an operand is known to be an immediate already,
 160 /// the setImm method should be used.
 161 void MachineOperand::ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags) {
 162   assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
 163
 164   removeRegFromUses();
 165
 166   OpKind = MO_Immediate;
 167   Contents.ImmVal = ImmVal;
 168   setTargetFlags(TargetFlags);
 169 }
 170
 171 void MachineOperand::ChangeToFPImmediate(const ConstantFP *FPImm,
 172                                          unsigned TargetFlags) {
 173   assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
 174
 175   removeRegFromUses();
 176
 177   OpKind = MO_FPImmediate;
 178   Contents.CFP = FPImm;
 179   setTargetFlags(TargetFlags);
 180 }
 181
 182 void MachineOperand::ChangeToES(const char *SymName,
 183                                 unsigned TargetFlags) {
 184   assert((!isReg() || !isTied()) &&
 185          "Cannot change a tied operand into an external symbol");
 186
 187   removeRegFromUses();
 188
 189   OpKind = MO_ExternalSymbol;
 190   Contents.OffsetedInfo.Val.SymbolName = SymName;
 191   setOffset(0); // Offset is always 0.
 192   setTargetFlags(TargetFlags);
 193 }
 194
 195 void MachineOperand::ChangeToGA(const GlobalValue *GV, int64_t Offset,
 196                                 unsigned TargetFlags) {
 197   assert((!isReg() || !isTied()) &&
 198          "Cannot change a tied operand into a global address");
 199
 200   removeRegFromUses();
 201
 202   OpKind = MO_GlobalAddress;
 203   Contents.OffsetedInfo.Val.GV = GV;
 204   setOffset(Offset);
 205   setTargetFlags(TargetFlags);
 206 }
 207
 208 void MachineOperand::ChangeToMCSymbol(MCSymbol *Sym, unsigned TargetFlags) {
 209   assert((!isReg() || !isTied()) &&
 210          "Cannot change a tied operand into an MCSymbol");
 211
 212   removeRegFromUses();
 213
 214   OpKind = MO_MCSymbol;
 215   Contents.Sym = Sym;
 216   setTargetFlags(TargetFlags);
 217 }
 218
 219 void MachineOperand::ChangeToFrameIndex(int Idx, unsigned TargetFlags) {
 220   assert((!isReg() || !isTied()) &&
 221          "Cannot change a tied operand into a FrameIndex");
 222
 223   removeRegFromUses();
 224
 225   OpKind = MO_FrameIndex;
 226   setIndex(Idx);
 227   setTargetFlags(TargetFlags);
 228 }
 229
 230 void MachineOperand::ChangeToTargetIndex(unsigned Idx, int64_t Offset,
 231                                          unsigned TargetFlags) {
 232   assert((!isReg() || !isTied()) &&
 233          "Cannot change a tied operand into a FrameIndex");
 234
 235   removeRegFromUses();
 236
 237   OpKind = MO_TargetIndex;
 238   setIndex(Idx);
 239   setOffset(Offset);
 240   setTargetFlags(TargetFlags);
 241 }
 242
 243 void MachineOperand::ChangeToDbgInstrRef(unsigned InstrIdx, unsigned OpIdx,
 244                                          unsigned TargetFlags) {
 245   assert((!isReg() || !isTied()) &&
 246          "Cannot change a tied operand into a DbgInstrRef");
 247
 248   removeRegFromUses();
 249
 250   OpKind = MO_DbgInstrRef;
 251   setInstrRefInstrIndex(InstrIdx);
 252   setInstrRefOpIndex(OpIdx);
 253   setTargetFlags(TargetFlags);
 254 }
 255
 256 /// ChangeToRegister - Replace this operand with a new register operand of
 257 /// the specified value.  If an operand is known to be an register already,
 258 /// the setReg method should be used.
 259 void MachineOperand::ChangeToRegister(Register Reg, bool isDef, bool isImp,
 260                                       bool isKill, bool isDead, bool isUndef,
 261                                       bool isDebug) {
 262   MachineRegisterInfo *RegInfo = nullptr;
 263   if (MachineFunction *MF = getMFIfAvailable(*this))
 264     RegInfo = &MF->getRegInfo();
 265   // If this operand is already a register operand, remove it from the
 266   // register's use/def lists.
 267   bool WasReg = isReg();
 268   if (RegInfo && WasReg)
 269     RegInfo->removeRegOperandFromUseList(this);
 270
 271   // Ensure debug instructions set debug flag on register uses.
 272   const MachineInstr *MI = getParent();
 273   if (!isDef && MI && MI->isDebugInstr())
 274     isDebug = true;
 275
 276   // Change this to a register and set the reg#.
 277   assert(!(isDead && !isDef) && "Dead flag on non-def");
 278   assert(!(isKill && isDef) && "Kill flag on def");
 279   OpKind = MO_Register;
 280   SmallContents.RegNo = Reg;
 281   SubReg_TargetFlags = 0;
 282   IsDef = isDef;
 283   IsImp = isImp;
 284   IsDeadOrKill = isKill | isDead;
 285   IsRenamable = false;
 286   IsUndef = isUndef;
 287   IsInternalRead = false;
 288   IsEarlyClobber = false;
 289   IsDebug = isDebug;
 290   // Ensure isOnRegUseList() returns false.
 291   Contents.Reg.Prev = nullptr;
 292   // Preserve the tie when the operand was already a register.
 293   if (!WasReg)
 294     TiedTo = 0;
 295
 296   // If this operand is embedded in a function, add the operand to the
 297   // register's use/def list.
 298   if (RegInfo)
 299     RegInfo->addRegOperandToUseList(this);
 300 }
 301
 302 /// isIdenticalTo - Return true if this operand is identical to the specified
 303 /// operand. Note that this should stay in sync with the hash_value overload
 304 /// below.
 305 bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
 306   if (getType() != Other.getType() ||
 307       getTargetFlags() != Other.getTargetFlags())
 308     return false;
 309
 310   switch (getType()) {
 311   case MachineOperand::MO_Register:
 312     return getReg() == Other.getReg() && isDef() == Other.isDef() &&
 313            getSubReg() == Other.getSubReg();
 314   case MachineOperand::MO_Immediate:
 315     return getImm() == Other.getImm();
 316   case MachineOperand::MO_CImmediate:
 317     return getCImm() == Other.getCImm();
 318   case MachineOperand::MO_FPImmediate:
 319     return getFPImm() == Other.getFPImm();
 320   case MachineOperand::MO_MachineBasicBlock:
 321     return getMBB() == Other.getMBB();
 322   case MachineOperand::MO_FrameIndex:
 323     return getIndex() == Other.getIndex();
 324   case MachineOperand::MO_ConstantPoolIndex:
 325   case MachineOperand::MO_TargetIndex:
 326     return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
 327   case MachineOperand::MO_JumpTableIndex:
 328     return getIndex() == Other.getIndex();
 329   case MachineOperand::MO_GlobalAddress:
 330     return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
 331   case MachineOperand::MO_ExternalSymbol:
 332     return strcmp(getSymbolName(), Other.getSymbolName()) == 0 &&
 333            getOffset() == Other.getOffset();
 334   case MachineOperand::MO_BlockAddress:
 335     return getBlockAddress() == Other.getBlockAddress() &&
 336            getOffset() == Other.getOffset();
 337   case MachineOperand::MO_RegisterMask:
 338   case MachineOperand::MO_RegisterLiveOut: {
 339     // Shallow compare of the two RegMasks
 340     const uint32_t *RegMask = getRegMask();
 341     const uint32_t *OtherRegMask = Other.getRegMask();
 342     if (RegMask == OtherRegMask)
 343       return true;
 344
 345     if (const MachineFunction *MF = getMFIfAvailable(*this)) {
 346       const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
 347       unsigned RegMaskSize = MachineOperand::getRegMaskSize(TRI->getNumRegs());
 348       // Deep compare of the two RegMasks
 349       return std::equal(RegMask, RegMask + RegMaskSize, OtherRegMask);
 350     }
 351     // We don't know the size of the RegMask, so we can't deep compare the two
 352     // reg masks.
 353     return false;
 354   }
 355   case MachineOperand::MO_MCSymbol:
 356     return getMCSymbol() == Other.getMCSymbol();
 357   case MachineOperand::MO_DbgInstrRef:
 358     return getInstrRefInstrIndex() == Other.getInstrRefInstrIndex() &&
 359            getInstrRefOpIndex() == Other.getInstrRefOpIndex();
 360   case MachineOperand::MO_CFIIndex:
 361     return getCFIIndex() == Other.getCFIIndex();
 362   case MachineOperand::MO_Metadata:
 363     return getMetadata() == Other.getMetadata();
 364   case MachineOperand::MO_IntrinsicID:
 365     return getIntrinsicID() == Other.getIntrinsicID();
 366   case MachineOperand::MO_Predicate:
 367     return getPredicate() == Other.getPredicate();
 368   case MachineOperand::MO_ShuffleMask:
 369     return getShuffleMask() == Other.getShuffleMask();
 370   }
 371   llvm_unreachable("Invalid machine operand type");
 372 }
 373
 374 // Note: this must stay exactly in sync with isIdenticalTo above.
 375 hash_code llvm::hash_value(const MachineOperand &MO) {
 376   switch (MO.getType()) {
 377   case MachineOperand::MO_Register:
 378     // Register operands don't have target flags.
 379     return hash_combine(MO.getType(), (unsigned)MO.getReg(), MO.getSubReg(), MO.isDef());
 380   case MachineOperand::MO_Immediate:
 381     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
 382   case MachineOperand::MO_CImmediate:
 383     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm());
 384   case MachineOperand::MO_FPImmediate:
 385     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm());
 386   case MachineOperand::MO_MachineBasicBlock:
 387     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB());
 388   case MachineOperand::MO_FrameIndex:
 389     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
 390   case MachineOperand::MO_ConstantPoolIndex:
 391   case MachineOperand::MO_TargetIndex:
 392     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(),
 393                         MO.getOffset());
 394   case MachineOperand::MO_JumpTableIndex:
 395     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
 396   case MachineOperand::MO_ExternalSymbol:
 397     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(),
 398                         StringRef(MO.getSymbolName()));
 399   case MachineOperand::MO_GlobalAddress:
 400     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(),
 401                         MO.getOffset());
 402   case MachineOperand::MO_BlockAddress:
 403     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getBlockAddress(),
 404                         MO.getOffset());
 405   case MachineOperand::MO_RegisterMask:
 406   case MachineOperand::MO_RegisterLiveOut: {
 407     if (const MachineFunction *MF = getMFIfAvailable(MO)) {
 408       const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
 409       unsigned RegMaskSize = MachineOperand::getRegMaskSize(TRI->getNumRegs());
 410       const uint32_t *RegMask = MO.getRegMask();
 411       std::vector<stable_hash> RegMaskHashes(RegMask, RegMask + RegMaskSize);
 412       return hash_combine(MO.getType(), MO.getTargetFlags(),
 413                           stable_hash_combine_array(RegMaskHashes.data(),
 414                                                     RegMaskHashes.size()));
 415     }
 416
 417     assert(0 && "MachineOperand not associated with any MachineFunction");
 418     return hash_combine(MO.getType(), MO.getTargetFlags());
 419   }
 420   case MachineOperand::MO_Metadata:
 421     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());
 422   case MachineOperand::MO_MCSymbol:
 423     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol());
 424   case MachineOperand::MO_DbgInstrRef:
 425     return hash_combine(MO.getType(), MO.getTargetFlags(),
 426                         MO.getInstrRefInstrIndex(), MO.getInstrRefOpIndex());
 427   case MachineOperand::MO_CFIIndex:
 428     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCFIIndex());
 429   case MachineOperand::MO_IntrinsicID:
 430     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIntrinsicID());
 431   case MachineOperand::MO_Predicate:
 432     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getPredicate());
 433   case MachineOperand::MO_ShuffleMask:
 434     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getShuffleMask());
 435   }
 436   llvm_unreachable("Invalid machine operand type");
 437 }
 438
 439 // Try to crawl up to the machine function and get TRI and IntrinsicInfo from
 440 // it.
 441 static void tryToGetTargetInfo(const MachineOperand &MO,
 442                                const TargetRegisterInfo *&TRI,
 443                                const TargetIntrinsicInfo *&IntrinsicInfo) {
 444   if (const MachineFunction *MF = getMFIfAvailable(MO)) {
 445     TRI = MF->getSubtarget().getRegisterInfo();
 446     IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
 447   }
 448 }
 449
 450 static const char *getTargetIndexName(const MachineFunction &MF, int Index) {
 451   const auto *TII = MF.getSubtarget().getInstrInfo();
 452   assert(TII && "expected instruction info");
 453   auto Indices = TII->getSerializableTargetIndices();
 454   auto Found = find_if(Indices, [&](const std::pair<int, const char *> &I) {
 455     return I.first == Index;
 456   });
 457   if (Found != Indices.end())
 458     return Found->second;
 459   return nullptr;
 460 }
 461
 462 const char *MachineOperand::getTargetIndexName() const {
 463   const MachineFunction *MF = getMFIfAvailable(*this);
 464   return MF ? ::getTargetIndexName(*MF, this->getIndex()) : nullptr;
 465 }
 466
 467 static const char *getTargetFlagName(const TargetInstrInfo *TII, unsigned TF) {
 468   auto Flags = TII->getSerializableDirectMachineOperandTargetFlags();
 469   for (const auto &I : Flags) {
 470     if (I.first == TF) {
 471       return I.second;
 472     }
 473   }
 474   return nullptr;
 475 }
 476
 477 static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS,
 478                              const TargetRegisterInfo *TRI) {
 479   if (!TRI) {
 480     OS << "%dwarfreg." << DwarfReg;
 481     return;
 482   }
 483
 484   if (std::optional<unsigned> Reg = TRI->getLLVMRegNum(DwarfReg, true))
 485     OS << printReg(*Reg, TRI);
 486   else
 487     OS << "<badreg>";
 488 }
 489
 490 static void printIRBlockReference(raw_ostream &OS, const BasicBlock &BB,
 491                                   ModuleSlotTracker &MST) {
 492   OS << "%ir-block.";
 493   if (BB.hasName()) {
 494     printLLVMNameWithoutPrefix(OS, BB.getName());
 495     return;
 496   }
 497   std::optional<int> Slot;
 498   if (const Function *F = BB.getParent()) {
 499     if (F == MST.getCurrentFunction()) {
 500       Slot = MST.getLocalSlot(&BB);
 501     } else if (const Module *M = F->getParent()) {
 502       ModuleSlotTracker CustomMST(M, /*ShouldInitializeAllMetadata=*/false);
 503       CustomMST.incorporateFunction(*F);
 504       Slot = CustomMST.getLocalSlot(&BB);
 505     }
 506   }
 507   if (Slot)
 508     MachineOperand::printIRSlotNumber(OS, *Slot);
 509   else
 510     OS << "<unknown>";
 511 }
 512
 513 static void printSyncScope(raw_ostream &OS, const LLVMContext &Context,
 514                            SyncScope::ID SSID,
 515                            SmallVectorImpl<StringRef> &SSNs) {
 516   switch (SSID) {
 517   case SyncScope::System:
 518     break;
 519   default:
 520     if (SSNs.empty())
 521       Context.getSyncScopeNames(SSNs);
 522
 523     OS << "syncscope(\"";
 524     printEscapedString(SSNs[SSID], OS);
 525     OS << "\") ";
 526     break;
 527   }
 528 }
 529
 530 static const char *getTargetMMOFlagName(const TargetInstrInfo &TII,
 531                                         unsigned TMMOFlag) {
 532   auto Flags = TII.getSerializableMachineMemOperandTargetFlags();
 533   for (const auto &I : Flags) {
 534     if (I.first == TMMOFlag) {
 535       return I.second;
 536     }
 537   }
 538   return nullptr;
 539 }
 540
 541 static void printFrameIndex(raw_ostream& OS, int FrameIndex, bool IsFixed,
 542                             const MachineFrameInfo *MFI) {
 543   StringRef Name;
 544   if (MFI) {
 545     IsFixed = MFI->isFixedObjectIndex(FrameIndex);
 546     if (const AllocaInst *Alloca = MFI->getObjectAllocation(FrameIndex))
 547       if (Alloca->hasName())
 548         Name = Alloca->getName();
 549     if (IsFixed)
 550       FrameIndex -= MFI->getObjectIndexBegin();
 551   }
 552   MachineOperand::printStackObjectReference(OS, FrameIndex, IsFixed, Name);
 553 }
 554
 555 void MachineOperand::printSubRegIdx(raw_ostream &OS, uint64_t Index,
 556                                     const TargetRegisterInfo *TRI) {
 557   OS << "%subreg.";
 558   if (TRI && Index != 0 && Index < TRI->getNumSubRegIndices())
 559     OS << TRI->getSubRegIndexName(Index);
 560   else
 561     OS << Index;
 562 }
 563
 564 void MachineOperand::printTargetFlags(raw_ostream &OS,
 565                                       const MachineOperand &Op) {
 566   if (!Op.getTargetFlags())
 567     return;
 568   const MachineFunction *MF = getMFIfAvailable(Op);
 569   if (!MF)
 570     return;
 571
 572   const auto *TII = MF->getSubtarget().getInstrInfo();
 573   assert(TII && "expected instruction info");
 574   auto Flags = TII->decomposeMachineOperandsTargetFlags(Op.getTargetFlags());
 575   OS << "target-flags(";
 576   const bool HasDirectFlags = Flags.first;
 577   const bool HasBitmaskFlags = Flags.second;
 578   if (!HasDirectFlags && !HasBitmaskFlags) {
 579     OS << "<unknown>) ";
 580     return;
 581   }
 582   if (HasDirectFlags) {
 583     if (const auto *Name = getTargetFlagName(TII, Flags.first))
 584       OS << Name;
 585     else
 586       OS << "<unknown target flag>";
 587   }
 588   if (!HasBitmaskFlags) {
 589     OS << ") ";
 590     return;
 591   }
 592   bool IsCommaNeeded = HasDirectFlags;
 593   unsigned BitMask = Flags.second;
 594   auto BitMasks = TII->getSerializableBitmaskMachineOperandTargetFlags();
 595   for (const auto &Mask : BitMasks) {
 596     // Check if the flag's bitmask has the bits of the current mask set.
 597     if ((BitMask & Mask.first) == Mask.first) {
 598       if (IsCommaNeeded)
 599         OS << ", ";
 600       IsCommaNeeded = true;
 601       OS << Mask.second;
 602       // Clear the bits which were serialized from the flag's bitmask.
 603       BitMask &= ~(Mask.first);
 604     }
 605   }
 606   if (BitMask) {
 607     // When the resulting flag's bitmask isn't zero, we know that we didn't
 608     // serialize all of the bit flags.
 609     if (IsCommaNeeded)
 610       OS << ", ";
 611     OS << "<unknown bitmask target flag>";
 612   }
 613   OS << ") ";
 614 }
 615
 616 void MachineOperand::printSymbol(raw_ostream &OS, MCSymbol &Sym) {
 617   OS << "<mcsymbol " << Sym << ">";
 618 }
 619
 620 void MachineOperand::printStackObjectReference(raw_ostream &OS,
 621                                                unsigned FrameIndex,
 622                                                bool IsFixed, StringRef Name) {
 623   if (IsFixed) {
 624     OS << "%fixed-stack." << FrameIndex;
 625     return;
 626   }
 627
 628   OS << "%stack." << FrameIndex;
 629   if (!Name.empty())
 630     OS << '.' << Name;
 631 }
 632
 633 void MachineOperand::printOperandOffset(raw_ostream &OS, int64_t Offset) {
 634   if (Offset == 0)
 635     return;
 636   if (Offset < 0) {
 637     OS << " - " << -Offset;
 638     return;
 639   }
 640   OS << " + " << Offset;
 641 }
 642
 643 void MachineOperand::printIRSlotNumber(raw_ostream &OS, int Slot) {
 644   if (Slot == -1)
 645     OS << "<badref>";
 646   else
 647     OS << Slot;
 648 }
 649
 650 static void printCFI(raw_ostream &OS, const MCCFIInstruction &CFI,
 651                      const TargetRegisterInfo *TRI) {
 652   switch (CFI.getOperation()) {
 653   case MCCFIInstruction::OpSameValue:
 654     OS << "same_value ";
 655     if (MCSymbol *Label = CFI.getLabel())
 656       MachineOperand::printSymbol(OS, *Label);
 657     printCFIRegister(CFI.getRegister(), OS, TRI);
 658     break;
 659   case MCCFIInstruction::OpRememberState:
 660     OS << "remember_state ";
 661     if (MCSymbol *Label = CFI.getLabel())
 662       MachineOperand::printSymbol(OS, *Label);
 663     break;
 664   case MCCFIInstruction::OpRestoreState:
 665     OS << "restore_state ";
 666     if (MCSymbol *Label = CFI.getLabel())
 667       MachineOperand::printSymbol(OS, *Label);
 668     break;
 669   case MCCFIInstruction::OpOffset:
 670     OS << "offset ";
 671     if (MCSymbol *Label = CFI.getLabel())
 672       MachineOperand::printSymbol(OS, *Label);
 673     printCFIRegister(CFI.getRegister(), OS, TRI);
 674     OS << ", " << CFI.getOffset();
 675     break;
 676   case MCCFIInstruction::OpDefCfaRegister:
 677     OS << "def_cfa_register ";
 678     if (MCSymbol *Label = CFI.getLabel())
 679       MachineOperand::printSymbol(OS, *Label);
 680     printCFIRegister(CFI.getRegister(), OS, TRI);
 681     break;
 682   case MCCFIInstruction::OpDefCfaOffset:
 683     OS << "def_cfa_offset ";
 684     if (MCSymbol *Label = CFI.getLabel())
 685       MachineOperand::printSymbol(OS, *Label);
 686     OS << CFI.getOffset();
 687     break;
 688   case MCCFIInstruction::OpDefCfa:
 689     OS << "def_cfa ";
 690     if (MCSymbol *Label = CFI.getLabel())
 691       MachineOperand::printSymbol(OS, *Label);
 692     printCFIRegister(CFI.getRegister(), OS, TRI);
 693     OS << ", " << CFI.getOffset();
 694     break;
 695   case MCCFIInstruction::OpLLVMDefAspaceCfa:
 696     OS << "llvm_def_aspace_cfa ";
 697     if (MCSymbol *Label = CFI.getLabel())
 698       MachineOperand::printSymbol(OS, *Label);
 699     printCFIRegister(CFI.getRegister(), OS, TRI);
 700     OS << ", " << CFI.getOffset();
 701     OS << ", " << CFI.getAddressSpace();
 702     break;
 703   case MCCFIInstruction::OpRelOffset:
 704     OS << "rel_offset ";
 705     if (MCSymbol *Label = CFI.getLabel())
 706       MachineOperand::printSymbol(OS, *Label);
 707     printCFIRegister(CFI.getRegister(), OS, TRI);
 708     OS << ", " << CFI.getOffset();
 709     break;
 710   case MCCFIInstruction::OpAdjustCfaOffset:
 711     OS << "adjust_cfa_offset ";
 712     if (MCSymbol *Label = CFI.getLabel())
 713       MachineOperand::printSymbol(OS, *Label);
 714     OS << CFI.getOffset();
 715     break;
 716   case MCCFIInstruction::OpRestore:
 717     OS << "restore ";
 718     if (MCSymbol *Label = CFI.getLabel())
 719       MachineOperand::printSymbol(OS, *Label);
 720     printCFIRegister(CFI.getRegister(), OS, TRI);
 721     break;
 722   case MCCFIInstruction::OpEscape: {
 723     OS << "escape ";
 724     if (MCSymbol *Label = CFI.getLabel())
 725       MachineOperand::printSymbol(OS, *Label);
 726     if (!CFI.getValues().empty()) {
 727       size_t e = CFI.getValues().size() - 1;
 728       for (size_t i = 0; i < e; ++i)
 729         OS << format("0x%02x", uint8_t(CFI.getValues()[i])) << ", ";
 730       OS << format("0x%02x", uint8_t(CFI.getValues()[e]));
 731     }
 732     break;
 733   }
 734   case MCCFIInstruction::OpUndefined:
 735     OS << "undefined ";
 736     if (MCSymbol *Label = CFI.getLabel())
 737       MachineOperand::printSymbol(OS, *Label);
 738     printCFIRegister(CFI.getRegister(), OS, TRI);
 739     break;
 740   case MCCFIInstruction::OpRegister:
 741     OS << "register ";
 742     if (MCSymbol *Label = CFI.getLabel())
 743       MachineOperand::printSymbol(OS, *Label);
 744     printCFIRegister(CFI.getRegister(), OS, TRI);
 745     OS << ", ";
 746     printCFIRegister(CFI.getRegister2(), OS, TRI);
 747     break;
 748   case MCCFIInstruction::OpWindowSave:
 749     OS << "window_save ";
 750     if (MCSymbol *Label = CFI.getLabel())
 751       MachineOperand::printSymbol(OS, *Label);
 752     break;
 753   case MCCFIInstruction::OpNegateRAState:
 754     OS << "negate_ra_sign_state ";
 755     if (MCSymbol *Label = CFI.getLabel())
 756       MachineOperand::printSymbol(OS, *Label);
 757     break;
 758   default:
 759     // TODO: Print the other CFI Operations.
 760     OS << "<unserializable cfi directive>";
 761     break;
 762   }
 763 }
 764
 765 void MachineOperand::print(raw_ostream &OS, const TargetRegisterInfo *TRI,
 766                            const TargetIntrinsicInfo *IntrinsicInfo) const {
 767   print(OS, LLT{}, TRI, IntrinsicInfo);
 768 }
 769
 770 void MachineOperand::print(raw_ostream &OS, LLT TypeToPrint,
 771                            const TargetRegisterInfo *TRI,
 772                            const TargetIntrinsicInfo *IntrinsicInfo) const {
 773   tryToGetTargetInfo(*this, TRI, IntrinsicInfo);
 774   ModuleSlotTracker DummyMST(nullptr);
 775   print(OS, DummyMST, TypeToPrint, std::nullopt, /*PrintDef=*/false,
 776         /*IsStandalone=*/true,
 777         /*ShouldPrintRegisterTies=*/true,
 778         /*TiedOperandIdx=*/0, TRI, IntrinsicInfo);
 779 }
 780
 781 void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
 782                            LLT TypeToPrint, std::optional<unsigned> OpIdx,
 783                            bool PrintDef, bool IsStandalone,
 784                            bool ShouldPrintRegisterTies,
 785                            unsigned TiedOperandIdx,
 786                            const TargetRegisterInfo *TRI,
 787                            const TargetIntrinsicInfo *IntrinsicInfo) const {
 788   printTargetFlags(OS, *this);
 789   switch (getType()) {
 790   case MachineOperand::MO_Register: {
 791     Register Reg = getReg();
 792     if (isImplicit())
 793       OS << (isDef() ? "implicit-def " : "implicit ");
 794     else if (PrintDef && isDef())
 795       // Print the 'def' flag only when the operand is defined after '='.
 796       OS << "def ";
 797     if (isInternalRead())
 798       OS << "internal ";
 799     if (isDead())
 800       OS << "dead ";
 801     if (isKill())
 802       OS << "killed ";
 803     if (isUndef())
 804       OS << "undef ";
 805     if (isEarlyClobber())
 806       OS << "early-clobber ";
 807     if (getReg().isPhysical() && isRenamable())
 808       OS << "renamable ";
 809     // isDebug() is exactly true for register operands of a DBG_VALUE. So we
 810     // simply infer it when parsing and do not need to print it.
 811
 812     const MachineRegisterInfo *MRI = nullptr;
 813     if (Reg.isVirtual()) {
 814       if (const MachineFunction *MF = getMFIfAvailable(*this)) {
 815         MRI = &MF->getRegInfo();
 816       }
 817     }
 818
 819     OS << printReg(Reg, TRI, 0, MRI);
 820     // Print the sub register.
 821     if (unsigned SubReg = getSubReg()) {
 822       if (TRI)
 823         OS << '.' << TRI->getSubRegIndexName(SubReg);
 824       else
 825         OS << ".subreg" << SubReg;
 826     }
 827     // Print the register class / bank.
 828     if (Reg.isVirtual()) {
 829       if (const MachineFunction *MF = getMFIfAvailable(*this)) {
 830         const MachineRegisterInfo &MRI = MF->getRegInfo();
 831         if (IsStandalone || !PrintDef || MRI.def_empty(Reg)) {
 832           OS << ':';
 833           OS << printRegClassOrBank(Reg, MRI, TRI);
 834         }
 835       }
 836     }
 837     // Print ties.
 838     if (ShouldPrintRegisterTies && isTied() && !isDef())
 839       OS << "(tied-def " << TiedOperandIdx << ")";
 840     // Print types.
 841     if (TypeToPrint.isValid())
 842       OS << '(' << TypeToPrint << ')';
 843     break;
 844   }
 845   case MachineOperand::MO_Immediate: {
 846     const MIRFormatter *Formatter = nullptr;
 847     if (const MachineFunction *MF = getMFIfAvailable(*this)) {
 848       const auto *TII = MF->getSubtarget().getInstrInfo();
 849       assert(TII && "expected instruction info");
 850       Formatter = TII->getMIRFormatter();
 851     }
 852     if (Formatter)
 853       Formatter->printImm(OS, *getParent(), OpIdx, getImm());
 854     else
 855       OS << getImm();
 856     break;
 857   }
 858   case MachineOperand::MO_CImmediate:
 859     getCImm()->printAsOperand(OS, /*PrintType=*/true, MST);
 860     break;
 861   case MachineOperand::MO_FPImmediate:
 862     getFPImm()->printAsOperand(OS, /*PrintType=*/true, MST);
 863     break;
 864   case MachineOperand::MO_MachineBasicBlock:
 865     OS << printMBBReference(*getMBB());
 866     break;
 867   case MachineOperand::MO_FrameIndex: {
 868     int FrameIndex = getIndex();
 869     bool IsFixed = false;
 870     const MachineFrameInfo *MFI = nullptr;
 871     if (const MachineFunction *MF = getMFIfAvailable(*this))
 872       MFI = &MF->getFrameInfo();
 873     printFrameIndex(OS, FrameIndex, IsFixed, MFI);
 874     break;
 875   }
 876   case MachineOperand::MO_ConstantPoolIndex:
 877     OS << "%const." << getIndex();
 878     printOperandOffset(OS, getOffset());
 879     break;
 880   case MachineOperand::MO_TargetIndex: {
 881     OS << "target-index(";
 882     const char *Name = "<unknown>";
 883     if (const MachineFunction *MF = getMFIfAvailable(*this))
 884       if (const auto *TargetIndexName = ::getTargetIndexName(*MF, getIndex()))
 885         Name = TargetIndexName;
 886     OS << Name << ')';
 887     printOperandOffset(OS, getOffset());
 888     break;
 889   }
 890   case MachineOperand::MO_JumpTableIndex:
 891     OS << printJumpTableEntryReference(getIndex());
 892     break;
 893   case MachineOperand::MO_GlobalAddress:
 894     getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
 895     printOperandOffset(OS, getOffset());
 896     break;
 897   case MachineOperand::MO_ExternalSymbol: {
 898     StringRef Name = getSymbolName();
 899     OS << '&';
 900     if (Name.empty()) {
 901       OS << "\"\"";
 902     } else {
 903       printLLVMNameWithoutPrefix(OS, Name);
 904     }
 905     printOperandOffset(OS, getOffset());
 906     break;
 907   }
 908   case MachineOperand::MO_BlockAddress: {
 909     OS << "blockaddress(";
 910     getBlockAddress()->getFunction()->printAsOperand(OS, /*PrintType=*/false,
 911                                                      MST);
 912     OS << ", ";
 913     printIRBlockReference(OS, *getBlockAddress()->getBasicBlock(), MST);
 914     OS << ')';
 915     MachineOperand::printOperandOffset(OS, getOffset());
 916     break;
 917   }
 918   case MachineOperand::MO_RegisterMask: {
 919     OS << "<regmask";
 920     if (TRI) {
 921       unsigned NumRegsInMask = 0;
 922       unsigned NumRegsEmitted = 0;
 923       for (unsigned i = 0; i < TRI->getNumRegs(); ++i) {
 924         unsigned MaskWord = i / 32;
 925         unsigned MaskBit = i % 32;
 926         if (getRegMask()[MaskWord] & (1 << MaskBit)) {
 927           if (PrintRegMaskNumRegs < 0 ||
 928               NumRegsEmitted <= static_cast<unsigned>(PrintRegMaskNumRegs)) {
 929             OS << " " << printReg(i, TRI);
 930             NumRegsEmitted++;
 931           }
 932           NumRegsInMask++;
 933         }
 934       }
 935       if (NumRegsEmitted != NumRegsInMask)
 936         OS << " and " << (NumRegsInMask - NumRegsEmitted) << " more...";
 937     } else {
 938       OS << " ...";
 939     }
 940     OS << ">";
 941     break;
 942   }
 943   case MachineOperand::MO_RegisterLiveOut: {
 944     const uint32_t *RegMask = getRegLiveOut();
 945     OS << "liveout(";
 946     if (!TRI) {
 947       OS << "<unknown>";
 948     } else {
 949       bool IsCommaNeeded = false;
 950       for (unsigned Reg = 0, E = TRI->getNumRegs(); Reg < E; ++Reg) {
 951         if (RegMask[Reg / 32] & (1U << (Reg % 32))) {
 952           if (IsCommaNeeded)
 953             OS << ", ";
 954           OS << printReg(Reg, TRI);
 955           IsCommaNeeded = true;
 956         }
 957       }
 958     }
 959     OS << ")";
 960     break;
 961   }
 962   case MachineOperand::MO_Metadata:
 963     getMetadata()->printAsOperand(OS, MST);
 964     break;
 965   case MachineOperand::MO_MCSymbol:
 966     printSymbol(OS, *getMCSymbol());
 967     break;
 968   case MachineOperand::MO_DbgInstrRef: {
 969     OS << "dbg-instr-ref(" << getInstrRefInstrIndex() << ", "
 970        << getInstrRefOpIndex() << ')';
 971     break;
 972   }
 973   case MachineOperand::MO_CFIIndex: {
 974     if (const MachineFunction *MF = getMFIfAvailable(*this))
 975       printCFI(OS, MF->getFrameInstructions()[getCFIIndex()], TRI);
 976     else
 977       OS << "<cfi directive>";
 978     break;
 979   }
 980   case MachineOperand::MO_IntrinsicID: {
 981     Intrinsic::ID ID = getIntrinsicID();
 982     if (ID < Intrinsic::num_intrinsics)
 983       OS << "intrinsic(@" << Intrinsic::getBaseName(ID) << ')';
 984     else if (IntrinsicInfo)
 985       OS << "intrinsic(@" << IntrinsicInfo->getName(ID) << ')';
 986     else
 987       OS << "intrinsic(" << ID << ')';
 988     break;
 989   }
 990   case MachineOperand::MO_Predicate: {
 991     auto Pred = static_cast<CmpInst::Predicate>(getPredicate());
 992     OS << (CmpInst::isIntPredicate(Pred) ? "int" : "float") << "pred("
 993        << Pred << ')';
 994     break;
 995   }
 996   case MachineOperand::MO_ShuffleMask:
 997     OS << "shufflemask(";
 998     ArrayRef<int> Mask = getShuffleMask();
 999     StringRef Separator;
1000     for (int Elt : Mask) {
1001       if (Elt == -1)
1002         OS << Separator << "undef";
1003       else
1004         OS << Separator << Elt;
1005       Separator = ", ";
1006     }
1007
1008     OS << ')';
1009     break;
1010   }
1011 }
1012
1013 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1014 LLVM_DUMP_METHOD void MachineOperand::dump() const { dbgs() << *this << '\n'; }
1015 #endif
1016
1017 //===----------------------------------------------------------------------===//
1018 // MachineMemOperand Implementation
1019 //===----------------------------------------------------------------------===//
1020
1021 /// getAddrSpace - Return the LLVM IR address space number that this pointer
1022 /// points into.
1023 unsigned MachinePointerInfo::getAddrSpace() const { return AddrSpace; }
1024
1025 /// isDereferenceable - Return true if V is always dereferenceable for
1026 /// Offset + Size byte.
1027 bool MachinePointerInfo::isDereferenceable(unsigned Size, LLVMContext &C,
1028                                            const DataLayout &DL) const {
1029   if (!isa<const Value *>(V))
1030     return false;
1031
1032   const Value *BasePtr = cast<const Value *>(V);
1033   if (BasePtr == nullptr)
1034     return false;
1035
1036   return isDereferenceableAndAlignedPointer(
1037       BasePtr, Align(1), APInt(DL.getPointerSizeInBits(), Offset + Size), DL);
1038 }
1039
1040 /// getConstantPool - Return a MachinePointerInfo record that refers to the
1041 /// constant pool.
1042 MachinePointerInfo MachinePointerInfo::getConstantPool(MachineFunction &MF) {
1043   return MachinePointerInfo(MF.getPSVManager().getConstantPool());
1044 }
1045
1046 /// getFixedStack - Return a MachinePointerInfo record that refers to the
1047 /// the specified FrameIndex.
1048 MachinePointerInfo MachinePointerInfo::getFixedStack(MachineFunction &MF,
1049                                                      int FI, int64_t Offset) {
1050   return MachinePointerInfo(MF.getPSVManager().getFixedStack(FI), Offset);
1051 }
1052
1053 MachinePointerInfo MachinePointerInfo::getJumpTable(MachineFunction &MF) {
1054   return MachinePointerInfo(MF.getPSVManager().getJumpTable());
1055 }
1056
1057 MachinePointerInfo MachinePointerInfo::getGOT(MachineFunction &MF) {
1058   return MachinePointerInfo(MF.getPSVManager().getGOT());
1059 }
1060
1061 MachinePointerInfo MachinePointerInfo::getStack(MachineFunction &MF,
1062                                                 int64_t Offset, uint8_t ID) {
1063   return MachinePointerInfo(MF.getPSVManager().getStack(), Offset, ID);
1064 }
1065
1066 MachinePointerInfo MachinePointerInfo::getUnknownStack(MachineFunction &MF) {
1067   return MachinePointerInfo(MF.getDataLayout().getAllocaAddrSpace());
1068 }
1069
1070 MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, Flags f,
1071                                      LLT type, Align a, const AAMDNodes &AAInfo,
1072                                      const MDNode *Ranges, SyncScope::ID SSID,
1073                                      AtomicOrdering Ordering,
1074                                      AtomicOrdering FailureOrdering)
1075     : PtrInfo(ptrinfo), MemoryType(type), FlagVals(f), BaseAlign(a),
1076       AAInfo(AAInfo), Ranges(Ranges) {
1077   assert((PtrInfo.V.isNull() || isa<const PseudoSourceValue *>(PtrInfo.V) ||
1078           isa<PointerType>(cast<const Value *>(PtrInfo.V)->getType())) &&
1079          "invalid pointer value");
1080   assert((isLoad() || isStore()) && "Not a load/store!");
1081
1082   AtomicInfo.SSID = static_cast<unsigned>(SSID);
1083   assert(getSyncScopeID() == SSID && "Value truncated");
1084   AtomicInfo.Ordering = static_cast<unsigned>(Ordering);
1085   assert(getSuccessOrdering() == Ordering && "Value truncated");
1086   AtomicInfo.FailureOrdering = static_cast<unsigned>(FailureOrdering);
1087   assert(getFailureOrdering() == FailureOrdering && "Value truncated");
1088 }
1089
1090 MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, Flags f,
1091                                      uint64_t s, Align a,
1092                                      const AAMDNodes &AAInfo,
1093                                      const MDNode *Ranges, SyncScope::ID SSID,
1094                                      AtomicOrdering Ordering,
1095                                      AtomicOrdering FailureOrdering)
1096     : MachineMemOperand(ptrinfo, f,
1097                         s == ~UINT64_C(0) ? LLT() : LLT::scalar(8 * s), a,
1098                         AAInfo, Ranges, SSID, Ordering, FailureOrdering) {}
1099
1100 void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
1101   // The Value and Offset may differ due to CSE. But the flags and size
1102   // should be the same.
1103   assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
1104   assert((MMO->getSize() == ~UINT64_C(0) || getSize() == ~UINT64_C(0) ||
1105           MMO->getSize() == getSize()) &&
1106          "Size mismatch!");
1107
1108   if (MMO->getBaseAlign() >= getBaseAlign()) {
1109     // Update the alignment value.
1110     BaseAlign = MMO->getBaseAlign();
1111     // Also update the base and offset, because the new alignment may
1112     // not be applicable with the old ones.
1113     PtrInfo = MMO->PtrInfo;
1114   }
1115 }
1116
1117 /// getAlign - Return the minimum known alignment in bytes of the
1118 /// actual memory reference.
1119 Align MachineMemOperand::getAlign() const {
1120   return commonAlignment(getBaseAlign(), getOffset());
1121 }
1122
1123 void MachineMemOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
1124                               SmallVectorImpl<StringRef> &SSNs,
1125                               const LLVMContext &Context,
1126                               const MachineFrameInfo *MFI,
1127                               const TargetInstrInfo *TII) const {
1128   OS << '(';
1129   if (isVolatile())
1130     OS << "volatile ";
1131   if (isNonTemporal())
1132     OS << "non-temporal ";
1133   if (isDereferenceable())
1134     OS << "dereferenceable ";
1135   if (isInvariant())
1136     OS << "invariant ";
1137   if (TII) {
1138     if (getFlags() & MachineMemOperand::MOTargetFlag1)
1139       OS << '"' << getTargetMMOFlagName(*TII, MachineMemOperand::MOTargetFlag1)
1140          << "\" ";
1141     if (getFlags() & MachineMemOperand::MOTargetFlag2)
1142       OS << '"' << getTargetMMOFlagName(*TII, MachineMemOperand::MOTargetFlag2)
1143          << "\" ";
1144     if (getFlags() & MachineMemOperand::MOTargetFlag3)
1145       OS << '"' << getTargetMMOFlagName(*TII, MachineMemOperand::MOTargetFlag3)
1146          << "\" ";
1147   } else {
1148     if (getFlags() & MachineMemOperand::MOTargetFlag1)
1149       OS << "\"MOTargetFlag1\" ";
1150     if (getFlags() & MachineMemOperand::MOTargetFlag2)
1151       OS << "\"MOTargetFlag2\" ";
1152     if (getFlags() & MachineMemOperand::MOTargetFlag3)
1153       OS << "\"MOTargetFlag3\" ";
1154   }
1155
1156   assert((isLoad() || isStore()) &&
1157          "machine memory operand must be a load or store (or both)");
1158   if (isLoad())
1159     OS << "load ";
1160   if (isStore())
1161     OS << "store ";
1162
1163   printSyncScope(OS, Context, getSyncScopeID(), SSNs);
1164
1165   if (getSuccessOrdering() != AtomicOrdering::NotAtomic)
1166     OS << toIRString(getSuccessOrdering()) << ' ';
1167   if (getFailureOrdering() != AtomicOrdering::NotAtomic)
1168     OS << toIRString(getFailureOrdering()) << ' ';
1169
1170   if (getMemoryType().isValid())
1171     OS << '(' << getMemoryType() << ')';
1172   else
1173     OS << "unknown-size";
1174
1175   if (const Value *Val = getValue()) {
1176     OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into ");
1177     MIRFormatter::printIRValue(OS, *Val, MST);
1178   } else if (const PseudoSourceValue *PVal = getPseudoValue()) {
1179     OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into ");
1180     assert(PVal && "Expected a pseudo source value");
1181     switch (PVal->kind()) {
1182     case PseudoSourceValue::Stack:
1183       OS << "stack";
1184       break;
1185     case PseudoSourceValue::GOT:
1186       OS << "got";
1187       break;
1188     case PseudoSourceValue::JumpTable:
1189       OS << "jump-table";
1190       break;
1191     case PseudoSourceValue::ConstantPool:
1192       OS << "constant-pool";
1193       break;
1194     case PseudoSourceValue::FixedStack: {
1195       int FrameIndex = cast<FixedStackPseudoSourceValue>(PVal)->getFrameIndex();
1196       bool IsFixed = true;
1197       printFrameIndex(OS, FrameIndex, IsFixed, MFI);
1198       break;
1199     }
1200     case PseudoSourceValue::GlobalValueCallEntry:
1201       OS << "call-entry ";
1202       cast<GlobalValuePseudoSourceValue>(PVal)->getValue()->printAsOperand(
1203           OS, /*PrintType=*/false, MST);
1204       break;
1205     case PseudoSourceValue::ExternalSymbolCallEntry:
1206       OS << "call-entry &";
1207       printLLVMNameWithoutPrefix(
1208           OS, cast<ExternalSymbolPseudoSourceValue>(PVal)->getSymbol());
1209       break;
1210     default: {
1211       const MIRFormatter *Formatter = TII->getMIRFormatter();
1212       // FIXME: This is not necessarily the correct MIR serialization format for
1213       // a custom pseudo source value, but at least it allows
1214       // MIR printing to work on a target with custom pseudo source
1215       // values.
1216       OS << "custom \"";
1217       Formatter->printCustomPseudoSourceValue(OS, MST, *PVal);
1218       OS << '\"';
1219       break;
1220     }
1221     }
1222   } else if (getOpaqueValue() == nullptr && getOffset() != 0) {
1223     OS << ((isLoad() && isStore()) ? " on "
1224            : isLoad()              ? " from "
1225                                    : " into ")
1226        << "unknown-address";
1227   }
1228   MachineOperand::printOperandOffset(OS, getOffset());
1229   if (getSize() > 0 && getAlign() != getSize())
1230     OS << ", align " << getAlign().value();
1231   if (getAlign() != getBaseAlign())
1232     OS << ", basealign " << getBaseAlign().value();
1233   auto AAInfo = getAAInfo();
1234   if (AAInfo.TBAA) {
1235     OS << ", !tbaa ";
1236     AAInfo.TBAA->printAsOperand(OS, MST);
1237   }
1238   if (AAInfo.Scope) {
1239     OS << ", !alias.scope ";
1240     AAInfo.Scope->printAsOperand(OS, MST);
1241   }
1242   if (AAInfo.NoAlias) {
1243     OS << ", !noalias ";
1244     AAInfo.NoAlias->printAsOperand(OS, MST);
1245   }
1246   if (getRanges()) {
1247     OS << ", !range ";
1248     getRanges()->printAsOperand(OS, MST);
1249   }
1250   // FIXME: Implement addrspace printing/parsing in MIR.
1251   // For now, print this even though parsing it is not available in MIR.
1252   if (unsigned AS = getAddrSpace())
1253     OS << ", addrspace " << AS;
1254
1255   OS << ')';
1256 }