llvm/lib/Target/AVR/AVRTargetMachine.cpp

   1 //===-- AVRTargetMachine.cpp - Define TargetMachine for AVR ---------------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file defines the AVR specific subclass of TargetMachine.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #include "AVRTargetMachine.h"
  14
  15 #include "llvm/CodeGen/Passes.h"
  16 #include "llvm/CodeGen/TargetPassConfig.h"
  17 #include "llvm/IR/Module.h"
  18 #include "llvm/MC/TargetRegistry.h"
  19
  20 #include "AVR.h"
  21 #include "AVRMachineFunctionInfo.h"
  22 #include "AVRTargetObjectFile.h"
  23 #include "MCTargetDesc/AVRMCTargetDesc.h"
  24 #include "TargetInfo/AVRTargetInfo.h"
  25
  26 #include <optional>
  27
  28 namespace llvm {
  29
  30 static const char *AVRDataLayout =
  31     "e-P1-p:16:8-i8:8-i16:8-i32:8-i64:8-f32:8-f64:8-n8-a:8";
  32
  33 /// Processes a CPU name.
  34 static StringRef getCPU(StringRef CPU) {
  35   if (CPU.empty() || CPU == "generic") {
  36     return "avr2";
  37   }
  38
  39   return CPU;
  40 }
  41
  42 static Reloc::Model getEffectiveRelocModel(std::optional<Reloc::Model> RM) {
  43   return RM.value_or(Reloc::Static);
  44 }
  45
  46 AVRTargetMachine::AVRTargetMachine(const Target &T, const Triple &TT,
  47                                    StringRef CPU, StringRef FS,
  48                                    const TargetOptions &Options,
  49                                    std::optional<Reloc::Model> RM,
  50                                    std::optional<CodeModel::Model> CM,
  51                                    CodeGenOptLevel OL, bool JIT)
  52     : LLVMTargetMachine(T, AVRDataLayout, TT, getCPU(CPU), FS, Options,
  53                         getEffectiveRelocModel(RM),
  54                         getEffectiveCodeModel(CM, CodeModel::Small), OL),
  55       SubTarget(TT, std::string(getCPU(CPU)), std::string(FS), *this) {
  56   this->TLOF = std::make_unique<AVRTargetObjectFile>();
  57   initAsmInfo();
  58 }
  59
  60 namespace {
  61 /// AVR Code Generator Pass Configuration Options.
  62 class AVRPassConfig : public TargetPassConfig {
  63 public:
  64   AVRPassConfig(AVRTargetMachine &TM, PassManagerBase &PM)
  65       : TargetPassConfig(TM, PM) {}
  66
  67   AVRTargetMachine &getAVRTargetMachine() const {
  68     return getTM<AVRTargetMachine>();
  69   }
  70
  71   void addIRPasses() override;
  72   bool addInstSelector() override;
  73   void addPreSched2() override;
  74   void addPreEmitPass() override;
  75 };
  76 } // namespace
  77
  78 TargetPassConfig *AVRTargetMachine::createPassConfig(PassManagerBase &PM) {
  79   return new AVRPassConfig(*this, PM);
  80 }
  81
  82 void AVRPassConfig::addIRPasses() {
  83   // Expand instructions like
  84   //   %result = shl i32 %n, %amount
  85   // to a loop so that library calls are avoided.
  86   addPass(createAVRShiftExpandPass());
  87
  88   TargetPassConfig::addIRPasses();
  89 }
  90
  91 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAVRTarget() {
  92   // Register the target.
  93   RegisterTargetMachine<AVRTargetMachine> X(getTheAVRTarget());
  94
  95   auto &PR = *PassRegistry::getPassRegistry();
  96   initializeAVRExpandPseudoPass(PR);
  97   initializeAVRShiftExpandPass(PR);
  98   initializeAVRDAGToDAGISelPass(PR);
  99 }
 100
 101 const AVRSubtarget *AVRTargetMachine::getSubtargetImpl() const {
 102   return &SubTarget;
 103 }
 104
 105 const AVRSubtarget *AVRTargetMachine::getSubtargetImpl(const Function &) const {
 106   return &SubTarget;
 107 }
 108
 109 MachineFunctionInfo *AVRTargetMachine::createMachineFunctionInfo(
 110     BumpPtrAllocator &Allocator, const Function &F,
 111     const TargetSubtargetInfo *STI) const {
 112   return AVRMachineFunctionInfo::create<AVRMachineFunctionInfo>(Allocator, F,
 113                                                                 STI);
 114 }
 115
 116 //===----------------------------------------------------------------------===//
 117 // Pass Pipeline Configuration
 118 //===----------------------------------------------------------------------===//
 119
 120 bool AVRPassConfig::addInstSelector() {
 121   // Install an instruction selector.
 122   addPass(createAVRISelDag(getAVRTargetMachine(), getOptLevel()));
 123   // Create the frame analyzer pass used by the PEI pass.
 124   addPass(createAVRFrameAnalyzerPass());
 125
 126   return false;
 127 }
 128
 129 void AVRPassConfig::addPreSched2() {
 130   addPass(createAVRExpandPseudoPass());
 131 }
 132
 133 void AVRPassConfig::addPreEmitPass() {
 134   // Must run branch selection immediately preceding the asm printer.
 135   addPass(&BranchRelaxationPassID);
 136 }
 137
 138 } // end of namespace llvm