| blob | 1dfd977186b0e7346ded214c72f5cc501112cb8c |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -enable-misched=false | FileCheck %s
4 define <8 x i8> @sqshl8b(ptr %A, ptr %B) nounwind {
5 ; CHECK-LABEL: sqshl8b:
6 ; CHECK: // %bb.0:
7 ; CHECK-NEXT: ldr d0, [x0]
8 ; CHECK-NEXT: ldr d1, [x1]
9 ; CHECK-NEXT: sqshl.8b v0, v0, v1
10 ; CHECK-NEXT: ret
11 %tmp1 = load <8 x i8>, ptr %A
12 %tmp2 = load <8 x i8>, ptr %B
13 %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqshl.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
14 ret <8 x i8> %tmp3
15 }
17 define <4 x i16> @sqshl4h(ptr %A, ptr %B) nounwind {
18 ; CHECK-LABEL: sqshl4h:
19 ; CHECK: // %bb.0:
20 ; CHECK-NEXT: ldr d0, [x0]
21 ; CHECK-NEXT: ldr d1, [x1]
22 ; CHECK-NEXT: sqshl.4h v0, v0, v1
23 ; CHECK-NEXT: ret
24 %tmp1 = load <4 x i16>, ptr %A
25 %tmp2 = load <4 x i16>, ptr %B
26 %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqshl.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
27 ret <4 x i16> %tmp3
28 }
30 define <2 x i32> @sqshl2s(ptr %A, ptr %B) nounwind {
31 ; CHECK-LABEL: sqshl2s:
32 ; CHECK: // %bb.0:
33 ; CHECK-NEXT: ldr d0, [x0]
34 ; CHECK-NEXT: ldr d1, [x1]
35 ; CHECK-NEXT: sqshl.2s v0, v0, v1
36 ; CHECK-NEXT: ret
37 %tmp1 = load <2 x i32>, ptr %A
38 %tmp2 = load <2 x i32>, ptr %B
39 %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqshl.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
40 ret <2 x i32> %tmp3
41 }
43 define <1 x i64> @sqshl1d(ptr %A, ptr %B) nounwind {
44 ; CHECK-LABEL: sqshl1d:
45 ; CHECK: // %bb.0:
46 ; CHECK-NEXT: ldr d0, [x0]
47 ; CHECK-NEXT: ldr d1, [x1]
48 ; CHECK-NEXT: sqshl d0, d0, d1
49 ; CHECK-NEXT: ret
50 %tmp1 = load <1 x i64>, ptr %A
51 %tmp2 = load <1 x i64>, ptr %B
52 %tmp3 = call <1 x i64> @llvm.aarch64.neon.sqshl.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
53 ret <1 x i64> %tmp3
54 }
56 define <1 x i64> @sqshl1d_constant(ptr %A) nounwind {
57 ; CHECK-LABEL: sqshl1d_constant:
58 ; CHECK: // %bb.0:
59 ; CHECK-NEXT: ldr d0, [x0]
60 ; CHECK-NEXT: sqshl d0, d0, #1
61 ; CHECK-NEXT: ret
62 %tmp1 = load <1 x i64>, ptr %A
63 %tmp3 = call <1 x i64> @llvm.aarch64.neon.sqshl.v1i64(<1 x i64> %tmp1, <1 x i64> <i64 1>)
64 ret <1 x i64> %tmp3
65 }
67 define i64 @sqshl_scalar(ptr %A, ptr %B) nounwind {
68 ; CHECK-LABEL: sqshl_scalar:
69 ; CHECK: // %bb.0:
70 ; CHECK-NEXT: ldr x8, [x0]
71 ; CHECK-NEXT: ldr x9, [x1]
72 ; CHECK-NEXT: fmov d0, x8
73 ; CHECK-NEXT: fmov d1, x9
74 ; CHECK-NEXT: sqshl d0, d0, d1
75 ; CHECK-NEXT: fmov x0, d0
76 ; CHECK-NEXT: ret
77 %tmp1 = load i64, ptr %A
78 %tmp2 = load i64, ptr %B
79 %tmp3 = call i64 @llvm.aarch64.neon.sqshl.i64(i64 %tmp1, i64 %tmp2)
80 ret i64 %tmp3
81 }
83 define i64 @sqshl_scalar_constant(ptr %A) nounwind {
84 ; CHECK-LABEL: sqshl_scalar_constant:
85 ; CHECK: // %bb.0:
86 ; CHECK-NEXT: ldr d0, [x0]
87 ; CHECK-NEXT: sqshl d0, d0, #1
88 ; CHECK-NEXT: fmov x0, d0
89 ; CHECK-NEXT: ret
90 %tmp1 = load i64, ptr %A
91 %tmp3 = call i64 @llvm.aarch64.neon.sqshl.i64(i64 %tmp1, i64 1)
92 ret i64 %tmp3
93 }
95 define <8 x i8> @uqshl8b(ptr %A, ptr %B) nounwind {
96 ; CHECK-LABEL: uqshl8b:
97 ; CHECK: // %bb.0:
98 ; CHECK-NEXT: ldr d0, [x0]
99 ; CHECK-NEXT: ldr d1, [x1]
100 ; CHECK-NEXT: uqshl.8b v0, v0, v1
101 ; CHECK-NEXT: ret
102 %tmp1 = load <8 x i8>, ptr %A
103 %tmp2 = load <8 x i8>, ptr %B
104 %tmp3 = call <8 x i8> @llvm.aarch64.neon.uqshl.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
105 ret <8 x i8> %tmp3
106 }
108 define <4 x i16> @uqshl4h(ptr %A, ptr %B) nounwind {
109 ; CHECK-LABEL: uqshl4h:
110 ; CHECK: // %bb.0:
111 ; CHECK-NEXT: ldr d0, [x0]
112 ; CHECK-NEXT: ldr d1, [x1]
113 ; CHECK-NEXT: uqshl.4h v0, v0, v1
114 ; CHECK-NEXT: ret
115 %tmp1 = load <4 x i16>, ptr %A
116 %tmp2 = load <4 x i16>, ptr %B
117 %tmp3 = call <4 x i16> @llvm.aarch64.neon.uqshl.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
118 ret <4 x i16> %tmp3
119 }
121 define <2 x i32> @uqshl2s(ptr %A, ptr %B) nounwind {
122 ; CHECK-LABEL: uqshl2s:
123 ; CHECK: // %bb.0:
124 ; CHECK-NEXT: ldr d0, [x0]
125 ; CHECK-NEXT: ldr d1, [x1]
126 ; CHECK-NEXT: uqshl.2s v0, v0, v1
127 ; CHECK-NEXT: ret
128 %tmp1 = load <2 x i32>, ptr %A
129 %tmp2 = load <2 x i32>, ptr %B
130 %tmp3 = call <2 x i32> @llvm.aarch64.neon.uqshl.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
131 ret <2 x i32> %tmp3
132 }
134 define <16 x i8> @sqshl16b(ptr %A, ptr %B) nounwind {
135 ; CHECK-LABEL: sqshl16b:
136 ; CHECK: // %bb.0:
137 ; CHECK-NEXT: ldr q0, [x0]
138 ; CHECK-NEXT: ldr q1, [x1]
139 ; CHECK-NEXT: sqshl.16b v0, v0, v1
140 ; CHECK-NEXT: ret
141 %tmp1 = load <16 x i8>, ptr %A
142 %tmp2 = load <16 x i8>, ptr %B
143 %tmp3 = call <16 x i8> @llvm.aarch64.neon.sqshl.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
144 ret <16 x i8> %tmp3
145 }
147 define <8 x i16> @sqshl8h(ptr %A, ptr %B) nounwind {
148 ; CHECK-LABEL: sqshl8h:
149 ; CHECK: // %bb.0:
150 ; CHECK-NEXT: ldr q0, [x0]
151 ; CHECK-NEXT: ldr q1, [x1]
152 ; CHECK-NEXT: sqshl.8h v0, v0, v1
153 ; CHECK-NEXT: ret
154 %tmp1 = load <8 x i16>, ptr %A
155 %tmp2 = load <8 x i16>, ptr %B
156 %tmp3 = call <8 x i16> @llvm.aarch64.neon.sqshl.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
157 ret <8 x i16> %tmp3
158 }
160 define <4 x i32> @sqshl4s(ptr %A, ptr %B) nounwind {
161 ; CHECK-LABEL: sqshl4s:
162 ; CHECK: // %bb.0:
163 ; CHECK-NEXT: ldr q0, [x0]
164 ; CHECK-NEXT: ldr q1, [x1]
165 ; CHECK-NEXT: sqshl.4s v0, v0, v1
166 ; CHECK-NEXT: ret
167 %tmp1 = load <4 x i32>, ptr %A
168 %tmp2 = load <4 x i32>, ptr %B
169 %tmp3 = call <4 x i32> @llvm.aarch64.neon.sqshl.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
170 ret <4 x i32> %tmp3
171 }
173 define <2 x i64> @sqshl2d(ptr %A, ptr %B) nounwind {
174 ; CHECK-LABEL: sqshl2d:
175 ; CHECK: // %bb.0:
176 ; CHECK-NEXT: ldr q0, [x0]
177 ; CHECK-NEXT: ldr q1, [x1]
178 ; CHECK-NEXT: sqshl.2d v0, v0, v1
179 ; CHECK-NEXT: ret
180 %tmp1 = load <2 x i64>, ptr %A
181 %tmp2 = load <2 x i64>, ptr %B
182 %tmp3 = call <2 x i64> @llvm.aarch64.neon.sqshl.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
183 ret <2 x i64> %tmp3
184 }
186 define <16 x i8> @uqshl16b(ptr %A, ptr %B) nounwind {
187 ; CHECK-LABEL: uqshl16b:
188 ; CHECK: // %bb.0:
189 ; CHECK-NEXT: ldr q0, [x0]
190 ; CHECK-NEXT: ldr q1, [x1]
191 ; CHECK-NEXT: uqshl.16b v0, v0, v1
192 ; CHECK-NEXT: ret
193 %tmp1 = load <16 x i8>, ptr %A
194 %tmp2 = load <16 x i8>, ptr %B
195 %tmp3 = call <16 x i8> @llvm.aarch64.neon.uqshl.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
196 ret <16 x i8> %tmp3
197 }
199 define <8 x i16> @uqshl8h(ptr %A, ptr %B) nounwind {
200 ; CHECK-LABEL: uqshl8h:
201 ; CHECK: // %bb.0:
202 ; CHECK-NEXT: ldr q0, [x0]
203 ; CHECK-NEXT: ldr q1, [x1]
204 ; CHECK-NEXT: uqshl.8h v0, v0, v1
205 ; CHECK-NEXT: ret
206 %tmp1 = load <8 x i16>, ptr %A
207 %tmp2 = load <8 x i16>, ptr %B
208 %tmp3 = call <8 x i16> @llvm.aarch64.neon.uqshl.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
209 ret <8 x i16> %tmp3
210 }
212 define <4 x i32> @uqshl4s(ptr %A, ptr %B) nounwind {
213 ; CHECK-LABEL: uqshl4s:
214 ; CHECK: // %bb.0:
215 ; CHECK-NEXT: ldr q0, [x0]
216 ; CHECK-NEXT: ldr q1, [x1]
217 ; CHECK-NEXT: uqshl.4s v0, v0, v1
218 ; CHECK-NEXT: ret
219 %tmp1 = load <4 x i32>, ptr %A
220 %tmp2 = load <4 x i32>, ptr %B
221 %tmp3 = call <4 x i32> @llvm.aarch64.neon.uqshl.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
222 ret <4 x i32> %tmp3
223 }
225 define <2 x i64> @uqshl2d(ptr %A, ptr %B) nounwind {
226 ; CHECK-LABEL: uqshl2d:
227 ; CHECK: // %bb.0:
228 ; CHECK-NEXT: ldr q0, [x0]
229 ; CHECK-NEXT: ldr q1, [x1]
230 ; CHECK-NEXT: uqshl.2d v0, v0, v1
231 ; CHECK-NEXT: ret
232 %tmp1 = load <2 x i64>, ptr %A
233 %tmp2 = load <2 x i64>, ptr %B
234 %tmp3 = call <2 x i64> @llvm.aarch64.neon.uqshl.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
235 ret <2 x i64> %tmp3
236 }
238 define <1 x i64> @uqshl1d(ptr %A, ptr %B) nounwind {
239 ; CHECK-LABEL: uqshl1d:
240 ; CHECK: // %bb.0:
241 ; CHECK-NEXT: ldr d0, [x0]
242 ; CHECK-NEXT: ldr d1, [x1]
243 ; CHECK-NEXT: uqshl d0, d0, d1
244 ; CHECK-NEXT: ret
245 %tmp1 = load <1 x i64>, ptr %A
246 %tmp2 = load <1 x i64>, ptr %B
247 %tmp3 = call <1 x i64> @llvm.aarch64.neon.uqshl.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
248 ret <1 x i64> %tmp3
249 }
251 define <1 x i64> @uqshl1d_constant(ptr %A) nounwind {
252 ; CHECK-LABEL: uqshl1d_constant:
253 ; CHECK: // %bb.0:
254 ; CHECK-NEXT: ldr d0, [x0]
255 ; CHECK-NEXT: uqshl d0, d0, #1
256 ; CHECK-NEXT: ret
257 %tmp1 = load <1 x i64>, ptr %A
258 %tmp3 = call <1 x i64> @llvm.aarch64.neon.uqshl.v1i64(<1 x i64> %tmp1, <1 x i64> <i64 1>)
259 ret <1 x i64> %tmp3
260 }
262 define i64 @uqshl_scalar(ptr %A, ptr %B) nounwind {
263 ; CHECK-LABEL: uqshl_scalar:
264 ; CHECK: // %bb.0:
265 ; CHECK-NEXT: ldr x8, [x0]
266 ; CHECK-NEXT: ldr x9, [x1]
267 ; CHECK-NEXT: fmov d0, x8
268 ; CHECK-NEXT: fmov d1, x9
269 ; CHECK-NEXT: uqshl d0, d0, d1
270 ; CHECK-NEXT: fmov x0, d0
271 ; CHECK-NEXT: ret
272 %tmp1 = load i64, ptr %A
273 %tmp2 = load i64, ptr %B
274 %tmp3 = call i64 @llvm.aarch64.neon.uqshl.i64(i64 %tmp1, i64 %tmp2)
275 ret i64 %tmp3
276 }
278 define i64 @uqshl_scalar_constant(ptr %A) nounwind {
279 ; CHECK-LABEL: uqshl_scalar_constant:
280 ; CHECK: // %bb.0:
281 ; CHECK-NEXT: ldr d0, [x0]
282 ; CHECK-NEXT: uqshl d0, d0, #1
283 ; CHECK-NEXT: fmov x0, d0
284 ; CHECK-NEXT: ret
285 %tmp1 = load i64, ptr %A
286 %tmp3 = call i64 @llvm.aarch64.neon.uqshl.i64(i64 %tmp1, i64 1)
287 ret i64 %tmp3
288 }
290 declare <8 x i8> @llvm.aarch64.neon.sqshl.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
291 declare <4 x i16> @llvm.aarch64.neon.sqshl.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
292 declare <2 x i32> @llvm.aarch64.neon.sqshl.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
293 declare <1 x i64> @llvm.aarch64.neon.sqshl.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
294 declare i64 @llvm.aarch64.neon.sqshl.i64(i64, i64) nounwind readnone
297 declare <8 x i8> @llvm.aarch64.neon.uqshl.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
298 declare <4 x i16> @llvm.aarch64.neon.uqshl.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
299 declare <2 x i32> @llvm.aarch64.neon.uqshl.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
300 declare <1 x i64> @llvm.aarch64.neon.uqshl.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
301 declare i64 @llvm.aarch64.neon.uqshl.i64(i64, i64) nounwind readnone
303 declare <16 x i8> @llvm.aarch64.neon.sqshl.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
304 declare <8 x i16> @llvm.aarch64.neon.sqshl.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
305 declare <4 x i32> @llvm.aarch64.neon.sqshl.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
306 declare <2 x i64> @llvm.aarch64.neon.sqshl.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
308 declare <16 x i8> @llvm.aarch64.neon.uqshl.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
309 declare <8 x i16> @llvm.aarch64.neon.uqshl.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
310 declare <4 x i32> @llvm.aarch64.neon.uqshl.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
311 declare <2 x i64> @llvm.aarch64.neon.uqshl.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
313 define <8 x i8> @srshl8b(ptr %A, ptr %B) nounwind {
314 ; CHECK-LABEL: srshl8b:
315 ; CHECK: // %bb.0:
316 ; CHECK-NEXT: ldr d0, [x0]
317 ; CHECK-NEXT: ldr d1, [x1]
318 ; CHECK-NEXT: srshl.8b v0, v0, v1
319 ; CHECK-NEXT: ret
320 %tmp1 = load <8 x i8>, ptr %A
321 %tmp2 = load <8 x i8>, ptr %B
322 %tmp3 = call <8 x i8> @llvm.aarch64.neon.srshl.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
323 ret <8 x i8> %tmp3
324 }
326 define <4 x i16> @srshl4h(ptr %A, ptr %B) nounwind {
327 ; CHECK-LABEL: srshl4h:
328 ; CHECK: // %bb.0:
329 ; CHECK-NEXT: ldr d0, [x0]
330 ; CHECK-NEXT: ldr d1, [x1]
331 ; CHECK-NEXT: srshl.4h v0, v0, v1
332 ; CHECK-NEXT: ret
333 %tmp1 = load <4 x i16>, ptr %A
334 %tmp2 = load <4 x i16>, ptr %B
335 %tmp3 = call <4 x i16> @llvm.aarch64.neon.srshl.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
336 ret <4 x i16> %tmp3
337 }
339 define <2 x i32> @srshl2s(ptr %A, ptr %B) nounwind {
340 ; CHECK-LABEL: srshl2s:
341 ; CHECK: // %bb.0:
342 ; CHECK-NEXT: ldr d0, [x0]
343 ; CHECK-NEXT: ldr d1, [x1]
344 ; CHECK-NEXT: srshl.2s v0, v0, v1
345 ; CHECK-NEXT: ret
346 %tmp1 = load <2 x i32>, ptr %A
347 %tmp2 = load <2 x i32>, ptr %B
348 %tmp3 = call <2 x i32> @llvm.aarch64.neon.srshl.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
349 ret <2 x i32> %tmp3
350 }
352 define <1 x i64> @srshl1d(ptr %A, ptr %B) nounwind {
353 ; CHECK-LABEL: srshl1d:
354 ; CHECK: // %bb.0:
355 ; CHECK-NEXT: ldr d0, [x0]
356 ; CHECK-NEXT: ldr d1, [x1]
357 ; CHECK-NEXT: srshl d0, d0, d1
358 ; CHECK-NEXT: ret
359 %tmp1 = load <1 x i64>, ptr %A
360 %tmp2 = load <1 x i64>, ptr %B
361 %tmp3 = call <1 x i64> @llvm.aarch64.neon.srshl.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
362 ret <1 x i64> %tmp3
363 }
365 define <1 x i64> @srshl1d_constant(ptr %A) nounwind {
366 ; CHECK-LABEL: srshl1d_constant:
367 ; CHECK: // %bb.0:
368 ; CHECK-NEXT: mov w8, #1 // =0x1
369 ; CHECK-NEXT: ldr d0, [x0]
370 ; CHECK-NEXT: fmov d1, x8
371 ; CHECK-NEXT: srshl d0, d0, d1
372 ; CHECK-NEXT: ret
373 %tmp1 = load <1 x i64>, ptr %A
374 %tmp3 = call <1 x i64> @llvm.aarch64.neon.srshl.v1i64(<1 x i64> %tmp1, <1 x i64> <i64 1>)
375 ret <1 x i64> %tmp3
376 }
378 define i64 @srshl_scalar(ptr %A, ptr %B) nounwind {
379 ; CHECK-LABEL: srshl_scalar:
380 ; CHECK: // %bb.0:
381 ; CHECK-NEXT: ldr x8, [x0]
382 ; CHECK-NEXT: ldr x9, [x1]
383 ; CHECK-NEXT: fmov d0, x8
384 ; CHECK-NEXT: fmov d1, x9
385 ; CHECK-NEXT: srshl d0, d0, d1
386 ; CHECK-NEXT: fmov x0, d0
387 ; CHECK-NEXT: ret
388 %tmp1 = load i64, ptr %A
389 %tmp2 = load i64, ptr %B
390 %tmp3 = call i64 @llvm.aarch64.neon.srshl.i64(i64 %tmp1, i64 %tmp2)
391 ret i64 %tmp3
392 }
394 define i64 @srshl_scalar_constant(ptr %A) nounwind {
395 ; CHECK-LABEL: srshl_scalar_constant:
396 ; CHECK: // %bb.0:
397 ; CHECK-NEXT: ldr x8, [x0]
398 ; CHECK-NEXT: mov w9, #1 // =0x1
399 ; CHECK-NEXT: fmov d1, x9
400 ; CHECK-NEXT: fmov d0, x8
401 ; CHECK-NEXT: srshl d0, d0, d1
402 ; CHECK-NEXT: fmov x0, d0
403 ; CHECK-NEXT: ret
404 %tmp1 = load i64, ptr %A
405 %tmp3 = call i64 @llvm.aarch64.neon.srshl.i64(i64 %tmp1, i64 1)
406 ret i64 %tmp3
407 }
409 define <8 x i8> @urshl8b(ptr %A, ptr %B) nounwind {
410 ; CHECK-LABEL: urshl8b:
411 ; CHECK: // %bb.0:
412 ; CHECK-NEXT: ldr d0, [x0]
413 ; CHECK-NEXT: ldr d1, [x1]
414 ; CHECK-NEXT: urshl.8b v0, v0, v1
415 ; CHECK-NEXT: ret
416 %tmp1 = load <8 x i8>, ptr %A
417 %tmp2 = load <8 x i8>, ptr %B
418 %tmp3 = call <8 x i8> @llvm.aarch64.neon.urshl.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
419 ret <8 x i8> %tmp3
420 }
422 define <4 x i16> @urshl4h(ptr %A, ptr %B) nounwind {
423 ; CHECK-LABEL: urshl4h:
424 ; CHECK: // %bb.0:
425 ; CHECK-NEXT: ldr d0, [x0]
426 ; CHECK-NEXT: ldr d1, [x1]
427 ; CHECK-NEXT: urshl.4h v0, v0, v1
428 ; CHECK-NEXT: ret
429 %tmp1 = load <4 x i16>, ptr %A
430 %tmp2 = load <4 x i16>, ptr %B
431 %tmp3 = call <4 x i16> @llvm.aarch64.neon.urshl.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
432 ret <4 x i16> %tmp3
433 }
435 define <2 x i32> @urshl2s(ptr %A, ptr %B) nounwind {
436 ; CHECK-LABEL: urshl2s:
437 ; CHECK: // %bb.0:
438 ; CHECK-NEXT: ldr d0, [x0]
439 ; CHECK-NEXT: ldr d1, [x1]
440 ; CHECK-NEXT: urshl.2s v0, v0, v1
441 ; CHECK-NEXT: ret
442 %tmp1 = load <2 x i32>, ptr %A
443 %tmp2 = load <2 x i32>, ptr %B
444 %tmp3 = call <2 x i32> @llvm.aarch64.neon.urshl.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
445 ret <2 x i32> %tmp3
446 }
448 define <1 x i64> @urshl1d(ptr %A, ptr %B) nounwind {
449 ; CHECK-LABEL: urshl1d:
450 ; CHECK: // %bb.0:
451 ; CHECK-NEXT: ldr d0, [x0]
452 ; CHECK-NEXT: ldr d1, [x1]
453 ; CHECK-NEXT: urshl d0, d0, d1
454 ; CHECK-NEXT: ret
455 %tmp1 = load <1 x i64>, ptr %A
456 %tmp2 = load <1 x i64>, ptr %B
457 %tmp3 = call <1 x i64> @llvm.aarch64.neon.urshl.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
458 ret <1 x i64> %tmp3
459 }
461 define <1 x i64> @urshl1d_constant(ptr %A) nounwind {
462 ; CHECK-LABEL: urshl1d_constant:
463 ; CHECK: // %bb.0:
464 ; CHECK-NEXT: mov w8, #1 // =0x1
465 ; CHECK-NEXT: ldr d0, [x0]
466 ; CHECK-NEXT: fmov d1, x8
467 ; CHECK-NEXT: urshl d0, d0, d1
468 ; CHECK-NEXT: ret
469 %tmp1 = load <1 x i64>, ptr %A
470 %tmp3 = call <1 x i64> @llvm.aarch64.neon.urshl.v1i64(<1 x i64> %tmp1, <1 x i64> <i64 1>)
471 ret <1 x i64> %tmp3
472 }
474 define i64 @urshl_scalar(ptr %A, ptr %B) nounwind {
475 ; CHECK-LABEL: urshl_scalar:
476 ; CHECK: // %bb.0:
477 ; CHECK-NEXT: ldr x8, [x0]
478 ; CHECK-NEXT: ldr x9, [x1]
479 ; CHECK-NEXT: fmov d0, x8
480 ; CHECK-NEXT: fmov d1, x9
481 ; CHECK-NEXT: urshl d0, d0, d1
482 ; CHECK-NEXT: fmov x0, d0
483 ; CHECK-NEXT: ret
484 %tmp1 = load i64, ptr %A
485 %tmp2 = load i64, ptr %B
486 %tmp3 = call i64 @llvm.aarch64.neon.urshl.i64(i64 %tmp1, i64 %tmp2)
487 ret i64 %tmp3
488 }
490 define i64 @urshl_scalar_constant(ptr %A) nounwind {
491 ; CHECK-LABEL: urshl_scalar_constant:
492 ; CHECK: // %bb.0:
493 ; CHECK-NEXT: ldr x8, [x0]
494 ; CHECK-NEXT: mov w9, #1 // =0x1
495 ; CHECK-NEXT: fmov d1, x9
496 ; CHECK-NEXT: fmov d0, x8
497 ; CHECK-NEXT: urshl d0, d0, d1
498 ; CHECK-NEXT: fmov x0, d0
499 ; CHECK-NEXT: ret
500 %tmp1 = load i64, ptr %A
501 %tmp3 = call i64 @llvm.aarch64.neon.urshl.i64(i64 %tmp1, i64 1)
502 ret i64 %tmp3
503 }
505 define <16 x i8> @srshl16b(ptr %A, ptr %B) nounwind {
506 ; CHECK-LABEL: srshl16b:
507 ; CHECK: // %bb.0:
508 ; CHECK-NEXT: ldr q0, [x0]
509 ; CHECK-NEXT: ldr q1, [x1]
510 ; CHECK-NEXT: srshl.16b v0, v0, v1
511 ; CHECK-NEXT: ret
512 %tmp1 = load <16 x i8>, ptr %A
513 %tmp2 = load <16 x i8>, ptr %B
514 %tmp3 = call <16 x i8> @llvm.aarch64.neon.srshl.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
515 ret <16 x i8> %tmp3
516 }
518 define <8 x i16> @srshl8h(ptr %A, ptr %B) nounwind {
519 ; CHECK-LABEL: srshl8h:
520 ; CHECK: // %bb.0:
521 ; CHECK-NEXT: ldr q0, [x0]
522 ; CHECK-NEXT: ldr q1, [x1]
523 ; CHECK-NEXT: srshl.8h v0, v0, v1
524 ; CHECK-NEXT: ret
525 %tmp1 = load <8 x i16>, ptr %A
526 %tmp2 = load <8 x i16>, ptr %B
527 %tmp3 = call <8 x i16> @llvm.aarch64.neon.srshl.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
528 ret <8 x i16> %tmp3
529 }
531 define <4 x i32> @srshl4s(ptr %A, ptr %B) nounwind {
532 ; CHECK-LABEL: srshl4s:
533 ; CHECK: // %bb.0:
534 ; CHECK-NEXT: ldr q0, [x0]
535 ; CHECK-NEXT: ldr q1, [x1]
536 ; CHECK-NEXT: srshl.4s v0, v0, v1
537 ; CHECK-NEXT: ret
538 %tmp1 = load <4 x i32>, ptr %A
539 %tmp2 = load <4 x i32>, ptr %B
540 %tmp3 = call <4 x i32> @llvm.aarch64.neon.srshl.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
541 ret <4 x i32> %tmp3
542 }
544 define <2 x i64> @srshl2d(ptr %A, ptr %B) nounwind {
545 ; CHECK-LABEL: srshl2d:
546 ; CHECK: // %bb.0:
547 ; CHECK-NEXT: ldr q0, [x0]
548 ; CHECK-NEXT: ldr q1, [x1]
549 ; CHECK-NEXT: srshl.2d v0, v0, v1
550 ; CHECK-NEXT: ret
551 %tmp1 = load <2 x i64>, ptr %A
552 %tmp2 = load <2 x i64>, ptr %B
553 %tmp3 = call <2 x i64> @llvm.aarch64.neon.srshl.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
554 ret <2 x i64> %tmp3
555 }
557 define <16 x i8> @urshl16b(ptr %A, ptr %B) nounwind {
558 ; CHECK-LABEL: urshl16b:
559 ; CHECK: // %bb.0:
560 ; CHECK-NEXT: ldr q0, [x0]
561 ; CHECK-NEXT: ldr q1, [x1]
562 ; CHECK-NEXT: urshl.16b v0, v0, v1
563 ; CHECK-NEXT: ret
564 %tmp1 = load <16 x i8>, ptr %A
565 %tmp2 = load <16 x i8>, ptr %B
566 %tmp3 = call <16 x i8> @llvm.aarch64.neon.urshl.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
567 ret <16 x i8> %tmp3
568 }
570 define <8 x i16> @urshl8h(ptr %A, ptr %B) nounwind {
571 ; CHECK-LABEL: urshl8h:
572 ; CHECK: // %bb.0:
573 ; CHECK-NEXT: ldr q0, [x0]
574 ; CHECK-NEXT: ldr q1, [x1]
575 ; CHECK-NEXT: urshl.8h v0, v0, v1
576 ; CHECK-NEXT: ret
577 %tmp1 = load <8 x i16>, ptr %A
578 %tmp2 = load <8 x i16>, ptr %B
579 %tmp3 = call <8 x i16> @llvm.aarch64.neon.urshl.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
580 ret <8 x i16> %tmp3
581 }
583 define <4 x i32> @urshl4s(ptr %A, ptr %B) nounwind {
584 ; CHECK-LABEL: urshl4s:
585 ; CHECK: // %bb.0:
586 ; CHECK-NEXT: ldr q0, [x0]
587 ; CHECK-NEXT: ldr q1, [x1]
588 ; CHECK-NEXT: urshl.4s v0, v0, v1
589 ; CHECK-NEXT: ret
590 %tmp1 = load <4 x i32>, ptr %A
591 %tmp2 = load <4 x i32>, ptr %B
592 %tmp3 = call <4 x i32> @llvm.aarch64.neon.urshl.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
593 ret <4 x i32> %tmp3
594 }
596 define <2 x i64> @urshl2d(ptr %A, ptr %B) nounwind {
597 ; CHECK-LABEL: urshl2d:
598 ; CHECK: // %bb.0:
599 ; CHECK-NEXT: ldr q0, [x0]
600 ; CHECK-NEXT: ldr q1, [x1]
601 ; CHECK-NEXT: urshl.2d v0, v0, v1
602 ; CHECK-NEXT: ret
603 %tmp1 = load <2 x i64>, ptr %A
604 %tmp2 = load <2 x i64>, ptr %B
605 %tmp3 = call <2 x i64> @llvm.aarch64.neon.urshl.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
606 ret <2 x i64> %tmp3
607 }
609 declare <8 x i8> @llvm.aarch64.neon.srshl.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
610 declare <4 x i16> @llvm.aarch64.neon.srshl.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
611 declare <2 x i32> @llvm.aarch64.neon.srshl.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
612 declare <1 x i64> @llvm.aarch64.neon.srshl.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
613 declare i64 @llvm.aarch64.neon.srshl.i64(i64, i64) nounwind readnone
615 declare <8 x i8> @llvm.aarch64.neon.urshl.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
616 declare <4 x i16> @llvm.aarch64.neon.urshl.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
617 declare <2 x i32> @llvm.aarch64.neon.urshl.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
618 declare <1 x i64> @llvm.aarch64.neon.urshl.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
619 declare i64 @llvm.aarch64.neon.urshl.i64(i64, i64) nounwind readnone
621 declare <16 x i8> @llvm.aarch64.neon.srshl.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
622 declare <8 x i16> @llvm.aarch64.neon.srshl.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
623 declare <4 x i32> @llvm.aarch64.neon.srshl.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
624 declare <2 x i64> @llvm.aarch64.neon.srshl.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
626 declare <16 x i8> @llvm.aarch64.neon.urshl.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
627 declare <8 x i16> @llvm.aarch64.neon.urshl.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
628 declare <4 x i32> @llvm.aarch64.neon.urshl.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
629 declare <2 x i64> @llvm.aarch64.neon.urshl.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
631 define <8 x i8> @sqrshl8b(ptr %A, ptr %B) nounwind {
632 ; CHECK-LABEL: sqrshl8b:
633 ; CHECK: // %bb.0:
634 ; CHECK-NEXT: ldr d0, [x0]
635 ; CHECK-NEXT: ldr d1, [x1]
636 ; CHECK-NEXT: sqrshl.8b v0, v0, v1
637 ; CHECK-NEXT: ret
638 %tmp1 = load <8 x i8>, ptr %A
639 %tmp2 = load <8 x i8>, ptr %B
640 %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqrshl.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
641 ret <8 x i8> %tmp3
642 }
644 define <4 x i16> @sqrshl4h(ptr %A, ptr %B) nounwind {
645 ; CHECK-LABEL: sqrshl4h:
646 ; CHECK: // %bb.0:
647 ; CHECK-NEXT: ldr d0, [x0]
648 ; CHECK-NEXT: ldr d1, [x1]
649 ; CHECK-NEXT: sqrshl.4h v0, v0, v1
650 ; CHECK-NEXT: ret
651 %tmp1 = load <4 x i16>, ptr %A
652 %tmp2 = load <4 x i16>, ptr %B
653 %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqrshl.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
654 ret <4 x i16> %tmp3
655 }
657 define <2 x i32> @sqrshl2s(ptr %A, ptr %B) nounwind {
658 ; CHECK-LABEL: sqrshl2s:
659 ; CHECK: // %bb.0:
660 ; CHECK-NEXT: ldr d0, [x0]
661 ; CHECK-NEXT: ldr d1, [x1]
662 ; CHECK-NEXT: sqrshl.2s v0, v0, v1
663 ; CHECK-NEXT: ret
664 %tmp1 = load <2 x i32>, ptr %A
665 %tmp2 = load <2 x i32>, ptr %B
666 %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqrshl.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
667 ret <2 x i32> %tmp3
668 }
670 define <8 x i8> @uqrshl8b(ptr %A, ptr %B) nounwind {
671 ; CHECK-LABEL: uqrshl8b:
672 ; CHECK: // %bb.0:
673 ; CHECK-NEXT: ldr d0, [x0]
674 ; CHECK-NEXT: ldr d1, [x1]
675 ; CHECK-NEXT: uqrshl.8b v0, v0, v1
676 ; CHECK-NEXT: ret
677 %tmp1 = load <8 x i8>, ptr %A
678 %tmp2 = load <8 x i8>, ptr %B
679 %tmp3 = call <8 x i8> @llvm.aarch64.neon.uqrshl.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
680 ret <8 x i8> %tmp3
681 }
683 define <4 x i16> @uqrshl4h(ptr %A, ptr %B) nounwind {
684 ; CHECK-LABEL: uqrshl4h:
685 ; CHECK: // %bb.0:
686 ; CHECK-NEXT: ldr d0, [x0]
687 ; CHECK-NEXT: ldr d1, [x1]
688 ; CHECK-NEXT: uqrshl.4h v0, v0, v1
689 ; CHECK-NEXT: ret
690 %tmp1 = load <4 x i16>, ptr %A
691 %tmp2 = load <4 x i16>, ptr %B
692 %tmp3 = call <4 x i16> @llvm.aarch64.neon.uqrshl.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
693 ret <4 x i16> %tmp3
694 }
696 define <2 x i32> @uqrshl2s(ptr %A, ptr %B) nounwind {
697 ; CHECK-LABEL: uqrshl2s:
698 ; CHECK: // %bb.0:
699 ; CHECK-NEXT: ldr d0, [x0]
700 ; CHECK-NEXT: ldr d1, [x1]
701 ; CHECK-NEXT: uqrshl.2s v0, v0, v1
702 ; CHECK-NEXT: ret
703 %tmp1 = load <2 x i32>, ptr %A
704 %tmp2 = load <2 x i32>, ptr %B
705 %tmp3 = call <2 x i32> @llvm.aarch64.neon.uqrshl.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
706 ret <2 x i32> %tmp3
707 }
709 define <16 x i8> @sqrshl16b(ptr %A, ptr %B) nounwind {
710 ; CHECK-LABEL: sqrshl16b:
711 ; CHECK: // %bb.0:
712 ; CHECK-NEXT: ldr q0, [x0]
713 ; CHECK-NEXT: ldr q1, [x1]
714 ; CHECK-NEXT: sqrshl.16b v0, v0, v1
715 ; CHECK-NEXT: ret
716 %tmp1 = load <16 x i8>, ptr %A
717 %tmp2 = load <16 x i8>, ptr %B
718 %tmp3 = call <16 x i8> @llvm.aarch64.neon.sqrshl.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
719 ret <16 x i8> %tmp3
720 }
722 define <8 x i16> @sqrshl8h(ptr %A, ptr %B) nounwind {
723 ; CHECK-LABEL: sqrshl8h:
724 ; CHECK: // %bb.0:
725 ; CHECK-NEXT: ldr q0, [x0]
726 ; CHECK-NEXT: ldr q1, [x1]
727 ; CHECK-NEXT: sqrshl.8h v0, v0, v1
728 ; CHECK-NEXT: ret
729 %tmp1 = load <8 x i16>, ptr %A
730 %tmp2 = load <8 x i16>, ptr %B
731 %tmp3 = call <8 x i16> @llvm.aarch64.neon.sqrshl.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
732 ret <8 x i16> %tmp3
733 }
735 define <4 x i32> @sqrshl4s(ptr %A, ptr %B) nounwind {
736 ; CHECK-LABEL: sqrshl4s:
737 ; CHECK: // %bb.0:
738 ; CHECK-NEXT: ldr q0, [x0]
739 ; CHECK-NEXT: ldr q1, [x1]
740 ; CHECK-NEXT: sqrshl.4s v0, v0, v1
741 ; CHECK-NEXT: ret
742 %tmp1 = load <4 x i32>, ptr %A
743 %tmp2 = load <4 x i32>, ptr %B
744 %tmp3 = call <4 x i32> @llvm.aarch64.neon.sqrshl.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
745 ret <4 x i32> %tmp3
746 }
748 define <2 x i64> @sqrshl2d(ptr %A, ptr %B) nounwind {
749 ; CHECK-LABEL: sqrshl2d:
750 ; CHECK: // %bb.0:
751 ; CHECK-NEXT: ldr q0, [x0]
752 ; CHECK-NEXT: ldr q1, [x1]
753 ; CHECK-NEXT: sqrshl.2d v0, v0, v1
754 ; CHECK-NEXT: ret
755 %tmp1 = load <2 x i64>, ptr %A
756 %tmp2 = load <2 x i64>, ptr %B
757 %tmp3 = call <2 x i64> @llvm.aarch64.neon.sqrshl.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
758 ret <2 x i64> %tmp3
759 }
761 define <1 x i64> @sqrshl1d(ptr %A, ptr %B) nounwind {
762 ; CHECK-LABEL: sqrshl1d:
763 ; CHECK: // %bb.0:
764 ; CHECK-NEXT: ldr d0, [x0]
765 ; CHECK-NEXT: ldr d1, [x1]
766 ; CHECK-NEXT: sqrshl d0, d0, d1
767 ; CHECK-NEXT: ret
768 %tmp1 = load <1 x i64>, ptr %A
769 %tmp2 = load <1 x i64>, ptr %B
770 %tmp3 = call <1 x i64> @llvm.aarch64.neon.sqrshl.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
771 ret <1 x i64> %tmp3
772 }
774 define <1 x i64> @sqrshl1d_constant(ptr %A) nounwind {
775 ; CHECK-LABEL: sqrshl1d_constant:
776 ; CHECK: // %bb.0:
777 ; CHECK-NEXT: mov w8, #1 // =0x1
778 ; CHECK-NEXT: ldr d0, [x0]
779 ; CHECK-NEXT: fmov d1, x8
780 ; CHECK-NEXT: sqrshl d0, d0, d1
781 ; CHECK-NEXT: ret
782 %tmp1 = load <1 x i64>, ptr %A
783 %tmp3 = call <1 x i64> @llvm.aarch64.neon.sqrshl.v1i64(<1 x i64> %tmp1, <1 x i64> <i64 1>)
784 ret <1 x i64> %tmp3
785 }
787 define i64 @sqrshl_scalar(ptr %A, ptr %B) nounwind {
788 ; CHECK-LABEL: sqrshl_scalar:
789 ; CHECK: // %bb.0:
790 ; CHECK-NEXT: ldr x8, [x0]
791 ; CHECK-NEXT: ldr x9, [x1]
792 ; CHECK-NEXT: fmov d0, x8
793 ; CHECK-NEXT: fmov d1, x9
794 ; CHECK-NEXT: sqrshl d0, d0, d1
795 ; CHECK-NEXT: fmov x0, d0
796 ; CHECK-NEXT: ret
797 %tmp1 = load i64, ptr %A
798 %tmp2 = load i64, ptr %B
799 %tmp3 = call i64 @llvm.aarch64.neon.sqrshl.i64(i64 %tmp1, i64 %tmp2)
800 ret i64 %tmp3
801 }
803 define i64 @sqrshl_scalar_constant(ptr %A) nounwind {
804 ; CHECK-LABEL: sqrshl_scalar_constant:
805 ; CHECK: // %bb.0:
806 ; CHECK-NEXT: ldr x8, [x0]
807 ; CHECK-NEXT: mov w9, #1 // =0x1
808 ; CHECK-NEXT: fmov d1, x9
809 ; CHECK-NEXT: fmov d0, x8
810 ; CHECK-NEXT: sqrshl d0, d0, d1
811 ; CHECK-NEXT: fmov x0, d0
812 ; CHECK-NEXT: ret
813 %tmp1 = load i64, ptr %A
814 %tmp3 = call i64 @llvm.aarch64.neon.sqrshl.i64(i64 %tmp1, i64 1)
815 ret i64 %tmp3
816 }
818 define <16 x i8> @uqrshl16b(ptr %A, ptr %B) nounwind {
819 ; CHECK-LABEL: uqrshl16b:
820 ; CHECK: // %bb.0:
821 ; CHECK-NEXT: ldr q0, [x0]
822 ; CHECK-NEXT: ldr q1, [x1]
823 ; CHECK-NEXT: uqrshl.16b v0, v0, v1
824 ; CHECK-NEXT: ret
825 %tmp1 = load <16 x i8>, ptr %A
826 %tmp2 = load <16 x i8>, ptr %B
827 %tmp3 = call <16 x i8> @llvm.aarch64.neon.uqrshl.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
828 ret <16 x i8> %tmp3
829 }
831 define <8 x i16> @uqrshl8h(ptr %A, ptr %B) nounwind {
832 ; CHECK-LABEL: uqrshl8h:
833 ; CHECK: // %bb.0:
834 ; CHECK-NEXT: ldr q0, [x0]
835 ; CHECK-NEXT: ldr q1, [x1]
836 ; CHECK-NEXT: uqrshl.8h v0, v0, v1
837 ; CHECK-NEXT: ret
838 %tmp1 = load <8 x i16>, ptr %A
839 %tmp2 = load <8 x i16>, ptr %B
840 %tmp3 = call <8 x i16> @llvm.aarch64.neon.uqrshl.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
841 ret <8 x i16> %tmp3
842 }
844 define <4 x i32> @uqrshl4s(ptr %A, ptr %B) nounwind {
845 ; CHECK-LABEL: uqrshl4s:
846 ; CHECK: // %bb.0:
847 ; CHECK-NEXT: ldr q0, [x0]
848 ; CHECK-NEXT: ldr q1, [x1]
849 ; CHECK-NEXT: uqrshl.4s v0, v0, v1
850 ; CHECK-NEXT: ret
851 %tmp1 = load <4 x i32>, ptr %A
852 %tmp2 = load <4 x i32>, ptr %B
853 %tmp3 = call <4 x i32> @llvm.aarch64.neon.uqrshl.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
854 ret <4 x i32> %tmp3
855 }
857 define <2 x i64> @uqrshl2d(ptr %A, ptr %B) nounwind {
858 ; CHECK-LABEL: uqrshl2d:
859 ; CHECK: // %bb.0:
860 ; CHECK-NEXT: ldr q0, [x0]
861 ; CHECK-NEXT: ldr q1, [x1]
862 ; CHECK-NEXT: uqrshl.2d v0, v0, v1
863 ; CHECK-NEXT: ret
864 %tmp1 = load <2 x i64>, ptr %A
865 %tmp2 = load <2 x i64>, ptr %B
866 %tmp3 = call <2 x i64> @llvm.aarch64.neon.uqrshl.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
867 ret <2 x i64> %tmp3
868 }
870 define <1 x i64> @uqrshl1d(ptr %A, ptr %B) nounwind {
871 ; CHECK-LABEL: uqrshl1d:
872 ; CHECK: // %bb.0:
873 ; CHECK-NEXT: ldr d0, [x0]
874 ; CHECK-NEXT: ldr d1, [x1]
875 ; CHECK-NEXT: uqrshl d0, d0, d1
876 ; CHECK-NEXT: ret
877 %tmp1 = load <1 x i64>, ptr %A
878 %tmp2 = load <1 x i64>, ptr %B
879 %tmp3 = call <1 x i64> @llvm.aarch64.neon.uqrshl.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
880 ret <1 x i64> %tmp3
881 }
883 define <1 x i64> @uqrshl1d_constant(ptr %A) nounwind {
884 ; CHECK-LABEL: uqrshl1d_constant:
885 ; CHECK: // %bb.0:
886 ; CHECK-NEXT: mov w8, #1 // =0x1
887 ; CHECK-NEXT: ldr d0, [x0]
888 ; CHECK-NEXT: fmov d1, x8
889 ; CHECK-NEXT: uqrshl d0, d0, d1
890 ; CHECK-NEXT: ret
891 %tmp1 = load <1 x i64>, ptr %A
892 %tmp3 = call <1 x i64> @llvm.aarch64.neon.uqrshl.v1i64(<1 x i64> %tmp1, <1 x i64> <i64 1>)
893 ret <1 x i64> %tmp3
894 }
896 define i64 @uqrshl_scalar(ptr %A, ptr %B) nounwind {
897 ; CHECK-LABEL: uqrshl_scalar:
898 ; CHECK: // %bb.0:
899 ; CHECK-NEXT: ldr x8, [x0]
900 ; CHECK-NEXT: ldr x9, [x1]
901 ; CHECK-NEXT: fmov d0, x8
902 ; CHECK-NEXT: fmov d1, x9
903 ; CHECK-NEXT: uqrshl d0, d0, d1
904 ; CHECK-NEXT: fmov x0, d0
905 ; CHECK-NEXT: ret
906 %tmp1 = load i64, ptr %A
907 %tmp2 = load i64, ptr %B
908 %tmp3 = call i64 @llvm.aarch64.neon.uqrshl.i64(i64 %tmp1, i64 %tmp2)
909 ret i64 %tmp3
910 }
912 define i64 @uqrshl_scalar_constant(ptr %A) nounwind {
913 ; CHECK-LABEL: uqrshl_scalar_constant:
914 ; CHECK: // %bb.0:
915 ; CHECK-NEXT: ldr x8, [x0]
916 ; CHECK-NEXT: mov w9, #1 // =0x1
917 ; CHECK-NEXT: fmov d1, x9
918 ; CHECK-NEXT: fmov d0, x8
919 ; CHECK-NEXT: uqrshl d0, d0, d1
920 ; CHECK-NEXT: fmov x0, d0
921 ; CHECK-NEXT: ret
922 %tmp1 = load i64, ptr %A
923 %tmp3 = call i64 @llvm.aarch64.neon.uqrshl.i64(i64 %tmp1, i64 1)
924 ret i64 %tmp3
925 }
927 declare <8 x i8> @llvm.aarch64.neon.sqrshl.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
928 declare <4 x i16> @llvm.aarch64.neon.sqrshl.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
929 declare <2 x i32> @llvm.aarch64.neon.sqrshl.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
930 declare <1 x i64> @llvm.aarch64.neon.sqrshl.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
931 declare i64 @llvm.aarch64.neon.sqrshl.i64(i64, i64) nounwind readnone
933 declare <8 x i8> @llvm.aarch64.neon.uqrshl.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
934 declare <4 x i16> @llvm.aarch64.neon.uqrshl.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
935 declare <2 x i32> @llvm.aarch64.neon.uqrshl.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
936 declare <1 x i64> @llvm.aarch64.neon.uqrshl.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
937 declare i64 @llvm.aarch64.neon.uqrshl.i64(i64, i64) nounwind readnone
939 declare <16 x i8> @llvm.aarch64.neon.sqrshl.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
940 declare <8 x i16> @llvm.aarch64.neon.sqrshl.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
941 declare <4 x i32> @llvm.aarch64.neon.sqrshl.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
942 declare <2 x i64> @llvm.aarch64.neon.sqrshl.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
944 declare <16 x i8> @llvm.aarch64.neon.uqrshl.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
945 declare <8 x i16> @llvm.aarch64.neon.uqrshl.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
946 declare <4 x i32> @llvm.aarch64.neon.uqrshl.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
947 declare <2 x i64> @llvm.aarch64.neon.uqrshl.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
949 define <8 x i8> @urshr8b(ptr %A) nounwind {
950 ; CHECK-LABEL: urshr8b:
951 ; CHECK: // %bb.0:
952 ; CHECK-NEXT: ldr d0, [x0]
953 ; CHECK-NEXT: urshr.8b v0, v0, #1
954 ; CHECK-NEXT: ret
955 %tmp1 = load <8 x i8>, ptr %A
956 %tmp3 = call <8 x i8> @llvm.aarch64.neon.urshl.v8i8(<8 x i8> %tmp1, <8 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)
957 ret <8 x i8> %tmp3
958 }
960 define <4 x i16> @urshr4h(ptr %A) nounwind {
961 ; CHECK-LABEL: urshr4h:
962 ; CHECK: // %bb.0:
963 ; CHECK-NEXT: ldr d0, [x0]
964 ; CHECK-NEXT: urshr.4h v0, v0, #1
965 ; CHECK-NEXT: ret
966 %tmp1 = load <4 x i16>, ptr %A
967 %tmp3 = call <4 x i16> @llvm.aarch64.neon.urshl.v4i16(<4 x i16> %tmp1, <4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>)
968 ret <4 x i16> %tmp3
969 }
971 define <2 x i32> @urshr2s(ptr %A) nounwind {
972 ; CHECK-LABEL: urshr2s:
973 ; CHECK: // %bb.0:
974 ; CHECK-NEXT: ldr d0, [x0]
975 ; CHECK-NEXT: urshr.2s v0, v0, #1
976 ; CHECK-NEXT: ret
977 %tmp1 = load <2 x i32>, ptr %A
978 %tmp3 = call <2 x i32> @llvm.aarch64.neon.urshl.v2i32(<2 x i32> %tmp1, <2 x i32> <i32 -1, i32 -1>)
979 ret <2 x i32> %tmp3
980 }
982 define <16 x i8> @urshr16b(ptr %A) nounwind {
983 ; CHECK-LABEL: urshr16b:
984 ; CHECK: // %bb.0:
985 ; CHECK-NEXT: ldr q0, [x0]
986 ; CHECK-NEXT: urshr.16b v0, v0, #1
987 ; CHECK-NEXT: ret
988 %tmp1 = load <16 x i8>, ptr %A
989 %tmp3 = call <16 x i8> @llvm.aarch64.neon.urshl.v16i8(<16 x i8> %tmp1, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)
990 ret <16 x i8> %tmp3
991 }
993 define <8 x i16> @urshr8h(ptr %A) nounwind {
994 ; CHECK-LABEL: urshr8h:
995 ; CHECK: // %bb.0:
996 ; CHECK-NEXT: ldr q0, [x0]
997 ; CHECK-NEXT: urshr.8h v0, v0, #1
998 ; CHECK-NEXT: ret
999 %tmp1 = load <8 x i16>, ptr %A
1000 %tmp3 = call <8 x i16> @llvm.aarch64.neon.urshl.v8i16(<8 x i16> %tmp1, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>)
1001 ret <8 x i16> %tmp3
1002 }
1004 define <4 x i32> @urshr4s(ptr %A) nounwind {
1005 ; CHECK-LABEL: urshr4s:
1006 ; CHECK: // %bb.0:
1007 ; CHECK-NEXT: ldr q0, [x0]
1008 ; CHECK-NEXT: urshr.4s v0, v0, #1
1009 ; CHECK-NEXT: ret
1010 %tmp1 = load <4 x i32>, ptr %A
1011 %tmp3 = call <4 x i32> @llvm.aarch64.neon.urshl.v4i32(<4 x i32> %tmp1, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>)
1012 ret <4 x i32> %tmp3
1013 }
1015 define <2 x i64> @urshr2d(ptr %A) nounwind {
1016 ; CHECK-LABEL: urshr2d:
1017 ; CHECK: // %bb.0:
1018 ; CHECK-NEXT: ldr q0, [x0]
1019 ; CHECK-NEXT: urshr.2d v0, v0, #1
1020 ; CHECK-NEXT: ret
1021 %tmp1 = load <2 x i64>, ptr %A
1022 %tmp3 = call <2 x i64> @llvm.aarch64.neon.urshl.v2i64(<2 x i64> %tmp1, <2 x i64> <i64 -1, i64 -1>)
1023 ret <2 x i64> %tmp3
1024 }
1026 define <1 x i64> @urshr1d(ptr %A) nounwind {
1027 ; CHECK-LABEL: urshr1d:
1028 ; CHECK: // %bb.0:
1029 ; CHECK-NEXT: ldr d0, [x0]
1030 ; CHECK-NEXT: urshr d0, d0, #1
1031 ; CHECK-NEXT: ret
1032 %tmp1 = load <1 x i64>, ptr %A
1033 %tmp3 = call <1 x i64> @llvm.aarch64.neon.urshl.v1i64(<1 x i64> %tmp1, <1 x i64> <i64 -1>)
1034 ret <1 x i64> %tmp3
1035 }
1037 define i64 @urshr_scalar(ptr %A) nounwind {
1038 ; CHECK-LABEL: urshr_scalar:
1039 ; CHECK: // %bb.0:
1040 ; CHECK-NEXT: ldr d0, [x0]
1041 ; CHECK-NEXT: urshr d0, d0, #1
1042 ; CHECK-NEXT: fmov x0, d0
1043 ; CHECK-NEXT: ret
1044 %tmp1 = load i64, ptr %A
1045 %tmp3 = call i64 @llvm.aarch64.neon.urshl.i64(i64 %tmp1, i64 -1)
1046 ret i64 %tmp3
1047 }
1049 define <8 x i8> @srshr8b(ptr %A) nounwind {
1050 ; CHECK-LABEL: srshr8b:
1051 ; CHECK: // %bb.0:
1052 ; CHECK-NEXT: ldr d0, [x0]
1053 ; CHECK-NEXT: srshr.8b v0, v0, #1
1054 ; CHECK-NEXT: ret
1055 %tmp1 = load <8 x i8>, ptr %A
1056 %tmp3 = call <8 x i8> @llvm.aarch64.neon.srshl.v8i8(<8 x i8> %tmp1, <8 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)
1057 ret <8 x i8> %tmp3
1058 }
1060 define <4 x i16> @srshr4h(ptr %A) nounwind {
1061 ; CHECK-LABEL: srshr4h:
1062 ; CHECK: // %bb.0:
1063 ; CHECK-NEXT: ldr d0, [x0]
1064 ; CHECK-NEXT: srshr.4h v0, v0, #1
1065 ; CHECK-NEXT: ret
1066 %tmp1 = load <4 x i16>, ptr %A
1067 %tmp3 = call <4 x i16> @llvm.aarch64.neon.srshl.v4i16(<4 x i16> %tmp1, <4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>)
1068 ret <4 x i16> %tmp3
1069 }
1071 define <2 x i32> @srshr2s(ptr %A) nounwind {
1072 ; CHECK-LABEL: srshr2s:
1073 ; CHECK: // %bb.0:
1074 ; CHECK-NEXT: ldr d0, [x0]
1075 ; CHECK-NEXT: srshr.2s v0, v0, #1
1076 ; CHECK-NEXT: ret
1077 %tmp1 = load <2 x i32>, ptr %A
1078 %tmp3 = call <2 x i32> @llvm.aarch64.neon.srshl.v2i32(<2 x i32> %tmp1, <2 x i32> <i32 -1, i32 -1>)
1079 ret <2 x i32> %tmp3
1080 }
1082 define <16 x i8> @srshr16b(ptr %A) nounwind {
1083 ; CHECK-LABEL: srshr16b:
1084 ; CHECK: // %bb.0:
1085 ; CHECK-NEXT: ldr q0, [x0]
1086 ; CHECK-NEXT: srshr.16b v0, v0, #1
1087 ; CHECK-NEXT: ret
1088 %tmp1 = load <16 x i8>, ptr %A
1089 %tmp3 = call <16 x i8> @llvm.aarch64.neon.srshl.v16i8(<16 x i8> %tmp1, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)
1090 ret <16 x i8> %tmp3
1091 }
1093 define <8 x i16> @srshr8h(ptr %A) nounwind {
1094 ; CHECK-LABEL: srshr8h:
1095 ; CHECK: // %bb.0:
1096 ; CHECK-NEXT: ldr q0, [x0]
1097 ; CHECK-NEXT: srshr.8h v0, v0, #1
1098 ; CHECK-NEXT: ret
1099 %tmp1 = load <8 x i16>, ptr %A
1100 %tmp3 = call <8 x i16> @llvm.aarch64.neon.srshl.v8i16(<8 x i16> %tmp1, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>)
1101 ret <8 x i16> %tmp3
1102 }
1104 define <4 x i32> @srshr4s(ptr %A) nounwind {
1105 ; CHECK-LABEL: srshr4s:
1106 ; CHECK: // %bb.0:
1107 ; CHECK-NEXT: ldr q0, [x0]
1108 ; CHECK-NEXT: srshr.4s v0, v0, #1
1109 ; CHECK-NEXT: ret
1110 %tmp1 = load <4 x i32>, ptr %A
1111 %tmp3 = call <4 x i32> @llvm.aarch64.neon.srshl.v4i32(<4 x i32> %tmp1, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>)
1112 ret <4 x i32> %tmp3
1113 }
1115 define <2 x i64> @srshr2d(ptr %A) nounwind {
1116 ; CHECK-LABEL: srshr2d:
1117 ; CHECK: // %bb.0:
1118 ; CHECK-NEXT: ldr q0, [x0]
1119 ; CHECK-NEXT: srshr.2d v0, v0, #1
1120 ; CHECK-NEXT: ret
1121 %tmp1 = load <2 x i64>, ptr %A
1122 %tmp3 = call <2 x i64> @llvm.aarch64.neon.srshl.v2i64(<2 x i64> %tmp1, <2 x i64> <i64 -1, i64 -1>)
1123 ret <2 x i64> %tmp3
1124 }
1126 define <1 x i64> @srshr1d(ptr %A) nounwind {
1127 ; CHECK-LABEL: srshr1d:
1128 ; CHECK: // %bb.0:
1129 ; CHECK-NEXT: ldr d0, [x0]
1130 ; CHECK-NEXT: srshr d0, d0, #1
1131 ; CHECK-NEXT: ret
1132 %tmp1 = load <1 x i64>, ptr %A
1133 %tmp3 = call <1 x i64> @llvm.aarch64.neon.srshl.v1i64(<1 x i64> %tmp1, <1 x i64> <i64 -1>)
1134 ret <1 x i64> %tmp3
1135 }
1137 define i64 @srshr_scalar(ptr %A) nounwind {
1138 ; CHECK-LABEL: srshr_scalar:
1139 ; CHECK: // %bb.0:
1140 ; CHECK-NEXT: ldr d0, [x0]
1141 ; CHECK-NEXT: srshr d0, d0, #1
1142 ; CHECK-NEXT: fmov x0, d0
1143 ; CHECK-NEXT: ret
1144 %tmp1 = load i64, ptr %A
1145 %tmp3 = call i64 @llvm.aarch64.neon.srshl.i64(i64 %tmp1, i64 -1)
1146 ret i64 %tmp3
1147 }
1149 define <8 x i8> @sqshlu8b(ptr %A) nounwind {
1150 ; CHECK-LABEL: sqshlu8b:
1151 ; CHECK: // %bb.0:
1152 ; CHECK-NEXT: ldr d0, [x0]
1153 ; CHECK-NEXT: sqshlu.8b v0, v0, #1
1154 ; CHECK-NEXT: ret
1155 %tmp1 = load <8 x i8>, ptr %A
1156 %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqshlu.v8i8(<8 x i8> %tmp1, <8 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)
1157 ret <8 x i8> %tmp3
1158 }
1160 define <4 x i16> @sqshlu4h(ptr %A) nounwind {
1161 ; CHECK-LABEL: sqshlu4h:
1162 ; CHECK: // %bb.0:
1163 ; CHECK-NEXT: ldr d0, [x0]
1164 ; CHECK-NEXT: sqshlu.4h v0, v0, #1
1165 ; CHECK-NEXT: ret
1166 %tmp1 = load <4 x i16>, ptr %A
1167 %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqshlu.v4i16(<4 x i16> %tmp1, <4 x i16> <i16 1, i16 1, i16 1, i16 1>)
1168 ret <4 x i16> %tmp3
1169 }
1171 define <2 x i32> @sqshlu2s(ptr %A) nounwind {
1172 ; CHECK-LABEL: sqshlu2s:
1173 ; CHECK: // %bb.0:
1174 ; CHECK-NEXT: ldr d0, [x0]
1175 ; CHECK-NEXT: sqshlu.2s v0, v0, #1
1176 ; CHECK-NEXT: ret
1177 %tmp1 = load <2 x i32>, ptr %A
1178 %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqshlu.v2i32(<2 x i32> %tmp1, <2 x i32> <i32 1, i32 1>)
1179 ret <2 x i32> %tmp3
1180 }
1182 define <16 x i8> @sqshlu16b(ptr %A) nounwind {
1183 ; CHECK-LABEL: sqshlu16b:
1184 ; CHECK: // %bb.0:
1185 ; CHECK-NEXT: ldr q0, [x0]
1186 ; CHECK-NEXT: sqshlu.16b v0, v0, #1
1187 ; CHECK-NEXT: ret
1188 %tmp1 = load <16 x i8>, ptr %A
1189 %tmp3 = call <16 x i8> @llvm.aarch64.neon.sqshlu.v16i8(<16 x i8> %tmp1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)
1190 ret <16 x i8> %tmp3
1191 }
1193 define <8 x i16> @sqshlu8h(ptr %A) nounwind {
1194 ; CHECK-LABEL: sqshlu8h:
1195 ; CHECK: // %bb.0:
1196 ; CHECK-NEXT: ldr q0, [x0]
1197 ; CHECK-NEXT: sqshlu.8h v0, v0, #1
1198 ; CHECK-NEXT: ret
1199 %tmp1 = load <8 x i16>, ptr %A
1200 %tmp3 = call <8 x i16> @llvm.aarch64.neon.sqshlu.v8i16(<8 x i16> %tmp1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)
1201 ret <8 x i16> %tmp3
1202 }
1204 define <4 x i32> @sqshlu4s(ptr %A) nounwind {
1205 ; CHECK-LABEL: sqshlu4s:
1206 ; CHECK: // %bb.0:
1207 ; CHECK-NEXT: ldr q0, [x0]
1208 ; CHECK-NEXT: sqshlu.4s v0, v0, #1
1209 ; CHECK-NEXT: ret
1210 %tmp1 = load <4 x i32>, ptr %A
1211 %tmp3 = call <4 x i32> @llvm.aarch64.neon.sqshlu.v4i32(<4 x i32> %tmp1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)
1212 ret <4 x i32> %tmp3
1213 }
1215 define <2 x i64> @sqshlu2d(ptr %A) nounwind {
1216 ; CHECK-LABEL: sqshlu2d:
1217 ; CHECK: // %bb.0:
1218 ; CHECK-NEXT: ldr q0, [x0]
1219 ; CHECK-NEXT: sqshlu.2d v0, v0, #1
1220 ; CHECK-NEXT: ret
1221 %tmp1 = load <2 x i64>, ptr %A
1222 %tmp3 = call <2 x i64> @llvm.aarch64.neon.sqshlu.v2i64(<2 x i64> %tmp1, <2 x i64> <i64 1, i64 1>)
1223 ret <2 x i64> %tmp3
1224 }
1226 define <1 x i64> @sqshlu1d_constant(ptr %A) nounwind {
1227 ; CHECK-LABEL: sqshlu1d_constant:
1228 ; CHECK: // %bb.0:
1229 ; CHECK-NEXT: ldr d0, [x0]
1230 ; CHECK-NEXT: sqshlu d0, d0, #1
1231 ; CHECK-NEXT: ret
1232 %tmp1 = load <1 x i64>, ptr %A
1233 %tmp3 = call <1 x i64> @llvm.aarch64.neon.sqshlu.v1i64(<1 x i64> %tmp1, <1 x i64> <i64 1>)
1234 ret <1 x i64> %tmp3
1235 }
1237 define i64 @sqshlu_i64_constant(ptr %A) nounwind {
1238 ; CHECK-LABEL: sqshlu_i64_constant:
1239 ; CHECK: // %bb.0:
1240 ; CHECK-NEXT: ldr d0, [x0]
1241 ; CHECK-NEXT: sqshlu d0, d0, #1
1242 ; CHECK-NEXT: fmov x0, d0
1243 ; CHECK-NEXT: ret
1244 %tmp1 = load i64, ptr %A
1245 %tmp3 = call i64 @llvm.aarch64.neon.sqshlu.i64(i64 %tmp1, i64 1)
1246 ret i64 %tmp3
1247 }
1249 define i32 @sqshlu_i32_constant(ptr %A) nounwind {
1250 ; CHECK-LABEL: sqshlu_i32_constant:
1251 ; CHECK: // %bb.0:
1252 ; CHECK-NEXT: ldr w8, [x0]
1253 ; CHECK-NEXT: fmov s0, w8
1254 ; CHECK-NEXT: sqshlu s0, s0, #1
1255 ; CHECK-NEXT: fmov w0, s0
1256 ; CHECK-NEXT: ret
1257 %tmp1 = load i32, ptr %A
1258 %tmp3 = call i32 @llvm.aarch64.neon.sqshlu.i32(i32 %tmp1, i32 1)
1259 ret i32 %tmp3
1260 }
1262 declare <8 x i8> @llvm.aarch64.neon.sqshlu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
1263 declare <4 x i16> @llvm.aarch64.neon.sqshlu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
1264 declare <2 x i32> @llvm.aarch64.neon.sqshlu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
1265 declare <1 x i64> @llvm.aarch64.neon.sqshlu.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
1266 declare i64 @llvm.aarch64.neon.sqshlu.i64(i64, i64) nounwind readnone
1267 declare i32 @llvm.aarch64.neon.sqshlu.i32(i32, i32) nounwind readnone
1269 declare <16 x i8> @llvm.aarch64.neon.sqshlu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
1270 declare <8 x i16> @llvm.aarch64.neon.sqshlu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
1271 declare <4 x i32> @llvm.aarch64.neon.sqshlu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
1272 declare <2 x i64> @llvm.aarch64.neon.sqshlu.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
1274 define <8 x i8> @rshrn8b(ptr %A) nounwind {
1275 ; CHECK-LABEL: rshrn8b:
1276 ; CHECK: // %bb.0:
1277 ; CHECK-NEXT: ldr q0, [x0]
1278 ; CHECK-NEXT: rshrn.8b v0, v0, #1
1279 ; CHECK-NEXT: ret
1280 %tmp1 = load <8 x i16>, ptr %A
1281 %tmp3 = call <8 x i8> @llvm.aarch64.neon.rshrn.v8i8(<8 x i16> %tmp1, i32 1)
1282 ret <8 x i8> %tmp3
1283 }
1285 define <4 x i16> @rshrn4h(ptr %A) nounwind {
1286 ; CHECK-LABEL: rshrn4h:
1287 ; CHECK: // %bb.0:
1288 ; CHECK-NEXT: ldr q0, [x0]
1289 ; CHECK-NEXT: rshrn.4h v0, v0, #1
1290 ; CHECK-NEXT: ret
1291 %tmp1 = load <4 x i32>, ptr %A
1292 %tmp3 = call <4 x i16> @llvm.aarch64.neon.rshrn.v4i16(<4 x i32> %tmp1, i32 1)
1293 ret <4 x i16> %tmp3
1294 }
1296 define <2 x i32> @rshrn2s(ptr %A) nounwind {
1297 ; CHECK-LABEL: rshrn2s:
1298 ; CHECK: // %bb.0:
1299 ; CHECK-NEXT: ldr q0, [x0]
1300 ; CHECK-NEXT: rshrn.2s v0, v0, #1
1301 ; CHECK-NEXT: ret
1302 %tmp1 = load <2 x i64>, ptr %A
1303 %tmp3 = call <2 x i32> @llvm.aarch64.neon.rshrn.v2i32(<2 x i64> %tmp1, i32 1)
1304 ret <2 x i32> %tmp3
1305 }
1307 define <16 x i8> @rshrn16b(ptr %ret, ptr %A) nounwind {
1308 ; CHECK-LABEL: rshrn16b:
1309 ; CHECK: // %bb.0:
1310 ; CHECK-NEXT: ldr d0, [x0]
1311 ; CHECK-NEXT: ldr q1, [x1]
1312 ; CHECK-NEXT: rshrn2.16b v0, v1, #1
1313 ; CHECK-NEXT: ret
1314 %out = load <8 x i8>, ptr %ret
1315 %tmp1 = load <8 x i16>, ptr %A
1316 %tmp3 = call <8 x i8> @llvm.aarch64.neon.rshrn.v8i8(<8 x i16> %tmp1, i32 1)
1317 %tmp4 = shufflevector <8 x i8> %out, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
1318 ret <16 x i8> %tmp4
1319 }
1321 define <8 x i16> @rshrn8h(ptr %ret, ptr %A) nounwind {
1322 ; CHECK-LABEL: rshrn8h:
1323 ; CHECK: // %bb.0:
1324 ; CHECK-NEXT: ldr d0, [x0]
1325 ; CHECK-NEXT: ldr q1, [x1]
1326 ; CHECK-NEXT: rshrn2.8h v0, v1, #1
1327 ; CHECK-NEXT: ret
1328 %out = load <4 x i16>, ptr %ret
1329 %tmp1 = load <4 x i32>, ptr %A
1330 %tmp3 = call <4 x i16> @llvm.aarch64.neon.rshrn.v4i16(<4 x i32> %tmp1, i32 1)
1331 %tmp4 = shufflevector <4 x i16> %out, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
1332 ret <8 x i16> %tmp4
1333 }
1335 define <4 x i32> @rshrn4s(ptr %ret, ptr %A) nounwind {
1336 ; CHECK-LABEL: rshrn4s:
1337 ; CHECK: // %bb.0:
1338 ; CHECK-NEXT: ldr d0, [x0]
1339 ; CHECK-NEXT: ldr q1, [x1]
1340 ; CHECK-NEXT: rshrn2.4s v0, v1, #1
1341 ; CHECK-NEXT: ret
1342 %out = load <2 x i32>, ptr %ret
1343 %tmp1 = load <2 x i64>, ptr %A
1344 %tmp3 = call <2 x i32> @llvm.aarch64.neon.rshrn.v2i32(<2 x i64> %tmp1, i32 1)
1345 %tmp4 = shufflevector <2 x i32> %out, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
1346 ret <4 x i32> %tmp4
1347 }
1349 declare <8 x i8> @llvm.aarch64.neon.rshrn.v8i8(<8 x i16>, i32) nounwind readnone
1350 declare <4 x i16> @llvm.aarch64.neon.rshrn.v4i16(<4 x i32>, i32) nounwind readnone
1351 declare <2 x i32> @llvm.aarch64.neon.rshrn.v2i32(<2 x i64>, i32) nounwind readnone
1353 define <8 x i8> @shrn8b(ptr %A) nounwind {
1354 ; CHECK-LABEL: shrn8b:
1355 ; CHECK: // %bb.0:
1356 ; CHECK-NEXT: ldr q0, [x0]
1357 ; CHECK-NEXT: shrn.8b v0, v0, #1
1358 ; CHECK-NEXT: ret
1359 %tmp1 = load <8 x i16>, ptr %A
1360 %tmp2 = lshr <8 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
1361 %tmp3 = trunc <8 x i16> %tmp2 to <8 x i8>
1362 ret <8 x i8> %tmp3
1363 }
1365 define <4 x i16> @shrn4h(ptr %A) nounwind {
1366 ; CHECK-LABEL: shrn4h:
1367 ; CHECK: // %bb.0:
1368 ; CHECK-NEXT: ldr q0, [x0]
1369 ; CHECK-NEXT: shrn.4h v0, v0, #1
1370 ; CHECK-NEXT: ret
1371 %tmp1 = load <4 x i32>, ptr %A
1372 %tmp2 = lshr <4 x i32> %tmp1, <i32 1, i32 1, i32 1, i32 1>
1373 %tmp3 = trunc <4 x i32> %tmp2 to <4 x i16>
1374 ret <4 x i16> %tmp3
1375 }
1377 define <2 x i32> @shrn2s(ptr %A) nounwind {
1378 ; CHECK-LABEL: shrn2s:
1379 ; CHECK: // %bb.0:
1380 ; CHECK-NEXT: ldr q0, [x0]
1381 ; CHECK-NEXT: shrn.2s v0, v0, #1
1382 ; CHECK-NEXT: ret
1383 %tmp1 = load <2 x i64>, ptr %A
1384 %tmp2 = lshr <2 x i64> %tmp1, <i64 1, i64 1>
1385 %tmp3 = trunc <2 x i64> %tmp2 to <2 x i32>
1386 ret <2 x i32> %tmp3
1387 }
1389 define <16 x i8> @shrn16b(ptr %ret, ptr %A) nounwind {
1390 ; CHECK-LABEL: shrn16b:
1391 ; CHECK: // %bb.0:
1392 ; CHECK-NEXT: ldr d0, [x0]
1393 ; CHECK-NEXT: ldr q1, [x1]
1394 ; CHECK-NEXT: shrn2.16b v0, v1, #1
1395 ; CHECK-NEXT: ret
1396 %out = load <8 x i8>, ptr %ret
1397 %tmp1 = load <8 x i16>, ptr %A
1398 %tmp2 = lshr <8 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
1399 %tmp3 = trunc <8 x i16> %tmp2 to <8 x i8>
1400 %tmp4 = shufflevector <8 x i8> %out, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
1401 ret <16 x i8> %tmp4
1402 }
1404 define <8 x i16> @shrn8h(ptr %ret, ptr %A) nounwind {
1405 ; CHECK-LABEL: shrn8h:
1406 ; CHECK: // %bb.0:
1407 ; CHECK-NEXT: ldr d0, [x0]
1408 ; CHECK-NEXT: ldr q1, [x1]
1409 ; CHECK-NEXT: shrn2.8h v0, v1, #1
1410 ; CHECK-NEXT: ret
1411 %out = load <4 x i16>, ptr %ret
1412 %tmp1 = load <4 x i32>, ptr %A
1413 %tmp2 = lshr <4 x i32> %tmp1, <i32 1, i32 1, i32 1, i32 1>
1414 %tmp3 = trunc <4 x i32> %tmp2 to <4 x i16>
1415 %tmp4 = shufflevector <4 x i16> %out, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
1416 ret <8 x i16> %tmp4
1417 }
1419 define <4 x i32> @shrn4s(ptr %ret, ptr %A) nounwind {
1420 ; CHECK-LABEL: shrn4s:
1421 ; CHECK: // %bb.0:
1422 ; CHECK-NEXT: ldr d0, [x0]
1423 ; CHECK-NEXT: ldr q1, [x1]
1424 ; CHECK-NEXT: shrn2.4s v0, v1, #1
1425 ; CHECK-NEXT: ret
1426 %out = load <2 x i32>, ptr %ret
1427 %tmp1 = load <2 x i64>, ptr %A
1428 %tmp2 = lshr <2 x i64> %tmp1, <i64 1, i64 1>
1429 %tmp3 = trunc <2 x i64> %tmp2 to <2 x i32>
1430 %tmp4 = shufflevector <2 x i32> %out, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
1431 ret <4 x i32> %tmp4
1432 }
1434 declare <8 x i8> @llvm.aarch64.neon.shrn.v8i8(<8 x i16>, i32) nounwind readnone
1435 declare <4 x i16> @llvm.aarch64.neon.shrn.v4i16(<4 x i32>, i32) nounwind readnone
1436 declare <2 x i32> @llvm.aarch64.neon.shrn.v2i32(<2 x i64>, i32) nounwind readnone
1438 define i32 @sqshrn1s(i64 %A) nounwind {
1439 ; CHECK-LABEL: sqshrn1s:
1440 ; CHECK: // %bb.0:
1441 ; CHECK-NEXT: fmov d0, x0
1442 ; CHECK-NEXT: sqshrn s0, d0, #1
1443 ; CHECK-NEXT: fmov w0, s0
1444 ; CHECK-NEXT: ret
1445 %tmp = call i32 @llvm.aarch64.neon.sqshrn.i32(i64 %A, i32 1)
1446 ret i32 %tmp
1447 }
1449 define <8 x i8> @sqshrn8b(ptr %A) nounwind {
1450 ; CHECK-LABEL: sqshrn8b:
1451 ; CHECK: // %bb.0:
1452 ; CHECK-NEXT: ldr q0, [x0]
1453 ; CHECK-NEXT: sqshrn.8b v0, v0, #1
1454 ; CHECK-NEXT: ret
1455 %tmp1 = load <8 x i16>, ptr %A
1456 %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqshrn.v8i8(<8 x i16> %tmp1, i32 1)
1457 ret <8 x i8> %tmp3
1458 }
1460 define <4 x i16> @sqshrn4h(ptr %A) nounwind {
1461 ; CHECK-LABEL: sqshrn4h:
1462 ; CHECK: // %bb.0:
1463 ; CHECK-NEXT: ldr q0, [x0]
1464 ; CHECK-NEXT: sqshrn.4h v0, v0, #1
1465 ; CHECK-NEXT: ret
1466 %tmp1 = load <4 x i32>, ptr %A
1467 %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqshrn.v4i16(<4 x i32> %tmp1, i32 1)
1468 ret <4 x i16> %tmp3
1469 }
1471 define <2 x i32> @sqshrn2s(ptr %A) nounwind {
1472 ; CHECK-LABEL: sqshrn2s:
1473 ; CHECK: // %bb.0:
1474 ; CHECK-NEXT: ldr q0, [x0]
1475 ; CHECK-NEXT: sqshrn.2s v0, v0, #1
1476 ; CHECK-NEXT: ret
1477 %tmp1 = load <2 x i64>, ptr %A
1478 %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqshrn.v2i32(<2 x i64> %tmp1, i32 1)
1479 ret <2 x i32> %tmp3
1480 }
1483 define <16 x i8> @sqshrn16b(ptr %ret, ptr %A) nounwind {
1484 ; CHECK-LABEL: sqshrn16b:
1485 ; CHECK: // %bb.0:
1486 ; CHECK-NEXT: ldr d0, [x0]
1487 ; CHECK-NEXT: ldr q1, [x1]
1488 ; CHECK-NEXT: sqshrn2.16b v0, v1, #1
1489 ; CHECK-NEXT: ret
1490 %out = load <8 x i8>, ptr %ret
1491 %tmp1 = load <8 x i16>, ptr %A
1492 %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqshrn.v8i8(<8 x i16> %tmp1, i32 1)
1493 %tmp4 = shufflevector <8 x i8> %out, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
1494 ret <16 x i8> %tmp4
1495 }
1497 define <8 x i16> @sqshrn8h(ptr %ret, ptr %A) nounwind {
1498 ; CHECK-LABEL: sqshrn8h:
1499 ; CHECK: // %bb.0:
1500 ; CHECK-NEXT: ldr d0, [x0]
1501 ; CHECK-NEXT: ldr q1, [x1]
1502 ; CHECK-NEXT: sqshrn2.8h v0, v1, #1
1503 ; CHECK-NEXT: ret
1504 %out = load <4 x i16>, ptr %ret
1505 %tmp1 = load <4 x i32>, ptr %A
1506 %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqshrn.v4i16(<4 x i32> %tmp1, i32 1)
1507 %tmp4 = shufflevector <4 x i16> %out, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
1508 ret <8 x i16> %tmp4
1509 }
1511 define <4 x i32> @sqshrn4s(ptr %ret, ptr %A) nounwind {
1512 ; CHECK-LABEL: sqshrn4s:
1513 ; CHECK: // %bb.0:
1514 ; CHECK-NEXT: ldr d0, [x0]
1515 ; CHECK-NEXT: ldr q1, [x1]
1516 ; CHECK-NEXT: sqshrn2.4s v0, v1, #1
1517 ; CHECK-NEXT: ret
1518 %out = load <2 x i32>, ptr %ret
1519 %tmp1 = load <2 x i64>, ptr %A
1520 %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqshrn.v2i32(<2 x i64> %tmp1, i32 1)
1521 %tmp4 = shufflevector <2 x i32> %out, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
1522 ret <4 x i32> %tmp4
1523 }
1525 declare i32 @llvm.aarch64.neon.sqshrn.i32(i64, i32) nounwind readnone
1526 declare <8 x i8> @llvm.aarch64.neon.sqshrn.v8i8(<8 x i16>, i32) nounwind readnone
1527 declare <4 x i16> @llvm.aarch64.neon.sqshrn.v4i16(<4 x i32>, i32) nounwind readnone
1528 declare <2 x i32> @llvm.aarch64.neon.sqshrn.v2i32(<2 x i64>, i32) nounwind readnone
1530 define i32 @sqshrun1s(i64 %A) nounwind {
1531 ; CHECK-LABEL: sqshrun1s:
1532 ; CHECK: // %bb.0:
1533 ; CHECK-NEXT: fmov d0, x0
1534 ; CHECK-NEXT: sqshrun s0, d0, #1
1535 ; CHECK-NEXT: fmov w0, s0
1536 ; CHECK-NEXT: ret
1537 %tmp = call i32 @llvm.aarch64.neon.sqshrun.i32(i64 %A, i32 1)
1538 ret i32 %tmp
1539 }
1541 define <8 x i8> @sqshrun8b(ptr %A) nounwind {
1542 ; CHECK-LABEL: sqshrun8b:
1543 ; CHECK: // %bb.0:
1544 ; CHECK-NEXT: ldr q0, [x0]
1545 ; CHECK-NEXT: sqshrun.8b v0, v0, #1
1546 ; CHECK-NEXT: ret
1547 %tmp1 = load <8 x i16>, ptr %A
1548 %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqshrun.v8i8(<8 x i16> %tmp1, i32 1)
1549 ret <8 x i8> %tmp3
1550 }
1552 define <4 x i16> @sqshrun4h(ptr %A) nounwind {
1553 ; CHECK-LABEL: sqshrun4h:
1554 ; CHECK: // %bb.0:
1555 ; CHECK-NEXT: ldr q0, [x0]
1556 ; CHECK-NEXT: sqshrun.4h v0, v0, #1
1557 ; CHECK-NEXT: ret
1558 %tmp1 = load <4 x i32>, ptr %A
1559 %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqshrun.v4i16(<4 x i32> %tmp1, i32 1)
1560 ret <4 x i16> %tmp3
1561 }
1563 define <2 x i32> @sqshrun2s(ptr %A) nounwind {
1564 ; CHECK-LABEL: sqshrun2s:
1565 ; CHECK: // %bb.0:
1566 ; CHECK-NEXT: ldr q0, [x0]
1567 ; CHECK-NEXT: sqshrun.2s v0, v0, #1
1568 ; CHECK-NEXT: ret
1569 %tmp1 = load <2 x i64>, ptr %A
1570 %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqshrun.v2i32(<2 x i64> %tmp1, i32 1)
1571 ret <2 x i32> %tmp3
1572 }
1574 define <16 x i8> @sqshrun16b(ptr %ret, ptr %A) nounwind {
1575 ; CHECK-LABEL: sqshrun16b:
1576 ; CHECK: // %bb.0:
1577 ; CHECK-NEXT: ldr d0, [x0]
1578 ; CHECK-NEXT: ldr q1, [x1]
1579 ; CHECK-NEXT: sqshrun2.16b v0, v1, #1
1580 ; CHECK-NEXT: ret
1581 %out = load <8 x i8>, ptr %ret
1582 %tmp1 = load <8 x i16>, ptr %A
1583 %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqshrun.v8i8(<8 x i16> %tmp1, i32 1)
1584 %tmp4 = shufflevector <8 x i8> %out, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
1585 ret <16 x i8> %tmp4
1586 }
1588 define <8 x i16> @sqshrun8h(ptr %ret, ptr %A) nounwind {
1589 ; CHECK-LABEL: sqshrun8h:
1590 ; CHECK: // %bb.0:
1591 ; CHECK-NEXT: ldr d0, [x0]
1592 ; CHECK-NEXT: ldr q1, [x1]
1593 ; CHECK-NEXT: sqshrun2.8h v0, v1, #1
1594 ; CHECK-NEXT: ret
1595 %out = load <4 x i16>, ptr %ret
1596 %tmp1 = load <4 x i32>, ptr %A
1597 %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqshrun.v4i16(<4 x i32> %tmp1, i32 1)
1598 %tmp4 = shufflevector <4 x i16> %out, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
1599 ret <8 x i16> %tmp4
1600 }
1602 define <4 x i32> @sqshrun4s(ptr %ret, ptr %A) nounwind {
1603 ; CHECK-LABEL: sqshrun4s:
1604 ; CHECK: // %bb.0:
1605 ; CHECK-NEXT: ldr d0, [x0]
1606 ; CHECK-NEXT: ldr q1, [x1]
1607 ; CHECK-NEXT: sqshrun2.4s v0, v1, #1
1608 ; CHECK-NEXT: ret
1609 %out = load <2 x i32>, ptr %ret
1610 %tmp1 = load <2 x i64>, ptr %A
1611 %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqshrun.v2i32(<2 x i64> %tmp1, i32 1)
1612 %tmp4 = shufflevector <2 x i32> %out, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
1613 ret <4 x i32> %tmp4
1614 }
1616 declare i32 @llvm.aarch64.neon.sqshrun.i32(i64, i32) nounwind readnone
1617 declare <8 x i8> @llvm.aarch64.neon.sqshrun.v8i8(<8 x i16>, i32) nounwind readnone
1618 declare <4 x i16> @llvm.aarch64.neon.sqshrun.v4i16(<4 x i32>, i32) nounwind readnone
1619 declare <2 x i32> @llvm.aarch64.neon.sqshrun.v2i32(<2 x i64>, i32) nounwind readnone
1621 define i32 @sqrshrn1s(i64 %A) nounwind {
1622 ; CHECK-LABEL: sqrshrn1s:
1623 ; CHECK: // %bb.0:
1624 ; CHECK-NEXT: fmov d0, x0
1625 ; CHECK-NEXT: sqrshrn s0, d0, #1
1626 ; CHECK-NEXT: fmov w0, s0
1627 ; CHECK-NEXT: ret
1628 %tmp = call i32 @llvm.aarch64.neon.sqrshrn.i32(i64 %A, i32 1)
1629 ret i32 %tmp
1630 }
1632 define <8 x i8> @sqrshrn8b(ptr %A) nounwind {
1633 ; CHECK-LABEL: sqrshrn8b:
1634 ; CHECK: // %bb.0:
1635 ; CHECK-NEXT: ldr q0, [x0]
1636 ; CHECK-NEXT: sqrshrn.8b v0, v0, #1
1637 ; CHECK-NEXT: ret
1638 %tmp1 = load <8 x i16>, ptr %A
1639 %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqrshrn.v8i8(<8 x i16> %tmp1, i32 1)
1640 ret <8 x i8> %tmp3
1641 }
1643 define <4 x i16> @sqrshrn4h(ptr %A) nounwind {
1644 ; CHECK-LABEL: sqrshrn4h:
1645 ; CHECK: // %bb.0:
1646 ; CHECK-NEXT: ldr q0, [x0]
1647 ; CHECK-NEXT: sqrshrn.4h v0, v0, #1
1648 ; CHECK-NEXT: ret
1649 %tmp1 = load <4 x i32>, ptr %A
1650 %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqrshrn.v4i16(<4 x i32> %tmp1, i32 1)
1651 ret <4 x i16> %tmp3
1652 }
1654 define <2 x i32> @sqrshrn2s(ptr %A) nounwind {
1655 ; CHECK-LABEL: sqrshrn2s:
1656 ; CHECK: // %bb.0:
1657 ; CHECK-NEXT: ldr q0, [x0]
1658 ; CHECK-NEXT: sqrshrn.2s v0, v0, #1
1659 ; CHECK-NEXT: ret
1660 %tmp1 = load <2 x i64>, ptr %A
1661 %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqrshrn.v2i32(<2 x i64> %tmp1, i32 1)
1662 ret <2 x i32> %tmp3
1663 }
1665 define <16 x i8> @sqrshrn16b(ptr %ret, ptr %A) nounwind {
1666 ; CHECK-LABEL: sqrshrn16b:
1667 ; CHECK: // %bb.0:
1668 ; CHECK-NEXT: ldr d0, [x0]
1669 ; CHECK-NEXT: ldr q1, [x1]
1670 ; CHECK-NEXT: sqrshrn2.16b v0, v1, #1
1671 ; CHECK-NEXT: ret
1672 %out = load <8 x i8>, ptr %ret
1673 %tmp1 = load <8 x i16>, ptr %A
1674 %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqrshrn.v8i8(<8 x i16> %tmp1, i32 1)
1675 %tmp4 = shufflevector <8 x i8> %out, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
1676 ret <16 x i8> %tmp4
1677 }
1679 define <8 x i16> @sqrshrn8h(ptr %ret, ptr %A) nounwind {
1680 ; CHECK-LABEL: sqrshrn8h:
1681 ; CHECK: // %bb.0:
1682 ; CHECK-NEXT: ldr d0, [x0]
1683 ; CHECK-NEXT: ldr q1, [x1]
1684 ; CHECK-NEXT: sqrshrn2.8h v0, v1, #1
1685 ; CHECK-NEXT: ret
1686 %out = load <4 x i16>, ptr %ret
1687 %tmp1 = load <4 x i32>, ptr %A
1688 %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqrshrn.v4i16(<4 x i32> %tmp1, i32 1)
1689 %tmp4 = shufflevector <4 x i16> %out, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
1690 ret <8 x i16> %tmp4
1691 }
1693 define <4 x i32> @sqrshrn4s(ptr %ret, ptr %A) nounwind {
1694 ; CHECK-LABEL: sqrshrn4s:
1695 ; CHECK: // %bb.0:
1696 ; CHECK-NEXT: ldr d0, [x0]
1697 ; CHECK-NEXT: ldr q1, [x1]
1698 ; CHECK-NEXT: sqrshrn2.4s v0, v1, #1
1699 ; CHECK-NEXT: ret
1700 %out = load <2 x i32>, ptr %ret
1701 %tmp1 = load <2 x i64>, ptr %A
1702 %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqrshrn.v2i32(<2 x i64> %tmp1, i32 1)
1703 %tmp4 = shufflevector <2 x i32> %out, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
1704 ret <4 x i32> %tmp4
1705 }
1707 declare i32 @llvm.aarch64.neon.sqrshrn.i32(i64, i32) nounwind readnone
1708 declare <8 x i8> @llvm.aarch64.neon.sqrshrn.v8i8(<8 x i16>, i32) nounwind readnone
1709 declare <4 x i16> @llvm.aarch64.neon.sqrshrn.v4i16(<4 x i32>, i32) nounwind readnone
1710 declare <2 x i32> @llvm.aarch64.neon.sqrshrn.v2i32(<2 x i64>, i32) nounwind readnone
1712 define i32 @sqrshrun1s(i64 %A) nounwind {
1713 ; CHECK-LABEL: sqrshrun1s:
1714 ; CHECK: // %bb.0:
1715 ; CHECK-NEXT: fmov d0, x0
1716 ; CHECK-NEXT: sqrshrun s0, d0, #1
1717 ; CHECK-NEXT: fmov w0, s0
1718 ; CHECK-NEXT: ret
1719 %tmp = call i32 @llvm.aarch64.neon.sqrshrun.i32(i64 %A, i32 1)
1720 ret i32 %tmp
1721 }
1723 define <8 x i8> @sqrshrun8b(ptr %A) nounwind {
1724 ; CHECK-LABEL: sqrshrun8b:
1725 ; CHECK: // %bb.0:
1726 ; CHECK-NEXT: ldr q0, [x0]
1727 ; CHECK-NEXT: sqrshrun.8b v0, v0, #1
1728 ; CHECK-NEXT: ret
1729 %tmp1 = load <8 x i16>, ptr %A
1730 %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqrshrun.v8i8(<8 x i16> %tmp1, i32 1)
1731 ret <8 x i8> %tmp3
1732 }
1734 define <4 x i16> @sqrshrun4h(ptr %A) nounwind {
1735 ; CHECK-LABEL: sqrshrun4h:
1736 ; CHECK: // %bb.0:
1737 ; CHECK-NEXT: ldr q0, [x0]
1738 ; CHECK-NEXT: sqrshrun.4h v0, v0, #1
1739 ; CHECK-NEXT: ret
1740 %tmp1 = load <4 x i32>, ptr %A
1741 %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqrshrun.v4i16(<4 x i32> %tmp1, i32 1)
1742 ret <4 x i16> %tmp3
1743 }
1745 define <2 x i32> @sqrshrun2s(ptr %A) nounwind {
1746 ; CHECK-LABEL: sqrshrun2s:
1747 ; CHECK: // %bb.0:
1748 ; CHECK-NEXT: ldr q0, [x0]
1749 ; CHECK-NEXT: sqrshrun.2s v0, v0, #1
1750 ; CHECK-NEXT: ret
1751 %tmp1 = load <2 x i64>, ptr %A
1752 %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqrshrun.v2i32(<2 x i64> %tmp1, i32 1)
1753 ret <2 x i32> %tmp3
1754 }
1756 define <16 x i8> @sqrshrun16b(ptr %ret, ptr %A) nounwind {
1757 ; CHECK-LABEL: sqrshrun16b:
1758 ; CHECK: // %bb.0:
1759 ; CHECK-NEXT: ldr d0, [x0]
1760 ; CHECK-NEXT: ldr q1, [x1]
1761 ; CHECK-NEXT: sqrshrun2.16b v0, v1, #1
1762 ; CHECK-NEXT: ret
1763 %out = load <8 x i8>, ptr %ret
1764 %tmp1 = load <8 x i16>, ptr %A
1765 %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqrshrun.v8i8(<8 x i16> %tmp1, i32 1)
1766 %tmp4 = shufflevector <8 x i8> %out, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
1767 ret <16 x i8> %tmp4
1768 }
1770 define <8 x i16> @sqrshrun8h(ptr %ret, ptr %A) nounwind {
1771 ; CHECK-LABEL: sqrshrun8h:
1772 ; CHECK: // %bb.0:
1773 ; CHECK-NEXT: ldr d0, [x0]
1774 ; CHECK-NEXT: ldr q1, [x1]
1775 ; CHECK-NEXT: sqrshrun2.8h v0, v1, #1
1776 ; CHECK-NEXT: ret
1777 %out = load <4 x i16>, ptr %ret
1778 %tmp1 = load <4 x i32>, ptr %A
1779 %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqrshrun.v4i16(<4 x i32> %tmp1, i32 1)
1780 %tmp4 = shufflevector <4 x i16> %out, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
1781 ret <8 x i16> %tmp4
1782 }
1784 define <4 x i32> @sqrshrun4s(ptr %ret, ptr %A) nounwind {
1785 ; CHECK-LABEL: sqrshrun4s:
1786 ; CHECK: // %bb.0:
1787 ; CHECK-NEXT: ldr d0, [x0]
1788 ; CHECK-NEXT: ldr q1, [x1]
1789 ; CHECK-NEXT: sqrshrun2.4s v0, v1, #1
1790 ; CHECK-NEXT: ret
1791 %out = load <2 x i32>, ptr %ret
1792 %tmp1 = load <2 x i64>, ptr %A
1793 %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqrshrun.v2i32(<2 x i64> %tmp1, i32 1)
1794 %tmp4 = shufflevector <2 x i32> %out, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
1795 ret <4 x i32> %tmp4
1796 }
1798 declare i32 @llvm.aarch64.neon.sqrshrun.i32(i64, i32) nounwind readnone
1799 declare <8 x i8> @llvm.aarch64.neon.sqrshrun.v8i8(<8 x i16>, i32) nounwind readnone
1800 declare <4 x i16> @llvm.aarch64.neon.sqrshrun.v4i16(<4 x i32>, i32) nounwind readnone
1801 declare <2 x i32> @llvm.aarch64.neon.sqrshrun.v2i32(<2 x i64>, i32) nounwind readnone
1803 define i32 @uqrshrn1s(i64 %A) nounwind {
1804 ; CHECK-LABEL: uqrshrn1s:
1805 ; CHECK: // %bb.0:
1806 ; CHECK-NEXT: fmov d0, x0
1807 ; CHECK-NEXT: uqrshrn s0, d0, #1
1808 ; CHECK-NEXT: fmov w0, s0
1809 ; CHECK-NEXT: ret
1810 %tmp = call i32 @llvm.aarch64.neon.uqrshrn.i32(i64 %A, i32 1)
1811 ret i32 %tmp
1812 }
1814 define <8 x i8> @uqrshrn8b(ptr %A) nounwind {
1815 ; CHECK-LABEL: uqrshrn8b:
1816 ; CHECK: // %bb.0:
1817 ; CHECK-NEXT: ldr q0, [x0]
1818 ; CHECK-NEXT: uqrshrn.8b v0, v0, #1
1819 ; CHECK-NEXT: ret
1820 %tmp1 = load <8 x i16>, ptr %A
1821 %tmp3 = call <8 x i8> @llvm.aarch64.neon.uqrshrn.v8i8(<8 x i16> %tmp1, i32 1)
1822 ret <8 x i8> %tmp3
1823 }
1825 define <4 x i16> @uqrshrn4h(ptr %A) nounwind {
1826 ; CHECK-LABEL: uqrshrn4h:
1827 ; CHECK: // %bb.0:
1828 ; CHECK-NEXT: ldr q0, [x0]
1829 ; CHECK-NEXT: uqrshrn.4h v0, v0, #1
1830 ; CHECK-NEXT: ret
1831 %tmp1 = load <4 x i32>, ptr %A
1832 %tmp3 = call <4 x i16> @llvm.aarch64.neon.uqrshrn.v4i16(<4 x i32> %tmp1, i32 1)
1833 ret <4 x i16> %tmp3
1834 }
1836 define <2 x i32> @uqrshrn2s(ptr %A) nounwind {
1837 ; CHECK-LABEL: uqrshrn2s:
1838 ; CHECK: // %bb.0:
1839 ; CHECK-NEXT: ldr q0, [x0]
1840 ; CHECK-NEXT: uqrshrn.2s v0, v0, #1
1841 ; CHECK-NEXT: ret
1842 %tmp1 = load <2 x i64>, ptr %A
1843 %tmp3 = call <2 x i32> @llvm.aarch64.neon.uqrshrn.v2i32(<2 x i64> %tmp1, i32 1)
1844 ret <2 x i32> %tmp3
1845 }
1847 define <16 x i8> @uqrshrn16b(ptr %ret, ptr %A) nounwind {
1848 ; CHECK-LABEL: uqrshrn16b:
1849 ; CHECK: // %bb.0:
1850 ; CHECK-NEXT: ldr d0, [x0]
1851 ; CHECK-NEXT: ldr q1, [x1]
1852 ; CHECK-NEXT: uqrshrn2.16b v0, v1, #1
1853 ; CHECK-NEXT: ret
1854 %out = load <8 x i8>, ptr %ret
1855 %tmp1 = load <8 x i16>, ptr %A
1856 %tmp3 = call <8 x i8> @llvm.aarch64.neon.uqrshrn.v8i8(<8 x i16> %tmp1, i32 1)
1857 %tmp4 = shufflevector <8 x i8> %out, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
1858 ret <16 x i8> %tmp4
1859 }
1861 define <8 x i16> @uqrshrn8h(ptr %ret, ptr %A) nounwind {
1862 ; CHECK-LABEL: uqrshrn8h:
1863 ; CHECK: // %bb.0:
1864 ; CHECK-NEXT: ldr d0, [x0]
1865 ; CHECK-NEXT: ldr q1, [x1]
1866 ; CHECK-NEXT: uqrshrn2.8h v0, v1, #1
1867 ; CHECK-NEXT: ret
1868 %out = load <4 x i16>, ptr %ret
1869 %tmp1 = load <4 x i32>, ptr %A
1870 %tmp3 = call <4 x i16> @llvm.aarch64.neon.uqrshrn.v4i16(<4 x i32> %tmp1, i32 1)
1871 %tmp4 = shufflevector <4 x i16> %out, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
1872 ret <8 x i16> %tmp4
1873 }
1875 define <4 x i32> @uqrshrn4s(ptr %ret, ptr %A) nounwind {
1876 ; CHECK-LABEL: uqrshrn4s:
1877 ; CHECK: // %bb.0:
1878 ; CHECK-NEXT: ldr d0, [x0]
1879 ; CHECK-NEXT: ldr q1, [x1]
1880 ; CHECK-NEXT: uqrshrn2.4s v0, v1, #1
1881 ; CHECK-NEXT: ret
1882 %out = load <2 x i32>, ptr %ret
1883 %tmp1 = load <2 x i64>, ptr %A
1884 %tmp3 = call <2 x i32> @llvm.aarch64.neon.uqrshrn.v2i32(<2 x i64> %tmp1, i32 1)
1885 %tmp4 = shufflevector <2 x i32> %out, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
1886 ret <4 x i32> %tmp4
1887 }
1889 declare i32 @llvm.aarch64.neon.uqrshrn.i32(i64, i32) nounwind readnone
1890 declare <8 x i8> @llvm.aarch64.neon.uqrshrn.v8i8(<8 x i16>, i32) nounwind readnone
1891 declare <4 x i16> @llvm.aarch64.neon.uqrshrn.v4i16(<4 x i32>, i32) nounwind readnone
1892 declare <2 x i32> @llvm.aarch64.neon.uqrshrn.v2i32(<2 x i64>, i32) nounwind readnone
1894 define i32 @uqshrn1s(i64 %A) nounwind {
1895 ; CHECK-LABEL: uqshrn1s:
1896 ; CHECK: // %bb.0:
1897 ; CHECK-NEXT: fmov d0, x0
1898 ; CHECK-NEXT: uqshrn s0, d0, #1
1899 ; CHECK-NEXT: fmov w0, s0
1900 ; CHECK-NEXT: ret
1901 %tmp = call i32 @llvm.aarch64.neon.uqshrn.i32(i64 %A, i32 1)
1902 ret i32 %tmp
1903 }
1905 define <8 x i8> @uqshrn8b(ptr %A) nounwind {
1906 ; CHECK-LABEL: uqshrn8b:
1907 ; CHECK: // %bb.0:
1908 ; CHECK-NEXT: ldr q0, [x0]
1909 ; CHECK-NEXT: uqshrn.8b v0, v0, #1
1910 ; CHECK-NEXT: ret
1911 %tmp1 = load <8 x i16>, ptr %A
1912 %tmp3 = call <8 x i8> @llvm.aarch64.neon.uqshrn.v8i8(<8 x i16> %tmp1, i32 1)
1913 ret <8 x i8> %tmp3
1914 }
1916 define <4 x i16> @uqshrn4h(ptr %A) nounwind {
1917 ; CHECK-LABEL: uqshrn4h:
1918 ; CHECK: // %bb.0:
1919 ; CHECK-NEXT: ldr q0, [x0]
1920 ; CHECK-NEXT: uqshrn.4h v0, v0, #1
1921 ; CHECK-NEXT: ret
1922 %tmp1 = load <4 x i32>, ptr %A
1923 %tmp3 = call <4 x i16> @llvm.aarch64.neon.uqshrn.v4i16(<4 x i32> %tmp1, i32 1)
1924 ret <4 x i16> %tmp3
1925 }
1927 define <2 x i32> @uqshrn2s(ptr %A) nounwind {
1928 ; CHECK-LABEL: uqshrn2s:
1929 ; CHECK: // %bb.0:
1930 ; CHECK-NEXT: ldr q0, [x0]
1931 ; CHECK-NEXT: uqshrn.2s v0, v0, #1
1932 ; CHECK-NEXT: ret
1933 %tmp1 = load <2 x i64>, ptr %A
1934 %tmp3 = call <2 x i32> @llvm.aarch64.neon.uqshrn.v2i32(<2 x i64> %tmp1, i32 1)
1935 ret <2 x i32> %tmp3
1936 }
1938 define <16 x i8> @uqshrn16b(ptr %ret, ptr %A) nounwind {
1939 ; CHECK-LABEL: uqshrn16b:
1940 ; CHECK: // %bb.0:
1941 ; CHECK-NEXT: ldr d0, [x0]
1942 ; CHECK-NEXT: ldr q1, [x1]
1943 ; CHECK-NEXT: uqshrn2.16b v0, v1, #1
1944 ; CHECK-NEXT: ret
1945 %out = load <8 x i8>, ptr %ret
1946 %tmp1 = load <8 x i16>, ptr %A
1947 %tmp3 = call <8 x i8> @llvm.aarch64.neon.uqshrn.v8i8(<8 x i16> %tmp1, i32 1)
1948 %tmp4 = shufflevector <8 x i8> %out, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
1949 ret <16 x i8> %tmp4
1950 }
1952 define <8 x i16> @uqshrn8h(ptr %ret, ptr %A) nounwind {
1953 ; CHECK-LABEL: uqshrn8h:
1954 ; CHECK: // %bb.0:
1955 ; CHECK-NEXT: ldr d0, [x0]
1956 ; CHECK-NEXT: ldr q1, [x1]
1957 ; CHECK-NEXT: uqshrn2.8h v0, v1, #1
1958 ; CHECK-NEXT: ret
1959 %out = load <4 x i16>, ptr %ret
1960 %tmp1 = load <4 x i32>, ptr %A
1961 %tmp3 = call <4 x i16> @llvm.aarch64.neon.uqshrn.v4i16(<4 x i32> %tmp1, i32 1)
1962 %tmp4 = shufflevector <4 x i16> %out, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
1963 ret <8 x i16> %tmp4
1964 }
1966 define <4 x i32> @uqshrn4s(ptr %ret, ptr %A) nounwind {
1967 ; CHECK-LABEL: uqshrn4s:
1968 ; CHECK: // %bb.0:
1969 ; CHECK-NEXT: ldr d0, [x0]
1970 ; CHECK-NEXT: ldr q1, [x1]
1971 ; CHECK-NEXT: uqshrn2.4s v0, v1, #1
1972 ; CHECK-NEXT: ret
1973 %out = load <2 x i32>, ptr %ret
1974 %tmp1 = load <2 x i64>, ptr %A
1975 %tmp3 = call <2 x i32> @llvm.aarch64.neon.uqshrn.v2i32(<2 x i64> %tmp1, i32 1)
1976 %tmp4 = shufflevector <2 x i32> %out, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
1977 ret <4 x i32> %tmp4
1978 }
1980 declare i32 @llvm.aarch64.neon.uqshrn.i32(i64, i32) nounwind readnone
1981 declare <8 x i8> @llvm.aarch64.neon.uqshrn.v8i8(<8 x i16>, i32) nounwind readnone
1982 declare <4 x i16> @llvm.aarch64.neon.uqshrn.v4i16(<4 x i32>, i32) nounwind readnone
1983 declare <2 x i32> @llvm.aarch64.neon.uqshrn.v2i32(<2 x i64>, i32) nounwind readnone
1985 define <8 x i16> @ushll8h(ptr %A) nounwind {
1986 ; CHECK-LABEL: ushll8h:
1987 ; CHECK: // %bb.0:
1988 ; CHECK-NEXT: ldr d0, [x0]
1989 ; CHECK-NEXT: ushll.8h v0, v0, #1
1990 ; CHECK-NEXT: ret
1991 %tmp1 = load <8 x i8>, ptr %A
1992 %tmp2 = zext <8 x i8> %tmp1 to <8 x i16>
1993 %tmp3 = shl <8 x i16> %tmp2, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
1994 ret <8 x i16> %tmp3
1995 }
1997 define <4 x i32> @ushll4s(ptr %A) nounwind {
1998 ; CHECK-LABEL: ushll4s:
1999 ; CHECK: // %bb.0:
2000 ; CHECK-NEXT: ldr d0, [x0]
2001 ; CHECK-NEXT: ushll.4s v0, v0, #1
2002 ; CHECK-NEXT: ret
2003 %tmp1 = load <4 x i16>, ptr %A
2004 %tmp2 = zext <4 x i16> %tmp1 to <4 x i32>
2005 %tmp3 = shl <4 x i32> %tmp2, <i32 1, i32 1, i32 1, i32 1>
2006 ret <4 x i32> %tmp3
2007 }
2009 define <2 x i64> @ushll2d(ptr %A) nounwind {
2010 ; CHECK-LABEL: ushll2d:
2011 ; CHECK: // %bb.0:
2012 ; CHECK-NEXT: ldr d0, [x0]
2013 ; CHECK-NEXT: ushll.2d v0, v0, #1
2014 ; CHECK-NEXT: ret
2015 %tmp1 = load <2 x i32>, ptr %A
2016 %tmp2 = zext <2 x i32> %tmp1 to <2 x i64>
2017 %tmp3 = shl <2 x i64> %tmp2, <i64 1, i64 1>
2018 ret <2 x i64> %tmp3
2019 }
2021 define <8 x i16> @ushll2_8h(ptr %A) nounwind {
2022 ; CHECK-LABEL: ushll2_8h:
2023 ; CHECK: // %bb.0:
2024 ; CHECK-NEXT: ldr d0, [x0, #8]
2025 ; CHECK-NEXT: ushll.8h v0, v0, #1
2026 ; CHECK-NEXT: ret
2027 %load1 = load <16 x i8>, ptr %A
2028 %tmp1 = shufflevector <16 x i8> %load1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
2029 %tmp2 = zext <8 x i8> %tmp1 to <8 x i16>
2030 %tmp3 = shl <8 x i16> %tmp2, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
2031 ret <8 x i16> %tmp3
2032 }
2034 define <4 x i32> @ushll2_4s(ptr %A) nounwind {
2035 ; CHECK-LABEL: ushll2_4s:
2036 ; CHECK: // %bb.0:
2037 ; CHECK-NEXT: ldr d0, [x0, #8]
2038 ; CHECK-NEXT: ushll.4s v0, v0, #1
2039 ; CHECK-NEXT: ret
2040 %load1 = load <8 x i16>, ptr %A
2041 %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
2042 %tmp2 = zext <4 x i16> %tmp1 to <4 x i32>
2043 %tmp3 = shl <4 x i32> %tmp2, <i32 1, i32 1, i32 1, i32 1>
2044 ret <4 x i32> %tmp3
2045 }
2047 define <2 x i64> @ushll2_2d(ptr %A) nounwind {
2048 ; CHECK-LABEL: ushll2_2d:
2049 ; CHECK: // %bb.0:
2050 ; CHECK-NEXT: ldr d0, [x0, #8]
2051 ; CHECK-NEXT: ushll.2d v0, v0, #1
2052 ; CHECK-NEXT: ret
2053 %load1 = load <4 x i32>, ptr %A
2054 %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
2055 %tmp2 = zext <2 x i32> %tmp1 to <2 x i64>
2056 %tmp3 = shl <2 x i64> %tmp2, <i64 1, i64 1>
2057 ret <2 x i64> %tmp3
2058 }
2060 declare <16 x i8> @llvm.aarch64.neon.ushl.v16i8(<16 x i8>, <16 x i8>)
2061 declare <8 x i16> @llvm.aarch64.neon.ushl.v8i16(<8 x i16>, <8 x i16>)
2062 declare <4 x i32> @llvm.aarch64.neon.ushl.v4i32(<4 x i32>, <4 x i32>)
2063 declare <2 x i64> @llvm.aarch64.neon.ushl.v2i64(<2 x i64>, <2 x i64>)
2064 declare <1 x i64> @llvm.aarch64.neon.ushl.v1i64(<1 x i64>, <1 x i64>)
2065 declare i64 @llvm.aarch64.neon.ushl.i64(i64, i64)
2067 define <8 x i16> @neon.ushll8h_constant_shift(ptr %A) nounwind {
2068 ; CHECK-LABEL: neon.ushll8h_constant_shift:
2069 ; CHECK: // %bb.0:
2070 ; CHECK-NEXT: ldr d0, [x0]
2071 ; CHECK-NEXT: ushll.8h v0, v0, #1
2072 ; CHECK-NEXT: ret
2073 %tmp1 = load <8 x i8>, ptr %A
2074 %tmp2 = zext <8 x i8> %tmp1 to <8 x i16>
2075 %tmp3 = call <8 x i16> @llvm.aarch64.neon.ushl.v8i16(<8 x i16> %tmp2, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)
2076 ret <8 x i16> %tmp3
2077 }
2079 define <8 x i16> @neon.ushl8h_no_constant_shift(ptr %A) nounwind {
2080 ; CHECK-LABEL: neon.ushl8h_no_constant_shift:
2081 ; CHECK: // %bb.0:
2082 ; CHECK-NEXT: ldr d0, [x0]
2083 ; CHECK-NEXT: ushll.8h v0, v0, #0
2084 ; CHECK-NEXT: ushl.8h v0, v0, v0
2085 ; CHECK-NEXT: ret
2086 %tmp1 = load <8 x i8>, ptr %A
2087 %tmp2 = zext <8 x i8> %tmp1 to <8 x i16>
2088 %tmp3 = call <8 x i16> @llvm.aarch64.neon.ushl.v8i16(<8 x i16> %tmp2, <8 x i16> %tmp2)
2089 ret <8 x i16> %tmp3
2090 }
2092 define <4 x i32> @neon.ushl8h_constant_shift_extend_not_2x(ptr %A) nounwind {
2093 ; CHECK-LABEL: neon.ushl8h_constant_shift_extend_not_2x:
2094 ; CHECK: // %bb.0:
2095 ; CHECK-NEXT: ldr s0, [x0]
2096 ; CHECK-NEXT: ushll.8h v0, v0, #0
2097 ; CHECK-NEXT: ushll.4s v0, v0, #1
2098 ; CHECK-NEXT: ret
2099 %tmp1 = load <4 x i8>, ptr %A
2100 %tmp2 = zext <4 x i8> %tmp1 to <4 x i32>
2101 %tmp3 = call <4 x i32> @llvm.aarch64.neon.ushl.v4i32(<4 x i32> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)
2102 ret <4 x i32> %tmp3
2103 }
2105 define <8 x i16> @neon.ushl8_noext_constant_shift(ptr %A) nounwind {
2106 ; CHECK-LABEL: neon.ushl8_noext_constant_shift:
2107 ; CHECK: // %bb.0:
2108 ; CHECK-NEXT: ldr q0, [x0]
2109 ; CHECK-NEXT: add.8h v0, v0, v0
2110 ; CHECK-NEXT: ret
2111 %tmp1 = load <8 x i16>, ptr %A
2112 %tmp3 = call <8 x i16> @llvm.aarch64.neon.ushl.v8i16(<8 x i16> %tmp1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)
2113 ret <8 x i16> %tmp3
2114 }
2116 define <4 x i32> @neon.ushll4s_constant_shift(ptr %A) nounwind {
2117 ; CHECK-LABEL: neon.ushll4s_constant_shift:
2118 ; CHECK: // %bb.0:
2119 ; CHECK-NEXT: ldr d0, [x0]
2120 ; CHECK-NEXT: ushll.4s v0, v0, #1
2121 ; CHECK-NEXT: ret
2122 %tmp1 = load <4 x i16>, ptr %A
2123 %tmp2 = zext <4 x i16> %tmp1 to <4 x i32>
2124 %tmp3 = call <4 x i32> @llvm.aarch64.neon.ushl.v4i32(<4 x i32> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)
2125 ret <4 x i32> %tmp3
2126 }
2128 ; FIXME: unnecessary ushll.4s v0, v0, #0?
2129 define <4 x i32> @neon.ushll4s_neg_constant_shift(ptr %A) nounwind {
2130 ; CHECK-LABEL: neon.ushll4s_neg_constant_shift:
2131 ; CHECK: // %bb.0:
2132 ; CHECK-NEXT: ldr d0, [x0]
2133 ; CHECK-NEXT: ushll.4s v0, v0, #0
2134 ; CHECK-NEXT: ushr.4s v0, v0, #1
2135 ; CHECK-NEXT: ret
2136 %tmp1 = load <4 x i16>, ptr %A
2137 %tmp2 = zext <4 x i16> %tmp1 to <4 x i32>
2138 %tmp3 = call <4 x i32> @llvm.aarch64.neon.ushl.v4i32(<4 x i32> %tmp2, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>)
2139 ret <4 x i32> %tmp3
2140 }
2142 ; FIXME: should be constant folded.
2143 define <4 x i32> @neon.ushll4s_constant_fold() nounwind {
2144 ; CHECK-LABEL: neon.ushll4s_constant_fold:
2145 ; CHECK: // %bb.0:
2146 ; CHECK-NEXT: adrp x8, .LCPI160_0
2147 ; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI160_0]
2148 ; CHECK-NEXT: add.4s v0, v0, v0
2149 ; CHECK-NEXT: ret
2150 %tmp3 = call <4 x i32> @llvm.aarch64.neon.ushl.v4i32(<4 x i32> <i32 0, i32 1, i32 2, i32 3>, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)
2151 ret <4 x i32> %tmp3
2152 }
2154 define <2 x i64> @neon.ushll2d_constant_shift(ptr %A) nounwind {
2155 ; CHECK-LABEL: neon.ushll2d_constant_shift:
2156 ; CHECK: // %bb.0:
2157 ; CHECK-NEXT: ldr d0, [x0]
2158 ; CHECK-NEXT: ushll.2d v0, v0, #1
2159 ; CHECK-NEXT: ret
2160 %tmp1 = load <2 x i32>, ptr %A
2161 %tmp2 = zext <2 x i32> %tmp1 to <2 x i64>
2162 %tmp3 = call <2 x i64> @llvm.aarch64.neon.ushl.v2i64(<2 x i64> %tmp2, <2 x i64> <i64 1, i64 1>)
2163 ret <2 x i64> %tmp3
2164 }
2166 define <1 x i64> @neon.ushl_vscalar_constant_shift(ptr %A) nounwind {
2167 ; CHECK-LABEL: neon.ushl_vscalar_constant_shift:
2168 ; CHECK: // %bb.0:
2169 ; CHECK-NEXT: movi.2d v1, #0000000000000000
2170 ; CHECK-NEXT: ldr s0, [x0]
2171 ; CHECK-NEXT: zip1.2s v0, v0, v1
2172 ; CHECK-NEXT: shl d0, d0, #1
2173 ; CHECK-NEXT: ret
2174 %tmp1 = load <1 x i32>, ptr %A
2175 %tmp2 = zext <1 x i32> %tmp1 to <1 x i64>
2176 %tmp3 = call <1 x i64> @llvm.aarch64.neon.ushl.v1i64(<1 x i64> %tmp2, <1 x i64> <i64 1>)
2177 ret <1 x i64> %tmp3
2178 }
2180 define i64 @neon.ushl_scalar_constant_shift(ptr %A) nounwind {
2181 ; CHECK-LABEL: neon.ushl_scalar_constant_shift:
2182 ; CHECK: // %bb.0:
2183 ; CHECK-NEXT: ldr w8, [x0]
2184 ; CHECK-NEXT: fmov d0, x8
2185 ; CHECK-NEXT: shl d0, d0, #1
2186 ; CHECK-NEXT: fmov x0, d0
2187 ; CHECK-NEXT: ret
2188 %tmp1 = load i32, ptr %A
2189 %tmp2 = zext i32 %tmp1 to i64
2190 %tmp3 = call i64 @llvm.aarch64.neon.ushl.i64(i64 %tmp2, i64 1)
2191 ret i64 %tmp3
2192 }
2194 define <8 x i16> @sshll8h(ptr %A) nounwind {
2195 ; CHECK-LABEL: sshll8h:
2196 ; CHECK: // %bb.0:
2197 ; CHECK-NEXT: ldr d0, [x0]
2198 ; CHECK-NEXT: sshll.8h v0, v0, #1
2199 ; CHECK-NEXT: ret
2200 %tmp1 = load <8 x i8>, ptr %A
2201 %tmp2 = sext <8 x i8> %tmp1 to <8 x i16>
2202 %tmp3 = shl <8 x i16> %tmp2, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
2203 ret <8 x i16> %tmp3
2204 }
2206 define <2 x i64> @sshll2d(ptr %A) nounwind {
2207 ; CHECK-LABEL: sshll2d:
2208 ; CHECK: // %bb.0:
2209 ; CHECK-NEXT: ldr d0, [x0]
2210 ; CHECK-NEXT: sshll.2d v0, v0, #1
2211 ; CHECK-NEXT: ret
2212 %tmp1 = load <2 x i32>, ptr %A
2213 %tmp2 = sext <2 x i32> %tmp1 to <2 x i64>
2214 %tmp3 = shl <2 x i64> %tmp2, <i64 1, i64 1>
2215 ret <2 x i64> %tmp3
2216 }
2218 declare <16 x i8> @llvm.aarch64.neon.sshl.v16i8(<16 x i8>, <16 x i8>)
2219 declare <8 x i16> @llvm.aarch64.neon.sshl.v8i16(<8 x i16>, <8 x i16>)
2220 declare <4 x i32> @llvm.aarch64.neon.sshl.v4i32(<4 x i32>, <4 x i32>)
2221 declare <2 x i64> @llvm.aarch64.neon.sshl.v2i64(<2 x i64>, <2 x i64>)
2222 declare <1 x i64> @llvm.aarch64.neon.sshl.v1i64(<1 x i64>, <1 x i64>)
2223 declare i64 @llvm.aarch64.neon.sshl.i64(i64, i64)
2225 define <16 x i8> @neon.sshl16b_constant_shift(ptr %A) nounwind {
2226 ; CHECK-LABEL: neon.sshl16b_constant_shift:
2227 ; CHECK: // %bb.0:
2228 ; CHECK-NEXT: ldr q0, [x0]
2229 ; CHECK-NEXT: add.16b v0, v0, v0
2230 ; CHECK-NEXT: ret
2231 %tmp1 = load <16 x i8>, ptr %A
2232 %tmp2 = call <16 x i8> @llvm.aarch64.neon.sshl.v16i8(<16 x i8> %tmp1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)
2233 ret <16 x i8> %tmp2
2234 }
2236 define <16 x i8> @neon.sshl16b_non_splat_constant_shift(ptr %A) nounwind {
2237 ; CHECK-LABEL: neon.sshl16b_non_splat_constant_shift:
2238 ; CHECK: // %bb.0:
2239 ; CHECK-NEXT: adrp x8, .LCPI167_0
2240 ; CHECK-NEXT: ldr q0, [x0]
2241 ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI167_0]
2242 ; CHECK-NEXT: sshl.16b v0, v0, v1
2243 ; CHECK-NEXT: ret
2244 %tmp1 = load <16 x i8>, ptr %A
2245 %tmp2 = call <16 x i8> @llvm.aarch64.neon.sshl.v16i8(<16 x i8> %tmp1, <16 x i8> <i8 6, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)
2246 ret <16 x i8> %tmp2
2247 }
2249 define <16 x i8> @neon.sshl16b_neg_constant_shift(ptr %A) nounwind {
2250 ; CHECK-LABEL: neon.sshl16b_neg_constant_shift:
2251 ; CHECK: // %bb.0:
2252 ; CHECK-NEXT: ldr q0, [x0]
2253 ; CHECK-NEXT: sshr.16b v0, v0, #2
2254 ; CHECK-NEXT: ret
2255 %tmp1 = load <16 x i8>, ptr %A
2256 %tmp2 = call <16 x i8> @llvm.aarch64.neon.sshl.v16i8(<16 x i8> %tmp1, <16 x i8> <i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2>)
2257 ret <16 x i8> %tmp2
2258 }
2260 define <8 x i16> @neon.sshll8h_constant_shift(ptr %A) nounwind {
2261 ; CHECK-LABEL: neon.sshll8h_constant_shift:
2262 ; CHECK: // %bb.0:
2263 ; CHECK-NEXT: ldr d0, [x0]
2264 ; CHECK-NEXT: sshll.8h v0, v0, #1
2265 ; CHECK-NEXT: ret
2266 %tmp1 = load <8 x i8>, ptr %A
2267 %tmp2 = sext <8 x i8> %tmp1 to <8 x i16>
2268 %tmp3 = call <8 x i16> @llvm.aarch64.neon.sshl.v8i16(<8 x i16> %tmp2, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)
2269 ret <8 x i16> %tmp3
2270 }
2272 define <4 x i32> @neon.sshl4s_wrong_ext_constant_shift(ptr %A) nounwind {
2273 ; CHECK-LABEL: neon.sshl4s_wrong_ext_constant_shift:
2274 ; CHECK: // %bb.0:
2275 ; CHECK-NEXT: ldr s0, [x0]
2276 ; CHECK-NEXT: sshll.8h v0, v0, #0
2277 ; CHECK-NEXT: sshll.4s v0, v0, #1
2278 ; CHECK-NEXT: ret
2279 %tmp1 = load <4 x i8>, ptr %A
2280 %tmp2 = sext <4 x i8> %tmp1 to <4 x i32>
2281 %tmp3 = call <4 x i32> @llvm.aarch64.neon.sshl.v4i32(<4 x i32> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)
2282 ret <4 x i32> %tmp3
2283 }
2285 define <4 x i32> @neon.sshll4s_constant_shift(ptr %A) nounwind {
2286 ; CHECK-LABEL: neon.sshll4s_constant_shift:
2287 ; CHECK: // %bb.0:
2288 ; CHECK-NEXT: ldr d0, [x0]
2289 ; CHECK-NEXT: sshll.4s v0, v0, #1
2290 ; CHECK-NEXT: ret
2291 %tmp1 = load <4 x i16>, ptr %A
2292 %tmp2 = sext <4 x i16> %tmp1 to <4 x i32>
2293 %tmp3 = call <4 x i32> @llvm.aarch64.neon.sshl.v4i32(<4 x i32> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)
2294 ret <4 x i32> %tmp3
2295 }
2297 define <4 x i32> @neon.sshll4s_neg_constant_shift(ptr %A) nounwind {
2298 ; CHECK-LABEL: neon.sshll4s_neg_constant_shift:
2299 ; CHECK: // %bb.0:
2300 ; CHECK-NEXT: ldr d0, [x0]
2301 ; CHECK-NEXT: sshll.4s v0, v0, #0
2302 ; CHECK-NEXT: sshr.4s v0, v0, #1
2303 ; CHECK-NEXT: ret
2304 %tmp1 = load <4 x i16>, ptr %A
2305 %tmp2 = sext <4 x i16> %tmp1 to <4 x i32>
2306 %tmp3 = call <4 x i32> @llvm.aarch64.neon.sshl.v4i32(<4 x i32> %tmp2, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>)
2307 ret <4 x i32> %tmp3
2308 }
2310 ; FIXME: should be constant folded.
2311 define <4 x i32> @neon.sshl4s_constant_fold() nounwind {
2312 ; CHECK-LABEL: neon.sshl4s_constant_fold:
2313 ; CHECK: // %bb.0:
2314 ; CHECK-NEXT: adrp x8, .LCPI173_0
2315 ; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI173_0]
2316 ; CHECK-NEXT: shl.4s v0, v0, #2
2317 ; CHECK-NEXT: ret
2318 %tmp3 = call <4 x i32> @llvm.aarch64.neon.sshl.v4i32(<4 x i32> <i32 0, i32 1, i32 2, i32 3>, <4 x i32> <i32 2, i32 2, i32 2, i32 2>)
2319 ret <4 x i32> %tmp3
2320 }
2322 define <4 x i32> @neon.sshl4s_no_fold(ptr %A) nounwind {
2323 ; CHECK-LABEL: neon.sshl4s_no_fold:
2324 ; CHECK: // %bb.0:
2325 ; CHECK-NEXT: ldr q0, [x0]
2326 ; CHECK-NEXT: add.4s v0, v0, v0
2327 ; CHECK-NEXT: ret
2328 %tmp1 = load <4 x i32>, ptr %A
2329 %tmp3 = call <4 x i32> @llvm.aarch64.neon.sshl.v4i32(<4 x i32> %tmp1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)
2330 ret <4 x i32> %tmp3
2331 }
2333 define <2 x i64> @neon.sshll2d_constant_shift(ptr %A) nounwind {
2334 ; CHECK-LABEL: neon.sshll2d_constant_shift:
2335 ; CHECK: // %bb.0:
2336 ; CHECK-NEXT: ldr d0, [x0]
2337 ; CHECK-NEXT: sshll.2d v0, v0, #1
2338 ; CHECK-NEXT: ret
2339 %tmp1 = load <2 x i32>, ptr %A
2340 %tmp2 = sext <2 x i32> %tmp1 to <2 x i64>
2341 %tmp3 = call <2 x i64> @llvm.aarch64.neon.sshl.v2i64(<2 x i64> %tmp2, <2 x i64> <i64 1, i64 1>)
2342 ret <2 x i64> %tmp3
2343 }
2345 define <1 x i64> @neon.sshll_vscalar_constant_shift(ptr %A) nounwind {
2346 ; CHECK-LABEL: neon.sshll_vscalar_constant_shift:
2347 ; CHECK: // %bb.0:
2348 ; CHECK-NEXT: movi.2d v1, #0000000000000000
2349 ; CHECK-NEXT: ldr s0, [x0]
2350 ; CHECK-NEXT: zip1.2s v0, v0, v1
2351 ; CHECK-NEXT: shl d0, d0, #1
2352 ; CHECK-NEXT: ret
2353 %tmp1 = load <1 x i32>, ptr %A
2354 %tmp2 = zext <1 x i32> %tmp1 to <1 x i64>
2355 %tmp3 = call <1 x i64> @llvm.aarch64.neon.sshl.v1i64(<1 x i64> %tmp2, <1 x i64> <i64 1>)
2356 ret <1 x i64> %tmp3
2357 }
2359 define i64 @neon.sshll_scalar_constant_shift(ptr %A) nounwind {
2360 ; CHECK-LABEL: neon.sshll_scalar_constant_shift:
2361 ; CHECK: // %bb.0:
2362 ; CHECK-NEXT: ldr w8, [x0]
2363 ; CHECK-NEXT: fmov d0, x8
2364 ; CHECK-NEXT: shl d0, d0, #1
2365 ; CHECK-NEXT: fmov x0, d0
2366 ; CHECK-NEXT: ret
2367 %tmp1 = load i32, ptr %A
2368 %tmp2 = zext i32 %tmp1 to i64
2369 %tmp3 = call i64 @llvm.aarch64.neon.sshl.i64(i64 %tmp2, i64 1)
2370 ret i64 %tmp3
2371 }
2373 define i64 @neon.sshll_scalar_constant_shift_m1(ptr %A) nounwind {
2374 ; CHECK-LABEL: neon.sshll_scalar_constant_shift_m1:
2375 ; CHECK: // %bb.0:
2376 ; CHECK-NEXT: ldr w8, [x0]
2377 ; CHECK-NEXT: fmov d0, x8
2378 ; CHECK-NEXT: sshr d0, d0, #1
2379 ; CHECK-NEXT: fmov x0, d0
2380 ; CHECK-NEXT: ret
2381 %tmp1 = load i32, ptr %A
2382 %tmp2 = zext i32 %tmp1 to i64
2383 %tmp3 = call i64 @llvm.aarch64.neon.sshl.i64(i64 %tmp2, i64 -1)
2384 ret i64 %tmp3
2385 }
2387 ; FIXME: should be constant folded.
2388 define <2 x i64> @neon.sshl2d_constant_fold() nounwind {
2389 ; CHECK-LABEL: neon.sshl2d_constant_fold:
2390 ; CHECK: // %bb.0:
2391 ; CHECK-NEXT: adrp x8, .LCPI179_0
2392 ; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI179_0]
2393 ; CHECK-NEXT: add.2d v0, v0, v0
2394 ; CHECK-NEXT: ret
2395 %tmp3 = call <2 x i64> @llvm.aarch64.neon.sshl.v2i64(<2 x i64> <i64 99, i64 1000>, <2 x i64> <i64 1, i64 1>)
2396 ret <2 x i64> %tmp3
2397 }
2399 define <2 x i64> @neon.sshl2d_no_fold(ptr %A) nounwind {
2400 ; CHECK-LABEL: neon.sshl2d_no_fold:
2401 ; CHECK: // %bb.0:
2402 ; CHECK-NEXT: ldr q0, [x0]
2403 ; CHECK-NEXT: shl.2d v0, v0, #2
2404 ; CHECK-NEXT: ret
2405 %tmp2 = load <2 x i64>, ptr %A
2406 %tmp3 = call <2 x i64> @llvm.aarch64.neon.sshl.v2i64(<2 x i64> %tmp2, <2 x i64> <i64 2, i64 2>)
2407 ret <2 x i64> %tmp3
2408 }
2410 define <8 x i16> @sshll2_8h(ptr %A) nounwind {
2411 ; CHECK-LABEL: sshll2_8h:
2412 ; CHECK: // %bb.0:
2413 ; CHECK-NEXT: ldr d0, [x0, #8]
2414 ; CHECK-NEXT: sshll.8h v0, v0, #1
2415 ; CHECK-NEXT: ret
2416 %load1 = load <16 x i8>, ptr %A
2417 %tmp1 = shufflevector <16 x i8> %load1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
2418 %tmp2 = sext <8 x i8> %tmp1 to <8 x i16>
2419 %tmp3 = shl <8 x i16> %tmp2, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
2420 ret <8 x i16> %tmp3
2421 }
2423 define <4 x i32> @sshll2_4s(ptr %A) nounwind {
2424 ; CHECK-LABEL: sshll2_4s:
2425 ; CHECK: // %bb.0:
2426 ; CHECK-NEXT: ldr d0, [x0, #8]
2427 ; CHECK-NEXT: sshll.4s v0, v0, #1
2428 ; CHECK-NEXT: ret
2429 %load1 = load <8 x i16>, ptr %A
2430 %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
2431 %tmp2 = sext <4 x i16> %tmp1 to <4 x i32>
2432 %tmp3 = shl <4 x i32> %tmp2, <i32 1, i32 1, i32 1, i32 1>
2433 ret <4 x i32> %tmp3
2434 }
2436 define <2 x i64> @sshll2_2d(ptr %A) nounwind {
2437 ; CHECK-LABEL: sshll2_2d:
2438 ; CHECK: // %bb.0:
2439 ; CHECK-NEXT: ldr d0, [x0, #8]
2440 ; CHECK-NEXT: sshll.2d v0, v0, #1
2441 ; CHECK-NEXT: ret
2442 %load1 = load <4 x i32>, ptr %A
2443 %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
2444 %tmp2 = sext <2 x i32> %tmp1 to <2 x i64>
2445 %tmp3 = shl <2 x i64> %tmp2, <i64 1, i64 1>
2446 ret <2 x i64> %tmp3
2447 }
2449 define <8 x i8> @sqshli8b(ptr %A) nounwind {
2450 ; CHECK-LABEL: sqshli8b:
2451 ; CHECK: // %bb.0:
2452 ; CHECK-NEXT: ldr d0, [x0]
2453 ; CHECK-NEXT: sqshl.8b v0, v0, #1
2454 ; CHECK-NEXT: ret
2455 %tmp1 = load <8 x i8>, ptr %A
2456 %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqshl.v8i8(<8 x i8> %tmp1, <8 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)
2457 ret <8 x i8> %tmp3
2458 }
2460 define <4 x i16> @sqshli4h(ptr %A) nounwind {
2461 ; CHECK-LABEL: sqshli4h:
2462 ; CHECK: // %bb.0:
2463 ; CHECK-NEXT: ldr d0, [x0]
2464 ; CHECK-NEXT: sqshl.4h v0, v0, #1
2465 ; CHECK-NEXT: ret
2466 %tmp1 = load <4 x i16>, ptr %A
2467 %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqshl.v4i16(<4 x i16> %tmp1, <4 x i16> <i16 1, i16 1, i16 1, i16 1>)
2468 ret <4 x i16> %tmp3
2469 }
2471 define <2 x i32> @sqshli2s(ptr %A) nounwind {
2472 ; CHECK-LABEL: sqshli2s:
2473 ; CHECK: // %bb.0:
2474 ; CHECK-NEXT: ldr d0, [x0]
2475 ; CHECK-NEXT: sqshl.2s v0, v0, #1
2476 ; CHECK-NEXT: ret
2477 %tmp1 = load <2 x i32>, ptr %A
2478 %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqshl.v2i32(<2 x i32> %tmp1, <2 x i32> <i32 1, i32 1>)
2479 ret <2 x i32> %tmp3
2480 }
2482 define <16 x i8> @sqshli16b(ptr %A) nounwind {
2483 ; CHECK-LABEL: sqshli16b:
2484 ; CHECK: // %bb.0:
2485 ; CHECK-NEXT: ldr q0, [x0]
2486 ; CHECK-NEXT: sqshl.16b v0, v0, #1
2487 ; CHECK-NEXT: ret
2488 %tmp1 = load <16 x i8>, ptr %A
2489 %tmp3 = call <16 x i8> @llvm.aarch64.neon.sqshl.v16i8(<16 x i8> %tmp1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)
2490 ret <16 x i8> %tmp3
2491 }
2493 define <8 x i16> @sqshli8h(ptr %A) nounwind {
2494 ; CHECK-LABEL: sqshli8h:
2495 ; CHECK: // %bb.0:
2496 ; CHECK-NEXT: ldr q0, [x0]
2497 ; CHECK-NEXT: sqshl.8h v0, v0, #1
2498 ; CHECK-NEXT: ret
2499 %tmp1 = load <8 x i16>, ptr %A
2500 %tmp3 = call <8 x i16> @llvm.aarch64.neon.sqshl.v8i16(<8 x i16> %tmp1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)
2501 ret <8 x i16> %tmp3
2502 }
2504 define <4 x i32> @sqshli4s(ptr %A) nounwind {
2505 ; CHECK-LABEL: sqshli4s:
2506 ; CHECK: // %bb.0:
2507 ; CHECK-NEXT: ldr q0, [x0]
2508 ; CHECK-NEXT: sqshl.4s v0, v0, #1
2509 ; CHECK-NEXT: ret
2510 %tmp1 = load <4 x i32>, ptr %A
2511 %tmp3 = call <4 x i32> @llvm.aarch64.neon.sqshl.v4i32(<4 x i32> %tmp1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)
2512 ret <4 x i32> %tmp3
2513 }
2515 define <2 x i64> @sqshli2d(ptr %A) nounwind {
2516 ; CHECK-LABEL: sqshli2d:
2517 ; CHECK: // %bb.0:
2518 ; CHECK-NEXT: ldr q0, [x0]
2519 ; CHECK-NEXT: sqshl.2d v0, v0, #1
2520 ; CHECK-NEXT: ret
2521 %tmp1 = load <2 x i64>, ptr %A
2522 %tmp3 = call <2 x i64> @llvm.aarch64.neon.sqshl.v2i64(<2 x i64> %tmp1, <2 x i64> <i64 1, i64 1>)
2523 ret <2 x i64> %tmp3
2524 }
2526 define <8 x i8> @uqshli8b(ptr %A) nounwind {
2527 ; CHECK-LABEL: uqshli8b:
2528 ; CHECK: // %bb.0:
2529 ; CHECK-NEXT: ldr d0, [x0]
2530 ; CHECK-NEXT: uqshl.8b v0, v0, #1
2531 ; CHECK-NEXT: ret
2532 %tmp1 = load <8 x i8>, ptr %A
2533 %tmp3 = call <8 x i8> @llvm.aarch64.neon.uqshl.v8i8(<8 x i8> %tmp1, <8 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)
2534 ret <8 x i8> %tmp3
2535 }
2537 define <8 x i8> @uqshli8b_1(ptr %A) nounwind {
2538 ; CHECK-LABEL: uqshli8b_1:
2539 ; CHECK: // %bb.0:
2540 ; CHECK-NEXT: movi.8b v1, #8
2541 ; CHECK-NEXT: ldr d0, [x0]
2542 ; CHECK-NEXT: uqshl.8b v0, v0, v1
2543 ; CHECK-NEXT: ret
2544 %tmp1 = load <8 x i8>, ptr %A
2545 %tmp3 = call <8 x i8> @llvm.aarch64.neon.uqshl.v8i8(<8 x i8> %tmp1, <8 x i8> <i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8>)
2546 ret <8 x i8> %tmp3
2547 }
2549 define <4 x i16> @uqshli4h(ptr %A) nounwind {
2550 ; CHECK-LABEL: uqshli4h:
2551 ; CHECK: // %bb.0:
2552 ; CHECK-NEXT: ldr d0, [x0]
2553 ; CHECK-NEXT: uqshl.4h v0, v0, #1
2554 ; CHECK-NEXT: ret
2555 %tmp1 = load <4 x i16>, ptr %A
2556 %tmp3 = call <4 x i16> @llvm.aarch64.neon.uqshl.v4i16(<4 x i16> %tmp1, <4 x i16> <i16 1, i16 1, i16 1, i16 1>)
2557 ret <4 x i16> %tmp3
2558 }
2560 define <2 x i32> @uqshli2s(ptr %A) nounwind {
2561 ; CHECK-LABEL: uqshli2s:
2562 ; CHECK: // %bb.0:
2563 ; CHECK-NEXT: ldr d0, [x0]
2564 ; CHECK-NEXT: uqshl.2s v0, v0, #1
2565 ; CHECK-NEXT: ret
2566 %tmp1 = load <2 x i32>, ptr %A
2567 %tmp3 = call <2 x i32> @llvm.aarch64.neon.uqshl.v2i32(<2 x i32> %tmp1, <2 x i32> <i32 1, i32 1>)
2568 ret <2 x i32> %tmp3
2569 }
2571 define <16 x i8> @uqshli16b(ptr %A) nounwind {
2572 ; CHECK-LABEL: uqshli16b:
2573 ; CHECK: // %bb.0:
2574 ; CHECK-NEXT: ldr q0, [x0]
2575 ; CHECK-NEXT: uqshl.16b v0, v0, #1
2576 ; CHECK-NEXT: ret
2577 %tmp1 = load <16 x i8>, ptr %A
2578 %tmp3 = call <16 x i8> @llvm.aarch64.neon.uqshl.v16i8(<16 x i8> %tmp1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)
2579 ret <16 x i8> %tmp3
2580 }
2582 define <8 x i16> @uqshli8h(ptr %A) nounwind {
2583 ; CHECK-LABEL: uqshli8h:
2584 ; CHECK: // %bb.0:
2585 ; CHECK-NEXT: ldr q0, [x0]
2586 ; CHECK-NEXT: uqshl.8h v0, v0, #1
2587 ; CHECK-NEXT: ret
2588 %tmp1 = load <8 x i16>, ptr %A
2589 %tmp3 = call <8 x i16> @llvm.aarch64.neon.uqshl.v8i16(<8 x i16> %tmp1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)
2590 ret <8 x i16> %tmp3
2591 }
2593 define <4 x i32> @uqshli4s(ptr %A) nounwind {
2594 ; CHECK-LABEL: uqshli4s:
2595 ; CHECK: // %bb.0:
2596 ; CHECK-NEXT: ldr q0, [x0]
2597 ; CHECK-NEXT: uqshl.4s v0, v0, #1
2598 ; CHECK-NEXT: ret
2599 %tmp1 = load <4 x i32>, ptr %A
2600 %tmp3 = call <4 x i32> @llvm.aarch64.neon.uqshl.v4i32(<4 x i32> %tmp1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)
2601 ret <4 x i32> %tmp3
2602 }
2604 define <2 x i64> @uqshli2d(ptr %A) nounwind {
2605 ; CHECK-LABEL: uqshli2d:
2606 ; CHECK: // %bb.0:
2607 ; CHECK-NEXT: ldr q0, [x0]
2608 ; CHECK-NEXT: uqshl.2d v0, v0, #1
2609 ; CHECK-NEXT: ret
2610 %tmp1 = load <2 x i64>, ptr %A
2611 %tmp3 = call <2 x i64> @llvm.aarch64.neon.uqshl.v2i64(<2 x i64> %tmp1, <2 x i64> <i64 1, i64 1>)
2612 ret <2 x i64> %tmp3
2613 }
2615 define <8 x i8> @ursra8b(ptr %A, ptr %B) nounwind {
2616 ; CHECK-LABEL: ursra8b:
2617 ; CHECK: // %bb.0:
2618 ; CHECK-NEXT: ldr d1, [x0]
2619 ; CHECK-NEXT: ldr d0, [x1]
2620 ; CHECK-NEXT: ursra.8b v0, v1, #1
2621 ; CHECK-NEXT: ret
2622 %tmp1 = load <8 x i8>, ptr %A
2623 %tmp3 = call <8 x i8> @llvm.aarch64.neon.urshl.v8i8(<8 x i8> %tmp1, <8 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)
2624 %tmp4 = load <8 x i8>, ptr %B
2625 %tmp5 = add <8 x i8> %tmp3, %tmp4
2626 ret <8 x i8> %tmp5
2627 }
2629 define <4 x i16> @ursra4h(ptr %A, ptr %B) nounwind {
2630 ; CHECK-LABEL: ursra4h:
2631 ; CHECK: // %bb.0:
2632 ; CHECK-NEXT: ldr d1, [x0]
2633 ; CHECK-NEXT: ldr d0, [x1]
2634 ; CHECK-NEXT: ursra.4h v0, v1, #1
2635 ; CHECK-NEXT: ret
2636 %tmp1 = load <4 x i16>, ptr %A
2637 %tmp3 = call <4 x i16> @llvm.aarch64.neon.urshl.v4i16(<4 x i16> %tmp1, <4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>)
2638 %tmp4 = load <4 x i16>, ptr %B
2639 %tmp5 = add <4 x i16> %tmp3, %tmp4
2640 ret <4 x i16> %tmp5
2641 }
2643 define <2 x i32> @ursra2s(ptr %A, ptr %B) nounwind {
2644 ; CHECK-LABEL: ursra2s:
2645 ; CHECK: // %bb.0:
2646 ; CHECK-NEXT: ldr d1, [x0]
2647 ; CHECK-NEXT: ldr d0, [x1]
2648 ; CHECK-NEXT: ursra.2s v0, v1, #1
2649 ; CHECK-NEXT: ret
2650 %tmp1 = load <2 x i32>, ptr %A
2651 %tmp3 = call <2 x i32> @llvm.aarch64.neon.urshl.v2i32(<2 x i32> %tmp1, <2 x i32> <i32 -1, i32 -1>)
2652 %tmp4 = load <2 x i32>, ptr %B
2653 %tmp5 = add <2 x i32> %tmp3, %tmp4
2654 ret <2 x i32> %tmp5
2655 }
2657 define <16 x i8> @ursra16b(ptr %A, ptr %B) nounwind {
2658 ; CHECK-LABEL: ursra16b:
2659 ; CHECK: // %bb.0:
2660 ; CHECK-NEXT: ldr q1, [x0]
2661 ; CHECK-NEXT: ldr q0, [x1]
2662 ; CHECK-NEXT: ursra.16b v0, v1, #1
2663 ; CHECK-NEXT: ret
2664 %tmp1 = load <16 x i8>, ptr %A
2665 %tmp3 = call <16 x i8> @llvm.aarch64.neon.urshl.v16i8(<16 x i8> %tmp1, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)
2666 %tmp4 = load <16 x i8>, ptr %B
2667 %tmp5 = add <16 x i8> %tmp3, %tmp4
2668 ret <16 x i8> %tmp5
2669 }
2671 define <8 x i16> @ursra8h(ptr %A, ptr %B) nounwind {
2672 ; CHECK-LABEL: ursra8h:
2673 ; CHECK: // %bb.0:
2674 ; CHECK-NEXT: ldr q1, [x0]
2675 ; CHECK-NEXT: ldr q0, [x1]
2676 ; CHECK-NEXT: ursra.8h v0, v1, #1
2677 ; CHECK-NEXT: ret
2678 %tmp1 = load <8 x i16>, ptr %A
2679 %tmp3 = call <8 x i16> @llvm.aarch64.neon.urshl.v8i16(<8 x i16> %tmp1, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>)
2680 %tmp4 = load <8 x i16>, ptr %B
2681 %tmp5 = add <8 x i16> %tmp3, %tmp4
2682 ret <8 x i16> %tmp5
2683 }
2685 define <4 x i32> @ursra4s(ptr %A, ptr %B) nounwind {
2686 ; CHECK-LABEL: ursra4s:
2687 ; CHECK: // %bb.0:
2688 ; CHECK-NEXT: ldr q1, [x0]
2689 ; CHECK-NEXT: ldr q0, [x1]
2690 ; CHECK-NEXT: ursra.4s v0, v1, #1
2691 ; CHECK-NEXT: ret
2692 %tmp1 = load <4 x i32>, ptr %A
2693 %tmp3 = call <4 x i32> @llvm.aarch64.neon.urshl.v4i32(<4 x i32> %tmp1, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>)
2694 %tmp4 = load <4 x i32>, ptr %B
2695 %tmp5 = add <4 x i32> %tmp3, %tmp4
2696 ret <4 x i32> %tmp5
2697 }
2699 define <2 x i64> @ursra2d(ptr %A, ptr %B) nounwind {
2700 ; CHECK-LABEL: ursra2d:
2701 ; CHECK: // %bb.0:
2702 ; CHECK-NEXT: ldr q1, [x0]
2703 ; CHECK-NEXT: ldr q0, [x1]
2704 ; CHECK-NEXT: ursra.2d v0, v1, #1
2705 ; CHECK-NEXT: ret
2706 %tmp1 = load <2 x i64>, ptr %A
2707 %tmp3 = call <2 x i64> @llvm.aarch64.neon.urshl.v2i64(<2 x i64> %tmp1, <2 x i64> <i64 -1, i64 -1>)
2708 %tmp4 = load <2 x i64>, ptr %B
2709 %tmp5 = add <2 x i64> %tmp3, %tmp4
2710 ret <2 x i64> %tmp5
2711 }
2713 define <1 x i64> @ursra1d(ptr %A, ptr %B) nounwind {
2714 ; CHECK-LABEL: ursra1d:
2715 ; CHECK: // %bb.0:
2716 ; CHECK-NEXT: ldr d1, [x0]
2717 ; CHECK-NEXT: ldr d0, [x1]
2718 ; CHECK-NEXT: ursra d0, d1, #1
2719 ; CHECK-NEXT: ret
2720 %tmp1 = load <1 x i64>, ptr %A
2721 %tmp3 = call <1 x i64> @llvm.aarch64.neon.urshl.v1i64(<1 x i64> %tmp1, <1 x i64> <i64 -1>)
2722 %tmp4 = load <1 x i64>, ptr %B
2723 %tmp5 = add <1 x i64> %tmp3, %tmp4
2724 ret <1 x i64> %tmp5
2725 }
2727 define i64 @ursra_scalar(ptr %A, ptr %B) nounwind {
2728 ; CHECK-LABEL: ursra_scalar:
2729 ; CHECK: // %bb.0:
2730 ; CHECK-NEXT: ldr d0, [x0]
2731 ; CHECK-NEXT: ldr d1, [x1]
2732 ; CHECK-NEXT: ursra d1, d0, #1
2733 ; CHECK-NEXT: fmov x0, d1
2734 ; CHECK-NEXT: ret
2735 %tmp1 = load i64, ptr %A
2736 %tmp3 = call i64 @llvm.aarch64.neon.urshl.i64(i64 %tmp1, i64 -1)
2737 %tmp4 = load i64, ptr %B
2738 %tmp5 = add i64 %tmp3, %tmp4
2739 ret i64 %tmp5
2740 }
2742 define <8 x i8> @srsra8b(ptr %A, ptr %B) nounwind {
2743 ; CHECK-LABEL: srsra8b:
2744 ; CHECK: // %bb.0:
2745 ; CHECK-NEXT: ldr d1, [x0]
2746 ; CHECK-NEXT: ldr d0, [x1]
2747 ; CHECK-NEXT: srsra.8b v0, v1, #1
2748 ; CHECK-NEXT: ret
2749 %tmp1 = load <8 x i8>, ptr %A
2750 %tmp3 = call <8 x i8> @llvm.aarch64.neon.srshl.v8i8(<8 x i8> %tmp1, <8 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)
2751 %tmp4 = load <8 x i8>, ptr %B
2752 %tmp5 = add <8 x i8> %tmp3, %tmp4
2753 ret <8 x i8> %tmp5
2754 }
2756 define <4 x i16> @srsra4h(ptr %A, ptr %B) nounwind {
2757 ; CHECK-LABEL: srsra4h:
2758 ; CHECK: // %bb.0:
2759 ; CHECK-NEXT: ldr d1, [x0]
2760 ; CHECK-NEXT: ldr d0, [x1]
2761 ; CHECK-NEXT: srsra.4h v0, v1, #1
2762 ; CHECK-NEXT: ret
2763 %tmp1 = load <4 x i16>, ptr %A
2764 %tmp3 = call <4 x i16> @llvm.aarch64.neon.srshl.v4i16(<4 x i16> %tmp1, <4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>)
2765 %tmp4 = load <4 x i16>, ptr %B
2766 %tmp5 = add <4 x i16> %tmp3, %tmp4
2767 ret <4 x i16> %tmp5
2768 }
2770 define <2 x i32> @srsra2s(ptr %A, ptr %B) nounwind {
2771 ; CHECK-LABEL: srsra2s:
2772 ; CHECK: // %bb.0:
2773 ; CHECK-NEXT: ldr d1, [x0]
2774 ; CHECK-NEXT: ldr d0, [x1]
2775 ; CHECK-NEXT: srsra.2s v0, v1, #1
2776 ; CHECK-NEXT: ret
2777 %tmp1 = load <2 x i32>, ptr %A
2778 %tmp3 = call <2 x i32> @llvm.aarch64.neon.srshl.v2i32(<2 x i32> %tmp1, <2 x i32> <i32 -1, i32 -1>)
2779 %tmp4 = load <2 x i32>, ptr %B
2780 %tmp5 = add <2 x i32> %tmp3, %tmp4
2781 ret <2 x i32> %tmp5
2782 }
2784 define <16 x i8> @srsra16b(ptr %A, ptr %B) nounwind {
2785 ; CHECK-LABEL: srsra16b:
2786 ; CHECK: // %bb.0:
2787 ; CHECK-NEXT: ldr q1, [x0]
2788 ; CHECK-NEXT: ldr q0, [x1]
2789 ; CHECK-NEXT: srsra.16b v0, v1, #1
2790 ; CHECK-NEXT: ret
2791 %tmp1 = load <16 x i8>, ptr %A
2792 %tmp3 = call <16 x i8> @llvm.aarch64.neon.srshl.v16i8(<16 x i8> %tmp1, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)
2793 %tmp4 = load <16 x i8>, ptr %B
2794 %tmp5 = add <16 x i8> %tmp3, %tmp4
2795 ret <16 x i8> %tmp5
2796 }
2798 define <8 x i16> @srsra8h(ptr %A, ptr %B) nounwind {
2799 ; CHECK-LABEL: srsra8h:
2800 ; CHECK: // %bb.0:
2801 ; CHECK-NEXT: ldr q1, [x0]
2802 ; CHECK-NEXT: ldr q0, [x1]
2803 ; CHECK-NEXT: srsra.8h v0, v1, #1
2804 ; CHECK-NEXT: ret
2805 %tmp1 = load <8 x i16>, ptr %A
2806 %tmp3 = call <8 x i16> @llvm.aarch64.neon.srshl.v8i16(<8 x i16> %tmp1, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>)
2807 %tmp4 = load <8 x i16>, ptr %B
2808 %tmp5 = add <8 x i16> %tmp3, %tmp4
2809 ret <8 x i16> %tmp5
2810 }
2812 define <4 x i32> @srsra4s(ptr %A, ptr %B) nounwind {
2813 ; CHECK-LABEL: srsra4s:
2814 ; CHECK: // %bb.0:
2815 ; CHECK-NEXT: ldr q1, [x0]
2816 ; CHECK-NEXT: ldr q0, [x1]
2817 ; CHECK-NEXT: srsra.4s v0, v1, #1
2818 ; CHECK-NEXT: ret
2819 %tmp1 = load <4 x i32>, ptr %A
2820 %tmp3 = call <4 x i32> @llvm.aarch64.neon.srshl.v4i32(<4 x i32> %tmp1, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>)
2821 %tmp4 = load <4 x i32>, ptr %B
2822 %tmp5 = add <4 x i32> %tmp3, %tmp4
2823 ret <4 x i32> %tmp5
2824 }
2826 define <2 x i64> @srsra2d(ptr %A, ptr %B) nounwind {
2827 ; CHECK-LABEL: srsra2d:
2828 ; CHECK: // %bb.0:
2829 ; CHECK-NEXT: ldr q1, [x0]
2830 ; CHECK-NEXT: ldr q0, [x1]
2831 ; CHECK-NEXT: srsra.2d v0, v1, #1
2832 ; CHECK-NEXT: ret
2833 %tmp1 = load <2 x i64>, ptr %A
2834 %tmp3 = call <2 x i64> @llvm.aarch64.neon.srshl.v2i64(<2 x i64> %tmp1, <2 x i64> <i64 -1, i64 -1>)
2835 %tmp4 = load <2 x i64>, ptr %B
2836 %tmp5 = add <2 x i64> %tmp3, %tmp4
2837 ret <2 x i64> %tmp5
2838 }
2840 define <1 x i64> @srsra1d(ptr %A, ptr %B) nounwind {
2841 ; CHECK-LABEL: srsra1d:
2842 ; CHECK: // %bb.0:
2843 ; CHECK-NEXT: ldr d1, [x0]
2844 ; CHECK-NEXT: ldr d0, [x1]
2845 ; CHECK-NEXT: srsra d0, d1, #1
2846 ; CHECK-NEXT: ret
2847 %tmp1 = load <1 x i64>, ptr %A
2848 %tmp3 = call <1 x i64> @llvm.aarch64.neon.srshl.v1i64(<1 x i64> %tmp1, <1 x i64> <i64 -1>)
2849 %tmp4 = load <1 x i64>, ptr %B
2850 %tmp5 = add <1 x i64> %tmp3, %tmp4
2851 ret <1 x i64> %tmp5
2852 }
2854 define i64 @srsra_scalar(ptr %A, ptr %B) nounwind {
2855 ; CHECK-LABEL: srsra_scalar:
2856 ; CHECK: // %bb.0:
2857 ; CHECK-NEXT: ldr d0, [x0]
2858 ; CHECK-NEXT: ldr d1, [x1]
2859 ; CHECK-NEXT: srsra d1, d0, #1
2860 ; CHECK-NEXT: fmov x0, d1
2861 ; CHECK-NEXT: ret
2862 %tmp1 = load i64, ptr %A
2863 %tmp3 = call i64 @llvm.aarch64.neon.srshl.i64(i64 %tmp1, i64 -1)
2864 %tmp4 = load i64, ptr %B
2865 %tmp5 = add i64 %tmp3, %tmp4
2866 ret i64 %tmp5
2867 }
2869 define <8 x i8> @usra8b(ptr %A, ptr %B) nounwind {
2870 ; CHECK-LABEL: usra8b:
2871 ; CHECK: // %bb.0:
2872 ; CHECK-NEXT: ldr d1, [x0]
2873 ; CHECK-NEXT: ldr d0, [x1]
2874 ; CHECK-NEXT: usra.8b v0, v1, #1
2875 ; CHECK-NEXT: ret
2876 %tmp1 = load <8 x i8>, ptr %A
2877 %tmp3 = lshr <8 x i8> %tmp1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
2878 %tmp4 = load <8 x i8>, ptr %B
2879 %tmp5 = add <8 x i8> %tmp3, %tmp4
2880 ret <8 x i8> %tmp5
2881 }
2883 define <4 x i16> @usra4h(ptr %A, ptr %B) nounwind {
2884 ; CHECK-LABEL: usra4h:
2885 ; CHECK: // %bb.0:
2886 ; CHECK-NEXT: ldr d1, [x0]
2887 ; CHECK-NEXT: ldr d0, [x1]
2888 ; CHECK-NEXT: usra.4h v0, v1, #1
2889 ; CHECK-NEXT: ret
2890 %tmp1 = load <4 x i16>, ptr %A
2891 %tmp3 = lshr <4 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1>
2892 %tmp4 = load <4 x i16>, ptr %B
2893 %tmp5 = add <4 x i16> %tmp3, %tmp4
2894 ret <4 x i16> %tmp5
2895 }
2897 define <2 x i32> @usra2s(ptr %A, ptr %B) nounwind {
2898 ; CHECK-LABEL: usra2s:
2899 ; CHECK: // %bb.0:
2900 ; CHECK-NEXT: ldr d1, [x0]
2901 ; CHECK-NEXT: ldr d0, [x1]
2902 ; CHECK-NEXT: usra.2s v0, v1, #1
2903 ; CHECK-NEXT: ret
2904 %tmp1 = load <2 x i32>, ptr %A
2905 %tmp3 = lshr <2 x i32> %tmp1, <i32 1, i32 1>
2906 %tmp4 = load <2 x i32>, ptr %B
2907 %tmp5 = add <2 x i32> %tmp3, %tmp4
2908 ret <2 x i32> %tmp5
2909 }
2911 define <16 x i8> @usra16b(ptr %A, ptr %B) nounwind {
2912 ; CHECK-LABEL: usra16b:
2913 ; CHECK: // %bb.0:
2914 ; CHECK-NEXT: ldr q1, [x0]
2915 ; CHECK-NEXT: ldr q0, [x1]
2916 ; CHECK-NEXT: usra.16b v0, v1, #1
2917 ; CHECK-NEXT: ret
2918 %tmp1 = load <16 x i8>, ptr %A
2919 %tmp3 = lshr <16 x i8> %tmp1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
2920 %tmp4 = load <16 x i8>, ptr %B
2921 %tmp5 = add <16 x i8> %tmp3, %tmp4
2922 ret <16 x i8> %tmp5
2923 }
2925 define <8 x i16> @usra8h(ptr %A, ptr %B) nounwind {
2926 ; CHECK-LABEL: usra8h:
2927 ; CHECK: // %bb.0:
2928 ; CHECK-NEXT: ldr q1, [x0]
2929 ; CHECK-NEXT: ldr q0, [x1]
2930 ; CHECK-NEXT: usra.8h v0, v1, #1
2931 ; CHECK-NEXT: ret
2932 %tmp1 = load <8 x i16>, ptr %A
2933 %tmp3 = lshr <8 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
2934 %tmp4 = load <8 x i16>, ptr %B
2935 %tmp5 = add <8 x i16> %tmp3, %tmp4
2936 ret <8 x i16> %tmp5
2937 }
2939 define <4 x i32> @usra4s(ptr %A, ptr %B) nounwind {
2940 ; CHECK-LABEL: usra4s:
2941 ; CHECK: // %bb.0:
2942 ; CHECK-NEXT: ldr q1, [x0]
2943 ; CHECK-NEXT: ldr q0, [x1]
2944 ; CHECK-NEXT: usra.4s v0, v1, #1
2945 ; CHECK-NEXT: ret
2946 %tmp1 = load <4 x i32>, ptr %A
2947 %tmp3 = lshr <4 x i32> %tmp1, <i32 1, i32 1, i32 1, i32 1>
2948 %tmp4 = load <4 x i32>, ptr %B
2949 %tmp5 = add <4 x i32> %tmp3, %tmp4
2950 ret <4 x i32> %tmp5
2951 }
2953 define <2 x i64> @usra2d(ptr %A, ptr %B) nounwind {
2954 ; CHECK-LABEL: usra2d:
2955 ; CHECK: // %bb.0:
2956 ; CHECK-NEXT: ldr q1, [x0]
2957 ; CHECK-NEXT: ldr q0, [x1]
2958 ; CHECK-NEXT: usra.2d v0, v1, #1
2959 ; CHECK-NEXT: ret
2960 %tmp1 = load <2 x i64>, ptr %A
2961 %tmp3 = lshr <2 x i64> %tmp1, <i64 1, i64 1>
2962 %tmp4 = load <2 x i64>, ptr %B
2963 %tmp5 = add <2 x i64> %tmp3, %tmp4
2964 ret <2 x i64> %tmp5
2965 }
2967 define <1 x i64> @usra1d(ptr %A, ptr %B) nounwind {
2968 ; CHECK-LABEL: usra1d:
2969 ; CHECK: // %bb.0:
2970 ; CHECK-NEXT: ldr d1, [x0]
2971 ; CHECK-NEXT: ldr d0, [x1]
2972 ; CHECK-NEXT: usra d0, d1, #1
2973 ; CHECK-NEXT: ret
2974 %tmp1 = load <1 x i64>, ptr %A
2975 %tmp3 = lshr <1 x i64> %tmp1, <i64 1>
2976 %tmp4 = load <1 x i64>, ptr %B
2977 %tmp5 = add <1 x i64> %tmp3, %tmp4
2978 ret <1 x i64> %tmp5
2979 }
2981 define <8 x i8> @ssra8b(ptr %A, ptr %B) nounwind {
2982 ; CHECK-LABEL: ssra8b:
2983 ; CHECK: // %bb.0:
2984 ; CHECK-NEXT: ldr d1, [x0]
2985 ; CHECK-NEXT: ldr d0, [x1]
2986 ; CHECK-NEXT: ssra.8b v0, v1, #1
2987 ; CHECK-NEXT: ret
2988 %tmp1 = load <8 x i8>, ptr %A
2989 %tmp3 = ashr <8 x i8> %tmp1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
2990 %tmp4 = load <8 x i8>, ptr %B
2991 %tmp5 = add <8 x i8> %tmp3, %tmp4
2992 ret <8 x i8> %tmp5
2993 }
2995 define <4 x i16> @ssra4h(ptr %A, ptr %B) nounwind {
2996 ; CHECK-LABEL: ssra4h:
2997 ; CHECK: // %bb.0:
2998 ; CHECK-NEXT: ldr d1, [x0]
2999 ; CHECK-NEXT: ldr d0, [x1]
3000 ; CHECK-NEXT: ssra.4h v0, v1, #1
3001 ; CHECK-NEXT: ret
3002 %tmp1 = load <4 x i16>, ptr %A
3003 %tmp3 = ashr <4 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1>
3004 %tmp4 = load <4 x i16>, ptr %B
3005 %tmp5 = add <4 x i16> %tmp3, %tmp4
3006 ret <4 x i16> %tmp5
3007 }
3009 define <2 x i32> @ssra2s(ptr %A, ptr %B) nounwind {
3010 ; CHECK-LABEL: ssra2s:
3011 ; CHECK: // %bb.0:
3012 ; CHECK-NEXT: ldr d1, [x0]
3013 ; CHECK-NEXT: ldr d0, [x1]
3014 ; CHECK-NEXT: ssra.2s v0, v1, #1
3015 ; CHECK-NEXT: ret
3016 %tmp1 = load <2 x i32>, ptr %A
3017 %tmp3 = ashr <2 x i32> %tmp1, <i32 1, i32 1>
3018 %tmp4 = load <2 x i32>, ptr %B
3019 %tmp5 = add <2 x i32> %tmp3, %tmp4
3020 ret <2 x i32> %tmp5
3021 }
3023 define <16 x i8> @ssra16b(ptr %A, ptr %B) nounwind {
3024 ; CHECK-LABEL: ssra16b:
3025 ; CHECK: // %bb.0:
3026 ; CHECK-NEXT: ldr q1, [x0]
3027 ; CHECK-NEXT: ldr q0, [x1]
3028 ; CHECK-NEXT: ssra.16b v0, v1, #1
3029 ; CHECK-NEXT: ret
3030 %tmp1 = load <16 x i8>, ptr %A
3031 %tmp3 = ashr <16 x i8> %tmp1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
3032 %tmp4 = load <16 x i8>, ptr %B
3033 %tmp5 = add <16 x i8> %tmp3, %tmp4
3034 ret <16 x i8> %tmp5
3035 }
3037 define <8 x i16> @ssra8h(ptr %A, ptr %B) nounwind {
3038 ; CHECK-LABEL: ssra8h:
3039 ; CHECK: // %bb.0:
3040 ; CHECK-NEXT: ldr q1, [x0]
3041 ; CHECK-NEXT: ldr q0, [x1]
3042 ; CHECK-NEXT: ssra.8h v0, v1, #1
3043 ; CHECK-NEXT: ret
3044 %tmp1 = load <8 x i16>, ptr %A
3045 %tmp3 = ashr <8 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
3046 %tmp4 = load <8 x i16>, ptr %B
3047 %tmp5 = add <8 x i16> %tmp3, %tmp4
3048 ret <8 x i16> %tmp5
3049 }
3051 define <4 x i32> @ssra4s(ptr %A, ptr %B) nounwind {
3052 ; CHECK-LABEL: ssra4s:
3053 ; CHECK: // %bb.0:
3054 ; CHECK-NEXT: ldr q1, [x0]
3055 ; CHECK-NEXT: ldr q0, [x1]
3056 ; CHECK-NEXT: ssra.4s v0, v1, #1
3057 ; CHECK-NEXT: ret
3058 %tmp1 = load <4 x i32>, ptr %A
3059 %tmp3 = ashr <4 x i32> %tmp1, <i32 1, i32 1, i32 1, i32 1>
3060 %tmp4 = load <4 x i32>, ptr %B
3061 %tmp5 = add <4 x i32> %tmp3, %tmp4
3062 ret <4 x i32> %tmp5
3063 }
3065 define <2 x i64> @ssra2d(ptr %A, ptr %B) nounwind {
3066 ; CHECK-LABEL: ssra2d:
3067 ; CHECK: // %bb.0:
3068 ; CHECK-NEXT: ldr q1, [x0]
3069 ; CHECK-NEXT: ldr q0, [x1]
3070 ; CHECK-NEXT: ssra.2d v0, v1, #1
3071 ; CHECK-NEXT: ret
3072 %tmp1 = load <2 x i64>, ptr %A
3073 %tmp3 = ashr <2 x i64> %tmp1, <i64 1, i64 1>
3074 %tmp4 = load <2 x i64>, ptr %B
3075 %tmp5 = add <2 x i64> %tmp3, %tmp4
3076 ret <2 x i64> %tmp5
3077 }
3079 define <8 x i8> @shr_orr8b(ptr %A, ptr %B) nounwind {
3080 ; CHECK-LABEL: shr_orr8b:
3081 ; CHECK: // %bb.0:
3082 ; CHECK-NEXT: ldr d0, [x0]
3083 ; CHECK-NEXT: ldr d1, [x1]
3084 ; CHECK-NEXT: ushr.8b v0, v0, #1
3085 ; CHECK-NEXT: orr.8b v0, v0, v1
3086 ; CHECK-NEXT: ret
3087 %tmp1 = load <8 x i8>, ptr %A
3088 %tmp4 = load <8 x i8>, ptr %B
3089 %tmp3 = lshr <8 x i8> %tmp1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
3090 %tmp5 = or <8 x i8> %tmp3, %tmp4
3091 ret <8 x i8> %tmp5
3092 }
3094 define <4 x i16> @shr_orr4h(ptr %A, ptr %B) nounwind {
3095 ; CHECK-LABEL: shr_orr4h:
3096 ; CHECK: // %bb.0:
3097 ; CHECK-NEXT: ldr d0, [x0]
3098 ; CHECK-NEXT: ldr d1, [x1]
3099 ; CHECK-NEXT: ushr.4h v0, v0, #1
3100 ; CHECK-NEXT: orr.8b v0, v0, v1
3101 ; CHECK-NEXT: ret
3102 %tmp1 = load <4 x i16>, ptr %A
3103 %tmp4 = load <4 x i16>, ptr %B
3104 %tmp3 = lshr <4 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1>
3105 %tmp5 = or <4 x i16> %tmp3, %tmp4
3106 ret <4 x i16> %tmp5
3107 }
3109 define <2 x i32> @shr_orr2s(ptr %A, ptr %B) nounwind {
3110 ; CHECK-LABEL: shr_orr2s:
3111 ; CHECK: // %bb.0:
3112 ; CHECK-NEXT: ldr d0, [x0]
3113 ; CHECK-NEXT: ldr d1, [x1]
3114 ; CHECK-NEXT: ushr.2s v0, v0, #1
3115 ; CHECK-NEXT: orr.8b v0, v0, v1
3116 ; CHECK-NEXT: ret
3117 %tmp1 = load <2 x i32>, ptr %A
3118 %tmp4 = load <2 x i32>, ptr %B
3119 %tmp3 = lshr <2 x i32> %tmp1, <i32 1, i32 1>
3120 %tmp5 = or <2 x i32> %tmp3, %tmp4
3121 ret <2 x i32> %tmp5
3122 }
3124 define <16 x i8> @shr_orr16b(ptr %A, ptr %B) nounwind {
3125 ; CHECK-LABEL: shr_orr16b:
3126 ; CHECK: // %bb.0:
3127 ; CHECK-NEXT: ldr q0, [x0]
3128 ; CHECK-NEXT: ldr q1, [x1]
3129 ; CHECK-NEXT: ushr.16b v0, v0, #1
3130 ; CHECK-NEXT: orr.16b v0, v0, v1
3131 ; CHECK-NEXT: ret
3132 %tmp1 = load <16 x i8>, ptr %A
3133 %tmp4 = load <16 x i8>, ptr %B
3134 %tmp3 = lshr <16 x i8> %tmp1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
3135 %tmp5 = or <16 x i8> %tmp3, %tmp4
3136 ret <16 x i8> %tmp5
3137 }
3139 define <8 x i16> @shr_orr8h(ptr %A, ptr %B) nounwind {
3140 ; CHECK-LABEL: shr_orr8h:
3141 ; CHECK: // %bb.0:
3142 ; CHECK-NEXT: ldr q0, [x0]
3143 ; CHECK-NEXT: ldr q1, [x1]
3144 ; CHECK-NEXT: ushr.8h v0, v0, #1
3145 ; CHECK-NEXT: orr.16b v0, v0, v1
3146 ; CHECK-NEXT: ret
3147 %tmp1 = load <8 x i16>, ptr %A
3148 %tmp4 = load <8 x i16>, ptr %B
3149 %tmp3 = lshr <8 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
3150 %tmp5 = or <8 x i16> %tmp3, %tmp4
3151 ret <8 x i16> %tmp5
3152 }
3154 define <4 x i32> @shr_orr4s(ptr %A, ptr %B) nounwind {
3155 ; CHECK-LABEL: shr_orr4s:
3156 ; CHECK: // %bb.0:
3157 ; CHECK-NEXT: ldr q0, [x0]
3158 ; CHECK-NEXT: ldr q1, [x1]
3159 ; CHECK-NEXT: ushr.4s v0, v0, #1
3160 ; CHECK-NEXT: orr.16b v0, v0, v1
3161 ; CHECK-NEXT: ret
3162 %tmp1 = load <4 x i32>, ptr %A
3163 %tmp4 = load <4 x i32>, ptr %B
3164 %tmp3 = lshr <4 x i32> %tmp1, <i32 1, i32 1, i32 1, i32 1>
3165 %tmp5 = or <4 x i32> %tmp3, %tmp4
3166 ret <4 x i32> %tmp5
3167 }
3169 define <2 x i64> @shr_orr2d(ptr %A, ptr %B) nounwind {
3170 ; CHECK-LABEL: shr_orr2d:
3171 ; CHECK: // %bb.0:
3172 ; CHECK-NEXT: ldr q0, [x0]
3173 ; CHECK-NEXT: ldr q1, [x1]
3174 ; CHECK-NEXT: ushr.2d v0, v0, #1
3175 ; CHECK-NEXT: orr.16b v0, v0, v1
3176 ; CHECK-NEXT: ret
3177 %tmp1 = load <2 x i64>, ptr %A
3178 %tmp4 = load <2 x i64>, ptr %B
3179 %tmp3 = lshr <2 x i64> %tmp1, <i64 1, i64 1>
3180 %tmp5 = or <2 x i64> %tmp3, %tmp4
3181 ret <2 x i64> %tmp5
3182 }
3184 define <8 x i8> @shl_orr8b(ptr %A, ptr %B) nounwind {
3185 ; CHECK-LABEL: shl_orr8b:
3186 ; CHECK: // %bb.0:
3187 ; CHECK-NEXT: ldr d0, [x0]
3188 ; CHECK-NEXT: ldr d1, [x1]
3189 ; CHECK-NEXT: add.8b v0, v0, v0
3190 ; CHECK-NEXT: orr.8b v0, v0, v1
3191 ; CHECK-NEXT: ret
3192 %tmp1 = load <8 x i8>, ptr %A
3193 %tmp4 = load <8 x i8>, ptr %B
3194 %tmp3 = shl <8 x i8> %tmp1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
3195 %tmp5 = or <8 x i8> %tmp3, %tmp4
3196 ret <8 x i8> %tmp5
3197 }
3199 define <4 x i16> @shl_orr4h(ptr %A, ptr %B) nounwind {
3200 ; CHECK-LABEL: shl_orr4h:
3201 ; CHECK: // %bb.0:
3202 ; CHECK-NEXT: ldr d0, [x0]
3203 ; CHECK-NEXT: ldr d1, [x1]
3204 ; CHECK-NEXT: add.4h v0, v0, v0
3205 ; CHECK-NEXT: orr.8b v0, v0, v1
3206 ; CHECK-NEXT: ret
3207 %tmp1 = load <4 x i16>, ptr %A
3208 %tmp4 = load <4 x i16>, ptr %B
3209 %tmp3 = shl <4 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1>
3210 %tmp5 = or <4 x i16> %tmp3, %tmp4
3211 ret <4 x i16> %tmp5
3212 }
3214 define <2 x i32> @shl_orr2s(ptr %A, ptr %B) nounwind {
3215 ; CHECK-LABEL: shl_orr2s:
3216 ; CHECK: // %bb.0:
3217 ; CHECK-NEXT: ldr d0, [x0]
3218 ; CHECK-NEXT: ldr d1, [x1]
3219 ; CHECK-NEXT: add.2s v0, v0, v0
3220 ; CHECK-NEXT: orr.8b v0, v0, v1
3221 ; CHECK-NEXT: ret
3222 %tmp1 = load <2 x i32>, ptr %A
3223 %tmp4 = load <2 x i32>, ptr %B
3224 %tmp3 = shl <2 x i32> %tmp1, <i32 1, i32 1>
3225 %tmp5 = or <2 x i32> %tmp3, %tmp4
3226 ret <2 x i32> %tmp5
3227 }
3229 define <16 x i8> @shl_orr16b(ptr %A, ptr %B) nounwind {
3230 ; CHECK-LABEL: shl_orr16b:
3231 ; CHECK: // %bb.0:
3232 ; CHECK-NEXT: ldr q0, [x0]
3233 ; CHECK-NEXT: ldr q1, [x1]
3234 ; CHECK-NEXT: add.16b v0, v0, v0
3235 ; CHECK-NEXT: orr.16b v0, v0, v1
3236 ; CHECK-NEXT: ret
3237 %tmp1 = load <16 x i8>, ptr %A
3238 %tmp4 = load <16 x i8>, ptr %B
3239 %tmp3 = shl <16 x i8> %tmp1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
3240 %tmp5 = or <16 x i8> %tmp3, %tmp4
3241 ret <16 x i8> %tmp5
3242 }
3244 define <8 x i16> @shl_orr8h(ptr %A, ptr %B) nounwind {
3245 ; CHECK-LABEL: shl_orr8h:
3246 ; CHECK: // %bb.0:
3247 ; CHECK-NEXT: ldr q0, [x0]
3248 ; CHECK-NEXT: ldr q1, [x1]
3249 ; CHECK-NEXT: add.8h v0, v0, v0
3250 ; CHECK-NEXT: orr.16b v0, v0, v1
3251 ; CHECK-NEXT: ret
3252 %tmp1 = load <8 x i16>, ptr %A
3253 %tmp4 = load <8 x i16>, ptr %B
3254 %tmp3 = shl <8 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
3255 %tmp5 = or <8 x i16> %tmp3, %tmp4
3256 ret <8 x i16> %tmp5
3257 }
3259 define <4 x i32> @shl_orr4s(ptr %A, ptr %B) nounwind {
3260 ; CHECK-LABEL: shl_orr4s:
3261 ; CHECK: // %bb.0:
3262 ; CHECK-NEXT: ldr q0, [x0]
3263 ; CHECK-NEXT: ldr q1, [x1]
3264 ; CHECK-NEXT: add.4s v0, v0, v0
3265 ; CHECK-NEXT: orr.16b v0, v0, v1
3266 ; CHECK-NEXT: ret
3267 %tmp1 = load <4 x i32>, ptr %A
3268 %tmp4 = load <4 x i32>, ptr %B
3269 %tmp3 = shl <4 x i32> %tmp1, <i32 1, i32 1, i32 1, i32 1>
3270 %tmp5 = or <4 x i32> %tmp3, %tmp4
3271 ret <4 x i32> %tmp5
3272 }
3274 define <2 x i64> @shl_orr2d(ptr %A, ptr %B) nounwind {
3275 ; CHECK-LABEL: shl_orr2d:
3276 ; CHECK: // %bb.0:
3277 ; CHECK-NEXT: ldr q0, [x0]
3278 ; CHECK-NEXT: ldr q1, [x1]
3279 ; CHECK-NEXT: add.2d v0, v0, v0
3280 ; CHECK-NEXT: orr.16b v0, v0, v1
3281 ; CHECK-NEXT: ret
3282 %tmp1 = load <2 x i64>, ptr %A
3283 %tmp4 = load <2 x i64>, ptr %B
3284 %tmp3 = shl <2 x i64> %tmp1, <i64 1, i64 1>
3285 %tmp5 = or <2 x i64> %tmp3, %tmp4
3286 ret <2 x i64> %tmp5
3287 }
3289 define <8 x i16> @shll(<8 x i8> %in) {
3290 ; CHECK-LABEL: shll:
3291 ; CHECK: // %bb.0:
3292 ; CHECK-NEXT: shll.8h v0, v0, #8
3293 ; CHECK-NEXT: ret
3294 %ext = zext <8 x i8> %in to <8 x i16>
3295 %res = shl <8 x i16> %ext, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
3296 ret <8 x i16> %res
3297 }
3299 define <4 x i32> @shll_high(<8 x i16> %in) {
3300 ; CHECK-LABEL: shll_high:
3301 ; CHECK: // %bb.0:
3302 ; CHECK-NEXT: shll2.4s v0, v0, #16
3303 ; CHECK-NEXT: ret
3304 %extract = shufflevector <8 x i16> %in, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
3305 %ext = zext <4 x i16> %extract to <4 x i32>
3306 %res = shl <4 x i32> %ext, <i32 16, i32 16, i32 16, i32 16>
3307 ret <4 x i32> %res
3308 }
3310 define <8 x i8> @sli8b(ptr %A, ptr %B) nounwind {
3311 ; CHECK-LABEL: sli8b:
3312 ; CHECK: // %bb.0:
3313 ; CHECK-NEXT: ldr d0, [x0]
3314 ; CHECK-NEXT: ldr d1, [x1]
3315 ; CHECK-NEXT: sli.8b v0, v1, #1
3316 ; CHECK-NEXT: ret
3317 %tmp1 = load <8 x i8>, ptr %A
3318 %tmp2 = load <8 x i8>, ptr %B
3319 %tmp3 = call <8 x i8> @llvm.aarch64.neon.vsli.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2, i32 1)
3320 ret <8 x i8> %tmp3
3321 }
3323 define <4 x i16> @sli4h(ptr %A, ptr %B) nounwind {
3324 ; CHECK-LABEL: sli4h:
3325 ; CHECK: // %bb.0:
3326 ; CHECK-NEXT: ldr d0, [x0]
3327 ; CHECK-NEXT: ldr d1, [x1]
3328 ; CHECK-NEXT: sli.4h v0, v1, #1
3329 ; CHECK-NEXT: ret
3330 %tmp1 = load <4 x i16>, ptr %A
3331 %tmp2 = load <4 x i16>, ptr %B
3332 %tmp3 = call <4 x i16> @llvm.aarch64.neon.vsli.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2, i32 1)
3333 ret <4 x i16> %tmp3
3334 }
3336 define <2 x i32> @sli2s(ptr %A, ptr %B) nounwind {
3337 ; CHECK-LABEL: sli2s:
3338 ; CHECK: // %bb.0:
3339 ; CHECK-NEXT: ldr d0, [x0]
3340 ; CHECK-NEXT: ldr d1, [x1]
3341 ; CHECK-NEXT: sli.2s v0, v1, #1
3342 ; CHECK-NEXT: ret
3343 %tmp1 = load <2 x i32>, ptr %A
3344 %tmp2 = load <2 x i32>, ptr %B
3345 %tmp3 = call <2 x i32> @llvm.aarch64.neon.vsli.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2, i32 1)
3346 ret <2 x i32> %tmp3
3347 }
3349 define <1 x i64> @sli1d(ptr %A, ptr %B) nounwind {
3350 ; CHECK-LABEL: sli1d:
3351 ; CHECK: // %bb.0:
3352 ; CHECK-NEXT: ldr d0, [x0]
3353 ; CHECK-NEXT: ldr d1, [x1]
3354 ; CHECK-NEXT: sli d0, d1, #1
3355 ; CHECK-NEXT: ret
3356 %tmp1 = load <1 x i64>, ptr %A
3357 %tmp2 = load <1 x i64>, ptr %B
3358 %tmp3 = call <1 x i64> @llvm.aarch64.neon.vsli.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2, i32 1)
3359 ret <1 x i64> %tmp3
3360 }
3362 define <16 x i8> @sli16b(ptr %A, ptr %B) nounwind {
3363 ; CHECK-LABEL: sli16b:
3364 ; CHECK: // %bb.0:
3365 ; CHECK-NEXT: ldr q0, [x0]
3366 ; CHECK-NEXT: ldr q1, [x1]
3367 ; CHECK-NEXT: sli.16b v0, v1, #1
3368 ; CHECK-NEXT: ret
3369 %tmp1 = load <16 x i8>, ptr %A
3370 %tmp2 = load <16 x i8>, ptr %B
3371 %tmp3 = call <16 x i8> @llvm.aarch64.neon.vsli.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2, i32 1)
3372 ret <16 x i8> %tmp3
3373 }
3375 define <8 x i16> @sli8h(ptr %A, ptr %B) nounwind {
3376 ; CHECK-LABEL: sli8h:
3377 ; CHECK: // %bb.0:
3378 ; CHECK-NEXT: ldr q0, [x0]
3379 ; CHECK-NEXT: ldr q1, [x1]
3380 ; CHECK-NEXT: sli.8h v0, v1, #1
3381 ; CHECK-NEXT: ret
3382 %tmp1 = load <8 x i16>, ptr %A
3383 %tmp2 = load <8 x i16>, ptr %B
3384 %tmp3 = call <8 x i16> @llvm.aarch64.neon.vsli.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2, i32 1)
3385 ret <8 x i16> %tmp3
3386 }
3388 define <4 x i32> @sli4s(ptr %A, ptr %B) nounwind {
3389 ; CHECK-LABEL: sli4s:
3390 ; CHECK: // %bb.0:
3391 ; CHECK-NEXT: ldr q0, [x0]
3392 ; CHECK-NEXT: ldr q1, [x1]
3393 ; CHECK-NEXT: sli.4s v0, v1, #1
3394 ; CHECK-NEXT: ret
3395 %tmp1 = load <4 x i32>, ptr %A
3396 %tmp2 = load <4 x i32>, ptr %B
3397 %tmp3 = call <4 x i32> @llvm.aarch64.neon.vsli.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2, i32 1)
3398 ret <4 x i32> %tmp3
3399 }
3401 define <2 x i64> @sli2d(ptr %A, ptr %B) nounwind {
3402 ; CHECK-LABEL: sli2d:
3403 ; CHECK: // %bb.0:
3404 ; CHECK-NEXT: ldr q0, [x0]
3405 ; CHECK-NEXT: ldr q1, [x1]
3406 ; CHECK-NEXT: sli.2d v0, v1, #1
3407 ; CHECK-NEXT: ret
3408 %tmp1 = load <2 x i64>, ptr %A
3409 %tmp2 = load <2 x i64>, ptr %B
3410 %tmp3 = call <2 x i64> @llvm.aarch64.neon.vsli.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2, i32 1)
3411 ret <2 x i64> %tmp3
3412 }
3414 declare <8 x i8> @llvm.aarch64.neon.vsli.v8i8(<8 x i8>, <8 x i8>, i32) nounwind readnone
3415 declare <4 x i16> @llvm.aarch64.neon.vsli.v4i16(<4 x i16>, <4 x i16>, i32) nounwind readnone
3416 declare <2 x i32> @llvm.aarch64.neon.vsli.v2i32(<2 x i32>, <2 x i32>, i32) nounwind readnone
3417 declare <1 x i64> @llvm.aarch64.neon.vsli.v1i64(<1 x i64>, <1 x i64>, i32) nounwind readnone
3419 declare <16 x i8> @llvm.aarch64.neon.vsli.v16i8(<16 x i8>, <16 x i8>, i32) nounwind readnone
3420 declare <8 x i16> @llvm.aarch64.neon.vsli.v8i16(<8 x i16>, <8 x i16>, i32) nounwind readnone
3421 declare <4 x i32> @llvm.aarch64.neon.vsli.v4i32(<4 x i32>, <4 x i32>, i32) nounwind readnone
3422 declare <2 x i64> @llvm.aarch64.neon.vsli.v2i64(<2 x i64>, <2 x i64>, i32) nounwind readnone
3424 define <1 x i64> @ashr_v1i64(<1 x i64> %a, <1 x i64> %b) {
3425 ; CHECK-LABEL: ashr_v1i64:
3426 ; CHECK: // %bb.0:
3427 ; CHECK-NEXT: neg d1, d1
3428 ; CHECK-NEXT: sshl d0, d0, d1
3429 ; CHECK-NEXT: ret
3430 %c = ashr <1 x i64> %a, %b
3431 ret <1 x i64> %c
3432 }
3434 define void @sqshl_zero_shift_amount(<2 x i64> %a, <2 x i64> %b, ptr %dst) {
3435 ; CHECK-LABEL: sqshl_zero_shift_amount:
3436 ; CHECK: // %bb.0: // %entry
3437 ; CHECK-NEXT: addp.2d v0, v0, v1
3438 ; CHECK-NEXT: str q0, [x0]
3439 ; CHECK-NEXT: ret
3440 entry:
3441 %vpaddq_v2.i.i = tail call <2 x i64> @llvm.aarch64.neon.addp.v2i64(<2 x i64> %a, <2 x i64> %b)
3442 %vshlq_v2.i.i = tail call <2 x i64> @llvm.aarch64.neon.sqshl.v2i64(<2 x i64> %vpaddq_v2.i.i, <2 x i64> zeroinitializer)
3443 store <2 x i64> %vshlq_v2.i.i, ptr %dst, align 8
3444 ret void
3445 }
3447 define void @uqshl_zero_shift_amount(<2 x i64> %a, <2 x i64> %b, ptr %dst) {
3448 ; CHECK-LABEL: uqshl_zero_shift_amount:
3449 ; CHECK: // %bb.0: // %entry
3450 ; CHECK-NEXT: addp.2d v0, v0, v1
3451 ; CHECK-NEXT: str q0, [x0]
3452 ; CHECK-NEXT: ret
3453 entry:
3454 %vpaddq_v2.i.i = tail call <2 x i64> @llvm.aarch64.neon.addp.v2i64(<2 x i64> %a, <2 x i64> %b)
3455 %vshlq_v2.i.i = tail call <2 x i64> @llvm.aarch64.neon.uqshl.v2i64(<2 x i64> %vpaddq_v2.i.i, <2 x i64> zeroinitializer)
3456 store <2 x i64> %vshlq_v2.i.i, ptr %dst, align 8
3457 ret void
3458 }
3460 define void @srshl_zero_shift_amount(<2 x i64> %a, <2 x i64> %b, ptr %dst) {
3461 ; CHECK-LABEL: srshl_zero_shift_amount:
3462 ; CHECK: // %bb.0: // %entry
3463 ; CHECK-NEXT: addp.2d v0, v0, v1
3464 ; CHECK-NEXT: str q0, [x0]
3465 ; CHECK-NEXT: ret
3466 entry:
3467 %vpaddq_v2.i.i = tail call <2 x i64> @llvm.aarch64.neon.addp.v2i64(<2 x i64> %a, <2 x i64> %b)
3468 %vshlq_v2.i.i = tail call <2 x i64> @llvm.aarch64.neon.srshl.v2i64(<2 x i64> %vpaddq_v2.i.i, <2 x i64> zeroinitializer)
3469 store <2 x i64> %vshlq_v2.i.i, ptr %dst, align 8
3470 ret void
3471 }
3473 define void @urshl_zero_shift_amount(<2 x i64> %a, <2 x i64> %b, ptr %dst) {
3474 ; CHECK-LABEL: urshl_zero_shift_amount:
3475 ; CHECK: // %bb.0: // %entry
3476 ; CHECK-NEXT: addp.2d v0, v0, v1
3477 ; CHECK-NEXT: str q0, [x0]
3478 ; CHECK-NEXT: ret
3479 entry:
3480 %vpaddq_v2.i.i = tail call <2 x i64> @llvm.aarch64.neon.addp.v2i64(<2 x i64> %a, <2 x i64> %b)
3481 %vshlq_v2.i.i = tail call <2 x i64> @llvm.aarch64.neon.urshl.v2i64(<2 x i64> %vpaddq_v2.i.i, <2 x i64> zeroinitializer)
3482 store <2 x i64> %vshlq_v2.i.i, ptr %dst, align 8
3483 ret void
3484 }
3486 define void @sqshlu_zero_shift_amount(<2 x i64> %a, <2 x i64> %b, ptr %dst) {
3487 ; CHECK-LABEL: sqshlu_zero_shift_amount:
3488 ; CHECK: // %bb.0: // %entry
3489 ; CHECK-NEXT: addp.2d v0, v0, v1
3490 ; CHECK-NEXT: sqshlu.2d v0, v0, #0
3491 ; CHECK-NEXT: str q0, [x0]
3492 ; CHECK-NEXT: ret
3493 entry:
3494 %vpaddq_v2.i.i = tail call <2 x i64> @llvm.aarch64.neon.addp.v2i64(<2 x i64> %a, <2 x i64> %b)
3495 %vshlq_v2.i.i = tail call <2 x i64> @llvm.aarch64.neon.sqshlu.v2i64(<2 x i64> %vpaddq_v2.i.i, <2 x i64> zeroinitializer)
3496 store <2 x i64> %vshlq_v2.i.i, ptr %dst, align 8
3497 ret void
3498 }
3500 define void @sshl_zero_shift_amount(<2 x i64> %a, <2 x i64> %b, ptr %dst) {
3501 ; CHECK-LABEL: sshl_zero_shift_amount:
3502 ; CHECK: // %bb.0: // %entry
3503 ; CHECK-NEXT: addp.2d v0, v0, v1
3504 ; CHECK-NEXT: str q0, [x0]
3505 ; CHECK-NEXT: ret
3506 entry:
3507 %vpaddq_v2.i.i = tail call <2 x i64> @llvm.aarch64.neon.addp.v2i64(<2 x i64> %a, <2 x i64> %b)
3508 %vshlq_v2.i.i = tail call <2 x i64> @llvm.aarch64.neon.sshl.v2i64(<2 x i64> %vpaddq_v2.i.i, <2 x i64> zeroinitializer)
3509 store <2 x i64> %vshlq_v2.i.i, ptr %dst, align 8
3510 ret void
3511 }
3513 define void @ushl_zero_shift_amount(<2 x i64> %a, <2 x i64> %b, ptr %dst) {
3514 ; CHECK-LABEL: ushl_zero_shift_amount:
3515 ; CHECK: // %bb.0: // %entry
3516 ; CHECK-NEXT: addp.2d v0, v0, v1
3517 ; CHECK-NEXT: str q0, [x0]
3518 ; CHECK-NEXT: ret
3519 entry:
3520 %vpaddq_v2.i.i = tail call <2 x i64> @llvm.aarch64.neon.addp.v2i64(<2 x i64> %a, <2 x i64> %b)
3521 %vshlq_v2.i.i = tail call <2 x i64> @llvm.aarch64.neon.ushl.v2i64(<2 x i64> %vpaddq_v2.i.i, <2 x i64> zeroinitializer)
3522 store <2 x i64> %vshlq_v2.i.i, ptr %dst, align 8
3523 ret void
3524 }
3526 define <4 x i32> @sext_rshrn(<4 x i32> noundef %a) {
3527 ; CHECK-LABEL: sext_rshrn:
3528 ; CHECK: // %bb.0: // %entry
3529 ; CHECK-NEXT: rshrn.4h v0, v0, #13
3530 ; CHECK-NEXT: sshll.4s v0, v0, #0
3531 ; CHECK-NEXT: ret
3532 entry:
3533 %vrshrn_n1 = tail call <4 x i16> @llvm.aarch64.neon.rshrn.v4i16(<4 x i32> %a, i32 13)
3534 %vmovl.i = sext <4 x i16> %vrshrn_n1 to <4 x i32>
3535 ret <4 x i32> %vmovl.i
3536 }
3538 define <4 x i32> @zext_rshrn(<4 x i32> noundef %a) {
3539 ; CHECK-LABEL: zext_rshrn:
3540 ; CHECK: // %bb.0: // %entry
3541 ; CHECK-NEXT: rshrn.4h v0, v0, #13
3542 ; CHECK-NEXT: ushll.4s v0, v0, #0
3543 ; CHECK-NEXT: ret
3544 entry:
3545 %vrshrn_n1 = tail call <4 x i16> @llvm.aarch64.neon.rshrn.v4i16(<4 x i32> %a, i32 13)
3546 %vmovl.i = zext <4 x i16> %vrshrn_n1 to <4 x i32>
3547 ret <4 x i32> %vmovl.i
3548 }
3550 define <4 x i16> @mul_rshrn(<4 x i32> noundef %a) {
3551 ; CHECK-LABEL: mul_rshrn:
3552 ; CHECK: // %bb.0: // %entry
3553 ; CHECK-NEXT: movi.4s v1, #3
3554 ; CHECK-NEXT: add.4s v0, v0, v1
3555 ; CHECK-NEXT: rshrn.4h v0, v0, #13
3556 ; CHECK-NEXT: ret
3557 entry:
3558 %b = add <4 x i32> %a, <i32 3, i32 3, i32 3, i32 3>
3559 %vrshrn_n1 = tail call <4 x i16> @llvm.aarch64.neon.rshrn.v4i16(<4 x i32> %b, i32 13)
3560 ret <4 x i16> %vrshrn_n1
3561 }
3563 declare <2 x i64> @llvm.aarch64.neon.addp.v2i64(<2 x i64>, <2 x i64>)