| blob | 3b1f19af90219dd4995a6f89456cf0b1fdb1abf2 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s
3 ; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s
6 target triple = "aarch64-unknown-linux-gnu"
8 define i1 @ptest_v16i1(ptr %a, ptr %b) {
9 ; CHECK-LABEL: ptest_v16i1:
10 ; CHECK: // %bb.0:
11 ; CHECK-NEXT: ptrue p0.s, vl4
12 ; CHECK-NEXT: ldp q1, q0, [x0, #32]
13 ; CHECK-NEXT: ldp q2, q3, [x0]
14 ; CHECK-NEXT: fcmne p1.s, p0/z, z0.s, #0.0
15 ; CHECK-NEXT: fcmne p2.s, p0/z, z1.s, #0.0
16 ; CHECK-NEXT: fcmne p3.s, p0/z, z3.s, #0.0
17 ; CHECK-NEXT: fcmne p0.s, p0/z, z2.s, #0.0
18 ; CHECK-NEXT: mov z0.s, p1/z, #-1 // =0xffffffffffffffff
19 ; CHECK-NEXT: mov z1.s, p2/z, #-1 // =0xffffffffffffffff
20 ; CHECK-NEXT: mov z2.s, p3/z, #-1 // =0xffffffffffffffff
21 ; CHECK-NEXT: mov z3.s, p0/z, #-1 // =0xffffffffffffffff
22 ; CHECK-NEXT: ptrue p0.h, vl4
23 ; CHECK-NEXT: ptrue p1.b, vl16
24 ; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h
25 ; CHECK-NEXT: uzp1 z1.h, z1.h, z1.h
26 ; CHECK-NEXT: uzp1 z2.h, z2.h, z2.h
27 ; CHECK-NEXT: uzp1 z3.h, z3.h, z3.h
28 ; CHECK-NEXT: splice z1.h, p0, z1.h, z0.h
29 ; CHECK-NEXT: splice z3.h, p0, z3.h, z2.h
30 ; CHECK-NEXT: ptrue p0.b, vl8
31 ; CHECK-NEXT: uzp1 z0.b, z1.b, z1.b
32 ; CHECK-NEXT: uzp1 z1.b, z3.b, z3.b
33 ; CHECK-NEXT: splice z1.b, p0, z1.b, z0.b
34 ; CHECK-NEXT: umaxv b0, p1, z1.b
35 ; CHECK-NEXT: fmov w8, s0
36 ; CHECK-NEXT: and w0, w8, #0x1
37 ; CHECK-NEXT: ret
38 %v0 = bitcast ptr %a to <16 x float>*
39 %v1 = load <16 x float>, <16 x float>* %v0, align 4
40 %v2 = fcmp une <16 x float> %v1, zeroinitializer
41 %v3 = call i1 @llvm.vector.reduce.or.i1.v16i1 (<16 x i1> %v2)
42 ret i1 %v3
43 }
45 define i1 @ptest_or_v16i1(ptr %a, ptr %b) {
46 ; CHECK-LABEL: ptest_or_v16i1:
47 ; CHECK: // %bb.0:
48 ; CHECK-NEXT: ptrue p0.s, vl4
49 ; CHECK-NEXT: ldp q0, q1, [x0]
50 ; CHECK-NEXT: ldp q2, q3, [x0, #32]
51 ; CHECK-NEXT: ldp q4, q5, [x1]
52 ; CHECK-NEXT: ldp q6, q7, [x1, #32]
53 ; CHECK-NEXT: fcmne p1.s, p0/z, z3.s, #0.0
54 ; CHECK-NEXT: fcmne p2.s, p0/z, z2.s, #0.0
55 ; CHECK-NEXT: fcmne p3.s, p0/z, z1.s, #0.0
56 ; CHECK-NEXT: fcmne p4.s, p0/z, z0.s, #0.0
57 ; CHECK-NEXT: fcmne p5.s, p0/z, z7.s, #0.0
58 ; CHECK-NEXT: fcmne p6.s, p0/z, z6.s, #0.0
59 ; CHECK-NEXT: fcmne p7.s, p0/z, z5.s, #0.0
60 ; CHECK-NEXT: fcmne p0.s, p0/z, z4.s, #0.0
61 ; CHECK-NEXT: mov z0.s, p1/z, #-1 // =0xffffffffffffffff
62 ; CHECK-NEXT: mov z1.s, p2/z, #-1 // =0xffffffffffffffff
63 ; CHECK-NEXT: mov z2.s, p3/z, #-1 // =0xffffffffffffffff
64 ; CHECK-NEXT: mov z3.s, p4/z, #-1 // =0xffffffffffffffff
65 ; CHECK-NEXT: mov z4.s, p5/z, #-1 // =0xffffffffffffffff
66 ; CHECK-NEXT: mov z5.s, p6/z, #-1 // =0xffffffffffffffff
67 ; CHECK-NEXT: mov z6.s, p7/z, #-1 // =0xffffffffffffffff
68 ; CHECK-NEXT: mov z7.s, p0/z, #-1 // =0xffffffffffffffff
69 ; CHECK-NEXT: ptrue p1.h, vl4
70 ; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h
71 ; CHECK-NEXT: uzp1 z1.h, z1.h, z1.h
72 ; CHECK-NEXT: uzp1 z2.h, z2.h, z2.h
73 ; CHECK-NEXT: uzp1 z3.h, z3.h, z3.h
74 ; CHECK-NEXT: uzp1 z4.h, z4.h, z4.h
75 ; CHECK-NEXT: uzp1 z5.h, z5.h, z5.h
76 ; CHECK-NEXT: uzp1 z6.h, z6.h, z6.h
77 ; CHECK-NEXT: uzp1 z7.h, z7.h, z7.h
78 ; CHECK-NEXT: ptrue p0.b, vl8
79 ; CHECK-NEXT: splice z1.h, p1, z1.h, z0.h
80 ; CHECK-NEXT: splice z3.h, p1, z3.h, z2.h
81 ; CHECK-NEXT: splice z5.h, p1, z5.h, z4.h
82 ; CHECK-NEXT: splice z7.h, p1, z7.h, z6.h
83 ; CHECK-NEXT: uzp1 z0.b, z1.b, z1.b
84 ; CHECK-NEXT: uzp1 z1.b, z3.b, z3.b
85 ; CHECK-NEXT: uzp1 z2.b, z5.b, z5.b
86 ; CHECK-NEXT: uzp1 z3.b, z7.b, z7.b
87 ; CHECK-NEXT: splice z1.b, p0, z1.b, z0.b
88 ; CHECK-NEXT: splice z3.b, p0, z3.b, z2.b
89 ; CHECK-NEXT: ptrue p0.b, vl16
90 ; CHECK-NEXT: orr z0.d, z1.d, z3.d
91 ; CHECK-NEXT: umaxv b0, p0, z0.b
92 ; CHECK-NEXT: fmov w8, s0
93 ; CHECK-NEXT: and w0, w8, #0x1
94 ; CHECK-NEXT: ret
95 %v0 = bitcast ptr %a to <16 x float>*
96 %v1 = load <16 x float>, <16 x float>* %v0, align 4
97 %v2 = fcmp une <16 x float> %v1, zeroinitializer
98 %v3 = bitcast float* %b to <16 x float>*
99 %v4 = load <16 x float>, <16 x float>* %v3, align 4
100 %v5 = fcmp une <16 x float> %v4, zeroinitializer
101 %v6 = or <16 x i1> %v2, %v5
102 %v7 = call i1 @llvm.vector.reduce.or.i1.v16i1 (<16 x i1> %v6)
103 ret i1 %v7
104 }
106 declare i1 @llvm.vector.reduce.or.i1.v16i1(<16 x i1>)
108 ;
109 ; AND reduction.
110 ;
112 define i1 @ptest_and_v16i1(ptr %a, ptr %b) {
113 ; CHECK-LABEL: ptest_and_v16i1:
114 ; CHECK: // %bb.0:
115 ; CHECK-NEXT: ptrue p0.s, vl4
116 ; CHECK-NEXT: ldp q0, q1, [x0]
117 ; CHECK-NEXT: ldp q2, q3, [x0, #32]
118 ; CHECK-NEXT: ldp q4, q5, [x1]
119 ; CHECK-NEXT: ldp q6, q7, [x1, #32]
120 ; CHECK-NEXT: fcmne p1.s, p0/z, z3.s, #0.0
121 ; CHECK-NEXT: fcmne p2.s, p0/z, z2.s, #0.0
122 ; CHECK-NEXT: fcmne p3.s, p0/z, z1.s, #0.0
123 ; CHECK-NEXT: fcmne p4.s, p0/z, z0.s, #0.0
124 ; CHECK-NEXT: fcmne p5.s, p0/z, z7.s, #0.0
125 ; CHECK-NEXT: fcmne p6.s, p0/z, z6.s, #0.0
126 ; CHECK-NEXT: fcmne p7.s, p0/z, z5.s, #0.0
127 ; CHECK-NEXT: fcmne p0.s, p0/z, z4.s, #0.0
128 ; CHECK-NEXT: mov z0.s, p1/z, #-1 // =0xffffffffffffffff
129 ; CHECK-NEXT: mov z1.s, p2/z, #-1 // =0xffffffffffffffff
130 ; CHECK-NEXT: mov z2.s, p3/z, #-1 // =0xffffffffffffffff
131 ; CHECK-NEXT: mov z3.s, p4/z, #-1 // =0xffffffffffffffff
132 ; CHECK-NEXT: mov z4.s, p5/z, #-1 // =0xffffffffffffffff
133 ; CHECK-NEXT: mov z5.s, p6/z, #-1 // =0xffffffffffffffff
134 ; CHECK-NEXT: mov z6.s, p7/z, #-1 // =0xffffffffffffffff
135 ; CHECK-NEXT: mov z7.s, p0/z, #-1 // =0xffffffffffffffff
136 ; CHECK-NEXT: ptrue p1.h, vl4
137 ; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h
138 ; CHECK-NEXT: uzp1 z1.h, z1.h, z1.h
139 ; CHECK-NEXT: uzp1 z2.h, z2.h, z2.h
140 ; CHECK-NEXT: uzp1 z3.h, z3.h, z3.h
141 ; CHECK-NEXT: uzp1 z4.h, z4.h, z4.h
142 ; CHECK-NEXT: uzp1 z5.h, z5.h, z5.h
143 ; CHECK-NEXT: uzp1 z6.h, z6.h, z6.h
144 ; CHECK-NEXT: uzp1 z7.h, z7.h, z7.h
145 ; CHECK-NEXT: ptrue p0.b, vl8
146 ; CHECK-NEXT: splice z1.h, p1, z1.h, z0.h
147 ; CHECK-NEXT: splice z3.h, p1, z3.h, z2.h
148 ; CHECK-NEXT: splice z5.h, p1, z5.h, z4.h
149 ; CHECK-NEXT: splice z7.h, p1, z7.h, z6.h
150 ; CHECK-NEXT: uzp1 z0.b, z1.b, z1.b
151 ; CHECK-NEXT: uzp1 z1.b, z3.b, z3.b
152 ; CHECK-NEXT: uzp1 z2.b, z5.b, z5.b
153 ; CHECK-NEXT: uzp1 z3.b, z7.b, z7.b
154 ; CHECK-NEXT: splice z1.b, p0, z1.b, z0.b
155 ; CHECK-NEXT: splice z3.b, p0, z3.b, z2.b
156 ; CHECK-NEXT: ptrue p0.b, vl16
157 ; CHECK-NEXT: and z0.d, z1.d, z3.d
158 ; CHECK-NEXT: uminv b0, p0, z0.b
159 ; CHECK-NEXT: fmov w8, s0
160 ; CHECK-NEXT: and w0, w8, #0x1
161 ; CHECK-NEXT: ret
162 %v0 = bitcast ptr %a to <16 x float>*
163 %v1 = load <16 x float>, <16 x float>* %v0, align 4
164 %v2 = fcmp une <16 x float> %v1, zeroinitializer
165 %v3 = bitcast float* %b to <16 x float>*
166 %v4 = load <16 x float>, <16 x float>* %v3, align 4
167 %v5 = fcmp une <16 x float> %v4, zeroinitializer
168 %v6 = and <16 x i1> %v2, %v5
169 %v7 = call i1 @llvm.vector.reduce.and.i1.v16i1 (<16 x i1> %v6)
170 ret i1 %v7
171 }
173 declare i1 @llvm.vector.reduce.and.i1.v16i1(<16 x i1>)