| blob | 9c46cf69cb0bfc5a4e7ab9836d29601896c4b07d |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=aarch64 -mattr=+neon | FileCheck %s
3 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=aarch64 -mattr=+neon | FileCheck %s
5 define <1 x i64> @lrint_v1f16(<1 x half> %x) {
6 ; CHECK-LABEL: lrint_v1f16:
7 ; CHECK: // %bb.0:
8 ; CHECK-NEXT: fcvt s0, h0
9 ; CHECK-NEXT: frintx s0, s0
10 ; CHECK-NEXT: fcvtzs x8, s0
11 ; CHECK-NEXT: fmov d0, x8
12 ; CHECK-NEXT: ret
13 %a = call <1 x i64> @llvm.lrint.v1i64.v1f16(<1 x half> %x)
14 ret <1 x i64> %a
15 }
16 declare <1 x i64> @llvm.lrint.v1i64.v1f16(<1 x half>)
18 define <2 x i64> @lrint_v2f16(<2 x half> %x) {
19 ; CHECK-LABEL: lrint_v2f16:
20 ; CHECK: // %bb.0:
21 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
22 ; CHECK-NEXT: mov h1, v0.h[1]
23 ; CHECK-NEXT: fcvt s0, h0
24 ; CHECK-NEXT: fcvt s1, h1
25 ; CHECK-NEXT: frintx s0, s0
26 ; CHECK-NEXT: frintx s1, s1
27 ; CHECK-NEXT: fcvtzs x8, s0
28 ; CHECK-NEXT: fcvtzs x9, s1
29 ; CHECK-NEXT: fmov d0, x8
30 ; CHECK-NEXT: mov v0.d[1], x9
31 ; CHECK-NEXT: ret
32 %a = call <2 x i64> @llvm.lrint.v2i64.v2f16(<2 x half> %x)
33 ret <2 x i64> %a
34 }
35 declare <2 x i64> @llvm.lrint.v2i64.v2f16(<2 x half>)
37 define <4 x i64> @lrint_v4f16(<4 x half> %x) {
38 ; CHECK-LABEL: lrint_v4f16:
39 ; CHECK: // %bb.0:
40 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
41 ; CHECK-NEXT: mov h1, v0.h[2]
42 ; CHECK-NEXT: mov h2, v0.h[1]
43 ; CHECK-NEXT: mov h3, v0.h[3]
44 ; CHECK-NEXT: fcvt s0, h0
45 ; CHECK-NEXT: fcvt s1, h1
46 ; CHECK-NEXT: fcvt s2, h2
47 ; CHECK-NEXT: fcvt s3, h3
48 ; CHECK-NEXT: frintx s0, s0
49 ; CHECK-NEXT: frintx s1, s1
50 ; CHECK-NEXT: frintx s2, s2
51 ; CHECK-NEXT: frintx s3, s3
52 ; CHECK-NEXT: fcvtzs x8, s0
53 ; CHECK-NEXT: fcvtzs x9, s1
54 ; CHECK-NEXT: fcvtzs x10, s2
55 ; CHECK-NEXT: fcvtzs x11, s3
56 ; CHECK-NEXT: fmov d0, x8
57 ; CHECK-NEXT: fmov d1, x9
58 ; CHECK-NEXT: mov v0.d[1], x10
59 ; CHECK-NEXT: mov v1.d[1], x11
60 ; CHECK-NEXT: ret
61 %a = call <4 x i64> @llvm.lrint.v4i64.v4f16(<4 x half> %x)
62 ret <4 x i64> %a
63 }
64 declare <4 x i64> @llvm.lrint.v4i64.v4f16(<4 x half>)
66 define <8 x i64> @lrint_v8f16(<8 x half> %x) {
67 ; CHECK-LABEL: lrint_v8f16:
68 ; CHECK: // %bb.0:
69 ; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
70 ; CHECK-NEXT: mov h4, v0.h[2]
71 ; CHECK-NEXT: mov h3, v0.h[1]
72 ; CHECK-NEXT: mov h7, v0.h[3]
73 ; CHECK-NEXT: fcvt s0, h0
74 ; CHECK-NEXT: mov h2, v1.h[2]
75 ; CHECK-NEXT: mov h5, v1.h[1]
76 ; CHECK-NEXT: mov h6, v1.h[3]
77 ; CHECK-NEXT: fcvt s1, h1
78 ; CHECK-NEXT: fcvt s4, h4
79 ; CHECK-NEXT: fcvt s3, h3
80 ; CHECK-NEXT: fcvt s7, h7
81 ; CHECK-NEXT: frintx s0, s0
82 ; CHECK-NEXT: fcvt s2, h2
83 ; CHECK-NEXT: fcvt s5, h5
84 ; CHECK-NEXT: fcvt s6, h6
85 ; CHECK-NEXT: frintx s1, s1
86 ; CHECK-NEXT: frintx s4, s4
87 ; CHECK-NEXT: frintx s3, s3
88 ; CHECK-NEXT: frintx s7, s7
89 ; CHECK-NEXT: fcvtzs x9, s0
90 ; CHECK-NEXT: frintx s2, s2
91 ; CHECK-NEXT: frintx s5, s5
92 ; CHECK-NEXT: frintx s6, s6
93 ; CHECK-NEXT: fcvtzs x8, s1
94 ; CHECK-NEXT: fcvtzs x12, s4
95 ; CHECK-NEXT: fcvtzs x11, s3
96 ; CHECK-NEXT: fcvtzs x15, s7
97 ; CHECK-NEXT: fmov d0, x9
98 ; CHECK-NEXT: fcvtzs x10, s2
99 ; CHECK-NEXT: fcvtzs x13, s5
100 ; CHECK-NEXT: fcvtzs x14, s6
101 ; CHECK-NEXT: fmov d2, x8
102 ; CHECK-NEXT: fmov d1, x12
103 ; CHECK-NEXT: mov v0.d[1], x11
104 ; CHECK-NEXT: fmov d3, x10
105 ; CHECK-NEXT: mov v2.d[1], x13
106 ; CHECK-NEXT: mov v1.d[1], x15
107 ; CHECK-NEXT: mov v3.d[1], x14
108 ; CHECK-NEXT: ret
109 %a = call <8 x i64> @llvm.lrint.v8i64.v8f16(<8 x half> %x)
110 ret <8 x i64> %a
111 }
112 declare <8 x i64> @llvm.lrint.v8i64.v8f16(<8 x half>)
114 define <16 x i64> @lrint_v16i64_v16f16(<16 x half> %x) {
115 ; CHECK-LABEL: lrint_v16i64_v16f16:
116 ; CHECK: // %bb.0:
117 ; CHECK-NEXT: ext v2.16b, v0.16b, v0.16b, #8
118 ; CHECK-NEXT: ext v3.16b, v1.16b, v1.16b, #8
119 ; CHECK-NEXT: mov h17, v0.h[1]
120 ; CHECK-NEXT: mov h19, v0.h[2]
121 ; CHECK-NEXT: fcvt s18, h0
122 ; CHECK-NEXT: mov h0, v0.h[3]
123 ; CHECK-NEXT: mov h4, v2.h[1]
124 ; CHECK-NEXT: mov h5, v2.h[2]
125 ; CHECK-NEXT: fcvt s7, h3
126 ; CHECK-NEXT: fcvt s6, h2
127 ; CHECK-NEXT: mov h16, v3.h[2]
128 ; CHECK-NEXT: mov h2, v2.h[3]
129 ; CHECK-NEXT: fcvt s17, h17
130 ; CHECK-NEXT: fcvt s19, h19
131 ; CHECK-NEXT: frintx s18, s18
132 ; CHECK-NEXT: fcvt s0, h0
133 ; CHECK-NEXT: fcvt s4, h4
134 ; CHECK-NEXT: fcvt s5, h5
135 ; CHECK-NEXT: frintx s7, s7
136 ; CHECK-NEXT: frintx s6, s6
137 ; CHECK-NEXT: fcvt s16, h16
138 ; CHECK-NEXT: fcvt s2, h2
139 ; CHECK-NEXT: frintx s17, s17
140 ; CHECK-NEXT: frintx s19, s19
141 ; CHECK-NEXT: fcvtzs x13, s18
142 ; CHECK-NEXT: frintx s0, s0
143 ; CHECK-NEXT: frintx s4, s4
144 ; CHECK-NEXT: frintx s5, s5
145 ; CHECK-NEXT: fcvtzs x9, s7
146 ; CHECK-NEXT: mov h7, v1.h[2]
147 ; CHECK-NEXT: fcvtzs x8, s6
148 ; CHECK-NEXT: mov h6, v1.h[1]
149 ; CHECK-NEXT: frintx s16, s16
150 ; CHECK-NEXT: fcvtzs x14, s17
151 ; CHECK-NEXT: fcvtzs x15, s19
152 ; CHECK-NEXT: fcvtzs x10, s4
153 ; CHECK-NEXT: mov h4, v3.h[1]
154 ; CHECK-NEXT: fcvtzs x11, s5
155 ; CHECK-NEXT: mov h5, v1.h[3]
156 ; CHECK-NEXT: mov h3, v3.h[3]
157 ; CHECK-NEXT: fcvt s1, h1
158 ; CHECK-NEXT: fcvt s7, h7
159 ; CHECK-NEXT: fcvt s6, h6
160 ; CHECK-NEXT: fcvtzs x12, s16
161 ; CHECK-NEXT: frintx s16, s2
162 ; CHECK-NEXT: fmov d2, x8
163 ; CHECK-NEXT: fcvt s4, h4
164 ; CHECK-NEXT: fcvt s3, h3
165 ; CHECK-NEXT: fcvt s5, h5
166 ; CHECK-NEXT: frintx s1, s1
167 ; CHECK-NEXT: frintx s7, s7
168 ; CHECK-NEXT: frintx s17, s6
169 ; CHECK-NEXT: fmov d6, x9
170 ; CHECK-NEXT: mov v2.d[1], x10
171 ; CHECK-NEXT: frintx s4, s4
172 ; CHECK-NEXT: frintx s18, s3
173 ; CHECK-NEXT: frintx s5, s5
174 ; CHECK-NEXT: fcvtzs x8, s1
175 ; CHECK-NEXT: fcvtzs x9, s7
176 ; CHECK-NEXT: fmov d3, x11
177 ; CHECK-NEXT: fcvtzs x11, s0
178 ; CHECK-NEXT: fmov d7, x12
179 ; CHECK-NEXT: fcvtzs x12, s16
180 ; CHECK-NEXT: fcvtzs x16, s17
181 ; CHECK-NEXT: fcvtzs x17, s4
182 ; CHECK-NEXT: fmov d0, x13
183 ; CHECK-NEXT: fmov d1, x15
184 ; CHECK-NEXT: fcvtzs x18, s18
185 ; CHECK-NEXT: fcvtzs x0, s5
186 ; CHECK-NEXT: fmov d4, x8
187 ; CHECK-NEXT: fmov d5, x9
188 ; CHECK-NEXT: mov v0.d[1], x14
189 ; CHECK-NEXT: mov v1.d[1], x11
190 ; CHECK-NEXT: mov v3.d[1], x12
191 ; CHECK-NEXT: mov v4.d[1], x16
192 ; CHECK-NEXT: mov v6.d[1], x17
193 ; CHECK-NEXT: mov v7.d[1], x18
194 ; CHECK-NEXT: mov v5.d[1], x0
195 ; CHECK-NEXT: ret
196 %a = call <16 x i64> @llvm.lrint.v16i64.v16f16(<16 x half> %x)
197 ret <16 x i64> %a
198 }
199 declare <16 x i64> @llvm.lrint.v16i64.v16f16(<16 x half>)
201 define <32 x i64> @lrint_v32i64_v32f16(<32 x half> %x) {
202 ; CHECK-LABEL: lrint_v32i64_v32f16:
203 ; CHECK: // %bb.0:
204 ; CHECK-NEXT: ext v4.16b, v1.16b, v1.16b, #8
205 ; CHECK-NEXT: ext v5.16b, v2.16b, v2.16b, #8
206 ; CHECK-NEXT: ext v6.16b, v3.16b, v3.16b, #8
207 ; CHECK-NEXT: ext v7.16b, v0.16b, v0.16b, #8
208 ; CHECK-NEXT: mov h19, v0.h[1]
209 ; CHECK-NEXT: fcvt s21, h0
210 ; CHECK-NEXT: mov h23, v1.h[2]
211 ; CHECK-NEXT: fcvt s22, h1
212 ; CHECK-NEXT: fcvt s26, h2
213 ; CHECK-NEXT: mov h27, v2.h[1]
214 ; CHECK-NEXT: mov h28, v2.h[2]
215 ; CHECK-NEXT: mov h16, v4.h[2]
216 ; CHECK-NEXT: fcvt s17, h5
217 ; CHECK-NEXT: mov h18, v5.h[2]
218 ; CHECK-NEXT: mov h20, v6.h[2]
219 ; CHECK-NEXT: fcvt s24, h7
220 ; CHECK-NEXT: fcvt s25, h6
221 ; CHECK-NEXT: fcvt s19, h19
222 ; CHECK-NEXT: frintx s22, s22
223 ; CHECK-NEXT: fcvt s16, h16
224 ; CHECK-NEXT: frintx s17, s17
225 ; CHECK-NEXT: fcvt s18, h18
226 ; CHECK-NEXT: fcvt s20, h20
227 ; CHECK-NEXT: frintx s16, s16
228 ; CHECK-NEXT: fcvtzs x12, s17
229 ; CHECK-NEXT: frintx s17, s18
230 ; CHECK-NEXT: frintx s18, s21
231 ; CHECK-NEXT: fcvt s21, h23
232 ; CHECK-NEXT: frintx s23, s24
233 ; CHECK-NEXT: frintx s24, s25
234 ; CHECK-NEXT: frintx s25, s19
235 ; CHECK-NEXT: mov h19, v7.h[1]
236 ; CHECK-NEXT: fcvtzs x13, s16
237 ; CHECK-NEXT: frintx s16, s20
238 ; CHECK-NEXT: frintx s20, s26
239 ; CHECK-NEXT: fcvtzs x9, s23
240 ; CHECK-NEXT: mov h23, v3.h[2]
241 ; CHECK-NEXT: fcvt s26, h27
242 ; CHECK-NEXT: fcvtzs x15, s24
243 ; CHECK-NEXT: fcvtzs x10, s25
244 ; CHECK-NEXT: fcvt s24, h28
245 ; CHECK-NEXT: mov h25, v3.h[3]
246 ; CHECK-NEXT: fcvtzs x14, s17
247 ; CHECK-NEXT: frintx s21, s21
248 ; CHECK-NEXT: fmov d17, x12
249 ; CHECK-NEXT: fcvtzs x12, s16
250 ; CHECK-NEXT: fmov d16, x13
251 ; CHECK-NEXT: fcvtzs x13, s22
252 ; CHECK-NEXT: fcvt s22, h3
253 ; CHECK-NEXT: mov h3, v3.h[1]
254 ; CHECK-NEXT: mov h27, v0.h[2]
255 ; CHECK-NEXT: mov h28, v2.h[3]
256 ; CHECK-NEXT: fcvt s23, h23
257 ; CHECK-NEXT: frintx s26, s26
258 ; CHECK-NEXT: fcvtzs x16, s20
259 ; CHECK-NEXT: frintx s20, s24
260 ; CHECK-NEXT: fcvt s24, h25
261 ; CHECK-NEXT: fcvtzs x11, s18
262 ; CHECK-NEXT: fmov d18, x14
263 ; CHECK-NEXT: fcvtzs x14, s21
264 ; CHECK-NEXT: frintx s22, s22
265 ; CHECK-NEXT: fcvt s3, h3
266 ; CHECK-NEXT: fcvt s25, h27
267 ; CHECK-NEXT: fcvt s27, h28
268 ; CHECK-NEXT: frintx s23, s23
269 ; CHECK-NEXT: mov h21, v1.h[3]
270 ; CHECK-NEXT: fmov d2, x15
271 ; CHECK-NEXT: fcvtzs x15, s26
272 ; CHECK-NEXT: fmov d26, x13
273 ; CHECK-NEXT: mov h1, v1.h[1]
274 ; CHECK-NEXT: fcvtzs x13, s20
275 ; CHECK-NEXT: frintx s20, s24
276 ; CHECK-NEXT: fmov d24, x14
277 ; CHECK-NEXT: fcvtzs x14, s22
278 ; CHECK-NEXT: frintx s3, s3
279 ; CHECK-NEXT: fmov d22, x16
280 ; CHECK-NEXT: frintx s27, s27
281 ; CHECK-NEXT: fcvtzs x16, s23
282 ; CHECK-NEXT: fcvt s21, h21
283 ; CHECK-NEXT: frintx s25, s25
284 ; CHECK-NEXT: fcvt s1, h1
285 ; CHECK-NEXT: mov h0, v0.h[3]
286 ; CHECK-NEXT: mov h23, v7.h[2]
287 ; CHECK-NEXT: mov v22.d[1], x15
288 ; CHECK-NEXT: fcvtzs x15, s20
289 ; CHECK-NEXT: fmov d20, x13
290 ; CHECK-NEXT: fcvtzs x13, s3
291 ; CHECK-NEXT: fmov d3, x14
292 ; CHECK-NEXT: fcvtzs x14, s27
293 ; CHECK-NEXT: fmov d27, x16
294 ; CHECK-NEXT: frintx s21, s21
295 ; CHECK-NEXT: mov h7, v7.h[3]
296 ; CHECK-NEXT: frintx s1, s1
297 ; CHECK-NEXT: fcvt s0, h0
298 ; CHECK-NEXT: fcvt s23, h23
299 ; CHECK-NEXT: fcvt s19, h19
300 ; CHECK-NEXT: mov v27.d[1], x15
301 ; CHECK-NEXT: fcvtzs x15, s25
302 ; CHECK-NEXT: mov h25, v6.h[3]
303 ; CHECK-NEXT: mov h6, v6.h[1]
304 ; CHECK-NEXT: mov v3.d[1], x13
305 ; CHECK-NEXT: fcvtzs x13, s21
306 ; CHECK-NEXT: mov h21, v5.h[1]
307 ; CHECK-NEXT: mov h5, v5.h[3]
308 ; CHECK-NEXT: mov v20.d[1], x14
309 ; CHECK-NEXT: fcvtzs x14, s1
310 ; CHECK-NEXT: mov h1, v4.h[1]
311 ; CHECK-NEXT: frintx s0, s0
312 ; CHECK-NEXT: fcvt s25, h25
313 ; CHECK-NEXT: fcvt s7, h7
314 ; CHECK-NEXT: stp q3, q27, [x8, #192]
315 ; CHECK-NEXT: fcvt s6, h6
316 ; CHECK-NEXT: mov h3, v4.h[3]
317 ; CHECK-NEXT: stp q22, q20, [x8, #128]
318 ; CHECK-NEXT: fcvt s21, h21
319 ; CHECK-NEXT: fcvt s5, h5
320 ; CHECK-NEXT: mov v24.d[1], x13
321 ; CHECK-NEXT: mov v26.d[1], x14
322 ; CHECK-NEXT: fcvt s4, h4
323 ; CHECK-NEXT: frintx s22, s25
324 ; CHECK-NEXT: fmov d20, x12
325 ; CHECK-NEXT: fcvt s1, h1
326 ; CHECK-NEXT: frintx s6, s6
327 ; CHECK-NEXT: fcvt s3, h3
328 ; CHECK-NEXT: fcvtzs x12, s0
329 ; CHECK-NEXT: frintx s5, s5
330 ; CHECK-NEXT: frintx s21, s21
331 ; CHECK-NEXT: fmov d0, x11
332 ; CHECK-NEXT: stp q26, q24, [x8, #64]
333 ; CHECK-NEXT: fmov d24, x15
334 ; CHECK-NEXT: frintx s4, s4
335 ; CHECK-NEXT: fcvtzs x11, s22
336 ; CHECK-NEXT: frintx s22, s23
337 ; CHECK-NEXT: frintx s1, s1
338 ; CHECK-NEXT: fcvtzs x13, s6
339 ; CHECK-NEXT: frintx s3, s3
340 ; CHECK-NEXT: frintx s6, s7
341 ; CHECK-NEXT: fcvtzs x14, s5
342 ; CHECK-NEXT: mov v24.d[1], x12
343 ; CHECK-NEXT: frintx s5, s19
344 ; CHECK-NEXT: fcvtzs x12, s21
345 ; CHECK-NEXT: mov v0.d[1], x10
346 ; CHECK-NEXT: fcvtzs x10, s4
347 ; CHECK-NEXT: mov v20.d[1], x11
348 ; CHECK-NEXT: fcvtzs x11, s22
349 ; CHECK-NEXT: mov v2.d[1], x13
350 ; CHECK-NEXT: fcvtzs x15, s3
351 ; CHECK-NEXT: fcvtzs x13, s1
352 ; CHECK-NEXT: mov v18.d[1], x14
353 ; CHECK-NEXT: fcvtzs x14, s6
354 ; CHECK-NEXT: stp q0, q24, [x8]
355 ; CHECK-NEXT: mov v17.d[1], x12
356 ; CHECK-NEXT: fcvtzs x12, s5
357 ; CHECK-NEXT: fmov d0, x10
358 ; CHECK-NEXT: fmov d1, x11
359 ; CHECK-NEXT: stp q2, q20, [x8, #224]
360 ; CHECK-NEXT: fmov d2, x9
361 ; CHECK-NEXT: mov v16.d[1], x15
362 ; CHECK-NEXT: stp q17, q18, [x8, #160]
363 ; CHECK-NEXT: mov v0.d[1], x13
364 ; CHECK-NEXT: mov v1.d[1], x14
365 ; CHECK-NEXT: mov v2.d[1], x12
366 ; CHECK-NEXT: stp q0, q16, [x8, #96]
367 ; CHECK-NEXT: stp q2, q1, [x8, #32]
368 ; CHECK-NEXT: ret
369 %a = call <32 x i64> @llvm.lrint.v32i64.v32f16(<32 x half> %x)
370 ret <32 x i64> %a
371 }
372 declare <32 x i64> @llvm.lrint.v32i64.v32f16(<32 x half>)
374 define <1 x i64> @lrint_v1f32(<1 x float> %x) {
375 ; CHECK-LABEL: lrint_v1f32:
376 ; CHECK: // %bb.0:
377 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
378 ; CHECK-NEXT: frintx s0, s0
379 ; CHECK-NEXT: fcvtzs x8, s0
380 ; CHECK-NEXT: fmov d0, x8
381 ; CHECK-NEXT: ret
382 %a = call <1 x i64> @llvm.lrint.v1i64.v1f32(<1 x float> %x)
383 ret <1 x i64> %a
384 }
385 declare <1 x i64> @llvm.lrint.v1i64.v1f32(<1 x float>)
387 define <2 x i64> @lrint_v2f32(<2 x float> %x) {
388 ; CHECK-LABEL: lrint_v2f32:
389 ; CHECK: // %bb.0:
390 ; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
391 ; CHECK-NEXT: mov s1, v0.s[1]
392 ; CHECK-NEXT: frintx s0, s0
393 ; CHECK-NEXT: frintx s1, s1
394 ; CHECK-NEXT: fcvtzs x8, s0
395 ; CHECK-NEXT: fcvtzs x9, s1
396 ; CHECK-NEXT: fmov d0, x8
397 ; CHECK-NEXT: mov v0.d[1], x9
398 ; CHECK-NEXT: ret
399 %a = call <2 x i64> @llvm.lrint.v2i64.v2f32(<2 x float> %x)
400 ret <2 x i64> %a
401 }
402 declare <2 x i64> @llvm.lrint.v2i64.v2f32(<2 x float>)
404 define <4 x i64> @lrint_v4f32(<4 x float> %x) {
405 ; CHECK-LABEL: lrint_v4f32:
406 ; CHECK: // %bb.0:
407 ; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
408 ; CHECK-NEXT: mov s3, v0.s[1]
409 ; CHECK-NEXT: frintx s0, s0
410 ; CHECK-NEXT: mov s2, v1.s[1]
411 ; CHECK-NEXT: frintx s1, s1
412 ; CHECK-NEXT: frintx s3, s3
413 ; CHECK-NEXT: fcvtzs x9, s0
414 ; CHECK-NEXT: frintx s2, s2
415 ; CHECK-NEXT: fcvtzs x8, s1
416 ; CHECK-NEXT: fcvtzs x11, s3
417 ; CHECK-NEXT: fmov d0, x9
418 ; CHECK-NEXT: fcvtzs x10, s2
419 ; CHECK-NEXT: fmov d1, x8
420 ; CHECK-NEXT: mov v0.d[1], x11
421 ; CHECK-NEXT: mov v1.d[1], x10
422 ; CHECK-NEXT: ret
423 %a = call <4 x i64> @llvm.lrint.v4i64.v4f32(<4 x float> %x)
424 ret <4 x i64> %a
425 }
426 declare <4 x i64> @llvm.lrint.v4i64.v4f32(<4 x float>)
428 define <8 x i64> @lrint_v8f32(<8 x float> %x) {
429 ; CHECK-LABEL: lrint_v8f32:
430 ; CHECK: // %bb.0:
431 ; CHECK-NEXT: ext v2.16b, v0.16b, v0.16b, #8
432 ; CHECK-NEXT: ext v3.16b, v1.16b, v1.16b, #8
433 ; CHECK-NEXT: mov s4, v0.s[1]
434 ; CHECK-NEXT: mov s7, v1.s[1]
435 ; CHECK-NEXT: frintx s0, s0
436 ; CHECK-NEXT: frintx s1, s1
437 ; CHECK-NEXT: mov s5, v2.s[1]
438 ; CHECK-NEXT: mov s6, v3.s[1]
439 ; CHECK-NEXT: frintx s2, s2
440 ; CHECK-NEXT: frintx s3, s3
441 ; CHECK-NEXT: frintx s4, s4
442 ; CHECK-NEXT: frintx s7, s7
443 ; CHECK-NEXT: fcvtzs x9, s0
444 ; CHECK-NEXT: fcvtzs x12, s1
445 ; CHECK-NEXT: frintx s5, s5
446 ; CHECK-NEXT: frintx s6, s6
447 ; CHECK-NEXT: fcvtzs x8, s2
448 ; CHECK-NEXT: fcvtzs x10, s3
449 ; CHECK-NEXT: fcvtzs x11, s4
450 ; CHECK-NEXT: fcvtzs x15, s7
451 ; CHECK-NEXT: fmov d0, x9
452 ; CHECK-NEXT: fmov d2, x12
453 ; CHECK-NEXT: fcvtzs x13, s5
454 ; CHECK-NEXT: fcvtzs x14, s6
455 ; CHECK-NEXT: fmov d1, x8
456 ; CHECK-NEXT: fmov d3, x10
457 ; CHECK-NEXT: mov v0.d[1], x11
458 ; CHECK-NEXT: mov v2.d[1], x15
459 ; CHECK-NEXT: mov v1.d[1], x13
460 ; CHECK-NEXT: mov v3.d[1], x14
461 ; CHECK-NEXT: ret
462 %a = call <8 x i64> @llvm.lrint.v8i64.v8f32(<8 x float> %x)
463 ret <8 x i64> %a
464 }
465 declare <8 x i64> @llvm.lrint.v8i64.v8f32(<8 x float>)
467 define <16 x i64> @lrint_v16i64_v16f32(<16 x float> %x) {
468 ; CHECK-LABEL: lrint_v16i64_v16f32:
469 ; CHECK: // %bb.0:
470 ; CHECK-NEXT: ext v4.16b, v0.16b, v0.16b, #8
471 ; CHECK-NEXT: ext v5.16b, v1.16b, v1.16b, #8
472 ; CHECK-NEXT: ext v6.16b, v2.16b, v2.16b, #8
473 ; CHECK-NEXT: frintx s7, s0
474 ; CHECK-NEXT: ext v16.16b, v3.16b, v3.16b, #8
475 ; CHECK-NEXT: mov s0, v0.s[1]
476 ; CHECK-NEXT: frintx s17, s4
477 ; CHECK-NEXT: mov s4, v4.s[1]
478 ; CHECK-NEXT: mov s18, v5.s[1]
479 ; CHECK-NEXT: frintx s5, s5
480 ; CHECK-NEXT: frintx s19, s6
481 ; CHECK-NEXT: fcvtzs x8, s7
482 ; CHECK-NEXT: frintx s7, s16
483 ; CHECK-NEXT: mov s6, v6.s[1]
484 ; CHECK-NEXT: mov s16, v16.s[1]
485 ; CHECK-NEXT: frintx s0, s0
486 ; CHECK-NEXT: frintx s4, s4
487 ; CHECK-NEXT: fcvtzs x9, s17
488 ; CHECK-NEXT: frintx s17, s1
489 ; CHECK-NEXT: mov s1, v1.s[1]
490 ; CHECK-NEXT: frintx s18, s18
491 ; CHECK-NEXT: fcvtzs x10, s5
492 ; CHECK-NEXT: mov s5, v2.s[1]
493 ; CHECK-NEXT: fcvtzs x11, s19
494 ; CHECK-NEXT: mov s19, v3.s[1]
495 ; CHECK-NEXT: frintx s2, s2
496 ; CHECK-NEXT: fcvtzs x12, s7
497 ; CHECK-NEXT: frintx s6, s6
498 ; CHECK-NEXT: fcvtzs x13, s4
499 ; CHECK-NEXT: frintx s4, s3
500 ; CHECK-NEXT: frintx s16, s16
501 ; CHECK-NEXT: fcvtzs x14, s18
502 ; CHECK-NEXT: frintx s18, s1
503 ; CHECK-NEXT: fcvtzs x15, s17
504 ; CHECK-NEXT: frintx s20, s5
505 ; CHECK-NEXT: frintx s17, s19
506 ; CHECK-NEXT: fmov d1, x9
507 ; CHECK-NEXT: fcvtzs x9, s2
508 ; CHECK-NEXT: fmov d5, x11
509 ; CHECK-NEXT: fmov d3, x10
510 ; CHECK-NEXT: fcvtzs x11, s4
511 ; CHECK-NEXT: fcvtzs x10, s0
512 ; CHECK-NEXT: fmov d7, x12
513 ; CHECK-NEXT: fcvtzs x12, s18
514 ; CHECK-NEXT: fcvtzs x17, s6
515 ; CHECK-NEXT: fcvtzs x18, s16
516 ; CHECK-NEXT: fcvtzs x16, s20
517 ; CHECK-NEXT: fcvtzs x0, s17
518 ; CHECK-NEXT: fmov d0, x8
519 ; CHECK-NEXT: fmov d2, x15
520 ; CHECK-NEXT: fmov d4, x9
521 ; CHECK-NEXT: mov v1.d[1], x13
522 ; CHECK-NEXT: fmov d6, x11
523 ; CHECK-NEXT: mov v3.d[1], x14
524 ; CHECK-NEXT: mov v0.d[1], x10
525 ; CHECK-NEXT: mov v5.d[1], x17
526 ; CHECK-NEXT: mov v7.d[1], x18
527 ; CHECK-NEXT: mov v2.d[1], x12
528 ; CHECK-NEXT: mov v4.d[1], x16
529 ; CHECK-NEXT: mov v6.d[1], x0
530 ; CHECK-NEXT: ret
531 %a = call <16 x i64> @llvm.lrint.v16i64.v16f32(<16 x float> %x)
532 ret <16 x i64> %a
533 }
534 declare <16 x i64> @llvm.lrint.v16i64.v16f32(<16 x float>)
536 define <1 x i64> @lrint_v1f64(<1 x double> %x) {
537 ; CHECK-LABEL: lrint_v1f64:
538 ; CHECK: // %bb.0:
539 ; CHECK-NEXT: frintx d0, d0
540 ; CHECK-NEXT: fcvtzs x8, d0
541 ; CHECK-NEXT: fmov d0, x8
542 ; CHECK-NEXT: ret
543 %a = call <1 x i64> @llvm.lrint.v1i64.v1f64(<1 x double> %x)
544 ret <1 x i64> %a
545 }
546 declare <1 x i64> @llvm.lrint.v1i64.v1f64(<1 x double>)
548 define <2 x i64> @lrint_v2f64(<2 x double> %x) {
549 ; CHECK-LABEL: lrint_v2f64:
550 ; CHECK: // %bb.0:
551 ; CHECK-NEXT: mov d1, v0.d[1]
552 ; CHECK-NEXT: frintx d0, d0
553 ; CHECK-NEXT: frintx d1, d1
554 ; CHECK-NEXT: fcvtzs x8, d0
555 ; CHECK-NEXT: fcvtzs x9, d1
556 ; CHECK-NEXT: fmov d0, x8
557 ; CHECK-NEXT: mov v0.d[1], x9
558 ; CHECK-NEXT: ret
559 %a = call <2 x i64> @llvm.lrint.v2i64.v2f64(<2 x double> %x)
560 ret <2 x i64> %a
561 }
562 declare <2 x i64> @llvm.lrint.v2i64.v2f64(<2 x double>)
564 define <4 x i64> @lrint_v4f64(<4 x double> %x) {
565 ; CHECK-LABEL: lrint_v4f64:
566 ; CHECK: // %bb.0:
567 ; CHECK-NEXT: mov d2, v0.d[1]
568 ; CHECK-NEXT: mov d3, v1.d[1]
569 ; CHECK-NEXT: frintx d0, d0
570 ; CHECK-NEXT: frintx d1, d1
571 ; CHECK-NEXT: frintx d2, d2
572 ; CHECK-NEXT: frintx d3, d3
573 ; CHECK-NEXT: fcvtzs x8, d0
574 ; CHECK-NEXT: fcvtzs x9, d1
575 ; CHECK-NEXT: fcvtzs x10, d2
576 ; CHECK-NEXT: fcvtzs x11, d3
577 ; CHECK-NEXT: fmov d0, x8
578 ; CHECK-NEXT: fmov d1, x9
579 ; CHECK-NEXT: mov v0.d[1], x10
580 ; CHECK-NEXT: mov v1.d[1], x11
581 ; CHECK-NEXT: ret
582 %a = call <4 x i64> @llvm.lrint.v4i64.v4f64(<4 x double> %x)
583 ret <4 x i64> %a
584 }
585 declare <4 x i64> @llvm.lrint.v4i64.v4f64(<4 x double>)
587 define <8 x i64> @lrint_v8f64(<8 x double> %x) {
588 ; CHECK-LABEL: lrint_v8f64:
589 ; CHECK: // %bb.0:
590 ; CHECK-NEXT: mov d4, v0.d[1]
591 ; CHECK-NEXT: mov d5, v1.d[1]
592 ; CHECK-NEXT: mov d6, v2.d[1]
593 ; CHECK-NEXT: mov d7, v3.d[1]
594 ; CHECK-NEXT: frintx d0, d0
595 ; CHECK-NEXT: frintx d1, d1
596 ; CHECK-NEXT: frintx d2, d2
597 ; CHECK-NEXT: frintx d3, d3
598 ; CHECK-NEXT: frintx d4, d4
599 ; CHECK-NEXT: frintx d5, d5
600 ; CHECK-NEXT: frintx d6, d6
601 ; CHECK-NEXT: frintx d7, d7
602 ; CHECK-NEXT: fcvtzs x8, d0
603 ; CHECK-NEXT: fcvtzs x9, d1
604 ; CHECK-NEXT: fcvtzs x10, d2
605 ; CHECK-NEXT: fcvtzs x11, d3
606 ; CHECK-NEXT: fcvtzs x12, d4
607 ; CHECK-NEXT: fcvtzs x13, d5
608 ; CHECK-NEXT: fcvtzs x14, d6
609 ; CHECK-NEXT: fcvtzs x15, d7
610 ; CHECK-NEXT: fmov d0, x8
611 ; CHECK-NEXT: fmov d1, x9
612 ; CHECK-NEXT: fmov d2, x10
613 ; CHECK-NEXT: fmov d3, x11
614 ; CHECK-NEXT: mov v0.d[1], x12
615 ; CHECK-NEXT: mov v1.d[1], x13
616 ; CHECK-NEXT: mov v2.d[1], x14
617 ; CHECK-NEXT: mov v3.d[1], x15
618 ; CHECK-NEXT: ret
619 %a = call <8 x i64> @llvm.lrint.v8i64.v8f64(<8 x double> %x)
620 ret <8 x i64> %a
621 }
622 declare <8 x i64> @llvm.lrint.v8i64.v8f64(<8 x double>)