llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir

   1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
   2 # RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s  | FileCheck -check-prefix=WAVE64 %s
   3 # RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s  | FileCheck -check-prefix=WAVE64 %s
   4 # RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr="+wavefrontsize32" -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s  | FileCheck -check-prefix=WAVE32 %s
   5 # RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr="+wavefrontsize32" -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s  | FileCheck -check-prefix=WAVE32 %s
   6
   7 ---
   8
   9 name:            or_s1_vcc_vcc_vcc
  10 legalized:       true
  11 regBankSelected: true
  12 tracksRegLiveness: true
  13
  14 body: |
  15   bb.0:
  16     liveins: $vgpr0, $vgpr1
  17     ; WAVE64-LABEL: name: or_s1_vcc_vcc_vcc
  18     ; WAVE64: liveins: $vgpr0, $vgpr1
  19     ; WAVE64-NEXT: {{  $}}
  20     ; WAVE64-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  21     ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  22     ; WAVE64-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
  23     ; WAVE64-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
  24     ; WAVE64-NEXT: [[V_CMP_EQ_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec
  25     ; WAVE64-NEXT: [[S_OR_B64_:%[0-9]+]]:sreg_64_xexec = S_OR_B64 [[V_CMP_EQ_U32_e64_]], [[V_CMP_EQ_U32_e64_1]], implicit-def dead $scc
  26     ; WAVE64-NEXT: S_ENDPGM 0, implicit [[S_OR_B64_]]
  27     ;
  28     ; WAVE32-LABEL: name: or_s1_vcc_vcc_vcc
  29     ; WAVE32: liveins: $vgpr0, $vgpr1
  30     ; WAVE32-NEXT: {{  $}}
  31     ; WAVE32-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  32     ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  33     ; WAVE32-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
  34     ; WAVE32-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
  35     ; WAVE32-NEXT: [[V_CMP_EQ_U32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec
  36     ; WAVE32-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_OR_B32 [[V_CMP_EQ_U32_e64_]], [[V_CMP_EQ_U32_e64_1]], implicit-def dead $scc
  37     ; WAVE32-NEXT: S_ENDPGM 0, implicit [[S_OR_B32_]]
  38     %0:vgpr(s32) = COPY $vgpr0
  39     %1:vgpr(s32) = COPY $vgpr1
  40     %2:vgpr(s32) = G_CONSTANT i32 0
  41     %3:vcc(s1) = G_ICMP intpred(eq), %0, %2
  42     %4:vcc(s1) = G_ICMP intpred(eq), %1, %2
  43     %5:vcc(s1) = G_OR %3, %4
  44     S_ENDPGM 0, implicit %5
  45 ...
  46
  47 # Should fail to select
  48 ---
  49
  50 name:            or_s1_sgpr_sgpr_sgpr
  51 legalized:       true
  52 regBankSelected: true
  53 tracksRegLiveness: true
  54
  55 body: |
  56   bb.0:
  57     liveins: $sgpr0, $sgpr1
  58     ; WAVE64-LABEL: name: or_s1_sgpr_sgpr_sgpr
  59     ; WAVE64: liveins: $sgpr0, $sgpr1
  60     ; WAVE64-NEXT: {{  $}}
  61     ; WAVE64-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
  62     ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
  63     ; WAVE64-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[COPY1]], implicit-def dead $scc
  64     ; WAVE64-NEXT: S_ENDPGM 0, implicit [[S_OR_B32_]]
  65     ;
  66     ; WAVE32-LABEL: name: or_s1_sgpr_sgpr_sgpr
  67     ; WAVE32: liveins: $sgpr0, $sgpr1
  68     ; WAVE32-NEXT: {{  $}}
  69     ; WAVE32-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
  70     ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
  71     ; WAVE32-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[COPY1]], implicit-def dead $scc
  72     ; WAVE32-NEXT: S_ENDPGM 0, implicit [[S_OR_B32_]]
  73     %0:sgpr(s32) = COPY $sgpr0
  74     %1:sgpr(s32) = COPY $sgpr1
  75     %2:sgpr(s1) = G_TRUNC %0
  76     %3:sgpr(s1) = G_TRUNC %1
  77     %4:sgpr(s1) = G_OR %2, %3
  78     S_ENDPGM 0, implicit %4
  79 ...
  80
  81 ---
  82
  83 name:            or_s16_sgpr_sgpr_sgpr
  84 legalized:       true
  85 regBankSelected: true
  86 tracksRegLiveness: true
  87
  88 body: |
  89   bb.0:
  90     liveins: $sgpr0, $sgpr1
  91     ; WAVE64-LABEL: name: or_s16_sgpr_sgpr_sgpr
  92     ; WAVE64: liveins: $sgpr0, $sgpr1
  93     ; WAVE64-NEXT: {{  $}}
  94     ; WAVE64-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
  95     ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
  96     ; WAVE64-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[COPY1]], implicit-def dead $scc
  97     ; WAVE64-NEXT: S_ENDPGM 0, implicit [[S_OR_B32_]]
  98     ;
  99     ; WAVE32-LABEL: name: or_s16_sgpr_sgpr_sgpr
 100     ; WAVE32: liveins: $sgpr0, $sgpr1
 101     ; WAVE32-NEXT: {{  $}}
 102     ; WAVE32-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
 103     ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
 104     ; WAVE32-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[COPY1]], implicit-def dead $scc
 105     ; WAVE32-NEXT: S_ENDPGM 0, implicit [[S_OR_B32_]]
 106     %0:sgpr(s32) = COPY $sgpr0
 107     %1:sgpr(s32) = COPY $sgpr1
 108     %2:sgpr(s16) = G_TRUNC %0
 109     %3:sgpr(s16) = G_TRUNC %1
 110     %4:sgpr(s16) = G_OR %2, %3
 111     S_ENDPGM 0, implicit %4
 112 ...
 113
 114 ---
 115
 116 name:            or_s16_vgpr_vgpr_vgpr
 117 legalized:       true
 118 regBankSelected: true
 119 tracksRegLiveness: true
 120
 121 body: |
 122   bb.0:
 123     liveins: $vgpr0, $vgpr1
 124     ; WAVE64-LABEL: name: or_s16_vgpr_vgpr_vgpr
 125     ; WAVE64: liveins: $vgpr0, $vgpr1
 126     ; WAVE64-NEXT: {{  $}}
 127     ; WAVE64-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
 128     ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
 129     ; WAVE64-NEXT: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[COPY]], [[COPY1]], implicit $exec
 130     ; WAVE64-NEXT: S_ENDPGM 0, implicit [[V_OR_B32_e64_]]
 131     ;
 132     ; WAVE32-LABEL: name: or_s16_vgpr_vgpr_vgpr
 133     ; WAVE32: liveins: $vgpr0, $vgpr1
 134     ; WAVE32-NEXT: {{  $}}
 135     ; WAVE32-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
 136     ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
 137     ; WAVE32-NEXT: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[COPY]], [[COPY1]], implicit $exec
 138     ; WAVE32-NEXT: S_ENDPGM 0, implicit [[V_OR_B32_e64_]]
 139     %0:vgpr(s32) = COPY $vgpr0
 140     %1:vgpr(s32) = COPY $vgpr1
 141     %2:vgpr(s16) = G_TRUNC %0
 142     %3:vgpr(s16) = G_TRUNC %1
 143     %4:vgpr(s16) = G_OR %2, %3
 144     S_ENDPGM 0, implicit %4
 145 ...
 146
 147 ---
 148
 149 name:            or_s32_sgpr_sgpr_sgpr
 150 legalized:       true
 151 regBankSelected: true
 152 tracksRegLiveness: true
 153
 154 body: |
 155   bb.0:
 156     liveins: $sgpr0, $sgpr1
 157     ; WAVE64-LABEL: name: or_s32_sgpr_sgpr_sgpr
 158     ; WAVE64: liveins: $sgpr0, $sgpr1
 159     ; WAVE64-NEXT: {{  $}}
 160     ; WAVE64-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
 161     ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
 162     ; WAVE64-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[COPY1]], implicit-def dead $scc
 163     ; WAVE64-NEXT: S_ENDPGM 0, implicit [[S_OR_B32_]]
 164     ;
 165     ; WAVE32-LABEL: name: or_s32_sgpr_sgpr_sgpr
 166     ; WAVE32: liveins: $sgpr0, $sgpr1
 167     ; WAVE32-NEXT: {{  $}}
 168     ; WAVE32-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
 169     ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
 170     ; WAVE32-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[COPY1]], implicit-def dead $scc
 171     ; WAVE32-NEXT: S_ENDPGM 0, implicit [[S_OR_B32_]]
 172     %0:sgpr(s32) = COPY $sgpr0
 173     %1:sgpr(s32) = COPY $sgpr1
 174     %2:sgpr(s32) = G_OR %0, %1
 175     S_ENDPGM 0, implicit %2
 176 ...
 177
 178 ---
 179
 180 name:            or_s64_sgpr_sgpr_sgpr
 181 legalized:       true
 182 regBankSelected: true
 183 tracksRegLiveness: true
 184
 185 body: |
 186   bb.0:
 187     liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
 188     ; WAVE64-LABEL: name: or_s64_sgpr_sgpr_sgpr
 189     ; WAVE64: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
 190     ; WAVE64-NEXT: {{  $}}
 191     ; WAVE64-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
 192     ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
 193     ; WAVE64-NEXT: [[S_OR_B64_:%[0-9]+]]:sreg_64 = S_OR_B64 [[COPY]], [[COPY1]], implicit-def dead $scc
 194     ; WAVE64-NEXT: S_ENDPGM 0, implicit [[S_OR_B64_]]
 195     ;
 196     ; WAVE32-LABEL: name: or_s64_sgpr_sgpr_sgpr
 197     ; WAVE32: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
 198     ; WAVE32-NEXT: {{  $}}
 199     ; WAVE32-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
 200     ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
 201     ; WAVE32-NEXT: [[S_OR_B64_:%[0-9]+]]:sreg_64 = S_OR_B64 [[COPY]], [[COPY1]], implicit-def dead $scc
 202     ; WAVE32-NEXT: S_ENDPGM 0, implicit [[S_OR_B64_]]
 203     %0:sgpr(s64) = COPY $sgpr0_sgpr1
 204     %1:sgpr(s64) = COPY $sgpr2_sgpr3
 205     %2:sgpr(s64) = G_OR %0, %1
 206     S_ENDPGM 0, implicit %2
 207 ...
 208
 209 ---
 210
 211 name:            or_v2s16_sgpr_sgpr_sgpr
 212 legalized:       true
 213 regBankSelected: true
 214 tracksRegLiveness: true
 215
 216 body: |
 217   bb.0:
 218     liveins: $sgpr0, $sgpr1
 219     ; WAVE64-LABEL: name: or_v2s16_sgpr_sgpr_sgpr
 220     ; WAVE64: liveins: $sgpr0, $sgpr1
 221     ; WAVE64-NEXT: {{  $}}
 222     ; WAVE64-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
 223     ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
 224     ; WAVE64-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[COPY1]], implicit-def dead $scc
 225     ; WAVE64-NEXT: S_ENDPGM 0, implicit [[S_OR_B32_]]
 226     ;
 227     ; WAVE32-LABEL: name: or_v2s16_sgpr_sgpr_sgpr
 228     ; WAVE32: liveins: $sgpr0, $sgpr1
 229     ; WAVE32-NEXT: {{  $}}
 230     ; WAVE32-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
 231     ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
 232     ; WAVE32-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY]], [[COPY1]], implicit-def dead $scc
 233     ; WAVE32-NEXT: S_ENDPGM 0, implicit [[S_OR_B32_]]
 234     %0:sgpr(<2 x s16>) = COPY $sgpr0
 235     %1:sgpr(<2 x s16>) = COPY $sgpr1
 236     %2:sgpr(<2 x s16>) = G_OR %0, %1
 237     S_ENDPGM 0, implicit %2
 238 ...
 239
 240 ---
 241
 242 name:            or_v2s32_sgpr_sgpr_sgpr
 243 legalized:       true
 244 regBankSelected: true
 245 tracksRegLiveness: true
 246
 247 body: |
 248   bb.0:
 249     liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
 250     ; WAVE64-LABEL: name: or_v2s32_sgpr_sgpr_sgpr
 251     ; WAVE64: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
 252     ; WAVE64-NEXT: {{  $}}
 253     ; WAVE64-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
 254     ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
 255     ; WAVE64-NEXT: [[S_OR_B64_:%[0-9]+]]:sreg_64 = S_OR_B64 [[COPY]], [[COPY1]], implicit-def dead $scc
 256     ; WAVE64-NEXT: S_ENDPGM 0, implicit [[S_OR_B64_]]
 257     ;
 258     ; WAVE32-LABEL: name: or_v2s32_sgpr_sgpr_sgpr
 259     ; WAVE32: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
 260     ; WAVE32-NEXT: {{  $}}
 261     ; WAVE32-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
 262     ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
 263     ; WAVE32-NEXT: [[S_OR_B64_:%[0-9]+]]:sreg_64 = S_OR_B64 [[COPY]], [[COPY1]], implicit-def dead $scc
 264     ; WAVE32-NEXT: S_ENDPGM 0, implicit [[S_OR_B64_]]
 265     %0:sgpr(<2 x s32>) = COPY $sgpr0_sgpr1
 266     %1:sgpr(<2 x s32>) = COPY $sgpr2_sgpr3
 267     %2:sgpr(<2 x s32>) = G_OR %0, %1
 268     S_ENDPGM 0, implicit %2
 269 ...
 270
 271 ---
 272
 273 name:            or_v4s16_sgpr_sgpr_sgpr
 274 legalized:       true
 275 regBankSelected: true
 276 tracksRegLiveness: true
 277
 278 body: |
 279   bb.0:
 280     liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
 281     ; WAVE64-LABEL: name: or_v4s16_sgpr_sgpr_sgpr
 282     ; WAVE64: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
 283     ; WAVE64-NEXT: {{  $}}
 284     ; WAVE64-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
 285     ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
 286     ; WAVE64-NEXT: [[S_OR_B64_:%[0-9]+]]:sreg_64 = S_OR_B64 [[COPY]], [[COPY1]], implicit-def dead $scc
 287     ; WAVE64-NEXT: S_ENDPGM 0, implicit [[S_OR_B64_]]
 288     ;
 289     ; WAVE32-LABEL: name: or_v4s16_sgpr_sgpr_sgpr
 290     ; WAVE32: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
 291     ; WAVE32-NEXT: {{  $}}
 292     ; WAVE32-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
 293     ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
 294     ; WAVE32-NEXT: [[S_OR_B64_:%[0-9]+]]:sreg_64 = S_OR_B64 [[COPY]], [[COPY1]], implicit-def dead $scc
 295     ; WAVE32-NEXT: S_ENDPGM 0, implicit [[S_OR_B64_]]
 296     %0:sgpr(<4 x s16>) = COPY $sgpr0_sgpr1
 297     %1:sgpr(<4 x s16>) = COPY $sgpr2_sgpr3
 298     %2:sgpr(<4 x s16>) = G_OR %0, %1
 299     S_ENDPGM 0, implicit %2
 300 ...
 301
 302 ---
 303
 304 name:            or_s32_vgpr_vgpr_vgpr
 305 legalized:       true
 306 regBankSelected: true
 307 tracksRegLiveness: true
 308
 309 body: |
 310   bb.0:
 311     liveins: $vgpr0, $vgpr1
 312     ; WAVE64-LABEL: name: or_s32_vgpr_vgpr_vgpr
 313     ; WAVE64: liveins: $vgpr0, $vgpr1
 314     ; WAVE64-NEXT: {{  $}}
 315     ; WAVE64-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
 316     ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
 317     ; WAVE64-NEXT: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[COPY]], [[COPY1]], implicit $exec
 318     ; WAVE64-NEXT: S_ENDPGM 0, implicit [[V_OR_B32_e64_]]
 319     ;
 320     ; WAVE32-LABEL: name: or_s32_vgpr_vgpr_vgpr
 321     ; WAVE32: liveins: $vgpr0, $vgpr1
 322     ; WAVE32-NEXT: {{  $}}
 323     ; WAVE32-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
 324     ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
 325     ; WAVE32-NEXT: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[COPY]], [[COPY1]], implicit $exec
 326     ; WAVE32-NEXT: S_ENDPGM 0, implicit [[V_OR_B32_e64_]]
 327     %0:vgpr(s32) = COPY $vgpr0
 328     %1:vgpr(s32) = COPY $vgpr1
 329     %2:vgpr(s32) = G_OR %0, %1
 330     S_ENDPGM 0, implicit %2
 331 ...
 332
 333 ---
 334
 335 name:            or_v2s16_vgpr_vgpr_vgpr
 336 legalized:       true
 337 regBankSelected: true
 338 tracksRegLiveness: true
 339
 340 body: |
 341   bb.0:
 342     liveins: $vgpr0, $vgpr1
 343     ; WAVE64-LABEL: name: or_v2s16_vgpr_vgpr_vgpr
 344     ; WAVE64: liveins: $vgpr0, $vgpr1
 345     ; WAVE64-NEXT: {{  $}}
 346     ; WAVE64-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
 347     ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
 348     ; WAVE64-NEXT: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[COPY]], [[COPY1]], implicit $exec
 349     ; WAVE64-NEXT: S_ENDPGM 0, implicit [[V_OR_B32_e64_]]
 350     ;
 351     ; WAVE32-LABEL: name: or_v2s16_vgpr_vgpr_vgpr
 352     ; WAVE32: liveins: $vgpr0, $vgpr1
 353     ; WAVE32-NEXT: {{  $}}
 354     ; WAVE32-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
 355     ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
 356     ; WAVE32-NEXT: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[COPY]], [[COPY1]], implicit $exec
 357     ; WAVE32-NEXT: S_ENDPGM 0, implicit [[V_OR_B32_e64_]]
 358     %0:vgpr(<2 x s16>) = COPY $vgpr0
 359     %1:vgpr(<2 x s16>) = COPY $vgpr1
 360     %2:vgpr(<2 x s16>) = G_OR %0, %1
 361     S_ENDPGM 0, implicit %2
 362 ...
 363
 364
 365 # This should fail to select
 366 ---
 367
 368 name:            or_s64_vgpr_vgpr_vgpr
 369 legalized:       true
 370 regBankSelected: true
 371 tracksRegLiveness: true
 372
 373 body: |
 374   bb.0:
 375     liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
 376     ; WAVE64-LABEL: name: or_s64_vgpr_vgpr_vgpr
 377     ; WAVE64: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
 378     ; WAVE64-NEXT: {{  $}}
 379     ; WAVE64-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
 380     ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3
 381     ; WAVE64-NEXT: [[OR:%[0-9]+]]:vgpr(s64) = G_OR [[COPY]], [[COPY1]]
 382     ; WAVE64-NEXT: S_ENDPGM 0, implicit [[OR]](s64)
 383     ;
 384     ; WAVE32-LABEL: name: or_s64_vgpr_vgpr_vgpr
 385     ; WAVE32: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
 386     ; WAVE32-NEXT: {{  $}}
 387     ; WAVE32-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
 388     ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3
 389     ; WAVE32-NEXT: [[OR:%[0-9]+]]:vgpr(s64) = G_OR [[COPY]], [[COPY1]]
 390     ; WAVE32-NEXT: S_ENDPGM 0, implicit [[OR]](s64)
 391     %0:vgpr(s64) = COPY $vgpr0_vgpr1
 392     %1:vgpr(s64) = COPY $vgpr2_vgpr3
 393     %2:vgpr(s64) = G_OR %0, %1
 394     S_ENDPGM 0, implicit %2
 395 ...
 396
 397 ---
 398
 399 name:            or_s1_vcc_copy_to_vcc
 400 legalized:       true
 401 regBankSelected: true
 402 tracksRegLiveness: true
 403
 404 body: |
 405   bb.0:
 406     liveins: $vgpr0, $vgpr1
 407     ; WAVE64-LABEL: name: or_s1_vcc_copy_to_vcc
 408     ; WAVE64: liveins: $vgpr0, $vgpr1
 409     ; WAVE64-NEXT: {{  $}}
 410     ; WAVE64-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
 411     ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
 412     ; WAVE64-NEXT: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
 413     ; WAVE64-NEXT: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
 414     ; WAVE64-NEXT: [[V_AND_B32_e32_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY1]], implicit $exec
 415     ; WAVE64-NEXT: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_1]], implicit $exec
 416     ; WAVE64-NEXT: [[S_OR_B64_:%[0-9]+]]:sreg_64_xexec = S_OR_B64 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc
 417     ; WAVE64-NEXT: S_ENDPGM 0, implicit [[S_OR_B64_]]
 418     ;
 419     ; WAVE32-LABEL: name: or_s1_vcc_copy_to_vcc
 420     ; WAVE32: liveins: $vgpr0, $vgpr1
 421     ; WAVE32-NEXT: {{  $}}
 422     ; WAVE32-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
 423     ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
 424     ; WAVE32-NEXT: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
 425     ; WAVE32-NEXT: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
 426     ; WAVE32-NEXT: [[V_AND_B32_e32_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY1]], implicit $exec
 427     ; WAVE32-NEXT: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_1]], implicit $exec
 428     ; WAVE32-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_OR_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc
 429     ; WAVE32-NEXT: S_ENDPGM 0, implicit [[S_OR_B32_]]
 430     %0:vgpr(s32) = COPY $vgpr0
 431     %1:vgpr(s32) = COPY $vgpr1
 432     %2:vgpr(s1) = G_TRUNC %0
 433     %3:vgpr(s1) = G_TRUNC %1
 434     %4:vcc(s1) = COPY %2
 435     %5:vcc(s1) = COPY %3
 436     %6:vcc(s1) = G_OR %4, %5
 437     S_ENDPGM 0, implicit %6
 438 ...
 439
 440 # The selector for the copy of the or result may constrain the result
 441 # register of the or, losing that it is a VCCRegBank context.
 442
 443 # Works for wave32, should fail for wave64
 444 ---
 445 name:            copy_select_constrain_vcc_result_reg_wave32
 446 legalized:       true
 447 regBankSelected: true
 448 tracksRegLiveness: true
 449 body:             |
 450   bb.0:
 451     liveins: $vgpr0, $sgpr0
 452
 453     ; WAVE64-LABEL: name: copy_select_constrain_vcc_result_reg_wave32
 454     ; WAVE64: liveins: $vgpr0, $sgpr0
 455     ; WAVE64-NEXT: {{  $}}
 456     ; WAVE64-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
 457     ; WAVE64-NEXT: %sgpr0:sreg_32 = COPY $sgpr0
 458     ; WAVE64-NEXT: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
 459     ; WAVE64-NEXT: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
 460     ; WAVE64-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, %sgpr0, implicit-def dead $scc
 461     ; WAVE64-NEXT: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec
 462     ; WAVE64-NEXT: [[S_OR_B64_:%[0-9]+]]:sreg_64_xexec = S_OR_B64 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc
 463     ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[S_OR_B64_]]
 464     ; WAVE64-NEXT: S_ENDPGM 0, implicit [[COPY1]]
 465     ;
 466     ; WAVE32-LABEL: name: copy_select_constrain_vcc_result_reg_wave32
 467     ; WAVE32: liveins: $vgpr0, $sgpr0
 468     ; WAVE32-NEXT: {{  $}}
 469     ; WAVE32-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
 470     ; WAVE32-NEXT: %sgpr0:sreg_32 = COPY $sgpr0
 471     ; WAVE32-NEXT: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
 472     ; WAVE32-NEXT: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
 473     ; WAVE32-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, %sgpr0, implicit-def dead $scc
 474     ; WAVE32-NEXT: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec
 475     ; WAVE32-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_OR_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc
 476     ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[S_OR_B32_]]
 477     ; WAVE32-NEXT: S_ENDPGM 0, implicit [[COPY1]]
 478     %1:vgpr(s32) = COPY $vgpr0
 479     %0:vgpr(s1) = G_TRUNC %1(s32)
 480     %sgpr0:sgpr(s32) = COPY $sgpr0
 481     %2:sgpr(s1) = G_TRUNC %sgpr0
 482     %6:sgpr(s32) = G_CONSTANT i32 0
 483     %7:sgpr(p1) = G_IMPLICIT_DEF
 484     %9:vcc(s1) = COPY %0(s1)
 485     %10:vcc(s1) = COPY %2(s1)
 486     %8:vcc(s1) = G_OR %9, %10
 487     %3:sreg_32_xm0(s1) = COPY %8(s1)
 488     S_ENDPGM 0, implicit %3
 489
 490 ...
 491
 492 # Works for wave64, should fail for wave32
 493 ---
 494 name:            copy_select_constrain_vcc_result_reg_wave64
 495 legalized:       true
 496 regBankSelected: true
 497 tracksRegLiveness: true
 498 body:             |
 499   bb.0:
 500     liveins: $vgpr0, $sgpr0
 501
 502     ; WAVE64-LABEL: name: copy_select_constrain_vcc_result_reg_wave64
 503     ; WAVE64: liveins: $vgpr0, $sgpr0
 504     ; WAVE64-NEXT: {{  $}}
 505     ; WAVE64-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
 506     ; WAVE64-NEXT: %sgpr0:sreg_32 = COPY $sgpr0
 507     ; WAVE64-NEXT: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
 508     ; WAVE64-NEXT: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
 509     ; WAVE64-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, %sgpr0, implicit-def dead $scc
 510     ; WAVE64-NEXT: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec
 511     ; WAVE64-NEXT: [[S_OR_B64_:%[0-9]+]]:sreg_64_xexec = S_OR_B64 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc
 512     ; WAVE64-NEXT: S_ENDPGM 0, implicit [[S_OR_B64_]]
 513     ;
 514     ; WAVE32-LABEL: name: copy_select_constrain_vcc_result_reg_wave64
 515     ; WAVE32: liveins: $vgpr0, $sgpr0
 516     ; WAVE32-NEXT: {{  $}}
 517     ; WAVE32-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
 518     ; WAVE32-NEXT: %sgpr0:sreg_32 = COPY $sgpr0
 519     ; WAVE32-NEXT: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
 520     ; WAVE32-NEXT: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
 521     ; WAVE32-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, %sgpr0, implicit-def dead $scc
 522     ; WAVE32-NEXT: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec
 523     ; WAVE32-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_OR_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc
 524     ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY [[S_OR_B32_]]
 525     ; WAVE32-NEXT: S_ENDPGM 0, implicit [[COPY1]]
 526     %1:vgpr(s32) = COPY $vgpr0
 527     %0:vgpr(s1) = G_TRUNC %1(s32)
 528     %sgpr0:sgpr(s32) = COPY $sgpr0
 529     %2:sgpr(s1) = G_TRUNC %sgpr0
 530     %6:sgpr(s32) = G_CONSTANT i32 0
 531     %7:sgpr(p1) = G_IMPLICIT_DEF
 532     %9:vcc(s1) = COPY %0(s1)
 533     %10:vcc(s1) = COPY %2(s1)
 534     %8:vcc(s1) = G_OR %9, %10
 535     %3:sreg_64_xexec(s1) = COPY %8(s1)
 536     S_ENDPGM 0, implicit %3
 537
 538 ...