llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-trunc.v2s16.mir

   1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
   2 # RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs  %s -o - | FileCheck -check-prefix=GFX6 %s
   3 # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs  %s -o - | FileCheck -check-prefix=GFX8 %s
   4 # RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs  %s -o - | FileCheck -check-prefix=GFX8 %s
   5 # RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs  %s -o - | FileCheck -check-prefix=GFX8 %s
   6 # RUN: llc -march=amdgcn -mcpu=gfx1100 -run-pass=instruction-select -verify-machineinstrs  %s -o - | FileCheck -check-prefix=GFX11 %s
   7
   8 ---
   9
  10 name: trunc_sgpr_v2s32_to_v2s16
  11 legalized:       true
  12 regBankSelected: true
  13
  14 body: |
  15   bb.0:
  16     liveins: $sgpr0_sgpr1
  17     ; GFX6-LABEL: name: trunc_sgpr_v2s32_to_v2s16
  18     ; GFX6: liveins: $sgpr0_sgpr1
  19     ; GFX6-NEXT: {{  $}}
  20     ; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
  21     ; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
  22     ; GFX6-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
  23     ; GFX6-NEXT: [[S_LSHL_B32_:%[0-9]+]]:sreg_32 = S_LSHL_B32 [[COPY2]], 16, implicit-def dead $scc
  24     ; GFX6-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 65535
  25     ; GFX6-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def dead $scc
  26     ; GFX6-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[S_LSHL_B32_]], [[S_AND_B32_]], implicit-def dead $scc
  27     ; GFX6-NEXT: S_ENDPGM 0, implicit [[S_OR_B32_]]
  28     ;
  29     ; GFX8-LABEL: name: trunc_sgpr_v2s32_to_v2s16
  30     ; GFX8: liveins: $sgpr0_sgpr1
  31     ; GFX8-NEXT: {{  $}}
  32     ; GFX8-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
  33     ; GFX8-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
  34     ; GFX8-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
  35     ; GFX8-NEXT: [[S_LSHL_B32_:%[0-9]+]]:sreg_32 = S_LSHL_B32 [[COPY2]], 16, implicit-def dead $scc
  36     ; GFX8-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 65535
  37     ; GFX8-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def dead $scc
  38     ; GFX8-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[S_LSHL_B32_]], [[S_AND_B32_]], implicit-def dead $scc
  39     ; GFX8-NEXT: S_ENDPGM 0, implicit [[S_OR_B32_]]
  40     ;
  41     ; GFX11-LABEL: name: trunc_sgpr_v2s32_to_v2s16
  42     ; GFX11: liveins: $sgpr0_sgpr1
  43     ; GFX11-NEXT: {{  $}}
  44     ; GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
  45     ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub0
  46     ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY]].sub1
  47     ; GFX11-NEXT: [[S_LSHL_B32_:%[0-9]+]]:sreg_32 = S_LSHL_B32 [[COPY2]], 16, implicit-def dead $scc
  48     ; GFX11-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 65535
  49     ; GFX11-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def dead $scc
  50     ; GFX11-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[S_LSHL_B32_]], [[S_AND_B32_]], implicit-def dead $scc
  51     ; GFX11-NEXT: S_ENDPGM 0, implicit [[S_OR_B32_]]
  52     %0:sgpr(<2 x s32>) = COPY $sgpr0_sgpr1
  53     %1:sgpr(<2 x s16>) = G_TRUNC %0
  54     S_ENDPGM 0, implicit %1
  55 ...
  56
  57 ---
  58
  59 name: trunc_vgpr_v2s32_to_v2s16
  60 legalized:       true
  61 regBankSelected: true
  62
  63 body: |
  64   bb.0:
  65     liveins: $vgpr0_vgpr1
  66     ; GFX6-LABEL: name: trunc_vgpr_v2s32_to_v2s16
  67     ; GFX6: liveins: $vgpr0_vgpr1
  68     ; GFX6-NEXT: {{  $}}
  69     ; GFX6-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
  70     ; GFX6-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
  71     ; GFX6-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
  72     ; GFX6-NEXT: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 16, [[COPY2]], implicit $exec
  73     ; GFX6-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 65535, implicit $exec
  74     ; GFX6-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec
  75     ; GFX6-NEXT: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_LSHLREV_B32_e64_]], [[V_AND_B32_e64_]], implicit $exec
  76     ; GFX6-NEXT: S_ENDPGM 0, implicit [[V_OR_B32_e64_]]
  77     ;
  78     ; GFX8-LABEL: name: trunc_vgpr_v2s32_to_v2s16
  79     ; GFX8: liveins: $vgpr0_vgpr1
  80     ; GFX8-NEXT: {{  $}}
  81     ; GFX8-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
  82     ; GFX8-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
  83     ; GFX8-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
  84     ; GFX8-NEXT: [[V_MOV_B32_sdwa:%[0-9]+]]:vgpr_32 = V_MOV_B32_sdwa 0, [[COPY2]], 0, 5, 2, 4, implicit $exec, implicit [[COPY1]](tied-def 0)
  85     ; GFX8-NEXT: S_ENDPGM 0, implicit [[V_MOV_B32_sdwa]]
  86     ;
  87     ; GFX11-LABEL: name: trunc_vgpr_v2s32_to_v2s16
  88     ; GFX11: liveins: $vgpr0_vgpr1
  89     ; GFX11-NEXT: {{  $}}
  90     ; GFX11-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
  91     ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
  92     ; GFX11-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1
  93     ; GFX11-NEXT: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 16, [[COPY2]], implicit $exec
  94     ; GFX11-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 65535, implicit $exec
  95     ; GFX11-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec
  96     ; GFX11-NEXT: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_LSHLREV_B32_e64_]], [[V_AND_B32_e64_]], implicit $exec
  97     ; GFX11-NEXT: S_ENDPGM 0, implicit [[V_OR_B32_e64_]]
  98     %0:vgpr(<2 x s32>) = COPY $vgpr0_vgpr1
  99     %1:vgpr(<2 x s16>) = G_TRUNC %0
 100     S_ENDPGM 0, implicit %1
 101 ...