1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2 # RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=WAVE64 %s
3 # RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=WAVE64 %s
4 # RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr="+wavefrontsize32" -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck -check-prefix=WAVE32 %s
5 # RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr="+wavefrontsize32" -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck -check-prefix=WAVE32 %s
9 name: xor_s1_vcc_vcc_vcc
12 tracksRegLiveness: true
16 liveins: $vgpr0, $vgpr1
17 ; WAVE64-LABEL: name: xor_s1_vcc_vcc_vcc
18 ; WAVE64: liveins: $vgpr0, $vgpr1
20 ; WAVE64-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
21 ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
22 ; WAVE64-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
23 ; WAVE64-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
24 ; WAVE64-NEXT: [[V_CMP_EQ_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec
25 ; WAVE64-NEXT: [[S_XOR_B64_:%[0-9]+]]:sreg_64_xexec = S_XOR_B64 [[V_CMP_EQ_U32_e64_]], [[V_CMP_EQ_U32_e64_1]], implicit-def dead $scc
26 ; WAVE64-NEXT: S_ENDPGM 0, implicit [[S_XOR_B64_]]
28 ; WAVE32-LABEL: name: xor_s1_vcc_vcc_vcc
29 ; WAVE32: liveins: $vgpr0, $vgpr1
31 ; WAVE32-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
32 ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
33 ; WAVE32-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
34 ; WAVE32-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], implicit $exec
35 ; WAVE32-NEXT: [[V_CMP_EQ_U32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U32_e64 [[COPY1]], [[V_MOV_B32_e32_]], implicit $exec
36 ; WAVE32-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_XOR_B32 [[V_CMP_EQ_U32_e64_]], [[V_CMP_EQ_U32_e64_1]], implicit-def dead $scc
37 ; WAVE32-NEXT: S_ENDPGM 0, implicit [[S_XOR_B32_]]
38 %0:vgpr(s32) = COPY $vgpr0
39 %1:vgpr(s32) = COPY $vgpr1
40 %2:vgpr(s32) = G_CONSTANT i32 0
41 %3:vcc(s1) = G_ICMP intpred(eq), %0, %2
42 %4:vcc(s1) = G_ICMP intpred(eq), %1, %2
43 %5:vcc(s1) = G_XOR %3, %4
44 S_ENDPGM 0, implicit %5
47 # Should fail to select
51 name: xor_s1_sgpr_sgpr_sgpr
54 tracksRegLiveness: true
58 liveins: $sgpr0, $sgpr1
59 ; WAVE64-LABEL: name: xor_s1_sgpr_sgpr_sgpr
60 ; WAVE64: liveins: $sgpr0, $sgpr1
62 ; WAVE64-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
63 ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
64 ; WAVE64-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[COPY1]], implicit-def dead $scc
65 ; WAVE64-NEXT: S_ENDPGM 0, implicit [[S_XOR_B32_]]
67 ; WAVE32-LABEL: name: xor_s1_sgpr_sgpr_sgpr
68 ; WAVE32: liveins: $sgpr0, $sgpr1
70 ; WAVE32-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
71 ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
72 ; WAVE32-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[COPY1]], implicit-def dead $scc
73 ; WAVE32-NEXT: S_ENDPGM 0, implicit [[S_XOR_B32_]]
74 %0:sgpr(s32) = COPY $sgpr0
75 %1:sgpr(s32) = COPY $sgpr1
76 %2:sgpr(s1) = G_TRUNC %0
77 %3:sgpr(s1) = G_TRUNC %1
78 %4:sgpr(s1) = G_XOR %2, %3
79 S_ENDPGM 0, implicit %4
84 name: xor_s16_sgpr_sgpr_sgpr
87 tracksRegLiveness: true
91 liveins: $sgpr0, $sgpr1
92 ; WAVE64-LABEL: name: xor_s16_sgpr_sgpr_sgpr
93 ; WAVE64: liveins: $sgpr0, $sgpr1
95 ; WAVE64-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
96 ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
97 ; WAVE64-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[COPY1]], implicit-def dead $scc
98 ; WAVE64-NEXT: S_ENDPGM 0, implicit [[S_XOR_B32_]]
100 ; WAVE32-LABEL: name: xor_s16_sgpr_sgpr_sgpr
101 ; WAVE32: liveins: $sgpr0, $sgpr1
102 ; WAVE32-NEXT: {{ $}}
103 ; WAVE32-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
104 ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
105 ; WAVE32-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[COPY1]], implicit-def dead $scc
106 ; WAVE32-NEXT: S_ENDPGM 0, implicit [[S_XOR_B32_]]
107 %0:sgpr(s32) = COPY $sgpr0
108 %1:sgpr(s32) = COPY $sgpr1
109 %2:sgpr(s16) = G_TRUNC %0
110 %3:sgpr(s16) = G_TRUNC %1
111 %4:sgpr(s16) = G_XOR %2, %3
112 S_ENDPGM 0, implicit %4
117 name: xor_s16_vgpr_vgpr_vgpr
119 regBankSelected: true
120 tracksRegLiveness: true
124 liveins: $vgpr0, $vgpr1
125 ; WAVE64-LABEL: name: xor_s16_vgpr_vgpr_vgpr
126 ; WAVE64: liveins: $vgpr0, $vgpr1
127 ; WAVE64-NEXT: {{ $}}
128 ; WAVE64-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
129 ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
130 ; WAVE64-NEXT: [[V_XOR_B32_e64_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e64 [[COPY]], [[COPY1]], implicit $exec
131 ; WAVE64-NEXT: S_ENDPGM 0, implicit [[V_XOR_B32_e64_]]
133 ; WAVE32-LABEL: name: xor_s16_vgpr_vgpr_vgpr
134 ; WAVE32: liveins: $vgpr0, $vgpr1
135 ; WAVE32-NEXT: {{ $}}
136 ; WAVE32-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
137 ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
138 ; WAVE32-NEXT: [[V_XOR_B32_e64_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e64 [[COPY]], [[COPY1]], implicit $exec
139 ; WAVE32-NEXT: S_ENDPGM 0, implicit [[V_XOR_B32_e64_]]
140 %0:vgpr(s32) = COPY $vgpr0
141 %1:vgpr(s32) = COPY $vgpr1
142 %2:vgpr(s16) = G_TRUNC %0
143 %3:vgpr(s16) = G_TRUNC %1
144 %4:vgpr(s16) = G_XOR %2, %3
145 S_ENDPGM 0, implicit %4
150 name: xor_s32_sgpr_sgpr_sgpr
152 regBankSelected: true
153 tracksRegLiveness: true
157 liveins: $sgpr0, $sgpr1
158 ; WAVE64-LABEL: name: xor_s32_sgpr_sgpr_sgpr
159 ; WAVE64: liveins: $sgpr0, $sgpr1
160 ; WAVE64-NEXT: {{ $}}
161 ; WAVE64-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
162 ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
163 ; WAVE64-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[COPY1]], implicit-def dead $scc
164 ; WAVE64-NEXT: S_ENDPGM 0, implicit [[S_XOR_B32_]]
166 ; WAVE32-LABEL: name: xor_s32_sgpr_sgpr_sgpr
167 ; WAVE32: liveins: $sgpr0, $sgpr1
168 ; WAVE32-NEXT: {{ $}}
169 ; WAVE32-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
170 ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
171 ; WAVE32-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[COPY1]], implicit-def dead $scc
172 ; WAVE32-NEXT: S_ENDPGM 0, implicit [[S_XOR_B32_]]
173 %0:sgpr(s32) = COPY $sgpr0
174 %1:sgpr(s32) = COPY $sgpr1
175 %2:sgpr(s32) = G_XOR %0, %1
176 S_ENDPGM 0, implicit %2
181 name: xor_s64_sgpr_sgpr_sgpr
183 regBankSelected: true
184 tracksRegLiveness: true
188 liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
189 ; WAVE64-LABEL: name: xor_s64_sgpr_sgpr_sgpr
190 ; WAVE64: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
191 ; WAVE64-NEXT: {{ $}}
192 ; WAVE64-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
193 ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
194 ; WAVE64-NEXT: [[S_XOR_B64_:%[0-9]+]]:sreg_64 = S_XOR_B64 [[COPY]], [[COPY1]], implicit-def dead $scc
195 ; WAVE64-NEXT: S_ENDPGM 0, implicit [[S_XOR_B64_]]
197 ; WAVE32-LABEL: name: xor_s64_sgpr_sgpr_sgpr
198 ; WAVE32: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
199 ; WAVE32-NEXT: {{ $}}
200 ; WAVE32-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
201 ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
202 ; WAVE32-NEXT: [[S_XOR_B64_:%[0-9]+]]:sreg_64 = S_XOR_B64 [[COPY]], [[COPY1]], implicit-def dead $scc
203 ; WAVE32-NEXT: S_ENDPGM 0, implicit [[S_XOR_B64_]]
204 %0:sgpr(s64) = COPY $sgpr0_sgpr1
205 %1:sgpr(s64) = COPY $sgpr2_sgpr3
206 %2:sgpr(s64) = G_XOR %0, %1
207 S_ENDPGM 0, implicit %2
212 name: xor_v2s16_sgpr_sgpr_sgpr
214 regBankSelected: true
215 tracksRegLiveness: true
219 liveins: $sgpr0, $sgpr1
220 ; WAVE64-LABEL: name: xor_v2s16_sgpr_sgpr_sgpr
221 ; WAVE64: liveins: $sgpr0, $sgpr1
222 ; WAVE64-NEXT: {{ $}}
223 ; WAVE64-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
224 ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
225 ; WAVE64-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[COPY1]], implicit-def dead $scc
226 ; WAVE64-NEXT: S_ENDPGM 0, implicit [[S_XOR_B32_]]
228 ; WAVE32-LABEL: name: xor_v2s16_sgpr_sgpr_sgpr
229 ; WAVE32: liveins: $sgpr0, $sgpr1
230 ; WAVE32-NEXT: {{ $}}
231 ; WAVE32-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
232 ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
233 ; WAVE32-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY]], [[COPY1]], implicit-def dead $scc
234 ; WAVE32-NEXT: S_ENDPGM 0, implicit [[S_XOR_B32_]]
235 %0:sgpr(<2 x s16>) = COPY $sgpr0
236 %1:sgpr(<2 x s16>) = COPY $sgpr1
237 %2:sgpr(<2 x s16>) = G_XOR %0, %1
238 S_ENDPGM 0, implicit %2
243 name: xor_v2s32_sgpr_sgpr_sgpr
245 regBankSelected: true
246 tracksRegLiveness: true
250 liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
251 ; WAVE64-LABEL: name: xor_v2s32_sgpr_sgpr_sgpr
252 ; WAVE64: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
253 ; WAVE64-NEXT: {{ $}}
254 ; WAVE64-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
255 ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
256 ; WAVE64-NEXT: [[S_XOR_B64_:%[0-9]+]]:sreg_64 = S_XOR_B64 [[COPY]], [[COPY1]], implicit-def dead $scc
257 ; WAVE64-NEXT: S_ENDPGM 0, implicit [[S_XOR_B64_]]
259 ; WAVE32-LABEL: name: xor_v2s32_sgpr_sgpr_sgpr
260 ; WAVE32: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
261 ; WAVE32-NEXT: {{ $}}
262 ; WAVE32-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
263 ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
264 ; WAVE32-NEXT: [[S_XOR_B64_:%[0-9]+]]:sreg_64 = S_XOR_B64 [[COPY]], [[COPY1]], implicit-def dead $scc
265 ; WAVE32-NEXT: S_ENDPGM 0, implicit [[S_XOR_B64_]]
266 %0:sgpr(<2 x s32>) = COPY $sgpr0_sgpr1
267 %1:sgpr(<2 x s32>) = COPY $sgpr2_sgpr3
268 %2:sgpr(<2 x s32>) = G_XOR %0, %1
269 S_ENDPGM 0, implicit %2
274 name: xor_v4s16_sgpr_sgpr_sgpr
276 regBankSelected: true
277 tracksRegLiveness: true
281 liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
282 ; WAVE64-LABEL: name: xor_v4s16_sgpr_sgpr_sgpr
283 ; WAVE64: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
284 ; WAVE64-NEXT: {{ $}}
285 ; WAVE64-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
286 ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
287 ; WAVE64-NEXT: [[S_XOR_B64_:%[0-9]+]]:sreg_64 = S_XOR_B64 [[COPY]], [[COPY1]], implicit-def dead $scc
288 ; WAVE64-NEXT: S_ENDPGM 0, implicit [[S_XOR_B64_]]
290 ; WAVE32-LABEL: name: xor_v4s16_sgpr_sgpr_sgpr
291 ; WAVE32: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
292 ; WAVE32-NEXT: {{ $}}
293 ; WAVE32-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
294 ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
295 ; WAVE32-NEXT: [[S_XOR_B64_:%[0-9]+]]:sreg_64 = S_XOR_B64 [[COPY]], [[COPY1]], implicit-def dead $scc
296 ; WAVE32-NEXT: S_ENDPGM 0, implicit [[S_XOR_B64_]]
297 %0:sgpr(<4 x s16>) = COPY $sgpr0_sgpr1
298 %1:sgpr(<4 x s16>) = COPY $sgpr2_sgpr3
299 %2:sgpr(<4 x s16>) = G_XOR %0, %1
300 S_ENDPGM 0, implicit %2
305 name: xor_s32_vgpr_vgpr_vgpr
307 regBankSelected: true
308 tracksRegLiveness: true
312 liveins: $vgpr0, $vgpr1
313 ; WAVE64-LABEL: name: xor_s32_vgpr_vgpr_vgpr
314 ; WAVE64: liveins: $vgpr0, $vgpr1
315 ; WAVE64-NEXT: {{ $}}
316 ; WAVE64-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
317 ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
318 ; WAVE64-NEXT: [[V_XOR_B32_e64_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e64 [[COPY]], [[COPY1]], implicit $exec
319 ; WAVE64-NEXT: S_ENDPGM 0, implicit [[V_XOR_B32_e64_]]
321 ; WAVE32-LABEL: name: xor_s32_vgpr_vgpr_vgpr
322 ; WAVE32: liveins: $vgpr0, $vgpr1
323 ; WAVE32-NEXT: {{ $}}
324 ; WAVE32-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
325 ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
326 ; WAVE32-NEXT: [[V_XOR_B32_e64_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e64 [[COPY]], [[COPY1]], implicit $exec
327 ; WAVE32-NEXT: S_ENDPGM 0, implicit [[V_XOR_B32_e64_]]
328 %0:vgpr(s32) = COPY $vgpr0
329 %1:vgpr(s32) = COPY $vgpr1
330 %2:vgpr(s32) = G_XOR %0, %1
331 S_ENDPGM 0, implicit %2
336 name: xor_v2s16_vgpr_vgpr_vgpr
338 regBankSelected: true
339 tracksRegLiveness: true
343 liveins: $vgpr0, $vgpr1
344 ; WAVE64-LABEL: name: xor_v2s16_vgpr_vgpr_vgpr
345 ; WAVE64: liveins: $vgpr0, $vgpr1
346 ; WAVE64-NEXT: {{ $}}
347 ; WAVE64-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
348 ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
349 ; WAVE64-NEXT: [[V_XOR_B32_e64_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e64 [[COPY]], [[COPY1]], implicit $exec
350 ; WAVE64-NEXT: S_ENDPGM 0, implicit [[V_XOR_B32_e64_]]
352 ; WAVE32-LABEL: name: xor_v2s16_vgpr_vgpr_vgpr
353 ; WAVE32: liveins: $vgpr0, $vgpr1
354 ; WAVE32-NEXT: {{ $}}
355 ; WAVE32-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
356 ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
357 ; WAVE32-NEXT: [[V_XOR_B32_e64_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e64 [[COPY]], [[COPY1]], implicit $exec
358 ; WAVE32-NEXT: S_ENDPGM 0, implicit [[V_XOR_B32_e64_]]
359 %0:vgpr(<2 x s16>) = COPY $vgpr0
360 %1:vgpr(<2 x s16>) = COPY $vgpr1
361 %2:vgpr(<2 x s16>) = G_XOR %0, %1
362 S_ENDPGM 0, implicit %2
366 # This should fail to select
369 name: xor_s64_vgpr_vgpr_vgpr
371 regBankSelected: true
372 tracksRegLiveness: true
376 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
377 ; WAVE64-LABEL: name: xor_s64_vgpr_vgpr_vgpr
378 ; WAVE64: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
379 ; WAVE64-NEXT: {{ $}}
380 ; WAVE64-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
381 ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3
382 ; WAVE64-NEXT: [[XOR:%[0-9]+]]:vgpr(s64) = G_XOR [[COPY]], [[COPY1]]
383 ; WAVE64-NEXT: S_ENDPGM 0, implicit [[XOR]](s64)
385 ; WAVE32-LABEL: name: xor_s64_vgpr_vgpr_vgpr
386 ; WAVE32: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
387 ; WAVE32-NEXT: {{ $}}
388 ; WAVE32-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
389 ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3
390 ; WAVE32-NEXT: [[XOR:%[0-9]+]]:vgpr(s64) = G_XOR [[COPY]], [[COPY1]]
391 ; WAVE32-NEXT: S_ENDPGM 0, implicit [[XOR]](s64)
392 %0:vgpr(s64) = COPY $vgpr0_vgpr1
393 %1:vgpr(s64) = COPY $vgpr2_vgpr3
394 %2:vgpr(s64) = G_XOR %0, %1
395 S_ENDPGM 0, implicit %2
400 name: xor_s1_vcc_copy_to_vcc
402 regBankSelected: true
403 tracksRegLiveness: true
407 liveins: $vgpr0, $vgpr1
408 ; WAVE64-LABEL: name: xor_s1_vcc_copy_to_vcc
409 ; WAVE64: liveins: $vgpr0, $vgpr1
410 ; WAVE64-NEXT: {{ $}}
411 ; WAVE64-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
412 ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
413 ; WAVE64-NEXT: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
414 ; WAVE64-NEXT: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
415 ; WAVE64-NEXT: [[V_AND_B32_e32_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY1]], implicit $exec
416 ; WAVE64-NEXT: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_1]], implicit $exec
417 ; WAVE64-NEXT: [[S_XOR_B64_:%[0-9]+]]:sreg_64_xexec = S_XOR_B64 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc
418 ; WAVE64-NEXT: S_ENDPGM 0, implicit [[S_XOR_B64_]]
420 ; WAVE32-LABEL: name: xor_s1_vcc_copy_to_vcc
421 ; WAVE32: liveins: $vgpr0, $vgpr1
422 ; WAVE32-NEXT: {{ $}}
423 ; WAVE32-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
424 ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
425 ; WAVE32-NEXT: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
426 ; WAVE32-NEXT: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
427 ; WAVE32-NEXT: [[V_AND_B32_e32_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY1]], implicit $exec
428 ; WAVE32-NEXT: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_1]], implicit $exec
429 ; WAVE32-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_XOR_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc
430 ; WAVE32-NEXT: S_ENDPGM 0, implicit [[S_XOR_B32_]]
431 %0:vgpr(s32) = COPY $vgpr0
432 %1:vgpr(s32) = COPY $vgpr1
433 %2:vgpr(s1) = G_TRUNC %0
434 %3:vgpr(s1) = G_TRUNC %1
437 %6:vcc(s1) = G_XOR %4, %5
438 S_ENDPGM 0, implicit %6
441 # The selector for the copy of the xor result may constrain the result
442 # register of the xor, losing that it is a VCCRegBank context.
444 # Works for wave32, should fail for wave64
446 name: copy_select_constrain_vcc_result_reg_wave32
448 regBankSelected: true
449 tracksRegLiveness: true
452 liveins: $vgpr0, $sgpr0
454 ; WAVE64-LABEL: name: copy_select_constrain_vcc_result_reg_wave32
455 ; WAVE64: liveins: $vgpr0, $sgpr0
456 ; WAVE64-NEXT: {{ $}}
457 ; WAVE64-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
458 ; WAVE64-NEXT: %sgpr0:sreg_32 = COPY $sgpr0
459 ; WAVE64-NEXT: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
460 ; WAVE64-NEXT: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
461 ; WAVE64-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, %sgpr0, implicit-def dead $scc
462 ; WAVE64-NEXT: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec
463 ; WAVE64-NEXT: [[S_XOR_B64_:%[0-9]+]]:sreg_64_xexec = S_XOR_B64 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc
464 ; WAVE64-NEXT: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[S_XOR_B64_]]
465 ; WAVE64-NEXT: S_ENDPGM 0, implicit [[COPY1]]
467 ; WAVE32-LABEL: name: copy_select_constrain_vcc_result_reg_wave32
468 ; WAVE32: liveins: $vgpr0, $sgpr0
469 ; WAVE32-NEXT: {{ $}}
470 ; WAVE32-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
471 ; WAVE32-NEXT: %sgpr0:sreg_32 = COPY $sgpr0
472 ; WAVE32-NEXT: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
473 ; WAVE32-NEXT: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
474 ; WAVE32-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, %sgpr0, implicit-def dead $scc
475 ; WAVE32-NEXT: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec
476 ; WAVE32-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_XOR_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc
477 ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY [[S_XOR_B32_]]
478 ; WAVE32-NEXT: S_ENDPGM 0, implicit [[COPY1]]
479 %1:vgpr(s32) = COPY $vgpr0
480 %0:vgpr(s1) = G_TRUNC %1(s32)
481 %sgpr0:sgpr(s32) = COPY $sgpr0
482 %2:sgpr(s1) = G_TRUNC %sgpr0
483 %6:sgpr(s32) = G_CONSTANT i32 0
484 %7:sgpr(p1) = G_IMPLICIT_DEF
485 %9:vcc(s1) = COPY %0(s1)
486 %10:vcc(s1) = COPY %2(s1)
487 %8:vcc(s1) = G_XOR %9, %10
488 %3:sreg_32_xm0(s1) = COPY %8(s1)
489 S_ENDPGM 0, implicit %3
493 # Works for wave64, should fail for wave32
495 name: copy_select_constrain_vcc_result_reg_wave64
497 regBankSelected: true
498 tracksRegLiveness: true
501 liveins: $vgpr0, $sgpr0
503 ; WAVE64-LABEL: name: copy_select_constrain_vcc_result_reg_wave64
504 ; WAVE64: liveins: $vgpr0, $sgpr0
505 ; WAVE64-NEXT: {{ $}}
506 ; WAVE64-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
507 ; WAVE64-NEXT: %sgpr0:sreg_32 = COPY $sgpr0
508 ; WAVE64-NEXT: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
509 ; WAVE64-NEXT: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
510 ; WAVE64-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, %sgpr0, implicit-def dead $scc
511 ; WAVE64-NEXT: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec
512 ; WAVE64-NEXT: [[S_XOR_B64_:%[0-9]+]]:sreg_64_xexec = S_XOR_B64 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc
513 ; WAVE64-NEXT: S_ENDPGM 0, implicit [[S_XOR_B64_]]
515 ; WAVE32-LABEL: name: copy_select_constrain_vcc_result_reg_wave64
516 ; WAVE32: liveins: $vgpr0, $sgpr0
517 ; WAVE32-NEXT: {{ $}}
518 ; WAVE32-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
519 ; WAVE32-NEXT: %sgpr0:sreg_32 = COPY $sgpr0
520 ; WAVE32-NEXT: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 1, [[COPY]], implicit $exec
521 ; WAVE32-NEXT: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 0, [[V_AND_B32_e32_]], implicit $exec
522 ; WAVE32-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, %sgpr0, implicit-def dead $scc
523 ; WAVE32-NEXT: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec
524 ; WAVE32-NEXT: [[S_XOR_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_XOR_B32 [[V_CMP_NE_U32_e64_]], [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc
525 ; WAVE32-NEXT: [[COPY1:%[0-9]+]]:sreg_64_xexec = COPY [[S_XOR_B32_]]
526 ; WAVE32-NEXT: S_ENDPGM 0, implicit [[COPY1]]
527 %1:vgpr(s32) = COPY $vgpr0
528 %0:vgpr(s1) = G_TRUNC %1(s32)
529 %sgpr0:sgpr(s32) = COPY $sgpr0
530 %2:sgpr(s1) = G_TRUNC %sgpr0
531 %6:sgpr(s32) = G_CONSTANT i32 0
532 %7:sgpr(p1) = G_IMPLICIT_DEF
533 %9:vcc(s1) = COPY %0(s1)
534 %10:vcc(s1) = COPY %2(s1)
535 %8:vcc(s1) = G_XOR %9, %10
536 %3:sreg_64_xexec(s1) = COPY %8(s1)
537 S_ENDPGM 0, implicit %3