| blob | 9480df5e83ba11838a9b9aa48f07eb4a4d9edf18 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -global-isel -march=amdgcn -mcpu=tahiti -verify-machineinstrs -o - < %s | FileCheck %s --check-prefixes=GFX,GFX6
3 ; RUN: llc -global-isel -march=amdgcn -mcpu=fiji -verify-machineinstrs -o - < %s | FileCheck %s --check-prefixes=GFX,GFX8
4 ; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs -o - < %s | FileCheck %s --check-prefixes=GFX,GFX10
6 declare i16 @llvm.abs.i16(i16, i1)
7 declare i32 @llvm.abs.i32(i32, i1)
8 declare i64 @llvm.abs.i64(i64, i1)
9 declare <2 x i8> @llvm.abs.v2i8(<2 x i8>, i1)
10 declare <3 x i8> @llvm.abs.v3i8(<3 x i8>, i1)
11 declare <2 x i16> @llvm.abs.v2i16(<2 x i16>, i1)
12 declare <3 x i16> @llvm.abs.v3i16(<3 x i16>, i1)
13 declare <4 x i32> @llvm.abs.v4i32(<4 x i32>, i1)
15 define amdgpu_cs i16 @abs_sgpr_i16(i16 inreg %arg) {
16 ; GFX-LABEL: abs_sgpr_i16:
17 ; GFX: ; %bb.0:
18 ; GFX-NEXT: s_sext_i32_i16 s0, s0
19 ; GFX-NEXT: s_abs_i32 s0, s0
20 ; GFX-NEXT: ; return to shader part epilog
21 %res = call i16 @llvm.abs.i16(i16 %arg, i1 false)
22 ret i16 %res
23 }
25 define amdgpu_cs i32 @abs_sgpr_i32(i32 inreg %arg) {
26 ; GFX-LABEL: abs_sgpr_i32:
27 ; GFX: ; %bb.0:
28 ; GFX-NEXT: s_abs_i32 s0, s0
29 ; GFX-NEXT: ; return to shader part epilog
30 %res = call i32 @llvm.abs.i32(i32 %arg, i1 false)
31 ret i32 %res
32 }
34 define amdgpu_cs i64 @abs_sgpr_i64(i64 inreg %arg) {
35 ; GFX-LABEL: abs_sgpr_i64:
36 ; GFX: ; %bb.0:
37 ; GFX-NEXT: s_ashr_i32 s2, s1, 31
38 ; GFX-NEXT: s_add_u32 s0, s0, s2
39 ; GFX-NEXT: s_mov_b32 s3, s2
40 ; GFX-NEXT: s_addc_u32 s1, s1, s2
41 ; GFX-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3]
42 ; GFX-NEXT: ; return to shader part epilog
43 %res = call i64 @llvm.abs.i64(i64 %arg, i1 false)
44 ret i64 %res
45 }
47 define amdgpu_cs <4 x i32> @abs_sgpr_v4i32(<4 x i32> inreg %arg) {
48 ; GFX-LABEL: abs_sgpr_v4i32:
49 ; GFX: ; %bb.0:
50 ; GFX-NEXT: s_abs_i32 s0, s0
51 ; GFX-NEXT: s_abs_i32 s1, s1
52 ; GFX-NEXT: s_abs_i32 s2, s2
53 ; GFX-NEXT: s_abs_i32 s3, s3
54 ; GFX-NEXT: ; return to shader part epilog
55 %res = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %arg, i1 false)
56 ret <4 x i32> %res
57 }
59 define amdgpu_cs i16 @abs_vgpr_i16(i16 %arg) {
60 ; GFX6-LABEL: abs_vgpr_i16:
61 ; GFX6: ; %bb.0:
62 ; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16
63 ; GFX6-NEXT: v_sub_i32_e32 v1, vcc, 0, v0
64 ; GFX6-NEXT: v_max_i32_e32 v0, v0, v1
65 ; GFX6-NEXT: v_readfirstlane_b32 s0, v0
66 ; GFX6-NEXT: ; return to shader part epilog
67 ;
68 ; GFX8-LABEL: abs_vgpr_i16:
69 ; GFX8: ; %bb.0:
70 ; GFX8-NEXT: v_sub_u16_e32 v1, 0, v0
71 ; GFX8-NEXT: v_max_i16_e32 v0, v0, v1
72 ; GFX8-NEXT: v_readfirstlane_b32 s0, v0
73 ; GFX8-NEXT: ; return to shader part epilog
74 ;
75 ; GFX10-LABEL: abs_vgpr_i16:
76 ; GFX10: ; %bb.0:
77 ; GFX10-NEXT: v_sub_nc_u16 v1, 0, v0
78 ; GFX10-NEXT: v_max_i16 v0, v0, v1
79 ; GFX10-NEXT: v_readfirstlane_b32 s0, v0
80 ; GFX10-NEXT: ; return to shader part epilog
81 %res = call i16 @llvm.abs.i16(i16 %arg, i1 false)
82 ret i16 %res
83 }
85 define amdgpu_cs i32 @abs_vgpr_i32(i32 %arg) {
86 ; GFX6-LABEL: abs_vgpr_i32:
87 ; GFX6: ; %bb.0:
88 ; GFX6-NEXT: v_sub_i32_e32 v1, vcc, 0, v0
89 ; GFX6-NEXT: v_max_i32_e32 v0, v0, v1
90 ; GFX6-NEXT: v_readfirstlane_b32 s0, v0
91 ; GFX6-NEXT: ; return to shader part epilog
92 ;
93 ; GFX8-LABEL: abs_vgpr_i32:
94 ; GFX8: ; %bb.0:
95 ; GFX8-NEXT: v_sub_u32_e32 v1, vcc, 0, v0
96 ; GFX8-NEXT: v_max_i32_e32 v0, v0, v1
97 ; GFX8-NEXT: v_readfirstlane_b32 s0, v0
98 ; GFX8-NEXT: ; return to shader part epilog
99 ;
100 ; GFX10-LABEL: abs_vgpr_i32:
101 ; GFX10: ; %bb.0:
102 ; GFX10-NEXT: v_sub_nc_u32_e32 v1, 0, v0
103 ; GFX10-NEXT: v_max_i32_e32 v0, v0, v1
104 ; GFX10-NEXT: v_readfirstlane_b32 s0, v0
105 ; GFX10-NEXT: ; return to shader part epilog
106 %res = call i32 @llvm.abs.i32(i32 %arg, i1 false)
107 ret i32 %res
108 }
110 define amdgpu_cs i64 @abs_vgpr_i64(i64 %arg) {
111 ; GFX6-LABEL: abs_vgpr_i64:
112 ; GFX6: ; %bb.0:
113 ; GFX6-NEXT: v_ashrrev_i32_e32 v2, 31, v1
114 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
115 ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc
116 ; GFX6-NEXT: v_xor_b32_e32 v0, v0, v2
117 ; GFX6-NEXT: v_xor_b32_e32 v1, v1, v2
118 ; GFX6-NEXT: v_readfirstlane_b32 s0, v0
119 ; GFX6-NEXT: v_readfirstlane_b32 s1, v1
120 ; GFX6-NEXT: ; return to shader part epilog
121 ;
122 ; GFX8-LABEL: abs_vgpr_i64:
123 ; GFX8: ; %bb.0:
124 ; GFX8-NEXT: v_ashrrev_i32_e32 v2, 31, v1
125 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2
126 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, v1, v2, vcc
127 ; GFX8-NEXT: v_xor_b32_e32 v0, v0, v2
128 ; GFX8-NEXT: v_xor_b32_e32 v1, v1, v2
129 ; GFX8-NEXT: v_readfirstlane_b32 s0, v0
130 ; GFX8-NEXT: v_readfirstlane_b32 s1, v1
131 ; GFX8-NEXT: ; return to shader part epilog
132 ;
133 ; GFX10-LABEL: abs_vgpr_i64:
134 ; GFX10: ; %bb.0:
135 ; GFX10-NEXT: v_ashrrev_i32_e32 v2, 31, v1
136 ; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
137 ; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v2, vcc_lo
138 ; GFX10-NEXT: v_xor_b32_e32 v0, v0, v2
139 ; GFX10-NEXT: v_xor_b32_e32 v1, v1, v2
140 ; GFX10-NEXT: v_readfirstlane_b32 s0, v0
141 ; GFX10-NEXT: v_readfirstlane_b32 s1, v1
142 ; GFX10-NEXT: ; return to shader part epilog
143 %res = call i64 @llvm.abs.i64(i64 %arg, i1 false)
144 ret i64 %res
145 }
147 define amdgpu_cs <4 x i32> @abs_vgpr_v4i32(<4 x i32> %arg) {
148 ; GFX6-LABEL: abs_vgpr_v4i32:
149 ; GFX6: ; %bb.0:
150 ; GFX6-NEXT: v_sub_i32_e32 v4, vcc, 0, v0
151 ; GFX6-NEXT: v_max_i32_e32 v0, v0, v4
152 ; GFX6-NEXT: v_sub_i32_e32 v4, vcc, 0, v1
153 ; GFX6-NEXT: v_max_i32_e32 v1, v1, v4
154 ; GFX6-NEXT: v_sub_i32_e32 v4, vcc, 0, v2
155 ; GFX6-NEXT: v_max_i32_e32 v2, v2, v4
156 ; GFX6-NEXT: v_sub_i32_e32 v4, vcc, 0, v3
157 ; GFX6-NEXT: v_max_i32_e32 v3, v3, v4
158 ; GFX6-NEXT: v_readfirstlane_b32 s0, v0
159 ; GFX6-NEXT: v_readfirstlane_b32 s1, v1
160 ; GFX6-NEXT: v_readfirstlane_b32 s2, v2
161 ; GFX6-NEXT: v_readfirstlane_b32 s3, v3
162 ; GFX6-NEXT: ; return to shader part epilog
163 ;
164 ; GFX8-LABEL: abs_vgpr_v4i32:
165 ; GFX8: ; %bb.0:
166 ; GFX8-NEXT: v_sub_u32_e32 v4, vcc, 0, v0
167 ; GFX8-NEXT: v_max_i32_e32 v0, v0, v4
168 ; GFX8-NEXT: v_sub_u32_e32 v4, vcc, 0, v1
169 ; GFX8-NEXT: v_max_i32_e32 v1, v1, v4
170 ; GFX8-NEXT: v_sub_u32_e32 v4, vcc, 0, v2
171 ; GFX8-NEXT: v_max_i32_e32 v2, v2, v4
172 ; GFX8-NEXT: v_sub_u32_e32 v4, vcc, 0, v3
173 ; GFX8-NEXT: v_max_i32_e32 v3, v3, v4
174 ; GFX8-NEXT: v_readfirstlane_b32 s0, v0
175 ; GFX8-NEXT: v_readfirstlane_b32 s1, v1
176 ; GFX8-NEXT: v_readfirstlane_b32 s2, v2
177 ; GFX8-NEXT: v_readfirstlane_b32 s3, v3
178 ; GFX8-NEXT: ; return to shader part epilog
179 ;
180 ; GFX10-LABEL: abs_vgpr_v4i32:
181 ; GFX10: ; %bb.0:
182 ; GFX10-NEXT: v_sub_nc_u32_e32 v4, 0, v0
183 ; GFX10-NEXT: v_sub_nc_u32_e32 v5, 0, v1
184 ; GFX10-NEXT: v_sub_nc_u32_e32 v6, 0, v2
185 ; GFX10-NEXT: v_sub_nc_u32_e32 v7, 0, v3
186 ; GFX10-NEXT: v_max_i32_e32 v0, v0, v4
187 ; GFX10-NEXT: v_max_i32_e32 v1, v1, v5
188 ; GFX10-NEXT: v_max_i32_e32 v2, v2, v6
189 ; GFX10-NEXT: v_max_i32_e32 v3, v3, v7
190 ; GFX10-NEXT: v_readfirstlane_b32 s0, v0
191 ; GFX10-NEXT: v_readfirstlane_b32 s1, v1
192 ; GFX10-NEXT: v_readfirstlane_b32 s2, v2
193 ; GFX10-NEXT: v_readfirstlane_b32 s3, v3
194 ; GFX10-NEXT: ; return to shader part epilog
195 %res = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %arg, i1 false)
196 ret <4 x i32> %res
197 }
199 define amdgpu_cs <2 x i8> @abs_sgpr_v2i8(<2 x i8> inreg %arg) {
200 ; GFX6-LABEL: abs_sgpr_v2i8:
201 ; GFX6: ; %bb.0:
202 ; GFX6-NEXT: s_sext_i32_i8 s0, s0
203 ; GFX6-NEXT: s_sext_i32_i8 s1, s1
204 ; GFX6-NEXT: s_abs_i32 s0, s0
205 ; GFX6-NEXT: s_abs_i32 s1, s1
206 ; GFX6-NEXT: ; return to shader part epilog
207 ;
208 ; GFX8-LABEL: abs_sgpr_v2i8:
209 ; GFX8: ; %bb.0:
210 ; GFX8-NEXT: s_lshl_b32 s0, s0, 8
211 ; GFX8-NEXT: s_lshl_b32 s1, s1, 8
212 ; GFX8-NEXT: s_sext_i32_i16 s0, s0
213 ; GFX8-NEXT: s_sext_i32_i16 s1, s1
214 ; GFX8-NEXT: s_ashr_i32 s0, s0, 8
215 ; GFX8-NEXT: s_ashr_i32 s1, s1, 8
216 ; GFX8-NEXT: s_sext_i32_i16 s0, s0
217 ; GFX8-NEXT: s_sext_i32_i16 s1, s1
218 ; GFX8-NEXT: s_abs_i32 s0, s0
219 ; GFX8-NEXT: s_abs_i32 s1, s1
220 ; GFX8-NEXT: ; return to shader part epilog
221 ;
222 ; GFX10-LABEL: abs_sgpr_v2i8:
223 ; GFX10: ; %bb.0:
224 ; GFX10-NEXT: s_sext_i32_i8 s0, s0
225 ; GFX10-NEXT: s_sext_i32_i8 s1, s1
226 ; GFX10-NEXT: s_sext_i32_i16 s0, s0
227 ; GFX10-NEXT: s_sext_i32_i16 s1, s1
228 ; GFX10-NEXT: s_abs_i32 s0, s0
229 ; GFX10-NEXT: s_abs_i32 s1, s1
230 ; GFX10-NEXT: ; return to shader part epilog
231 %res = call <2 x i8> @llvm.abs.v2i8(<2 x i8> %arg, i1 false)
232 ret <2 x i8> %res
233 }
235 define amdgpu_cs <2 x i8> @abs_vgpr_v2i8(<2 x i8> %arg) {
236 ; GFX6-LABEL: abs_vgpr_v2i8:
237 ; GFX6: ; %bb.0:
238 ; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 8
239 ; GFX6-NEXT: v_sub_i32_e32 v2, vcc, 0, v0
240 ; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 8
241 ; GFX6-NEXT: v_max_i32_e32 v0, v0, v2
242 ; GFX6-NEXT: v_sub_i32_e32 v2, vcc, 0, v1
243 ; GFX6-NEXT: v_max_i32_e32 v1, v1, v2
244 ; GFX6-NEXT: v_readfirstlane_b32 s0, v0
245 ; GFX6-NEXT: v_readfirstlane_b32 s1, v1
246 ; GFX6-NEXT: ; return to shader part epilog
247 ;
248 ; GFX8-LABEL: abs_vgpr_v2i8:
249 ; GFX8: ; %bb.0:
250 ; GFX8-NEXT: v_lshlrev_b16_e32 v0, 8, v0
251 ; GFX8-NEXT: v_ashrrev_i16_e32 v0, 8, v0
252 ; GFX8-NEXT: v_lshlrev_b16_e32 v1, 8, v1
253 ; GFX8-NEXT: v_sub_u16_e32 v2, 0, v0
254 ; GFX8-NEXT: v_ashrrev_i16_e32 v1, 8, v1
255 ; GFX8-NEXT: v_max_i16_e32 v0, v0, v2
256 ; GFX8-NEXT: v_sub_u16_e32 v2, 0, v1
257 ; GFX8-NEXT: v_max_i16_e32 v1, v1, v2
258 ; GFX8-NEXT: v_readfirstlane_b32 s0, v0
259 ; GFX8-NEXT: v_readfirstlane_b32 s1, v1
260 ; GFX8-NEXT: ; return to shader part epilog
261 ;
262 ; GFX10-LABEL: abs_vgpr_v2i8:
263 ; GFX10: ; %bb.0:
264 ; GFX10-NEXT: v_bfe_i32 v0, v0, 0, 8
265 ; GFX10-NEXT: v_bfe_i32 v1, v1, 0, 8
266 ; GFX10-NEXT: v_sub_nc_u16 v2, 0, v0
267 ; GFX10-NEXT: v_sub_nc_u16 v3, 0, v1
268 ; GFX10-NEXT: v_max_i16 v0, v0, v2
269 ; GFX10-NEXT: v_max_i16 v1, v1, v3
270 ; GFX10-NEXT: v_readfirstlane_b32 s0, v0
271 ; GFX10-NEXT: v_readfirstlane_b32 s1, v1
272 ; GFX10-NEXT: ; return to shader part epilog
273 %res = call <2 x i8> @llvm.abs.v2i8(<2 x i8> %arg, i1 false)
274 ret <2 x i8> %res
275 }
277 define amdgpu_cs <3 x i8> @abs_sgpr_v3i8(<3 x i8> inreg %arg) {
278 ; GFX6-LABEL: abs_sgpr_v3i8:
279 ; GFX6: ; %bb.0:
280 ; GFX6-NEXT: s_sext_i32_i8 s0, s0
281 ; GFX6-NEXT: s_sext_i32_i8 s1, s1
282 ; GFX6-NEXT: s_sext_i32_i8 s2, s2
283 ; GFX6-NEXT: s_abs_i32 s0, s0
284 ; GFX6-NEXT: s_abs_i32 s1, s1
285 ; GFX6-NEXT: s_abs_i32 s2, s2
286 ; GFX6-NEXT: ; return to shader part epilog
287 ;
288 ; GFX8-LABEL: abs_sgpr_v3i8:
289 ; GFX8: ; %bb.0:
290 ; GFX8-NEXT: s_lshl_b32 s0, s0, 8
291 ; GFX8-NEXT: s_lshl_b32 s1, s1, 8
292 ; GFX8-NEXT: s_lshl_b32 s2, s2, 8
293 ; GFX8-NEXT: s_sext_i32_i16 s0, s0
294 ; GFX8-NEXT: s_sext_i32_i16 s1, s1
295 ; GFX8-NEXT: s_sext_i32_i16 s2, s2
296 ; GFX8-NEXT: s_ashr_i32 s0, s0, 8
297 ; GFX8-NEXT: s_ashr_i32 s1, s1, 8
298 ; GFX8-NEXT: s_ashr_i32 s2, s2, 8
299 ; GFX8-NEXT: s_sext_i32_i16 s0, s0
300 ; GFX8-NEXT: s_sext_i32_i16 s1, s1
301 ; GFX8-NEXT: s_sext_i32_i16 s2, s2
302 ; GFX8-NEXT: s_abs_i32 s0, s0
303 ; GFX8-NEXT: s_abs_i32 s1, s1
304 ; GFX8-NEXT: s_abs_i32 s2, s2
305 ; GFX8-NEXT: ; return to shader part epilog
306 ;
307 ; GFX10-LABEL: abs_sgpr_v3i8:
308 ; GFX10: ; %bb.0:
309 ; GFX10-NEXT: s_sext_i32_i8 s0, s0
310 ; GFX10-NEXT: s_sext_i32_i8 s1, s1
311 ; GFX10-NEXT: s_sext_i32_i8 s2, s2
312 ; GFX10-NEXT: s_sext_i32_i16 s0, s0
313 ; GFX10-NEXT: s_sext_i32_i16 s1, s1
314 ; GFX10-NEXT: s_sext_i32_i16 s2, s2
315 ; GFX10-NEXT: s_abs_i32 s0, s0
316 ; GFX10-NEXT: s_abs_i32 s1, s1
317 ; GFX10-NEXT: s_abs_i32 s2, s2
318 ; GFX10-NEXT: ; return to shader part epilog
319 %res = call <3 x i8> @llvm.abs.v3i8(<3 x i8> %arg, i1 false)
320 ret <3 x i8> %res
321 }
323 define amdgpu_cs <3 x i8> @abs_vgpr_v3i8(<3 x i8> %arg) {
324 ; GFX6-LABEL: abs_vgpr_v3i8:
325 ; GFX6: ; %bb.0:
326 ; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 8
327 ; GFX6-NEXT: v_sub_i32_e32 v3, vcc, 0, v0
328 ; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 8
329 ; GFX6-NEXT: v_max_i32_e32 v0, v0, v3
330 ; GFX6-NEXT: v_sub_i32_e32 v3, vcc, 0, v1
331 ; GFX6-NEXT: v_bfe_i32 v2, v2, 0, 8
332 ; GFX6-NEXT: v_max_i32_e32 v1, v1, v3
333 ; GFX6-NEXT: v_sub_i32_e32 v3, vcc, 0, v2
334 ; GFX6-NEXT: v_max_i32_e32 v2, v2, v3
335 ; GFX6-NEXT: v_readfirstlane_b32 s0, v0
336 ; GFX6-NEXT: v_readfirstlane_b32 s1, v1
337 ; GFX6-NEXT: v_readfirstlane_b32 s2, v2
338 ; GFX6-NEXT: ; return to shader part epilog
339 ;
340 ; GFX8-LABEL: abs_vgpr_v3i8:
341 ; GFX8: ; %bb.0:
342 ; GFX8-NEXT: v_lshlrev_b16_e32 v0, 8, v0
343 ; GFX8-NEXT: v_ashrrev_i16_e32 v0, 8, v0
344 ; GFX8-NEXT: v_lshlrev_b16_e32 v1, 8, v1
345 ; GFX8-NEXT: v_sub_u16_e32 v3, 0, v0
346 ; GFX8-NEXT: v_ashrrev_i16_e32 v1, 8, v1
347 ; GFX8-NEXT: v_lshlrev_b16_e32 v2, 8, v2
348 ; GFX8-NEXT: v_max_i16_e32 v0, v0, v3
349 ; GFX8-NEXT: v_sub_u16_e32 v3, 0, v1
350 ; GFX8-NEXT: v_ashrrev_i16_e32 v2, 8, v2
351 ; GFX8-NEXT: v_max_i16_e32 v1, v1, v3
352 ; GFX8-NEXT: v_sub_u16_e32 v3, 0, v2
353 ; GFX8-NEXT: v_max_i16_e32 v2, v2, v3
354 ; GFX8-NEXT: v_readfirstlane_b32 s0, v0
355 ; GFX8-NEXT: v_readfirstlane_b32 s1, v1
356 ; GFX8-NEXT: v_readfirstlane_b32 s2, v2
357 ; GFX8-NEXT: ; return to shader part epilog
358 ;
359 ; GFX10-LABEL: abs_vgpr_v3i8:
360 ; GFX10: ; %bb.0:
361 ; GFX10-NEXT: v_bfe_i32 v0, v0, 0, 8
362 ; GFX10-NEXT: v_bfe_i32 v1, v1, 0, 8
363 ; GFX10-NEXT: v_bfe_i32 v2, v2, 0, 8
364 ; GFX10-NEXT: v_sub_nc_u16 v3, 0, v0
365 ; GFX10-NEXT: v_sub_nc_u16 v4, 0, v1
366 ; GFX10-NEXT: v_sub_nc_u16 v5, 0, v2
367 ; GFX10-NEXT: v_max_i16 v0, v0, v3
368 ; GFX10-NEXT: v_max_i16 v1, v1, v4
369 ; GFX10-NEXT: v_max_i16 v2, v2, v5
370 ; GFX10-NEXT: v_readfirstlane_b32 s0, v0
371 ; GFX10-NEXT: v_readfirstlane_b32 s1, v1
372 ; GFX10-NEXT: v_readfirstlane_b32 s2, v2
373 ; GFX10-NEXT: ; return to shader part epilog
374 %res = call <3 x i8> @llvm.abs.v3i8(<3 x i8> %arg, i1 false)
375 ret <3 x i8> %res
376 }
378 define amdgpu_cs <2 x i16> @abs_sgpr_v2i16(<2 x i16> inreg %arg) {
379 ; GFX6-LABEL: abs_sgpr_v2i16:
380 ; GFX6: ; %bb.0:
381 ; GFX6-NEXT: s_sext_i32_i16 s0, s0
382 ; GFX6-NEXT: s_sext_i32_i16 s1, s1
383 ; GFX6-NEXT: s_abs_i32 s0, s0
384 ; GFX6-NEXT: s_abs_i32 s1, s1
385 ; GFX6-NEXT: ; return to shader part epilog
386 ;
387 ; GFX8-LABEL: abs_sgpr_v2i16:
388 ; GFX8: ; %bb.0:
389 ; GFX8-NEXT: s_lshr_b32 s1, s0, 16
390 ; GFX8-NEXT: s_sext_i32_i16 s1, s1
391 ; GFX8-NEXT: s_sext_i32_i16 s0, s0
392 ; GFX8-NEXT: s_abs_i32 s1, s1
393 ; GFX8-NEXT: s_abs_i32 s0, s0
394 ; GFX8-NEXT: s_and_b32 s1, 0xffff, s1
395 ; GFX8-NEXT: s_and_b32 s0, 0xffff, s0
396 ; GFX8-NEXT: s_lshl_b32 s1, s1, 16
397 ; GFX8-NEXT: s_or_b32 s0, s0, s1
398 ; GFX8-NEXT: ; return to shader part epilog
399 ;
400 ; GFX10-LABEL: abs_sgpr_v2i16:
401 ; GFX10: ; %bb.0:
402 ; GFX10-NEXT: s_sext_i32_i16 s1, s0
403 ; GFX10-NEXT: s_ashr_i32 s0, s0, 16
404 ; GFX10-NEXT: s_abs_i32 s1, s1
405 ; GFX10-NEXT: s_abs_i32 s0, s0
406 ; GFX10-NEXT: s_pack_ll_b32_b16 s0, s1, s0
407 ; GFX10-NEXT: ; return to shader part epilog
408 %res = call <2 x i16> @llvm.abs.v2i16(<2 x i16> %arg, i1 false)
409 ret <2 x i16> %res
410 }
412 define amdgpu_cs <2 x i16> @abs_vgpr_v2i16(<2 x i16> %arg) {
413 ; GFX6-LABEL: abs_vgpr_v2i16:
414 ; GFX6: ; %bb.0:
415 ; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16
416 ; GFX6-NEXT: v_sub_i32_e32 v2, vcc, 0, v0
417 ; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16
418 ; GFX6-NEXT: v_max_i32_e32 v0, v0, v2
419 ; GFX6-NEXT: v_sub_i32_e32 v2, vcc, 0, v1
420 ; GFX6-NEXT: v_max_i32_e32 v1, v1, v2
421 ; GFX6-NEXT: v_readfirstlane_b32 s0, v0
422 ; GFX6-NEXT: v_readfirstlane_b32 s1, v1
423 ; GFX6-NEXT: ; return to shader part epilog
424 ;
425 ; GFX8-LABEL: abs_vgpr_v2i16:
426 ; GFX8: ; %bb.0:
427 ; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v0
428 ; GFX8-NEXT: v_sub_u16_e32 v2, 0, v0
429 ; GFX8-NEXT: v_sub_u16_e32 v3, 0, v1
430 ; GFX8-NEXT: v_max_i16_e32 v0, v0, v2
431 ; GFX8-NEXT: v_max_i16_sdwa v1, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
432 ; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
433 ; GFX8-NEXT: v_readfirstlane_b32 s0, v0
434 ; GFX8-NEXT: ; return to shader part epilog
435 ;
436 ; GFX10-LABEL: abs_vgpr_v2i16:
437 ; GFX10: ; %bb.0:
438 ; GFX10-NEXT: v_pk_sub_i16 v1, 0, v0
439 ; GFX10-NEXT: v_pk_max_i16 v0, v0, v1
440 ; GFX10-NEXT: v_readfirstlane_b32 s0, v0
441 ; GFX10-NEXT: ; return to shader part epilog
442 %res = call <2 x i16> @llvm.abs.v2i16(<2 x i16> %arg, i1 false)
443 ret <2 x i16> %res
444 }
446 define amdgpu_cs <3 x i16> @abs_sgpr_v3i16(<3 x i16> inreg %arg) {
447 ; GFX6-LABEL: abs_sgpr_v3i16:
448 ; GFX6: ; %bb.0:
449 ; GFX6-NEXT: s_sext_i32_i16 s0, s0
450 ; GFX6-NEXT: s_sext_i32_i16 s1, s1
451 ; GFX6-NEXT: s_sext_i32_i16 s2, s2
452 ; GFX6-NEXT: s_abs_i32 s0, s0
453 ; GFX6-NEXT: s_abs_i32 s1, s1
454 ; GFX6-NEXT: s_abs_i32 s2, s2
455 ; GFX6-NEXT: ; return to shader part epilog
456 ;
457 ; GFX8-LABEL: abs_sgpr_v3i16:
458 ; GFX8: ; %bb.0:
459 ; GFX8-NEXT: s_lshr_b32 s2, s0, 16
460 ; GFX8-NEXT: s_sext_i32_i16 s2, s2
461 ; GFX8-NEXT: s_sext_i32_i16 s0, s0
462 ; GFX8-NEXT: s_abs_i32 s2, s2
463 ; GFX8-NEXT: s_abs_i32 s0, s0
464 ; GFX8-NEXT: s_sext_i32_i16 s1, s1
465 ; GFX8-NEXT: s_and_b32 s2, 0xffff, s2
466 ; GFX8-NEXT: s_abs_i32 s1, s1
467 ; GFX8-NEXT: s_and_b32 s0, 0xffff, s0
468 ; GFX8-NEXT: s_lshl_b32 s2, s2, 16
469 ; GFX8-NEXT: s_or_b32 s0, s0, s2
470 ; GFX8-NEXT: s_and_b32 s1, 0xffff, s1
471 ; GFX8-NEXT: ; return to shader part epilog
472 ;
473 ; GFX10-LABEL: abs_sgpr_v3i16:
474 ; GFX10: ; %bb.0:
475 ; GFX10-NEXT: s_sext_i32_i16 s2, s0
476 ; GFX10-NEXT: s_ashr_i32 s0, s0, 16
477 ; GFX10-NEXT: s_abs_i32 s2, s2
478 ; GFX10-NEXT: s_abs_i32 s0, s0
479 ; GFX10-NEXT: s_sext_i32_i16 s1, s1
480 ; GFX10-NEXT: s_pack_ll_b32_b16 s0, s2, s0
481 ; GFX10-NEXT: s_abs_i32 s1, s1
482 ; GFX10-NEXT: ; return to shader part epilog
483 %res = call <3 x i16> @llvm.abs.v3i16(<3 x i16> %arg, i1 false)
484 ret <3 x i16> %res
485 }
487 define amdgpu_cs <3 x i16> @abs_vgpr_v3i16(<3 x i16> %arg) {
488 ; GFX6-LABEL: abs_vgpr_v3i16:
489 ; GFX6: ; %bb.0:
490 ; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16
491 ; GFX6-NEXT: v_sub_i32_e32 v3, vcc, 0, v0
492 ; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16
493 ; GFX6-NEXT: v_max_i32_e32 v0, v0, v3
494 ; GFX6-NEXT: v_sub_i32_e32 v3, vcc, 0, v1
495 ; GFX6-NEXT: v_bfe_i32 v2, v2, 0, 16
496 ; GFX6-NEXT: v_max_i32_e32 v1, v1, v3
497 ; GFX6-NEXT: v_sub_i32_e32 v3, vcc, 0, v2
498 ; GFX6-NEXT: v_max_i32_e32 v2, v2, v3
499 ; GFX6-NEXT: v_readfirstlane_b32 s0, v0
500 ; GFX6-NEXT: v_readfirstlane_b32 s1, v1
501 ; GFX6-NEXT: v_readfirstlane_b32 s2, v2
502 ; GFX6-NEXT: ; return to shader part epilog
503 ;
504 ; GFX8-LABEL: abs_vgpr_v3i16:
505 ; GFX8: ; %bb.0:
506 ; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v0
507 ; GFX8-NEXT: v_sub_u16_e32 v3, 0, v0
508 ; GFX8-NEXT: v_sub_u16_e32 v4, 0, v2
509 ; GFX8-NEXT: v_sub_u16_e32 v5, 0, v1
510 ; GFX8-NEXT: v_max_i16_e32 v0, v0, v3
511 ; GFX8-NEXT: v_max_i16_sdwa v2, v2, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
512 ; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
513 ; GFX8-NEXT: v_max_i16_e32 v1, v1, v5
514 ; GFX8-NEXT: v_readfirstlane_b32 s0, v0
515 ; GFX8-NEXT: v_readfirstlane_b32 s1, v1
516 ; GFX8-NEXT: ; return to shader part epilog
517 ;
518 ; GFX10-LABEL: abs_vgpr_v3i16:
519 ; GFX10: ; %bb.0:
520 ; GFX10-NEXT: v_pk_sub_i16 v2, 0, v0
521 ; GFX10-NEXT: v_sub_nc_u16 v3, 0, v1
522 ; GFX10-NEXT: v_pk_max_i16 v0, v0, v2
523 ; GFX10-NEXT: v_max_i16 v1, v1, v3
524 ; GFX10-NEXT: v_readfirstlane_b32 s0, v0
525 ; GFX10-NEXT: v_readfirstlane_b32 s1, v1
526 ; GFX10-NEXT: ; return to shader part epilog
527 %res = call <3 x i16> @llvm.abs.v3i16(<3 x i16> %arg, i1 false)
528 ret <3 x i16> %res
529 }