| blob | 06c3220784059467e673d1b646559bb64c3552d9 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GFX68 %s
3 ; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GFX68 %s
4 ; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX10 %s
5 ; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -mattr=-enable-prt-strict-null -verify-machineinstrs < %s | FileCheck -check-prefix=NOPRT %s
6 ; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX10 %s
8 define amdgpu_ps float @load_1d_f32_x(<8 x i32> inreg %rsrc, i32 %s) {
9 ; GFX68-LABEL: load_1d_f32_x:
10 ; GFX68: ; %bb.0:
11 ; GFX68-NEXT: s_mov_b32 s0, s2
12 ; GFX68-NEXT: s_mov_b32 s1, s3
13 ; GFX68-NEXT: s_mov_b32 s2, s4
14 ; GFX68-NEXT: s_mov_b32 s3, s5
15 ; GFX68-NEXT: s_mov_b32 s4, s6
16 ; GFX68-NEXT: s_mov_b32 s5, s7
17 ; GFX68-NEXT: s_mov_b32 s6, s8
18 ; GFX68-NEXT: s_mov_b32 s7, s9
19 ; GFX68-NEXT: image_load v0, v0, s[0:7] dmask:0x1 unorm
20 ; GFX68-NEXT: s_waitcnt vmcnt(0)
21 ; GFX68-NEXT: ; return to shader part epilog
22 ;
23 ; GFX10-LABEL: load_1d_f32_x:
24 ; GFX10: ; %bb.0:
25 ; GFX10-NEXT: s_mov_b32 s0, s2
26 ; GFX10-NEXT: s_mov_b32 s1, s3
27 ; GFX10-NEXT: s_mov_b32 s2, s4
28 ; GFX10-NEXT: s_mov_b32 s3, s5
29 ; GFX10-NEXT: s_mov_b32 s4, s6
30 ; GFX10-NEXT: s_mov_b32 s5, s7
31 ; GFX10-NEXT: s_mov_b32 s6, s8
32 ; GFX10-NEXT: s_mov_b32 s7, s9
33 ; GFX10-NEXT: image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm
34 ; GFX10-NEXT: s_waitcnt vmcnt(0)
35 ; GFX10-NEXT: ; return to shader part epilog
36 ;
37 ; NOPRT-LABEL: load_1d_f32_x:
38 ; NOPRT: ; %bb.0:
39 ; NOPRT-NEXT: s_mov_b32 s0, s2
40 ; NOPRT-NEXT: s_mov_b32 s1, s3
41 ; NOPRT-NEXT: s_mov_b32 s2, s4
42 ; NOPRT-NEXT: s_mov_b32 s3, s5
43 ; NOPRT-NEXT: s_mov_b32 s4, s6
44 ; NOPRT-NEXT: s_mov_b32 s5, s7
45 ; NOPRT-NEXT: s_mov_b32 s6, s8
46 ; NOPRT-NEXT: s_mov_b32 s7, s9
47 ; NOPRT-NEXT: image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm
48 ; NOPRT-NEXT: s_waitcnt vmcnt(0)
49 ; NOPRT-NEXT: ; return to shader part epilog
50 %v = call float @llvm.amdgcn.image.load.1d.f32.i32(i32 1, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
51 ret float %v
52 }
54 define amdgpu_ps float @load_1d_f32_y(<8 x i32> inreg %rsrc, i32 %s) {
55 ; GFX68-LABEL: load_1d_f32_y:
56 ; GFX68: ; %bb.0:
57 ; GFX68-NEXT: s_mov_b32 s0, s2
58 ; GFX68-NEXT: s_mov_b32 s1, s3
59 ; GFX68-NEXT: s_mov_b32 s2, s4
60 ; GFX68-NEXT: s_mov_b32 s3, s5
61 ; GFX68-NEXT: s_mov_b32 s4, s6
62 ; GFX68-NEXT: s_mov_b32 s5, s7
63 ; GFX68-NEXT: s_mov_b32 s6, s8
64 ; GFX68-NEXT: s_mov_b32 s7, s9
65 ; GFX68-NEXT: image_load v0, v0, s[0:7] dmask:0x2 unorm
66 ; GFX68-NEXT: s_waitcnt vmcnt(0)
67 ; GFX68-NEXT: ; return to shader part epilog
68 ;
69 ; GFX10-LABEL: load_1d_f32_y:
70 ; GFX10: ; %bb.0:
71 ; GFX10-NEXT: s_mov_b32 s0, s2
72 ; GFX10-NEXT: s_mov_b32 s1, s3
73 ; GFX10-NEXT: s_mov_b32 s2, s4
74 ; GFX10-NEXT: s_mov_b32 s3, s5
75 ; GFX10-NEXT: s_mov_b32 s4, s6
76 ; GFX10-NEXT: s_mov_b32 s5, s7
77 ; GFX10-NEXT: s_mov_b32 s6, s8
78 ; GFX10-NEXT: s_mov_b32 s7, s9
79 ; GFX10-NEXT: image_load v0, v0, s[0:7] dmask:0x2 dim:SQ_RSRC_IMG_1D unorm
80 ; GFX10-NEXT: s_waitcnt vmcnt(0)
81 ; GFX10-NEXT: ; return to shader part epilog
82 ;
83 ; NOPRT-LABEL: load_1d_f32_y:
84 ; NOPRT: ; %bb.0:
85 ; NOPRT-NEXT: s_mov_b32 s0, s2
86 ; NOPRT-NEXT: s_mov_b32 s1, s3
87 ; NOPRT-NEXT: s_mov_b32 s2, s4
88 ; NOPRT-NEXT: s_mov_b32 s3, s5
89 ; NOPRT-NEXT: s_mov_b32 s4, s6
90 ; NOPRT-NEXT: s_mov_b32 s5, s7
91 ; NOPRT-NEXT: s_mov_b32 s6, s8
92 ; NOPRT-NEXT: s_mov_b32 s7, s9
93 ; NOPRT-NEXT: image_load v0, v0, s[0:7] dmask:0x2 dim:SQ_RSRC_IMG_1D unorm
94 ; NOPRT-NEXT: s_waitcnt vmcnt(0)
95 ; NOPRT-NEXT: ; return to shader part epilog
96 %v = call float @llvm.amdgcn.image.load.1d.f32.i32(i32 2, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
97 ret float %v
98 }
100 define amdgpu_ps float @load_1d_f32_z(<8 x i32> inreg %rsrc, i32 %s) {
101 ; GFX68-LABEL: load_1d_f32_z:
102 ; GFX68: ; %bb.0:
103 ; GFX68-NEXT: s_mov_b32 s0, s2
104 ; GFX68-NEXT: s_mov_b32 s1, s3
105 ; GFX68-NEXT: s_mov_b32 s2, s4
106 ; GFX68-NEXT: s_mov_b32 s3, s5
107 ; GFX68-NEXT: s_mov_b32 s4, s6
108 ; GFX68-NEXT: s_mov_b32 s5, s7
109 ; GFX68-NEXT: s_mov_b32 s6, s8
110 ; GFX68-NEXT: s_mov_b32 s7, s9
111 ; GFX68-NEXT: image_load v0, v0, s[0:7] dmask:0x4 unorm
112 ; GFX68-NEXT: s_waitcnt vmcnt(0)
113 ; GFX68-NEXT: ; return to shader part epilog
114 ;
115 ; GFX10-LABEL: load_1d_f32_z:
116 ; GFX10: ; %bb.0:
117 ; GFX10-NEXT: s_mov_b32 s0, s2
118 ; GFX10-NEXT: s_mov_b32 s1, s3
119 ; GFX10-NEXT: s_mov_b32 s2, s4
120 ; GFX10-NEXT: s_mov_b32 s3, s5
121 ; GFX10-NEXT: s_mov_b32 s4, s6
122 ; GFX10-NEXT: s_mov_b32 s5, s7
123 ; GFX10-NEXT: s_mov_b32 s6, s8
124 ; GFX10-NEXT: s_mov_b32 s7, s9
125 ; GFX10-NEXT: image_load v0, v0, s[0:7] dmask:0x4 dim:SQ_RSRC_IMG_1D unorm
126 ; GFX10-NEXT: s_waitcnt vmcnt(0)
127 ; GFX10-NEXT: ; return to shader part epilog
128 ;
129 ; NOPRT-LABEL: load_1d_f32_z:
130 ; NOPRT: ; %bb.0:
131 ; NOPRT-NEXT: s_mov_b32 s0, s2
132 ; NOPRT-NEXT: s_mov_b32 s1, s3
133 ; NOPRT-NEXT: s_mov_b32 s2, s4
134 ; NOPRT-NEXT: s_mov_b32 s3, s5
135 ; NOPRT-NEXT: s_mov_b32 s4, s6
136 ; NOPRT-NEXT: s_mov_b32 s5, s7
137 ; NOPRT-NEXT: s_mov_b32 s6, s8
138 ; NOPRT-NEXT: s_mov_b32 s7, s9
139 ; NOPRT-NEXT: image_load v0, v0, s[0:7] dmask:0x4 dim:SQ_RSRC_IMG_1D unorm
140 ; NOPRT-NEXT: s_waitcnt vmcnt(0)
141 ; NOPRT-NEXT: ; return to shader part epilog
142 %v = call float @llvm.amdgcn.image.load.1d.f32.i32(i32 4, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
143 ret float %v
144 }
146 define amdgpu_ps float @load_1d_f32_w(<8 x i32> inreg %rsrc, i32 %s) {
147 ; GFX68-LABEL: load_1d_f32_w:
148 ; GFX68: ; %bb.0:
149 ; GFX68-NEXT: s_mov_b32 s0, s2
150 ; GFX68-NEXT: s_mov_b32 s1, s3
151 ; GFX68-NEXT: s_mov_b32 s2, s4
152 ; GFX68-NEXT: s_mov_b32 s3, s5
153 ; GFX68-NEXT: s_mov_b32 s4, s6
154 ; GFX68-NEXT: s_mov_b32 s5, s7
155 ; GFX68-NEXT: s_mov_b32 s6, s8
156 ; GFX68-NEXT: s_mov_b32 s7, s9
157 ; GFX68-NEXT: image_load v0, v0, s[0:7] dmask:0x8 unorm
158 ; GFX68-NEXT: s_waitcnt vmcnt(0)
159 ; GFX68-NEXT: ; return to shader part epilog
160 ;
161 ; GFX10-LABEL: load_1d_f32_w:
162 ; GFX10: ; %bb.0:
163 ; GFX10-NEXT: s_mov_b32 s0, s2
164 ; GFX10-NEXT: s_mov_b32 s1, s3
165 ; GFX10-NEXT: s_mov_b32 s2, s4
166 ; GFX10-NEXT: s_mov_b32 s3, s5
167 ; GFX10-NEXT: s_mov_b32 s4, s6
168 ; GFX10-NEXT: s_mov_b32 s5, s7
169 ; GFX10-NEXT: s_mov_b32 s6, s8
170 ; GFX10-NEXT: s_mov_b32 s7, s9
171 ; GFX10-NEXT: image_load v0, v0, s[0:7] dmask:0x8 dim:SQ_RSRC_IMG_1D unorm
172 ; GFX10-NEXT: s_waitcnt vmcnt(0)
173 ; GFX10-NEXT: ; return to shader part epilog
174 ;
175 ; NOPRT-LABEL: load_1d_f32_w:
176 ; NOPRT: ; %bb.0:
177 ; NOPRT-NEXT: s_mov_b32 s0, s2
178 ; NOPRT-NEXT: s_mov_b32 s1, s3
179 ; NOPRT-NEXT: s_mov_b32 s2, s4
180 ; NOPRT-NEXT: s_mov_b32 s3, s5
181 ; NOPRT-NEXT: s_mov_b32 s4, s6
182 ; NOPRT-NEXT: s_mov_b32 s5, s7
183 ; NOPRT-NEXT: s_mov_b32 s6, s8
184 ; NOPRT-NEXT: s_mov_b32 s7, s9
185 ; NOPRT-NEXT: image_load v0, v0, s[0:7] dmask:0x8 dim:SQ_RSRC_IMG_1D unorm
186 ; NOPRT-NEXT: s_waitcnt vmcnt(0)
187 ; NOPRT-NEXT: ; return to shader part epilog
188 %v = call float @llvm.amdgcn.image.load.1d.f32.i32(i32 8, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
189 ret float %v
190 }
192 define amdgpu_ps <2 x float> @load_1d_v2f32_xy(<8 x i32> inreg %rsrc, i32 %s) {
193 ; GFX68-LABEL: load_1d_v2f32_xy:
194 ; GFX68: ; %bb.0:
195 ; GFX68-NEXT: s_mov_b32 s0, s2
196 ; GFX68-NEXT: s_mov_b32 s1, s3
197 ; GFX68-NEXT: s_mov_b32 s2, s4
198 ; GFX68-NEXT: s_mov_b32 s3, s5
199 ; GFX68-NEXT: s_mov_b32 s4, s6
200 ; GFX68-NEXT: s_mov_b32 s5, s7
201 ; GFX68-NEXT: s_mov_b32 s6, s8
202 ; GFX68-NEXT: s_mov_b32 s7, s9
203 ; GFX68-NEXT: image_load v[0:1], v0, s[0:7] dmask:0x3 unorm
204 ; GFX68-NEXT: s_waitcnt vmcnt(0)
205 ; GFX68-NEXT: ; return to shader part epilog
206 ;
207 ; GFX10-LABEL: load_1d_v2f32_xy:
208 ; GFX10: ; %bb.0:
209 ; GFX10-NEXT: s_mov_b32 s0, s2
210 ; GFX10-NEXT: s_mov_b32 s1, s3
211 ; GFX10-NEXT: s_mov_b32 s2, s4
212 ; GFX10-NEXT: s_mov_b32 s3, s5
213 ; GFX10-NEXT: s_mov_b32 s4, s6
214 ; GFX10-NEXT: s_mov_b32 s5, s7
215 ; GFX10-NEXT: s_mov_b32 s6, s8
216 ; GFX10-NEXT: s_mov_b32 s7, s9
217 ; GFX10-NEXT: image_load v[0:1], v0, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm
218 ; GFX10-NEXT: s_waitcnt vmcnt(0)
219 ; GFX10-NEXT: ; return to shader part epilog
220 ;
221 ; NOPRT-LABEL: load_1d_v2f32_xy:
222 ; NOPRT: ; %bb.0:
223 ; NOPRT-NEXT: s_mov_b32 s0, s2
224 ; NOPRT-NEXT: s_mov_b32 s1, s3
225 ; NOPRT-NEXT: s_mov_b32 s2, s4
226 ; NOPRT-NEXT: s_mov_b32 s3, s5
227 ; NOPRT-NEXT: s_mov_b32 s4, s6
228 ; NOPRT-NEXT: s_mov_b32 s5, s7
229 ; NOPRT-NEXT: s_mov_b32 s6, s8
230 ; NOPRT-NEXT: s_mov_b32 s7, s9
231 ; NOPRT-NEXT: image_load v[0:1], v0, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm
232 ; NOPRT-NEXT: s_waitcnt vmcnt(0)
233 ; NOPRT-NEXT: ; return to shader part epilog
234 %v = call <2 x float> @llvm.amdgcn.image.load.1d.v2f32.i32(i32 3, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
235 ret <2 x float> %v
236 }
238 define amdgpu_ps <2 x float> @load_1d_v2f32_xz(<8 x i32> inreg %rsrc, i32 %s) {
239 ; GFX68-LABEL: load_1d_v2f32_xz:
240 ; GFX68: ; %bb.0:
241 ; GFX68-NEXT: s_mov_b32 s0, s2
242 ; GFX68-NEXT: s_mov_b32 s1, s3
243 ; GFX68-NEXT: s_mov_b32 s2, s4
244 ; GFX68-NEXT: s_mov_b32 s3, s5
245 ; GFX68-NEXT: s_mov_b32 s4, s6
246 ; GFX68-NEXT: s_mov_b32 s5, s7
247 ; GFX68-NEXT: s_mov_b32 s6, s8
248 ; GFX68-NEXT: s_mov_b32 s7, s9
249 ; GFX68-NEXT: image_load v[0:1], v0, s[0:7] dmask:0x5 unorm
250 ; GFX68-NEXT: s_waitcnt vmcnt(0)
251 ; GFX68-NEXT: ; return to shader part epilog
252 ;
253 ; GFX10-LABEL: load_1d_v2f32_xz:
254 ; GFX10: ; %bb.0:
255 ; GFX10-NEXT: s_mov_b32 s0, s2
256 ; GFX10-NEXT: s_mov_b32 s1, s3
257 ; GFX10-NEXT: s_mov_b32 s2, s4
258 ; GFX10-NEXT: s_mov_b32 s3, s5
259 ; GFX10-NEXT: s_mov_b32 s4, s6
260 ; GFX10-NEXT: s_mov_b32 s5, s7
261 ; GFX10-NEXT: s_mov_b32 s6, s8
262 ; GFX10-NEXT: s_mov_b32 s7, s9
263 ; GFX10-NEXT: image_load v[0:1], v0, s[0:7] dmask:0x5 dim:SQ_RSRC_IMG_1D unorm
264 ; GFX10-NEXT: s_waitcnt vmcnt(0)
265 ; GFX10-NEXT: ; return to shader part epilog
266 ;
267 ; NOPRT-LABEL: load_1d_v2f32_xz:
268 ; NOPRT: ; %bb.0:
269 ; NOPRT-NEXT: s_mov_b32 s0, s2
270 ; NOPRT-NEXT: s_mov_b32 s1, s3
271 ; NOPRT-NEXT: s_mov_b32 s2, s4
272 ; NOPRT-NEXT: s_mov_b32 s3, s5
273 ; NOPRT-NEXT: s_mov_b32 s4, s6
274 ; NOPRT-NEXT: s_mov_b32 s5, s7
275 ; NOPRT-NEXT: s_mov_b32 s6, s8
276 ; NOPRT-NEXT: s_mov_b32 s7, s9
277 ; NOPRT-NEXT: image_load v[0:1], v0, s[0:7] dmask:0x5 dim:SQ_RSRC_IMG_1D unorm
278 ; NOPRT-NEXT: s_waitcnt vmcnt(0)
279 ; NOPRT-NEXT: ; return to shader part epilog
280 %v = call <2 x float> @llvm.amdgcn.image.load.1d.v2f32.i32(i32 5, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
281 ret <2 x float> %v
282 }
284 define amdgpu_ps <2 x float> @load_1d_v2f32_xw(<8 x i32> inreg %rsrc, i32 %s) {
285 ; GFX68-LABEL: load_1d_v2f32_xw:
286 ; GFX68: ; %bb.0:
287 ; GFX68-NEXT: s_mov_b32 s0, s2
288 ; GFX68-NEXT: s_mov_b32 s1, s3
289 ; GFX68-NEXT: s_mov_b32 s2, s4
290 ; GFX68-NEXT: s_mov_b32 s3, s5
291 ; GFX68-NEXT: s_mov_b32 s4, s6
292 ; GFX68-NEXT: s_mov_b32 s5, s7
293 ; GFX68-NEXT: s_mov_b32 s6, s8
294 ; GFX68-NEXT: s_mov_b32 s7, s9
295 ; GFX68-NEXT: image_load v[0:1], v0, s[0:7] dmask:0x9 unorm
296 ; GFX68-NEXT: s_waitcnt vmcnt(0)
297 ; GFX68-NEXT: ; return to shader part epilog
298 ;
299 ; GFX10-LABEL: load_1d_v2f32_xw:
300 ; GFX10: ; %bb.0:
301 ; GFX10-NEXT: s_mov_b32 s0, s2
302 ; GFX10-NEXT: s_mov_b32 s1, s3
303 ; GFX10-NEXT: s_mov_b32 s2, s4
304 ; GFX10-NEXT: s_mov_b32 s3, s5
305 ; GFX10-NEXT: s_mov_b32 s4, s6
306 ; GFX10-NEXT: s_mov_b32 s5, s7
307 ; GFX10-NEXT: s_mov_b32 s6, s8
308 ; GFX10-NEXT: s_mov_b32 s7, s9
309 ; GFX10-NEXT: image_load v[0:1], v0, s[0:7] dmask:0x9 dim:SQ_RSRC_IMG_1D unorm
310 ; GFX10-NEXT: s_waitcnt vmcnt(0)
311 ; GFX10-NEXT: ; return to shader part epilog
312 ;
313 ; NOPRT-LABEL: load_1d_v2f32_xw:
314 ; NOPRT: ; %bb.0:
315 ; NOPRT-NEXT: s_mov_b32 s0, s2
316 ; NOPRT-NEXT: s_mov_b32 s1, s3
317 ; NOPRT-NEXT: s_mov_b32 s2, s4
318 ; NOPRT-NEXT: s_mov_b32 s3, s5
319 ; NOPRT-NEXT: s_mov_b32 s4, s6
320 ; NOPRT-NEXT: s_mov_b32 s5, s7
321 ; NOPRT-NEXT: s_mov_b32 s6, s8
322 ; NOPRT-NEXT: s_mov_b32 s7, s9
323 ; NOPRT-NEXT: image_load v[0:1], v0, s[0:7] dmask:0x9 dim:SQ_RSRC_IMG_1D unorm
324 ; NOPRT-NEXT: s_waitcnt vmcnt(0)
325 ; NOPRT-NEXT: ; return to shader part epilog
326 %v = call <2 x float> @llvm.amdgcn.image.load.1d.v2f32.i32(i32 9, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
327 ret <2 x float> %v
328 }
330 define amdgpu_ps <2 x float> @load_1d_v2f32_yz(<8 x i32> inreg %rsrc, i32 %s) {
331 ; GFX68-LABEL: load_1d_v2f32_yz:
332 ; GFX68: ; %bb.0:
333 ; GFX68-NEXT: s_mov_b32 s0, s2
334 ; GFX68-NEXT: s_mov_b32 s1, s3
335 ; GFX68-NEXT: s_mov_b32 s2, s4
336 ; GFX68-NEXT: s_mov_b32 s3, s5
337 ; GFX68-NEXT: s_mov_b32 s4, s6
338 ; GFX68-NEXT: s_mov_b32 s5, s7
339 ; GFX68-NEXT: s_mov_b32 s6, s8
340 ; GFX68-NEXT: s_mov_b32 s7, s9
341 ; GFX68-NEXT: image_load v[0:1], v0, s[0:7] dmask:0x6 unorm
342 ; GFX68-NEXT: s_waitcnt vmcnt(0)
343 ; GFX68-NEXT: ; return to shader part epilog
344 ;
345 ; GFX10-LABEL: load_1d_v2f32_yz:
346 ; GFX10: ; %bb.0:
347 ; GFX10-NEXT: s_mov_b32 s0, s2
348 ; GFX10-NEXT: s_mov_b32 s1, s3
349 ; GFX10-NEXT: s_mov_b32 s2, s4
350 ; GFX10-NEXT: s_mov_b32 s3, s5
351 ; GFX10-NEXT: s_mov_b32 s4, s6
352 ; GFX10-NEXT: s_mov_b32 s5, s7
353 ; GFX10-NEXT: s_mov_b32 s6, s8
354 ; GFX10-NEXT: s_mov_b32 s7, s9
355 ; GFX10-NEXT: image_load v[0:1], v0, s[0:7] dmask:0x6 dim:SQ_RSRC_IMG_1D unorm
356 ; GFX10-NEXT: s_waitcnt vmcnt(0)
357 ; GFX10-NEXT: ; return to shader part epilog
358 ;
359 ; NOPRT-LABEL: load_1d_v2f32_yz:
360 ; NOPRT: ; %bb.0:
361 ; NOPRT-NEXT: s_mov_b32 s0, s2
362 ; NOPRT-NEXT: s_mov_b32 s1, s3
363 ; NOPRT-NEXT: s_mov_b32 s2, s4
364 ; NOPRT-NEXT: s_mov_b32 s3, s5
365 ; NOPRT-NEXT: s_mov_b32 s4, s6
366 ; NOPRT-NEXT: s_mov_b32 s5, s7
367 ; NOPRT-NEXT: s_mov_b32 s6, s8
368 ; NOPRT-NEXT: s_mov_b32 s7, s9
369 ; NOPRT-NEXT: image_load v[0:1], v0, s[0:7] dmask:0x6 dim:SQ_RSRC_IMG_1D unorm
370 ; NOPRT-NEXT: s_waitcnt vmcnt(0)
371 ; NOPRT-NEXT: ; return to shader part epilog
372 %v = call <2 x float> @llvm.amdgcn.image.load.1d.v2f32.i32(i32 6, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
373 ret <2 x float> %v
374 }
376 define amdgpu_ps <3 x float> @load_1d_v3f32_xyz(<8 x i32> inreg %rsrc, i32 %s) {
377 ; GFX68-LABEL: load_1d_v3f32_xyz:
378 ; GFX68: ; %bb.0:
379 ; GFX68-NEXT: s_mov_b32 s0, s2
380 ; GFX68-NEXT: s_mov_b32 s1, s3
381 ; GFX68-NEXT: s_mov_b32 s2, s4
382 ; GFX68-NEXT: s_mov_b32 s3, s5
383 ; GFX68-NEXT: s_mov_b32 s4, s6
384 ; GFX68-NEXT: s_mov_b32 s5, s7
385 ; GFX68-NEXT: s_mov_b32 s6, s8
386 ; GFX68-NEXT: s_mov_b32 s7, s9
387 ; GFX68-NEXT: image_load v[0:2], v0, s[0:7] dmask:0x7 unorm
388 ; GFX68-NEXT: s_waitcnt vmcnt(0)
389 ; GFX68-NEXT: ; return to shader part epilog
390 ;
391 ; GFX10-LABEL: load_1d_v3f32_xyz:
392 ; GFX10: ; %bb.0:
393 ; GFX10-NEXT: s_mov_b32 s0, s2
394 ; GFX10-NEXT: s_mov_b32 s1, s3
395 ; GFX10-NEXT: s_mov_b32 s2, s4
396 ; GFX10-NEXT: s_mov_b32 s3, s5
397 ; GFX10-NEXT: s_mov_b32 s4, s6
398 ; GFX10-NEXT: s_mov_b32 s5, s7
399 ; GFX10-NEXT: s_mov_b32 s6, s8
400 ; GFX10-NEXT: s_mov_b32 s7, s9
401 ; GFX10-NEXT: image_load v[0:2], v0, s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_1D unorm
402 ; GFX10-NEXT: s_waitcnt vmcnt(0)
403 ; GFX10-NEXT: ; return to shader part epilog
404 ;
405 ; NOPRT-LABEL: load_1d_v3f32_xyz:
406 ; NOPRT: ; %bb.0:
407 ; NOPRT-NEXT: s_mov_b32 s0, s2
408 ; NOPRT-NEXT: s_mov_b32 s1, s3
409 ; NOPRT-NEXT: s_mov_b32 s2, s4
410 ; NOPRT-NEXT: s_mov_b32 s3, s5
411 ; NOPRT-NEXT: s_mov_b32 s4, s6
412 ; NOPRT-NEXT: s_mov_b32 s5, s7
413 ; NOPRT-NEXT: s_mov_b32 s6, s8
414 ; NOPRT-NEXT: s_mov_b32 s7, s9
415 ; NOPRT-NEXT: image_load v[0:2], v0, s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_1D unorm
416 ; NOPRT-NEXT: s_waitcnt vmcnt(0)
417 ; NOPRT-NEXT: ; return to shader part epilog
418 %v = call <3 x float> @llvm.amdgcn.image.load.1d.v3f32.i32(i32 7, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
419 ret <3 x float> %v
420 }
422 define amdgpu_ps <4 x float> @load_1d_v4f32_xyzw(<8 x i32> inreg %rsrc, i32 %s) {
423 ; GFX68-LABEL: load_1d_v4f32_xyzw:
424 ; GFX68: ; %bb.0:
425 ; GFX68-NEXT: s_mov_b32 s0, s2
426 ; GFX68-NEXT: s_mov_b32 s1, s3
427 ; GFX68-NEXT: s_mov_b32 s2, s4
428 ; GFX68-NEXT: s_mov_b32 s3, s5
429 ; GFX68-NEXT: s_mov_b32 s4, s6
430 ; GFX68-NEXT: s_mov_b32 s5, s7
431 ; GFX68-NEXT: s_mov_b32 s6, s8
432 ; GFX68-NEXT: s_mov_b32 s7, s9
433 ; GFX68-NEXT: image_load v[0:3], v0, s[0:7] dmask:0xf unorm
434 ; GFX68-NEXT: s_waitcnt vmcnt(0)
435 ; GFX68-NEXT: ; return to shader part epilog
436 ;
437 ; GFX10-LABEL: load_1d_v4f32_xyzw:
438 ; GFX10: ; %bb.0:
439 ; GFX10-NEXT: s_mov_b32 s0, s2
440 ; GFX10-NEXT: s_mov_b32 s1, s3
441 ; GFX10-NEXT: s_mov_b32 s2, s4
442 ; GFX10-NEXT: s_mov_b32 s3, s5
443 ; GFX10-NEXT: s_mov_b32 s4, s6
444 ; GFX10-NEXT: s_mov_b32 s5, s7
445 ; GFX10-NEXT: s_mov_b32 s6, s8
446 ; GFX10-NEXT: s_mov_b32 s7, s9
447 ; GFX10-NEXT: image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm
448 ; GFX10-NEXT: s_waitcnt vmcnt(0)
449 ; GFX10-NEXT: ; return to shader part epilog
450 ;
451 ; NOPRT-LABEL: load_1d_v4f32_xyzw:
452 ; NOPRT: ; %bb.0:
453 ; NOPRT-NEXT: s_mov_b32 s0, s2
454 ; NOPRT-NEXT: s_mov_b32 s1, s3
455 ; NOPRT-NEXT: s_mov_b32 s2, s4
456 ; NOPRT-NEXT: s_mov_b32 s3, s5
457 ; NOPRT-NEXT: s_mov_b32 s4, s6
458 ; NOPRT-NEXT: s_mov_b32 s5, s7
459 ; NOPRT-NEXT: s_mov_b32 s6, s8
460 ; NOPRT-NEXT: s_mov_b32 s7, s9
461 ; NOPRT-NEXT: image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm
462 ; NOPRT-NEXT: s_waitcnt vmcnt(0)
463 ; NOPRT-NEXT: ; return to shader part epilog
464 %v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32 15, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
465 ret <4 x float> %v
466 }
468 define amdgpu_ps float @load_1d_f32_tfe_dmask_x(<8 x i32> inreg %rsrc, i32 %s) {
469 ; GFX68-LABEL: load_1d_f32_tfe_dmask_x:
470 ; GFX68: ; %bb.0:
471 ; GFX68-NEXT: v_mov_b32_e32 v1, 0
472 ; GFX68-NEXT: s_mov_b32 s0, s2
473 ; GFX68-NEXT: s_mov_b32 s1, s3
474 ; GFX68-NEXT: s_mov_b32 s2, s4
475 ; GFX68-NEXT: s_mov_b32 s3, s5
476 ; GFX68-NEXT: s_mov_b32 s4, s6
477 ; GFX68-NEXT: s_mov_b32 s5, s7
478 ; GFX68-NEXT: s_mov_b32 s6, s8
479 ; GFX68-NEXT: s_mov_b32 s7, s9
480 ; GFX68-NEXT: v_mov_b32_e32 v2, v1
481 ; GFX68-NEXT: image_load v[1:2], v0, s[0:7] dmask:0x1 unorm tfe
482 ; GFX68-NEXT: s_waitcnt vmcnt(0)
483 ; GFX68-NEXT: v_mov_b32_e32 v0, v2
484 ; GFX68-NEXT: ; return to shader part epilog
485 ;
486 ; GFX10-LABEL: load_1d_f32_tfe_dmask_x:
487 ; GFX10: ; %bb.0:
488 ; GFX10-NEXT: v_mov_b32_e32 v1, 0
489 ; GFX10-NEXT: s_mov_b32 s0, s2
490 ; GFX10-NEXT: s_mov_b32 s1, s3
491 ; GFX10-NEXT: s_mov_b32 s2, s4
492 ; GFX10-NEXT: s_mov_b32 s3, s5
493 ; GFX10-NEXT: s_mov_b32 s4, s6
494 ; GFX10-NEXT: s_mov_b32 s5, s7
495 ; GFX10-NEXT: s_mov_b32 s6, s8
496 ; GFX10-NEXT: s_mov_b32 s7, s9
497 ; GFX10-NEXT: v_mov_b32_e32 v2, v1
498 ; GFX10-NEXT: image_load v[1:2], v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm tfe
499 ; GFX10-NEXT: s_waitcnt vmcnt(0)
500 ; GFX10-NEXT: v_mov_b32_e32 v0, v2
501 ; GFX10-NEXT: ; return to shader part epilog
502 ;
503 ; NOPRT-LABEL: load_1d_f32_tfe_dmask_x:
504 ; NOPRT: ; %bb.0:
505 ; NOPRT-NEXT: s_mov_b32 s0, s2
506 ; NOPRT-NEXT: s_mov_b32 s1, s3
507 ; NOPRT-NEXT: s_mov_b32 s2, s4
508 ; NOPRT-NEXT: s_mov_b32 s3, s5
509 ; NOPRT-NEXT: s_mov_b32 s4, s6
510 ; NOPRT-NEXT: s_mov_b32 s5, s7
511 ; NOPRT-NEXT: s_mov_b32 s6, s8
512 ; NOPRT-NEXT: s_mov_b32 s7, s9
513 ; NOPRT-NEXT: v_mov_b32_e32 v1, 0
514 ; NOPRT-NEXT: image_load v[0:1], v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm tfe
515 ; NOPRT-NEXT: s_waitcnt vmcnt(0)
516 ; NOPRT-NEXT: v_mov_b32_e32 v0, v1
517 ; NOPRT-NEXT: ; return to shader part epilog
518 %v = call { float, i32 } @llvm.amdgcn.image.load.1d.sl_f32i32s.i32(i32 1, i32 %s, <8 x i32> %rsrc, i32 1, i32 0)
519 %v.err = extractvalue { float, i32 } %v, 1
520 %vv = bitcast i32 %v.err to float
521 ret float %vv
522 }
524 define amdgpu_ps float @load_1d_v2f32_tfe_dmask_xy(<8 x i32> inreg %rsrc, i32 %s) {
525 ; GFX68-LABEL: load_1d_v2f32_tfe_dmask_xy:
526 ; GFX68: ; %bb.0:
527 ; GFX68-NEXT: v_mov_b32_e32 v1, 0
528 ; GFX68-NEXT: s_mov_b32 s0, s2
529 ; GFX68-NEXT: s_mov_b32 s1, s3
530 ; GFX68-NEXT: s_mov_b32 s2, s4
531 ; GFX68-NEXT: s_mov_b32 s3, s5
532 ; GFX68-NEXT: s_mov_b32 s4, s6
533 ; GFX68-NEXT: s_mov_b32 s5, s7
534 ; GFX68-NEXT: s_mov_b32 s6, s8
535 ; GFX68-NEXT: s_mov_b32 s7, s9
536 ; GFX68-NEXT: v_mov_b32_e32 v2, v1
537 ; GFX68-NEXT: v_mov_b32_e32 v3, v1
538 ; GFX68-NEXT: image_load v[1:3], v0, s[0:7] dmask:0x3 unorm tfe
539 ; GFX68-NEXT: s_waitcnt vmcnt(0)
540 ; GFX68-NEXT: v_mov_b32_e32 v0, v3
541 ; GFX68-NEXT: ; return to shader part epilog
542 ;
543 ; GFX10-LABEL: load_1d_v2f32_tfe_dmask_xy:
544 ; GFX10: ; %bb.0:
545 ; GFX10-NEXT: v_mov_b32_e32 v1, 0
546 ; GFX10-NEXT: s_mov_b32 s0, s2
547 ; GFX10-NEXT: s_mov_b32 s1, s3
548 ; GFX10-NEXT: s_mov_b32 s2, s4
549 ; GFX10-NEXT: s_mov_b32 s3, s5
550 ; GFX10-NEXT: s_mov_b32 s4, s6
551 ; GFX10-NEXT: s_mov_b32 s5, s7
552 ; GFX10-NEXT: s_mov_b32 s6, s8
553 ; GFX10-NEXT: s_mov_b32 s7, s9
554 ; GFX10-NEXT: v_mov_b32_e32 v2, v1
555 ; GFX10-NEXT: v_mov_b32_e32 v3, v1
556 ; GFX10-NEXT: image_load v[1:3], v0, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm tfe
557 ; GFX10-NEXT: s_waitcnt vmcnt(0)
558 ; GFX10-NEXT: v_mov_b32_e32 v0, v3
559 ; GFX10-NEXT: ; return to shader part epilog
560 ;
561 ; NOPRT-LABEL: load_1d_v2f32_tfe_dmask_xy:
562 ; NOPRT: ; %bb.0:
563 ; NOPRT-NEXT: s_mov_b32 s0, s2
564 ; NOPRT-NEXT: s_mov_b32 s1, s3
565 ; NOPRT-NEXT: s_mov_b32 s2, s4
566 ; NOPRT-NEXT: s_mov_b32 s3, s5
567 ; NOPRT-NEXT: s_mov_b32 s4, s6
568 ; NOPRT-NEXT: s_mov_b32 s5, s7
569 ; NOPRT-NEXT: s_mov_b32 s6, s8
570 ; NOPRT-NEXT: s_mov_b32 s7, s9
571 ; NOPRT-NEXT: v_mov_b32_e32 v2, 0
572 ; NOPRT-NEXT: image_load v[0:2], v0, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm tfe
573 ; NOPRT-NEXT: s_waitcnt vmcnt(0)
574 ; NOPRT-NEXT: v_mov_b32_e32 v0, v2
575 ; NOPRT-NEXT: ; return to shader part epilog
576 %v = call { <2 x float>, i32 } @llvm.amdgcn.image.load.1d.sl_v2f32i32s.i32(i32 3, i32 %s, <8 x i32> %rsrc, i32 1, i32 0)
577 %v.err = extractvalue { <2 x float>, i32 } %v, 1
578 %vv = bitcast i32 %v.err to float
579 ret float %vv
580 }
582 define amdgpu_ps float @load_1d_v3f32_tfe_dmask_xyz(<8 x i32> inreg %rsrc, i32 %s) {
583 ; GFX68-LABEL: load_1d_v3f32_tfe_dmask_xyz:
584 ; GFX68: ; %bb.0:
585 ; GFX68-NEXT: v_mov_b32_e32 v1, 0
586 ; GFX68-NEXT: s_mov_b32 s0, s2
587 ; GFX68-NEXT: s_mov_b32 s1, s3
588 ; GFX68-NEXT: s_mov_b32 s2, s4
589 ; GFX68-NEXT: s_mov_b32 s3, s5
590 ; GFX68-NEXT: s_mov_b32 s4, s6
591 ; GFX68-NEXT: s_mov_b32 s5, s7
592 ; GFX68-NEXT: s_mov_b32 s6, s8
593 ; GFX68-NEXT: s_mov_b32 s7, s9
594 ; GFX68-NEXT: v_mov_b32_e32 v2, v1
595 ; GFX68-NEXT: v_mov_b32_e32 v3, v1
596 ; GFX68-NEXT: v_mov_b32_e32 v4, v1
597 ; GFX68-NEXT: image_load v[1:4], v0, s[0:7] dmask:0x7 unorm tfe
598 ; GFX68-NEXT: s_waitcnt vmcnt(0)
599 ; GFX68-NEXT: v_mov_b32_e32 v0, v4
600 ; GFX68-NEXT: ; return to shader part epilog
601 ;
602 ; GFX10-LABEL: load_1d_v3f32_tfe_dmask_xyz:
603 ; GFX10: ; %bb.0:
604 ; GFX10-NEXT: v_mov_b32_e32 v1, 0
605 ; GFX10-NEXT: s_mov_b32 s0, s2
606 ; GFX10-NEXT: s_mov_b32 s1, s3
607 ; GFX10-NEXT: s_mov_b32 s2, s4
608 ; GFX10-NEXT: s_mov_b32 s3, s5
609 ; GFX10-NEXT: s_mov_b32 s4, s6
610 ; GFX10-NEXT: s_mov_b32 s5, s7
611 ; GFX10-NEXT: s_mov_b32 s6, s8
612 ; GFX10-NEXT: s_mov_b32 s7, s9
613 ; GFX10-NEXT: v_mov_b32_e32 v2, v1
614 ; GFX10-NEXT: v_mov_b32_e32 v3, v1
615 ; GFX10-NEXT: v_mov_b32_e32 v4, v1
616 ; GFX10-NEXT: image_load v[1:4], v0, s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_1D unorm tfe
617 ; GFX10-NEXT: s_waitcnt vmcnt(0)
618 ; GFX10-NEXT: v_mov_b32_e32 v0, v4
619 ; GFX10-NEXT: ; return to shader part epilog
620 ;
621 ; NOPRT-LABEL: load_1d_v3f32_tfe_dmask_xyz:
622 ; NOPRT: ; %bb.0:
623 ; NOPRT-NEXT: s_mov_b32 s0, s2
624 ; NOPRT-NEXT: s_mov_b32 s1, s3
625 ; NOPRT-NEXT: s_mov_b32 s2, s4
626 ; NOPRT-NEXT: s_mov_b32 s3, s5
627 ; NOPRT-NEXT: s_mov_b32 s4, s6
628 ; NOPRT-NEXT: s_mov_b32 s5, s7
629 ; NOPRT-NEXT: s_mov_b32 s6, s8
630 ; NOPRT-NEXT: s_mov_b32 s7, s9
631 ; NOPRT-NEXT: v_mov_b32_e32 v3, 0
632 ; NOPRT-NEXT: image_load v[0:3], v0, s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_1D unorm tfe
633 ; NOPRT-NEXT: s_waitcnt vmcnt(0)
634 ; NOPRT-NEXT: v_mov_b32_e32 v0, v3
635 ; NOPRT-NEXT: ; return to shader part epilog
636 %v = call { <3 x float>, i32 } @llvm.amdgcn.image.load.1d.sl_v3f32i32s.i32(i32 7, i32 %s, <8 x i32> %rsrc, i32 1, i32 0)
637 %v.err = extractvalue { <3 x float>, i32 } %v, 1
638 %vv = bitcast i32 %v.err to float
639 ret float %vv
640 }
642 define amdgpu_ps float @load_1d_v4f32_tfe_dmask_xyzw(<8 x i32> inreg %rsrc, i32 %s) {
643 ; GFX68-LABEL: load_1d_v4f32_tfe_dmask_xyzw:
644 ; GFX68: ; %bb.0:
645 ; GFX68-NEXT: v_mov_b32_e32 v1, 0
646 ; GFX68-NEXT: s_mov_b32 s0, s2
647 ; GFX68-NEXT: s_mov_b32 s1, s3
648 ; GFX68-NEXT: s_mov_b32 s2, s4
649 ; GFX68-NEXT: s_mov_b32 s3, s5
650 ; GFX68-NEXT: s_mov_b32 s4, s6
651 ; GFX68-NEXT: s_mov_b32 s5, s7
652 ; GFX68-NEXT: s_mov_b32 s6, s8
653 ; GFX68-NEXT: s_mov_b32 s7, s9
654 ; GFX68-NEXT: v_mov_b32_e32 v2, v1
655 ; GFX68-NEXT: image_load v[1:2], v0, s[0:7] dmask:0x10 unorm tfe
656 ; GFX68-NEXT: s_waitcnt vmcnt(0)
657 ; GFX68-NEXT: v_mov_b32_e32 v0, v2
658 ; GFX68-NEXT: ; return to shader part epilog
659 ;
660 ; GFX10-LABEL: load_1d_v4f32_tfe_dmask_xyzw:
661 ; GFX10: ; %bb.0:
662 ; GFX10-NEXT: v_mov_b32_e32 v1, 0
663 ; GFX10-NEXT: s_mov_b32 s0, s2
664 ; GFX10-NEXT: s_mov_b32 s1, s3
665 ; GFX10-NEXT: s_mov_b32 s2, s4
666 ; GFX10-NEXT: s_mov_b32 s3, s5
667 ; GFX10-NEXT: s_mov_b32 s4, s6
668 ; GFX10-NEXT: s_mov_b32 s5, s7
669 ; GFX10-NEXT: s_mov_b32 s6, s8
670 ; GFX10-NEXT: s_mov_b32 s7, s9
671 ; GFX10-NEXT: v_mov_b32_e32 v2, v1
672 ; GFX10-NEXT: image_load v[1:2], v0, s[0:7] dmask:0x10 dim:SQ_RSRC_IMG_1D unorm tfe
673 ; GFX10-NEXT: s_waitcnt vmcnt(0)
674 ; GFX10-NEXT: v_mov_b32_e32 v0, v2
675 ; GFX10-NEXT: ; return to shader part epilog
676 ;
677 ; NOPRT-LABEL: load_1d_v4f32_tfe_dmask_xyzw:
678 ; NOPRT: ; %bb.0:
679 ; NOPRT-NEXT: s_mov_b32 s0, s2
680 ; NOPRT-NEXT: s_mov_b32 s1, s3
681 ; NOPRT-NEXT: s_mov_b32 s2, s4
682 ; NOPRT-NEXT: s_mov_b32 s3, s5
683 ; NOPRT-NEXT: s_mov_b32 s4, s6
684 ; NOPRT-NEXT: s_mov_b32 s5, s7
685 ; NOPRT-NEXT: s_mov_b32 s6, s8
686 ; NOPRT-NEXT: s_mov_b32 s7, s9
687 ; NOPRT-NEXT: v_mov_b32_e32 v1, 0
688 ; NOPRT-NEXT: image_load v[0:1], v0, s[0:7] dmask:0x10 dim:SQ_RSRC_IMG_1D unorm tfe
689 ; NOPRT-NEXT: s_waitcnt vmcnt(0)
690 ; NOPRT-NEXT: v_mov_b32_e32 v0, v1
691 ; NOPRT-NEXT: ; return to shader part epilog
692 %v = call { <4 x float>, i32 } @llvm.amdgcn.image.load.1d.sl_v4f32i32s.i32(i32 16, i32 %s, <8 x i32> %rsrc, i32 1, i32 0)
693 %v.err = extractvalue { <4 x float>, i32 } %v, 1
694 %vv = bitcast i32 %v.err to float
695 ret float %vv
696 }
698 define amdgpu_ps float @load_1d_f32_tfe_dmask_0(<8 x i32> inreg %rsrc, i32 %s) {
699 ; GFX68-LABEL: load_1d_f32_tfe_dmask_0:
700 ; GFX68: ; %bb.0:
701 ; GFX68-NEXT: v_mov_b32_e32 v1, 0
702 ; GFX68-NEXT: s_mov_b32 s0, s2
703 ; GFX68-NEXT: s_mov_b32 s1, s3
704 ; GFX68-NEXT: s_mov_b32 s2, s4
705 ; GFX68-NEXT: s_mov_b32 s3, s5
706 ; GFX68-NEXT: s_mov_b32 s4, s6
707 ; GFX68-NEXT: s_mov_b32 s5, s7
708 ; GFX68-NEXT: s_mov_b32 s6, s8
709 ; GFX68-NEXT: s_mov_b32 s7, s9
710 ; GFX68-NEXT: v_mov_b32_e32 v2, v1
711 ; GFX68-NEXT: image_load v[1:2], v0, s[0:7] dmask:0x1 unorm tfe
712 ; GFX68-NEXT: s_waitcnt vmcnt(0)
713 ; GFX68-NEXT: v_mov_b32_e32 v0, v2
714 ; GFX68-NEXT: ; return to shader part epilog
715 ;
716 ; GFX10-LABEL: load_1d_f32_tfe_dmask_0:
717 ; GFX10: ; %bb.0:
718 ; GFX10-NEXT: v_mov_b32_e32 v1, 0
719 ; GFX10-NEXT: s_mov_b32 s0, s2
720 ; GFX10-NEXT: s_mov_b32 s1, s3
721 ; GFX10-NEXT: s_mov_b32 s2, s4
722 ; GFX10-NEXT: s_mov_b32 s3, s5
723 ; GFX10-NEXT: s_mov_b32 s4, s6
724 ; GFX10-NEXT: s_mov_b32 s5, s7
725 ; GFX10-NEXT: s_mov_b32 s6, s8
726 ; GFX10-NEXT: s_mov_b32 s7, s9
727 ; GFX10-NEXT: v_mov_b32_e32 v2, v1
728 ; GFX10-NEXT: image_load v[1:2], v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm tfe
729 ; GFX10-NEXT: s_waitcnt vmcnt(0)
730 ; GFX10-NEXT: v_mov_b32_e32 v0, v2
731 ; GFX10-NEXT: ; return to shader part epilog
732 ;
733 ; NOPRT-LABEL: load_1d_f32_tfe_dmask_0:
734 ; NOPRT: ; %bb.0:
735 ; NOPRT-NEXT: s_mov_b32 s0, s2
736 ; NOPRT-NEXT: s_mov_b32 s1, s3
737 ; NOPRT-NEXT: s_mov_b32 s2, s4
738 ; NOPRT-NEXT: s_mov_b32 s3, s5
739 ; NOPRT-NEXT: s_mov_b32 s4, s6
740 ; NOPRT-NEXT: s_mov_b32 s5, s7
741 ; NOPRT-NEXT: s_mov_b32 s6, s8
742 ; NOPRT-NEXT: s_mov_b32 s7, s9
743 ; NOPRT-NEXT: v_mov_b32_e32 v1, 0
744 ; NOPRT-NEXT: image_load v[0:1], v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm tfe
745 ; NOPRT-NEXT: s_waitcnt vmcnt(0)
746 ; NOPRT-NEXT: v_mov_b32_e32 v0, v1
747 ; NOPRT-NEXT: ; return to shader part epilog
748 %v = call { float, i32 } @llvm.amdgcn.image.load.1d.sl_f32i32s.i32(i32 0, i32 %s, <8 x i32> %rsrc, i32 1, i32 0)
749 %v.err = extractvalue { float, i32 } %v, 1
750 %vv = bitcast i32 %v.err to float
751 ret float %vv
752 }
754 declare float @llvm.amdgcn.image.load.1d.f32.i32(i32 immarg, i32, <8 x i32>, i32 immarg, i32 immarg) #0
755 declare <2 x float> @llvm.amdgcn.image.load.1d.v2f32.i32(i32 immarg, i32, <8 x i32>, i32 immarg, i32 immarg) #0
756 declare <3 x float> @llvm.amdgcn.image.load.1d.v3f32.i32(i32 immarg, i32, <8 x i32>, i32 immarg, i32 immarg) #0
757 declare <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32 immarg, i32, <8 x i32>, i32 immarg, i32 immarg) #0
759 declare { float, i32 } @llvm.amdgcn.image.load.1d.sl_f32i32s.i32(i32 immarg, i32, <8 x i32>, i32 immarg, i32 immarg) #0
760 declare { <2 x float>, i32 } @llvm.amdgcn.image.load.1d.sl_v2f32i32s.i32(i32 immarg, i32, <8 x i32>, i32 immarg, i32 immarg) #0
761 declare { <3 x float>, i32 } @llvm.amdgcn.image.load.1d.sl_v3f32i32s.i32(i32 immarg, i32, <8 x i32>, i32 immarg, i32 immarg) #0
762 declare { <4 x float>, i32 } @llvm.amdgcn.image.load.1d.sl_v4f32i32s.i32(i32 immarg, i32, <8 x i32>, i32 immarg, i32 immarg) #0
764 attributes #0 = { nounwind readonly }