| blob | d59d3ac732a275a2e1107cac2c9f5273f1b1f301 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -global-isel -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GFX8 %s
3 ; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefix=GFX10 %s
4 ; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefix=GFX11 %s
6 ; FIXME: Merge with DAG test
8 define amdgpu_kernel void @dpp_test(ptr addrspace(1) %out, i32 %in) {
9 ; GFX8-LABEL: dpp_test:
10 ; GFX8: ; %bb.0:
11 ; GFX8-NEXT: s_load_dword s2, s[0:1], 0x2c
12 ; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
13 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
14 ; GFX8-NEXT: v_mov_b32_e32 v2, s2
15 ; GFX8-NEXT: v_mov_b32_e32 v0, s0
16 ; GFX8-NEXT: s_nop 0
17 ; GFX8-NEXT: v_mov_b32_dpp v2, v2 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:1
18 ; GFX8-NEXT: v_mov_b32_e32 v1, s1
19 ; GFX8-NEXT: flat_store_dword v[0:1], v2
20 ; GFX8-NEXT: s_endpgm
21 ;
22 ; GFX10-LABEL: dpp_test:
23 ; GFX10: ; %bb.0:
24 ; GFX10-NEXT: s_clause 0x1 ; encoding: [0x01,0x00,0xa1,0xbf]
25 ; GFX10-NEXT: s_load_dword s4, s[0:1], 0x2c ; encoding: [0x00,0x01,0x00,0xf4,0x2c,0x00,0x00,0xfa]
26 ; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 ; encoding: [0x80,0x00,0x04,0xf4,0x24,0x00,0x00,0xfa]
27 ; GFX10-NEXT: v_mov_b32_e32 v1, 0 ; encoding: [0x80,0x02,0x02,0x7e]
28 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0xc0,0x8c,0xbf]
29 ; GFX10-NEXT: v_mov_b32_e32 v0, s4 ; encoding: [0x04,0x02,0x00,0x7e]
30 ; GFX10-NEXT: v_mov_b32_dpp v0, v0 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x01,0x08,0x11]
31 ; GFX10-NEXT: global_store_dword v1, v0, s[2:3] ; encoding: [0x00,0x80,0x70,0xdc,0x01,0x00,0x02,0x00]
32 ; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
33 ;
34 ; GFX11-LABEL: dpp_test:
35 ; GFX11: ; %bb.0:
36 ; GFX11-NEXT: s_clause 0x1 ; encoding: [0x01,0x00,0x85,0xbf]
37 ; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c ; encoding: [0x80,0x00,0x00,0xf4,0x2c,0x00,0x00,0xf8]
38 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 ; encoding: [0x00,0x00,0x04,0xf4,0x24,0x00,0x00,0xf8]
39 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x07,0xfc,0x89,0xbf]
40 ; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2 ; encoding: [0x80,0x00,0x10,0xca,0x02,0x00,0x00,0x01]
41 ; GFX11-NEXT: v_mov_b32_dpp v0, v0 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:1 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x01,0x08,0x11]
42 ; GFX11-NEXT: global_store_b32 v1, v0, s[0:1] ; encoding: [0x00,0x00,0x6a,0xdc,0x01,0x00,0x00,0x00]
43 ; GFX11-NEXT: s_nop 0 ; encoding: [0x00,0x00,0x80,0xbf]
44 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; encoding: [0x03,0x00,0xb6,0xbf]
45 ; GFX11-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
46 %tmp0 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %in, i32 1, i32 1, i32 1, i1 true) #0
47 store i32 %tmp0, ptr addrspace(1) %out
48 ret void
49 }
50 define amdgpu_kernel void @mov_dpp64_test(ptr addrspace(1) %out, i64 %in1) {
51 ; GFX8-LABEL: mov_dpp64_test:
52 ; GFX8: ; %bb.0:
53 ; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
54 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
55 ; GFX8-NEXT: v_mov_b32_e32 v0, s2
56 ; GFX8-NEXT: v_mov_b32_e32 v1, s3
57 ; GFX8-NEXT: v_mov_b32_e32 v3, s1
58 ; GFX8-NEXT: v_mov_b32_dpp v0, v0 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
59 ; GFX8-NEXT: v_mov_b32_dpp v1, v1 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
60 ; GFX8-NEXT: v_mov_b32_e32 v2, s0
61 ; GFX8-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
62 ; GFX8-NEXT: s_endpgm
63 ;
64 ; GFX10-LABEL: mov_dpp64_test:
65 ; GFX10: ; %bb.0:
66 ; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; encoding: [0x00,0x00,0x08,0xf4,0x24,0x00,0x00,0xfa]
67 ; GFX10-NEXT: v_mov_b32_e32 v2, 0 ; encoding: [0x80,0x02,0x04,0x7e]
68 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0xc0,0x8c,0xbf]
69 ; GFX10-NEXT: v_mov_b32_e32 v0, s2 ; encoding: [0x02,0x02,0x00,0x7e]
70 ; GFX10-NEXT: v_mov_b32_e32 v1, s3 ; encoding: [0x03,0x02,0x02,0x7e]
71 ; GFX10-NEXT: v_mov_b32_dpp v0, v0 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x01,0x00,0x11]
72 ; GFX10-NEXT: v_mov_b32_dpp v1, v1 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 ; encoding: [0xfa,0x02,0x02,0x7e,0x01,0x01,0x00,0x11]
73 ; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] ; encoding: [0x00,0x80,0x74,0xdc,0x02,0x00,0x00,0x00]
74 ; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
75 ;
76 ; GFX11-LABEL: mov_dpp64_test:
77 ; GFX11: ; %bb.0:
78 ; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24 ; encoding: [0x00,0x00,0x08,0xf4,0x24,0x00,0x00,0xf8]
79 ; GFX11-NEXT: v_mov_b32_e32 v2, 0 ; encoding: [0x80,0x02,0x04,0x7e]
80 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x07,0xfc,0x89,0xbf]
81 ; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3 ; encoding: [0x02,0x00,0x10,0xca,0x03,0x00,0x00,0x00]
82 ; GFX11-NEXT: v_mov_b32_dpp v0, v0 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x01,0x00,0x11]
83 ; GFX11-NEXT: v_mov_b32_dpp v1, v1 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 ; encoding: [0xfa,0x02,0x02,0x7e,0x01,0x01,0x00,0x11]
84 ; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] ; encoding: [0x00,0x00,0x6e,0xdc,0x02,0x00,0x00,0x00]
85 ; GFX11-NEXT: s_nop 0 ; encoding: [0x00,0x00,0x80,0xbf]
86 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; encoding: [0x03,0x00,0xb6,0xbf]
87 ; GFX11-NEXT: s_endpgm ; encoding: [0x00,0x00,0xb0,0xbf]
88 %tmp0 = call i64 @llvm.amdgcn.mov.dpp.i64(i64 %in1, i32 1, i32 1, i32 1, i1 false) #0
89 store i64 %tmp0, ptr addrspace(1) %out
90 ret void
91 }
93 declare i32 @llvm.amdgcn.mov.dpp.i32(i32, i32 immarg, i32 immarg, i32 immarg, i1 immarg) #0
94 declare i64 @llvm.amdgcn.mov.dpp.i64(i64, i32 immarg, i32 immarg, i32 immarg, i1 immarg) #0
96 attributes #0 = { convergent nounwind readnone }