| blob | 34c5a582c1c64aad88775ca84515a25fdfe9c1bb |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -global-isel -march=amdgcn -mcpu=tonga -amdgpu-dpp-combine=false -verify-machineinstrs < %s | FileCheck -check-prefix=GFX8 %s
3 ; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1010 -amdgpu-dpp-combine=false -verify-machineinstrs < %s | FileCheck -check-prefix=GFX10 %s
4 ; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -amdgpu-dpp-combine=false -verify-machineinstrs < %s | FileCheck -check-prefix=GFX11 %s
6 define amdgpu_kernel void @dpp_test(ptr addrspace(1) %out, i32 %in1, i32 %in2) {
7 ; GFX8-LABEL: dpp_test:
8 ; GFX8: ; %bb.0:
9 ; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
10 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
11 ; GFX8-NEXT: v_mov_b32_e32 v2, s2
12 ; GFX8-NEXT: v_mov_b32_e32 v0, s3
13 ; GFX8-NEXT: s_nop 1
14 ; GFX8-NEXT: v_mov_b32_dpp v2, v0 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
15 ; GFX8-NEXT: v_mov_b32_e32 v0, s0
16 ; GFX8-NEXT: v_mov_b32_e32 v1, s1
17 ; GFX8-NEXT: flat_store_dword v[0:1], v2
18 ; GFX8-NEXT: s_endpgm
19 ;
20 ; GFX10-LABEL: dpp_test:
21 ; GFX10: ; %bb.0:
22 ; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
23 ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
24 ; GFX10-NEXT: v_mov_b32_e32 v0, s2
25 ; GFX10-NEXT: v_mov_b32_e32 v1, s3
26 ; GFX10-NEXT: v_mov_b32_dpp v0, v1 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
27 ; GFX10-NEXT: v_mov_b32_e32 v1, 0
28 ; GFX10-NEXT: global_store_dword v1, v0, s[0:1]
29 ; GFX10-NEXT: s_endpgm
30 ;
31 ; GFX11-LABEL: dpp_test:
32 ; GFX11: ; %bb.0:
33 ; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
34 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
35 ; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
36 ; GFX11-NEXT: v_mov_b32_dpp v0, v1 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
37 ; GFX11-NEXT: v_mov_b32_e32 v1, 0
38 ; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
39 ; GFX11-NEXT: s_nop 0
40 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
41 ; GFX11-NEXT: s_endpgm
42 %tmp0 = call i32 @llvm.amdgcn.update.dpp.i32(i32 %in1, i32 %in2, i32 1, i32 1, i32 1, i1 false)
43 store i32 %tmp0, ptr addrspace(1) %out
44 ret void
45 }
46 define amdgpu_kernel void @update_dpp64_test(ptr addrspace(1) %arg, i64 %in1, i64 %in2) {
47 ; GFX8-LABEL: update_dpp64_test:
48 ; GFX8: ; %bb.0:
49 ; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
50 ; GFX8-NEXT: v_lshlrev_b32_e32 v2, 3, v0
51 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
52 ; GFX8-NEXT: v_mov_b32_e32 v0, s0
53 ; GFX8-NEXT: v_mov_b32_e32 v1, s1
54 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2
55 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
56 ; GFX8-NEXT: flat_load_dwordx2 v[2:3], v[0:1]
57 ; GFX8-NEXT: v_mov_b32_e32 v5, s3
58 ; GFX8-NEXT: v_mov_b32_e32 v4, s2
59 ; GFX8-NEXT: s_waitcnt vmcnt(0)
60 ; GFX8-NEXT: v_mov_b32_dpp v5, v3 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
61 ; GFX8-NEXT: v_mov_b32_dpp v4, v2 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
62 ; GFX8-NEXT: flat_store_dwordx2 v[0:1], v[4:5]
63 ; GFX8-NEXT: s_endpgm
64 ;
65 ; GFX10-LABEL: update_dpp64_test:
66 ; GFX10: ; %bb.0:
67 ; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
68 ; GFX10-NEXT: v_lshlrev_b32_e32 v4, 3, v0
69 ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
70 ; GFX10-NEXT: global_load_dwordx2 v[0:1], v4, s[0:1]
71 ; GFX10-NEXT: v_mov_b32_e32 v2, s2
72 ; GFX10-NEXT: v_mov_b32_e32 v3, s3
73 ; GFX10-NEXT: s_waitcnt vmcnt(0)
74 ; GFX10-NEXT: v_mov_b32_dpp v2, v0 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
75 ; GFX10-NEXT: v_mov_b32_dpp v3, v1 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
76 ; GFX10-NEXT: global_store_dwordx2 v4, v[2:3], s[0:1]
77 ; GFX10-NEXT: s_endpgm
78 ;
79 ; GFX11-LABEL: update_dpp64_test:
80 ; GFX11: ; %bb.0:
81 ; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
82 ; GFX11-NEXT: v_lshlrev_b32_e32 v4, 3, v0
83 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
84 ; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
85 ; GFX11-NEXT: global_load_b64 v[0:1], v4, s[0:1]
86 ; GFX11-NEXT: s_waitcnt vmcnt(0)
87 ; GFX11-NEXT: v_mov_b32_dpp v2, v0 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
88 ; GFX11-NEXT: v_mov_b32_dpp v3, v1 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
89 ; GFX11-NEXT: global_store_b64 v4, v[2:3], s[0:1]
90 ; GFX11-NEXT: s_nop 0
91 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
92 ; GFX11-NEXT: s_endpgm
93 %id = tail call i32 @llvm.amdgcn.workitem.id.x()
94 %gep = getelementptr inbounds i64, ptr addrspace(1) %arg, i32 %id
95 %load = load i64, ptr addrspace(1) %gep
96 %tmp0 = call i64 @llvm.amdgcn.update.dpp.i64(i64 %in1, i64 %load, i32 1, i32 1, i32 1, i1 false) #1
97 store i64 %tmp0, ptr addrspace(1) %gep
98 ret void
99 }
101 declare i32 @llvm.amdgcn.workitem.id.x() #0
102 declare i32 @llvm.amdgcn.update.dpp.i32(i32, i32, i32 immarg, i32 immarg, i32 immarg, i1 immarg) #1
103 declare i64 @llvm.amdgcn.update.dpp.i64(i64, i64, i32 immarg, i32 immarg, i32 immarg, i1 immarg) #1
105 attributes #0 = { nounwind readnone speculatable }
106 attributes #1 = { convergent nounwind readnone }