1 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s
2 ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN %s
4 ; FIXME: Check something here. Currently it seems fabs + fneg aren't
5 ; into 2 modifiers, although theoretically that should work.
7 ; GCN-LABEL: {{^}}fneg_fabs_fadd_f64:
8 ; GCN: v_add_f64 {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, -|v{{\[[0-9]+:[0-9]+\]}}|
9 define amdgpu_kernel void @fneg_fabs_fadd_f64(ptr addrspace(1) %out, double %x, double %y) {
10 %fabs = call double @llvm.fabs.f64(double %x)
11 %fsub = fsub double -0.000000e+00, %fabs
12 %fadd = fadd double %y, %fsub
13 store double %fadd, ptr addrspace(1) %out, align 8
17 define amdgpu_kernel void @v_fneg_fabs_fadd_f64(ptr addrspace(1) %out, ptr addrspace(1) %xptr, ptr addrspace(1) %yptr) {
18 %x = load double, ptr addrspace(1) %xptr, align 8
19 %y = load double, ptr addrspace(1) %xptr, align 8
20 %fabs = call double @llvm.fabs.f64(double %x)
21 %fsub = fsub double -0.000000e+00, %fabs
22 %fadd = fadd double %y, %fsub
23 store double %fadd, ptr addrspace(1) %out, align 8
27 ; GCN-LABEL: {{^}}fneg_fabs_fmul_f64:
28 ; GCN: v_mul_f64 {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, -|v{{\[[0-9]+:[0-9]+\]}}|
29 define amdgpu_kernel void @fneg_fabs_fmul_f64(ptr addrspace(1) %out, double %x, double %y) {
30 %fabs = call double @llvm.fabs.f64(double %x)
31 %fsub = fsub double -0.000000e+00, %fabs
32 %fmul = fmul double %y, %fsub
33 store double %fmul, ptr addrspace(1) %out, align 8
37 ; GCN-LABEL: {{^}}fneg_fabs_free_f64:
38 define amdgpu_kernel void @fneg_fabs_free_f64(ptr addrspace(1) %out, i64 %in) {
39 %bc = bitcast i64 %in to double
40 %fabs = call double @llvm.fabs.f64(double %bc)
41 %fsub = fsub double -0.000000e+00, %fabs
42 store double %fsub, ptr addrspace(1) %out
46 ; GCN-LABEL: {{^}}fneg_fabs_fn_free_f64:
48 ; VI: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80000000
49 define amdgpu_kernel void @fneg_fabs_fn_free_f64(ptr addrspace(1) %out, i64 %in) {
50 %bc = bitcast i64 %in to double
51 %fabs = call double @fabs(double %bc)
52 %fsub = fsub double -0.000000e+00, %fabs
53 store double %fsub, ptr addrspace(1) %out
57 ; GCN-LABEL: {{^}}fneg_fabs_f64:
58 ; SI-DAG: s_load_dwordx2 s[[[LO_X:[0-9]+]]:[[HI_X:[0-9]+]]], s[{{[0-9]+:[0-9]+}}], 0x13
59 ; VI-DAG: s_load_dwordx2 s[[[LO_X:[0-9]+]]:[[HI_X:[0-9]+]]], s[{{[0-9]+:[0-9]+}}], 0x4c
60 ; GCN-DAG: s_bitset1_b32 s[[HI_X]], 31
61 ; GCN-DAG: v_mov_b32_e32 v[[LO_V:[0-9]+]], s[[LO_X]]
62 ; GCN-DAG: v_mov_b32_e32 v[[HI_V:[0-9]+]], s[[HI_X]]
63 ; GCN: buffer_store_dwordx2 v[[[LO_V]]:[[HI_V]]]
64 define amdgpu_kernel void @fneg_fabs_f64(ptr addrspace(1) %out, [8 x i32], double %in) {
65 %fabs = call double @llvm.fabs.f64(double %in)
66 %fsub = fsub double -0.000000e+00, %fabs
67 store double %fsub, ptr addrspace(1) %out, align 8
71 ; GCN-LABEL: {{^}}fneg_fabs_v2f64:
73 ; GCN: s_bitset1_b32 s{{[0-9]+}}, 31
74 ; GCN: s_bitset1_b32 s{{[0-9]+}}, 31
75 define amdgpu_kernel void @fneg_fabs_v2f64(ptr addrspace(1) %out, <2 x double> %in) {
76 %fabs = call <2 x double> @llvm.fabs.v2f64(<2 x double> %in)
77 %fsub = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %fabs
78 store <2 x double> %fsub, ptr addrspace(1) %out
82 ; GCN-LABEL: {{^}}fneg_fabs_v4f64:
84 ; GCN: s_bitset1_b32 s{{[0-9]+}}, 31
85 ; GCN: s_bitset1_b32 s{{[0-9]+}}, 31
86 ; GCN: s_bitset1_b32 s{{[0-9]+}}, 31
87 ; GCN: s_bitset1_b32 s{{[0-9]+}}, 31
88 define amdgpu_kernel void @fneg_fabs_v4f64(ptr addrspace(1) %out, <4 x double> %in) {
89 %fabs = call <4 x double> @llvm.fabs.v4f64(<4 x double> %in)
90 %fsub = fsub <4 x double> <double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00>, %fabs
91 store <4 x double> %fsub, ptr addrspace(1) %out
95 declare double @fabs(double) readnone
96 declare double @llvm.fabs.f64(double) readnone
97 declare <2 x double> @llvm.fabs.v2f64(<2 x double>) readnone
98 declare <4 x double> @llvm.fabs.v4f64(<4 x double>) readnone