1 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefixes=GCN,SI,SICIVI,FUNC %s
2 ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-enable-ds128 -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefixes=GCN,SICIVI,GFX89,FUNC %s
3 ; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-enable-ds128 -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefixes=GCN,GFX9,GFX89,FUNC %s
4 ; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=EG -check-prefix=FUNC %s
6 ; Testing for ds_read/write_b128
7 ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=+enable-ds128 < %s | FileCheck -allow-deprecated-dag-overlap -check-prefixes=CIVI,FUNC %s
8 ; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=+enable-ds128 < %s | FileCheck -allow-deprecated-dag-overlap -check-prefixes=CIVI,FUNC %s
10 ; FUNC-LABEL: {{^}}local_load_i16:
12 ; SICIVI: s_mov_b32 m0
14 ; GCN: ds_read_u16 v{{[0-9]+}}
16 ; EG: MOV {{[* ]*}}[[FROM:T[0-9]+\.[XYZW]]], KC0[2].Z
17 ; EG: LDS_USHORT_READ_RET {{.*}} [[FROM]]
18 ; EG-DAG: MOV {{[* ]*}}[[DATA:T[0-9]+\.[XYZW]]], OQAP
19 ; EG-DAG: MOV {{[* ]*}}[[TO:T[0-9]+\.[XYZW]]], KC0[2].Y
20 ; EG: LDS_SHORT_WRITE {{\*?}} [[TO]], [[DATA]]
21 define amdgpu_kernel void @local_load_i16(ptr addrspace(3) %out, ptr addrspace(3) %in) {
23 %ld = load i16, ptr addrspace(3) %in
24 store i16 %ld, ptr addrspace(3) %out
28 ; FUNC-LABEL: {{^}}local_load_v2i16:
30 ; SICIVI: s_mov_b32 m0
34 ; EG: MOV {{[* ]*}}[[FROM:T[0-9]+\.[XYZW]]], KC0[2].Z
35 ; EG: LDS_READ_RET {{.*}} [[FROM]]
36 ; EG-DAG: MOV {{[* ]*}}[[DATA:T[0-9]+\.[XYZW]]], OQAP
37 ; EG-DAG: MOV {{[* ]*}}[[TO:T[0-9]+\.[XYZW]]], KC0[2].Y
38 ; EG: LDS_WRITE {{\*?}} [[TO]], [[DATA]]
39 define amdgpu_kernel void @local_load_v2i16(ptr addrspace(3) %out, ptr addrspace(3) %in) {
41 %ld = load <2 x i16>, ptr addrspace(3) %in
42 store <2 x i16> %ld, ptr addrspace(3) %out
46 ; FUNC-LABEL: {{^}}local_load_v3i16:
48 ; SICIVI: s_mov_b32 m0
51 ; GCN-DAG: ds_write_b32
52 ; GCN-DAG: ds_write_b16
54 ; EG-DAG: LDS_USHORT_READ_RET
55 ; EG-DAG: LDS_USHORT_READ_RET
56 define amdgpu_kernel void @local_load_v3i16(ptr addrspace(3) %out, ptr addrspace(3) %in) {
58 %ld = load <3 x i16>, ptr addrspace(3) %in
59 store <3 x i16> %ld, ptr addrspace(3) %out
63 ; FUNC-LABEL: {{^}}local_load_v4i16:
65 ; SICIVI: s_mov_b32 m0
71 define amdgpu_kernel void @local_load_v4i16(ptr addrspace(3) %out, ptr addrspace(3) %in) {
73 %ld = load <4 x i16>, ptr addrspace(3) %in
74 store <4 x i16> %ld, ptr addrspace(3) %out
78 ; FUNC-LABEL: {{^}}local_load_v8i16:
80 ; SICIVI: s_mov_b32 m0
82 ; GCN: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset1:1{{$}}
88 define amdgpu_kernel void @local_load_v8i16(ptr addrspace(3) %out, ptr addrspace(3) %in) {
90 %ld = load <8 x i16>, ptr addrspace(3) %in
91 store <8 x i16> %ld, ptr addrspace(3) %out
95 ; FUNC-LABEL: {{^}}local_load_v16i16:
97 ; SICIVI: s_mov_b32 m0
99 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:2 offset1:3{{$}}
100 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset1:1{{$}}
112 define amdgpu_kernel void @local_load_v16i16(ptr addrspace(3) %out, ptr addrspace(3) %in) {
114 %ld = load <16 x i16>, ptr addrspace(3) %in
115 store <16 x i16> %ld, ptr addrspace(3) %out
119 ; FUNC-LABEL: {{^}}local_zextload_i16_to_i32:
121 ; SICIVI: s_mov_b32 m0
126 ; EG: MOV {{[* ]*}}[[FROM:T[0-9]+\.[XYZW]]], KC0[2].Z
127 ; EG: LDS_USHORT_READ_RET {{.*}} [[FROM]]
128 ; EG-DAG: MOV {{[* ]*}}[[DATA:T[0-9]+\.[XYZW]]], OQAP
129 ; EG-DAG: MOV {{[* ]*}}[[TO:T[0-9]+\.[XYZW]]], KC0[2].Y
130 ; EG: LDS_WRITE {{\*?}} [[TO]], [[DATA]]
131 define amdgpu_kernel void @local_zextload_i16_to_i32(ptr addrspace(3) %out, ptr addrspace(3) %in) #0 {
132 %a = load i16, ptr addrspace(3) %in
133 %ext = zext i16 %a to i32
134 store i32 %ext, ptr addrspace(3) %out
138 ; FUNC-LABEL: {{^}}local_sextload_i16_to_i32:
142 ; SICIVI: s_mov_b32 m0
146 ; EG: MOV {{[* ]*}}[[FROM:T[0-9]+\.[XYZW]]], KC0[2].Z
147 ; EG: LDS_USHORT_READ_RET {{.*}} [[FROM]]
148 ; EG-DAG: MOV {{[* ]*}}[[TMP:T[0-9]+\.[XYZW]]], OQAP
149 ; EG-DAG: MOV {{[* ]*}}[[TO:T[0-9]+\.[XYZW]]], KC0[2].Y
150 ; EG-DAG: BFE_INT {{[* ]*}}[[DATA:T[0-9]+\.[XYZW]]], {{.*}}, 0.0, literal
152 ; EG: LDS_WRITE {{\*?}} [[TO]], [[DATA]]
153 define amdgpu_kernel void @local_sextload_i16_to_i32(ptr addrspace(3) %out, ptr addrspace(3) %in) #0 {
154 %a = load i16, ptr addrspace(3) %in
155 %ext = sext i16 %a to i32
156 store i32 %ext, ptr addrspace(3) %out
160 ; FUNC-LABEL: {{^}}local_zextload_v1i16_to_v1i32:
162 ; SICIVI: s_mov_b32 m0
166 ; EG: MOV {{[* ]*}}[[FROM:T[0-9]+\.[XYZW]]], KC0[2].Z
167 ; EG: LDS_USHORT_READ_RET {{.*}} [[FROM]]
168 ; EG-DAG: MOV {{[* ]*}}[[DATA:T[0-9]+\.[XYZW]]], OQAP
169 ; EG-DAG: MOV {{[* ]*}}[[TO:T[0-9]+\.[XYZW]]], KC0[2].Y
170 ; EG: LDS_WRITE {{\*?}} [[TO]], [[DATA]]
171 define amdgpu_kernel void @local_zextload_v1i16_to_v1i32(ptr addrspace(3) %out, ptr addrspace(3) %in) #0 {
172 %load = load <1 x i16>, ptr addrspace(3) %in
173 %ext = zext <1 x i16> %load to <1 x i32>
174 store <1 x i32> %ext, ptr addrspace(3) %out
178 ; FUNC-LABEL: {{^}}local_sextload_v1i16_to_v1i32:
180 ; SICIVI: s_mov_b32 m0
184 ; EG: MOV {{[* ]*}}[[FROM:T[0-9]+\.[XYZW]]], KC0[2].Z
185 ; EG: LDS_USHORT_READ_RET {{.*}} [[FROM]]
186 ; EG-DAG: MOV {{[* ]*}}[[TMP:T[0-9]+\.[XYZW]]], OQAP
187 ; EG-DAG: MOV {{[* ]*}}[[TO:T[0-9]+\.[XYZW]]], KC0[2].Y
188 ; EG-DAG: BFE_INT {{[* ]*}}[[DATA:T[0-9]+\.[XYZW]]], {{.*}}, 0.0, literal
190 ; EG: LDS_WRITE {{\*?}} [[TO]], [[DATA]]
191 define amdgpu_kernel void @local_sextload_v1i16_to_v1i32(ptr addrspace(3) %out, ptr addrspace(3) %in) #0 {
192 %load = load <1 x i16>, ptr addrspace(3) %in
193 %ext = sext <1 x i16> %load to <1 x i32>
194 store <1 x i32> %ext, ptr addrspace(3) %out
198 ; FUNC-LABEL: {{^}}local_zextload_v2i16_to_v2i32:
201 ; SICIVI: s_mov_b32 m0
206 define amdgpu_kernel void @local_zextload_v2i16_to_v2i32(ptr addrspace(3) %out, ptr addrspace(3) %in) #0 {
207 %load = load <2 x i16>, ptr addrspace(3) %in
208 %ext = zext <2 x i16> %load to <2 x i32>
209 store <2 x i32> %ext, ptr addrspace(3) %out
213 ; FUNC-LABEL: {{^}}local_sextload_v2i16_to_v2i32:
216 ; SICIVI: s_mov_b32 m0
223 define amdgpu_kernel void @local_sextload_v2i16_to_v2i32(ptr addrspace(3) %out, ptr addrspace(3) %in) #0 {
224 %load = load <2 x i16>, ptr addrspace(3) %in
225 %ext = sext <2 x i16> %load to <2 x i32>
226 store <2 x i32> %ext, ptr addrspace(3) %out
230 ; FUNC-LABEL: {{^}}local_local_zextload_v3i16_to_v3i32:
232 ; SICIVI: s_mov_b32 m0
235 ; SI-DAG: ds_write_b32
236 ; SI-DAG: ds_write_b64
237 ; CIVI-DAG: ds_write_b96
238 ; GFX9-DAG: ds_write_b96
240 ; EG: LDS_USHORT_READ_RET
241 ; EG: LDS_USHORT_READ_RET
242 ; EG: LDS_USHORT_READ_RET
243 define amdgpu_kernel void @local_local_zextload_v3i16_to_v3i32(ptr addrspace(3) %out, ptr addrspace(3) %in) {
245 %ld = load <3 x i16>, ptr addrspace(3) %in
246 %ext = zext <3 x i16> %ld to <3 x i32>
247 store <3 x i32> %ext, ptr addrspace(3) %out
251 ; FUNC-LABEL: {{^}}local_local_sextload_v3i16_to_v3i32:
253 ; SICIVI: s_mov_b32 m0
256 ; SI-DAG: ds_write_b32
257 ; SI-DAG: ds_write_b64
258 ; CIVI-DAG: ds_write_b96
259 ; GFX9-DAG: ds_write_b96
261 ; EG: LDS_USHORT_READ_RET
262 ; EG: LDS_USHORT_READ_RET
263 ; EG: LDS_USHORT_READ_RET
267 define amdgpu_kernel void @local_local_sextload_v3i16_to_v3i32(ptr addrspace(3) %out, ptr addrspace(3) %in) {
269 %ld = load <3 x i16>, ptr addrspace(3) %in
270 %ext = sext <3 x i16> %ld to <3 x i32>
271 store <3 x i32> %ext, ptr addrspace(3) %out
275 ; FUNC-LABEL: {{^}}local_local_zextload_v4i16_to_v4i32:
278 ; SICIVI: s_mov_b32 m0
284 define amdgpu_kernel void @local_local_zextload_v4i16_to_v4i32(ptr addrspace(3) %out, ptr addrspace(3) %in) #0 {
285 %load = load <4 x i16>, ptr addrspace(3) %in
286 %ext = zext <4 x i16> %load to <4 x i32>
287 store <4 x i32> %ext, ptr addrspace(3) %out
291 ; FUNC-LABEL: {{^}}local_sextload_v4i16_to_v4i32:
294 ; SICIVI: s_mov_b32 m0
304 define amdgpu_kernel void @local_sextload_v4i16_to_v4i32(ptr addrspace(3) %out, ptr addrspace(3) %in) #0 {
305 %load = load <4 x i16>, ptr addrspace(3) %in
306 %ext = sext <4 x i16> %load to <4 x i32>
307 store <4 x i32> %ext, ptr addrspace(3) %out
311 ; FUNC-LABEL: {{^}}local_zextload_v8i16_to_v8i32:
313 ; SICIVI: s_mov_b32 m0
315 ; GCN: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset1:1{{$}}
321 define amdgpu_kernel void @local_zextload_v8i16_to_v8i32(ptr addrspace(3) %out, ptr addrspace(3) %in) #0 {
322 %load = load <8 x i16>, ptr addrspace(3) %in
323 %ext = zext <8 x i16> %load to <8 x i32>
324 store <8 x i32> %ext, ptr addrspace(3) %out
328 ; FUNC-LABEL: {{^}}local_sextload_v8i16_to_v8i32:
330 ; SICIVI: s_mov_b32 m0
332 ; GCN: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset1:1{{$}}
346 define amdgpu_kernel void @local_sextload_v8i16_to_v8i32(ptr addrspace(3) %out, ptr addrspace(3) %in) #0 {
347 %load = load <8 x i16>, ptr addrspace(3) %in
348 %ext = sext <8 x i16> %load to <8 x i32>
349 store <8 x i32> %ext, ptr addrspace(3) %out
353 ; FUNC-LABEL: {{^}}local_zextload_v16i16_to_v16i32:
355 ; SICIVI: s_mov_b32 m0
357 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset1:1{{$}}
358 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:2 offset1:3{{$}}
373 define amdgpu_kernel void @local_zextload_v16i16_to_v16i32(ptr addrspace(3) %out, ptr addrspace(3) %in) #0 {
374 %load = load <16 x i16>, ptr addrspace(3) %in
375 %ext = zext <16 x i16> %load to <16 x i32>
376 store <16 x i32> %ext, ptr addrspace(3) %out
380 ; FUNC-LABEL: {{^}}local_sextload_v16i16_to_v16i32:
382 ; SICIVI: s_mov_b32 m0
385 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset1:1{{$}}
386 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:2 offset1:3{{$}}
412 define amdgpu_kernel void @local_sextload_v16i16_to_v16i32(ptr addrspace(3) %out, ptr addrspace(3) %in) #0 {
413 %load = load <16 x i16>, ptr addrspace(3) %in
414 %ext = sext <16 x i16> %load to <16 x i32>
415 store <16 x i32> %ext, ptr addrspace(3) %out
419 ; FUNC-LABEL: {{^}}local_zextload_v32i16_to_v32i32:
421 ; SICIVI: s_mov_b32 m0
423 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset1:1{{$}}
424 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:2 offset1:3
425 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:4 offset1:5
426 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:6 offset1:7
444 define amdgpu_kernel void @local_zextload_v32i16_to_v32i32(ptr addrspace(3) %out, ptr addrspace(3) %in) #0 {
445 %load = load <32 x i16>, ptr addrspace(3) %in
446 %ext = zext <32 x i16> %load to <32 x i32>
447 store <32 x i32> %ext, ptr addrspace(3) %out
451 ; FUNC-LABEL: {{^}}local_sextload_v32i16_to_v32i32:
453 ; SICIVI: s_mov_b32 m0
455 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:2 offset1:3{{$}}
456 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:4 offset1:5
457 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset1:1{{$}}
458 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:6 offset1:7
459 ; GCN-DAG: ds_write2_b64 v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}} offset0:14 offset1:15
460 ; GCN-DAG: ds_write2_b64 v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}} offset0:12 offset1:13
461 ; GCN-DAG: ds_write2_b64 v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}} offset0:10 offset1:11
462 ; GCN-DAG: ds_write2_b64 v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}} offset0:8 offset1:9
463 ; GCN-DAG: ds_write2_b64 v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}} offset0:6 offset1:7
464 ; GCN-DAG: ds_write2_b64 v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}} offset0:4 offset1:5
465 ; GCN-DAG: ds_write2_b64 v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}} offset0:2 offset1:3
466 ; GCN-DAG: ds_write2_b64 v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}} offset1:1
484 define amdgpu_kernel void @local_sextload_v32i16_to_v32i32(ptr addrspace(3) %out, ptr addrspace(3) %in) #0 {
485 %load = load <32 x i16>, ptr addrspace(3) %in
486 %ext = sext <32 x i16> %load to <32 x i32>
487 store <32 x i32> %ext, ptr addrspace(3) %out
491 ; FUNC-LABEL: {{^}}local_zextload_v64i16_to_v64i32:
493 ; SICIVI: s_mov_b32 m0
495 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:14 offset1:15
496 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset1:1{{$}}
497 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:2 offset1:3
498 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:4 offset1:5
499 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:6 offset1:7
500 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:8 offset1:9
501 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:12 offset1:13
502 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:10 offset1:11
503 ; GCN-DAG: ds_write2_b64 v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}} offset0:30 offset1:31
504 ; GCN-DAG: ds_write2_b64 v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}} offset0:28 offset1:29
505 ; GCN-DAG: ds_write2_b64 v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}} offset0:26 offset1:27
506 ; GCN-DAG: ds_write2_b64 v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}} offset0:24 offset1:25
507 ; GCN-DAG: ds_write2_b64 v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}} offset0:22 offset1:23
508 ; GCN-DAG: ds_write2_b64 v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}} offset0:20 offset1:21
509 ; GCN-DAG: ds_write2_b64 v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}} offset0:18 offset1:19
510 ; GCN-DAG: ds_write2_b64 v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}} offset0:16 offset1:17
511 ; GCN-DAG: ds_write2_b64 v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}} offset0:14 offset1:15
512 ; GCN-DAG: ds_write2_b64 v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}} offset0:12 offset1:13
513 ; GCN-DAG: ds_write2_b64 v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}} offset0:10 offset1:11
514 ; GCN-DAG: ds_write2_b64 v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}} offset0:8 offset1:9
515 ; GCN-DAG: ds_write2_b64 v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}} offset0:6 offset1:7
516 ; GCN-DAG: ds_write2_b64 v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}} offset0:4 offset1:5
517 ; GCN-DAG: ds_write2_b64 v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}} offset0:2 offset1:3
518 ; GCN-DAG: ds_write2_b64 v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}} offset1:1
552 define amdgpu_kernel void @local_zextload_v64i16_to_v64i32(ptr addrspace(3) %out, ptr addrspace(3) %in) #0 {
553 %load = load <64 x i16>, ptr addrspace(3) %in
554 %ext = zext <64 x i16> %load to <64 x i32>
555 store <64 x i32> %ext, ptr addrspace(3) %out
559 ; FUNC-LABEL: {{^}}local_sextload_v64i16_to_v64i32:
561 ; SICIVI: s_mov_b32 m0
595 define amdgpu_kernel void @local_sextload_v64i16_to_v64i32(ptr addrspace(3) %out, ptr addrspace(3) %in) #0 {
596 %load = load <64 x i16>, ptr addrspace(3) %in
597 %ext = sext <64 x i16> %load to <64 x i32>
598 store <64 x i32> %ext, ptr addrspace(3) %out
602 ; FUNC-LABEL: {{^}}local_zextload_i16_to_i64:
604 ; SICIVI: s_mov_b32 m0
606 ; GCN-DAG: ds_read_u16 v[[LO:[0-9]+]],
607 ; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}}
609 ; GCN: ds_write_b64 v{{[0-9]+}}, v[[[LO]]:[[HI]]]
611 ; EG: MOV {{[* ]*}}[[FROM:T[0-9]+\.[XYZW]]], KC0[2].Z
612 ; EG: LDS_USHORT_READ_RET {{.*}} [[FROM]]
613 ; EG-DAG: MOV {{[* ]*}}[[DATA:T[0-9]+\.[XYZW]]], OQAP
614 ; EG-DAG: MOV {{[* ]*}}[[TO:T[0-9]+\.[XYZW]]], KC0[2].Y
616 define amdgpu_kernel void @local_zextload_i16_to_i64(ptr addrspace(3) %out, ptr addrspace(3) %in) #0 {
617 %a = load i16, ptr addrspace(3) %in
618 %ext = zext i16 %a to i64
619 store i64 %ext, ptr addrspace(3) %out
623 ; FUNC-LABEL: {{^}}local_sextload_i16_to_i64:
625 ; SICIVI: s_mov_b32 m0
627 ; FIXME: Need to optimize this sequence to avoid an extra shift.
628 ; t25: i32,ch = load<LD2[%in(addrspace=3)], anyext from i16> t12, t10, undef:i32
629 ; t28: i64 = any_extend t25
630 ; t30: i64 = sign_extend_inreg t28, ValueType:ch:i16
631 ; SI: ds_read_i16 v[[LO:[0-9]+]],
632 ; GFX89: ds_read_u16 v[[ULO:[0-9]+]]
633 ; GFX89: v_bfe_i32 v[[LO:[0-9]+]], v[[ULO]], 0, 16
634 ; GCN-DAG: v_ashrrev_i32_e32 v[[HI:[0-9]+]], 31, v[[LO]]
636 ; GCN: ds_write_b64 v{{[0-9]+}}, v[[[LO]]:[[HI]]]
638 ; EG: MOV {{[* ]*}}[[FROM:T[0-9]+\.[XYZW]]], KC0[2].Z
639 ; EG: LDS_USHORT_READ_RET {{.*}} [[FROM]]
640 ; EG-DAG: MOV {{[* ]*}}[[TMP:T[0-9]+\.[XYZW]]], OQAP
641 ; EG-DAG: MOV {{[* ]*}}[[TO:T[0-9]+\.[XYZW]]], KC0[2].Y
642 ; EG-DAG: BFE_INT {{[* ]*}}[[DATA:T[0-9]+\.[XYZW]]], {{.*}}, 0.0, literal
645 ; EG: LDS_WRITE {{\*?}} [[TO]], [[DATA]]
646 define amdgpu_kernel void @local_sextload_i16_to_i64(ptr addrspace(3) %out, ptr addrspace(3) %in) #0 {
647 %a = load i16, ptr addrspace(3) %in
648 %ext = sext i16 %a to i64
649 store i64 %ext, ptr addrspace(3) %out
653 ; FUNC-LABEL: {{^}}local_zextload_v1i16_to_v1i64:
655 ; SICIVI: s_mov_b32 m0
658 ; EG: MOV {{[* ]*}}[[FROM:T[0-9]+\.[XYZW]]], KC0[2].Z
659 ; EG: LDS_USHORT_READ_RET {{.*}} [[FROM]]
660 ; EG-DAG: MOV {{[* ]*}}[[DATA:T[0-9]+\.[XYZW]]], OQAP
661 ; EG-DAG: MOV {{[* ]*}}[[TO:T[0-9]+\.[XYZW]]], KC0[2].Y
663 define amdgpu_kernel void @local_zextload_v1i16_to_v1i64(ptr addrspace(3) %out, ptr addrspace(3) %in) #0 {
664 %load = load <1 x i16>, ptr addrspace(3) %in
665 %ext = zext <1 x i16> %load to <1 x i64>
666 store <1 x i64> %ext, ptr addrspace(3) %out
670 ; FUNC-LABEL: {{^}}local_sextload_v1i16_to_v1i64:
672 ; SICIVI: s_mov_b32 m0
675 ; EG: MOV {{[* ]*}}[[FROM:T[0-9]+\.[XYZW]]], KC0[2].Z
676 ; EG: LDS_USHORT_READ_RET {{.*}} [[FROM]]
677 ; EG-DAG: MOV {{[* ]*}}[[TMP:T[0-9]+\.[XYZW]]], OQAP
678 ; EG-DAG: MOV {{[* ]*}}[[TO:T[0-9]+\.[XYZW]]], KC0[2].Y
679 ; EG-DAG: BFE_INT {{[* ]*}}[[DATA:T[0-9]+\.[XYZW]]], {{.*}}, 0.0, literal
682 ; EG: LDS_WRITE {{\*?}} [[TO]], [[DATA]]
683 define amdgpu_kernel void @local_sextload_v1i16_to_v1i64(ptr addrspace(3) %out, ptr addrspace(3) %in) #0 {
684 %load = load <1 x i16>, ptr addrspace(3) %in
685 %ext = sext <1 x i16> %load to <1 x i64>
686 store <1 x i64> %ext, ptr addrspace(3) %out
690 ; FUNC-LABEL: {{^}}local_zextload_v2i16_to_v2i64:
692 ; SICIVI: s_mov_b32 m0
696 define amdgpu_kernel void @local_zextload_v2i16_to_v2i64(ptr addrspace(3) %out, ptr addrspace(3) %in) #0 {
697 %load = load <2 x i16>, ptr addrspace(3) %in
698 %ext = zext <2 x i16> %load to <2 x i64>
699 store <2 x i64> %ext, ptr addrspace(3) %out
703 ; FUNC-LABEL: {{^}}local_sextload_v2i16_to_v2i64:
705 ; SICIVI: s_mov_b32 m0
711 define amdgpu_kernel void @local_sextload_v2i16_to_v2i64(ptr addrspace(3) %out, ptr addrspace(3) %in) #0 {
712 %load = load <2 x i16>, ptr addrspace(3) %in
713 %ext = sext <2 x i16> %load to <2 x i64>
714 store <2 x i64> %ext, ptr addrspace(3) %out
718 ; FUNC-LABEL: {{^}}local_zextload_v4i16_to_v4i64:
720 ; SICIVI: s_mov_b32 m0
725 define amdgpu_kernel void @local_zextload_v4i16_to_v4i64(ptr addrspace(3) %out, ptr addrspace(3) %in) #0 {
726 %load = load <4 x i16>, ptr addrspace(3) %in
727 %ext = zext <4 x i16> %load to <4 x i64>
728 store <4 x i64> %ext, ptr addrspace(3) %out
732 ; FUNC-LABEL: {{^}}local_sextload_v4i16_to_v4i64:
734 ; SICIVI: s_mov_b32 m0
743 define amdgpu_kernel void @local_sextload_v4i16_to_v4i64(ptr addrspace(3) %out, ptr addrspace(3) %in) #0 {
744 %load = load <4 x i16>, ptr addrspace(3) %in
745 %ext = sext <4 x i16> %load to <4 x i64>
746 store <4 x i64> %ext, ptr addrspace(3) %out
750 ; FUNC-LABEL: {{^}}local_zextload_v8i16_to_v8i64:
752 ; SICIVI: s_mov_b32 m0
759 define amdgpu_kernel void @local_zextload_v8i16_to_v8i64(ptr addrspace(3) %out, ptr addrspace(3) %in) #0 {
760 %load = load <8 x i16>, ptr addrspace(3) %in
761 %ext = zext <8 x i16> %load to <8 x i64>
762 store <8 x i64> %ext, ptr addrspace(3) %out
766 ; FUNC-LABEL: {{^}}local_sextload_v8i16_to_v8i64:
768 ; SICIVI: s_mov_b32 m0
783 define amdgpu_kernel void @local_sextload_v8i16_to_v8i64(ptr addrspace(3) %out, ptr addrspace(3) %in) #0 {
784 %load = load <8 x i16>, ptr addrspace(3) %in
785 %ext = sext <8 x i16> %load to <8 x i64>
786 store <8 x i64> %ext, ptr addrspace(3) %out
790 ; FUNC-LABEL: {{^}}local_zextload_v16i16_to_v16i64:
792 ; SICIVI: s_mov_b32 m0
803 define amdgpu_kernel void @local_zextload_v16i16_to_v16i64(ptr addrspace(3) %out, ptr addrspace(3) %in) #0 {
804 %load = load <16 x i16>, ptr addrspace(3) %in
805 %ext = zext <16 x i16> %load to <16 x i64>
806 store <16 x i64> %ext, ptr addrspace(3) %out
810 ; FUNC-LABEL: {{^}}local_sextload_v16i16_to_v16i64:
812 ; SICIVI: s_mov_b32 m0
839 define amdgpu_kernel void @local_sextload_v16i16_to_v16i64(ptr addrspace(3) %out, ptr addrspace(3) %in) #0 {
840 %load = load <16 x i16>, ptr addrspace(3) %in
841 %ext = sext <16 x i16> %load to <16 x i64>
842 store <16 x i64> %ext, ptr addrspace(3) %out
846 ; FUNC-LABEL: {{^}}local_zextload_v32i16_to_v32i64:
848 ; SICIVI: s_mov_b32 m0
867 define amdgpu_kernel void @local_zextload_v32i16_to_v32i64(ptr addrspace(3) %out, ptr addrspace(3) %in) #0 {
868 %load = load <32 x i16>, ptr addrspace(3) %in
869 %ext = zext <32 x i16> %load to <32 x i64>
870 store <32 x i64> %ext, ptr addrspace(3) %out
874 ; FUNC-LABEL: {{^}}local_sextload_v32i16_to_v32i64:
876 ; SICIVI: s_mov_b32 m0
927 define amdgpu_kernel void @local_sextload_v32i16_to_v32i64(ptr addrspace(3) %out, ptr addrspace(3) %in) #0 {
928 %load = load <32 x i16>, ptr addrspace(3) %in
929 %ext = sext <32 x i16> %load to <32 x i64>
930 store <32 x i64> %ext, ptr addrspace(3) %out
934 ; ; XFUNC-LABEL: {{^}}local_zextload_v64i16_to_v64i64:
935 ; define amdgpu_kernel void @local_zextload_v64i16_to_v64i64(ptr addrspace(3) %out, ptr addrspace(3) %in) #0 {
936 ; %load = load <64 x i16>, ptr addrspace(3) %in
937 ; %ext = zext <64 x i16> %load to <64 x i64>
938 ; store <64 x i64> %ext, ptr addrspace(3) %out
942 ; ; XFUNC-LABEL: {{^}}local_sextload_v64i16_to_v64i64:
943 ; define amdgpu_kernel void @local_sextload_v64i16_to_v64i64(ptr addrspace(3) %out, ptr addrspace(3) %in) #0 {
944 ; %load = load <64 x i16>, ptr addrspace(3) %in
945 ; %ext = sext <64 x i16> %load to <64 x i64>
946 ; store <64 x i64> %ext, ptr addrspace(3) %out
950 ; Tests if ds_read/write_b128 gets generated for the 16 byte aligned load.
951 ; FUNC-LABEL: {{^}}local_v8i16_to_128:
953 ; SI-NOT: ds_read_b128
954 ; SI-NOT: ds_write_b128
957 ; CIVI: ds_write_b128
963 define amdgpu_kernel void @local_v8i16_to_128(ptr addrspace(3) %out, ptr addrspace(3) %in) {
964 %ld = load <8 x i16>, ptr addrspace(3) %in, align 16
965 store <8 x i16> %ld, ptr addrspace(3) %out, align 16
969 attributes #0 = { nounwind }