1 ; Function Attrs: nounwind
2 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
4 ; CFG flattening should use parallel-or to generate branch conditions and
5 ; then merge if-regions with the same bodies.
7 ; FIXME: For some reason having the allocas here allowed the flatten cfg pass
8 ; to do its transformation, however now that we are using local memory for
9 ; allocas, the transformation isn't happening.
15 define amdgpu_kernel void @_Z9chk1D_512v() #0 {
17 %a0 = alloca i32, align 4, addrspace(5)
18 %b0 = alloca i32, align 4, addrspace(5)
19 %c0 = alloca i32, align 4, addrspace(5)
20 %d0 = alloca i32, align 4, addrspace(5)
21 %a1 = alloca i32, align 4, addrspace(5)
22 %b1 = alloca i32, align 4, addrspace(5)
23 %c1 = alloca i32, align 4, addrspace(5)
24 %d1 = alloca i32, align 4, addrspace(5)
25 %data = alloca i32, align 4, addrspace(5)
26 %0 = load i32, ptr addrspace(5) %a0, align 4
27 %1 = load i32, ptr addrspace(5) %b0, align 4
28 %cmp = icmp ne i32 %0, %1
29 br i1 %cmp, label %land.lhs.true, label %if.else
31 land.lhs.true: ; preds = %entry
32 %2 = load i32, ptr addrspace(5) %c0, align 4
33 %3 = load i32, ptr addrspace(5) %d0, align 4
34 %cmp1 = icmp ne i32 %2, %3
35 br i1 %cmp1, label %if.then, label %if.else
37 if.then: ; preds = %land.lhs.true
40 if.else: ; preds = %land.lhs.true, %entry
41 store i32 1, ptr addrspace(5) %data, align 4
44 if.end: ; preds = %if.else, %if.then
45 %4 = load i32, ptr addrspace(5) %a1, align 4
46 %5 = load i32, ptr addrspace(5) %b1, align 4
47 %cmp2 = icmp ne i32 %4, %5
48 br i1 %cmp2, label %land.lhs.true3, label %if.else6
50 land.lhs.true3: ; preds = %if.end
51 %6 = load i32, ptr addrspace(5) %c1, align 4
52 %7 = load i32, ptr addrspace(5) %d1, align 4
53 %cmp4 = icmp ne i32 %6, %7
54 br i1 %cmp4, label %if.then5, label %if.else6
56 if.then5: ; preds = %land.lhs.true3
59 if.else6: ; preds = %land.lhs.true3, %if.end
60 store i32 1, ptr addrspace(5) %data, align 4
63 if.end7: ; preds = %if.else6, %if.then5