llvm/test/CodeGen/AMDGPU/post-ra-sched-reset.mir

   1 # RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=post-RA-sched -verify-machineinstrs -debug-only=post-RA-sched -o - %s 2>&1 | FileCheck %s
   2
   3 # REQUIRES: asserts
   4
   5 # CHECK-NOT: Stall in cycle
   6 ---
   7 name:            hazard_rec_reset
   8 tracksRegLiveness: true
   9 body:             |
  10   bb.0:
  11     successors: %bb.1
  12
  13     $m0 = S_MOV_B32 0
  14
  15   bb.1:
  16     liveins: $vgpr4
  17
  18     S_SETREG_IMM32_B32 0, 1, implicit-def $mode, implicit $mode
  19     $vgpr0 = V_INTERP_P1_F32 killed $vgpr4, 0, 0, implicit $mode, implicit $m0, implicit $exec
  20     S_ENDPGM 0
  21
  22 ...