1 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2 # RUN: llc -mtriple=amdgcn-amd-amdhsa -amdgpu-enable-rewrite-partial-reg-uses=true -verify-machineinstrs -start-before=rename-independent-subregs -stop-after=rewrite-partial-reg-uses %s -o - | FileCheck -check-prefix=CHECK %s
4 name: test_subregs_composition_vreg_1024
5 tracksRegLiveness: true
8 ; CHECK-LABEL: name: test_subregs_composition_vreg_1024
9 ; CHECK: undef %5.sub0:vreg_96 = V_MOV_B32_e32 1, implicit $exec
10 ; CHECK-NEXT: %5.sub1:vreg_96 = V_MOV_B32_e32 2, implicit $exec
11 ; CHECK-NEXT: S_NOP 0, implicit %5.sub0_sub1
12 ; CHECK-NEXT: S_NOP 0, implicit %5.sub1_sub2
13 ; CHECK-NEXT: undef %6.sub0:vreg_128 = V_MOV_B32_e32 11, implicit $exec
14 ; CHECK-NEXT: %6.sub1:vreg_128 = V_MOV_B32_e32 12, implicit $exec
15 ; CHECK-NEXT: S_NOP 0, implicit %6.sub0_sub1_sub2
16 ; CHECK-NEXT: S_NOP 0, implicit %6.sub1_sub2_sub3
17 ; CHECK-NEXT: undef %7.sub0:vreg_160 = V_MOV_B32_e32 21, implicit $exec
18 ; CHECK-NEXT: %7.sub1:vreg_160 = V_MOV_B32_e32 22, implicit $exec
19 ; CHECK-NEXT: S_NOP 0, implicit %7.sub0_sub1_sub2_sub3
20 ; CHECK-NEXT: S_NOP 0, implicit %7.sub1_sub2_sub3_sub4
21 ; CHECK-NEXT: undef %8.sub0:vreg_192 = V_MOV_B32_e32 31, implicit $exec
22 ; CHECK-NEXT: %8.sub1:vreg_192 = V_MOV_B32_e32 32, implicit $exec
23 ; CHECK-NEXT: S_NOP 0, implicit %8.sub0_sub1_sub2_sub3_sub4
24 ; CHECK-NEXT: S_NOP 0, implicit %8.sub1_sub2_sub3_sub4_sub5
25 ; CHECK-NEXT: undef %9.sub0:vreg_256 = V_MOV_B32_e32 41, implicit $exec
26 ; CHECK-NEXT: %9.sub2:vreg_256 = V_MOV_B32_e32 43, implicit $exec
27 ; CHECK-NEXT: S_NOP 0, implicit %9.sub0_sub1_sub2_sub3_sub4_sub5
28 ; CHECK-NEXT: S_NOP 0, implicit %9.sub2_sub3_sub4_sub5_sub6_sub7
29 undef %0.sub1:vreg_1024 = V_MOV_B32_e32 01, implicit $exec
30 %0.sub2:vreg_1024 = V_MOV_B32_e32 02, implicit $exec
31 S_NOP 0, implicit %0.sub1_sub2
32 S_NOP 0, implicit %0.sub2_sub3
34 undef %1.sub1:vreg_1024 = V_MOV_B32_e32 11, implicit $exec
35 %1.sub2:vreg_1024 = V_MOV_B32_e32 12, implicit $exec
36 S_NOP 0, implicit %1.sub1_sub2_sub3
37 S_NOP 0, implicit %1.sub2_sub3_sub4
39 undef %2.sub1:vreg_1024 = V_MOV_B32_e32 21, implicit $exec
40 %2.sub2:vreg_1024 = V_MOV_B32_e32 22, implicit $exec
41 S_NOP 0, implicit %2.sub1_sub2_sub3_sub4
42 S_NOP 0, implicit %2.sub2_sub3_sub4_sub5
44 undef %3.sub1:vreg_1024 = V_MOV_B32_e32 31, implicit $exec
45 %3.sub2:vreg_1024 = V_MOV_B32_e32 32, implicit $exec
46 S_NOP 0, implicit %3.sub1_sub2_sub3_sub4_sub5
47 S_NOP 0, implicit %3.sub2_sub3_sub4_sub5_sub6
49 undef %4.sub1:vreg_1024 = V_MOV_B32_e32 41, implicit $exec
50 %4.sub3:vreg_1024 = V_MOV_B32_e32 43, implicit $exec
51 S_NOP 0, implicit %4.sub1_sub2_sub3_sub4_sub5_sub6
52 S_NOP 0, implicit %4.sub3_sub4_sub5_sub6_sub7_sub8
56 name: test_vreg_64_w32
57 tracksRegLiveness: true
60 ; CHECK-LABEL: name: test_vreg_64_w32
61 ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
62 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
63 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 11, implicit $exec
64 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
65 undef %0.sub0:vreg_64 = V_MOV_B32_e32 00, implicit $exec
66 S_NOP 0, implicit %0.sub0
68 undef %1.sub1:vreg_64 = V_MOV_B32_e32 11, implicit $exec
69 S_NOP 0, implicit %1.sub1
73 name: test_vreg_96_w32
74 tracksRegLiveness: true
77 ; CHECK-LABEL: name: test_vreg_96_w32
78 ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
79 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
80 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 11, implicit $exec
81 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
82 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 22, implicit $exec
83 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
84 undef %0.sub0:vreg_96 = V_MOV_B32_e32 00, implicit $exec
85 S_NOP 0, implicit %0.sub0
87 undef %1.sub1:vreg_96 = V_MOV_B32_e32 11, implicit $exec
88 S_NOP 0, implicit %1.sub1
90 undef %2.sub2:vreg_96 = V_MOV_B32_e32 22, implicit $exec
91 S_NOP 0, implicit %2.sub2
95 name: test_vreg_96_w64
96 tracksRegLiveness: true
99 ; CHECK-LABEL: name: test_vreg_96_w64
100 ; CHECK: undef %2.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
101 ; CHECK-NEXT: %2.sub1:vreg_64 = V_MOV_B32_e32 1, implicit $exec
102 ; CHECK-NEXT: S_NOP 0, implicit %2
103 ; CHECK-NEXT: undef %3.sub0:vreg_64 = V_MOV_B32_e32 11, implicit $exec
104 ; CHECK-NEXT: %3.sub1:vreg_64 = V_MOV_B32_e32 12, implicit $exec
105 ; CHECK-NEXT: S_NOP 0, implicit %3
106 undef %0.sub0:vreg_96 = V_MOV_B32_e32 00, implicit $exec
107 %0.sub1:vreg_96 = V_MOV_B32_e32 01, implicit $exec
108 S_NOP 0, implicit %0.sub0_sub1
110 undef %1.sub1:vreg_96 = V_MOV_B32_e32 11, implicit $exec
111 %1.sub2:vreg_96 = V_MOV_B32_e32 12, implicit $exec
112 S_NOP 0, implicit %1.sub1_sub2
116 name: test_vreg_128_w32
117 tracksRegLiveness: true
120 ; CHECK-LABEL: name: test_vreg_128_w32
121 ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
122 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
123 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 11, implicit $exec
124 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
125 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 23, implicit $exec
126 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
127 undef %0.sub0:vreg_128 = V_MOV_B32_e32 00, implicit $exec
128 S_NOP 0, implicit %0.sub0
130 undef %1.sub1:vreg_128 = V_MOV_B32_e32 11, implicit $exec
131 S_NOP 0, implicit %1.sub1
133 undef %2.sub3:vreg_128 = V_MOV_B32_e32 23, implicit $exec
134 S_NOP 0, implicit %2.sub3
138 name: test_vreg_128_w64
139 tracksRegLiveness: true
142 ; CHECK-LABEL: name: test_vreg_128_w64
143 ; CHECK: undef %3.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
144 ; CHECK-NEXT: %3.sub1:vreg_64 = V_MOV_B32_e32 1, implicit $exec
145 ; CHECK-NEXT: S_NOP 0, implicit %3
146 ; CHECK-NEXT: undef %4.sub0:vreg_64 = V_MOV_B32_e32 11, implicit $exec
147 ; CHECK-NEXT: %4.sub1:vreg_64 = V_MOV_B32_e32 12, implicit $exec
148 ; CHECK-NEXT: S_NOP 0, implicit %4
149 ; CHECK-NEXT: undef %5.sub0:vreg_64 = V_MOV_B32_e32 22, implicit $exec
150 ; CHECK-NEXT: %5.sub1:vreg_64 = V_MOV_B32_e32 23, implicit $exec
151 ; CHECK-NEXT: S_NOP 0, implicit %5
152 undef %0.sub0:vreg_128 = V_MOV_B32_e32 00, implicit $exec
153 %0.sub1:vreg_128 = V_MOV_B32_e32 01, implicit $exec
154 S_NOP 0, implicit %0.sub0_sub1
156 undef %1.sub1:vreg_128 = V_MOV_B32_e32 11, implicit $exec
157 %1.sub2:vreg_128 = V_MOV_B32_e32 12, implicit $exec
158 S_NOP 0, implicit %1.sub1_sub2
160 undef %2.sub2:vreg_128 = V_MOV_B32_e32 22, implicit $exec
161 %2.sub3:vreg_128 = V_MOV_B32_e32 23, implicit $exec
162 S_NOP 0, implicit %2.sub2_sub3
166 name: test_vreg_128_w96
167 tracksRegLiveness: true
170 ; CHECK-LABEL: name: test_vreg_128_w96
171 ; CHECK: undef %2.sub0:vreg_96 = V_MOV_B32_e32 0, implicit $exec
172 ; CHECK-NEXT: %2.sub1:vreg_96 = V_MOV_B32_e32 1, implicit $exec
173 ; CHECK-NEXT: %2.sub2:vreg_96 = V_MOV_B32_e32 2, implicit $exec
174 ; CHECK-NEXT: S_NOP 0, implicit %2
175 ; CHECK-NEXT: undef %3.sub0:vreg_96 = V_MOV_B32_e32 11, implicit $exec
176 ; CHECK-NEXT: %3.sub1:vreg_96 = V_MOV_B32_e32 12, implicit $exec
177 ; CHECK-NEXT: %3.sub2:vreg_96 = V_MOV_B32_e32 13, implicit $exec
178 ; CHECK-NEXT: S_NOP 0, implicit %3
179 undef %0.sub0:vreg_128 = V_MOV_B32_e32 00, implicit $exec
180 %0.sub1:vreg_128 = V_MOV_B32_e32 01, implicit $exec
181 %0.sub2:vreg_128 = V_MOV_B32_e32 02, implicit $exec
182 S_NOP 0, implicit %0.sub0_sub1_sub2
184 undef %1.sub1:vreg_128 = V_MOV_B32_e32 11, implicit $exec
185 %1.sub2:vreg_128 = V_MOV_B32_e32 12, implicit $exec
186 %1.sub3:vreg_128 = V_MOV_B32_e32 13, implicit $exec
187 S_NOP 0, implicit %1.sub1_sub2_sub3
191 name: test_vreg_160_w32
192 tracksRegLiveness: true
195 ; CHECK-LABEL: name: test_vreg_160_w32
196 ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
197 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
198 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 11, implicit $exec
199 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
200 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 24, implicit $exec
201 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
202 undef %0.sub0:vreg_160 = V_MOV_B32_e32 00, implicit $exec
203 S_NOP 0, implicit %0.sub0
205 undef %1.sub1:vreg_160 = V_MOV_B32_e32 11, implicit $exec
206 S_NOP 0, implicit %1.sub1
208 undef %2.sub4:vreg_160 = V_MOV_B32_e32 24, implicit $exec
209 S_NOP 0, implicit %2.sub4
213 name: test_vreg_160_w64
214 tracksRegLiveness: true
217 ; CHECK-LABEL: name: test_vreg_160_w64
218 ; CHECK: undef %3.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
219 ; CHECK-NEXT: %3.sub1:vreg_64 = V_MOV_B32_e32 1, implicit $exec
220 ; CHECK-NEXT: S_NOP 0, implicit %3
221 ; CHECK-NEXT: undef %4.sub0:vreg_64 = V_MOV_B32_e32 11, implicit $exec
222 ; CHECK-NEXT: %4.sub1:vreg_64 = V_MOV_B32_e32 12, implicit $exec
223 ; CHECK-NEXT: S_NOP 0, implicit %4
224 ; CHECK-NEXT: undef %5.sub0:vreg_64 = V_MOV_B32_e32 23, implicit $exec
225 ; CHECK-NEXT: %5.sub1:vreg_64 = V_MOV_B32_e32 24, implicit $exec
226 ; CHECK-NEXT: S_NOP 0, implicit %5
227 undef %0.sub0:vreg_160 = V_MOV_B32_e32 00, implicit $exec
228 %0.sub1:vreg_160 = V_MOV_B32_e32 01, implicit $exec
229 S_NOP 0, implicit %0.sub0_sub1
231 undef %1.sub1:vreg_160 = V_MOV_B32_e32 11, implicit $exec
232 %1.sub2:vreg_160 = V_MOV_B32_e32 12, implicit $exec
233 S_NOP 0, implicit %1.sub1_sub2
235 undef %2.sub3:vreg_160 = V_MOV_B32_e32 23, implicit $exec
236 %2.sub4:vreg_160 = V_MOV_B32_e32 24, implicit $exec
237 S_NOP 0, implicit %2.sub3_sub4
241 name: test_vreg_160_w96
242 tracksRegLiveness: true
245 ; CHECK-LABEL: name: test_vreg_160_w96
246 ; CHECK: undef %3.sub0:vreg_96 = V_MOV_B32_e32 0, implicit $exec
247 ; CHECK-NEXT: %3.sub1:vreg_96 = V_MOV_B32_e32 1, implicit $exec
248 ; CHECK-NEXT: %3.sub2:vreg_96 = V_MOV_B32_e32 2, implicit $exec
249 ; CHECK-NEXT: S_NOP 0, implicit %3
250 ; CHECK-NEXT: undef %4.sub0:vreg_96 = V_MOV_B32_e32 11, implicit $exec
251 ; CHECK-NEXT: %4.sub1:vreg_96 = V_MOV_B32_e32 12, implicit $exec
252 ; CHECK-NEXT: %4.sub2:vreg_96 = V_MOV_B32_e32 13, implicit $exec
253 ; CHECK-NEXT: S_NOP 0, implicit %4
254 ; CHECK-NEXT: undef %5.sub0:vreg_96 = V_MOV_B32_e32 22, implicit $exec
255 ; CHECK-NEXT: %5.sub1:vreg_96 = V_MOV_B32_e32 23, implicit $exec
256 ; CHECK-NEXT: %5.sub2:vreg_96 = V_MOV_B32_e32 24, implicit $exec
257 ; CHECK-NEXT: S_NOP 0, implicit %5
258 undef %0.sub0:vreg_160 = V_MOV_B32_e32 00, implicit $exec
259 %0.sub1:vreg_160 = V_MOV_B32_e32 01, implicit $exec
260 %0.sub2:vreg_160 = V_MOV_B32_e32 02, implicit $exec
261 S_NOP 0, implicit %0.sub0_sub1_sub2
263 undef %1.sub1:vreg_160 = V_MOV_B32_e32 11, implicit $exec
264 %1.sub2:vreg_160 = V_MOV_B32_e32 12, implicit $exec
265 %1.sub3:vreg_160 = V_MOV_B32_e32 13, implicit $exec
266 S_NOP 0, implicit %1.sub1_sub2_sub3
268 undef %2.sub2:vreg_160 = V_MOV_B32_e32 22, implicit $exec
269 %2.sub3:vreg_160 = V_MOV_B32_e32 23, implicit $exec
270 %2.sub4:vreg_160 = V_MOV_B32_e32 24, implicit $exec
271 S_NOP 0, implicit %2.sub2_sub3_sub4
275 name: test_vreg_160_w128
276 tracksRegLiveness: true
279 ; CHECK-LABEL: name: test_vreg_160_w128
280 ; CHECK: undef %2.sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec
281 ; CHECK-NEXT: %2.sub1:vreg_128 = V_MOV_B32_e32 1, implicit $exec
282 ; CHECK-NEXT: %2.sub2:vreg_128 = V_MOV_B32_e32 2, implicit $exec
283 ; CHECK-NEXT: %2.sub3:vreg_128 = V_MOV_B32_e32 3, implicit $exec
284 ; CHECK-NEXT: S_NOP 0, implicit %2
285 ; CHECK-NEXT: undef %3.sub0:vreg_128 = V_MOV_B32_e32 11, implicit $exec
286 ; CHECK-NEXT: %3.sub1:vreg_128 = V_MOV_B32_e32 12, implicit $exec
287 ; CHECK-NEXT: %3.sub2:vreg_128 = V_MOV_B32_e32 13, implicit $exec
288 ; CHECK-NEXT: %3.sub3:vreg_128 = V_MOV_B32_e32 14, implicit $exec
289 ; CHECK-NEXT: S_NOP 0, implicit %3
290 undef %0.sub0:vreg_160 = V_MOV_B32_e32 00, implicit $exec
291 %0.sub1:vreg_160 = V_MOV_B32_e32 01, implicit $exec
292 %0.sub2:vreg_160 = V_MOV_B32_e32 02, implicit $exec
293 %0.sub3:vreg_160 = V_MOV_B32_e32 03, implicit $exec
294 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3
296 undef %1.sub1:vreg_160 = V_MOV_B32_e32 11, implicit $exec
297 %1.sub2:vreg_160 = V_MOV_B32_e32 12, implicit $exec
298 %1.sub3:vreg_160 = V_MOV_B32_e32 13, implicit $exec
299 %1.sub4:vreg_160 = V_MOV_B32_e32 14, implicit $exec
300 S_NOP 0, implicit %1.sub1_sub2_sub3_sub4
304 name: test_vreg_192_w32
305 tracksRegLiveness: true
308 ; CHECK-LABEL: name: test_vreg_192_w32
309 ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
310 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
311 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 11, implicit $exec
312 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
313 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 25, implicit $exec
314 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
315 undef %0.sub0:vreg_192 = V_MOV_B32_e32 00, implicit $exec
316 S_NOP 0, implicit %0.sub0
318 undef %1.sub1:vreg_192 = V_MOV_B32_e32 11, implicit $exec
319 S_NOP 0, implicit %1.sub1
321 undef %2.sub5:vreg_192 = V_MOV_B32_e32 25, implicit $exec
322 S_NOP 0, implicit %2.sub5
326 name: test_vreg_192_w64
327 tracksRegLiveness: true
330 ; CHECK-LABEL: name: test_vreg_192_w64
331 ; CHECK: undef %3.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
332 ; CHECK-NEXT: %3.sub1:vreg_64 = V_MOV_B32_e32 1, implicit $exec
333 ; CHECK-NEXT: S_NOP 0, implicit %3
334 ; CHECK-NEXT: undef %4.sub0:vreg_64 = V_MOV_B32_e32 11, implicit $exec
335 ; CHECK-NEXT: %4.sub1:vreg_64 = V_MOV_B32_e32 12, implicit $exec
336 ; CHECK-NEXT: S_NOP 0, implicit %4
337 ; CHECK-NEXT: undef %5.sub0:vreg_64 = V_MOV_B32_e32 24, implicit $exec
338 ; CHECK-NEXT: %5.sub1:vreg_64 = V_MOV_B32_e32 25, implicit $exec
339 ; CHECK-NEXT: S_NOP 0, implicit %5
340 undef %0.sub0:vreg_192 = V_MOV_B32_e32 00, implicit $exec
341 %0.sub1:vreg_192 = V_MOV_B32_e32 01, implicit $exec
342 S_NOP 0, implicit %0.sub0_sub1
344 undef %1.sub1:vreg_192 = V_MOV_B32_e32 11, implicit $exec
345 %1.sub2:vreg_192 = V_MOV_B32_e32 12, implicit $exec
346 S_NOP 0, implicit %1.sub1_sub2
348 undef %2.sub4:vreg_192 = V_MOV_B32_e32 24, implicit $exec
349 %2.sub5:vreg_192 = V_MOV_B32_e32 25, implicit $exec
350 S_NOP 0, implicit %2.sub4_sub5
354 name: test_vreg_192_w96
355 tracksRegLiveness: true
358 ; CHECK-LABEL: name: test_vreg_192_w96
359 ; CHECK: undef %3.sub0:vreg_96 = V_MOV_B32_e32 0, implicit $exec
360 ; CHECK-NEXT: %3.sub1:vreg_96 = V_MOV_B32_e32 1, implicit $exec
361 ; CHECK-NEXT: %3.sub2:vreg_96 = V_MOV_B32_e32 2, implicit $exec
362 ; CHECK-NEXT: S_NOP 0, implicit %3
363 ; CHECK-NEXT: undef %4.sub0:vreg_96 = V_MOV_B32_e32 11, implicit $exec
364 ; CHECK-NEXT: %4.sub1:vreg_96 = V_MOV_B32_e32 12, implicit $exec
365 ; CHECK-NEXT: %4.sub2:vreg_96 = V_MOV_B32_e32 13, implicit $exec
366 ; CHECK-NEXT: S_NOP 0, implicit %4
367 ; CHECK-NEXT: undef %5.sub0:vreg_96 = V_MOV_B32_e32 23, implicit $exec
368 ; CHECK-NEXT: %5.sub1:vreg_96 = V_MOV_B32_e32 24, implicit $exec
369 ; CHECK-NEXT: %5.sub2:vreg_96 = V_MOV_B32_e32 25, implicit $exec
370 ; CHECK-NEXT: S_NOP 0, implicit %5
371 undef %0.sub0:vreg_192 = V_MOV_B32_e32 00, implicit $exec
372 %0.sub1:vreg_192 = V_MOV_B32_e32 01, implicit $exec
373 %0.sub2:vreg_192 = V_MOV_B32_e32 02, implicit $exec
374 S_NOP 0, implicit %0.sub0_sub1_sub2
376 undef %1.sub1:vreg_192 = V_MOV_B32_e32 11, implicit $exec
377 %1.sub2:vreg_192 = V_MOV_B32_e32 12, implicit $exec
378 %1.sub3:vreg_192 = V_MOV_B32_e32 13, implicit $exec
379 S_NOP 0, implicit %1.sub1_sub2_sub3
381 undef %2.sub3:vreg_192 = V_MOV_B32_e32 23, implicit $exec
382 %2.sub4:vreg_192 = V_MOV_B32_e32 24, implicit $exec
383 %2.sub5:vreg_192 = V_MOV_B32_e32 25, implicit $exec
384 S_NOP 0, implicit %2.sub3_sub4_sub5
388 name: test_vreg_192_w128
389 tracksRegLiveness: true
392 ; CHECK-LABEL: name: test_vreg_192_w128
393 ; CHECK: undef %3.sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec
394 ; CHECK-NEXT: %3.sub1:vreg_128 = V_MOV_B32_e32 1, implicit $exec
395 ; CHECK-NEXT: %3.sub2:vreg_128 = V_MOV_B32_e32 2, implicit $exec
396 ; CHECK-NEXT: %3.sub3:vreg_128 = V_MOV_B32_e32 3, implicit $exec
397 ; CHECK-NEXT: S_NOP 0, implicit %3
398 ; CHECK-NEXT: undef %4.sub0:vreg_128 = V_MOV_B32_e32 11, implicit $exec
399 ; CHECK-NEXT: %4.sub1:vreg_128 = V_MOV_B32_e32 12, implicit $exec
400 ; CHECK-NEXT: %4.sub2:vreg_128 = V_MOV_B32_e32 13, implicit $exec
401 ; CHECK-NEXT: %4.sub3:vreg_128 = V_MOV_B32_e32 14, implicit $exec
402 ; CHECK-NEXT: S_NOP 0, implicit %4
403 ; CHECK-NEXT: undef %5.sub0:vreg_128 = V_MOV_B32_e32 22, implicit $exec
404 ; CHECK-NEXT: %5.sub1:vreg_128 = V_MOV_B32_e32 23, implicit $exec
405 ; CHECK-NEXT: %5.sub2:vreg_128 = V_MOV_B32_e32 24, implicit $exec
406 ; CHECK-NEXT: %5.sub3:vreg_128 = V_MOV_B32_e32 25, implicit $exec
407 ; CHECK-NEXT: S_NOP 0, implicit %5
408 undef %0.sub0:vreg_192 = V_MOV_B32_e32 00, implicit $exec
409 %0.sub1:vreg_192 = V_MOV_B32_e32 01, implicit $exec
410 %0.sub2:vreg_192 = V_MOV_B32_e32 02, implicit $exec
411 %0.sub3:vreg_192 = V_MOV_B32_e32 03, implicit $exec
412 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3
414 undef %1.sub1:vreg_192 = V_MOV_B32_e32 11, implicit $exec
415 %1.sub2:vreg_192 = V_MOV_B32_e32 12, implicit $exec
416 %1.sub3:vreg_192 = V_MOV_B32_e32 13, implicit $exec
417 %1.sub4:vreg_192 = V_MOV_B32_e32 14, implicit $exec
418 S_NOP 0, implicit %1.sub1_sub2_sub3_sub4
420 undef %2.sub2:vreg_192 = V_MOV_B32_e32 22, implicit $exec
421 %2.sub3:vreg_192 = V_MOV_B32_e32 23, implicit $exec
422 %2.sub4:vreg_192 = V_MOV_B32_e32 24, implicit $exec
423 %2.sub5:vreg_192 = V_MOV_B32_e32 25, implicit $exec
424 S_NOP 0, implicit %2.sub2_sub3_sub4_sub5
428 name: test_vreg_192_w160
429 tracksRegLiveness: true
432 ; CHECK-LABEL: name: test_vreg_192_w160
433 ; CHECK: undef %2.sub0:vreg_160 = V_MOV_B32_e32 0, implicit $exec
434 ; CHECK-NEXT: %2.sub1:vreg_160 = V_MOV_B32_e32 1, implicit $exec
435 ; CHECK-NEXT: %2.sub2:vreg_160 = V_MOV_B32_e32 2, implicit $exec
436 ; CHECK-NEXT: %2.sub3:vreg_160 = V_MOV_B32_e32 3, implicit $exec
437 ; CHECK-NEXT: %2.sub4:vreg_160 = V_MOV_B32_e32 4, implicit $exec
438 ; CHECK-NEXT: S_NOP 0, implicit %2
439 ; CHECK-NEXT: undef %3.sub0:vreg_160 = V_MOV_B32_e32 11, implicit $exec
440 ; CHECK-NEXT: %3.sub1:vreg_160 = V_MOV_B32_e32 12, implicit $exec
441 ; CHECK-NEXT: %3.sub2:vreg_160 = V_MOV_B32_e32 13, implicit $exec
442 ; CHECK-NEXT: %3.sub3:vreg_160 = V_MOV_B32_e32 14, implicit $exec
443 ; CHECK-NEXT: %3.sub4:vreg_160 = V_MOV_B32_e32 15, implicit $exec
444 ; CHECK-NEXT: S_NOP 0, implicit %3
445 undef %0.sub0:vreg_192 = V_MOV_B32_e32 00, implicit $exec
446 %0.sub1:vreg_192 = V_MOV_B32_e32 01, implicit $exec
447 %0.sub2:vreg_192 = V_MOV_B32_e32 02, implicit $exec
448 %0.sub3:vreg_192 = V_MOV_B32_e32 03, implicit $exec
449 %0.sub4:vreg_192 = V_MOV_B32_e32 04, implicit $exec
450 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4
452 undef %1.sub1:vreg_192 = V_MOV_B32_e32 11, implicit $exec
453 %1.sub2:vreg_192 = V_MOV_B32_e32 12, implicit $exec
454 %1.sub3:vreg_192 = V_MOV_B32_e32 13, implicit $exec
455 %1.sub4:vreg_192 = V_MOV_B32_e32 14, implicit $exec
456 %1.sub5:vreg_192 = V_MOV_B32_e32 15, implicit $exec
457 S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub5
461 name: test_vreg_224_w32
462 tracksRegLiveness: true
465 ; CHECK-LABEL: name: test_vreg_224_w32
466 ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
467 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
468 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 11, implicit $exec
469 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
470 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 26, implicit $exec
471 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
472 undef %0.sub0:vreg_224 = V_MOV_B32_e32 00, implicit $exec
473 S_NOP 0, implicit %0.sub0
475 undef %1.sub1:vreg_224 = V_MOV_B32_e32 11, implicit $exec
476 S_NOP 0, implicit %1.sub1
478 undef %2.sub6:vreg_224 = V_MOV_B32_e32 26, implicit $exec
479 S_NOP 0, implicit %2.sub6
483 name: test_vreg_224_w64
484 tracksRegLiveness: true
487 ; CHECK-LABEL: name: test_vreg_224_w64
488 ; CHECK: undef %3.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
489 ; CHECK-NEXT: %3.sub1:vreg_64 = V_MOV_B32_e32 1, implicit $exec
490 ; CHECK-NEXT: S_NOP 0, implicit %3
491 ; CHECK-NEXT: undef %4.sub0:vreg_64 = V_MOV_B32_e32 11, implicit $exec
492 ; CHECK-NEXT: %4.sub1:vreg_64 = V_MOV_B32_e32 12, implicit $exec
493 ; CHECK-NEXT: S_NOP 0, implicit %4
494 ; CHECK-NEXT: undef %5.sub0:vreg_64 = V_MOV_B32_e32 25, implicit $exec
495 ; CHECK-NEXT: %5.sub1:vreg_64 = V_MOV_B32_e32 26, implicit $exec
496 ; CHECK-NEXT: S_NOP 0, implicit %5
497 undef %0.sub0:vreg_224 = V_MOV_B32_e32 00, implicit $exec
498 %0.sub1:vreg_224 = V_MOV_B32_e32 01, implicit $exec
499 S_NOP 0, implicit %0.sub0_sub1
501 undef %1.sub1:vreg_224 = V_MOV_B32_e32 11, implicit $exec
502 %1.sub2:vreg_224 = V_MOV_B32_e32 12, implicit $exec
503 S_NOP 0, implicit %1.sub1_sub2
505 undef %2.sub5:vreg_224 = V_MOV_B32_e32 25, implicit $exec
506 %2.sub6:vreg_224 = V_MOV_B32_e32 26, implicit $exec
507 S_NOP 0, implicit %2.sub5_sub6
511 name: test_vreg_224_w96
512 tracksRegLiveness: true
515 ; CHECK-LABEL: name: test_vreg_224_w96
516 ; CHECK: undef %3.sub0:vreg_96 = V_MOV_B32_e32 0, implicit $exec
517 ; CHECK-NEXT: %3.sub1:vreg_96 = V_MOV_B32_e32 1, implicit $exec
518 ; CHECK-NEXT: %3.sub2:vreg_96 = V_MOV_B32_e32 2, implicit $exec
519 ; CHECK-NEXT: S_NOP 0, implicit %3
520 ; CHECK-NEXT: undef %4.sub0:vreg_96 = V_MOV_B32_e32 11, implicit $exec
521 ; CHECK-NEXT: %4.sub1:vreg_96 = V_MOV_B32_e32 12, implicit $exec
522 ; CHECK-NEXT: %4.sub2:vreg_96 = V_MOV_B32_e32 13, implicit $exec
523 ; CHECK-NEXT: S_NOP 0, implicit %4
524 ; CHECK-NEXT: undef %5.sub0:vreg_96 = V_MOV_B32_e32 24, implicit $exec
525 ; CHECK-NEXT: %5.sub1:vreg_96 = V_MOV_B32_e32 25, implicit $exec
526 ; CHECK-NEXT: %5.sub2:vreg_96 = V_MOV_B32_e32 26, implicit $exec
527 ; CHECK-NEXT: S_NOP 0, implicit %5
528 undef %0.sub0:vreg_224 = V_MOV_B32_e32 00, implicit $exec
529 %0.sub1:vreg_224 = V_MOV_B32_e32 01, implicit $exec
530 %0.sub2:vreg_224 = V_MOV_B32_e32 02, implicit $exec
531 S_NOP 0, implicit %0.sub0_sub1_sub2
533 undef %1.sub1:vreg_224 = V_MOV_B32_e32 11, implicit $exec
534 %1.sub2:vreg_224 = V_MOV_B32_e32 12, implicit $exec
535 %1.sub3:vreg_224 = V_MOV_B32_e32 13, implicit $exec
536 S_NOP 0, implicit %1.sub1_sub2_sub3
538 undef %2.sub4:vreg_224 = V_MOV_B32_e32 24, implicit $exec
539 %2.sub5:vreg_224 = V_MOV_B32_e32 25, implicit $exec
540 %2.sub6:vreg_224 = V_MOV_B32_e32 26, implicit $exec
541 S_NOP 0, implicit %2.sub4_sub5_sub6
545 name: test_vreg_224_w128
546 tracksRegLiveness: true
549 ; CHECK-LABEL: name: test_vreg_224_w128
550 ; CHECK: undef %3.sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec
551 ; CHECK-NEXT: %3.sub1:vreg_128 = V_MOV_B32_e32 1, implicit $exec
552 ; CHECK-NEXT: %3.sub2:vreg_128 = V_MOV_B32_e32 2, implicit $exec
553 ; CHECK-NEXT: %3.sub3:vreg_128 = V_MOV_B32_e32 3, implicit $exec
554 ; CHECK-NEXT: S_NOP 0, implicit %3
555 ; CHECK-NEXT: undef %4.sub0:vreg_128 = V_MOV_B32_e32 11, implicit $exec
556 ; CHECK-NEXT: %4.sub1:vreg_128 = V_MOV_B32_e32 12, implicit $exec
557 ; CHECK-NEXT: %4.sub2:vreg_128 = V_MOV_B32_e32 13, implicit $exec
558 ; CHECK-NEXT: %4.sub3:vreg_128 = V_MOV_B32_e32 14, implicit $exec
559 ; CHECK-NEXT: S_NOP 0, implicit %4
560 ; CHECK-NEXT: undef %5.sub0:vreg_128 = V_MOV_B32_e32 23, implicit $exec
561 ; CHECK-NEXT: %5.sub1:vreg_128 = V_MOV_B32_e32 24, implicit $exec
562 ; CHECK-NEXT: %5.sub2:vreg_128 = V_MOV_B32_e32 25, implicit $exec
563 ; CHECK-NEXT: %5.sub3:vreg_128 = V_MOV_B32_e32 26, implicit $exec
564 ; CHECK-NEXT: S_NOP 0, implicit %5
565 undef %0.sub0:vreg_224 = V_MOV_B32_e32 00, implicit $exec
566 %0.sub1:vreg_224 = V_MOV_B32_e32 01, implicit $exec
567 %0.sub2:vreg_224 = V_MOV_B32_e32 02, implicit $exec
568 %0.sub3:vreg_224 = V_MOV_B32_e32 03, implicit $exec
569 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3
571 undef %1.sub1:vreg_224 = V_MOV_B32_e32 11, implicit $exec
572 %1.sub2:vreg_224 = V_MOV_B32_e32 12, implicit $exec
573 %1.sub3:vreg_224 = V_MOV_B32_e32 13, implicit $exec
574 %1.sub4:vreg_224 = V_MOV_B32_e32 14, implicit $exec
575 S_NOP 0, implicit %1.sub1_sub2_sub3_sub4
577 undef %2.sub3:vreg_224 = V_MOV_B32_e32 23, implicit $exec
578 %2.sub4:vreg_224 = V_MOV_B32_e32 24, implicit $exec
579 %2.sub5:vreg_224 = V_MOV_B32_e32 25, implicit $exec
580 %2.sub6:vreg_224 = V_MOV_B32_e32 26, implicit $exec
581 S_NOP 0, implicit %2.sub3_sub4_sub5_sub6
585 name: test_vreg_224_w160
586 tracksRegLiveness: true
589 ; CHECK-LABEL: name: test_vreg_224_w160
590 ; CHECK: undef %3.sub0:vreg_160 = V_MOV_B32_e32 0, implicit $exec
591 ; CHECK-NEXT: %3.sub1:vreg_160 = V_MOV_B32_e32 1, implicit $exec
592 ; CHECK-NEXT: %3.sub2:vreg_160 = V_MOV_B32_e32 2, implicit $exec
593 ; CHECK-NEXT: %3.sub3:vreg_160 = V_MOV_B32_e32 3, implicit $exec
594 ; CHECK-NEXT: %3.sub4:vreg_160 = V_MOV_B32_e32 4, implicit $exec
595 ; CHECK-NEXT: S_NOP 0, implicit %3
596 ; CHECK-NEXT: undef %4.sub0:vreg_160 = V_MOV_B32_e32 11, implicit $exec
597 ; CHECK-NEXT: %4.sub1:vreg_160 = V_MOV_B32_e32 12, implicit $exec
598 ; CHECK-NEXT: %4.sub2:vreg_160 = V_MOV_B32_e32 13, implicit $exec
599 ; CHECK-NEXT: %4.sub3:vreg_160 = V_MOV_B32_e32 14, implicit $exec
600 ; CHECK-NEXT: %4.sub4:vreg_160 = V_MOV_B32_e32 15, implicit $exec
601 ; CHECK-NEXT: S_NOP 0, implicit %4
602 ; CHECK-NEXT: undef %5.sub0:vreg_160 = V_MOV_B32_e32 22, implicit $exec
603 ; CHECK-NEXT: %5.sub1:vreg_160 = V_MOV_B32_e32 23, implicit $exec
604 ; CHECK-NEXT: %5.sub2:vreg_160 = V_MOV_B32_e32 24, implicit $exec
605 ; CHECK-NEXT: %5.sub3:vreg_160 = V_MOV_B32_e32 25, implicit $exec
606 ; CHECK-NEXT: %5.sub4:vreg_160 = V_MOV_B32_e32 26, implicit $exec
607 ; CHECK-NEXT: S_NOP 0, implicit %5
608 undef %0.sub0:vreg_224 = V_MOV_B32_e32 00, implicit $exec
609 %0.sub1:vreg_224 = V_MOV_B32_e32 01, implicit $exec
610 %0.sub2:vreg_224 = V_MOV_B32_e32 02, implicit $exec
611 %0.sub3:vreg_224 = V_MOV_B32_e32 03, implicit $exec
612 %0.sub4:vreg_224 = V_MOV_B32_e32 04, implicit $exec
613 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4
615 undef %1.sub1:vreg_224 = V_MOV_B32_e32 11, implicit $exec
616 %1.sub2:vreg_224 = V_MOV_B32_e32 12, implicit $exec
617 %1.sub3:vreg_224 = V_MOV_B32_e32 13, implicit $exec
618 %1.sub4:vreg_224 = V_MOV_B32_e32 14, implicit $exec
619 %1.sub5:vreg_224 = V_MOV_B32_e32 15, implicit $exec
620 S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub5
622 undef %2.sub2:vreg_224 = V_MOV_B32_e32 22, implicit $exec
623 %2.sub3:vreg_224 = V_MOV_B32_e32 23, implicit $exec
624 %2.sub4:vreg_224 = V_MOV_B32_e32 24, implicit $exec
625 %2.sub5:vreg_224 = V_MOV_B32_e32 25, implicit $exec
626 %2.sub6:vreg_224 = V_MOV_B32_e32 26, implicit $exec
627 S_NOP 0, implicit %2.sub2_sub3_sub4_sub5_sub6
631 name: test_vreg_224_w192
632 tracksRegLiveness: true
635 ; CHECK-LABEL: name: test_vreg_224_w192
636 ; CHECK: undef %2.sub0:vreg_192 = V_MOV_B32_e32 0, implicit $exec
637 ; CHECK-NEXT: %2.sub1:vreg_192 = V_MOV_B32_e32 1, implicit $exec
638 ; CHECK-NEXT: %2.sub2:vreg_192 = V_MOV_B32_e32 2, implicit $exec
639 ; CHECK-NEXT: %2.sub3:vreg_192 = V_MOV_B32_e32 3, implicit $exec
640 ; CHECK-NEXT: %2.sub4:vreg_192 = V_MOV_B32_e32 4, implicit $exec
641 ; CHECK-NEXT: %2.sub5:vreg_192 = V_MOV_B32_e32 5, implicit $exec
642 ; CHECK-NEXT: S_NOP 0, implicit %2
643 ; CHECK-NEXT: undef %3.sub0:vreg_192 = V_MOV_B32_e32 11, implicit $exec
644 ; CHECK-NEXT: %3.sub1:vreg_192 = V_MOV_B32_e32 12, implicit $exec
645 ; CHECK-NEXT: %3.sub2:vreg_192 = V_MOV_B32_e32 13, implicit $exec
646 ; CHECK-NEXT: %3.sub3:vreg_192 = V_MOV_B32_e32 14, implicit $exec
647 ; CHECK-NEXT: %3.sub4:vreg_192 = V_MOV_B32_e32 15, implicit $exec
648 ; CHECK-NEXT: %3.sub5:vreg_192 = V_MOV_B32_e32 16, implicit $exec
649 ; CHECK-NEXT: S_NOP 0, implicit %3
650 undef %0.sub0:vreg_224 = V_MOV_B32_e32 00, implicit $exec
651 %0.sub1:vreg_224 = V_MOV_B32_e32 01, implicit $exec
652 %0.sub2:vreg_224 = V_MOV_B32_e32 02, implicit $exec
653 %0.sub3:vreg_224 = V_MOV_B32_e32 03, implicit $exec
654 %0.sub4:vreg_224 = V_MOV_B32_e32 04, implicit $exec
655 %0.sub5:vreg_224 = V_MOV_B32_e32 05, implicit $exec
656 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5
658 undef %1.sub1:vreg_224 = V_MOV_B32_e32 11, implicit $exec
659 %1.sub2:vreg_224 = V_MOV_B32_e32 12, implicit $exec
660 %1.sub3:vreg_224 = V_MOV_B32_e32 13, implicit $exec
661 %1.sub4:vreg_224 = V_MOV_B32_e32 14, implicit $exec
662 %1.sub5:vreg_224 = V_MOV_B32_e32 15, implicit $exec
663 %1.sub6:vreg_224 = V_MOV_B32_e32 16, implicit $exec
664 S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub5_sub6
668 name: test_vreg_256_w32
669 tracksRegLiveness: true
672 ; CHECK-LABEL: name: test_vreg_256_w32
673 ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
674 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
675 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 11, implicit $exec
676 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
677 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 27, implicit $exec
678 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
679 undef %0.sub0:vreg_256 = V_MOV_B32_e32 00, implicit $exec
680 S_NOP 0, implicit %0.sub0
682 undef %1.sub1:vreg_256 = V_MOV_B32_e32 11, implicit $exec
683 S_NOP 0, implicit %1.sub1
685 undef %2.sub7:vreg_256 = V_MOV_B32_e32 27, implicit $exec
686 S_NOP 0, implicit %2.sub7
690 name: test_vreg_256_w64
691 tracksRegLiveness: true
694 ; CHECK-LABEL: name: test_vreg_256_w64
695 ; CHECK: undef %3.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
696 ; CHECK-NEXT: %3.sub1:vreg_64 = V_MOV_B32_e32 1, implicit $exec
697 ; CHECK-NEXT: S_NOP 0, implicit %3
698 ; CHECK-NEXT: undef %4.sub0:vreg_64 = V_MOV_B32_e32 11, implicit $exec
699 ; CHECK-NEXT: %4.sub1:vreg_64 = V_MOV_B32_e32 12, implicit $exec
700 ; CHECK-NEXT: S_NOP 0, implicit %4
701 ; CHECK-NEXT: undef %5.sub0:vreg_64 = V_MOV_B32_e32 26, implicit $exec
702 ; CHECK-NEXT: %5.sub1:vreg_64 = V_MOV_B32_e32 27, implicit $exec
703 ; CHECK-NEXT: S_NOP 0, implicit %5
704 undef %0.sub0:vreg_256 = V_MOV_B32_e32 00, implicit $exec
705 %0.sub1:vreg_256 = V_MOV_B32_e32 01, implicit $exec
706 S_NOP 0, implicit %0.sub0_sub1
708 undef %1.sub1:vreg_256 = V_MOV_B32_e32 11, implicit $exec
709 %1.sub2:vreg_256 = V_MOV_B32_e32 12, implicit $exec
710 S_NOP 0, implicit %1.sub1_sub2
712 undef %2.sub6:vreg_256 = V_MOV_B32_e32 26, implicit $exec
713 %2.sub7:vreg_256 = V_MOV_B32_e32 27, implicit $exec
714 S_NOP 0, implicit %2.sub6_sub7
718 name: test_vreg_256_w96
719 tracksRegLiveness: true
722 ; CHECK-LABEL: name: test_vreg_256_w96
723 ; CHECK: undef %3.sub0:vreg_96 = V_MOV_B32_e32 0, implicit $exec
724 ; CHECK-NEXT: %3.sub1:vreg_96 = V_MOV_B32_e32 1, implicit $exec
725 ; CHECK-NEXT: %3.sub2:vreg_96 = V_MOV_B32_e32 2, implicit $exec
726 ; CHECK-NEXT: S_NOP 0, implicit %3
727 ; CHECK-NEXT: undef %4.sub0:vreg_96 = V_MOV_B32_e32 11, implicit $exec
728 ; CHECK-NEXT: %4.sub1:vreg_96 = V_MOV_B32_e32 12, implicit $exec
729 ; CHECK-NEXT: %4.sub2:vreg_96 = V_MOV_B32_e32 13, implicit $exec
730 ; CHECK-NEXT: S_NOP 0, implicit %4
731 ; CHECK-NEXT: undef %5.sub0:vreg_96 = V_MOV_B32_e32 25, implicit $exec
732 ; CHECK-NEXT: %5.sub1:vreg_96 = V_MOV_B32_e32 26, implicit $exec
733 ; CHECK-NEXT: %5.sub2:vreg_96 = V_MOV_B32_e32 27, implicit $exec
734 ; CHECK-NEXT: S_NOP 0, implicit %5
735 undef %0.sub0:vreg_256 = V_MOV_B32_e32 00, implicit $exec
736 %0.sub1:vreg_256 = V_MOV_B32_e32 01, implicit $exec
737 %0.sub2:vreg_256 = V_MOV_B32_e32 02, implicit $exec
738 S_NOP 0, implicit %0.sub0_sub1_sub2
740 undef %1.sub1:vreg_256 = V_MOV_B32_e32 11, implicit $exec
741 %1.sub2:vreg_256 = V_MOV_B32_e32 12, implicit $exec
742 %1.sub3:vreg_256 = V_MOV_B32_e32 13, implicit $exec
743 S_NOP 0, implicit %1.sub1_sub2_sub3
745 undef %2.sub5:vreg_256 = V_MOV_B32_e32 25, implicit $exec
746 %2.sub6:vreg_256 = V_MOV_B32_e32 26, implicit $exec
747 %2.sub7:vreg_256 = V_MOV_B32_e32 27, implicit $exec
748 S_NOP 0, implicit %2.sub5_sub6_sub7
752 name: test_vreg_256_w128
753 tracksRegLiveness: true
756 ; CHECK-LABEL: name: test_vreg_256_w128
757 ; CHECK: undef %3.sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec
758 ; CHECK-NEXT: %3.sub1:vreg_128 = V_MOV_B32_e32 1, implicit $exec
759 ; CHECK-NEXT: %3.sub2:vreg_128 = V_MOV_B32_e32 2, implicit $exec
760 ; CHECK-NEXT: %3.sub3:vreg_128 = V_MOV_B32_e32 3, implicit $exec
761 ; CHECK-NEXT: S_NOP 0, implicit %3
762 ; CHECK-NEXT: undef %4.sub0:vreg_128 = V_MOV_B32_e32 11, implicit $exec
763 ; CHECK-NEXT: %4.sub1:vreg_128 = V_MOV_B32_e32 12, implicit $exec
764 ; CHECK-NEXT: %4.sub2:vreg_128 = V_MOV_B32_e32 13, implicit $exec
765 ; CHECK-NEXT: %4.sub3:vreg_128 = V_MOV_B32_e32 14, implicit $exec
766 ; CHECK-NEXT: S_NOP 0, implicit %4
767 ; CHECK-NEXT: undef %5.sub0:vreg_128 = V_MOV_B32_e32 24, implicit $exec
768 ; CHECK-NEXT: %5.sub1:vreg_128 = V_MOV_B32_e32 25, implicit $exec
769 ; CHECK-NEXT: %5.sub2:vreg_128 = V_MOV_B32_e32 26, implicit $exec
770 ; CHECK-NEXT: %5.sub3:vreg_128 = V_MOV_B32_e32 27, implicit $exec
771 ; CHECK-NEXT: S_NOP 0, implicit %5
772 undef %0.sub0:vreg_256 = V_MOV_B32_e32 00, implicit $exec
773 %0.sub1:vreg_256 = V_MOV_B32_e32 01, implicit $exec
774 %0.sub2:vreg_256 = V_MOV_B32_e32 02, implicit $exec
775 %0.sub3:vreg_256 = V_MOV_B32_e32 03, implicit $exec
776 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3
778 undef %1.sub1:vreg_256 = V_MOV_B32_e32 11, implicit $exec
779 %1.sub2:vreg_256 = V_MOV_B32_e32 12, implicit $exec
780 %1.sub3:vreg_256 = V_MOV_B32_e32 13, implicit $exec
781 %1.sub4:vreg_256 = V_MOV_B32_e32 14, implicit $exec
782 S_NOP 0, implicit %1.sub1_sub2_sub3_sub4
784 undef %2.sub4:vreg_256 = V_MOV_B32_e32 24, implicit $exec
785 %2.sub5:vreg_256 = V_MOV_B32_e32 25, implicit $exec
786 %2.sub6:vreg_256 = V_MOV_B32_e32 26, implicit $exec
787 %2.sub7:vreg_256 = V_MOV_B32_e32 27, implicit $exec
788 S_NOP 0, implicit %2.sub4_sub5_sub6_sub7
792 name: test_vreg_256_w160
793 tracksRegLiveness: true
796 ; CHECK-LABEL: name: test_vreg_256_w160
797 ; CHECK: undef %3.sub0:vreg_160 = V_MOV_B32_e32 0, implicit $exec
798 ; CHECK-NEXT: %3.sub1:vreg_160 = V_MOV_B32_e32 1, implicit $exec
799 ; CHECK-NEXT: %3.sub2:vreg_160 = V_MOV_B32_e32 2, implicit $exec
800 ; CHECK-NEXT: %3.sub3:vreg_160 = V_MOV_B32_e32 3, implicit $exec
801 ; CHECK-NEXT: %3.sub4:vreg_160 = V_MOV_B32_e32 4, implicit $exec
802 ; CHECK-NEXT: S_NOP 0, implicit %3
803 ; CHECK-NEXT: undef %4.sub0:vreg_160 = V_MOV_B32_e32 11, implicit $exec
804 ; CHECK-NEXT: %4.sub1:vreg_160 = V_MOV_B32_e32 12, implicit $exec
805 ; CHECK-NEXT: %4.sub2:vreg_160 = V_MOV_B32_e32 13, implicit $exec
806 ; CHECK-NEXT: %4.sub3:vreg_160 = V_MOV_B32_e32 14, implicit $exec
807 ; CHECK-NEXT: %4.sub4:vreg_160 = V_MOV_B32_e32 15, implicit $exec
808 ; CHECK-NEXT: S_NOP 0, implicit %4
809 ; CHECK-NEXT: undef %5.sub0:vreg_160 = V_MOV_B32_e32 23, implicit $exec
810 ; CHECK-NEXT: %5.sub1:vreg_160 = V_MOV_B32_e32 24, implicit $exec
811 ; CHECK-NEXT: %5.sub2:vreg_160 = V_MOV_B32_e32 25, implicit $exec
812 ; CHECK-NEXT: %5.sub3:vreg_160 = V_MOV_B32_e32 26, implicit $exec
813 ; CHECK-NEXT: %5.sub4:vreg_160 = V_MOV_B32_e32 27, implicit $exec
814 ; CHECK-NEXT: S_NOP 0, implicit %5
815 undef %0.sub0:vreg_256 = V_MOV_B32_e32 00, implicit $exec
816 %0.sub1:vreg_256 = V_MOV_B32_e32 01, implicit $exec
817 %0.sub2:vreg_256 = V_MOV_B32_e32 02, implicit $exec
818 %0.sub3:vreg_256 = V_MOV_B32_e32 03, implicit $exec
819 %0.sub4:vreg_256 = V_MOV_B32_e32 04, implicit $exec
820 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4
822 undef %1.sub1:vreg_256 = V_MOV_B32_e32 11, implicit $exec
823 %1.sub2:vreg_256 = V_MOV_B32_e32 12, implicit $exec
824 %1.sub3:vreg_256 = V_MOV_B32_e32 13, implicit $exec
825 %1.sub4:vreg_256 = V_MOV_B32_e32 14, implicit $exec
826 %1.sub5:vreg_256 = V_MOV_B32_e32 15, implicit $exec
827 S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub5
829 undef %2.sub3:vreg_256 = V_MOV_B32_e32 23, implicit $exec
830 %2.sub4:vreg_256 = V_MOV_B32_e32 24, implicit $exec
831 %2.sub5:vreg_256 = V_MOV_B32_e32 25, implicit $exec
832 %2.sub6:vreg_256 = V_MOV_B32_e32 26, implicit $exec
833 %2.sub7:vreg_256 = V_MOV_B32_e32 27, implicit $exec
834 S_NOP 0, implicit %2.sub3_sub4_sub5_sub6_sub7
838 name: test_vreg_256_w192
839 tracksRegLiveness: true
842 ; CHECK-LABEL: name: test_vreg_256_w192
843 ; CHECK: undef %3.sub0:vreg_192 = V_MOV_B32_e32 0, implicit $exec
844 ; CHECK-NEXT: %3.sub1:vreg_192 = V_MOV_B32_e32 1, implicit $exec
845 ; CHECK-NEXT: %3.sub2:vreg_192 = V_MOV_B32_e32 2, implicit $exec
846 ; CHECK-NEXT: %3.sub3:vreg_192 = V_MOV_B32_e32 3, implicit $exec
847 ; CHECK-NEXT: %3.sub4:vreg_192 = V_MOV_B32_e32 4, implicit $exec
848 ; CHECK-NEXT: %3.sub5:vreg_192 = V_MOV_B32_e32 5, implicit $exec
849 ; CHECK-NEXT: S_NOP 0, implicit %3
850 ; CHECK-NEXT: undef %4.sub0:vreg_192 = V_MOV_B32_e32 11, implicit $exec
851 ; CHECK-NEXT: %4.sub1:vreg_192 = V_MOV_B32_e32 12, implicit $exec
852 ; CHECK-NEXT: %4.sub2:vreg_192 = V_MOV_B32_e32 13, implicit $exec
853 ; CHECK-NEXT: %4.sub3:vreg_192 = V_MOV_B32_e32 14, implicit $exec
854 ; CHECK-NEXT: %4.sub4:vreg_192 = V_MOV_B32_e32 15, implicit $exec
855 ; CHECK-NEXT: %4.sub5:vreg_192 = V_MOV_B32_e32 16, implicit $exec
856 ; CHECK-NEXT: S_NOP 0, implicit %4
857 ; CHECK-NEXT: undef %5.sub0:vreg_192 = V_MOV_B32_e32 22, implicit $exec
858 ; CHECK-NEXT: %5.sub1:vreg_192 = V_MOV_B32_e32 23, implicit $exec
859 ; CHECK-NEXT: %5.sub2:vreg_192 = V_MOV_B32_e32 24, implicit $exec
860 ; CHECK-NEXT: %5.sub3:vreg_192 = V_MOV_B32_e32 25, implicit $exec
861 ; CHECK-NEXT: %5.sub4:vreg_192 = V_MOV_B32_e32 26, implicit $exec
862 ; CHECK-NEXT: %5.sub5:vreg_192 = V_MOV_B32_e32 27, implicit $exec
863 ; CHECK-NEXT: S_NOP 0, implicit %5
864 undef %0.sub0:vreg_256 = V_MOV_B32_e32 00, implicit $exec
865 %0.sub1:vreg_256 = V_MOV_B32_e32 01, implicit $exec
866 %0.sub2:vreg_256 = V_MOV_B32_e32 02, implicit $exec
867 %0.sub3:vreg_256 = V_MOV_B32_e32 03, implicit $exec
868 %0.sub4:vreg_256 = V_MOV_B32_e32 04, implicit $exec
869 %0.sub5:vreg_256 = V_MOV_B32_e32 05, implicit $exec
870 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5
872 undef %1.sub1:vreg_256 = V_MOV_B32_e32 11, implicit $exec
873 %1.sub2:vreg_256 = V_MOV_B32_e32 12, implicit $exec
874 %1.sub3:vreg_256 = V_MOV_B32_e32 13, implicit $exec
875 %1.sub4:vreg_256 = V_MOV_B32_e32 14, implicit $exec
876 %1.sub5:vreg_256 = V_MOV_B32_e32 15, implicit $exec
877 %1.sub6:vreg_256 = V_MOV_B32_e32 16, implicit $exec
878 S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub5_sub6
880 undef %2.sub2:vreg_256 = V_MOV_B32_e32 22, implicit $exec
881 %2.sub3:vreg_256 = V_MOV_B32_e32 23, implicit $exec
882 %2.sub4:vreg_256 = V_MOV_B32_e32 24, implicit $exec
883 %2.sub5:vreg_256 = V_MOV_B32_e32 25, implicit $exec
884 %2.sub6:vreg_256 = V_MOV_B32_e32 26, implicit $exec
885 %2.sub7:vreg_256 = V_MOV_B32_e32 27, implicit $exec
886 S_NOP 0, implicit %2.sub2_sub3_sub4_sub5_sub6_sub7
890 name: test_vreg_288_w32
891 tracksRegLiveness: true
894 ; CHECK-LABEL: name: test_vreg_288_w32
895 ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
896 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
897 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 11, implicit $exec
898 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
899 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 28, implicit $exec
900 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
901 undef %0.sub0:vreg_288 = V_MOV_B32_e32 00, implicit $exec
902 S_NOP 0, implicit %0.sub0
904 undef %1.sub1:vreg_288 = V_MOV_B32_e32 11, implicit $exec
905 S_NOP 0, implicit %1.sub1
907 undef %2.sub8:vreg_288 = V_MOV_B32_e32 28, implicit $exec
908 S_NOP 0, implicit %2.sub8
912 name: test_vreg_288_w64
913 tracksRegLiveness: true
916 ; CHECK-LABEL: name: test_vreg_288_w64
917 ; CHECK: undef %3.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
918 ; CHECK-NEXT: %3.sub1:vreg_64 = V_MOV_B32_e32 1, implicit $exec
919 ; CHECK-NEXT: S_NOP 0, implicit %3
920 ; CHECK-NEXT: undef %4.sub0:vreg_64 = V_MOV_B32_e32 11, implicit $exec
921 ; CHECK-NEXT: %4.sub1:vreg_64 = V_MOV_B32_e32 12, implicit $exec
922 ; CHECK-NEXT: S_NOP 0, implicit %4
923 ; CHECK-NEXT: undef %5.sub0:vreg_64 = V_MOV_B32_e32 27, implicit $exec
924 ; CHECK-NEXT: %5.sub1:vreg_64 = V_MOV_B32_e32 28, implicit $exec
925 ; CHECK-NEXT: S_NOP 0, implicit %5
926 undef %0.sub0:vreg_288 = V_MOV_B32_e32 00, implicit $exec
927 %0.sub1:vreg_288 = V_MOV_B32_e32 01, implicit $exec
928 S_NOP 0, implicit %0.sub0_sub1
930 undef %1.sub1:vreg_288 = V_MOV_B32_e32 11, implicit $exec
931 %1.sub2:vreg_288 = V_MOV_B32_e32 12, implicit $exec
932 S_NOP 0, implicit %1.sub1_sub2
934 undef %2.sub7:vreg_288 = V_MOV_B32_e32 27, implicit $exec
935 %2.sub8:vreg_288 = V_MOV_B32_e32 28, implicit $exec
936 S_NOP 0, implicit %2.sub7_sub8
940 name: test_vreg_288_w96
941 tracksRegLiveness: true
944 ; CHECK-LABEL: name: test_vreg_288_w96
945 ; CHECK: undef %3.sub0:vreg_96 = V_MOV_B32_e32 0, implicit $exec
946 ; CHECK-NEXT: %3.sub1:vreg_96 = V_MOV_B32_e32 1, implicit $exec
947 ; CHECK-NEXT: %3.sub2:vreg_96 = V_MOV_B32_e32 2, implicit $exec
948 ; CHECK-NEXT: S_NOP 0, implicit %3
949 ; CHECK-NEXT: undef %4.sub0:vreg_96 = V_MOV_B32_e32 11, implicit $exec
950 ; CHECK-NEXT: %4.sub1:vreg_96 = V_MOV_B32_e32 12, implicit $exec
951 ; CHECK-NEXT: %4.sub2:vreg_96 = V_MOV_B32_e32 13, implicit $exec
952 ; CHECK-NEXT: S_NOP 0, implicit %4
953 ; CHECK-NEXT: undef %5.sub0:vreg_96 = V_MOV_B32_e32 26, implicit $exec
954 ; CHECK-NEXT: %5.sub1:vreg_96 = V_MOV_B32_e32 27, implicit $exec
955 ; CHECK-NEXT: %5.sub2:vreg_96 = V_MOV_B32_e32 28, implicit $exec
956 ; CHECK-NEXT: S_NOP 0, implicit %5
957 undef %0.sub0:vreg_288 = V_MOV_B32_e32 00, implicit $exec
958 %0.sub1:vreg_288 = V_MOV_B32_e32 01, implicit $exec
959 %0.sub2:vreg_288 = V_MOV_B32_e32 02, implicit $exec
960 S_NOP 0, implicit %0.sub0_sub1_sub2
962 undef %1.sub1:vreg_288 = V_MOV_B32_e32 11, implicit $exec
963 %1.sub2:vreg_288 = V_MOV_B32_e32 12, implicit $exec
964 %1.sub3:vreg_288 = V_MOV_B32_e32 13, implicit $exec
965 S_NOP 0, implicit %1.sub1_sub2_sub3
967 undef %2.sub6:vreg_288 = V_MOV_B32_e32 26, implicit $exec
968 %2.sub7:vreg_288 = V_MOV_B32_e32 27, implicit $exec
969 %2.sub8:vreg_288 = V_MOV_B32_e32 28, implicit $exec
970 S_NOP 0, implicit %2.sub6_sub7_sub8
974 name: test_vreg_288_w128
975 tracksRegLiveness: true
978 ; CHECK-LABEL: name: test_vreg_288_w128
979 ; CHECK: undef %3.sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec
980 ; CHECK-NEXT: %3.sub1:vreg_128 = V_MOV_B32_e32 1, implicit $exec
981 ; CHECK-NEXT: %3.sub2:vreg_128 = V_MOV_B32_e32 2, implicit $exec
982 ; CHECK-NEXT: %3.sub3:vreg_128 = V_MOV_B32_e32 3, implicit $exec
983 ; CHECK-NEXT: S_NOP 0, implicit %3
984 ; CHECK-NEXT: undef %4.sub0:vreg_128 = V_MOV_B32_e32 11, implicit $exec
985 ; CHECK-NEXT: %4.sub1:vreg_128 = V_MOV_B32_e32 12, implicit $exec
986 ; CHECK-NEXT: %4.sub2:vreg_128 = V_MOV_B32_e32 13, implicit $exec
987 ; CHECK-NEXT: %4.sub3:vreg_128 = V_MOV_B32_e32 14, implicit $exec
988 ; CHECK-NEXT: S_NOP 0, implicit %4
989 ; CHECK-NEXT: undef %5.sub0:vreg_128 = V_MOV_B32_e32 25, implicit $exec
990 ; CHECK-NEXT: %5.sub1:vreg_128 = V_MOV_B32_e32 26, implicit $exec
991 ; CHECK-NEXT: %5.sub2:vreg_128 = V_MOV_B32_e32 27, implicit $exec
992 ; CHECK-NEXT: %5.sub3:vreg_128 = V_MOV_B32_e32 28, implicit $exec
993 ; CHECK-NEXT: S_NOP 0, implicit %5
994 undef %0.sub0:vreg_288 = V_MOV_B32_e32 00, implicit $exec
995 %0.sub1:vreg_288 = V_MOV_B32_e32 01, implicit $exec
996 %0.sub2:vreg_288 = V_MOV_B32_e32 02, implicit $exec
997 %0.sub3:vreg_288 = V_MOV_B32_e32 03, implicit $exec
998 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3
1000 undef %1.sub1:vreg_288 = V_MOV_B32_e32 11, implicit $exec
1001 %1.sub2:vreg_288 = V_MOV_B32_e32 12, implicit $exec
1002 %1.sub3:vreg_288 = V_MOV_B32_e32 13, implicit $exec
1003 %1.sub4:vreg_288 = V_MOV_B32_e32 14, implicit $exec
1004 S_NOP 0, implicit %1.sub1_sub2_sub3_sub4
1006 undef %2.sub5:vreg_288 = V_MOV_B32_e32 25, implicit $exec
1007 %2.sub6:vreg_288 = V_MOV_B32_e32 26, implicit $exec
1008 %2.sub7:vreg_288 = V_MOV_B32_e32 27, implicit $exec
1009 %2.sub8:vreg_288 = V_MOV_B32_e32 28, implicit $exec
1010 S_NOP 0, implicit %2.sub5_sub6_sub7_sub8
1014 name: test_vreg_288_w160
1015 tracksRegLiveness: true
1018 ; CHECK-LABEL: name: test_vreg_288_w160
1019 ; CHECK: undef %3.sub0:vreg_160 = V_MOV_B32_e32 0, implicit $exec
1020 ; CHECK-NEXT: %3.sub1:vreg_160 = V_MOV_B32_e32 1, implicit $exec
1021 ; CHECK-NEXT: %3.sub2:vreg_160 = V_MOV_B32_e32 2, implicit $exec
1022 ; CHECK-NEXT: %3.sub3:vreg_160 = V_MOV_B32_e32 3, implicit $exec
1023 ; CHECK-NEXT: %3.sub4:vreg_160 = V_MOV_B32_e32 4, implicit $exec
1024 ; CHECK-NEXT: S_NOP 0, implicit %3
1025 ; CHECK-NEXT: undef %4.sub0:vreg_160 = V_MOV_B32_e32 11, implicit $exec
1026 ; CHECK-NEXT: %4.sub1:vreg_160 = V_MOV_B32_e32 12, implicit $exec
1027 ; CHECK-NEXT: %4.sub2:vreg_160 = V_MOV_B32_e32 13, implicit $exec
1028 ; CHECK-NEXT: %4.sub3:vreg_160 = V_MOV_B32_e32 14, implicit $exec
1029 ; CHECK-NEXT: %4.sub4:vreg_160 = V_MOV_B32_e32 15, implicit $exec
1030 ; CHECK-NEXT: S_NOP 0, implicit %4
1031 ; CHECK-NEXT: undef %5.sub0:vreg_160 = V_MOV_B32_e32 24, implicit $exec
1032 ; CHECK-NEXT: %5.sub1:vreg_160 = V_MOV_B32_e32 25, implicit $exec
1033 ; CHECK-NEXT: %5.sub2:vreg_160 = V_MOV_B32_e32 26, implicit $exec
1034 ; CHECK-NEXT: %5.sub3:vreg_160 = V_MOV_B32_e32 27, implicit $exec
1035 ; CHECK-NEXT: %5.sub4:vreg_160 = V_MOV_B32_e32 28, implicit $exec
1036 ; CHECK-NEXT: S_NOP 0, implicit %5
1037 undef %0.sub0:vreg_288 = V_MOV_B32_e32 00, implicit $exec
1038 %0.sub1:vreg_288 = V_MOV_B32_e32 01, implicit $exec
1039 %0.sub2:vreg_288 = V_MOV_B32_e32 02, implicit $exec
1040 %0.sub3:vreg_288 = V_MOV_B32_e32 03, implicit $exec
1041 %0.sub4:vreg_288 = V_MOV_B32_e32 04, implicit $exec
1042 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4
1044 undef %1.sub1:vreg_288 = V_MOV_B32_e32 11, implicit $exec
1045 %1.sub2:vreg_288 = V_MOV_B32_e32 12, implicit $exec
1046 %1.sub3:vreg_288 = V_MOV_B32_e32 13, implicit $exec
1047 %1.sub4:vreg_288 = V_MOV_B32_e32 14, implicit $exec
1048 %1.sub5:vreg_288 = V_MOV_B32_e32 15, implicit $exec
1049 S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub5
1051 undef %2.sub4:vreg_288 = V_MOV_B32_e32 24, implicit $exec
1052 %2.sub5:vreg_288 = V_MOV_B32_e32 25, implicit $exec
1053 %2.sub6:vreg_288 = V_MOV_B32_e32 26, implicit $exec
1054 %2.sub7:vreg_288 = V_MOV_B32_e32 27, implicit $exec
1055 %2.sub8:vreg_288 = V_MOV_B32_e32 28, implicit $exec
1056 S_NOP 0, implicit %2.sub4_sub5_sub6_sub7_sub8
1060 name: test_vreg_288_w192
1061 tracksRegLiveness: true
1064 ; CHECK-LABEL: name: test_vreg_288_w192
1065 ; CHECK: undef %3.sub0:vreg_192 = V_MOV_B32_e32 0, implicit $exec
1066 ; CHECK-NEXT: %3.sub1:vreg_192 = V_MOV_B32_e32 1, implicit $exec
1067 ; CHECK-NEXT: %3.sub2:vreg_192 = V_MOV_B32_e32 2, implicit $exec
1068 ; CHECK-NEXT: %3.sub3:vreg_192 = V_MOV_B32_e32 3, implicit $exec
1069 ; CHECK-NEXT: %3.sub4:vreg_192 = V_MOV_B32_e32 4, implicit $exec
1070 ; CHECK-NEXT: %3.sub5:vreg_192 = V_MOV_B32_e32 5, implicit $exec
1071 ; CHECK-NEXT: S_NOP 0, implicit %3
1072 ; CHECK-NEXT: undef %4.sub0:vreg_192 = V_MOV_B32_e32 11, implicit $exec
1073 ; CHECK-NEXT: %4.sub1:vreg_192 = V_MOV_B32_e32 12, implicit $exec
1074 ; CHECK-NEXT: %4.sub2:vreg_192 = V_MOV_B32_e32 13, implicit $exec
1075 ; CHECK-NEXT: %4.sub3:vreg_192 = V_MOV_B32_e32 14, implicit $exec
1076 ; CHECK-NEXT: %4.sub4:vreg_192 = V_MOV_B32_e32 15, implicit $exec
1077 ; CHECK-NEXT: %4.sub5:vreg_192 = V_MOV_B32_e32 16, implicit $exec
1078 ; CHECK-NEXT: S_NOP 0, implicit %4
1079 ; CHECK-NEXT: undef %5.sub0:vreg_192 = V_MOV_B32_e32 23, implicit $exec
1080 ; CHECK-NEXT: %5.sub1:vreg_192 = V_MOV_B32_e32 24, implicit $exec
1081 ; CHECK-NEXT: %5.sub2:vreg_192 = V_MOV_B32_e32 25, implicit $exec
1082 ; CHECK-NEXT: %5.sub3:vreg_192 = V_MOV_B32_e32 26, implicit $exec
1083 ; CHECK-NEXT: %5.sub4:vreg_192 = V_MOV_B32_e32 27, implicit $exec
1084 ; CHECK-NEXT: %5.sub5:vreg_192 = V_MOV_B32_e32 28, implicit $exec
1085 ; CHECK-NEXT: S_NOP 0, implicit %5
1086 undef %0.sub0:vreg_288 = V_MOV_B32_e32 00, implicit $exec
1087 %0.sub1:vreg_288 = V_MOV_B32_e32 01, implicit $exec
1088 %0.sub2:vreg_288 = V_MOV_B32_e32 02, implicit $exec
1089 %0.sub3:vreg_288 = V_MOV_B32_e32 03, implicit $exec
1090 %0.sub4:vreg_288 = V_MOV_B32_e32 04, implicit $exec
1091 %0.sub5:vreg_288 = V_MOV_B32_e32 05, implicit $exec
1092 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5
1094 undef %1.sub1:vreg_288 = V_MOV_B32_e32 11, implicit $exec
1095 %1.sub2:vreg_288 = V_MOV_B32_e32 12, implicit $exec
1096 %1.sub3:vreg_288 = V_MOV_B32_e32 13, implicit $exec
1097 %1.sub4:vreg_288 = V_MOV_B32_e32 14, implicit $exec
1098 %1.sub5:vreg_288 = V_MOV_B32_e32 15, implicit $exec
1099 %1.sub6:vreg_288 = V_MOV_B32_e32 16, implicit $exec
1100 S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub5_sub6
1102 undef %2.sub3:vreg_288 = V_MOV_B32_e32 23, implicit $exec
1103 %2.sub4:vreg_288 = V_MOV_B32_e32 24, implicit $exec
1104 %2.sub5:vreg_288 = V_MOV_B32_e32 25, implicit $exec
1105 %2.sub6:vreg_288 = V_MOV_B32_e32 26, implicit $exec
1106 %2.sub7:vreg_288 = V_MOV_B32_e32 27, implicit $exec
1107 %2.sub8:vreg_288 = V_MOV_B32_e32 28, implicit $exec
1108 S_NOP 0, implicit %2.sub3_sub4_sub5_sub6_sub7_sub8
1112 name: test_vreg_288_w256
1113 tracksRegLiveness: true
1116 ; CHECK-LABEL: name: test_vreg_288_w256
1117 ; CHECK: undef %2.sub0:vreg_256 = V_MOV_B32_e32 0, implicit $exec
1118 ; CHECK-NEXT: %2.sub1:vreg_256 = V_MOV_B32_e32 1, implicit $exec
1119 ; CHECK-NEXT: %2.sub2:vreg_256 = V_MOV_B32_e32 2, implicit $exec
1120 ; CHECK-NEXT: %2.sub3:vreg_256 = V_MOV_B32_e32 3, implicit $exec
1121 ; CHECK-NEXT: %2.sub4:vreg_256 = V_MOV_B32_e32 4, implicit $exec
1122 ; CHECK-NEXT: %2.sub5:vreg_256 = V_MOV_B32_e32 5, implicit $exec
1123 ; CHECK-NEXT: %2.sub6:vreg_256 = V_MOV_B32_e32 6, implicit $exec
1124 ; CHECK-NEXT: %2.sub7:vreg_256 = V_MOV_B32_e32 7, implicit $exec
1125 ; CHECK-NEXT: S_NOP 0, implicit %2
1126 ; CHECK-NEXT: undef %3.sub0:vreg_256 = V_MOV_B32_e32 11, implicit $exec
1127 ; CHECK-NEXT: %3.sub1:vreg_256 = V_MOV_B32_e32 12, implicit $exec
1128 ; CHECK-NEXT: %3.sub2:vreg_256 = V_MOV_B32_e32 13, implicit $exec
1129 ; CHECK-NEXT: %3.sub3:vreg_256 = V_MOV_B32_e32 14, implicit $exec
1130 ; CHECK-NEXT: %3.sub4:vreg_256 = V_MOV_B32_e32 15, implicit $exec
1131 ; CHECK-NEXT: %3.sub5:vreg_256 = V_MOV_B32_e32 16, implicit $exec
1132 ; CHECK-NEXT: %3.sub6:vreg_256 = V_MOV_B32_e32 17, implicit $exec
1133 ; CHECK-NEXT: %3.sub7:vreg_256 = V_MOV_B32_e32 18, implicit $exec
1134 ; CHECK-NEXT: S_NOP 0, implicit %3
1135 undef %0.sub0:vreg_288 = V_MOV_B32_e32 00, implicit $exec
1136 %0.sub1:vreg_288 = V_MOV_B32_e32 01, implicit $exec
1137 %0.sub2:vreg_288 = V_MOV_B32_e32 02, implicit $exec
1138 %0.sub3:vreg_288 = V_MOV_B32_e32 03, implicit $exec
1139 %0.sub4:vreg_288 = V_MOV_B32_e32 04, implicit $exec
1140 %0.sub5:vreg_288 = V_MOV_B32_e32 05, implicit $exec
1141 %0.sub6:vreg_288 = V_MOV_B32_e32 06, implicit $exec
1142 %0.sub7:vreg_288 = V_MOV_B32_e32 07, implicit $exec
1143 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7
1145 undef %1.sub1:vreg_288 = V_MOV_B32_e32 11, implicit $exec
1146 %1.sub2:vreg_288 = V_MOV_B32_e32 12, implicit $exec
1147 %1.sub3:vreg_288 = V_MOV_B32_e32 13, implicit $exec
1148 %1.sub4:vreg_288 = V_MOV_B32_e32 14, implicit $exec
1149 %1.sub5:vreg_288 = V_MOV_B32_e32 15, implicit $exec
1150 %1.sub6:vreg_288 = V_MOV_B32_e32 16, implicit $exec
1151 %1.sub7:vreg_288 = V_MOV_B32_e32 17, implicit $exec
1152 %1.sub8:vreg_288 = V_MOV_B32_e32 18, implicit $exec
1153 S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8
1157 name: test_vreg_320_w32
1158 tracksRegLiveness: true
1161 ; CHECK-LABEL: name: test_vreg_320_w32
1162 ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
1163 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
1164 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 11, implicit $exec
1165 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
1166 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 29, implicit $exec
1167 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
1168 undef %0.sub0:vreg_320 = V_MOV_B32_e32 00, implicit $exec
1169 S_NOP 0, implicit %0.sub0
1171 undef %1.sub1:vreg_320 = V_MOV_B32_e32 11, implicit $exec
1172 S_NOP 0, implicit %1.sub1
1174 undef %2.sub9:vreg_320 = V_MOV_B32_e32 29, implicit $exec
1175 S_NOP 0, implicit %2.sub9
1179 name: test_vreg_320_w64
1180 tracksRegLiveness: true
1183 ; CHECK-LABEL: name: test_vreg_320_w64
1184 ; CHECK: undef %3.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
1185 ; CHECK-NEXT: %3.sub1:vreg_64 = V_MOV_B32_e32 1, implicit $exec
1186 ; CHECK-NEXT: S_NOP 0, implicit %3
1187 ; CHECK-NEXT: undef %4.sub0:vreg_64 = V_MOV_B32_e32 11, implicit $exec
1188 ; CHECK-NEXT: %4.sub1:vreg_64 = V_MOV_B32_e32 12, implicit $exec
1189 ; CHECK-NEXT: S_NOP 0, implicit %4
1190 ; CHECK-NEXT: undef %5.sub0:vreg_64 = V_MOV_B32_e32 28, implicit $exec
1191 ; CHECK-NEXT: %5.sub1:vreg_64 = V_MOV_B32_e32 29, implicit $exec
1192 ; CHECK-NEXT: S_NOP 0, implicit %5
1193 undef %0.sub0:vreg_320 = V_MOV_B32_e32 00, implicit $exec
1194 %0.sub1:vreg_320 = V_MOV_B32_e32 01, implicit $exec
1195 S_NOP 0, implicit %0.sub0_sub1
1197 undef %1.sub1:vreg_320 = V_MOV_B32_e32 11, implicit $exec
1198 %1.sub2:vreg_320 = V_MOV_B32_e32 12, implicit $exec
1199 S_NOP 0, implicit %1.sub1_sub2
1201 undef %2.sub8:vreg_320 = V_MOV_B32_e32 28, implicit $exec
1202 %2.sub9:vreg_320 = V_MOV_B32_e32 29, implicit $exec
1203 S_NOP 0, implicit %2.sub8_sub9
1207 name: test_vreg_320_w96
1208 tracksRegLiveness: true
1211 ; CHECK-LABEL: name: test_vreg_320_w96
1212 ; CHECK: undef %3.sub0:vreg_96 = V_MOV_B32_e32 0, implicit $exec
1213 ; CHECK-NEXT: %3.sub1:vreg_96 = V_MOV_B32_e32 1, implicit $exec
1214 ; CHECK-NEXT: %3.sub2:vreg_96 = V_MOV_B32_e32 2, implicit $exec
1215 ; CHECK-NEXT: S_NOP 0, implicit %3
1216 ; CHECK-NEXT: undef %4.sub0:vreg_96 = V_MOV_B32_e32 11, implicit $exec
1217 ; CHECK-NEXT: %4.sub1:vreg_96 = V_MOV_B32_e32 12, implicit $exec
1218 ; CHECK-NEXT: %4.sub2:vreg_96 = V_MOV_B32_e32 13, implicit $exec
1219 ; CHECK-NEXT: S_NOP 0, implicit %4
1220 ; CHECK-NEXT: undef %5.sub0:vreg_96 = V_MOV_B32_e32 27, implicit $exec
1221 ; CHECK-NEXT: %5.sub1:vreg_96 = V_MOV_B32_e32 28, implicit $exec
1222 ; CHECK-NEXT: %5.sub2:vreg_96 = V_MOV_B32_e32 29, implicit $exec
1223 ; CHECK-NEXT: S_NOP 0, implicit %5
1224 undef %0.sub0:vreg_320 = V_MOV_B32_e32 00, implicit $exec
1225 %0.sub1:vreg_320 = V_MOV_B32_e32 01, implicit $exec
1226 %0.sub2:vreg_320 = V_MOV_B32_e32 02, implicit $exec
1227 S_NOP 0, implicit %0.sub0_sub1_sub2
1229 undef %1.sub1:vreg_320 = V_MOV_B32_e32 11, implicit $exec
1230 %1.sub2:vreg_320 = V_MOV_B32_e32 12, implicit $exec
1231 %1.sub3:vreg_320 = V_MOV_B32_e32 13, implicit $exec
1232 S_NOP 0, implicit %1.sub1_sub2_sub3
1234 undef %2.sub7:vreg_320 = V_MOV_B32_e32 27, implicit $exec
1235 %2.sub8:vreg_320 = V_MOV_B32_e32 28, implicit $exec
1236 %2.sub9:vreg_320 = V_MOV_B32_e32 29, implicit $exec
1237 S_NOP 0, implicit %2.sub7_sub8_sub9
1241 name: test_vreg_320_w128
1242 tracksRegLiveness: true
1245 ; CHECK-LABEL: name: test_vreg_320_w128
1246 ; CHECK: undef %3.sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec
1247 ; CHECK-NEXT: %3.sub1:vreg_128 = V_MOV_B32_e32 1, implicit $exec
1248 ; CHECK-NEXT: %3.sub2:vreg_128 = V_MOV_B32_e32 2, implicit $exec
1249 ; CHECK-NEXT: %3.sub3:vreg_128 = V_MOV_B32_e32 3, implicit $exec
1250 ; CHECK-NEXT: S_NOP 0, implicit %3
1251 ; CHECK-NEXT: undef %4.sub0:vreg_128 = V_MOV_B32_e32 11, implicit $exec
1252 ; CHECK-NEXT: %4.sub1:vreg_128 = V_MOV_B32_e32 12, implicit $exec
1253 ; CHECK-NEXT: %4.sub2:vreg_128 = V_MOV_B32_e32 13, implicit $exec
1254 ; CHECK-NEXT: %4.sub3:vreg_128 = V_MOV_B32_e32 14, implicit $exec
1255 ; CHECK-NEXT: S_NOP 0, implicit %4
1256 ; CHECK-NEXT: undef %5.sub0:vreg_128 = V_MOV_B32_e32 26, implicit $exec
1257 ; CHECK-NEXT: %5.sub1:vreg_128 = V_MOV_B32_e32 27, implicit $exec
1258 ; CHECK-NEXT: %5.sub2:vreg_128 = V_MOV_B32_e32 28, implicit $exec
1259 ; CHECK-NEXT: %5.sub3:vreg_128 = V_MOV_B32_e32 29, implicit $exec
1260 ; CHECK-NEXT: S_NOP 0, implicit %5
1261 undef %0.sub0:vreg_320 = V_MOV_B32_e32 00, implicit $exec
1262 %0.sub1:vreg_320 = V_MOV_B32_e32 01, implicit $exec
1263 %0.sub2:vreg_320 = V_MOV_B32_e32 02, implicit $exec
1264 %0.sub3:vreg_320 = V_MOV_B32_e32 03, implicit $exec
1265 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3
1267 undef %1.sub1:vreg_320 = V_MOV_B32_e32 11, implicit $exec
1268 %1.sub2:vreg_320 = V_MOV_B32_e32 12, implicit $exec
1269 %1.sub3:vreg_320 = V_MOV_B32_e32 13, implicit $exec
1270 %1.sub4:vreg_320 = V_MOV_B32_e32 14, implicit $exec
1271 S_NOP 0, implicit %1.sub1_sub2_sub3_sub4
1273 undef %2.sub6:vreg_320 = V_MOV_B32_e32 26, implicit $exec
1274 %2.sub7:vreg_320 = V_MOV_B32_e32 27, implicit $exec
1275 %2.sub8:vreg_320 = V_MOV_B32_e32 28, implicit $exec
1276 %2.sub9:vreg_320 = V_MOV_B32_e32 29, implicit $exec
1277 S_NOP 0, implicit %2.sub6_sub7_sub8_sub9
1281 name: test_vreg_320_w160
1282 tracksRegLiveness: true
1285 ; CHECK-LABEL: name: test_vreg_320_w160
1286 ; CHECK: undef %3.sub0:vreg_160 = V_MOV_B32_e32 0, implicit $exec
1287 ; CHECK-NEXT: %3.sub1:vreg_160 = V_MOV_B32_e32 1, implicit $exec
1288 ; CHECK-NEXT: %3.sub2:vreg_160 = V_MOV_B32_e32 2, implicit $exec
1289 ; CHECK-NEXT: %3.sub3:vreg_160 = V_MOV_B32_e32 3, implicit $exec
1290 ; CHECK-NEXT: %3.sub4:vreg_160 = V_MOV_B32_e32 4, implicit $exec
1291 ; CHECK-NEXT: S_NOP 0, implicit %3
1292 ; CHECK-NEXT: undef %4.sub0:vreg_160 = V_MOV_B32_e32 11, implicit $exec
1293 ; CHECK-NEXT: %4.sub1:vreg_160 = V_MOV_B32_e32 12, implicit $exec
1294 ; CHECK-NEXT: %4.sub2:vreg_160 = V_MOV_B32_e32 13, implicit $exec
1295 ; CHECK-NEXT: %4.sub3:vreg_160 = V_MOV_B32_e32 14, implicit $exec
1296 ; CHECK-NEXT: %4.sub4:vreg_160 = V_MOV_B32_e32 15, implicit $exec
1297 ; CHECK-NEXT: S_NOP 0, implicit %4
1298 ; CHECK-NEXT: undef %5.sub0:vreg_160 = V_MOV_B32_e32 25, implicit $exec
1299 ; CHECK-NEXT: %5.sub1:vreg_160 = V_MOV_B32_e32 26, implicit $exec
1300 ; CHECK-NEXT: %5.sub2:vreg_160 = V_MOV_B32_e32 27, implicit $exec
1301 ; CHECK-NEXT: %5.sub3:vreg_160 = V_MOV_B32_e32 28, implicit $exec
1302 ; CHECK-NEXT: %5.sub4:vreg_160 = V_MOV_B32_e32 29, implicit $exec
1303 ; CHECK-NEXT: S_NOP 0, implicit %5
1304 undef %0.sub0:vreg_320 = V_MOV_B32_e32 00, implicit $exec
1305 %0.sub1:vreg_320 = V_MOV_B32_e32 01, implicit $exec
1306 %0.sub2:vreg_320 = V_MOV_B32_e32 02, implicit $exec
1307 %0.sub3:vreg_320 = V_MOV_B32_e32 03, implicit $exec
1308 %0.sub4:vreg_320 = V_MOV_B32_e32 04, implicit $exec
1309 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4
1311 undef %1.sub1:vreg_320 = V_MOV_B32_e32 11, implicit $exec
1312 %1.sub2:vreg_320 = V_MOV_B32_e32 12, implicit $exec
1313 %1.sub3:vreg_320 = V_MOV_B32_e32 13, implicit $exec
1314 %1.sub4:vreg_320 = V_MOV_B32_e32 14, implicit $exec
1315 %1.sub5:vreg_320 = V_MOV_B32_e32 15, implicit $exec
1316 S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub5
1318 undef %2.sub5:vreg_320 = V_MOV_B32_e32 25, implicit $exec
1319 %2.sub6:vreg_320 = V_MOV_B32_e32 26, implicit $exec
1320 %2.sub7:vreg_320 = V_MOV_B32_e32 27, implicit $exec
1321 %2.sub8:vreg_320 = V_MOV_B32_e32 28, implicit $exec
1322 %2.sub9:vreg_320 = V_MOV_B32_e32 29, implicit $exec
1323 S_NOP 0, implicit %2.sub5_sub6_sub7_sub8_sub9
1327 name: test_vreg_320_w192
1328 tracksRegLiveness: true
1331 ; CHECK-LABEL: name: test_vreg_320_w192
1332 ; CHECK: undef %3.sub0:vreg_192 = V_MOV_B32_e32 0, implicit $exec
1333 ; CHECK-NEXT: %3.sub1:vreg_192 = V_MOV_B32_e32 1, implicit $exec
1334 ; CHECK-NEXT: %3.sub2:vreg_192 = V_MOV_B32_e32 2, implicit $exec
1335 ; CHECK-NEXT: %3.sub3:vreg_192 = V_MOV_B32_e32 3, implicit $exec
1336 ; CHECK-NEXT: %3.sub4:vreg_192 = V_MOV_B32_e32 4, implicit $exec
1337 ; CHECK-NEXT: %3.sub5:vreg_192 = V_MOV_B32_e32 5, implicit $exec
1338 ; CHECK-NEXT: S_NOP 0, implicit %3
1339 ; CHECK-NEXT: undef %4.sub0:vreg_192 = V_MOV_B32_e32 11, implicit $exec
1340 ; CHECK-NEXT: %4.sub1:vreg_192 = V_MOV_B32_e32 12, implicit $exec
1341 ; CHECK-NEXT: %4.sub2:vreg_192 = V_MOV_B32_e32 13, implicit $exec
1342 ; CHECK-NEXT: %4.sub3:vreg_192 = V_MOV_B32_e32 14, implicit $exec
1343 ; CHECK-NEXT: %4.sub4:vreg_192 = V_MOV_B32_e32 15, implicit $exec
1344 ; CHECK-NEXT: %4.sub5:vreg_192 = V_MOV_B32_e32 16, implicit $exec
1345 ; CHECK-NEXT: S_NOP 0, implicit %4
1346 ; CHECK-NEXT: undef %5.sub0:vreg_192 = V_MOV_B32_e32 24, implicit $exec
1347 ; CHECK-NEXT: %5.sub1:vreg_192 = V_MOV_B32_e32 25, implicit $exec
1348 ; CHECK-NEXT: %5.sub2:vreg_192 = V_MOV_B32_e32 26, implicit $exec
1349 ; CHECK-NEXT: %5.sub3:vreg_192 = V_MOV_B32_e32 27, implicit $exec
1350 ; CHECK-NEXT: %5.sub4:vreg_192 = V_MOV_B32_e32 28, implicit $exec
1351 ; CHECK-NEXT: %5.sub5:vreg_192 = V_MOV_B32_e32 29, implicit $exec
1352 ; CHECK-NEXT: S_NOP 0, implicit %5
1353 undef %0.sub0:vreg_320 = V_MOV_B32_e32 00, implicit $exec
1354 %0.sub1:vreg_320 = V_MOV_B32_e32 01, implicit $exec
1355 %0.sub2:vreg_320 = V_MOV_B32_e32 02, implicit $exec
1356 %0.sub3:vreg_320 = V_MOV_B32_e32 03, implicit $exec
1357 %0.sub4:vreg_320 = V_MOV_B32_e32 04, implicit $exec
1358 %0.sub5:vreg_320 = V_MOV_B32_e32 05, implicit $exec
1359 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5
1361 undef %1.sub1:vreg_320 = V_MOV_B32_e32 11, implicit $exec
1362 %1.sub2:vreg_320 = V_MOV_B32_e32 12, implicit $exec
1363 %1.sub3:vreg_320 = V_MOV_B32_e32 13, implicit $exec
1364 %1.sub4:vreg_320 = V_MOV_B32_e32 14, implicit $exec
1365 %1.sub5:vreg_320 = V_MOV_B32_e32 15, implicit $exec
1366 %1.sub6:vreg_320 = V_MOV_B32_e32 16, implicit $exec
1367 S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub5_sub6
1369 undef %2.sub4:vreg_320 = V_MOV_B32_e32 24, implicit $exec
1370 %2.sub5:vreg_320 = V_MOV_B32_e32 25, implicit $exec
1371 %2.sub6:vreg_320 = V_MOV_B32_e32 26, implicit $exec
1372 %2.sub7:vreg_320 = V_MOV_B32_e32 27, implicit $exec
1373 %2.sub8:vreg_320 = V_MOV_B32_e32 28, implicit $exec
1374 %2.sub9:vreg_320 = V_MOV_B32_e32 29, implicit $exec
1375 S_NOP 0, implicit %2.sub4_sub5_sub6_sub7_sub8_sub9
1379 name: test_vreg_320_w256
1380 tracksRegLiveness: true
1383 ; CHECK-LABEL: name: test_vreg_320_w256
1384 ; CHECK: undef %3.sub0:vreg_256 = V_MOV_B32_e32 0, implicit $exec
1385 ; CHECK-NEXT: %3.sub1:vreg_256 = V_MOV_B32_e32 1, implicit $exec
1386 ; CHECK-NEXT: %3.sub2:vreg_256 = V_MOV_B32_e32 2, implicit $exec
1387 ; CHECK-NEXT: %3.sub3:vreg_256 = V_MOV_B32_e32 3, implicit $exec
1388 ; CHECK-NEXT: %3.sub4:vreg_256 = V_MOV_B32_e32 4, implicit $exec
1389 ; CHECK-NEXT: %3.sub5:vreg_256 = V_MOV_B32_e32 5, implicit $exec
1390 ; CHECK-NEXT: %3.sub6:vreg_256 = V_MOV_B32_e32 6, implicit $exec
1391 ; CHECK-NEXT: %3.sub7:vreg_256 = V_MOV_B32_e32 7, implicit $exec
1392 ; CHECK-NEXT: S_NOP 0, implicit %3
1393 ; CHECK-NEXT: undef %4.sub0:vreg_256 = V_MOV_B32_e32 11, implicit $exec
1394 ; CHECK-NEXT: %4.sub1:vreg_256 = V_MOV_B32_e32 12, implicit $exec
1395 ; CHECK-NEXT: %4.sub2:vreg_256 = V_MOV_B32_e32 13, implicit $exec
1396 ; CHECK-NEXT: %4.sub3:vreg_256 = V_MOV_B32_e32 14, implicit $exec
1397 ; CHECK-NEXT: %4.sub4:vreg_256 = V_MOV_B32_e32 15, implicit $exec
1398 ; CHECK-NEXT: %4.sub5:vreg_256 = V_MOV_B32_e32 16, implicit $exec
1399 ; CHECK-NEXT: %4.sub6:vreg_256 = V_MOV_B32_e32 17, implicit $exec
1400 ; CHECK-NEXT: %4.sub7:vreg_256 = V_MOV_B32_e32 18, implicit $exec
1401 ; CHECK-NEXT: S_NOP 0, implicit %4
1402 ; CHECK-NEXT: undef %5.sub0:vreg_256 = V_MOV_B32_e32 22, implicit $exec
1403 ; CHECK-NEXT: %5.sub1:vreg_256 = V_MOV_B32_e32 23, implicit $exec
1404 ; CHECK-NEXT: %5.sub2:vreg_256 = V_MOV_B32_e32 24, implicit $exec
1405 ; CHECK-NEXT: %5.sub3:vreg_256 = V_MOV_B32_e32 25, implicit $exec
1406 ; CHECK-NEXT: %5.sub4:vreg_256 = V_MOV_B32_e32 26, implicit $exec
1407 ; CHECK-NEXT: %5.sub5:vreg_256 = V_MOV_B32_e32 27, implicit $exec
1408 ; CHECK-NEXT: %5.sub6:vreg_256 = V_MOV_B32_e32 28, implicit $exec
1409 ; CHECK-NEXT: %5.sub7:vreg_256 = V_MOV_B32_e32 29, implicit $exec
1410 ; CHECK-NEXT: S_NOP 0, implicit %5
1411 undef %0.sub0:vreg_320 = V_MOV_B32_e32 00, implicit $exec
1412 %0.sub1:vreg_320 = V_MOV_B32_e32 01, implicit $exec
1413 %0.sub2:vreg_320 = V_MOV_B32_e32 02, implicit $exec
1414 %0.sub3:vreg_320 = V_MOV_B32_e32 03, implicit $exec
1415 %0.sub4:vreg_320 = V_MOV_B32_e32 04, implicit $exec
1416 %0.sub5:vreg_320 = V_MOV_B32_e32 05, implicit $exec
1417 %0.sub6:vreg_320 = V_MOV_B32_e32 06, implicit $exec
1418 %0.sub7:vreg_320 = V_MOV_B32_e32 07, implicit $exec
1419 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7
1421 undef %1.sub1:vreg_320 = V_MOV_B32_e32 11, implicit $exec
1422 %1.sub2:vreg_320 = V_MOV_B32_e32 12, implicit $exec
1423 %1.sub3:vreg_320 = V_MOV_B32_e32 13, implicit $exec
1424 %1.sub4:vreg_320 = V_MOV_B32_e32 14, implicit $exec
1425 %1.sub5:vreg_320 = V_MOV_B32_e32 15, implicit $exec
1426 %1.sub6:vreg_320 = V_MOV_B32_e32 16, implicit $exec
1427 %1.sub7:vreg_320 = V_MOV_B32_e32 17, implicit $exec
1428 %1.sub8:vreg_320 = V_MOV_B32_e32 18, implicit $exec
1429 S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8
1431 undef %2.sub2:vreg_320 = V_MOV_B32_e32 22, implicit $exec
1432 %2.sub3:vreg_320 = V_MOV_B32_e32 23, implicit $exec
1433 %2.sub4:vreg_320 = V_MOV_B32_e32 24, implicit $exec
1434 %2.sub5:vreg_320 = V_MOV_B32_e32 25, implicit $exec
1435 %2.sub6:vreg_320 = V_MOV_B32_e32 26, implicit $exec
1436 %2.sub7:vreg_320 = V_MOV_B32_e32 27, implicit $exec
1437 %2.sub8:vreg_320 = V_MOV_B32_e32 28, implicit $exec
1438 %2.sub9:vreg_320 = V_MOV_B32_e32 29, implicit $exec
1439 S_NOP 0, implicit %2.sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9
1443 name: test_vreg_352_w32
1444 tracksRegLiveness: true
1447 ; CHECK-LABEL: name: test_vreg_352_w32
1448 ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
1449 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
1450 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 11, implicit $exec
1451 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
1452 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 210, implicit $exec
1453 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
1454 undef %0.sub0:vreg_352 = V_MOV_B32_e32 00, implicit $exec
1455 S_NOP 0, implicit %0.sub0
1457 undef %1.sub1:vreg_352 = V_MOV_B32_e32 11, implicit $exec
1458 S_NOP 0, implicit %1.sub1
1460 undef %2.sub10:vreg_352 = V_MOV_B32_e32 210, implicit $exec
1461 S_NOP 0, implicit %2.sub10
1465 name: test_vreg_352_w64
1466 tracksRegLiveness: true
1469 ; CHECK-LABEL: name: test_vreg_352_w64
1470 ; CHECK: undef %3.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
1471 ; CHECK-NEXT: %3.sub1:vreg_64 = V_MOV_B32_e32 1, implicit $exec
1472 ; CHECK-NEXT: S_NOP 0, implicit %3
1473 ; CHECK-NEXT: undef %4.sub0:vreg_64 = V_MOV_B32_e32 11, implicit $exec
1474 ; CHECK-NEXT: %4.sub1:vreg_64 = V_MOV_B32_e32 12, implicit $exec
1475 ; CHECK-NEXT: S_NOP 0, implicit %4
1476 ; CHECK-NEXT: undef %5.sub0:vreg_64 = V_MOV_B32_e32 29, implicit $exec
1477 ; CHECK-NEXT: %5.sub1:vreg_64 = V_MOV_B32_e32 210, implicit $exec
1478 ; CHECK-NEXT: S_NOP 0, implicit %5
1479 undef %0.sub0:vreg_352 = V_MOV_B32_e32 00, implicit $exec
1480 %0.sub1:vreg_352 = V_MOV_B32_e32 01, implicit $exec
1481 S_NOP 0, implicit %0.sub0_sub1
1483 undef %1.sub1:vreg_352 = V_MOV_B32_e32 11, implicit $exec
1484 %1.sub2:vreg_352 = V_MOV_B32_e32 12, implicit $exec
1485 S_NOP 0, implicit %1.sub1_sub2
1487 undef %2.sub9:vreg_352 = V_MOV_B32_e32 29, implicit $exec
1488 %2.sub10:vreg_352 = V_MOV_B32_e32 210, implicit $exec
1489 S_NOP 0, implicit %2.sub9_sub10
1493 name: test_vreg_352_w96
1494 tracksRegLiveness: true
1497 ; CHECK-LABEL: name: test_vreg_352_w96
1498 ; CHECK: undef %3.sub0:vreg_96 = V_MOV_B32_e32 0, implicit $exec
1499 ; CHECK-NEXT: %3.sub1:vreg_96 = V_MOV_B32_e32 1, implicit $exec
1500 ; CHECK-NEXT: %3.sub2:vreg_96 = V_MOV_B32_e32 2, implicit $exec
1501 ; CHECK-NEXT: S_NOP 0, implicit %3
1502 ; CHECK-NEXT: undef %4.sub0:vreg_96 = V_MOV_B32_e32 11, implicit $exec
1503 ; CHECK-NEXT: %4.sub1:vreg_96 = V_MOV_B32_e32 12, implicit $exec
1504 ; CHECK-NEXT: %4.sub2:vreg_96 = V_MOV_B32_e32 13, implicit $exec
1505 ; CHECK-NEXT: S_NOP 0, implicit %4
1506 ; CHECK-NEXT: undef %5.sub0:vreg_96 = V_MOV_B32_e32 28, implicit $exec
1507 ; CHECK-NEXT: %5.sub1:vreg_96 = V_MOV_B32_e32 29, implicit $exec
1508 ; CHECK-NEXT: %5.sub2:vreg_96 = V_MOV_B32_e32 210, implicit $exec
1509 ; CHECK-NEXT: S_NOP 0, implicit %5
1510 undef %0.sub0:vreg_352 = V_MOV_B32_e32 00, implicit $exec
1511 %0.sub1:vreg_352 = V_MOV_B32_e32 01, implicit $exec
1512 %0.sub2:vreg_352 = V_MOV_B32_e32 02, implicit $exec
1513 S_NOP 0, implicit %0.sub0_sub1_sub2
1515 undef %1.sub1:vreg_352 = V_MOV_B32_e32 11, implicit $exec
1516 %1.sub2:vreg_352 = V_MOV_B32_e32 12, implicit $exec
1517 %1.sub3:vreg_352 = V_MOV_B32_e32 13, implicit $exec
1518 S_NOP 0, implicit %1.sub1_sub2_sub3
1520 undef %2.sub8:vreg_352 = V_MOV_B32_e32 28, implicit $exec
1521 %2.sub9:vreg_352 = V_MOV_B32_e32 29, implicit $exec
1522 %2.sub10:vreg_352 = V_MOV_B32_e32 210, implicit $exec
1523 S_NOP 0, implicit %2.sub8_sub9_sub10
1527 name: test_vreg_352_w128
1528 tracksRegLiveness: true
1531 ; CHECK-LABEL: name: test_vreg_352_w128
1532 ; CHECK: undef %3.sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec
1533 ; CHECK-NEXT: %3.sub1:vreg_128 = V_MOV_B32_e32 1, implicit $exec
1534 ; CHECK-NEXT: %3.sub2:vreg_128 = V_MOV_B32_e32 2, implicit $exec
1535 ; CHECK-NEXT: %3.sub3:vreg_128 = V_MOV_B32_e32 3, implicit $exec
1536 ; CHECK-NEXT: S_NOP 0, implicit %3
1537 ; CHECK-NEXT: undef %4.sub0:vreg_128 = V_MOV_B32_e32 11, implicit $exec
1538 ; CHECK-NEXT: %4.sub1:vreg_128 = V_MOV_B32_e32 12, implicit $exec
1539 ; CHECK-NEXT: %4.sub2:vreg_128 = V_MOV_B32_e32 13, implicit $exec
1540 ; CHECK-NEXT: %4.sub3:vreg_128 = V_MOV_B32_e32 14, implicit $exec
1541 ; CHECK-NEXT: S_NOP 0, implicit %4
1542 ; CHECK-NEXT: undef %5.sub0:vreg_128 = V_MOV_B32_e32 27, implicit $exec
1543 ; CHECK-NEXT: %5.sub1:vreg_128 = V_MOV_B32_e32 28, implicit $exec
1544 ; CHECK-NEXT: %5.sub2:vreg_128 = V_MOV_B32_e32 29, implicit $exec
1545 ; CHECK-NEXT: %5.sub3:vreg_128 = V_MOV_B32_e32 210, implicit $exec
1546 ; CHECK-NEXT: S_NOP 0, implicit %5
1547 undef %0.sub0:vreg_352 = V_MOV_B32_e32 00, implicit $exec
1548 %0.sub1:vreg_352 = V_MOV_B32_e32 01, implicit $exec
1549 %0.sub2:vreg_352 = V_MOV_B32_e32 02, implicit $exec
1550 %0.sub3:vreg_352 = V_MOV_B32_e32 03, implicit $exec
1551 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3
1553 undef %1.sub1:vreg_352 = V_MOV_B32_e32 11, implicit $exec
1554 %1.sub2:vreg_352 = V_MOV_B32_e32 12, implicit $exec
1555 %1.sub3:vreg_352 = V_MOV_B32_e32 13, implicit $exec
1556 %1.sub4:vreg_352 = V_MOV_B32_e32 14, implicit $exec
1557 S_NOP 0, implicit %1.sub1_sub2_sub3_sub4
1559 undef %2.sub7:vreg_352 = V_MOV_B32_e32 27, implicit $exec
1560 %2.sub8:vreg_352 = V_MOV_B32_e32 28, implicit $exec
1561 %2.sub9:vreg_352 = V_MOV_B32_e32 29, implicit $exec
1562 %2.sub10:vreg_352 = V_MOV_B32_e32 210, implicit $exec
1563 S_NOP 0, implicit %2.sub7_sub8_sub9_sub10
1567 name: test_vreg_352_w160
1568 tracksRegLiveness: true
1571 ; CHECK-LABEL: name: test_vreg_352_w160
1572 ; CHECK: undef %3.sub0:vreg_160 = V_MOV_B32_e32 0, implicit $exec
1573 ; CHECK-NEXT: %3.sub1:vreg_160 = V_MOV_B32_e32 1, implicit $exec
1574 ; CHECK-NEXT: %3.sub2:vreg_160 = V_MOV_B32_e32 2, implicit $exec
1575 ; CHECK-NEXT: %3.sub3:vreg_160 = V_MOV_B32_e32 3, implicit $exec
1576 ; CHECK-NEXT: %3.sub4:vreg_160 = V_MOV_B32_e32 4, implicit $exec
1577 ; CHECK-NEXT: S_NOP 0, implicit %3
1578 ; CHECK-NEXT: undef %4.sub0:vreg_160 = V_MOV_B32_e32 11, implicit $exec
1579 ; CHECK-NEXT: %4.sub1:vreg_160 = V_MOV_B32_e32 12, implicit $exec
1580 ; CHECK-NEXT: %4.sub2:vreg_160 = V_MOV_B32_e32 13, implicit $exec
1581 ; CHECK-NEXT: %4.sub3:vreg_160 = V_MOV_B32_e32 14, implicit $exec
1582 ; CHECK-NEXT: %4.sub4:vreg_160 = V_MOV_B32_e32 15, implicit $exec
1583 ; CHECK-NEXT: S_NOP 0, implicit %4
1584 ; CHECK-NEXT: undef %5.sub0:vreg_160 = V_MOV_B32_e32 26, implicit $exec
1585 ; CHECK-NEXT: %5.sub1:vreg_160 = V_MOV_B32_e32 27, implicit $exec
1586 ; CHECK-NEXT: %5.sub2:vreg_160 = V_MOV_B32_e32 28, implicit $exec
1587 ; CHECK-NEXT: %5.sub3:vreg_160 = V_MOV_B32_e32 29, implicit $exec
1588 ; CHECK-NEXT: %5.sub4:vreg_160 = V_MOV_B32_e32 210, implicit $exec
1589 ; CHECK-NEXT: S_NOP 0, implicit %5
1590 undef %0.sub0:vreg_352 = V_MOV_B32_e32 00, implicit $exec
1591 %0.sub1:vreg_352 = V_MOV_B32_e32 01, implicit $exec
1592 %0.sub2:vreg_352 = V_MOV_B32_e32 02, implicit $exec
1593 %0.sub3:vreg_352 = V_MOV_B32_e32 03, implicit $exec
1594 %0.sub4:vreg_352 = V_MOV_B32_e32 04, implicit $exec
1595 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4
1597 undef %1.sub1:vreg_352 = V_MOV_B32_e32 11, implicit $exec
1598 %1.sub2:vreg_352 = V_MOV_B32_e32 12, implicit $exec
1599 %1.sub3:vreg_352 = V_MOV_B32_e32 13, implicit $exec
1600 %1.sub4:vreg_352 = V_MOV_B32_e32 14, implicit $exec
1601 %1.sub5:vreg_352 = V_MOV_B32_e32 15, implicit $exec
1602 S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub5
1604 undef %2.sub6:vreg_352 = V_MOV_B32_e32 26, implicit $exec
1605 %2.sub7:vreg_352 = V_MOV_B32_e32 27, implicit $exec
1606 %2.sub8:vreg_352 = V_MOV_B32_e32 28, implicit $exec
1607 %2.sub9:vreg_352 = V_MOV_B32_e32 29, implicit $exec
1608 %2.sub10:vreg_352 = V_MOV_B32_e32 210, implicit $exec
1609 S_NOP 0, implicit %2.sub6_sub7_sub8_sub9_sub10
1613 name: test_vreg_352_w192
1614 tracksRegLiveness: true
1617 ; CHECK-LABEL: name: test_vreg_352_w192
1618 ; CHECK: undef %3.sub0:vreg_192 = V_MOV_B32_e32 0, implicit $exec
1619 ; CHECK-NEXT: %3.sub1:vreg_192 = V_MOV_B32_e32 1, implicit $exec
1620 ; CHECK-NEXT: %3.sub2:vreg_192 = V_MOV_B32_e32 2, implicit $exec
1621 ; CHECK-NEXT: %3.sub3:vreg_192 = V_MOV_B32_e32 3, implicit $exec
1622 ; CHECK-NEXT: %3.sub4:vreg_192 = V_MOV_B32_e32 4, implicit $exec
1623 ; CHECK-NEXT: %3.sub5:vreg_192 = V_MOV_B32_e32 5, implicit $exec
1624 ; CHECK-NEXT: S_NOP 0, implicit %3
1625 ; CHECK-NEXT: undef %4.sub0:vreg_192 = V_MOV_B32_e32 11, implicit $exec
1626 ; CHECK-NEXT: %4.sub1:vreg_192 = V_MOV_B32_e32 12, implicit $exec
1627 ; CHECK-NEXT: %4.sub2:vreg_192 = V_MOV_B32_e32 13, implicit $exec
1628 ; CHECK-NEXT: %4.sub3:vreg_192 = V_MOV_B32_e32 14, implicit $exec
1629 ; CHECK-NEXT: %4.sub4:vreg_192 = V_MOV_B32_e32 15, implicit $exec
1630 ; CHECK-NEXT: %4.sub5:vreg_192 = V_MOV_B32_e32 16, implicit $exec
1631 ; CHECK-NEXT: S_NOP 0, implicit %4
1632 ; CHECK-NEXT: undef %5.sub0:vreg_192 = V_MOV_B32_e32 25, implicit $exec
1633 ; CHECK-NEXT: %5.sub1:vreg_192 = V_MOV_B32_e32 26, implicit $exec
1634 ; CHECK-NEXT: %5.sub2:vreg_192 = V_MOV_B32_e32 27, implicit $exec
1635 ; CHECK-NEXT: %5.sub3:vreg_192 = V_MOV_B32_e32 28, implicit $exec
1636 ; CHECK-NEXT: %5.sub4:vreg_192 = V_MOV_B32_e32 29, implicit $exec
1637 ; CHECK-NEXT: %5.sub5:vreg_192 = V_MOV_B32_e32 210, implicit $exec
1638 ; CHECK-NEXT: S_NOP 0, implicit %5
1639 undef %0.sub0:vreg_352 = V_MOV_B32_e32 00, implicit $exec
1640 %0.sub1:vreg_352 = V_MOV_B32_e32 01, implicit $exec
1641 %0.sub2:vreg_352 = V_MOV_B32_e32 02, implicit $exec
1642 %0.sub3:vreg_352 = V_MOV_B32_e32 03, implicit $exec
1643 %0.sub4:vreg_352 = V_MOV_B32_e32 04, implicit $exec
1644 %0.sub5:vreg_352 = V_MOV_B32_e32 05, implicit $exec
1645 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5
1647 undef %1.sub1:vreg_352 = V_MOV_B32_e32 11, implicit $exec
1648 %1.sub2:vreg_352 = V_MOV_B32_e32 12, implicit $exec
1649 %1.sub3:vreg_352 = V_MOV_B32_e32 13, implicit $exec
1650 %1.sub4:vreg_352 = V_MOV_B32_e32 14, implicit $exec
1651 %1.sub5:vreg_352 = V_MOV_B32_e32 15, implicit $exec
1652 %1.sub6:vreg_352 = V_MOV_B32_e32 16, implicit $exec
1653 S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub5_sub6
1655 undef %2.sub5:vreg_352 = V_MOV_B32_e32 25, implicit $exec
1656 %2.sub6:vreg_352 = V_MOV_B32_e32 26, implicit $exec
1657 %2.sub7:vreg_352 = V_MOV_B32_e32 27, implicit $exec
1658 %2.sub8:vreg_352 = V_MOV_B32_e32 28, implicit $exec
1659 %2.sub9:vreg_352 = V_MOV_B32_e32 29, implicit $exec
1660 %2.sub10:vreg_352 = V_MOV_B32_e32 210, implicit $exec
1661 S_NOP 0, implicit %2.sub5_sub6_sub7_sub8_sub9_sub10
1665 name: test_vreg_352_w256
1666 tracksRegLiveness: true
1669 ; CHECK-LABEL: name: test_vreg_352_w256
1670 ; CHECK: undef %3.sub0:vreg_256 = V_MOV_B32_e32 0, implicit $exec
1671 ; CHECK-NEXT: %3.sub1:vreg_256 = V_MOV_B32_e32 1, implicit $exec
1672 ; CHECK-NEXT: %3.sub2:vreg_256 = V_MOV_B32_e32 2, implicit $exec
1673 ; CHECK-NEXT: %3.sub3:vreg_256 = V_MOV_B32_e32 3, implicit $exec
1674 ; CHECK-NEXT: %3.sub4:vreg_256 = V_MOV_B32_e32 4, implicit $exec
1675 ; CHECK-NEXT: %3.sub5:vreg_256 = V_MOV_B32_e32 5, implicit $exec
1676 ; CHECK-NEXT: %3.sub6:vreg_256 = V_MOV_B32_e32 6, implicit $exec
1677 ; CHECK-NEXT: %3.sub7:vreg_256 = V_MOV_B32_e32 7, implicit $exec
1678 ; CHECK-NEXT: S_NOP 0, implicit %3
1679 ; CHECK-NEXT: undef %4.sub0:vreg_256 = V_MOV_B32_e32 11, implicit $exec
1680 ; CHECK-NEXT: %4.sub1:vreg_256 = V_MOV_B32_e32 12, implicit $exec
1681 ; CHECK-NEXT: %4.sub2:vreg_256 = V_MOV_B32_e32 13, implicit $exec
1682 ; CHECK-NEXT: %4.sub3:vreg_256 = V_MOV_B32_e32 14, implicit $exec
1683 ; CHECK-NEXT: %4.sub4:vreg_256 = V_MOV_B32_e32 15, implicit $exec
1684 ; CHECK-NEXT: %4.sub5:vreg_256 = V_MOV_B32_e32 16, implicit $exec
1685 ; CHECK-NEXT: %4.sub6:vreg_256 = V_MOV_B32_e32 17, implicit $exec
1686 ; CHECK-NEXT: %4.sub7:vreg_256 = V_MOV_B32_e32 18, implicit $exec
1687 ; CHECK-NEXT: S_NOP 0, implicit %4
1688 ; CHECK-NEXT: undef %5.sub0:vreg_256 = V_MOV_B32_e32 23, implicit $exec
1689 ; CHECK-NEXT: %5.sub1:vreg_256 = V_MOV_B32_e32 24, implicit $exec
1690 ; CHECK-NEXT: %5.sub2:vreg_256 = V_MOV_B32_e32 25, implicit $exec
1691 ; CHECK-NEXT: %5.sub3:vreg_256 = V_MOV_B32_e32 26, implicit $exec
1692 ; CHECK-NEXT: %5.sub4:vreg_256 = V_MOV_B32_e32 27, implicit $exec
1693 ; CHECK-NEXT: %5.sub5:vreg_256 = V_MOV_B32_e32 28, implicit $exec
1694 ; CHECK-NEXT: %5.sub6:vreg_256 = V_MOV_B32_e32 29, implicit $exec
1695 ; CHECK-NEXT: %5.sub7:vreg_256 = V_MOV_B32_e32 210, implicit $exec
1696 ; CHECK-NEXT: S_NOP 0, implicit %5
1697 undef %0.sub0:vreg_352 = V_MOV_B32_e32 00, implicit $exec
1698 %0.sub1:vreg_352 = V_MOV_B32_e32 01, implicit $exec
1699 %0.sub2:vreg_352 = V_MOV_B32_e32 02, implicit $exec
1700 %0.sub3:vreg_352 = V_MOV_B32_e32 03, implicit $exec
1701 %0.sub4:vreg_352 = V_MOV_B32_e32 04, implicit $exec
1702 %0.sub5:vreg_352 = V_MOV_B32_e32 05, implicit $exec
1703 %0.sub6:vreg_352 = V_MOV_B32_e32 06, implicit $exec
1704 %0.sub7:vreg_352 = V_MOV_B32_e32 07, implicit $exec
1705 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7
1707 undef %1.sub1:vreg_352 = V_MOV_B32_e32 11, implicit $exec
1708 %1.sub2:vreg_352 = V_MOV_B32_e32 12, implicit $exec
1709 %1.sub3:vreg_352 = V_MOV_B32_e32 13, implicit $exec
1710 %1.sub4:vreg_352 = V_MOV_B32_e32 14, implicit $exec
1711 %1.sub5:vreg_352 = V_MOV_B32_e32 15, implicit $exec
1712 %1.sub6:vreg_352 = V_MOV_B32_e32 16, implicit $exec
1713 %1.sub7:vreg_352 = V_MOV_B32_e32 17, implicit $exec
1714 %1.sub8:vreg_352 = V_MOV_B32_e32 18, implicit $exec
1715 S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8
1717 undef %2.sub3:vreg_352 = V_MOV_B32_e32 23, implicit $exec
1718 %2.sub4:vreg_352 = V_MOV_B32_e32 24, implicit $exec
1719 %2.sub5:vreg_352 = V_MOV_B32_e32 25, implicit $exec
1720 %2.sub6:vreg_352 = V_MOV_B32_e32 26, implicit $exec
1721 %2.sub7:vreg_352 = V_MOV_B32_e32 27, implicit $exec
1722 %2.sub8:vreg_352 = V_MOV_B32_e32 28, implicit $exec
1723 %2.sub9:vreg_352 = V_MOV_B32_e32 29, implicit $exec
1724 %2.sub10:vreg_352 = V_MOV_B32_e32 210, implicit $exec
1725 S_NOP 0, implicit %2.sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10
1729 name: test_vreg_384_w32
1730 tracksRegLiveness: true
1733 ; CHECK-LABEL: name: test_vreg_384_w32
1734 ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
1735 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
1736 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 11, implicit $exec
1737 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
1738 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 211, implicit $exec
1739 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
1740 undef %0.sub0:vreg_384 = V_MOV_B32_e32 00, implicit $exec
1741 S_NOP 0, implicit %0.sub0
1743 undef %1.sub1:vreg_384 = V_MOV_B32_e32 11, implicit $exec
1744 S_NOP 0, implicit %1.sub1
1746 undef %2.sub11:vreg_384 = V_MOV_B32_e32 211, implicit $exec
1747 S_NOP 0, implicit %2.sub11
1751 name: test_vreg_384_w64
1752 tracksRegLiveness: true
1755 ; CHECK-LABEL: name: test_vreg_384_w64
1756 ; CHECK: undef %3.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
1757 ; CHECK-NEXT: %3.sub1:vreg_64 = V_MOV_B32_e32 1, implicit $exec
1758 ; CHECK-NEXT: S_NOP 0, implicit %3
1759 ; CHECK-NEXT: undef %4.sub0:vreg_64 = V_MOV_B32_e32 11, implicit $exec
1760 ; CHECK-NEXT: %4.sub1:vreg_64 = V_MOV_B32_e32 12, implicit $exec
1761 ; CHECK-NEXT: S_NOP 0, implicit %4
1762 ; CHECK-NEXT: undef %5.sub0:vreg_64 = V_MOV_B32_e32 210, implicit $exec
1763 ; CHECK-NEXT: %5.sub1:vreg_64 = V_MOV_B32_e32 211, implicit $exec
1764 ; CHECK-NEXT: S_NOP 0, implicit %5
1765 undef %0.sub0:vreg_384 = V_MOV_B32_e32 00, implicit $exec
1766 %0.sub1:vreg_384 = V_MOV_B32_e32 01, implicit $exec
1767 S_NOP 0, implicit %0.sub0_sub1
1769 undef %1.sub1:vreg_384 = V_MOV_B32_e32 11, implicit $exec
1770 %1.sub2:vreg_384 = V_MOV_B32_e32 12, implicit $exec
1771 S_NOP 0, implicit %1.sub1_sub2
1773 undef %2.sub10:vreg_384 = V_MOV_B32_e32 210, implicit $exec
1774 %2.sub11:vreg_384 = V_MOV_B32_e32 211, implicit $exec
1775 S_NOP 0, implicit %2.sub10_sub11
1779 name: test_vreg_384_w96
1780 tracksRegLiveness: true
1783 ; CHECK-LABEL: name: test_vreg_384_w96
1784 ; CHECK: undef %3.sub0:vreg_96 = V_MOV_B32_e32 0, implicit $exec
1785 ; CHECK-NEXT: %3.sub1:vreg_96 = V_MOV_B32_e32 1, implicit $exec
1786 ; CHECK-NEXT: %3.sub2:vreg_96 = V_MOV_B32_e32 2, implicit $exec
1787 ; CHECK-NEXT: S_NOP 0, implicit %3
1788 ; CHECK-NEXT: undef %4.sub0:vreg_96 = V_MOV_B32_e32 11, implicit $exec
1789 ; CHECK-NEXT: %4.sub1:vreg_96 = V_MOV_B32_e32 12, implicit $exec
1790 ; CHECK-NEXT: %4.sub2:vreg_96 = V_MOV_B32_e32 13, implicit $exec
1791 ; CHECK-NEXT: S_NOP 0, implicit %4
1792 ; CHECK-NEXT: undef %5.sub0:vreg_96 = V_MOV_B32_e32 29, implicit $exec
1793 ; CHECK-NEXT: %5.sub1:vreg_96 = V_MOV_B32_e32 210, implicit $exec
1794 ; CHECK-NEXT: %5.sub2:vreg_96 = V_MOV_B32_e32 211, implicit $exec
1795 ; CHECK-NEXT: S_NOP 0, implicit %5
1796 undef %0.sub0:vreg_384 = V_MOV_B32_e32 00, implicit $exec
1797 %0.sub1:vreg_384 = V_MOV_B32_e32 01, implicit $exec
1798 %0.sub2:vreg_384 = V_MOV_B32_e32 02, implicit $exec
1799 S_NOP 0, implicit %0.sub0_sub1_sub2
1801 undef %1.sub1:vreg_384 = V_MOV_B32_e32 11, implicit $exec
1802 %1.sub2:vreg_384 = V_MOV_B32_e32 12, implicit $exec
1803 %1.sub3:vreg_384 = V_MOV_B32_e32 13, implicit $exec
1804 S_NOP 0, implicit %1.sub1_sub2_sub3
1806 undef %2.sub9:vreg_384 = V_MOV_B32_e32 29, implicit $exec
1807 %2.sub10:vreg_384 = V_MOV_B32_e32 210, implicit $exec
1808 %2.sub11:vreg_384 = V_MOV_B32_e32 211, implicit $exec
1809 S_NOP 0, implicit %2.sub9_sub10_sub11
1813 name: test_vreg_384_w128
1814 tracksRegLiveness: true
1817 ; CHECK-LABEL: name: test_vreg_384_w128
1818 ; CHECK: undef %3.sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec
1819 ; CHECK-NEXT: %3.sub1:vreg_128 = V_MOV_B32_e32 1, implicit $exec
1820 ; CHECK-NEXT: %3.sub2:vreg_128 = V_MOV_B32_e32 2, implicit $exec
1821 ; CHECK-NEXT: %3.sub3:vreg_128 = V_MOV_B32_e32 3, implicit $exec
1822 ; CHECK-NEXT: S_NOP 0, implicit %3
1823 ; CHECK-NEXT: undef %4.sub0:vreg_128 = V_MOV_B32_e32 11, implicit $exec
1824 ; CHECK-NEXT: %4.sub1:vreg_128 = V_MOV_B32_e32 12, implicit $exec
1825 ; CHECK-NEXT: %4.sub2:vreg_128 = V_MOV_B32_e32 13, implicit $exec
1826 ; CHECK-NEXT: %4.sub3:vreg_128 = V_MOV_B32_e32 14, implicit $exec
1827 ; CHECK-NEXT: S_NOP 0, implicit %4
1828 ; CHECK-NEXT: undef %5.sub0:vreg_128 = V_MOV_B32_e32 28, implicit $exec
1829 ; CHECK-NEXT: %5.sub1:vreg_128 = V_MOV_B32_e32 29, implicit $exec
1830 ; CHECK-NEXT: %5.sub2:vreg_128 = V_MOV_B32_e32 210, implicit $exec
1831 ; CHECK-NEXT: %5.sub3:vreg_128 = V_MOV_B32_e32 211, implicit $exec
1832 ; CHECK-NEXT: S_NOP 0, implicit %5
1833 undef %0.sub0:vreg_384 = V_MOV_B32_e32 00, implicit $exec
1834 %0.sub1:vreg_384 = V_MOV_B32_e32 01, implicit $exec
1835 %0.sub2:vreg_384 = V_MOV_B32_e32 02, implicit $exec
1836 %0.sub3:vreg_384 = V_MOV_B32_e32 03, implicit $exec
1837 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3
1839 undef %1.sub1:vreg_384 = V_MOV_B32_e32 11, implicit $exec
1840 %1.sub2:vreg_384 = V_MOV_B32_e32 12, implicit $exec
1841 %1.sub3:vreg_384 = V_MOV_B32_e32 13, implicit $exec
1842 %1.sub4:vreg_384 = V_MOV_B32_e32 14, implicit $exec
1843 S_NOP 0, implicit %1.sub1_sub2_sub3_sub4
1845 undef %2.sub8:vreg_384 = V_MOV_B32_e32 28, implicit $exec
1846 %2.sub9:vreg_384 = V_MOV_B32_e32 29, implicit $exec
1847 %2.sub10:vreg_384 = V_MOV_B32_e32 210, implicit $exec
1848 %2.sub11:vreg_384 = V_MOV_B32_e32 211, implicit $exec
1849 S_NOP 0, implicit %2.sub8_sub9_sub10_sub11
1853 name: test_vreg_384_w160
1854 tracksRegLiveness: true
1857 ; CHECK-LABEL: name: test_vreg_384_w160
1858 ; CHECK: undef %3.sub0:vreg_160 = V_MOV_B32_e32 0, implicit $exec
1859 ; CHECK-NEXT: %3.sub1:vreg_160 = V_MOV_B32_e32 1, implicit $exec
1860 ; CHECK-NEXT: %3.sub2:vreg_160 = V_MOV_B32_e32 2, implicit $exec
1861 ; CHECK-NEXT: %3.sub3:vreg_160 = V_MOV_B32_e32 3, implicit $exec
1862 ; CHECK-NEXT: %3.sub4:vreg_160 = V_MOV_B32_e32 4, implicit $exec
1863 ; CHECK-NEXT: S_NOP 0, implicit %3
1864 ; CHECK-NEXT: undef %4.sub0:vreg_160 = V_MOV_B32_e32 11, implicit $exec
1865 ; CHECK-NEXT: %4.sub1:vreg_160 = V_MOV_B32_e32 12, implicit $exec
1866 ; CHECK-NEXT: %4.sub2:vreg_160 = V_MOV_B32_e32 13, implicit $exec
1867 ; CHECK-NEXT: %4.sub3:vreg_160 = V_MOV_B32_e32 14, implicit $exec
1868 ; CHECK-NEXT: %4.sub4:vreg_160 = V_MOV_B32_e32 15, implicit $exec
1869 ; CHECK-NEXT: S_NOP 0, implicit %4
1870 ; CHECK-NEXT: undef %5.sub0:vreg_160 = V_MOV_B32_e32 27, implicit $exec
1871 ; CHECK-NEXT: %5.sub1:vreg_160 = V_MOV_B32_e32 28, implicit $exec
1872 ; CHECK-NEXT: %5.sub2:vreg_160 = V_MOV_B32_e32 29, implicit $exec
1873 ; CHECK-NEXT: %5.sub3:vreg_160 = V_MOV_B32_e32 210, implicit $exec
1874 ; CHECK-NEXT: %5.sub4:vreg_160 = V_MOV_B32_e32 211, implicit $exec
1875 ; CHECK-NEXT: S_NOP 0, implicit %5
1876 undef %0.sub0:vreg_384 = V_MOV_B32_e32 00, implicit $exec
1877 %0.sub1:vreg_384 = V_MOV_B32_e32 01, implicit $exec
1878 %0.sub2:vreg_384 = V_MOV_B32_e32 02, implicit $exec
1879 %0.sub3:vreg_384 = V_MOV_B32_e32 03, implicit $exec
1880 %0.sub4:vreg_384 = V_MOV_B32_e32 04, implicit $exec
1881 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4
1883 undef %1.sub1:vreg_384 = V_MOV_B32_e32 11, implicit $exec
1884 %1.sub2:vreg_384 = V_MOV_B32_e32 12, implicit $exec
1885 %1.sub3:vreg_384 = V_MOV_B32_e32 13, implicit $exec
1886 %1.sub4:vreg_384 = V_MOV_B32_e32 14, implicit $exec
1887 %1.sub5:vreg_384 = V_MOV_B32_e32 15, implicit $exec
1888 S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub5
1890 undef %2.sub7:vreg_384 = V_MOV_B32_e32 27, implicit $exec
1891 %2.sub8:vreg_384 = V_MOV_B32_e32 28, implicit $exec
1892 %2.sub9:vreg_384 = V_MOV_B32_e32 29, implicit $exec
1893 %2.sub10:vreg_384 = V_MOV_B32_e32 210, implicit $exec
1894 %2.sub11:vreg_384 = V_MOV_B32_e32 211, implicit $exec
1895 S_NOP 0, implicit %2.sub7_sub8_sub9_sub10_sub11
1899 name: test_vreg_384_w192
1900 tracksRegLiveness: true
1903 ; CHECK-LABEL: name: test_vreg_384_w192
1904 ; CHECK: undef %3.sub0:vreg_192 = V_MOV_B32_e32 0, implicit $exec
1905 ; CHECK-NEXT: %3.sub1:vreg_192 = V_MOV_B32_e32 1, implicit $exec
1906 ; CHECK-NEXT: %3.sub2:vreg_192 = V_MOV_B32_e32 2, implicit $exec
1907 ; CHECK-NEXT: %3.sub3:vreg_192 = V_MOV_B32_e32 3, implicit $exec
1908 ; CHECK-NEXT: %3.sub4:vreg_192 = V_MOV_B32_e32 4, implicit $exec
1909 ; CHECK-NEXT: %3.sub5:vreg_192 = V_MOV_B32_e32 5, implicit $exec
1910 ; CHECK-NEXT: S_NOP 0, implicit %3
1911 ; CHECK-NEXT: undef %4.sub0:vreg_192 = V_MOV_B32_e32 11, implicit $exec
1912 ; CHECK-NEXT: %4.sub1:vreg_192 = V_MOV_B32_e32 12, implicit $exec
1913 ; CHECK-NEXT: %4.sub2:vreg_192 = V_MOV_B32_e32 13, implicit $exec
1914 ; CHECK-NEXT: %4.sub3:vreg_192 = V_MOV_B32_e32 14, implicit $exec
1915 ; CHECK-NEXT: %4.sub4:vreg_192 = V_MOV_B32_e32 15, implicit $exec
1916 ; CHECK-NEXT: %4.sub5:vreg_192 = V_MOV_B32_e32 16, implicit $exec
1917 ; CHECK-NEXT: S_NOP 0, implicit %4
1918 ; CHECK-NEXT: undef %5.sub0:vreg_192 = V_MOV_B32_e32 26, implicit $exec
1919 ; CHECK-NEXT: %5.sub1:vreg_192 = V_MOV_B32_e32 27, implicit $exec
1920 ; CHECK-NEXT: %5.sub2:vreg_192 = V_MOV_B32_e32 28, implicit $exec
1921 ; CHECK-NEXT: %5.sub3:vreg_192 = V_MOV_B32_e32 29, implicit $exec
1922 ; CHECK-NEXT: %5.sub4:vreg_192 = V_MOV_B32_e32 210, implicit $exec
1923 ; CHECK-NEXT: %5.sub5:vreg_192 = V_MOV_B32_e32 211, implicit $exec
1924 ; CHECK-NEXT: S_NOP 0, implicit %5
1925 undef %0.sub0:vreg_384 = V_MOV_B32_e32 00, implicit $exec
1926 %0.sub1:vreg_384 = V_MOV_B32_e32 01, implicit $exec
1927 %0.sub2:vreg_384 = V_MOV_B32_e32 02, implicit $exec
1928 %0.sub3:vreg_384 = V_MOV_B32_e32 03, implicit $exec
1929 %0.sub4:vreg_384 = V_MOV_B32_e32 04, implicit $exec
1930 %0.sub5:vreg_384 = V_MOV_B32_e32 05, implicit $exec
1931 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5
1933 undef %1.sub1:vreg_384 = V_MOV_B32_e32 11, implicit $exec
1934 %1.sub2:vreg_384 = V_MOV_B32_e32 12, implicit $exec
1935 %1.sub3:vreg_384 = V_MOV_B32_e32 13, implicit $exec
1936 %1.sub4:vreg_384 = V_MOV_B32_e32 14, implicit $exec
1937 %1.sub5:vreg_384 = V_MOV_B32_e32 15, implicit $exec
1938 %1.sub6:vreg_384 = V_MOV_B32_e32 16, implicit $exec
1939 S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub5_sub6
1941 undef %2.sub6:vreg_384 = V_MOV_B32_e32 26, implicit $exec
1942 %2.sub7:vreg_384 = V_MOV_B32_e32 27, implicit $exec
1943 %2.sub8:vreg_384 = V_MOV_B32_e32 28, implicit $exec
1944 %2.sub9:vreg_384 = V_MOV_B32_e32 29, implicit $exec
1945 %2.sub10:vreg_384 = V_MOV_B32_e32 210, implicit $exec
1946 %2.sub11:vreg_384 = V_MOV_B32_e32 211, implicit $exec
1947 S_NOP 0, implicit %2.sub6_sub7_sub8_sub9_sub10_sub11
1951 name: test_vreg_384_w256
1952 tracksRegLiveness: true
1955 ; CHECK-LABEL: name: test_vreg_384_w256
1956 ; CHECK: undef %3.sub0:vreg_256 = V_MOV_B32_e32 0, implicit $exec
1957 ; CHECK-NEXT: %3.sub1:vreg_256 = V_MOV_B32_e32 1, implicit $exec
1958 ; CHECK-NEXT: %3.sub2:vreg_256 = V_MOV_B32_e32 2, implicit $exec
1959 ; CHECK-NEXT: %3.sub3:vreg_256 = V_MOV_B32_e32 3, implicit $exec
1960 ; CHECK-NEXT: %3.sub4:vreg_256 = V_MOV_B32_e32 4, implicit $exec
1961 ; CHECK-NEXT: %3.sub5:vreg_256 = V_MOV_B32_e32 5, implicit $exec
1962 ; CHECK-NEXT: %3.sub6:vreg_256 = V_MOV_B32_e32 6, implicit $exec
1963 ; CHECK-NEXT: %3.sub7:vreg_256 = V_MOV_B32_e32 7, implicit $exec
1964 ; CHECK-NEXT: S_NOP 0, implicit %3
1965 ; CHECK-NEXT: undef %4.sub0:vreg_256 = V_MOV_B32_e32 11, implicit $exec
1966 ; CHECK-NEXT: %4.sub1:vreg_256 = V_MOV_B32_e32 12, implicit $exec
1967 ; CHECK-NEXT: %4.sub2:vreg_256 = V_MOV_B32_e32 13, implicit $exec
1968 ; CHECK-NEXT: %4.sub3:vreg_256 = V_MOV_B32_e32 14, implicit $exec
1969 ; CHECK-NEXT: %4.sub4:vreg_256 = V_MOV_B32_e32 15, implicit $exec
1970 ; CHECK-NEXT: %4.sub5:vreg_256 = V_MOV_B32_e32 16, implicit $exec
1971 ; CHECK-NEXT: %4.sub6:vreg_256 = V_MOV_B32_e32 17, implicit $exec
1972 ; CHECK-NEXT: %4.sub7:vreg_256 = V_MOV_B32_e32 18, implicit $exec
1973 ; CHECK-NEXT: S_NOP 0, implicit %4
1974 ; CHECK-NEXT: undef %5.sub0:vreg_256 = V_MOV_B32_e32 24, implicit $exec
1975 ; CHECK-NEXT: %5.sub1:vreg_256 = V_MOV_B32_e32 25, implicit $exec
1976 ; CHECK-NEXT: %5.sub2:vreg_256 = V_MOV_B32_e32 26, implicit $exec
1977 ; CHECK-NEXT: %5.sub3:vreg_256 = V_MOV_B32_e32 27, implicit $exec
1978 ; CHECK-NEXT: %5.sub4:vreg_256 = V_MOV_B32_e32 28, implicit $exec
1979 ; CHECK-NEXT: %5.sub5:vreg_256 = V_MOV_B32_e32 29, implicit $exec
1980 ; CHECK-NEXT: %5.sub6:vreg_256 = V_MOV_B32_e32 210, implicit $exec
1981 ; CHECK-NEXT: %5.sub7:vreg_256 = V_MOV_B32_e32 211, implicit $exec
1982 ; CHECK-NEXT: S_NOP 0, implicit %5
1983 undef %0.sub0:vreg_384 = V_MOV_B32_e32 00, implicit $exec
1984 %0.sub1:vreg_384 = V_MOV_B32_e32 01, implicit $exec
1985 %0.sub2:vreg_384 = V_MOV_B32_e32 02, implicit $exec
1986 %0.sub3:vreg_384 = V_MOV_B32_e32 03, implicit $exec
1987 %0.sub4:vreg_384 = V_MOV_B32_e32 04, implicit $exec
1988 %0.sub5:vreg_384 = V_MOV_B32_e32 05, implicit $exec
1989 %0.sub6:vreg_384 = V_MOV_B32_e32 06, implicit $exec
1990 %0.sub7:vreg_384 = V_MOV_B32_e32 07, implicit $exec
1991 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7
1993 undef %1.sub1:vreg_384 = V_MOV_B32_e32 11, implicit $exec
1994 %1.sub2:vreg_384 = V_MOV_B32_e32 12, implicit $exec
1995 %1.sub3:vreg_384 = V_MOV_B32_e32 13, implicit $exec
1996 %1.sub4:vreg_384 = V_MOV_B32_e32 14, implicit $exec
1997 %1.sub5:vreg_384 = V_MOV_B32_e32 15, implicit $exec
1998 %1.sub6:vreg_384 = V_MOV_B32_e32 16, implicit $exec
1999 %1.sub7:vreg_384 = V_MOV_B32_e32 17, implicit $exec
2000 %1.sub8:vreg_384 = V_MOV_B32_e32 18, implicit $exec
2001 S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8
2003 undef %2.sub4:vreg_384 = V_MOV_B32_e32 24, implicit $exec
2004 %2.sub5:vreg_384 = V_MOV_B32_e32 25, implicit $exec
2005 %2.sub6:vreg_384 = V_MOV_B32_e32 26, implicit $exec
2006 %2.sub7:vreg_384 = V_MOV_B32_e32 27, implicit $exec
2007 %2.sub8:vreg_384 = V_MOV_B32_e32 28, implicit $exec
2008 %2.sub9:vreg_384 = V_MOV_B32_e32 29, implicit $exec
2009 %2.sub10:vreg_384 = V_MOV_B32_e32 210, implicit $exec
2010 %2.sub11:vreg_384 = V_MOV_B32_e32 211, implicit $exec
2011 S_NOP 0, implicit %2.sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11
2015 name: test_vreg_512_w32
2016 tracksRegLiveness: true
2019 ; CHECK-LABEL: name: test_vreg_512_w32
2020 ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
2021 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
2022 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 11, implicit $exec
2023 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
2024 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 215, implicit $exec
2025 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
2026 undef %0.sub0:vreg_512 = V_MOV_B32_e32 00, implicit $exec
2027 S_NOP 0, implicit %0.sub0
2029 undef %1.sub1:vreg_512 = V_MOV_B32_e32 11, implicit $exec
2030 S_NOP 0, implicit %1.sub1
2032 undef %2.sub15:vreg_512 = V_MOV_B32_e32 215, implicit $exec
2033 S_NOP 0, implicit %2.sub15
2037 name: test_vreg_512_w64
2038 tracksRegLiveness: true
2041 ; CHECK-LABEL: name: test_vreg_512_w64
2042 ; CHECK: undef %3.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
2043 ; CHECK-NEXT: %3.sub1:vreg_64 = V_MOV_B32_e32 1, implicit $exec
2044 ; CHECK-NEXT: S_NOP 0, implicit %3
2045 ; CHECK-NEXT: undef %4.sub0:vreg_64 = V_MOV_B32_e32 11, implicit $exec
2046 ; CHECK-NEXT: %4.sub1:vreg_64 = V_MOV_B32_e32 12, implicit $exec
2047 ; CHECK-NEXT: S_NOP 0, implicit %4
2048 ; CHECK-NEXT: undef %5.sub0:vreg_64 = V_MOV_B32_e32 214, implicit $exec
2049 ; CHECK-NEXT: %5.sub1:vreg_64 = V_MOV_B32_e32 215, implicit $exec
2050 ; CHECK-NEXT: S_NOP 0, implicit %5
2051 undef %0.sub0:vreg_512 = V_MOV_B32_e32 00, implicit $exec
2052 %0.sub1:vreg_512 = V_MOV_B32_e32 01, implicit $exec
2053 S_NOP 0, implicit %0.sub0_sub1
2055 undef %1.sub1:vreg_512 = V_MOV_B32_e32 11, implicit $exec
2056 %1.sub2:vreg_512 = V_MOV_B32_e32 12, implicit $exec
2057 S_NOP 0, implicit %1.sub1_sub2
2059 undef %2.sub14:vreg_512 = V_MOV_B32_e32 214, implicit $exec
2060 %2.sub15:vreg_512 = V_MOV_B32_e32 215, implicit $exec
2061 S_NOP 0, implicit %2.sub14_sub15
2065 name: test_vreg_512_w96
2066 tracksRegLiveness: true
2069 ; CHECK-LABEL: name: test_vreg_512_w96
2070 ; CHECK: undef %3.sub0:vreg_96 = V_MOV_B32_e32 0, implicit $exec
2071 ; CHECK-NEXT: %3.sub1:vreg_96 = V_MOV_B32_e32 1, implicit $exec
2072 ; CHECK-NEXT: %3.sub2:vreg_96 = V_MOV_B32_e32 2, implicit $exec
2073 ; CHECK-NEXT: S_NOP 0, implicit %3
2074 ; CHECK-NEXT: undef %4.sub0:vreg_96 = V_MOV_B32_e32 11, implicit $exec
2075 ; CHECK-NEXT: %4.sub1:vreg_96 = V_MOV_B32_e32 12, implicit $exec
2076 ; CHECK-NEXT: %4.sub2:vreg_96 = V_MOV_B32_e32 13, implicit $exec
2077 ; CHECK-NEXT: S_NOP 0, implicit %4
2078 ; CHECK-NEXT: undef %5.sub0:vreg_96 = V_MOV_B32_e32 213, implicit $exec
2079 ; CHECK-NEXT: %5.sub1:vreg_96 = V_MOV_B32_e32 214, implicit $exec
2080 ; CHECK-NEXT: %5.sub2:vreg_96 = V_MOV_B32_e32 215, implicit $exec
2081 ; CHECK-NEXT: S_NOP 0, implicit %5
2082 undef %0.sub0:vreg_512 = V_MOV_B32_e32 00, implicit $exec
2083 %0.sub1:vreg_512 = V_MOV_B32_e32 01, implicit $exec
2084 %0.sub2:vreg_512 = V_MOV_B32_e32 02, implicit $exec
2085 S_NOP 0, implicit %0.sub0_sub1_sub2
2087 undef %1.sub1:vreg_512 = V_MOV_B32_e32 11, implicit $exec
2088 %1.sub2:vreg_512 = V_MOV_B32_e32 12, implicit $exec
2089 %1.sub3:vreg_512 = V_MOV_B32_e32 13, implicit $exec
2090 S_NOP 0, implicit %1.sub1_sub2_sub3
2092 undef %2.sub13:vreg_512 = V_MOV_B32_e32 213, implicit $exec
2093 %2.sub14:vreg_512 = V_MOV_B32_e32 214, implicit $exec
2094 %2.sub15:vreg_512 = V_MOV_B32_e32 215, implicit $exec
2095 S_NOP 0, implicit %2.sub13_sub14_sub15
2099 name: test_vreg_512_w128
2100 tracksRegLiveness: true
2103 ; CHECK-LABEL: name: test_vreg_512_w128
2104 ; CHECK: undef %3.sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec
2105 ; CHECK-NEXT: %3.sub1:vreg_128 = V_MOV_B32_e32 1, implicit $exec
2106 ; CHECK-NEXT: %3.sub2:vreg_128 = V_MOV_B32_e32 2, implicit $exec
2107 ; CHECK-NEXT: %3.sub3:vreg_128 = V_MOV_B32_e32 3, implicit $exec
2108 ; CHECK-NEXT: S_NOP 0, implicit %3
2109 ; CHECK-NEXT: undef %4.sub0:vreg_128 = V_MOV_B32_e32 11, implicit $exec
2110 ; CHECK-NEXT: %4.sub1:vreg_128 = V_MOV_B32_e32 12, implicit $exec
2111 ; CHECK-NEXT: %4.sub2:vreg_128 = V_MOV_B32_e32 13, implicit $exec
2112 ; CHECK-NEXT: %4.sub3:vreg_128 = V_MOV_B32_e32 14, implicit $exec
2113 ; CHECK-NEXT: S_NOP 0, implicit %4
2114 ; CHECK-NEXT: undef %5.sub0:vreg_128 = V_MOV_B32_e32 212, implicit $exec
2115 ; CHECK-NEXT: %5.sub1:vreg_128 = V_MOV_B32_e32 213, implicit $exec
2116 ; CHECK-NEXT: %5.sub2:vreg_128 = V_MOV_B32_e32 214, implicit $exec
2117 ; CHECK-NEXT: %5.sub3:vreg_128 = V_MOV_B32_e32 215, implicit $exec
2118 ; CHECK-NEXT: S_NOP 0, implicit %5
2119 undef %0.sub0:vreg_512 = V_MOV_B32_e32 00, implicit $exec
2120 %0.sub1:vreg_512 = V_MOV_B32_e32 01, implicit $exec
2121 %0.sub2:vreg_512 = V_MOV_B32_e32 02, implicit $exec
2122 %0.sub3:vreg_512 = V_MOV_B32_e32 03, implicit $exec
2123 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3
2125 undef %1.sub1:vreg_512 = V_MOV_B32_e32 11, implicit $exec
2126 %1.sub2:vreg_512 = V_MOV_B32_e32 12, implicit $exec
2127 %1.sub3:vreg_512 = V_MOV_B32_e32 13, implicit $exec
2128 %1.sub4:vreg_512 = V_MOV_B32_e32 14, implicit $exec
2129 S_NOP 0, implicit %1.sub1_sub2_sub3_sub4
2131 undef %2.sub12:vreg_512 = V_MOV_B32_e32 212, implicit $exec
2132 %2.sub13:vreg_512 = V_MOV_B32_e32 213, implicit $exec
2133 %2.sub14:vreg_512 = V_MOV_B32_e32 214, implicit $exec
2134 %2.sub15:vreg_512 = V_MOV_B32_e32 215, implicit $exec
2135 S_NOP 0, implicit %2.sub12_sub13_sub14_sub15
2139 name: test_vreg_512_w160
2140 tracksRegLiveness: true
2143 ; CHECK-LABEL: name: test_vreg_512_w160
2144 ; CHECK: undef %3.sub0:vreg_160 = V_MOV_B32_e32 0, implicit $exec
2145 ; CHECK-NEXT: %3.sub1:vreg_160 = V_MOV_B32_e32 1, implicit $exec
2146 ; CHECK-NEXT: %3.sub2:vreg_160 = V_MOV_B32_e32 2, implicit $exec
2147 ; CHECK-NEXT: %3.sub3:vreg_160 = V_MOV_B32_e32 3, implicit $exec
2148 ; CHECK-NEXT: %3.sub4:vreg_160 = V_MOV_B32_e32 4, implicit $exec
2149 ; CHECK-NEXT: S_NOP 0, implicit %3
2150 ; CHECK-NEXT: undef %4.sub0:vreg_160 = V_MOV_B32_e32 11, implicit $exec
2151 ; CHECK-NEXT: %4.sub1:vreg_160 = V_MOV_B32_e32 12, implicit $exec
2152 ; CHECK-NEXT: %4.sub2:vreg_160 = V_MOV_B32_e32 13, implicit $exec
2153 ; CHECK-NEXT: %4.sub3:vreg_160 = V_MOV_B32_e32 14, implicit $exec
2154 ; CHECK-NEXT: %4.sub4:vreg_160 = V_MOV_B32_e32 15, implicit $exec
2155 ; CHECK-NEXT: S_NOP 0, implicit %4
2156 ; CHECK-NEXT: undef %5.sub0:vreg_160 = V_MOV_B32_e32 211, implicit $exec
2157 ; CHECK-NEXT: %5.sub1:vreg_160 = V_MOV_B32_e32 212, implicit $exec
2158 ; CHECK-NEXT: %5.sub2:vreg_160 = V_MOV_B32_e32 213, implicit $exec
2159 ; CHECK-NEXT: %5.sub3:vreg_160 = V_MOV_B32_e32 214, implicit $exec
2160 ; CHECK-NEXT: %5.sub4:vreg_160 = V_MOV_B32_e32 215, implicit $exec
2161 ; CHECK-NEXT: S_NOP 0, implicit %5
2162 undef %0.sub0:vreg_512 = V_MOV_B32_e32 00, implicit $exec
2163 %0.sub1:vreg_512 = V_MOV_B32_e32 01, implicit $exec
2164 %0.sub2:vreg_512 = V_MOV_B32_e32 02, implicit $exec
2165 %0.sub3:vreg_512 = V_MOV_B32_e32 03, implicit $exec
2166 %0.sub4:vreg_512 = V_MOV_B32_e32 04, implicit $exec
2167 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4
2169 undef %1.sub1:vreg_512 = V_MOV_B32_e32 11, implicit $exec
2170 %1.sub2:vreg_512 = V_MOV_B32_e32 12, implicit $exec
2171 %1.sub3:vreg_512 = V_MOV_B32_e32 13, implicit $exec
2172 %1.sub4:vreg_512 = V_MOV_B32_e32 14, implicit $exec
2173 %1.sub5:vreg_512 = V_MOV_B32_e32 15, implicit $exec
2174 S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub5
2176 undef %2.sub11:vreg_512 = V_MOV_B32_e32 211, implicit $exec
2177 %2.sub12:vreg_512 = V_MOV_B32_e32 212, implicit $exec
2178 %2.sub13:vreg_512 = V_MOV_B32_e32 213, implicit $exec
2179 %2.sub14:vreg_512 = V_MOV_B32_e32 214, implicit $exec
2180 %2.sub15:vreg_512 = V_MOV_B32_e32 215, implicit $exec
2181 S_NOP 0, implicit %2.sub11_sub12_sub13_sub14_sub15
2185 name: test_vreg_512_w192
2186 tracksRegLiveness: true
2189 ; CHECK-LABEL: name: test_vreg_512_w192
2190 ; CHECK: undef %3.sub0:vreg_192 = V_MOV_B32_e32 0, implicit $exec
2191 ; CHECK-NEXT: %3.sub1:vreg_192 = V_MOV_B32_e32 1, implicit $exec
2192 ; CHECK-NEXT: %3.sub2:vreg_192 = V_MOV_B32_e32 2, implicit $exec
2193 ; CHECK-NEXT: %3.sub3:vreg_192 = V_MOV_B32_e32 3, implicit $exec
2194 ; CHECK-NEXT: %3.sub4:vreg_192 = V_MOV_B32_e32 4, implicit $exec
2195 ; CHECK-NEXT: %3.sub5:vreg_192 = V_MOV_B32_e32 5, implicit $exec
2196 ; CHECK-NEXT: S_NOP 0, implicit %3
2197 ; CHECK-NEXT: undef %4.sub0:vreg_192 = V_MOV_B32_e32 11, implicit $exec
2198 ; CHECK-NEXT: %4.sub1:vreg_192 = V_MOV_B32_e32 12, implicit $exec
2199 ; CHECK-NEXT: %4.sub2:vreg_192 = V_MOV_B32_e32 13, implicit $exec
2200 ; CHECK-NEXT: %4.sub3:vreg_192 = V_MOV_B32_e32 14, implicit $exec
2201 ; CHECK-NEXT: %4.sub4:vreg_192 = V_MOV_B32_e32 15, implicit $exec
2202 ; CHECK-NEXT: %4.sub5:vreg_192 = V_MOV_B32_e32 16, implicit $exec
2203 ; CHECK-NEXT: S_NOP 0, implicit %4
2204 ; CHECK-NEXT: undef %5.sub0:vreg_192 = V_MOV_B32_e32 210, implicit $exec
2205 ; CHECK-NEXT: %5.sub1:vreg_192 = V_MOV_B32_e32 211, implicit $exec
2206 ; CHECK-NEXT: %5.sub2:vreg_192 = V_MOV_B32_e32 212, implicit $exec
2207 ; CHECK-NEXT: %5.sub3:vreg_192 = V_MOV_B32_e32 213, implicit $exec
2208 ; CHECK-NEXT: %5.sub4:vreg_192 = V_MOV_B32_e32 214, implicit $exec
2209 ; CHECK-NEXT: %5.sub5:vreg_192 = V_MOV_B32_e32 215, implicit $exec
2210 ; CHECK-NEXT: S_NOP 0, implicit %5
2211 undef %0.sub0:vreg_512 = V_MOV_B32_e32 00, implicit $exec
2212 %0.sub1:vreg_512 = V_MOV_B32_e32 01, implicit $exec
2213 %0.sub2:vreg_512 = V_MOV_B32_e32 02, implicit $exec
2214 %0.sub3:vreg_512 = V_MOV_B32_e32 03, implicit $exec
2215 %0.sub4:vreg_512 = V_MOV_B32_e32 04, implicit $exec
2216 %0.sub5:vreg_512 = V_MOV_B32_e32 05, implicit $exec
2217 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5
2219 undef %1.sub1:vreg_512 = V_MOV_B32_e32 11, implicit $exec
2220 %1.sub2:vreg_512 = V_MOV_B32_e32 12, implicit $exec
2221 %1.sub3:vreg_512 = V_MOV_B32_e32 13, implicit $exec
2222 %1.sub4:vreg_512 = V_MOV_B32_e32 14, implicit $exec
2223 %1.sub5:vreg_512 = V_MOV_B32_e32 15, implicit $exec
2224 %1.sub6:vreg_512 = V_MOV_B32_e32 16, implicit $exec
2225 S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub5_sub6
2227 undef %2.sub10:vreg_512 = V_MOV_B32_e32 210, implicit $exec
2228 %2.sub11:vreg_512 = V_MOV_B32_e32 211, implicit $exec
2229 %2.sub12:vreg_512 = V_MOV_B32_e32 212, implicit $exec
2230 %2.sub13:vreg_512 = V_MOV_B32_e32 213, implicit $exec
2231 %2.sub14:vreg_512 = V_MOV_B32_e32 214, implicit $exec
2232 %2.sub15:vreg_512 = V_MOV_B32_e32 215, implicit $exec
2233 S_NOP 0, implicit %2.sub10_sub11_sub12_sub13_sub14_sub15
2237 name: test_vreg_512_w256
2238 tracksRegLiveness: true
2241 ; CHECK-LABEL: name: test_vreg_512_w256
2242 ; CHECK: undef %3.sub0:vreg_256 = V_MOV_B32_e32 0, implicit $exec
2243 ; CHECK-NEXT: %3.sub1:vreg_256 = V_MOV_B32_e32 1, implicit $exec
2244 ; CHECK-NEXT: %3.sub2:vreg_256 = V_MOV_B32_e32 2, implicit $exec
2245 ; CHECK-NEXT: %3.sub3:vreg_256 = V_MOV_B32_e32 3, implicit $exec
2246 ; CHECK-NEXT: %3.sub4:vreg_256 = V_MOV_B32_e32 4, implicit $exec
2247 ; CHECK-NEXT: %3.sub5:vreg_256 = V_MOV_B32_e32 5, implicit $exec
2248 ; CHECK-NEXT: %3.sub6:vreg_256 = V_MOV_B32_e32 6, implicit $exec
2249 ; CHECK-NEXT: %3.sub7:vreg_256 = V_MOV_B32_e32 7, implicit $exec
2250 ; CHECK-NEXT: S_NOP 0, implicit %3
2251 ; CHECK-NEXT: undef %4.sub0:vreg_256 = V_MOV_B32_e32 11, implicit $exec
2252 ; CHECK-NEXT: %4.sub1:vreg_256 = V_MOV_B32_e32 12, implicit $exec
2253 ; CHECK-NEXT: %4.sub2:vreg_256 = V_MOV_B32_e32 13, implicit $exec
2254 ; CHECK-NEXT: %4.sub3:vreg_256 = V_MOV_B32_e32 14, implicit $exec
2255 ; CHECK-NEXT: %4.sub4:vreg_256 = V_MOV_B32_e32 15, implicit $exec
2256 ; CHECK-NEXT: %4.sub5:vreg_256 = V_MOV_B32_e32 16, implicit $exec
2257 ; CHECK-NEXT: %4.sub6:vreg_256 = V_MOV_B32_e32 17, implicit $exec
2258 ; CHECK-NEXT: %4.sub7:vreg_256 = V_MOV_B32_e32 18, implicit $exec
2259 ; CHECK-NEXT: S_NOP 0, implicit %4
2260 ; CHECK-NEXT: undef %5.sub0:vreg_256 = V_MOV_B32_e32 28, implicit $exec
2261 ; CHECK-NEXT: %5.sub1:vreg_256 = V_MOV_B32_e32 29, implicit $exec
2262 ; CHECK-NEXT: %5.sub2:vreg_256 = V_MOV_B32_e32 210, implicit $exec
2263 ; CHECK-NEXT: %5.sub3:vreg_256 = V_MOV_B32_e32 211, implicit $exec
2264 ; CHECK-NEXT: %5.sub4:vreg_256 = V_MOV_B32_e32 212, implicit $exec
2265 ; CHECK-NEXT: %5.sub5:vreg_256 = V_MOV_B32_e32 213, implicit $exec
2266 ; CHECK-NEXT: %5.sub6:vreg_256 = V_MOV_B32_e32 214, implicit $exec
2267 ; CHECK-NEXT: %5.sub7:vreg_256 = V_MOV_B32_e32 215, implicit $exec
2268 ; CHECK-NEXT: S_NOP 0, implicit %5
2269 undef %0.sub0:vreg_512 = V_MOV_B32_e32 00, implicit $exec
2270 %0.sub1:vreg_512 = V_MOV_B32_e32 01, implicit $exec
2271 %0.sub2:vreg_512 = V_MOV_B32_e32 02, implicit $exec
2272 %0.sub3:vreg_512 = V_MOV_B32_e32 03, implicit $exec
2273 %0.sub4:vreg_512 = V_MOV_B32_e32 04, implicit $exec
2274 %0.sub5:vreg_512 = V_MOV_B32_e32 05, implicit $exec
2275 %0.sub6:vreg_512 = V_MOV_B32_e32 06, implicit $exec
2276 %0.sub7:vreg_512 = V_MOV_B32_e32 07, implicit $exec
2277 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7
2279 undef %1.sub1:vreg_512 = V_MOV_B32_e32 11, implicit $exec
2280 %1.sub2:vreg_512 = V_MOV_B32_e32 12, implicit $exec
2281 %1.sub3:vreg_512 = V_MOV_B32_e32 13, implicit $exec
2282 %1.sub4:vreg_512 = V_MOV_B32_e32 14, implicit $exec
2283 %1.sub5:vreg_512 = V_MOV_B32_e32 15, implicit $exec
2284 %1.sub6:vreg_512 = V_MOV_B32_e32 16, implicit $exec
2285 %1.sub7:vreg_512 = V_MOV_B32_e32 17, implicit $exec
2286 %1.sub8:vreg_512 = V_MOV_B32_e32 18, implicit $exec
2287 S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8
2289 undef %2.sub8:vreg_512 = V_MOV_B32_e32 28, implicit $exec
2290 %2.sub9:vreg_512 = V_MOV_B32_e32 29, implicit $exec
2291 %2.sub10:vreg_512 = V_MOV_B32_e32 210, implicit $exec
2292 %2.sub11:vreg_512 = V_MOV_B32_e32 211, implicit $exec
2293 %2.sub12:vreg_512 = V_MOV_B32_e32 212, implicit $exec
2294 %2.sub13:vreg_512 = V_MOV_B32_e32 213, implicit $exec
2295 %2.sub14:vreg_512 = V_MOV_B32_e32 214, implicit $exec
2296 %2.sub15:vreg_512 = V_MOV_B32_e32 215, implicit $exec
2297 S_NOP 0, implicit %2.sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15
2301 name: test_vreg_1024_w32
2302 tracksRegLiveness: true
2305 ; CHECK-LABEL: name: test_vreg_1024_w32
2306 ; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
2307 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_]]
2308 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 11, implicit $exec
2309 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
2310 ; CHECK-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 231, implicit $exec
2311 ; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_2]]
2312 undef %0.sub0:vreg_1024 = V_MOV_B32_e32 00, implicit $exec
2313 S_NOP 0, implicit %0.sub0
2315 undef %1.sub1:vreg_1024 = V_MOV_B32_e32 11, implicit $exec
2316 S_NOP 0, implicit %1.sub1
2318 undef %2.sub31:vreg_1024 = V_MOV_B32_e32 231, implicit $exec
2319 S_NOP 0, implicit %2.sub31
2323 name: test_vreg_1024_w64
2324 tracksRegLiveness: true
2327 ; CHECK-LABEL: name: test_vreg_1024_w64
2328 ; CHECK: undef %3.sub0:vreg_64 = V_MOV_B32_e32 0, implicit $exec
2329 ; CHECK-NEXT: %3.sub1:vreg_64 = V_MOV_B32_e32 1, implicit $exec
2330 ; CHECK-NEXT: S_NOP 0, implicit %3
2331 ; CHECK-NEXT: undef %4.sub0:vreg_64 = V_MOV_B32_e32 11, implicit $exec
2332 ; CHECK-NEXT: %4.sub1:vreg_64 = V_MOV_B32_e32 12, implicit $exec
2333 ; CHECK-NEXT: S_NOP 0, implicit %4
2334 ; CHECK-NEXT: undef %5.sub0:vreg_64 = V_MOV_B32_e32 230, implicit $exec
2335 ; CHECK-NEXT: %5.sub1:vreg_64 = V_MOV_B32_e32 231, implicit $exec
2336 ; CHECK-NEXT: S_NOP 0, implicit %5
2337 undef %0.sub0:vreg_1024 = V_MOV_B32_e32 00, implicit $exec
2338 %0.sub1:vreg_1024 = V_MOV_B32_e32 01, implicit $exec
2339 S_NOP 0, implicit %0.sub0_sub1
2341 undef %1.sub1:vreg_1024 = V_MOV_B32_e32 11, implicit $exec
2342 %1.sub2:vreg_1024 = V_MOV_B32_e32 12, implicit $exec
2343 S_NOP 0, implicit %1.sub1_sub2
2345 undef %2.sub30:vreg_1024 = V_MOV_B32_e32 230, implicit $exec
2346 %2.sub31:vreg_1024 = V_MOV_B32_e32 231, implicit $exec
2347 S_NOP 0, implicit %2.sub30_sub31
2351 name: test_vreg_1024_w96
2352 tracksRegLiveness: true
2355 ; CHECK-LABEL: name: test_vreg_1024_w96
2356 ; CHECK: undef %3.sub0:vreg_96 = V_MOV_B32_e32 0, implicit $exec
2357 ; CHECK-NEXT: %3.sub1:vreg_96 = V_MOV_B32_e32 1, implicit $exec
2358 ; CHECK-NEXT: %3.sub2:vreg_96 = V_MOV_B32_e32 2, implicit $exec
2359 ; CHECK-NEXT: S_NOP 0, implicit %3
2360 ; CHECK-NEXT: undef %4.sub0:vreg_96 = V_MOV_B32_e32 11, implicit $exec
2361 ; CHECK-NEXT: %4.sub1:vreg_96 = V_MOV_B32_e32 12, implicit $exec
2362 ; CHECK-NEXT: %4.sub2:vreg_96 = V_MOV_B32_e32 13, implicit $exec
2363 ; CHECK-NEXT: S_NOP 0, implicit %4
2364 ; CHECK-NEXT: undef %5.sub0:vreg_96 = V_MOV_B32_e32 229, implicit $exec
2365 ; CHECK-NEXT: %5.sub1:vreg_96 = V_MOV_B32_e32 230, implicit $exec
2366 ; CHECK-NEXT: %5.sub2:vreg_96 = V_MOV_B32_e32 231, implicit $exec
2367 ; CHECK-NEXT: S_NOP 0, implicit %5
2368 undef %0.sub0:vreg_1024 = V_MOV_B32_e32 00, implicit $exec
2369 %0.sub1:vreg_1024 = V_MOV_B32_e32 01, implicit $exec
2370 %0.sub2:vreg_1024 = V_MOV_B32_e32 02, implicit $exec
2371 S_NOP 0, implicit %0.sub0_sub1_sub2
2373 undef %1.sub1:vreg_1024 = V_MOV_B32_e32 11, implicit $exec
2374 %1.sub2:vreg_1024 = V_MOV_B32_e32 12, implicit $exec
2375 %1.sub3:vreg_1024 = V_MOV_B32_e32 13, implicit $exec
2376 S_NOP 0, implicit %1.sub1_sub2_sub3
2378 undef %2.sub29:vreg_1024 = V_MOV_B32_e32 229, implicit $exec
2379 %2.sub30:vreg_1024 = V_MOV_B32_e32 230, implicit $exec
2380 %2.sub31:vreg_1024 = V_MOV_B32_e32 231, implicit $exec
2381 S_NOP 0, implicit %2.sub29_sub30_sub31
2385 name: test_vreg_1024_w128
2386 tracksRegLiveness: true
2389 ; CHECK-LABEL: name: test_vreg_1024_w128
2390 ; CHECK: undef %3.sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec
2391 ; CHECK-NEXT: %3.sub1:vreg_128 = V_MOV_B32_e32 1, implicit $exec
2392 ; CHECK-NEXT: %3.sub2:vreg_128 = V_MOV_B32_e32 2, implicit $exec
2393 ; CHECK-NEXT: %3.sub3:vreg_128 = V_MOV_B32_e32 3, implicit $exec
2394 ; CHECK-NEXT: S_NOP 0, implicit %3
2395 ; CHECK-NEXT: undef %4.sub0:vreg_128 = V_MOV_B32_e32 11, implicit $exec
2396 ; CHECK-NEXT: %4.sub1:vreg_128 = V_MOV_B32_e32 12, implicit $exec
2397 ; CHECK-NEXT: %4.sub2:vreg_128 = V_MOV_B32_e32 13, implicit $exec
2398 ; CHECK-NEXT: %4.sub3:vreg_128 = V_MOV_B32_e32 14, implicit $exec
2399 ; CHECK-NEXT: S_NOP 0, implicit %4
2400 ; CHECK-NEXT: undef %5.sub0:vreg_128 = V_MOV_B32_e32 228, implicit $exec
2401 ; CHECK-NEXT: %5.sub1:vreg_128 = V_MOV_B32_e32 229, implicit $exec
2402 ; CHECK-NEXT: %5.sub2:vreg_128 = V_MOV_B32_e32 230, implicit $exec
2403 ; CHECK-NEXT: %5.sub3:vreg_128 = V_MOV_B32_e32 231, implicit $exec
2404 ; CHECK-NEXT: S_NOP 0, implicit %5
2405 undef %0.sub0:vreg_1024 = V_MOV_B32_e32 00, implicit $exec
2406 %0.sub1:vreg_1024 = V_MOV_B32_e32 01, implicit $exec
2407 %0.sub2:vreg_1024 = V_MOV_B32_e32 02, implicit $exec
2408 %0.sub3:vreg_1024 = V_MOV_B32_e32 03, implicit $exec
2409 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3
2411 undef %1.sub1:vreg_1024 = V_MOV_B32_e32 11, implicit $exec
2412 %1.sub2:vreg_1024 = V_MOV_B32_e32 12, implicit $exec
2413 %1.sub3:vreg_1024 = V_MOV_B32_e32 13, implicit $exec
2414 %1.sub4:vreg_1024 = V_MOV_B32_e32 14, implicit $exec
2415 S_NOP 0, implicit %1.sub1_sub2_sub3_sub4
2417 undef %2.sub28:vreg_1024 = V_MOV_B32_e32 228, implicit $exec
2418 %2.sub29:vreg_1024 = V_MOV_B32_e32 229, implicit $exec
2419 %2.sub30:vreg_1024 = V_MOV_B32_e32 230, implicit $exec
2420 %2.sub31:vreg_1024 = V_MOV_B32_e32 231, implicit $exec
2421 S_NOP 0, implicit %2.sub28_sub29_sub30_sub31
2425 name: test_vreg_1024_w160
2426 tracksRegLiveness: true
2429 ; CHECK-LABEL: name: test_vreg_1024_w160
2430 ; CHECK: undef %3.sub0:vreg_160 = V_MOV_B32_e32 0, implicit $exec
2431 ; CHECK-NEXT: %3.sub1:vreg_160 = V_MOV_B32_e32 1, implicit $exec
2432 ; CHECK-NEXT: %3.sub2:vreg_160 = V_MOV_B32_e32 2, implicit $exec
2433 ; CHECK-NEXT: %3.sub3:vreg_160 = V_MOV_B32_e32 3, implicit $exec
2434 ; CHECK-NEXT: %3.sub4:vreg_160 = V_MOV_B32_e32 4, implicit $exec
2435 ; CHECK-NEXT: S_NOP 0, implicit %3
2436 ; CHECK-NEXT: undef %4.sub0:vreg_160 = V_MOV_B32_e32 11, implicit $exec
2437 ; CHECK-NEXT: %4.sub1:vreg_160 = V_MOV_B32_e32 12, implicit $exec
2438 ; CHECK-NEXT: %4.sub2:vreg_160 = V_MOV_B32_e32 13, implicit $exec
2439 ; CHECK-NEXT: %4.sub3:vreg_160 = V_MOV_B32_e32 14, implicit $exec
2440 ; CHECK-NEXT: %4.sub4:vreg_160 = V_MOV_B32_e32 15, implicit $exec
2441 ; CHECK-NEXT: S_NOP 0, implicit %4
2442 ; CHECK-NEXT: undef %5.sub0:vreg_160 = V_MOV_B32_e32 227, implicit $exec
2443 ; CHECK-NEXT: %5.sub1:vreg_160 = V_MOV_B32_e32 228, implicit $exec
2444 ; CHECK-NEXT: %5.sub2:vreg_160 = V_MOV_B32_e32 229, implicit $exec
2445 ; CHECK-NEXT: %5.sub3:vreg_160 = V_MOV_B32_e32 230, implicit $exec
2446 ; CHECK-NEXT: %5.sub4:vreg_160 = V_MOV_B32_e32 231, implicit $exec
2447 ; CHECK-NEXT: S_NOP 0, implicit %5
2448 undef %0.sub0:vreg_1024 = V_MOV_B32_e32 00, implicit $exec
2449 %0.sub1:vreg_1024 = V_MOV_B32_e32 01, implicit $exec
2450 %0.sub2:vreg_1024 = V_MOV_B32_e32 02, implicit $exec
2451 %0.sub3:vreg_1024 = V_MOV_B32_e32 03, implicit $exec
2452 %0.sub4:vreg_1024 = V_MOV_B32_e32 04, implicit $exec
2453 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4
2455 undef %1.sub1:vreg_1024 = V_MOV_B32_e32 11, implicit $exec
2456 %1.sub2:vreg_1024 = V_MOV_B32_e32 12, implicit $exec
2457 %1.sub3:vreg_1024 = V_MOV_B32_e32 13, implicit $exec
2458 %1.sub4:vreg_1024 = V_MOV_B32_e32 14, implicit $exec
2459 %1.sub5:vreg_1024 = V_MOV_B32_e32 15, implicit $exec
2460 S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub5
2462 undef %2.sub27:vreg_1024 = V_MOV_B32_e32 227, implicit $exec
2463 %2.sub28:vreg_1024 = V_MOV_B32_e32 228, implicit $exec
2464 %2.sub29:vreg_1024 = V_MOV_B32_e32 229, implicit $exec
2465 %2.sub30:vreg_1024 = V_MOV_B32_e32 230, implicit $exec
2466 %2.sub31:vreg_1024 = V_MOV_B32_e32 231, implicit $exec
2467 S_NOP 0, implicit %2.sub27_sub28_sub29_sub30_sub31
2471 name: test_vreg_1024_w192
2472 tracksRegLiveness: true
2475 ; CHECK-LABEL: name: test_vreg_1024_w192
2476 ; CHECK: undef %3.sub0:vreg_192 = V_MOV_B32_e32 0, implicit $exec
2477 ; CHECK-NEXT: %3.sub1:vreg_192 = V_MOV_B32_e32 1, implicit $exec
2478 ; CHECK-NEXT: %3.sub2:vreg_192 = V_MOV_B32_e32 2, implicit $exec
2479 ; CHECK-NEXT: %3.sub3:vreg_192 = V_MOV_B32_e32 3, implicit $exec
2480 ; CHECK-NEXT: %3.sub4:vreg_192 = V_MOV_B32_e32 4, implicit $exec
2481 ; CHECK-NEXT: %3.sub5:vreg_192 = V_MOV_B32_e32 5, implicit $exec
2482 ; CHECK-NEXT: S_NOP 0, implicit %3
2483 ; CHECK-NEXT: undef %4.sub0:vreg_192 = V_MOV_B32_e32 11, implicit $exec
2484 ; CHECK-NEXT: %4.sub1:vreg_192 = V_MOV_B32_e32 12, implicit $exec
2485 ; CHECK-NEXT: %4.sub2:vreg_192 = V_MOV_B32_e32 13, implicit $exec
2486 ; CHECK-NEXT: %4.sub3:vreg_192 = V_MOV_B32_e32 14, implicit $exec
2487 ; CHECK-NEXT: %4.sub4:vreg_192 = V_MOV_B32_e32 15, implicit $exec
2488 ; CHECK-NEXT: %4.sub5:vreg_192 = V_MOV_B32_e32 16, implicit $exec
2489 ; CHECK-NEXT: S_NOP 0, implicit %4
2490 ; CHECK-NEXT: undef %5.sub0:vreg_192 = V_MOV_B32_e32 226, implicit $exec
2491 ; CHECK-NEXT: %5.sub1:vreg_192 = V_MOV_B32_e32 227, implicit $exec
2492 ; CHECK-NEXT: %5.sub2:vreg_192 = V_MOV_B32_e32 228, implicit $exec
2493 ; CHECK-NEXT: %5.sub3:vreg_192 = V_MOV_B32_e32 229, implicit $exec
2494 ; CHECK-NEXT: %5.sub4:vreg_192 = V_MOV_B32_e32 230, implicit $exec
2495 ; CHECK-NEXT: %5.sub5:vreg_192 = V_MOV_B32_e32 231, implicit $exec
2496 ; CHECK-NEXT: S_NOP 0, implicit %5
2497 undef %0.sub0:vreg_1024 = V_MOV_B32_e32 00, implicit $exec
2498 %0.sub1:vreg_1024 = V_MOV_B32_e32 01, implicit $exec
2499 %0.sub2:vreg_1024 = V_MOV_B32_e32 02, implicit $exec
2500 %0.sub3:vreg_1024 = V_MOV_B32_e32 03, implicit $exec
2501 %0.sub4:vreg_1024 = V_MOV_B32_e32 04, implicit $exec
2502 %0.sub5:vreg_1024 = V_MOV_B32_e32 05, implicit $exec
2503 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5
2505 undef %1.sub1:vreg_1024 = V_MOV_B32_e32 11, implicit $exec
2506 %1.sub2:vreg_1024 = V_MOV_B32_e32 12, implicit $exec
2507 %1.sub3:vreg_1024 = V_MOV_B32_e32 13, implicit $exec
2508 %1.sub4:vreg_1024 = V_MOV_B32_e32 14, implicit $exec
2509 %1.sub5:vreg_1024 = V_MOV_B32_e32 15, implicit $exec
2510 %1.sub6:vreg_1024 = V_MOV_B32_e32 16, implicit $exec
2511 S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub5_sub6
2513 undef %2.sub26:vreg_1024 = V_MOV_B32_e32 226, implicit $exec
2514 %2.sub27:vreg_1024 = V_MOV_B32_e32 227, implicit $exec
2515 %2.sub28:vreg_1024 = V_MOV_B32_e32 228, implicit $exec
2516 %2.sub29:vreg_1024 = V_MOV_B32_e32 229, implicit $exec
2517 %2.sub30:vreg_1024 = V_MOV_B32_e32 230, implicit $exec
2518 %2.sub31:vreg_1024 = V_MOV_B32_e32 231, implicit $exec
2519 S_NOP 0, implicit %2.sub26_sub27_sub28_sub29_sub30_sub31
2523 name: test_vreg_1024_w256
2524 tracksRegLiveness: true
2527 ; CHECK-LABEL: name: test_vreg_1024_w256
2528 ; CHECK: undef %3.sub0:vreg_256 = V_MOV_B32_e32 0, implicit $exec
2529 ; CHECK-NEXT: %3.sub1:vreg_256 = V_MOV_B32_e32 1, implicit $exec
2530 ; CHECK-NEXT: %3.sub2:vreg_256 = V_MOV_B32_e32 2, implicit $exec
2531 ; CHECK-NEXT: %3.sub3:vreg_256 = V_MOV_B32_e32 3, implicit $exec
2532 ; CHECK-NEXT: %3.sub4:vreg_256 = V_MOV_B32_e32 4, implicit $exec
2533 ; CHECK-NEXT: %3.sub5:vreg_256 = V_MOV_B32_e32 5, implicit $exec
2534 ; CHECK-NEXT: %3.sub6:vreg_256 = V_MOV_B32_e32 6, implicit $exec
2535 ; CHECK-NEXT: %3.sub7:vreg_256 = V_MOV_B32_e32 7, implicit $exec
2536 ; CHECK-NEXT: S_NOP 0, implicit %3
2537 ; CHECK-NEXT: undef %4.sub0:vreg_256 = V_MOV_B32_e32 11, implicit $exec
2538 ; CHECK-NEXT: %4.sub1:vreg_256 = V_MOV_B32_e32 12, implicit $exec
2539 ; CHECK-NEXT: %4.sub2:vreg_256 = V_MOV_B32_e32 13, implicit $exec
2540 ; CHECK-NEXT: %4.sub3:vreg_256 = V_MOV_B32_e32 14, implicit $exec
2541 ; CHECK-NEXT: %4.sub4:vreg_256 = V_MOV_B32_e32 15, implicit $exec
2542 ; CHECK-NEXT: %4.sub5:vreg_256 = V_MOV_B32_e32 16, implicit $exec
2543 ; CHECK-NEXT: %4.sub6:vreg_256 = V_MOV_B32_e32 17, implicit $exec
2544 ; CHECK-NEXT: %4.sub7:vreg_256 = V_MOV_B32_e32 18, implicit $exec
2545 ; CHECK-NEXT: S_NOP 0, implicit %4
2546 ; CHECK-NEXT: undef %5.sub0:vreg_256 = V_MOV_B32_e32 224, implicit $exec
2547 ; CHECK-NEXT: %5.sub1:vreg_256 = V_MOV_B32_e32 225, implicit $exec
2548 ; CHECK-NEXT: %5.sub2:vreg_256 = V_MOV_B32_e32 226, implicit $exec
2549 ; CHECK-NEXT: %5.sub3:vreg_256 = V_MOV_B32_e32 227, implicit $exec
2550 ; CHECK-NEXT: %5.sub4:vreg_256 = V_MOV_B32_e32 228, implicit $exec
2551 ; CHECK-NEXT: %5.sub5:vreg_256 = V_MOV_B32_e32 229, implicit $exec
2552 ; CHECK-NEXT: %5.sub6:vreg_256 = V_MOV_B32_e32 230, implicit $exec
2553 ; CHECK-NEXT: %5.sub7:vreg_256 = V_MOV_B32_e32 231, implicit $exec
2554 ; CHECK-NEXT: S_NOP 0, implicit %5
2555 undef %0.sub0:vreg_1024 = V_MOV_B32_e32 00, implicit $exec
2556 %0.sub1:vreg_1024 = V_MOV_B32_e32 01, implicit $exec
2557 %0.sub2:vreg_1024 = V_MOV_B32_e32 02, implicit $exec
2558 %0.sub3:vreg_1024 = V_MOV_B32_e32 03, implicit $exec
2559 %0.sub4:vreg_1024 = V_MOV_B32_e32 04, implicit $exec
2560 %0.sub5:vreg_1024 = V_MOV_B32_e32 05, implicit $exec
2561 %0.sub6:vreg_1024 = V_MOV_B32_e32 06, implicit $exec
2562 %0.sub7:vreg_1024 = V_MOV_B32_e32 07, implicit $exec
2563 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7
2565 undef %1.sub1:vreg_1024 = V_MOV_B32_e32 11, implicit $exec
2566 %1.sub2:vreg_1024 = V_MOV_B32_e32 12, implicit $exec
2567 %1.sub3:vreg_1024 = V_MOV_B32_e32 13, implicit $exec
2568 %1.sub4:vreg_1024 = V_MOV_B32_e32 14, implicit $exec
2569 %1.sub5:vreg_1024 = V_MOV_B32_e32 15, implicit $exec
2570 %1.sub6:vreg_1024 = V_MOV_B32_e32 16, implicit $exec
2571 %1.sub7:vreg_1024 = V_MOV_B32_e32 17, implicit $exec
2572 %1.sub8:vreg_1024 = V_MOV_B32_e32 18, implicit $exec
2573 S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8
2575 undef %2.sub24:vreg_1024 = V_MOV_B32_e32 224, implicit $exec
2576 %2.sub25:vreg_1024 = V_MOV_B32_e32 225, implicit $exec
2577 %2.sub26:vreg_1024 = V_MOV_B32_e32 226, implicit $exec
2578 %2.sub27:vreg_1024 = V_MOV_B32_e32 227, implicit $exec
2579 %2.sub28:vreg_1024 = V_MOV_B32_e32 228, implicit $exec
2580 %2.sub29:vreg_1024 = V_MOV_B32_e32 229, implicit $exec
2581 %2.sub30:vreg_1024 = V_MOV_B32_e32 230, implicit $exec
2582 %2.sub31:vreg_1024 = V_MOV_B32_e32 231, implicit $exec
2583 S_NOP 0, implicit %2.sub24_sub25_sub26_sub27_sub28_sub29_sub30_sub31
2587 name: test_vreg_1024_w512
2588 tracksRegLiveness: true
2591 ; CHECK-LABEL: name: test_vreg_1024_w512
2592 ; CHECK: undef %3.sub0:vreg_512 = V_MOV_B32_e32 0, implicit $exec
2593 ; CHECK-NEXT: %3.sub1:vreg_512 = V_MOV_B32_e32 1, implicit $exec
2594 ; CHECK-NEXT: %3.sub2:vreg_512 = V_MOV_B32_e32 2, implicit $exec
2595 ; CHECK-NEXT: %3.sub3:vreg_512 = V_MOV_B32_e32 3, implicit $exec
2596 ; CHECK-NEXT: %3.sub4:vreg_512 = V_MOV_B32_e32 4, implicit $exec
2597 ; CHECK-NEXT: %3.sub5:vreg_512 = V_MOV_B32_e32 5, implicit $exec
2598 ; CHECK-NEXT: %3.sub6:vreg_512 = V_MOV_B32_e32 6, implicit $exec
2599 ; CHECK-NEXT: %3.sub7:vreg_512 = V_MOV_B32_e32 7, implicit $exec
2600 ; CHECK-NEXT: %3.sub8:vreg_512 = V_MOV_B32_e32 8, implicit $exec
2601 ; CHECK-NEXT: %3.sub9:vreg_512 = V_MOV_B32_e32 9, implicit $exec
2602 ; CHECK-NEXT: %3.sub10:vreg_512 = V_MOV_B32_e32 10, implicit $exec
2603 ; CHECK-NEXT: %3.sub11:vreg_512 = V_MOV_B32_e32 11, implicit $exec
2604 ; CHECK-NEXT: %3.sub12:vreg_512 = V_MOV_B32_e32 12, implicit $exec
2605 ; CHECK-NEXT: %3.sub13:vreg_512 = V_MOV_B32_e32 13, implicit $exec
2606 ; CHECK-NEXT: %3.sub14:vreg_512 = V_MOV_B32_e32 14, implicit $exec
2607 ; CHECK-NEXT: %3.sub15:vreg_512 = V_MOV_B32_e32 15, implicit $exec
2608 ; CHECK-NEXT: S_NOP 0, implicit %3
2609 ; CHECK-NEXT: undef %4.sub0:vreg_512 = V_MOV_B32_e32 11, implicit $exec
2610 ; CHECK-NEXT: %4.sub1:vreg_512 = V_MOV_B32_e32 12, implicit $exec
2611 ; CHECK-NEXT: %4.sub2:vreg_512 = V_MOV_B32_e32 13, implicit $exec
2612 ; CHECK-NEXT: %4.sub3:vreg_512 = V_MOV_B32_e32 14, implicit $exec
2613 ; CHECK-NEXT: %4.sub4:vreg_512 = V_MOV_B32_e32 15, implicit $exec
2614 ; CHECK-NEXT: %4.sub5:vreg_512 = V_MOV_B32_e32 16, implicit $exec
2615 ; CHECK-NEXT: %4.sub6:vreg_512 = V_MOV_B32_e32 17, implicit $exec
2616 ; CHECK-NEXT: %4.sub7:vreg_512 = V_MOV_B32_e32 18, implicit $exec
2617 ; CHECK-NEXT: %4.sub8:vreg_512 = V_MOV_B32_e32 19, implicit $exec
2618 ; CHECK-NEXT: %4.sub9:vreg_512 = V_MOV_B32_e32 110, implicit $exec
2619 ; CHECK-NEXT: %4.sub10:vreg_512 = V_MOV_B32_e32 111, implicit $exec
2620 ; CHECK-NEXT: %4.sub11:vreg_512 = V_MOV_B32_e32 112, implicit $exec
2621 ; CHECK-NEXT: %4.sub12:vreg_512 = V_MOV_B32_e32 113, implicit $exec
2622 ; CHECK-NEXT: %4.sub13:vreg_512 = V_MOV_B32_e32 114, implicit $exec
2623 ; CHECK-NEXT: %4.sub14:vreg_512 = V_MOV_B32_e32 115, implicit $exec
2624 ; CHECK-NEXT: %4.sub15:vreg_512 = V_MOV_B32_e32 116, implicit $exec
2625 ; CHECK-NEXT: S_NOP 0, implicit %4
2626 ; CHECK-NEXT: undef %5.sub0:vreg_512 = V_MOV_B32_e32 216, implicit $exec
2627 ; CHECK-NEXT: %5.sub1:vreg_512 = V_MOV_B32_e32 217, implicit $exec
2628 ; CHECK-NEXT: %5.sub2:vreg_512 = V_MOV_B32_e32 218, implicit $exec
2629 ; CHECK-NEXT: %5.sub3:vreg_512 = V_MOV_B32_e32 219, implicit $exec
2630 ; CHECK-NEXT: %5.sub4:vreg_512 = V_MOV_B32_e32 220, implicit $exec
2631 ; CHECK-NEXT: %5.sub5:vreg_512 = V_MOV_B32_e32 221, implicit $exec
2632 ; CHECK-NEXT: %5.sub6:vreg_512 = V_MOV_B32_e32 222, implicit $exec
2633 ; CHECK-NEXT: %5.sub7:vreg_512 = V_MOV_B32_e32 223, implicit $exec
2634 ; CHECK-NEXT: %5.sub8:vreg_512 = V_MOV_B32_e32 224, implicit $exec
2635 ; CHECK-NEXT: %5.sub9:vreg_512 = V_MOV_B32_e32 225, implicit $exec
2636 ; CHECK-NEXT: %5.sub10:vreg_512 = V_MOV_B32_e32 226, implicit $exec
2637 ; CHECK-NEXT: %5.sub11:vreg_512 = V_MOV_B32_e32 227, implicit $exec
2638 ; CHECK-NEXT: %5.sub12:vreg_512 = V_MOV_B32_e32 228, implicit $exec
2639 ; CHECK-NEXT: %5.sub13:vreg_512 = V_MOV_B32_e32 229, implicit $exec
2640 ; CHECK-NEXT: %5.sub14:vreg_512 = V_MOV_B32_e32 230, implicit $exec
2641 ; CHECK-NEXT: %5.sub15:vreg_512 = V_MOV_B32_e32 231, implicit $exec
2642 ; CHECK-NEXT: S_NOP 0, implicit %5
2643 undef %0.sub0:vreg_1024 = V_MOV_B32_e32 00, implicit $exec
2644 %0.sub1:vreg_1024 = V_MOV_B32_e32 01, implicit $exec
2645 %0.sub2:vreg_1024 = V_MOV_B32_e32 02, implicit $exec
2646 %0.sub3:vreg_1024 = V_MOV_B32_e32 03, implicit $exec
2647 %0.sub4:vreg_1024 = V_MOV_B32_e32 04, implicit $exec
2648 %0.sub5:vreg_1024 = V_MOV_B32_e32 05, implicit $exec
2649 %0.sub6:vreg_1024 = V_MOV_B32_e32 06, implicit $exec
2650 %0.sub7:vreg_1024 = V_MOV_B32_e32 07, implicit $exec
2651 %0.sub8:vreg_1024 = V_MOV_B32_e32 08, implicit $exec
2652 %0.sub9:vreg_1024 = V_MOV_B32_e32 09, implicit $exec
2653 %0.sub10:vreg_1024 = V_MOV_B32_e32 010, implicit $exec
2654 %0.sub11:vreg_1024 = V_MOV_B32_e32 011, implicit $exec
2655 %0.sub12:vreg_1024 = V_MOV_B32_e32 012, implicit $exec
2656 %0.sub13:vreg_1024 = V_MOV_B32_e32 013, implicit $exec
2657 %0.sub14:vreg_1024 = V_MOV_B32_e32 014, implicit $exec
2658 %0.sub15:vreg_1024 = V_MOV_B32_e32 015, implicit $exec
2659 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15
2661 undef %1.sub1:vreg_1024 = V_MOV_B32_e32 11, implicit $exec
2662 %1.sub2:vreg_1024 = V_MOV_B32_e32 12, implicit $exec
2663 %1.sub3:vreg_1024 = V_MOV_B32_e32 13, implicit $exec
2664 %1.sub4:vreg_1024 = V_MOV_B32_e32 14, implicit $exec
2665 %1.sub5:vreg_1024 = V_MOV_B32_e32 15, implicit $exec
2666 %1.sub6:vreg_1024 = V_MOV_B32_e32 16, implicit $exec
2667 %1.sub7:vreg_1024 = V_MOV_B32_e32 17, implicit $exec
2668 %1.sub8:vreg_1024 = V_MOV_B32_e32 18, implicit $exec
2669 %1.sub9:vreg_1024 = V_MOV_B32_e32 19, implicit $exec
2670 %1.sub10:vreg_1024 = V_MOV_B32_e32 110, implicit $exec
2671 %1.sub11:vreg_1024 = V_MOV_B32_e32 111, implicit $exec
2672 %1.sub12:vreg_1024 = V_MOV_B32_e32 112, implicit $exec
2673 %1.sub13:vreg_1024 = V_MOV_B32_e32 113, implicit $exec
2674 %1.sub14:vreg_1024 = V_MOV_B32_e32 114, implicit $exec
2675 %1.sub15:vreg_1024 = V_MOV_B32_e32 115, implicit $exec
2676 %1.sub16:vreg_1024 = V_MOV_B32_e32 116, implicit $exec
2677 S_NOP 0, implicit %1.sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16
2679 undef %2.sub16:vreg_1024 = V_MOV_B32_e32 216, implicit $exec
2680 %2.sub17:vreg_1024 = V_MOV_B32_e32 217, implicit $exec
2681 %2.sub18:vreg_1024 = V_MOV_B32_e32 218, implicit $exec
2682 %2.sub19:vreg_1024 = V_MOV_B32_e32 219, implicit $exec
2683 %2.sub20:vreg_1024 = V_MOV_B32_e32 220, implicit $exec
2684 %2.sub21:vreg_1024 = V_MOV_B32_e32 221, implicit $exec
2685 %2.sub22:vreg_1024 = V_MOV_B32_e32 222, implicit $exec
2686 %2.sub23:vreg_1024 = V_MOV_B32_e32 223, implicit $exec
2687 %2.sub24:vreg_1024 = V_MOV_B32_e32 224, implicit $exec
2688 %2.sub25:vreg_1024 = V_MOV_B32_e32 225, implicit $exec
2689 %2.sub26:vreg_1024 = V_MOV_B32_e32 226, implicit $exec
2690 %2.sub27:vreg_1024 = V_MOV_B32_e32 227, implicit $exec
2691 %2.sub28:vreg_1024 = V_MOV_B32_e32 228, implicit $exec
2692 %2.sub29:vreg_1024 = V_MOV_B32_e32 229, implicit $exec
2693 %2.sub30:vreg_1024 = V_MOV_B32_e32 230, implicit $exec
2694 %2.sub31:vreg_1024 = V_MOV_B32_e32 231, implicit $exec
2695 S_NOP 0, implicit %2.sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_sub28_sub29_sub30_sub31
2699 name: test_subregs_composition_vreg_1024_align2
2700 tracksRegLiveness: true
2703 ; CHECK-LABEL: name: test_subregs_composition_vreg_1024_align2
2704 ; CHECK: undef %4.sub0:vreg_160_align2 = V_MOV_B32_e32 12, implicit $exec
2705 ; CHECK-NEXT: %4.sub2:vreg_160_align2 = V_MOV_B32_e32 14, implicit $exec
2706 ; CHECK-NEXT: S_NOP 0, implicit %4.sub0_sub1_sub2
2707 ; CHECK-NEXT: S_NOP 0, implicit %4.sub2_sub3_sub4
2708 ; CHECK-NEXT: undef %5.sub0:vreg_192_align2 = V_MOV_B32_e32 22, implicit $exec
2709 ; CHECK-NEXT: %5.sub2:vreg_192_align2 = V_MOV_B32_e32 24, implicit $exec
2710 ; CHECK-NEXT: S_NOP 0, implicit %5.sub0_sub1_sub2_sub3
2711 ; CHECK-NEXT: S_NOP 0, implicit %5.sub2_sub3_sub4_sub5
2712 ; CHECK-NEXT: undef %6.sub0:vreg_224_align2 = V_MOV_B32_e32 32, implicit $exec
2713 ; CHECK-NEXT: %6.sub2:vreg_224_align2 = V_MOV_B32_e32 34, implicit $exec
2714 ; CHECK-NEXT: S_NOP 0, implicit %6.sub0_sub1_sub2_sub3_sub4
2715 ; CHECK-NEXT: S_NOP 0, implicit %6.sub2_sub3_sub4_sub5_sub6
2716 ; CHECK-NEXT: undef %7.sub0:vreg_256_align2 = V_MOV_B32_e32 42, implicit $exec
2717 ; CHECK-NEXT: %7.sub2:vreg_256_align2 = V_MOV_B32_e32 44, implicit $exec
2718 ; CHECK-NEXT: S_NOP 0, implicit %7.sub0_sub1_sub2_sub3_sub4_sub5
2719 ; CHECK-NEXT: S_NOP 0, implicit %7.sub2_sub3_sub4_sub5_sub6_sub7
2720 undef %1.sub2:vreg_1024_align2 = V_MOV_B32_e32 12, implicit $exec
2721 %1.sub4:vreg_1024_align2 = V_MOV_B32_e32 14, implicit $exec
2722 S_NOP 0, implicit %1.sub2_sub3_sub4
2723 S_NOP 0, implicit %1.sub4_sub5_sub6
2725 undef %2.sub2:vreg_1024_align2 = V_MOV_B32_e32 22, implicit $exec
2726 %2.sub4:vreg_1024_align2 = V_MOV_B32_e32 24, implicit $exec
2727 S_NOP 0, implicit %2.sub2_sub3_sub4_sub5
2728 S_NOP 0, implicit %2.sub4_sub5_sub6_sub7
2730 undef %3.sub2:vreg_1024_align2 = V_MOV_B32_e32 32, implicit $exec
2731 %3.sub4:vreg_1024_align2 = V_MOV_B32_e32 34, implicit $exec
2732 S_NOP 0, implicit %3.sub2_sub3_sub4_sub5_sub6
2733 S_NOP 0, implicit %3.sub4_sub5_sub6_sub7_sub8
2735 undef %4.sub2:vreg_1024_align2 = V_MOV_B32_e32 42, implicit $exec
2736 %4.sub4:vreg_1024_align2 = V_MOV_B32_e32 44, implicit $exec
2737 S_NOP 0, implicit %4.sub2_sub3_sub4_sub5_sub6_sub7
2738 S_NOP 0, implicit %4.sub4_sub5_sub6_sub7_sub8_sub9
2742 name: test_vreg_64_align2_w32
2743 tracksRegLiveness: true
2746 ; CHECK-LABEL: name: test_vreg_64_align2_w32
2747 ; CHECK: undef %0.sub0:vreg_64_align2 = V_MOV_B32_e32 0, implicit $exec
2748 ; CHECK-NEXT: S_NOP 0, implicit %0.sub0
2749 ; CHECK-NEXT: undef %1.sub1:vreg_64_align2 = V_MOV_B32_e32 11, implicit $exec
2750 ; CHECK-NEXT: S_NOP 0, implicit %1.sub1
2751 undef %0.sub0:vreg_64_align2 = V_MOV_B32_e32 00, implicit $exec
2752 S_NOP 0, implicit %0.sub0
2754 undef %1.sub1:vreg_64_align2 = V_MOV_B32_e32 11, implicit $exec
2755 S_NOP 0, implicit %1.sub1
2759 name: test_vreg_96_align2_w32
2760 tracksRegLiveness: true
2763 ; CHECK-LABEL: name: test_vreg_96_align2_w32
2764 ; CHECK: undef %0.sub0:vreg_96_align2 = V_MOV_B32_e32 0, implicit $exec
2765 ; CHECK-NEXT: S_NOP 0, implicit %0.sub0
2766 ; CHECK-NEXT: undef %1.sub1:vreg_96_align2 = V_MOV_B32_e32 11, implicit $exec
2767 ; CHECK-NEXT: S_NOP 0, implicit %1.sub1
2768 ; CHECK-NEXT: undef %2.sub2:vreg_96_align2 = V_MOV_B32_e32 22, implicit $exec
2769 ; CHECK-NEXT: S_NOP 0, implicit %2.sub2
2770 undef %0.sub0:vreg_96_align2 = V_MOV_B32_e32 00, implicit $exec
2771 S_NOP 0, implicit %0.sub0
2773 undef %1.sub1:vreg_96_align2 = V_MOV_B32_e32 11, implicit $exec
2774 S_NOP 0, implicit %1.sub1
2776 undef %2.sub2:vreg_96_align2 = V_MOV_B32_e32 22, implicit $exec
2777 S_NOP 0, implicit %2.sub2
2780 # Skip test_vreg_96_align2_w64: the 64-bit subreg isn't fully supported for the regclass vreg_96_align2
2782 name: test_vreg_128_align2_w32
2783 tracksRegLiveness: true
2786 ; CHECK-LABEL: name: test_vreg_128_align2_w32
2787 ; CHECK: undef %0.sub0:vreg_128_align2 = V_MOV_B32_e32 0, implicit $exec
2788 ; CHECK-NEXT: S_NOP 0, implicit %0.sub0
2789 ; CHECK-NEXT: undef %1.sub1:vreg_128_align2 = V_MOV_B32_e32 11, implicit $exec
2790 ; CHECK-NEXT: S_NOP 0, implicit %1.sub1
2791 ; CHECK-NEXT: undef %2.sub3:vreg_128_align2 = V_MOV_B32_e32 23, implicit $exec
2792 ; CHECK-NEXT: S_NOP 0, implicit %2.sub3
2793 undef %0.sub0:vreg_128_align2 = V_MOV_B32_e32 00, implicit $exec
2794 S_NOP 0, implicit %0.sub0
2796 undef %1.sub1:vreg_128_align2 = V_MOV_B32_e32 11, implicit $exec
2797 S_NOP 0, implicit %1.sub1
2799 undef %2.sub3:vreg_128_align2 = V_MOV_B32_e32 23, implicit $exec
2800 S_NOP 0, implicit %2.sub3
2804 name: test_vreg_128_align2_w64
2805 tracksRegLiveness: true
2808 ; CHECK-LABEL: name: test_vreg_128_align2_w64
2809 ; CHECK: undef %2.sub0:vreg_64_align2 = V_MOV_B32_e32 0, implicit $exec
2810 ; CHECK-NEXT: %2.sub1:vreg_64_align2 = V_MOV_B32_e32 1, implicit $exec
2811 ; CHECK-NEXT: S_NOP 0, implicit %2
2812 ; CHECK-NEXT: undef %3.sub0:vreg_64_align2 = V_MOV_B32_e32 12, implicit $exec
2813 ; CHECK-NEXT: %3.sub1:vreg_64_align2 = V_MOV_B32_e32 13, implicit $exec
2814 ; CHECK-NEXT: S_NOP 0, implicit %3
2815 undef %0.sub0:vreg_128_align2 = V_MOV_B32_e32 00, implicit $exec
2816 %0.sub1:vreg_128_align2 = V_MOV_B32_e32 01, implicit $exec
2817 S_NOP 0, implicit %0.sub0_sub1
2819 undef %1.sub2:vreg_128_align2 = V_MOV_B32_e32 12, implicit $exec
2820 %1.sub3:vreg_128_align2 = V_MOV_B32_e32 13, implicit $exec
2821 S_NOP 0, implicit %1.sub2_sub3
2824 # Skip test_vreg_128_align2_w96: the 96-bit subreg isn't fully supported for the regclass vreg_128_align2
2826 name: test_vreg_160_align2_w32
2827 tracksRegLiveness: true
2830 ; CHECK-LABEL: name: test_vreg_160_align2_w32
2831 ; CHECK: undef %0.sub0:vreg_160_align2 = V_MOV_B32_e32 0, implicit $exec
2832 ; CHECK-NEXT: S_NOP 0, implicit %0.sub0
2833 ; CHECK-NEXT: undef %1.sub1:vreg_160_align2 = V_MOV_B32_e32 11, implicit $exec
2834 ; CHECK-NEXT: S_NOP 0, implicit %1.sub1
2835 ; CHECK-NEXT: undef %2.sub4:vreg_160_align2 = V_MOV_B32_e32 24, implicit $exec
2836 ; CHECK-NEXT: S_NOP 0, implicit %2.sub4
2837 undef %0.sub0:vreg_160_align2 = V_MOV_B32_e32 00, implicit $exec
2838 S_NOP 0, implicit %0.sub0
2840 undef %1.sub1:vreg_160_align2 = V_MOV_B32_e32 11, implicit $exec
2841 S_NOP 0, implicit %1.sub1
2843 undef %2.sub4:vreg_160_align2 = V_MOV_B32_e32 24, implicit $exec
2844 S_NOP 0, implicit %2.sub4
2847 # Skip test_vreg_160_align2_w64: the 64-bit subreg isn't fully supported for the regclass vreg_160_align2
2849 name: test_vreg_160_align2_w96
2850 tracksRegLiveness: true
2853 ; CHECK-LABEL: name: test_vreg_160_align2_w96
2854 ; CHECK: undef %2.sub0:vreg_96_align2 = V_MOV_B32_e32 0, implicit $exec
2855 ; CHECK-NEXT: %2.sub1:vreg_96_align2 = V_MOV_B32_e32 1, implicit $exec
2856 ; CHECK-NEXT: %2.sub2:vreg_96_align2 = V_MOV_B32_e32 2, implicit $exec
2857 ; CHECK-NEXT: S_NOP 0, implicit %2
2858 ; CHECK-NEXT: undef %3.sub0:vreg_96_align2 = V_MOV_B32_e32 12, implicit $exec
2859 ; CHECK-NEXT: %3.sub1:vreg_96_align2 = V_MOV_B32_e32 13, implicit $exec
2860 ; CHECK-NEXT: %3.sub2:vreg_96_align2 = V_MOV_B32_e32 14, implicit $exec
2861 ; CHECK-NEXT: S_NOP 0, implicit %3
2862 undef %0.sub0:vreg_160_align2 = V_MOV_B32_e32 00, implicit $exec
2863 %0.sub1:vreg_160_align2 = V_MOV_B32_e32 01, implicit $exec
2864 %0.sub2:vreg_160_align2 = V_MOV_B32_e32 02, implicit $exec
2865 S_NOP 0, implicit %0.sub0_sub1_sub2
2867 undef %1.sub2:vreg_160_align2 = V_MOV_B32_e32 12, implicit $exec
2868 %1.sub3:vreg_160_align2 = V_MOV_B32_e32 13, implicit $exec
2869 %1.sub4:vreg_160_align2 = V_MOV_B32_e32 14, implicit $exec
2870 S_NOP 0, implicit %1.sub2_sub3_sub4
2873 # Skip test_vreg_160_align2_w128: the 128-bit subreg isn't fully supported for the regclass vreg_160_align2
2875 name: test_vreg_192_align2_w32
2876 tracksRegLiveness: true
2879 ; CHECK-LABEL: name: test_vreg_192_align2_w32
2880 ; CHECK: undef %0.sub0:vreg_192_align2 = V_MOV_B32_e32 0, implicit $exec
2881 ; CHECK-NEXT: S_NOP 0, implicit %0.sub0
2882 ; CHECK-NEXT: undef %1.sub1:vreg_192_align2 = V_MOV_B32_e32 11, implicit $exec
2883 ; CHECK-NEXT: S_NOP 0, implicit %1.sub1
2884 ; CHECK-NEXT: undef %2.sub5:vreg_192_align2 = V_MOV_B32_e32 25, implicit $exec
2885 ; CHECK-NEXT: S_NOP 0, implicit %2.sub5
2886 undef %0.sub0:vreg_192_align2 = V_MOV_B32_e32 00, implicit $exec
2887 S_NOP 0, implicit %0.sub0
2889 undef %1.sub1:vreg_192_align2 = V_MOV_B32_e32 11, implicit $exec
2890 S_NOP 0, implicit %1.sub1
2892 undef %2.sub5:vreg_192_align2 = V_MOV_B32_e32 25, implicit $exec
2893 S_NOP 0, implicit %2.sub5
2897 name: test_vreg_192_align2_w64
2898 tracksRegLiveness: true
2901 ; CHECK-LABEL: name: test_vreg_192_align2_w64
2902 ; CHECK: undef %3.sub0:vreg_64_align2 = V_MOV_B32_e32 0, implicit $exec
2903 ; CHECK-NEXT: %3.sub1:vreg_64_align2 = V_MOV_B32_e32 1, implicit $exec
2904 ; CHECK-NEXT: S_NOP 0, implicit %3
2905 ; CHECK-NEXT: undef %4.sub0:vreg_64_align2 = V_MOV_B32_e32 12, implicit $exec
2906 ; CHECK-NEXT: %4.sub1:vreg_64_align2 = V_MOV_B32_e32 13, implicit $exec
2907 ; CHECK-NEXT: S_NOP 0, implicit %4
2908 ; CHECK-NEXT: undef %5.sub0:vreg_64_align2 = V_MOV_B32_e32 24, implicit $exec
2909 ; CHECK-NEXT: %5.sub1:vreg_64_align2 = V_MOV_B32_e32 25, implicit $exec
2910 ; CHECK-NEXT: S_NOP 0, implicit %5
2911 undef %0.sub0:vreg_192_align2 = V_MOV_B32_e32 00, implicit $exec
2912 %0.sub1:vreg_192_align2 = V_MOV_B32_e32 01, implicit $exec
2913 S_NOP 0, implicit %0.sub0_sub1
2915 undef %1.sub2:vreg_192_align2 = V_MOV_B32_e32 12, implicit $exec
2916 %1.sub3:vreg_192_align2 = V_MOV_B32_e32 13, implicit $exec
2917 S_NOP 0, implicit %1.sub2_sub3
2919 undef %2.sub4:vreg_192_align2 = V_MOV_B32_e32 24, implicit $exec
2920 %2.sub5:vreg_192_align2 = V_MOV_B32_e32 25, implicit $exec
2921 S_NOP 0, implicit %2.sub4_sub5
2924 # Skip test_vreg_192_align2_w96: the 96-bit subreg isn't fully supported for the regclass vreg_192_align2
2926 name: test_vreg_192_align2_w128
2927 tracksRegLiveness: true
2930 ; CHECK-LABEL: name: test_vreg_192_align2_w128
2931 ; CHECK: undef %2.sub0:vreg_128_align2 = V_MOV_B32_e32 0, implicit $exec
2932 ; CHECK-NEXT: %2.sub1:vreg_128_align2 = V_MOV_B32_e32 1, implicit $exec
2933 ; CHECK-NEXT: %2.sub2:vreg_128_align2 = V_MOV_B32_e32 2, implicit $exec
2934 ; CHECK-NEXT: %2.sub3:vreg_128_align2 = V_MOV_B32_e32 3, implicit $exec
2935 ; CHECK-NEXT: S_NOP 0, implicit %2
2936 ; CHECK-NEXT: undef %3.sub0:vreg_128_align2 = V_MOV_B32_e32 12, implicit $exec
2937 ; CHECK-NEXT: %3.sub1:vreg_128_align2 = V_MOV_B32_e32 13, implicit $exec
2938 ; CHECK-NEXT: %3.sub2:vreg_128_align2 = V_MOV_B32_e32 14, implicit $exec
2939 ; CHECK-NEXT: %3.sub3:vreg_128_align2 = V_MOV_B32_e32 15, implicit $exec
2940 ; CHECK-NEXT: S_NOP 0, implicit %3
2941 undef %0.sub0:vreg_192_align2 = V_MOV_B32_e32 00, implicit $exec
2942 %0.sub1:vreg_192_align2 = V_MOV_B32_e32 01, implicit $exec
2943 %0.sub2:vreg_192_align2 = V_MOV_B32_e32 02, implicit $exec
2944 %0.sub3:vreg_192_align2 = V_MOV_B32_e32 03, implicit $exec
2945 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3
2947 undef %1.sub2:vreg_192_align2 = V_MOV_B32_e32 12, implicit $exec
2948 %1.sub3:vreg_192_align2 = V_MOV_B32_e32 13, implicit $exec
2949 %1.sub4:vreg_192_align2 = V_MOV_B32_e32 14, implicit $exec
2950 %1.sub5:vreg_192_align2 = V_MOV_B32_e32 15, implicit $exec
2951 S_NOP 0, implicit %1.sub2_sub3_sub4_sub5
2954 # Skip test_vreg_192_align2_w160: the 160-bit subreg isn't fully supported for the regclass vreg_192_align2
2956 name: test_vreg_224_align2_w32
2957 tracksRegLiveness: true
2960 ; CHECK-LABEL: name: test_vreg_224_align2_w32
2961 ; CHECK: undef %0.sub0:vreg_224_align2 = V_MOV_B32_e32 0, implicit $exec
2962 ; CHECK-NEXT: S_NOP 0, implicit %0.sub0
2963 ; CHECK-NEXT: undef %1.sub1:vreg_224_align2 = V_MOV_B32_e32 11, implicit $exec
2964 ; CHECK-NEXT: S_NOP 0, implicit %1.sub1
2965 ; CHECK-NEXT: undef %2.sub6:vreg_224_align2 = V_MOV_B32_e32 26, implicit $exec
2966 ; CHECK-NEXT: S_NOP 0, implicit %2.sub6
2967 undef %0.sub0:vreg_224_align2 = V_MOV_B32_e32 00, implicit $exec
2968 S_NOP 0, implicit %0.sub0
2970 undef %1.sub1:vreg_224_align2 = V_MOV_B32_e32 11, implicit $exec
2971 S_NOP 0, implicit %1.sub1
2973 undef %2.sub6:vreg_224_align2 = V_MOV_B32_e32 26, implicit $exec
2974 S_NOP 0, implicit %2.sub6
2977 # Skip test_vreg_224_align2_w64: the 64-bit subreg isn't fully supported for the regclass vreg_224_align2
2979 name: test_vreg_224_align2_w96
2980 tracksRegLiveness: true
2983 ; CHECK-LABEL: name: test_vreg_224_align2_w96
2984 ; CHECK: undef %3.sub0:vreg_96_align2 = V_MOV_B32_e32 0, implicit $exec
2985 ; CHECK-NEXT: %3.sub1:vreg_96_align2 = V_MOV_B32_e32 1, implicit $exec
2986 ; CHECK-NEXT: %3.sub2:vreg_96_align2 = V_MOV_B32_e32 2, implicit $exec
2987 ; CHECK-NEXT: S_NOP 0, implicit %3
2988 ; CHECK-NEXT: undef %4.sub0:vreg_96_align2 = V_MOV_B32_e32 12, implicit $exec
2989 ; CHECK-NEXT: %4.sub1:vreg_96_align2 = V_MOV_B32_e32 13, implicit $exec
2990 ; CHECK-NEXT: %4.sub2:vreg_96_align2 = V_MOV_B32_e32 14, implicit $exec
2991 ; CHECK-NEXT: S_NOP 0, implicit %4
2992 ; CHECK-NEXT: undef %5.sub0:vreg_96_align2 = V_MOV_B32_e32 24, implicit $exec
2993 ; CHECK-NEXT: %5.sub1:vreg_96_align2 = V_MOV_B32_e32 25, implicit $exec
2994 ; CHECK-NEXT: %5.sub2:vreg_96_align2 = V_MOV_B32_e32 26, implicit $exec
2995 ; CHECK-NEXT: S_NOP 0, implicit %5
2996 undef %0.sub0:vreg_224_align2 = V_MOV_B32_e32 00, implicit $exec
2997 %0.sub1:vreg_224_align2 = V_MOV_B32_e32 01, implicit $exec
2998 %0.sub2:vreg_224_align2 = V_MOV_B32_e32 02, implicit $exec
2999 S_NOP 0, implicit %0.sub0_sub1_sub2
3001 undef %1.sub2:vreg_224_align2 = V_MOV_B32_e32 12, implicit $exec
3002 %1.sub3:vreg_224_align2 = V_MOV_B32_e32 13, implicit $exec
3003 %1.sub4:vreg_224_align2 = V_MOV_B32_e32 14, implicit $exec
3004 S_NOP 0, implicit %1.sub2_sub3_sub4
3006 undef %2.sub4:vreg_224_align2 = V_MOV_B32_e32 24, implicit $exec
3007 %2.sub5:vreg_224_align2 = V_MOV_B32_e32 25, implicit $exec
3008 %2.sub6:vreg_224_align2 = V_MOV_B32_e32 26, implicit $exec
3009 S_NOP 0, implicit %2.sub4_sub5_sub6
3012 # Skip test_vreg_224_align2_w128: the 128-bit subreg isn't fully supported for the regclass vreg_224_align2
3014 name: test_vreg_224_align2_w160
3015 tracksRegLiveness: true
3018 ; CHECK-LABEL: name: test_vreg_224_align2_w160
3019 ; CHECK: undef %2.sub0:vreg_160_align2 = V_MOV_B32_e32 0, implicit $exec
3020 ; CHECK-NEXT: %2.sub1:vreg_160_align2 = V_MOV_B32_e32 1, implicit $exec
3021 ; CHECK-NEXT: %2.sub2:vreg_160_align2 = V_MOV_B32_e32 2, implicit $exec
3022 ; CHECK-NEXT: %2.sub3:vreg_160_align2 = V_MOV_B32_e32 3, implicit $exec
3023 ; CHECK-NEXT: %2.sub4:vreg_160_align2 = V_MOV_B32_e32 4, implicit $exec
3024 ; CHECK-NEXT: S_NOP 0, implicit %2
3025 ; CHECK-NEXT: undef %3.sub0:vreg_160_align2 = V_MOV_B32_e32 12, implicit $exec
3026 ; CHECK-NEXT: %3.sub1:vreg_160_align2 = V_MOV_B32_e32 13, implicit $exec
3027 ; CHECK-NEXT: %3.sub2:vreg_160_align2 = V_MOV_B32_e32 14, implicit $exec
3028 ; CHECK-NEXT: %3.sub3:vreg_160_align2 = V_MOV_B32_e32 15, implicit $exec
3029 ; CHECK-NEXT: %3.sub4:vreg_160_align2 = V_MOV_B32_e32 16, implicit $exec
3030 ; CHECK-NEXT: S_NOP 0, implicit %3
3031 undef %0.sub0:vreg_224_align2 = V_MOV_B32_e32 00, implicit $exec
3032 %0.sub1:vreg_224_align2 = V_MOV_B32_e32 01, implicit $exec
3033 %0.sub2:vreg_224_align2 = V_MOV_B32_e32 02, implicit $exec
3034 %0.sub3:vreg_224_align2 = V_MOV_B32_e32 03, implicit $exec
3035 %0.sub4:vreg_224_align2 = V_MOV_B32_e32 04, implicit $exec
3036 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4
3038 undef %1.sub2:vreg_224_align2 = V_MOV_B32_e32 12, implicit $exec
3039 %1.sub3:vreg_224_align2 = V_MOV_B32_e32 13, implicit $exec
3040 %1.sub4:vreg_224_align2 = V_MOV_B32_e32 14, implicit $exec
3041 %1.sub5:vreg_224_align2 = V_MOV_B32_e32 15, implicit $exec
3042 %1.sub6:vreg_224_align2 = V_MOV_B32_e32 16, implicit $exec
3043 S_NOP 0, implicit %1.sub2_sub3_sub4_sub5_sub6
3046 # Skip test_vreg_224_align2_w192: the 192-bit subreg isn't fully supported for the regclass vreg_224_align2
3048 name: test_vreg_256_align2_w32
3049 tracksRegLiveness: true
3052 ; CHECK-LABEL: name: test_vreg_256_align2_w32
3053 ; CHECK: undef %0.sub0:vreg_256_align2 = V_MOV_B32_e32 0, implicit $exec
3054 ; CHECK-NEXT: S_NOP 0, implicit %0.sub0
3055 ; CHECK-NEXT: undef %1.sub1:vreg_256_align2 = V_MOV_B32_e32 11, implicit $exec
3056 ; CHECK-NEXT: S_NOP 0, implicit %1.sub1
3057 ; CHECK-NEXT: undef %2.sub7:vreg_256_align2 = V_MOV_B32_e32 27, implicit $exec
3058 ; CHECK-NEXT: S_NOP 0, implicit %2.sub7
3059 undef %0.sub0:vreg_256_align2 = V_MOV_B32_e32 00, implicit $exec
3060 S_NOP 0, implicit %0.sub0
3062 undef %1.sub1:vreg_256_align2 = V_MOV_B32_e32 11, implicit $exec
3063 S_NOP 0, implicit %1.sub1
3065 undef %2.sub7:vreg_256_align2 = V_MOV_B32_e32 27, implicit $exec
3066 S_NOP 0, implicit %2.sub7
3070 name: test_vreg_256_align2_w64
3071 tracksRegLiveness: true
3074 ; CHECK-LABEL: name: test_vreg_256_align2_w64
3075 ; CHECK: undef %3.sub0:vreg_64_align2 = V_MOV_B32_e32 0, implicit $exec
3076 ; CHECK-NEXT: %3.sub1:vreg_64_align2 = V_MOV_B32_e32 1, implicit $exec
3077 ; CHECK-NEXT: S_NOP 0, implicit %3
3078 ; CHECK-NEXT: undef %4.sub0:vreg_64_align2 = V_MOV_B32_e32 12, implicit $exec
3079 ; CHECK-NEXT: %4.sub1:vreg_64_align2 = V_MOV_B32_e32 13, implicit $exec
3080 ; CHECK-NEXT: S_NOP 0, implicit %4
3081 ; CHECK-NEXT: undef %5.sub0:vreg_64_align2 = V_MOV_B32_e32 26, implicit $exec
3082 ; CHECK-NEXT: %5.sub1:vreg_64_align2 = V_MOV_B32_e32 27, implicit $exec
3083 ; CHECK-NEXT: S_NOP 0, implicit %5
3084 undef %0.sub0:vreg_256_align2 = V_MOV_B32_e32 00, implicit $exec
3085 %0.sub1:vreg_256_align2 = V_MOV_B32_e32 01, implicit $exec
3086 S_NOP 0, implicit %0.sub0_sub1
3088 undef %1.sub2:vreg_256_align2 = V_MOV_B32_e32 12, implicit $exec
3089 %1.sub3:vreg_256_align2 = V_MOV_B32_e32 13, implicit $exec
3090 S_NOP 0, implicit %1.sub2_sub3
3092 undef %2.sub6:vreg_256_align2 = V_MOV_B32_e32 26, implicit $exec
3093 %2.sub7:vreg_256_align2 = V_MOV_B32_e32 27, implicit $exec
3094 S_NOP 0, implicit %2.sub6_sub7
3097 # Skip test_vreg_256_align2_w96: the 96-bit subreg isn't fully supported for the regclass vreg_256_align2
3099 name: test_vreg_256_align2_w128
3100 tracksRegLiveness: true
3103 ; CHECK-LABEL: name: test_vreg_256_align2_w128
3104 ; CHECK: undef %3.sub0:vreg_128_align2 = V_MOV_B32_e32 0, implicit $exec
3105 ; CHECK-NEXT: %3.sub1:vreg_128_align2 = V_MOV_B32_e32 1, implicit $exec
3106 ; CHECK-NEXT: %3.sub2:vreg_128_align2 = V_MOV_B32_e32 2, implicit $exec
3107 ; CHECK-NEXT: %3.sub3:vreg_128_align2 = V_MOV_B32_e32 3, implicit $exec
3108 ; CHECK-NEXT: S_NOP 0, implicit %3
3109 ; CHECK-NEXT: undef %4.sub0:vreg_128_align2 = V_MOV_B32_e32 12, implicit $exec
3110 ; CHECK-NEXT: %4.sub1:vreg_128_align2 = V_MOV_B32_e32 13, implicit $exec
3111 ; CHECK-NEXT: %4.sub2:vreg_128_align2 = V_MOV_B32_e32 14, implicit $exec
3112 ; CHECK-NEXT: %4.sub3:vreg_128_align2 = V_MOV_B32_e32 15, implicit $exec
3113 ; CHECK-NEXT: S_NOP 0, implicit %4
3114 ; CHECK-NEXT: undef %5.sub0:vreg_128_align2 = V_MOV_B32_e32 24, implicit $exec
3115 ; CHECK-NEXT: %5.sub1:vreg_128_align2 = V_MOV_B32_e32 25, implicit $exec
3116 ; CHECK-NEXT: %5.sub2:vreg_128_align2 = V_MOV_B32_e32 26, implicit $exec
3117 ; CHECK-NEXT: %5.sub3:vreg_128_align2 = V_MOV_B32_e32 27, implicit $exec
3118 ; CHECK-NEXT: S_NOP 0, implicit %5
3119 undef %0.sub0:vreg_256_align2 = V_MOV_B32_e32 00, implicit $exec
3120 %0.sub1:vreg_256_align2 = V_MOV_B32_e32 01, implicit $exec
3121 %0.sub2:vreg_256_align2 = V_MOV_B32_e32 02, implicit $exec
3122 %0.sub3:vreg_256_align2 = V_MOV_B32_e32 03, implicit $exec
3123 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3
3125 undef %1.sub2:vreg_256_align2 = V_MOV_B32_e32 12, implicit $exec
3126 %1.sub3:vreg_256_align2 = V_MOV_B32_e32 13, implicit $exec
3127 %1.sub4:vreg_256_align2 = V_MOV_B32_e32 14, implicit $exec
3128 %1.sub5:vreg_256_align2 = V_MOV_B32_e32 15, implicit $exec
3129 S_NOP 0, implicit %1.sub2_sub3_sub4_sub5
3131 undef %2.sub4:vreg_256_align2 = V_MOV_B32_e32 24, implicit $exec
3132 %2.sub5:vreg_256_align2 = V_MOV_B32_e32 25, implicit $exec
3133 %2.sub6:vreg_256_align2 = V_MOV_B32_e32 26, implicit $exec
3134 %2.sub7:vreg_256_align2 = V_MOV_B32_e32 27, implicit $exec
3135 S_NOP 0, implicit %2.sub4_sub5_sub6_sub7
3138 # Skip test_vreg_256_align2_w160: the 160-bit subreg isn't fully supported for the regclass vreg_256_align2
3140 name: test_vreg_256_align2_w192
3141 tracksRegLiveness: true
3144 ; CHECK-LABEL: name: test_vreg_256_align2_w192
3145 ; CHECK: undef %2.sub0:vreg_192_align2 = V_MOV_B32_e32 0, implicit $exec
3146 ; CHECK-NEXT: %2.sub1:vreg_192_align2 = V_MOV_B32_e32 1, implicit $exec
3147 ; CHECK-NEXT: %2.sub2:vreg_192_align2 = V_MOV_B32_e32 2, implicit $exec
3148 ; CHECK-NEXT: %2.sub3:vreg_192_align2 = V_MOV_B32_e32 3, implicit $exec
3149 ; CHECK-NEXT: %2.sub4:vreg_192_align2 = V_MOV_B32_e32 4, implicit $exec
3150 ; CHECK-NEXT: %2.sub5:vreg_192_align2 = V_MOV_B32_e32 5, implicit $exec
3151 ; CHECK-NEXT: S_NOP 0, implicit %2
3152 ; CHECK-NEXT: undef %3.sub0:vreg_192_align2 = V_MOV_B32_e32 12, implicit $exec
3153 ; CHECK-NEXT: %3.sub1:vreg_192_align2 = V_MOV_B32_e32 13, implicit $exec
3154 ; CHECK-NEXT: %3.sub2:vreg_192_align2 = V_MOV_B32_e32 14, implicit $exec
3155 ; CHECK-NEXT: %3.sub3:vreg_192_align2 = V_MOV_B32_e32 15, implicit $exec
3156 ; CHECK-NEXT: %3.sub4:vreg_192_align2 = V_MOV_B32_e32 16, implicit $exec
3157 ; CHECK-NEXT: %3.sub5:vreg_192_align2 = V_MOV_B32_e32 17, implicit $exec
3158 ; CHECK-NEXT: S_NOP 0, implicit %3
3159 undef %0.sub0:vreg_256_align2 = V_MOV_B32_e32 00, implicit $exec
3160 %0.sub1:vreg_256_align2 = V_MOV_B32_e32 01, implicit $exec
3161 %0.sub2:vreg_256_align2 = V_MOV_B32_e32 02, implicit $exec
3162 %0.sub3:vreg_256_align2 = V_MOV_B32_e32 03, implicit $exec
3163 %0.sub4:vreg_256_align2 = V_MOV_B32_e32 04, implicit $exec
3164 %0.sub5:vreg_256_align2 = V_MOV_B32_e32 05, implicit $exec
3165 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5
3167 undef %1.sub2:vreg_256_align2 = V_MOV_B32_e32 12, implicit $exec
3168 %1.sub3:vreg_256_align2 = V_MOV_B32_e32 13, implicit $exec
3169 %1.sub4:vreg_256_align2 = V_MOV_B32_e32 14, implicit $exec
3170 %1.sub5:vreg_256_align2 = V_MOV_B32_e32 15, implicit $exec
3171 %1.sub6:vreg_256_align2 = V_MOV_B32_e32 16, implicit $exec
3172 %1.sub7:vreg_256_align2 = V_MOV_B32_e32 17, implicit $exec
3173 S_NOP 0, implicit %1.sub2_sub3_sub4_sub5_sub6_sub7
3177 name: test_vreg_288_align2_w32
3178 tracksRegLiveness: true
3181 ; CHECK-LABEL: name: test_vreg_288_align2_w32
3182 ; CHECK: undef %0.sub0:vreg_288_align2 = V_MOV_B32_e32 0, implicit $exec
3183 ; CHECK-NEXT: S_NOP 0, implicit %0.sub0
3184 ; CHECK-NEXT: undef %1.sub1:vreg_288_align2 = V_MOV_B32_e32 11, implicit $exec
3185 ; CHECK-NEXT: S_NOP 0, implicit %1.sub1
3186 ; CHECK-NEXT: undef %2.sub8:vreg_288_align2 = V_MOV_B32_e32 28, implicit $exec
3187 ; CHECK-NEXT: S_NOP 0, implicit %2.sub8
3188 undef %0.sub0:vreg_288_align2 = V_MOV_B32_e32 00, implicit $exec
3189 S_NOP 0, implicit %0.sub0
3191 undef %1.sub1:vreg_288_align2 = V_MOV_B32_e32 11, implicit $exec
3192 S_NOP 0, implicit %1.sub1
3194 undef %2.sub8:vreg_288_align2 = V_MOV_B32_e32 28, implicit $exec
3195 S_NOP 0, implicit %2.sub8
3198 # Skip test_vreg_288_align2_w64: the 64-bit subreg isn't fully supported for the regclass vreg_288_align2
3200 name: test_vreg_288_align2_w96
3201 tracksRegLiveness: true
3204 ; CHECK-LABEL: name: test_vreg_288_align2_w96
3205 ; CHECK: undef %3.sub0:vreg_96_align2 = V_MOV_B32_e32 0, implicit $exec
3206 ; CHECK-NEXT: %3.sub1:vreg_96_align2 = V_MOV_B32_e32 1, implicit $exec
3207 ; CHECK-NEXT: %3.sub2:vreg_96_align2 = V_MOV_B32_e32 2, implicit $exec
3208 ; CHECK-NEXT: S_NOP 0, implicit %3
3209 ; CHECK-NEXT: undef %4.sub0:vreg_96_align2 = V_MOV_B32_e32 12, implicit $exec
3210 ; CHECK-NEXT: %4.sub1:vreg_96_align2 = V_MOV_B32_e32 13, implicit $exec
3211 ; CHECK-NEXT: %4.sub2:vreg_96_align2 = V_MOV_B32_e32 14, implicit $exec
3212 ; CHECK-NEXT: S_NOP 0, implicit %4
3213 ; CHECK-NEXT: undef %5.sub0:vreg_96_align2 = V_MOV_B32_e32 26, implicit $exec
3214 ; CHECK-NEXT: %5.sub1:vreg_96_align2 = V_MOV_B32_e32 27, implicit $exec
3215 ; CHECK-NEXT: %5.sub2:vreg_96_align2 = V_MOV_B32_e32 28, implicit $exec
3216 ; CHECK-NEXT: S_NOP 0, implicit %5
3217 undef %0.sub0:vreg_288_align2 = V_MOV_B32_e32 00, implicit $exec
3218 %0.sub1:vreg_288_align2 = V_MOV_B32_e32 01, implicit $exec
3219 %0.sub2:vreg_288_align2 = V_MOV_B32_e32 02, implicit $exec
3220 S_NOP 0, implicit %0.sub0_sub1_sub2
3222 undef %1.sub2:vreg_288_align2 = V_MOV_B32_e32 12, implicit $exec
3223 %1.sub3:vreg_288_align2 = V_MOV_B32_e32 13, implicit $exec
3224 %1.sub4:vreg_288_align2 = V_MOV_B32_e32 14, implicit $exec
3225 S_NOP 0, implicit %1.sub2_sub3_sub4
3227 undef %2.sub6:vreg_288_align2 = V_MOV_B32_e32 26, implicit $exec
3228 %2.sub7:vreg_288_align2 = V_MOV_B32_e32 27, implicit $exec
3229 %2.sub8:vreg_288_align2 = V_MOV_B32_e32 28, implicit $exec
3230 S_NOP 0, implicit %2.sub6_sub7_sub8
3233 # Skip test_vreg_288_align2_w128: the 128-bit subreg isn't fully supported for the regclass vreg_288_align2
3235 name: test_vreg_288_align2_w160
3236 tracksRegLiveness: true
3239 ; CHECK-LABEL: name: test_vreg_288_align2_w160
3240 ; CHECK: undef %3.sub0:vreg_160_align2 = V_MOV_B32_e32 0, implicit $exec
3241 ; CHECK-NEXT: %3.sub1:vreg_160_align2 = V_MOV_B32_e32 1, implicit $exec
3242 ; CHECK-NEXT: %3.sub2:vreg_160_align2 = V_MOV_B32_e32 2, implicit $exec
3243 ; CHECK-NEXT: %3.sub3:vreg_160_align2 = V_MOV_B32_e32 3, implicit $exec
3244 ; CHECK-NEXT: %3.sub4:vreg_160_align2 = V_MOV_B32_e32 4, implicit $exec
3245 ; CHECK-NEXT: S_NOP 0, implicit %3
3246 ; CHECK-NEXT: undef %4.sub0:vreg_160_align2 = V_MOV_B32_e32 12, implicit $exec
3247 ; CHECK-NEXT: %4.sub1:vreg_160_align2 = V_MOV_B32_e32 13, implicit $exec
3248 ; CHECK-NEXT: %4.sub2:vreg_160_align2 = V_MOV_B32_e32 14, implicit $exec
3249 ; CHECK-NEXT: %4.sub3:vreg_160_align2 = V_MOV_B32_e32 15, implicit $exec
3250 ; CHECK-NEXT: %4.sub4:vreg_160_align2 = V_MOV_B32_e32 16, implicit $exec
3251 ; CHECK-NEXT: S_NOP 0, implicit %4
3252 ; CHECK-NEXT: undef %5.sub0:vreg_160_align2 = V_MOV_B32_e32 24, implicit $exec
3253 ; CHECK-NEXT: %5.sub1:vreg_160_align2 = V_MOV_B32_e32 25, implicit $exec
3254 ; CHECK-NEXT: %5.sub2:vreg_160_align2 = V_MOV_B32_e32 26, implicit $exec
3255 ; CHECK-NEXT: %5.sub3:vreg_160_align2 = V_MOV_B32_e32 27, implicit $exec
3256 ; CHECK-NEXT: %5.sub4:vreg_160_align2 = V_MOV_B32_e32 28, implicit $exec
3257 ; CHECK-NEXT: S_NOP 0, implicit %5
3258 undef %0.sub0:vreg_288_align2 = V_MOV_B32_e32 00, implicit $exec
3259 %0.sub1:vreg_288_align2 = V_MOV_B32_e32 01, implicit $exec
3260 %0.sub2:vreg_288_align2 = V_MOV_B32_e32 02, implicit $exec
3261 %0.sub3:vreg_288_align2 = V_MOV_B32_e32 03, implicit $exec
3262 %0.sub4:vreg_288_align2 = V_MOV_B32_e32 04, implicit $exec
3263 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4
3265 undef %1.sub2:vreg_288_align2 = V_MOV_B32_e32 12, implicit $exec
3266 %1.sub3:vreg_288_align2 = V_MOV_B32_e32 13, implicit $exec
3267 %1.sub4:vreg_288_align2 = V_MOV_B32_e32 14, implicit $exec
3268 %1.sub5:vreg_288_align2 = V_MOV_B32_e32 15, implicit $exec
3269 %1.sub6:vreg_288_align2 = V_MOV_B32_e32 16, implicit $exec
3270 S_NOP 0, implicit %1.sub2_sub3_sub4_sub5_sub6
3272 undef %2.sub4:vreg_288_align2 = V_MOV_B32_e32 24, implicit $exec
3273 %2.sub5:vreg_288_align2 = V_MOV_B32_e32 25, implicit $exec
3274 %2.sub6:vreg_288_align2 = V_MOV_B32_e32 26, implicit $exec
3275 %2.sub7:vreg_288_align2 = V_MOV_B32_e32 27, implicit $exec
3276 %2.sub8:vreg_288_align2 = V_MOV_B32_e32 28, implicit $exec
3277 S_NOP 0, implicit %2.sub4_sub5_sub6_sub7_sub8
3280 # Skip test_vreg_288_align2_w192: the 192-bit subreg isn't fully supported for the regclass vreg_288_align2
3281 # Skip test_vreg_288_align2_w256: the 256-bit subreg isn't fully supported for the regclass vreg_288_align2
3283 name: test_vreg_320_align2_w32
3284 tracksRegLiveness: true
3287 ; CHECK-LABEL: name: test_vreg_320_align2_w32
3288 ; CHECK: undef %0.sub0:vreg_320_align2 = V_MOV_B32_e32 0, implicit $exec
3289 ; CHECK-NEXT: S_NOP 0, implicit %0.sub0
3290 ; CHECK-NEXT: undef %1.sub1:vreg_320_align2 = V_MOV_B32_e32 11, implicit $exec
3291 ; CHECK-NEXT: S_NOP 0, implicit %1.sub1
3292 ; CHECK-NEXT: undef %2.sub9:vreg_320_align2 = V_MOV_B32_e32 29, implicit $exec
3293 ; CHECK-NEXT: S_NOP 0, implicit %2.sub9
3294 undef %0.sub0:vreg_320_align2 = V_MOV_B32_e32 00, implicit $exec
3295 S_NOP 0, implicit %0.sub0
3297 undef %1.sub1:vreg_320_align2 = V_MOV_B32_e32 11, implicit $exec
3298 S_NOP 0, implicit %1.sub1
3300 undef %2.sub9:vreg_320_align2 = V_MOV_B32_e32 29, implicit $exec
3301 S_NOP 0, implicit %2.sub9
3305 name: test_vreg_320_align2_w64
3306 tracksRegLiveness: true
3309 ; CHECK-LABEL: name: test_vreg_320_align2_w64
3310 ; CHECK: undef %3.sub0:vreg_64_align2 = V_MOV_B32_e32 0, implicit $exec
3311 ; CHECK-NEXT: %3.sub1:vreg_64_align2 = V_MOV_B32_e32 1, implicit $exec
3312 ; CHECK-NEXT: S_NOP 0, implicit %3
3313 ; CHECK-NEXT: undef %4.sub0:vreg_64_align2 = V_MOV_B32_e32 12, implicit $exec
3314 ; CHECK-NEXT: %4.sub1:vreg_64_align2 = V_MOV_B32_e32 13, implicit $exec
3315 ; CHECK-NEXT: S_NOP 0, implicit %4
3316 ; CHECK-NEXT: undef %5.sub0:vreg_64_align2 = V_MOV_B32_e32 28, implicit $exec
3317 ; CHECK-NEXT: %5.sub1:vreg_64_align2 = V_MOV_B32_e32 29, implicit $exec
3318 ; CHECK-NEXT: S_NOP 0, implicit %5
3319 undef %0.sub0:vreg_320_align2 = V_MOV_B32_e32 00, implicit $exec
3320 %0.sub1:vreg_320_align2 = V_MOV_B32_e32 01, implicit $exec
3321 S_NOP 0, implicit %0.sub0_sub1
3323 undef %1.sub2:vreg_320_align2 = V_MOV_B32_e32 12, implicit $exec
3324 %1.sub3:vreg_320_align2 = V_MOV_B32_e32 13, implicit $exec
3325 S_NOP 0, implicit %1.sub2_sub3
3327 undef %2.sub8:vreg_320_align2 = V_MOV_B32_e32 28, implicit $exec
3328 %2.sub9:vreg_320_align2 = V_MOV_B32_e32 29, implicit $exec
3329 S_NOP 0, implicit %2.sub8_sub9
3332 # Skip test_vreg_320_align2_w96: the 96-bit subreg isn't fully supported for the regclass vreg_320_align2
3334 name: test_vreg_320_align2_w128
3335 tracksRegLiveness: true
3338 ; CHECK-LABEL: name: test_vreg_320_align2_w128
3339 ; CHECK: undef %3.sub0:vreg_128_align2 = V_MOV_B32_e32 0, implicit $exec
3340 ; CHECK-NEXT: %3.sub1:vreg_128_align2 = V_MOV_B32_e32 1, implicit $exec
3341 ; CHECK-NEXT: %3.sub2:vreg_128_align2 = V_MOV_B32_e32 2, implicit $exec
3342 ; CHECK-NEXT: %3.sub3:vreg_128_align2 = V_MOV_B32_e32 3, implicit $exec
3343 ; CHECK-NEXT: S_NOP 0, implicit %3
3344 ; CHECK-NEXT: undef %4.sub0:vreg_128_align2 = V_MOV_B32_e32 12, implicit $exec
3345 ; CHECK-NEXT: %4.sub1:vreg_128_align2 = V_MOV_B32_e32 13, implicit $exec
3346 ; CHECK-NEXT: %4.sub2:vreg_128_align2 = V_MOV_B32_e32 14, implicit $exec
3347 ; CHECK-NEXT: %4.sub3:vreg_128_align2 = V_MOV_B32_e32 15, implicit $exec
3348 ; CHECK-NEXT: S_NOP 0, implicit %4
3349 ; CHECK-NEXT: undef %5.sub0:vreg_128_align2 = V_MOV_B32_e32 26, implicit $exec
3350 ; CHECK-NEXT: %5.sub1:vreg_128_align2 = V_MOV_B32_e32 27, implicit $exec
3351 ; CHECK-NEXT: %5.sub2:vreg_128_align2 = V_MOV_B32_e32 28, implicit $exec
3352 ; CHECK-NEXT: %5.sub3:vreg_128_align2 = V_MOV_B32_e32 29, implicit $exec
3353 ; CHECK-NEXT: S_NOP 0, implicit %5
3354 undef %0.sub0:vreg_320_align2 = V_MOV_B32_e32 00, implicit $exec
3355 %0.sub1:vreg_320_align2 = V_MOV_B32_e32 01, implicit $exec
3356 %0.sub2:vreg_320_align2 = V_MOV_B32_e32 02, implicit $exec
3357 %0.sub3:vreg_320_align2 = V_MOV_B32_e32 03, implicit $exec
3358 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3
3360 undef %1.sub2:vreg_320_align2 = V_MOV_B32_e32 12, implicit $exec
3361 %1.sub3:vreg_320_align2 = V_MOV_B32_e32 13, implicit $exec
3362 %1.sub4:vreg_320_align2 = V_MOV_B32_e32 14, implicit $exec
3363 %1.sub5:vreg_320_align2 = V_MOV_B32_e32 15, implicit $exec
3364 S_NOP 0, implicit %1.sub2_sub3_sub4_sub5
3366 undef %2.sub6:vreg_320_align2 = V_MOV_B32_e32 26, implicit $exec
3367 %2.sub7:vreg_320_align2 = V_MOV_B32_e32 27, implicit $exec
3368 %2.sub8:vreg_320_align2 = V_MOV_B32_e32 28, implicit $exec
3369 %2.sub9:vreg_320_align2 = V_MOV_B32_e32 29, implicit $exec
3370 S_NOP 0, implicit %2.sub6_sub7_sub8_sub9
3373 # Skip test_vreg_320_align2_w160: the 160-bit subreg isn't fully supported for the regclass vreg_320_align2
3375 name: test_vreg_320_align2_w192
3376 tracksRegLiveness: true
3379 ; CHECK-LABEL: name: test_vreg_320_align2_w192
3380 ; CHECK: undef %3.sub0:vreg_192_align2 = V_MOV_B32_e32 0, implicit $exec
3381 ; CHECK-NEXT: %3.sub1:vreg_192_align2 = V_MOV_B32_e32 1, implicit $exec
3382 ; CHECK-NEXT: %3.sub2:vreg_192_align2 = V_MOV_B32_e32 2, implicit $exec
3383 ; CHECK-NEXT: %3.sub3:vreg_192_align2 = V_MOV_B32_e32 3, implicit $exec
3384 ; CHECK-NEXT: %3.sub4:vreg_192_align2 = V_MOV_B32_e32 4, implicit $exec
3385 ; CHECK-NEXT: %3.sub5:vreg_192_align2 = V_MOV_B32_e32 5, implicit $exec
3386 ; CHECK-NEXT: S_NOP 0, implicit %3
3387 ; CHECK-NEXT: undef %4.sub0:vreg_192_align2 = V_MOV_B32_e32 12, implicit $exec
3388 ; CHECK-NEXT: %4.sub1:vreg_192_align2 = V_MOV_B32_e32 13, implicit $exec
3389 ; CHECK-NEXT: %4.sub2:vreg_192_align2 = V_MOV_B32_e32 14, implicit $exec
3390 ; CHECK-NEXT: %4.sub3:vreg_192_align2 = V_MOV_B32_e32 15, implicit $exec
3391 ; CHECK-NEXT: %4.sub4:vreg_192_align2 = V_MOV_B32_e32 16, implicit $exec
3392 ; CHECK-NEXT: %4.sub5:vreg_192_align2 = V_MOV_B32_e32 17, implicit $exec
3393 ; CHECK-NEXT: S_NOP 0, implicit %4
3394 ; CHECK-NEXT: undef %5.sub0:vreg_192_align2 = V_MOV_B32_e32 24, implicit $exec
3395 ; CHECK-NEXT: %5.sub1:vreg_192_align2 = V_MOV_B32_e32 25, implicit $exec
3396 ; CHECK-NEXT: %5.sub2:vreg_192_align2 = V_MOV_B32_e32 26, implicit $exec
3397 ; CHECK-NEXT: %5.sub3:vreg_192_align2 = V_MOV_B32_e32 27, implicit $exec
3398 ; CHECK-NEXT: %5.sub4:vreg_192_align2 = V_MOV_B32_e32 28, implicit $exec
3399 ; CHECK-NEXT: %5.sub5:vreg_192_align2 = V_MOV_B32_e32 29, implicit $exec
3400 ; CHECK-NEXT: S_NOP 0, implicit %5
3401 undef %0.sub0:vreg_320_align2 = V_MOV_B32_e32 00, implicit $exec
3402 %0.sub1:vreg_320_align2 = V_MOV_B32_e32 01, implicit $exec
3403 %0.sub2:vreg_320_align2 = V_MOV_B32_e32 02, implicit $exec
3404 %0.sub3:vreg_320_align2 = V_MOV_B32_e32 03, implicit $exec
3405 %0.sub4:vreg_320_align2 = V_MOV_B32_e32 04, implicit $exec
3406 %0.sub5:vreg_320_align2 = V_MOV_B32_e32 05, implicit $exec
3407 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5
3409 undef %1.sub2:vreg_320_align2 = V_MOV_B32_e32 12, implicit $exec
3410 %1.sub3:vreg_320_align2 = V_MOV_B32_e32 13, implicit $exec
3411 %1.sub4:vreg_320_align2 = V_MOV_B32_e32 14, implicit $exec
3412 %1.sub5:vreg_320_align2 = V_MOV_B32_e32 15, implicit $exec
3413 %1.sub6:vreg_320_align2 = V_MOV_B32_e32 16, implicit $exec
3414 %1.sub7:vreg_320_align2 = V_MOV_B32_e32 17, implicit $exec
3415 S_NOP 0, implicit %1.sub2_sub3_sub4_sub5_sub6_sub7
3417 undef %2.sub4:vreg_320_align2 = V_MOV_B32_e32 24, implicit $exec
3418 %2.sub5:vreg_320_align2 = V_MOV_B32_e32 25, implicit $exec
3419 %2.sub6:vreg_320_align2 = V_MOV_B32_e32 26, implicit $exec
3420 %2.sub7:vreg_320_align2 = V_MOV_B32_e32 27, implicit $exec
3421 %2.sub8:vreg_320_align2 = V_MOV_B32_e32 28, implicit $exec
3422 %2.sub9:vreg_320_align2 = V_MOV_B32_e32 29, implicit $exec
3423 S_NOP 0, implicit %2.sub4_sub5_sub6_sub7_sub8_sub9
3427 name: test_vreg_320_align2_w256
3428 tracksRegLiveness: true
3431 ; CHECK-LABEL: name: test_vreg_320_align2_w256
3432 ; CHECK: undef %2.sub0:vreg_256_align2 = V_MOV_B32_e32 0, implicit $exec
3433 ; CHECK-NEXT: %2.sub1:vreg_256_align2 = V_MOV_B32_e32 1, implicit $exec
3434 ; CHECK-NEXT: %2.sub2:vreg_256_align2 = V_MOV_B32_e32 2, implicit $exec
3435 ; CHECK-NEXT: %2.sub3:vreg_256_align2 = V_MOV_B32_e32 3, implicit $exec
3436 ; CHECK-NEXT: %2.sub4:vreg_256_align2 = V_MOV_B32_e32 4, implicit $exec
3437 ; CHECK-NEXT: %2.sub5:vreg_256_align2 = V_MOV_B32_e32 5, implicit $exec
3438 ; CHECK-NEXT: %2.sub6:vreg_256_align2 = V_MOV_B32_e32 6, implicit $exec
3439 ; CHECK-NEXT: %2.sub7:vreg_256_align2 = V_MOV_B32_e32 7, implicit $exec
3440 ; CHECK-NEXT: S_NOP 0, implicit %2
3441 ; CHECK-NEXT: undef %3.sub0:vreg_256_align2 = V_MOV_B32_e32 12, implicit $exec
3442 ; CHECK-NEXT: %3.sub1:vreg_256_align2 = V_MOV_B32_e32 13, implicit $exec
3443 ; CHECK-NEXT: %3.sub2:vreg_256_align2 = V_MOV_B32_e32 14, implicit $exec
3444 ; CHECK-NEXT: %3.sub3:vreg_256_align2 = V_MOV_B32_e32 15, implicit $exec
3445 ; CHECK-NEXT: %3.sub4:vreg_256_align2 = V_MOV_B32_e32 16, implicit $exec
3446 ; CHECK-NEXT: %3.sub5:vreg_256_align2 = V_MOV_B32_e32 17, implicit $exec
3447 ; CHECK-NEXT: %3.sub6:vreg_256_align2 = V_MOV_B32_e32 18, implicit $exec
3448 ; CHECK-NEXT: %3.sub7:vreg_256_align2 = V_MOV_B32_e32 19, implicit $exec
3449 ; CHECK-NEXT: S_NOP 0, implicit %3
3450 undef %0.sub0:vreg_320_align2 = V_MOV_B32_e32 00, implicit $exec
3451 %0.sub1:vreg_320_align2 = V_MOV_B32_e32 01, implicit $exec
3452 %0.sub2:vreg_320_align2 = V_MOV_B32_e32 02, implicit $exec
3453 %0.sub3:vreg_320_align2 = V_MOV_B32_e32 03, implicit $exec
3454 %0.sub4:vreg_320_align2 = V_MOV_B32_e32 04, implicit $exec
3455 %0.sub5:vreg_320_align2 = V_MOV_B32_e32 05, implicit $exec
3456 %0.sub6:vreg_320_align2 = V_MOV_B32_e32 06, implicit $exec
3457 %0.sub7:vreg_320_align2 = V_MOV_B32_e32 07, implicit $exec
3458 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7
3460 undef %1.sub2:vreg_320_align2 = V_MOV_B32_e32 12, implicit $exec
3461 %1.sub3:vreg_320_align2 = V_MOV_B32_e32 13, implicit $exec
3462 %1.sub4:vreg_320_align2 = V_MOV_B32_e32 14, implicit $exec
3463 %1.sub5:vreg_320_align2 = V_MOV_B32_e32 15, implicit $exec
3464 %1.sub6:vreg_320_align2 = V_MOV_B32_e32 16, implicit $exec
3465 %1.sub7:vreg_320_align2 = V_MOV_B32_e32 17, implicit $exec
3466 %1.sub8:vreg_320_align2 = V_MOV_B32_e32 18, implicit $exec
3467 %1.sub9:vreg_320_align2 = V_MOV_B32_e32 19, implicit $exec
3468 S_NOP 0, implicit %1.sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9
3472 name: test_vreg_352_align2_w32
3473 tracksRegLiveness: true
3476 ; CHECK-LABEL: name: test_vreg_352_align2_w32
3477 ; CHECK: undef %0.sub0:vreg_352_align2 = V_MOV_B32_e32 0, implicit $exec
3478 ; CHECK-NEXT: S_NOP 0, implicit %0.sub0
3479 ; CHECK-NEXT: undef %1.sub1:vreg_352_align2 = V_MOV_B32_e32 11, implicit $exec
3480 ; CHECK-NEXT: S_NOP 0, implicit %1.sub1
3481 ; CHECK-NEXT: undef %2.sub10:vreg_352_align2 = V_MOV_B32_e32 210, implicit $exec
3482 ; CHECK-NEXT: S_NOP 0, implicit %2.sub10
3483 undef %0.sub0:vreg_352_align2 = V_MOV_B32_e32 00, implicit $exec
3484 S_NOP 0, implicit %0.sub0
3486 undef %1.sub1:vreg_352_align2 = V_MOV_B32_e32 11, implicit $exec
3487 S_NOP 0, implicit %1.sub1
3489 undef %2.sub10:vreg_352_align2 = V_MOV_B32_e32 210, implicit $exec
3490 S_NOP 0, implicit %2.sub10
3493 # Skip test_vreg_352_align2_w64: the 64-bit subreg isn't fully supported for the regclass vreg_352_align2
3495 name: test_vreg_352_align2_w96
3496 tracksRegLiveness: true
3499 ; CHECK-LABEL: name: test_vreg_352_align2_w96
3500 ; CHECK: undef %3.sub0:vreg_96_align2 = V_MOV_B32_e32 0, implicit $exec
3501 ; CHECK-NEXT: %3.sub1:vreg_96_align2 = V_MOV_B32_e32 1, implicit $exec
3502 ; CHECK-NEXT: %3.sub2:vreg_96_align2 = V_MOV_B32_e32 2, implicit $exec
3503 ; CHECK-NEXT: S_NOP 0, implicit %3
3504 ; CHECK-NEXT: undef %4.sub0:vreg_96_align2 = V_MOV_B32_e32 12, implicit $exec
3505 ; CHECK-NEXT: %4.sub1:vreg_96_align2 = V_MOV_B32_e32 13, implicit $exec
3506 ; CHECK-NEXT: %4.sub2:vreg_96_align2 = V_MOV_B32_e32 14, implicit $exec
3507 ; CHECK-NEXT: S_NOP 0, implicit %4
3508 ; CHECK-NEXT: undef %5.sub0:vreg_96_align2 = V_MOV_B32_e32 28, implicit $exec
3509 ; CHECK-NEXT: %5.sub1:vreg_96_align2 = V_MOV_B32_e32 29, implicit $exec
3510 ; CHECK-NEXT: %5.sub2:vreg_96_align2 = V_MOV_B32_e32 210, implicit $exec
3511 ; CHECK-NEXT: S_NOP 0, implicit %5
3512 undef %0.sub0:vreg_352_align2 = V_MOV_B32_e32 00, implicit $exec
3513 %0.sub1:vreg_352_align2 = V_MOV_B32_e32 01, implicit $exec
3514 %0.sub2:vreg_352_align2 = V_MOV_B32_e32 02, implicit $exec
3515 S_NOP 0, implicit %0.sub0_sub1_sub2
3517 undef %1.sub2:vreg_352_align2 = V_MOV_B32_e32 12, implicit $exec
3518 %1.sub3:vreg_352_align2 = V_MOV_B32_e32 13, implicit $exec
3519 %1.sub4:vreg_352_align2 = V_MOV_B32_e32 14, implicit $exec
3520 S_NOP 0, implicit %1.sub2_sub3_sub4
3522 undef %2.sub8:vreg_352_align2 = V_MOV_B32_e32 28, implicit $exec
3523 %2.sub9:vreg_352_align2 = V_MOV_B32_e32 29, implicit $exec
3524 %2.sub10:vreg_352_align2 = V_MOV_B32_e32 210, implicit $exec
3525 S_NOP 0, implicit %2.sub8_sub9_sub10
3528 # Skip test_vreg_352_align2_w128: the 128-bit subreg isn't fully supported for the regclass vreg_352_align2
3530 name: test_vreg_352_align2_w160
3531 tracksRegLiveness: true
3534 ; CHECK-LABEL: name: test_vreg_352_align2_w160
3535 ; CHECK: undef %3.sub0:vreg_160_align2 = V_MOV_B32_e32 0, implicit $exec
3536 ; CHECK-NEXT: %3.sub1:vreg_160_align2 = V_MOV_B32_e32 1, implicit $exec
3537 ; CHECK-NEXT: %3.sub2:vreg_160_align2 = V_MOV_B32_e32 2, implicit $exec
3538 ; CHECK-NEXT: %3.sub3:vreg_160_align2 = V_MOV_B32_e32 3, implicit $exec
3539 ; CHECK-NEXT: %3.sub4:vreg_160_align2 = V_MOV_B32_e32 4, implicit $exec
3540 ; CHECK-NEXT: S_NOP 0, implicit %3
3541 ; CHECK-NEXT: undef %4.sub0:vreg_160_align2 = V_MOV_B32_e32 12, implicit $exec
3542 ; CHECK-NEXT: %4.sub1:vreg_160_align2 = V_MOV_B32_e32 13, implicit $exec
3543 ; CHECK-NEXT: %4.sub2:vreg_160_align2 = V_MOV_B32_e32 14, implicit $exec
3544 ; CHECK-NEXT: %4.sub3:vreg_160_align2 = V_MOV_B32_e32 15, implicit $exec
3545 ; CHECK-NEXT: %4.sub4:vreg_160_align2 = V_MOV_B32_e32 16, implicit $exec
3546 ; CHECK-NEXT: S_NOP 0, implicit %4
3547 ; CHECK-NEXT: undef %5.sub0:vreg_160_align2 = V_MOV_B32_e32 26, implicit $exec
3548 ; CHECK-NEXT: %5.sub1:vreg_160_align2 = V_MOV_B32_e32 27, implicit $exec
3549 ; CHECK-NEXT: %5.sub2:vreg_160_align2 = V_MOV_B32_e32 28, implicit $exec
3550 ; CHECK-NEXT: %5.sub3:vreg_160_align2 = V_MOV_B32_e32 29, implicit $exec
3551 ; CHECK-NEXT: %5.sub4:vreg_160_align2 = V_MOV_B32_e32 210, implicit $exec
3552 ; CHECK-NEXT: S_NOP 0, implicit %5
3553 undef %0.sub0:vreg_352_align2 = V_MOV_B32_e32 00, implicit $exec
3554 %0.sub1:vreg_352_align2 = V_MOV_B32_e32 01, implicit $exec
3555 %0.sub2:vreg_352_align2 = V_MOV_B32_e32 02, implicit $exec
3556 %0.sub3:vreg_352_align2 = V_MOV_B32_e32 03, implicit $exec
3557 %0.sub4:vreg_352_align2 = V_MOV_B32_e32 04, implicit $exec
3558 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4
3560 undef %1.sub2:vreg_352_align2 = V_MOV_B32_e32 12, implicit $exec
3561 %1.sub3:vreg_352_align2 = V_MOV_B32_e32 13, implicit $exec
3562 %1.sub4:vreg_352_align2 = V_MOV_B32_e32 14, implicit $exec
3563 %1.sub5:vreg_352_align2 = V_MOV_B32_e32 15, implicit $exec
3564 %1.sub6:vreg_352_align2 = V_MOV_B32_e32 16, implicit $exec
3565 S_NOP 0, implicit %1.sub2_sub3_sub4_sub5_sub6
3567 undef %2.sub6:vreg_352_align2 = V_MOV_B32_e32 26, implicit $exec
3568 %2.sub7:vreg_352_align2 = V_MOV_B32_e32 27, implicit $exec
3569 %2.sub8:vreg_352_align2 = V_MOV_B32_e32 28, implicit $exec
3570 %2.sub9:vreg_352_align2 = V_MOV_B32_e32 29, implicit $exec
3571 %2.sub10:vreg_352_align2 = V_MOV_B32_e32 210, implicit $exec
3572 S_NOP 0, implicit %2.sub6_sub7_sub8_sub9_sub10
3575 # Skip test_vreg_352_align2_w192: the 192-bit subreg isn't fully supported for the regclass vreg_352_align2
3576 # Skip test_vreg_352_align2_w256: the 256-bit subreg isn't fully supported for the regclass vreg_352_align2
3578 name: test_vreg_384_align2_w32
3579 tracksRegLiveness: true
3582 ; CHECK-LABEL: name: test_vreg_384_align2_w32
3583 ; CHECK: undef %0.sub0:vreg_384_align2 = V_MOV_B32_e32 0, implicit $exec
3584 ; CHECK-NEXT: S_NOP 0, implicit %0.sub0
3585 ; CHECK-NEXT: undef %1.sub1:vreg_384_align2 = V_MOV_B32_e32 11, implicit $exec
3586 ; CHECK-NEXT: S_NOP 0, implicit %1.sub1
3587 ; CHECK-NEXT: undef %2.sub11:vreg_384_align2 = V_MOV_B32_e32 211, implicit $exec
3588 ; CHECK-NEXT: S_NOP 0, implicit %2.sub11
3589 undef %0.sub0:vreg_384_align2 = V_MOV_B32_e32 00, implicit $exec
3590 S_NOP 0, implicit %0.sub0
3592 undef %1.sub1:vreg_384_align2 = V_MOV_B32_e32 11, implicit $exec
3593 S_NOP 0, implicit %1.sub1
3595 undef %2.sub11:vreg_384_align2 = V_MOV_B32_e32 211, implicit $exec
3596 S_NOP 0, implicit %2.sub11
3600 name: test_vreg_384_align2_w64
3601 tracksRegLiveness: true
3604 ; CHECK-LABEL: name: test_vreg_384_align2_w64
3605 ; CHECK: undef %3.sub0:vreg_64_align2 = V_MOV_B32_e32 0, implicit $exec
3606 ; CHECK-NEXT: %3.sub1:vreg_64_align2 = V_MOV_B32_e32 1, implicit $exec
3607 ; CHECK-NEXT: S_NOP 0, implicit %3
3608 ; CHECK-NEXT: undef %4.sub0:vreg_64_align2 = V_MOV_B32_e32 110, implicit $exec
3609 ; CHECK-NEXT: %4.sub1:vreg_64_align2 = V_MOV_B32_e32 111, implicit $exec
3610 ; CHECK-NEXT: S_NOP 0, implicit %4
3611 ; CHECK-NEXT: undef %5.sub0:vreg_64_align2 = V_MOV_B32_e32 22, implicit $exec
3612 ; CHECK-NEXT: %5.sub1:vreg_64_align2 = V_MOV_B32_e32 23, implicit $exec
3613 ; CHECK-NEXT: S_NOP 0, implicit %5
3614 undef %0.sub0:vreg_384_align2 = V_MOV_B32_e32 00, implicit $exec
3615 %0.sub1:vreg_384_align2 = V_MOV_B32_e32 01, implicit $exec
3616 S_NOP 0, implicit %0.sub0_sub1
3618 undef %1.sub10:vreg_384_align2 = V_MOV_B32_e32 110, implicit $exec
3619 %1.sub11:vreg_384_align2 = V_MOV_B32_e32 111, implicit $exec
3620 S_NOP 0, implicit %1.sub10_sub11
3622 undef %2.sub2:vreg_384_align2 = V_MOV_B32_e32 22, implicit $exec
3623 %2.sub3:vreg_384_align2 = V_MOV_B32_e32 23, implicit $exec
3624 S_NOP 0, implicit %2.sub2_sub3
3627 # Skip test_vreg_384_align2_w96: the 96-bit subreg isn't fully supported for the regclass vreg_384_align2
3629 name: test_vreg_384_align2_w128
3630 tracksRegLiveness: true
3633 ; CHECK-LABEL: name: test_vreg_384_align2_w128
3634 ; CHECK: undef %3.sub0:vreg_128_align2 = V_MOV_B32_e32 0, implicit $exec
3635 ; CHECK-NEXT: %3.sub1:vreg_128_align2 = V_MOV_B32_e32 1, implicit $exec
3636 ; CHECK-NEXT: %3.sub2:vreg_128_align2 = V_MOV_B32_e32 2, implicit $exec
3637 ; CHECK-NEXT: %3.sub3:vreg_128_align2 = V_MOV_B32_e32 3, implicit $exec
3638 ; CHECK-NEXT: S_NOP 0, implicit %3
3639 ; CHECK-NEXT: undef %4.sub0:vreg_128_align2 = V_MOV_B32_e32 12, implicit $exec
3640 ; CHECK-NEXT: %4.sub1:vreg_128_align2 = V_MOV_B32_e32 13, implicit $exec
3641 ; CHECK-NEXT: %4.sub2:vreg_128_align2 = V_MOV_B32_e32 14, implicit $exec
3642 ; CHECK-NEXT: %4.sub3:vreg_128_align2 = V_MOV_B32_e32 15, implicit $exec
3643 ; CHECK-NEXT: S_NOP 0, implicit %4
3644 ; CHECK-NEXT: undef %5.sub0:vreg_128_align2 = V_MOV_B32_e32 28, implicit $exec
3645 ; CHECK-NEXT: %5.sub1:vreg_128_align2 = V_MOV_B32_e32 29, implicit $exec
3646 ; CHECK-NEXT: %5.sub2:vreg_128_align2 = V_MOV_B32_e32 210, implicit $exec
3647 ; CHECK-NEXT: %5.sub3:vreg_128_align2 = V_MOV_B32_e32 211, implicit $exec
3648 ; CHECK-NEXT: S_NOP 0, implicit %5
3649 undef %0.sub0:vreg_384_align2 = V_MOV_B32_e32 00, implicit $exec
3650 %0.sub1:vreg_384_align2 = V_MOV_B32_e32 01, implicit $exec
3651 %0.sub2:vreg_384_align2 = V_MOV_B32_e32 02, implicit $exec
3652 %0.sub3:vreg_384_align2 = V_MOV_B32_e32 03, implicit $exec
3653 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3
3655 undef %1.sub2:vreg_384_align2 = V_MOV_B32_e32 12, implicit $exec
3656 %1.sub3:vreg_384_align2 = V_MOV_B32_e32 13, implicit $exec
3657 %1.sub4:vreg_384_align2 = V_MOV_B32_e32 14, implicit $exec
3658 %1.sub5:vreg_384_align2 = V_MOV_B32_e32 15, implicit $exec
3659 S_NOP 0, implicit %1.sub2_sub3_sub4_sub5
3661 undef %2.sub8:vreg_384_align2 = V_MOV_B32_e32 28, implicit $exec
3662 %2.sub9:vreg_384_align2 = V_MOV_B32_e32 29, implicit $exec
3663 %2.sub10:vreg_384_align2 = V_MOV_B32_e32 210, implicit $exec
3664 %2.sub11:vreg_384_align2 = V_MOV_B32_e32 211, implicit $exec
3665 S_NOP 0, implicit %2.sub8_sub9_sub10_sub11
3668 # Skip test_vreg_384_align2_w160: the 160-bit subreg isn't fully supported for the regclass vreg_384_align2
3670 name: test_vreg_384_align2_w192
3671 tracksRegLiveness: true
3674 ; CHECK-LABEL: name: test_vreg_384_align2_w192
3675 ; CHECK: undef %3.sub0:vreg_192_align2 = V_MOV_B32_e32 0, implicit $exec
3676 ; CHECK-NEXT: %3.sub1:vreg_192_align2 = V_MOV_B32_e32 1, implicit $exec
3677 ; CHECK-NEXT: %3.sub2:vreg_192_align2 = V_MOV_B32_e32 2, implicit $exec
3678 ; CHECK-NEXT: %3.sub3:vreg_192_align2 = V_MOV_B32_e32 3, implicit $exec
3679 ; CHECK-NEXT: %3.sub4:vreg_192_align2 = V_MOV_B32_e32 4, implicit $exec
3680 ; CHECK-NEXT: %3.sub5:vreg_192_align2 = V_MOV_B32_e32 5, implicit $exec
3681 ; CHECK-NEXT: S_NOP 0, implicit %3
3682 ; CHECK-NEXT: undef %4.sub0:vreg_192_align2 = V_MOV_B32_e32 12, implicit $exec
3683 ; CHECK-NEXT: %4.sub1:vreg_192_align2 = V_MOV_B32_e32 13, implicit $exec
3684 ; CHECK-NEXT: %4.sub2:vreg_192_align2 = V_MOV_B32_e32 14, implicit $exec
3685 ; CHECK-NEXT: %4.sub3:vreg_192_align2 = V_MOV_B32_e32 15, implicit $exec
3686 ; CHECK-NEXT: %4.sub4:vreg_192_align2 = V_MOV_B32_e32 16, implicit $exec
3687 ; CHECK-NEXT: %4.sub5:vreg_192_align2 = V_MOV_B32_e32 17, implicit $exec
3688 ; CHECK-NEXT: S_NOP 0, implicit %4
3689 ; CHECK-NEXT: undef %5.sub0:vreg_192_align2 = V_MOV_B32_e32 26, implicit $exec
3690 ; CHECK-NEXT: %5.sub1:vreg_192_align2 = V_MOV_B32_e32 27, implicit $exec
3691 ; CHECK-NEXT: %5.sub2:vreg_192_align2 = V_MOV_B32_e32 28, implicit $exec
3692 ; CHECK-NEXT: %5.sub3:vreg_192_align2 = V_MOV_B32_e32 29, implicit $exec
3693 ; CHECK-NEXT: %5.sub4:vreg_192_align2 = V_MOV_B32_e32 210, implicit $exec
3694 ; CHECK-NEXT: %5.sub5:vreg_192_align2 = V_MOV_B32_e32 211, implicit $exec
3695 ; CHECK-NEXT: S_NOP 0, implicit %5
3696 undef %0.sub0:vreg_384_align2 = V_MOV_B32_e32 00, implicit $exec
3697 %0.sub1:vreg_384_align2 = V_MOV_B32_e32 01, implicit $exec
3698 %0.sub2:vreg_384_align2 = V_MOV_B32_e32 02, implicit $exec
3699 %0.sub3:vreg_384_align2 = V_MOV_B32_e32 03, implicit $exec
3700 %0.sub4:vreg_384_align2 = V_MOV_B32_e32 04, implicit $exec
3701 %0.sub5:vreg_384_align2 = V_MOV_B32_e32 05, implicit $exec
3702 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5
3704 undef %1.sub2:vreg_384_align2 = V_MOV_B32_e32 12, implicit $exec
3705 %1.sub3:vreg_384_align2 = V_MOV_B32_e32 13, implicit $exec
3706 %1.sub4:vreg_384_align2 = V_MOV_B32_e32 14, implicit $exec
3707 %1.sub5:vreg_384_align2 = V_MOV_B32_e32 15, implicit $exec
3708 %1.sub6:vreg_384_align2 = V_MOV_B32_e32 16, implicit $exec
3709 %1.sub7:vreg_384_align2 = V_MOV_B32_e32 17, implicit $exec
3710 S_NOP 0, implicit %1.sub2_sub3_sub4_sub5_sub6_sub7
3712 undef %2.sub6:vreg_384_align2 = V_MOV_B32_e32 26, implicit $exec
3713 %2.sub7:vreg_384_align2 = V_MOV_B32_e32 27, implicit $exec
3714 %2.sub8:vreg_384_align2 = V_MOV_B32_e32 28, implicit $exec
3715 %2.sub9:vreg_384_align2 = V_MOV_B32_e32 29, implicit $exec
3716 %2.sub10:vreg_384_align2 = V_MOV_B32_e32 210, implicit $exec
3717 %2.sub11:vreg_384_align2 = V_MOV_B32_e32 211, implicit $exec
3718 S_NOP 0, implicit %2.sub6_sub7_sub8_sub9_sub10_sub11
3722 name: test_vreg_384_align2_w256
3723 tracksRegLiveness: true
3726 ; CHECK-LABEL: name: test_vreg_384_align2_w256
3727 ; CHECK: undef %3.sub0:vreg_256_align2 = V_MOV_B32_e32 0, implicit $exec
3728 ; CHECK-NEXT: %3.sub1:vreg_256_align2 = V_MOV_B32_e32 1, implicit $exec
3729 ; CHECK-NEXT: %3.sub2:vreg_256_align2 = V_MOV_B32_e32 2, implicit $exec
3730 ; CHECK-NEXT: %3.sub3:vreg_256_align2 = V_MOV_B32_e32 3, implicit $exec
3731 ; CHECK-NEXT: %3.sub4:vreg_256_align2 = V_MOV_B32_e32 4, implicit $exec
3732 ; CHECK-NEXT: %3.sub5:vreg_256_align2 = V_MOV_B32_e32 5, implicit $exec
3733 ; CHECK-NEXT: %3.sub6:vreg_256_align2 = V_MOV_B32_e32 6, implicit $exec
3734 ; CHECK-NEXT: %3.sub7:vreg_256_align2 = V_MOV_B32_e32 7, implicit $exec
3735 ; CHECK-NEXT: S_NOP 0, implicit %3
3736 ; CHECK-NEXT: undef %4.sub0:vreg_256_align2 = V_MOV_B32_e32 12, implicit $exec
3737 ; CHECK-NEXT: %4.sub1:vreg_256_align2 = V_MOV_B32_e32 13, implicit $exec
3738 ; CHECK-NEXT: %4.sub2:vreg_256_align2 = V_MOV_B32_e32 14, implicit $exec
3739 ; CHECK-NEXT: %4.sub3:vreg_256_align2 = V_MOV_B32_e32 15, implicit $exec
3740 ; CHECK-NEXT: %4.sub4:vreg_256_align2 = V_MOV_B32_e32 16, implicit $exec
3741 ; CHECK-NEXT: %4.sub5:vreg_256_align2 = V_MOV_B32_e32 17, implicit $exec
3742 ; CHECK-NEXT: %4.sub6:vreg_256_align2 = V_MOV_B32_e32 18, implicit $exec
3743 ; CHECK-NEXT: %4.sub7:vreg_256_align2 = V_MOV_B32_e32 19, implicit $exec
3744 ; CHECK-NEXT: S_NOP 0, implicit %4
3745 ; CHECK-NEXT: undef %5.sub0:vreg_256_align2 = V_MOV_B32_e32 24, implicit $exec
3746 ; CHECK-NEXT: %5.sub1:vreg_256_align2 = V_MOV_B32_e32 25, implicit $exec
3747 ; CHECK-NEXT: %5.sub2:vreg_256_align2 = V_MOV_B32_e32 26, implicit $exec
3748 ; CHECK-NEXT: %5.sub3:vreg_256_align2 = V_MOV_B32_e32 27, implicit $exec
3749 ; CHECK-NEXT: %5.sub4:vreg_256_align2 = V_MOV_B32_e32 28, implicit $exec
3750 ; CHECK-NEXT: %5.sub5:vreg_256_align2 = V_MOV_B32_e32 29, implicit $exec
3751 ; CHECK-NEXT: %5.sub6:vreg_256_align2 = V_MOV_B32_e32 210, implicit $exec
3752 ; CHECK-NEXT: %5.sub7:vreg_256_align2 = V_MOV_B32_e32 211, implicit $exec
3753 ; CHECK-NEXT: S_NOP 0, implicit %5
3754 undef %0.sub0:vreg_384_align2 = V_MOV_B32_e32 00, implicit $exec
3755 %0.sub1:vreg_384_align2 = V_MOV_B32_e32 01, implicit $exec
3756 %0.sub2:vreg_384_align2 = V_MOV_B32_e32 02, implicit $exec
3757 %0.sub3:vreg_384_align2 = V_MOV_B32_e32 03, implicit $exec
3758 %0.sub4:vreg_384_align2 = V_MOV_B32_e32 04, implicit $exec
3759 %0.sub5:vreg_384_align2 = V_MOV_B32_e32 05, implicit $exec
3760 %0.sub6:vreg_384_align2 = V_MOV_B32_e32 06, implicit $exec
3761 %0.sub7:vreg_384_align2 = V_MOV_B32_e32 07, implicit $exec
3762 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7
3764 undef %1.sub2:vreg_384_align2 = V_MOV_B32_e32 12, implicit $exec
3765 %1.sub3:vreg_384_align2 = V_MOV_B32_e32 13, implicit $exec
3766 %1.sub4:vreg_384_align2 = V_MOV_B32_e32 14, implicit $exec
3767 %1.sub5:vreg_384_align2 = V_MOV_B32_e32 15, implicit $exec
3768 %1.sub6:vreg_384_align2 = V_MOV_B32_e32 16, implicit $exec
3769 %1.sub7:vreg_384_align2 = V_MOV_B32_e32 17, implicit $exec
3770 %1.sub8:vreg_384_align2 = V_MOV_B32_e32 18, implicit $exec
3771 %1.sub9:vreg_384_align2 = V_MOV_B32_e32 19, implicit $exec
3772 S_NOP 0, implicit %1.sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9
3774 undef %2.sub4:vreg_384_align2 = V_MOV_B32_e32 24, implicit $exec
3775 %2.sub5:vreg_384_align2 = V_MOV_B32_e32 25, implicit $exec
3776 %2.sub6:vreg_384_align2 = V_MOV_B32_e32 26, implicit $exec
3777 %2.sub7:vreg_384_align2 = V_MOV_B32_e32 27, implicit $exec
3778 %2.sub8:vreg_384_align2 = V_MOV_B32_e32 28, implicit $exec
3779 %2.sub9:vreg_384_align2 = V_MOV_B32_e32 29, implicit $exec
3780 %2.sub10:vreg_384_align2 = V_MOV_B32_e32 210, implicit $exec
3781 %2.sub11:vreg_384_align2 = V_MOV_B32_e32 211, implicit $exec
3782 S_NOP 0, implicit %2.sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11
3786 name: test_vreg_512_align2_w32
3787 tracksRegLiveness: true
3790 ; CHECK-LABEL: name: test_vreg_512_align2_w32
3791 ; CHECK: undef %0.sub0:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec
3792 ; CHECK-NEXT: S_NOP 0, implicit %0.sub0
3793 ; CHECK-NEXT: undef %1.sub1:vreg_512_align2 = V_MOV_B32_e32 11, implicit $exec
3794 ; CHECK-NEXT: S_NOP 0, implicit %1.sub1
3795 ; CHECK-NEXT: undef %2.sub15:vreg_512_align2 = V_MOV_B32_e32 215, implicit $exec
3796 ; CHECK-NEXT: S_NOP 0, implicit %2.sub15
3797 undef %0.sub0:vreg_512_align2 = V_MOV_B32_e32 00, implicit $exec
3798 S_NOP 0, implicit %0.sub0
3800 undef %1.sub1:vreg_512_align2 = V_MOV_B32_e32 11, implicit $exec
3801 S_NOP 0, implicit %1.sub1
3803 undef %2.sub15:vreg_512_align2 = V_MOV_B32_e32 215, implicit $exec
3804 S_NOP 0, implicit %2.sub15
3808 name: test_vreg_512_align2_w64
3809 tracksRegLiveness: true
3812 ; CHECK-LABEL: name: test_vreg_512_align2_w64
3813 ; CHECK: undef %3.sub0:vreg_64_align2 = V_MOV_B32_e32 0, implicit $exec
3814 ; CHECK-NEXT: %3.sub1:vreg_64_align2 = V_MOV_B32_e32 1, implicit $exec
3815 ; CHECK-NEXT: S_NOP 0, implicit %3
3816 ; CHECK-NEXT: undef %4.sub0:vreg_64_align2 = V_MOV_B32_e32 114, implicit $exec
3817 ; CHECK-NEXT: %4.sub1:vreg_64_align2 = V_MOV_B32_e32 115, implicit $exec
3818 ; CHECK-NEXT: S_NOP 0, implicit %4
3819 ; CHECK-NEXT: undef %5.sub0:vreg_64_align2 = V_MOV_B32_e32 22, implicit $exec
3820 ; CHECK-NEXT: %5.sub1:vreg_64_align2 = V_MOV_B32_e32 23, implicit $exec
3821 ; CHECK-NEXT: S_NOP 0, implicit %5
3822 undef %0.sub0:vreg_512_align2 = V_MOV_B32_e32 00, implicit $exec
3823 %0.sub1:vreg_512_align2 = V_MOV_B32_e32 01, implicit $exec
3824 S_NOP 0, implicit %0.sub0_sub1
3826 undef %1.sub14:vreg_512_align2 = V_MOV_B32_e32 114, implicit $exec
3827 %1.sub15:vreg_512_align2 = V_MOV_B32_e32 115, implicit $exec
3828 S_NOP 0, implicit %1.sub14_sub15
3830 undef %2.sub2:vreg_512_align2 = V_MOV_B32_e32 22, implicit $exec
3831 %2.sub3:vreg_512_align2 = V_MOV_B32_e32 23, implicit $exec
3832 S_NOP 0, implicit %2.sub2_sub3
3835 # Skip test_vreg_512_align2_w96: the 96-bit subreg isn't fully supported for the regclass vreg_512_align2
3837 name: test_vreg_512_align2_w128
3838 tracksRegLiveness: true
3841 ; CHECK-LABEL: name: test_vreg_512_align2_w128
3842 ; CHECK: undef %3.sub0:vreg_128_align2 = V_MOV_B32_e32 0, implicit $exec
3843 ; CHECK-NEXT: %3.sub1:vreg_128_align2 = V_MOV_B32_e32 1, implicit $exec
3844 ; CHECK-NEXT: %3.sub2:vreg_128_align2 = V_MOV_B32_e32 2, implicit $exec
3845 ; CHECK-NEXT: %3.sub3:vreg_128_align2 = V_MOV_B32_e32 3, implicit $exec
3846 ; CHECK-NEXT: S_NOP 0, implicit %3
3847 ; CHECK-NEXT: undef %4.sub0:vreg_128_align2 = V_MOV_B32_e32 112, implicit $exec
3848 ; CHECK-NEXT: %4.sub1:vreg_128_align2 = V_MOV_B32_e32 113, implicit $exec
3849 ; CHECK-NEXT: %4.sub2:vreg_128_align2 = V_MOV_B32_e32 114, implicit $exec
3850 ; CHECK-NEXT: %4.sub3:vreg_128_align2 = V_MOV_B32_e32 115, implicit $exec
3851 ; CHECK-NEXT: S_NOP 0, implicit %4
3852 ; CHECK-NEXT: undef %5.sub0:vreg_128_align2 = V_MOV_B32_e32 22, implicit $exec
3853 ; CHECK-NEXT: %5.sub1:vreg_128_align2 = V_MOV_B32_e32 23, implicit $exec
3854 ; CHECK-NEXT: %5.sub2:vreg_128_align2 = V_MOV_B32_e32 24, implicit $exec
3855 ; CHECK-NEXT: %5.sub3:vreg_128_align2 = V_MOV_B32_e32 25, implicit $exec
3856 ; CHECK-NEXT: S_NOP 0, implicit %5
3857 undef %0.sub0:vreg_512_align2 = V_MOV_B32_e32 00, implicit $exec
3858 %0.sub1:vreg_512_align2 = V_MOV_B32_e32 01, implicit $exec
3859 %0.sub2:vreg_512_align2 = V_MOV_B32_e32 02, implicit $exec
3860 %0.sub3:vreg_512_align2 = V_MOV_B32_e32 03, implicit $exec
3861 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3
3863 undef %1.sub12:vreg_512_align2 = V_MOV_B32_e32 112, implicit $exec
3864 %1.sub13:vreg_512_align2 = V_MOV_B32_e32 113, implicit $exec
3865 %1.sub14:vreg_512_align2 = V_MOV_B32_e32 114, implicit $exec
3866 %1.sub15:vreg_512_align2 = V_MOV_B32_e32 115, implicit $exec
3867 S_NOP 0, implicit %1.sub12_sub13_sub14_sub15
3869 undef %2.sub2:vreg_512_align2 = V_MOV_B32_e32 22, implicit $exec
3870 %2.sub3:vreg_512_align2 = V_MOV_B32_e32 23, implicit $exec
3871 %2.sub4:vreg_512_align2 = V_MOV_B32_e32 24, implicit $exec
3872 %2.sub5:vreg_512_align2 = V_MOV_B32_e32 25, implicit $exec
3873 S_NOP 0, implicit %2.sub2_sub3_sub4_sub5
3876 # Skip test_vreg_512_align2_w160: the 160-bit subreg isn't fully supported for the regclass vreg_512_align2
3878 name: test_vreg_512_align2_w192
3879 tracksRegLiveness: true
3882 ; CHECK-LABEL: name: test_vreg_512_align2_w192
3883 ; CHECK: undef %3.sub0:vreg_192_align2 = V_MOV_B32_e32 0, implicit $exec
3884 ; CHECK-NEXT: %3.sub1:vreg_192_align2 = V_MOV_B32_e32 1, implicit $exec
3885 ; CHECK-NEXT: %3.sub2:vreg_192_align2 = V_MOV_B32_e32 2, implicit $exec
3886 ; CHECK-NEXT: %3.sub3:vreg_192_align2 = V_MOV_B32_e32 3, implicit $exec
3887 ; CHECK-NEXT: %3.sub4:vreg_192_align2 = V_MOV_B32_e32 4, implicit $exec
3888 ; CHECK-NEXT: %3.sub5:vreg_192_align2 = V_MOV_B32_e32 5, implicit $exec
3889 ; CHECK-NEXT: S_NOP 0, implicit %3
3890 ; CHECK-NEXT: undef %4.sub0:vreg_192_align2 = V_MOV_B32_e32 110, implicit $exec
3891 ; CHECK-NEXT: %4.sub1:vreg_192_align2 = V_MOV_B32_e32 111, implicit $exec
3892 ; CHECK-NEXT: %4.sub2:vreg_192_align2 = V_MOV_B32_e32 112, implicit $exec
3893 ; CHECK-NEXT: %4.sub3:vreg_192_align2 = V_MOV_B32_e32 113, implicit $exec
3894 ; CHECK-NEXT: %4.sub4:vreg_192_align2 = V_MOV_B32_e32 114, implicit $exec
3895 ; CHECK-NEXT: %4.sub5:vreg_192_align2 = V_MOV_B32_e32 115, implicit $exec
3896 ; CHECK-NEXT: S_NOP 0, implicit %4
3897 ; CHECK-NEXT: undef %5.sub0:vreg_192_align2 = V_MOV_B32_e32 22, implicit $exec
3898 ; CHECK-NEXT: %5.sub1:vreg_192_align2 = V_MOV_B32_e32 23, implicit $exec
3899 ; CHECK-NEXT: %5.sub2:vreg_192_align2 = V_MOV_B32_e32 24, implicit $exec
3900 ; CHECK-NEXT: %5.sub3:vreg_192_align2 = V_MOV_B32_e32 25, implicit $exec
3901 ; CHECK-NEXT: %5.sub4:vreg_192_align2 = V_MOV_B32_e32 26, implicit $exec
3902 ; CHECK-NEXT: %5.sub5:vreg_192_align2 = V_MOV_B32_e32 27, implicit $exec
3903 ; CHECK-NEXT: S_NOP 0, implicit %5
3904 undef %0.sub0:vreg_512_align2 = V_MOV_B32_e32 00, implicit $exec
3905 %0.sub1:vreg_512_align2 = V_MOV_B32_e32 01, implicit $exec
3906 %0.sub2:vreg_512_align2 = V_MOV_B32_e32 02, implicit $exec
3907 %0.sub3:vreg_512_align2 = V_MOV_B32_e32 03, implicit $exec
3908 %0.sub4:vreg_512_align2 = V_MOV_B32_e32 04, implicit $exec
3909 %0.sub5:vreg_512_align2 = V_MOV_B32_e32 05, implicit $exec
3910 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5
3912 undef %1.sub10:vreg_512_align2 = V_MOV_B32_e32 110, implicit $exec
3913 %1.sub11:vreg_512_align2 = V_MOV_B32_e32 111, implicit $exec
3914 %1.sub12:vreg_512_align2 = V_MOV_B32_e32 112, implicit $exec
3915 %1.sub13:vreg_512_align2 = V_MOV_B32_e32 113, implicit $exec
3916 %1.sub14:vreg_512_align2 = V_MOV_B32_e32 114, implicit $exec
3917 %1.sub15:vreg_512_align2 = V_MOV_B32_e32 115, implicit $exec
3918 S_NOP 0, implicit %1.sub10_sub11_sub12_sub13_sub14_sub15
3920 undef %2.sub2:vreg_512_align2 = V_MOV_B32_e32 22, implicit $exec
3921 %2.sub3:vreg_512_align2 = V_MOV_B32_e32 23, implicit $exec
3922 %2.sub4:vreg_512_align2 = V_MOV_B32_e32 24, implicit $exec
3923 %2.sub5:vreg_512_align2 = V_MOV_B32_e32 25, implicit $exec
3924 %2.sub6:vreg_512_align2 = V_MOV_B32_e32 26, implicit $exec
3925 %2.sub7:vreg_512_align2 = V_MOV_B32_e32 27, implicit $exec
3926 S_NOP 0, implicit %2.sub2_sub3_sub4_sub5_sub6_sub7
3930 name: test_vreg_512_align2_w256
3931 tracksRegLiveness: true
3934 ; CHECK-LABEL: name: test_vreg_512_align2_w256
3935 ; CHECK: undef %3.sub0:vreg_256_align2 = V_MOV_B32_e32 0, implicit $exec
3936 ; CHECK-NEXT: %3.sub1:vreg_256_align2 = V_MOV_B32_e32 1, implicit $exec
3937 ; CHECK-NEXT: %3.sub2:vreg_256_align2 = V_MOV_B32_e32 2, implicit $exec
3938 ; CHECK-NEXT: %3.sub3:vreg_256_align2 = V_MOV_B32_e32 3, implicit $exec
3939 ; CHECK-NEXT: %3.sub4:vreg_256_align2 = V_MOV_B32_e32 4, implicit $exec
3940 ; CHECK-NEXT: %3.sub5:vreg_256_align2 = V_MOV_B32_e32 5, implicit $exec
3941 ; CHECK-NEXT: %3.sub6:vreg_256_align2 = V_MOV_B32_e32 6, implicit $exec
3942 ; CHECK-NEXT: %3.sub7:vreg_256_align2 = V_MOV_B32_e32 7, implicit $exec
3943 ; CHECK-NEXT: S_NOP 0, implicit %3
3944 ; CHECK-NEXT: undef %4.sub0:vreg_256_align2 = V_MOV_B32_e32 12, implicit $exec
3945 ; CHECK-NEXT: %4.sub1:vreg_256_align2 = V_MOV_B32_e32 13, implicit $exec
3946 ; CHECK-NEXT: %4.sub2:vreg_256_align2 = V_MOV_B32_e32 14, implicit $exec
3947 ; CHECK-NEXT: %4.sub3:vreg_256_align2 = V_MOV_B32_e32 15, implicit $exec
3948 ; CHECK-NEXT: %4.sub4:vreg_256_align2 = V_MOV_B32_e32 16, implicit $exec
3949 ; CHECK-NEXT: %4.sub5:vreg_256_align2 = V_MOV_B32_e32 17, implicit $exec
3950 ; CHECK-NEXT: %4.sub6:vreg_256_align2 = V_MOV_B32_e32 18, implicit $exec
3951 ; CHECK-NEXT: %4.sub7:vreg_256_align2 = V_MOV_B32_e32 19, implicit $exec
3952 ; CHECK-NEXT: S_NOP 0, implicit %4
3953 ; CHECK-NEXT: undef %5.sub0:vreg_256_align2 = V_MOV_B32_e32 28, implicit $exec
3954 ; CHECK-NEXT: %5.sub1:vreg_256_align2 = V_MOV_B32_e32 29, implicit $exec
3955 ; CHECK-NEXT: %5.sub2:vreg_256_align2 = V_MOV_B32_e32 210, implicit $exec
3956 ; CHECK-NEXT: %5.sub3:vreg_256_align2 = V_MOV_B32_e32 211, implicit $exec
3957 ; CHECK-NEXT: %5.sub4:vreg_256_align2 = V_MOV_B32_e32 212, implicit $exec
3958 ; CHECK-NEXT: %5.sub5:vreg_256_align2 = V_MOV_B32_e32 213, implicit $exec
3959 ; CHECK-NEXT: %5.sub6:vreg_256_align2 = V_MOV_B32_e32 214, implicit $exec
3960 ; CHECK-NEXT: %5.sub7:vreg_256_align2 = V_MOV_B32_e32 215, implicit $exec
3961 ; CHECK-NEXT: S_NOP 0, implicit %5
3962 undef %0.sub0:vreg_512_align2 = V_MOV_B32_e32 00, implicit $exec
3963 %0.sub1:vreg_512_align2 = V_MOV_B32_e32 01, implicit $exec
3964 %0.sub2:vreg_512_align2 = V_MOV_B32_e32 02, implicit $exec
3965 %0.sub3:vreg_512_align2 = V_MOV_B32_e32 03, implicit $exec
3966 %0.sub4:vreg_512_align2 = V_MOV_B32_e32 04, implicit $exec
3967 %0.sub5:vreg_512_align2 = V_MOV_B32_e32 05, implicit $exec
3968 %0.sub6:vreg_512_align2 = V_MOV_B32_e32 06, implicit $exec
3969 %0.sub7:vreg_512_align2 = V_MOV_B32_e32 07, implicit $exec
3970 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7
3972 undef %1.sub2:vreg_512_align2 = V_MOV_B32_e32 12, implicit $exec
3973 %1.sub3:vreg_512_align2 = V_MOV_B32_e32 13, implicit $exec
3974 %1.sub4:vreg_512_align2 = V_MOV_B32_e32 14, implicit $exec
3975 %1.sub5:vreg_512_align2 = V_MOV_B32_e32 15, implicit $exec
3976 %1.sub6:vreg_512_align2 = V_MOV_B32_e32 16, implicit $exec
3977 %1.sub7:vreg_512_align2 = V_MOV_B32_e32 17, implicit $exec
3978 %1.sub8:vreg_512_align2 = V_MOV_B32_e32 18, implicit $exec
3979 %1.sub9:vreg_512_align2 = V_MOV_B32_e32 19, implicit $exec
3980 S_NOP 0, implicit %1.sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9
3982 undef %2.sub8:vreg_512_align2 = V_MOV_B32_e32 28, implicit $exec
3983 %2.sub9:vreg_512_align2 = V_MOV_B32_e32 29, implicit $exec
3984 %2.sub10:vreg_512_align2 = V_MOV_B32_e32 210, implicit $exec
3985 %2.sub11:vreg_512_align2 = V_MOV_B32_e32 211, implicit $exec
3986 %2.sub12:vreg_512_align2 = V_MOV_B32_e32 212, implicit $exec
3987 %2.sub13:vreg_512_align2 = V_MOV_B32_e32 213, implicit $exec
3988 %2.sub14:vreg_512_align2 = V_MOV_B32_e32 214, implicit $exec
3989 %2.sub15:vreg_512_align2 = V_MOV_B32_e32 215, implicit $exec
3990 S_NOP 0, implicit %2.sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15
3994 name: test_vreg_1024_align2_w32
3995 tracksRegLiveness: true
3998 ; CHECK-LABEL: name: test_vreg_1024_align2_w32
3999 ; CHECK: undef %0.sub0:vreg_1024_align2 = V_MOV_B32_e32 0, implicit $exec
4000 ; CHECK-NEXT: S_NOP 0, implicit %0.sub0
4001 ; CHECK-NEXT: undef %1.sub1:vreg_1024_align2 = V_MOV_B32_e32 11, implicit $exec
4002 ; CHECK-NEXT: S_NOP 0, implicit %1.sub1
4003 ; CHECK-NEXT: undef %2.sub31:vreg_1024_align2 = V_MOV_B32_e32 231, implicit $exec
4004 ; CHECK-NEXT: S_NOP 0, implicit %2.sub31
4005 undef %0.sub0:vreg_1024_align2 = V_MOV_B32_e32 00, implicit $exec
4006 S_NOP 0, implicit %0.sub0
4008 undef %1.sub1:vreg_1024_align2 = V_MOV_B32_e32 11, implicit $exec
4009 S_NOP 0, implicit %1.sub1
4011 undef %2.sub31:vreg_1024_align2 = V_MOV_B32_e32 231, implicit $exec
4012 S_NOP 0, implicit %2.sub31
4016 name: test_vreg_1024_align2_w64
4017 tracksRegLiveness: true
4020 ; CHECK-LABEL: name: test_vreg_1024_align2_w64
4021 ; CHECK: undef %3.sub0:vreg_64_align2 = V_MOV_B32_e32 0, implicit $exec
4022 ; CHECK-NEXT: %3.sub1:vreg_64_align2 = V_MOV_B32_e32 1, implicit $exec
4023 ; CHECK-NEXT: S_NOP 0, implicit %3
4024 ; CHECK-NEXT: undef %4.sub0:vreg_64_align2 = V_MOV_B32_e32 12, implicit $exec
4025 ; CHECK-NEXT: %4.sub1:vreg_64_align2 = V_MOV_B32_e32 13, implicit $exec
4026 ; CHECK-NEXT: S_NOP 0, implicit %4
4027 ; CHECK-NEXT: undef %5.sub0:vreg_64_align2 = V_MOV_B32_e32 230, implicit $exec
4028 ; CHECK-NEXT: %5.sub1:vreg_64_align2 = V_MOV_B32_e32 231, implicit $exec
4029 ; CHECK-NEXT: S_NOP 0, implicit %5
4030 undef %0.sub0:vreg_1024_align2 = V_MOV_B32_e32 00, implicit $exec
4031 %0.sub1:vreg_1024_align2 = V_MOV_B32_e32 01, implicit $exec
4032 S_NOP 0, implicit %0.sub0_sub1
4034 undef %1.sub2:vreg_1024_align2 = V_MOV_B32_e32 12, implicit $exec
4035 %1.sub3:vreg_1024_align2 = V_MOV_B32_e32 13, implicit $exec
4036 S_NOP 0, implicit %1.sub2_sub3
4038 undef %2.sub30:vreg_1024_align2 = V_MOV_B32_e32 230, implicit $exec
4039 %2.sub31:vreg_1024_align2 = V_MOV_B32_e32 231, implicit $exec
4040 S_NOP 0, implicit %2.sub30_sub31
4043 # Skip test_vreg_1024_align2_w96: the 96-bit subreg isn't fully supported for the regclass vreg_1024_align2
4045 name: test_vreg_1024_align2_w128
4046 tracksRegLiveness: true
4049 ; CHECK-LABEL: name: test_vreg_1024_align2_w128
4050 ; CHECK: undef %3.sub0:vreg_128_align2 = V_MOV_B32_e32 0, implicit $exec
4051 ; CHECK-NEXT: %3.sub1:vreg_128_align2 = V_MOV_B32_e32 1, implicit $exec
4052 ; CHECK-NEXT: %3.sub2:vreg_128_align2 = V_MOV_B32_e32 2, implicit $exec
4053 ; CHECK-NEXT: %3.sub3:vreg_128_align2 = V_MOV_B32_e32 3, implicit $exec
4054 ; CHECK-NEXT: S_NOP 0, implicit %3
4055 ; CHECK-NEXT: undef %4.sub0:vreg_128_align2 = V_MOV_B32_e32 12, implicit $exec
4056 ; CHECK-NEXT: %4.sub1:vreg_128_align2 = V_MOV_B32_e32 13, implicit $exec
4057 ; CHECK-NEXT: %4.sub2:vreg_128_align2 = V_MOV_B32_e32 14, implicit $exec
4058 ; CHECK-NEXT: %4.sub3:vreg_128_align2 = V_MOV_B32_e32 15, implicit $exec
4059 ; CHECK-NEXT: S_NOP 0, implicit %4
4060 ; CHECK-NEXT: undef %5.sub0:vreg_128_align2 = V_MOV_B32_e32 228, implicit $exec
4061 ; CHECK-NEXT: %5.sub1:vreg_128_align2 = V_MOV_B32_e32 229, implicit $exec
4062 ; CHECK-NEXT: %5.sub2:vreg_128_align2 = V_MOV_B32_e32 230, implicit $exec
4063 ; CHECK-NEXT: %5.sub3:vreg_128_align2 = V_MOV_B32_e32 231, implicit $exec
4064 ; CHECK-NEXT: S_NOP 0, implicit %5
4065 undef %0.sub0:vreg_1024_align2 = V_MOV_B32_e32 00, implicit $exec
4066 %0.sub1:vreg_1024_align2 = V_MOV_B32_e32 01, implicit $exec
4067 %0.sub2:vreg_1024_align2 = V_MOV_B32_e32 02, implicit $exec
4068 %0.sub3:vreg_1024_align2 = V_MOV_B32_e32 03, implicit $exec
4069 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3
4071 undef %1.sub2:vreg_1024_align2 = V_MOV_B32_e32 12, implicit $exec
4072 %1.sub3:vreg_1024_align2 = V_MOV_B32_e32 13, implicit $exec
4073 %1.sub4:vreg_1024_align2 = V_MOV_B32_e32 14, implicit $exec
4074 %1.sub5:vreg_1024_align2 = V_MOV_B32_e32 15, implicit $exec
4075 S_NOP 0, implicit %1.sub2_sub3_sub4_sub5
4077 undef %2.sub28:vreg_1024_align2 = V_MOV_B32_e32 228, implicit $exec
4078 %2.sub29:vreg_1024_align2 = V_MOV_B32_e32 229, implicit $exec
4079 %2.sub30:vreg_1024_align2 = V_MOV_B32_e32 230, implicit $exec
4080 %2.sub31:vreg_1024_align2 = V_MOV_B32_e32 231, implicit $exec
4081 S_NOP 0, implicit %2.sub28_sub29_sub30_sub31
4084 # Skip test_vreg_1024_align2_w160: the 160-bit subreg isn't fully supported for the regclass vreg_1024_align2
4086 name: test_vreg_1024_align2_w192
4087 tracksRegLiveness: true
4090 ; CHECK-LABEL: name: test_vreg_1024_align2_w192
4091 ; CHECK: undef %3.sub0:vreg_192_align2 = V_MOV_B32_e32 0, implicit $exec
4092 ; CHECK-NEXT: %3.sub1:vreg_192_align2 = V_MOV_B32_e32 1, implicit $exec
4093 ; CHECK-NEXT: %3.sub2:vreg_192_align2 = V_MOV_B32_e32 2, implicit $exec
4094 ; CHECK-NEXT: %3.sub3:vreg_192_align2 = V_MOV_B32_e32 3, implicit $exec
4095 ; CHECK-NEXT: %3.sub4:vreg_192_align2 = V_MOV_B32_e32 4, implicit $exec
4096 ; CHECK-NEXT: %3.sub5:vreg_192_align2 = V_MOV_B32_e32 5, implicit $exec
4097 ; CHECK-NEXT: S_NOP 0, implicit %3
4098 ; CHECK-NEXT: undef %4.sub0:vreg_192_align2 = V_MOV_B32_e32 12, implicit $exec
4099 ; CHECK-NEXT: %4.sub1:vreg_192_align2 = V_MOV_B32_e32 13, implicit $exec
4100 ; CHECK-NEXT: %4.sub2:vreg_192_align2 = V_MOV_B32_e32 14, implicit $exec
4101 ; CHECK-NEXT: %4.sub3:vreg_192_align2 = V_MOV_B32_e32 15, implicit $exec
4102 ; CHECK-NEXT: %4.sub4:vreg_192_align2 = V_MOV_B32_e32 16, implicit $exec
4103 ; CHECK-NEXT: %4.sub5:vreg_192_align2 = V_MOV_B32_e32 17, implicit $exec
4104 ; CHECK-NEXT: S_NOP 0, implicit %4
4105 ; CHECK-NEXT: undef %5.sub0:vreg_192_align2 = V_MOV_B32_e32 226, implicit $exec
4106 ; CHECK-NEXT: %5.sub1:vreg_192_align2 = V_MOV_B32_e32 227, implicit $exec
4107 ; CHECK-NEXT: %5.sub2:vreg_192_align2 = V_MOV_B32_e32 228, implicit $exec
4108 ; CHECK-NEXT: %5.sub3:vreg_192_align2 = V_MOV_B32_e32 229, implicit $exec
4109 ; CHECK-NEXT: %5.sub4:vreg_192_align2 = V_MOV_B32_e32 230, implicit $exec
4110 ; CHECK-NEXT: %5.sub5:vreg_192_align2 = V_MOV_B32_e32 231, implicit $exec
4111 ; CHECK-NEXT: S_NOP 0, implicit %5
4112 undef %0.sub0:vreg_1024_align2 = V_MOV_B32_e32 00, implicit $exec
4113 %0.sub1:vreg_1024_align2 = V_MOV_B32_e32 01, implicit $exec
4114 %0.sub2:vreg_1024_align2 = V_MOV_B32_e32 02, implicit $exec
4115 %0.sub3:vreg_1024_align2 = V_MOV_B32_e32 03, implicit $exec
4116 %0.sub4:vreg_1024_align2 = V_MOV_B32_e32 04, implicit $exec
4117 %0.sub5:vreg_1024_align2 = V_MOV_B32_e32 05, implicit $exec
4118 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5
4120 undef %1.sub2:vreg_1024_align2 = V_MOV_B32_e32 12, implicit $exec
4121 %1.sub3:vreg_1024_align2 = V_MOV_B32_e32 13, implicit $exec
4122 %1.sub4:vreg_1024_align2 = V_MOV_B32_e32 14, implicit $exec
4123 %1.sub5:vreg_1024_align2 = V_MOV_B32_e32 15, implicit $exec
4124 %1.sub6:vreg_1024_align2 = V_MOV_B32_e32 16, implicit $exec
4125 %1.sub7:vreg_1024_align2 = V_MOV_B32_e32 17, implicit $exec
4126 S_NOP 0, implicit %1.sub2_sub3_sub4_sub5_sub6_sub7
4128 undef %2.sub26:vreg_1024_align2 = V_MOV_B32_e32 226, implicit $exec
4129 %2.sub27:vreg_1024_align2 = V_MOV_B32_e32 227, implicit $exec
4130 %2.sub28:vreg_1024_align2 = V_MOV_B32_e32 228, implicit $exec
4131 %2.sub29:vreg_1024_align2 = V_MOV_B32_e32 229, implicit $exec
4132 %2.sub30:vreg_1024_align2 = V_MOV_B32_e32 230, implicit $exec
4133 %2.sub31:vreg_1024_align2 = V_MOV_B32_e32 231, implicit $exec
4134 S_NOP 0, implicit %2.sub26_sub27_sub28_sub29_sub30_sub31
4138 name: test_vreg_1024_align2_w256
4139 tracksRegLiveness: true
4142 ; CHECK-LABEL: name: test_vreg_1024_align2_w256
4143 ; CHECK: undef %3.sub0:vreg_256_align2 = V_MOV_B32_e32 0, implicit $exec
4144 ; CHECK-NEXT: %3.sub1:vreg_256_align2 = V_MOV_B32_e32 1, implicit $exec
4145 ; CHECK-NEXT: %3.sub2:vreg_256_align2 = V_MOV_B32_e32 2, implicit $exec
4146 ; CHECK-NEXT: %3.sub3:vreg_256_align2 = V_MOV_B32_e32 3, implicit $exec
4147 ; CHECK-NEXT: %3.sub4:vreg_256_align2 = V_MOV_B32_e32 4, implicit $exec
4148 ; CHECK-NEXT: %3.sub5:vreg_256_align2 = V_MOV_B32_e32 5, implicit $exec
4149 ; CHECK-NEXT: %3.sub6:vreg_256_align2 = V_MOV_B32_e32 6, implicit $exec
4150 ; CHECK-NEXT: %3.sub7:vreg_256_align2 = V_MOV_B32_e32 7, implicit $exec
4151 ; CHECK-NEXT: S_NOP 0, implicit %3
4152 ; CHECK-NEXT: undef %4.sub0:vreg_256_align2 = V_MOV_B32_e32 12, implicit $exec
4153 ; CHECK-NEXT: %4.sub1:vreg_256_align2 = V_MOV_B32_e32 13, implicit $exec
4154 ; CHECK-NEXT: %4.sub2:vreg_256_align2 = V_MOV_B32_e32 14, implicit $exec
4155 ; CHECK-NEXT: %4.sub3:vreg_256_align2 = V_MOV_B32_e32 15, implicit $exec
4156 ; CHECK-NEXT: %4.sub4:vreg_256_align2 = V_MOV_B32_e32 16, implicit $exec
4157 ; CHECK-NEXT: %4.sub5:vreg_256_align2 = V_MOV_B32_e32 17, implicit $exec
4158 ; CHECK-NEXT: %4.sub6:vreg_256_align2 = V_MOV_B32_e32 18, implicit $exec
4159 ; CHECK-NEXT: %4.sub7:vreg_256_align2 = V_MOV_B32_e32 19, implicit $exec
4160 ; CHECK-NEXT: S_NOP 0, implicit %4
4161 ; CHECK-NEXT: undef %5.sub0:vreg_256_align2 = V_MOV_B32_e32 224, implicit $exec
4162 ; CHECK-NEXT: %5.sub1:vreg_256_align2 = V_MOV_B32_e32 225, implicit $exec
4163 ; CHECK-NEXT: %5.sub2:vreg_256_align2 = V_MOV_B32_e32 226, implicit $exec
4164 ; CHECK-NEXT: %5.sub3:vreg_256_align2 = V_MOV_B32_e32 227, implicit $exec
4165 ; CHECK-NEXT: %5.sub4:vreg_256_align2 = V_MOV_B32_e32 228, implicit $exec
4166 ; CHECK-NEXT: %5.sub5:vreg_256_align2 = V_MOV_B32_e32 229, implicit $exec
4167 ; CHECK-NEXT: %5.sub6:vreg_256_align2 = V_MOV_B32_e32 230, implicit $exec
4168 ; CHECK-NEXT: %5.sub7:vreg_256_align2 = V_MOV_B32_e32 231, implicit $exec
4169 ; CHECK-NEXT: S_NOP 0, implicit %5
4170 undef %0.sub0:vreg_1024_align2 = V_MOV_B32_e32 00, implicit $exec
4171 %0.sub1:vreg_1024_align2 = V_MOV_B32_e32 01, implicit $exec
4172 %0.sub2:vreg_1024_align2 = V_MOV_B32_e32 02, implicit $exec
4173 %0.sub3:vreg_1024_align2 = V_MOV_B32_e32 03, implicit $exec
4174 %0.sub4:vreg_1024_align2 = V_MOV_B32_e32 04, implicit $exec
4175 %0.sub5:vreg_1024_align2 = V_MOV_B32_e32 05, implicit $exec
4176 %0.sub6:vreg_1024_align2 = V_MOV_B32_e32 06, implicit $exec
4177 %0.sub7:vreg_1024_align2 = V_MOV_B32_e32 07, implicit $exec
4178 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7
4180 undef %1.sub2:vreg_1024_align2 = V_MOV_B32_e32 12, implicit $exec
4181 %1.sub3:vreg_1024_align2 = V_MOV_B32_e32 13, implicit $exec
4182 %1.sub4:vreg_1024_align2 = V_MOV_B32_e32 14, implicit $exec
4183 %1.sub5:vreg_1024_align2 = V_MOV_B32_e32 15, implicit $exec
4184 %1.sub6:vreg_1024_align2 = V_MOV_B32_e32 16, implicit $exec
4185 %1.sub7:vreg_1024_align2 = V_MOV_B32_e32 17, implicit $exec
4186 %1.sub8:vreg_1024_align2 = V_MOV_B32_e32 18, implicit $exec
4187 %1.sub9:vreg_1024_align2 = V_MOV_B32_e32 19, implicit $exec
4188 S_NOP 0, implicit %1.sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9
4190 undef %2.sub24:vreg_1024_align2 = V_MOV_B32_e32 224, implicit $exec
4191 %2.sub25:vreg_1024_align2 = V_MOV_B32_e32 225, implicit $exec
4192 %2.sub26:vreg_1024_align2 = V_MOV_B32_e32 226, implicit $exec
4193 %2.sub27:vreg_1024_align2 = V_MOV_B32_e32 227, implicit $exec
4194 %2.sub28:vreg_1024_align2 = V_MOV_B32_e32 228, implicit $exec
4195 %2.sub29:vreg_1024_align2 = V_MOV_B32_e32 229, implicit $exec
4196 %2.sub30:vreg_1024_align2 = V_MOV_B32_e32 230, implicit $exec
4197 %2.sub31:vreg_1024_align2 = V_MOV_B32_e32 231, implicit $exec
4198 S_NOP 0, implicit %2.sub24_sub25_sub26_sub27_sub28_sub29_sub30_sub31
4202 name: test_vreg_1024_align2_w512
4203 tracksRegLiveness: true
4206 ; CHECK-LABEL: name: test_vreg_1024_align2_w512
4207 ; CHECK: undef %3.sub0:vreg_512_align2 = V_MOV_B32_e32 0, implicit $exec
4208 ; CHECK-NEXT: %3.sub1:vreg_512_align2 = V_MOV_B32_e32 1, implicit $exec
4209 ; CHECK-NEXT: %3.sub2:vreg_512_align2 = V_MOV_B32_e32 2, implicit $exec
4210 ; CHECK-NEXT: %3.sub3:vreg_512_align2 = V_MOV_B32_e32 3, implicit $exec
4211 ; CHECK-NEXT: %3.sub4:vreg_512_align2 = V_MOV_B32_e32 4, implicit $exec
4212 ; CHECK-NEXT: %3.sub5:vreg_512_align2 = V_MOV_B32_e32 5, implicit $exec
4213 ; CHECK-NEXT: %3.sub6:vreg_512_align2 = V_MOV_B32_e32 6, implicit $exec
4214 ; CHECK-NEXT: %3.sub7:vreg_512_align2 = V_MOV_B32_e32 7, implicit $exec
4215 ; CHECK-NEXT: %3.sub8:vreg_512_align2 = V_MOV_B32_e32 8, implicit $exec
4216 ; CHECK-NEXT: %3.sub9:vreg_512_align2 = V_MOV_B32_e32 9, implicit $exec
4217 ; CHECK-NEXT: %3.sub10:vreg_512_align2 = V_MOV_B32_e32 10, implicit $exec
4218 ; CHECK-NEXT: %3.sub11:vreg_512_align2 = V_MOV_B32_e32 11, implicit $exec
4219 ; CHECK-NEXT: %3.sub12:vreg_512_align2 = V_MOV_B32_e32 12, implicit $exec
4220 ; CHECK-NEXT: %3.sub13:vreg_512_align2 = V_MOV_B32_e32 13, implicit $exec
4221 ; CHECK-NEXT: %3.sub14:vreg_512_align2 = V_MOV_B32_e32 14, implicit $exec
4222 ; CHECK-NEXT: %3.sub15:vreg_512_align2 = V_MOV_B32_e32 15, implicit $exec
4223 ; CHECK-NEXT: S_NOP 0, implicit %3
4224 ; CHECK-NEXT: undef %4.sub0:vreg_512_align2 = V_MOV_B32_e32 116, implicit $exec
4225 ; CHECK-NEXT: %4.sub1:vreg_512_align2 = V_MOV_B32_e32 117, implicit $exec
4226 ; CHECK-NEXT: %4.sub2:vreg_512_align2 = V_MOV_B32_e32 118, implicit $exec
4227 ; CHECK-NEXT: %4.sub3:vreg_512_align2 = V_MOV_B32_e32 119, implicit $exec
4228 ; CHECK-NEXT: %4.sub4:vreg_512_align2 = V_MOV_B32_e32 120, implicit $exec
4229 ; CHECK-NEXT: %4.sub5:vreg_512_align2 = V_MOV_B32_e32 121, implicit $exec
4230 ; CHECK-NEXT: %4.sub6:vreg_512_align2 = V_MOV_B32_e32 122, implicit $exec
4231 ; CHECK-NEXT: %4.sub7:vreg_512_align2 = V_MOV_B32_e32 123, implicit $exec
4232 ; CHECK-NEXT: %4.sub8:vreg_512_align2 = V_MOV_B32_e32 124, implicit $exec
4233 ; CHECK-NEXT: %4.sub9:vreg_512_align2 = V_MOV_B32_e32 125, implicit $exec
4234 ; CHECK-NEXT: %4.sub10:vreg_512_align2 = V_MOV_B32_e32 126, implicit $exec
4235 ; CHECK-NEXT: %4.sub11:vreg_512_align2 = V_MOV_B32_e32 127, implicit $exec
4236 ; CHECK-NEXT: %4.sub12:vreg_512_align2 = V_MOV_B32_e32 128, implicit $exec
4237 ; CHECK-NEXT: %4.sub13:vreg_512_align2 = V_MOV_B32_e32 129, implicit $exec
4238 ; CHECK-NEXT: %4.sub14:vreg_512_align2 = V_MOV_B32_e32 130, implicit $exec
4239 ; CHECK-NEXT: %4.sub15:vreg_512_align2 = V_MOV_B32_e32 131, implicit $exec
4240 ; CHECK-NEXT: S_NOP 0, implicit %4
4241 ; CHECK-NEXT: undef %5.sub0:vreg_512_align2 = V_MOV_B32_e32 22, implicit $exec
4242 ; CHECK-NEXT: %5.sub1:vreg_512_align2 = V_MOV_B32_e32 23, implicit $exec
4243 ; CHECK-NEXT: %5.sub2:vreg_512_align2 = V_MOV_B32_e32 24, implicit $exec
4244 ; CHECK-NEXT: %5.sub3:vreg_512_align2 = V_MOV_B32_e32 25, implicit $exec
4245 ; CHECK-NEXT: %5.sub4:vreg_512_align2 = V_MOV_B32_e32 26, implicit $exec
4246 ; CHECK-NEXT: %5.sub5:vreg_512_align2 = V_MOV_B32_e32 27, implicit $exec
4247 ; CHECK-NEXT: %5.sub6:vreg_512_align2 = V_MOV_B32_e32 28, implicit $exec
4248 ; CHECK-NEXT: %5.sub7:vreg_512_align2 = V_MOV_B32_e32 29, implicit $exec
4249 ; CHECK-NEXT: %5.sub8:vreg_512_align2 = V_MOV_B32_e32 210, implicit $exec
4250 ; CHECK-NEXT: %5.sub9:vreg_512_align2 = V_MOV_B32_e32 211, implicit $exec
4251 ; CHECK-NEXT: %5.sub10:vreg_512_align2 = V_MOV_B32_e32 212, implicit $exec
4252 ; CHECK-NEXT: %5.sub11:vreg_512_align2 = V_MOV_B32_e32 213, implicit $exec
4253 ; CHECK-NEXT: %5.sub12:vreg_512_align2 = V_MOV_B32_e32 214, implicit $exec
4254 ; CHECK-NEXT: %5.sub13:vreg_512_align2 = V_MOV_B32_e32 215, implicit $exec
4255 ; CHECK-NEXT: %5.sub14:vreg_512_align2 = V_MOV_B32_e32 216, implicit $exec
4256 ; CHECK-NEXT: %5.sub15:vreg_512_align2 = V_MOV_B32_e32 217, implicit $exec
4257 ; CHECK-NEXT: S_NOP 0, implicit %5
4258 undef %0.sub0:vreg_1024_align2 = V_MOV_B32_e32 00, implicit $exec
4259 %0.sub1:vreg_1024_align2 = V_MOV_B32_e32 01, implicit $exec
4260 %0.sub2:vreg_1024_align2 = V_MOV_B32_e32 02, implicit $exec
4261 %0.sub3:vreg_1024_align2 = V_MOV_B32_e32 03, implicit $exec
4262 %0.sub4:vreg_1024_align2 = V_MOV_B32_e32 04, implicit $exec
4263 %0.sub5:vreg_1024_align2 = V_MOV_B32_e32 05, implicit $exec
4264 %0.sub6:vreg_1024_align2 = V_MOV_B32_e32 06, implicit $exec
4265 %0.sub7:vreg_1024_align2 = V_MOV_B32_e32 07, implicit $exec
4266 %0.sub8:vreg_1024_align2 = V_MOV_B32_e32 08, implicit $exec
4267 %0.sub9:vreg_1024_align2 = V_MOV_B32_e32 09, implicit $exec
4268 %0.sub10:vreg_1024_align2 = V_MOV_B32_e32 010, implicit $exec
4269 %0.sub11:vreg_1024_align2 = V_MOV_B32_e32 011, implicit $exec
4270 %0.sub12:vreg_1024_align2 = V_MOV_B32_e32 012, implicit $exec
4271 %0.sub13:vreg_1024_align2 = V_MOV_B32_e32 013, implicit $exec
4272 %0.sub14:vreg_1024_align2 = V_MOV_B32_e32 014, implicit $exec
4273 %0.sub15:vreg_1024_align2 = V_MOV_B32_e32 015, implicit $exec
4274 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15
4276 undef %1.sub16:vreg_1024_align2 = V_MOV_B32_e32 116, implicit $exec
4277 %1.sub17:vreg_1024_align2 = V_MOV_B32_e32 117, implicit $exec
4278 %1.sub18:vreg_1024_align2 = V_MOV_B32_e32 118, implicit $exec
4279 %1.sub19:vreg_1024_align2 = V_MOV_B32_e32 119, implicit $exec
4280 %1.sub20:vreg_1024_align2 = V_MOV_B32_e32 120, implicit $exec
4281 %1.sub21:vreg_1024_align2 = V_MOV_B32_e32 121, implicit $exec
4282 %1.sub22:vreg_1024_align2 = V_MOV_B32_e32 122, implicit $exec
4283 %1.sub23:vreg_1024_align2 = V_MOV_B32_e32 123, implicit $exec
4284 %1.sub24:vreg_1024_align2 = V_MOV_B32_e32 124, implicit $exec
4285 %1.sub25:vreg_1024_align2 = V_MOV_B32_e32 125, implicit $exec
4286 %1.sub26:vreg_1024_align2 = V_MOV_B32_e32 126, implicit $exec
4287 %1.sub27:vreg_1024_align2 = V_MOV_B32_e32 127, implicit $exec
4288 %1.sub28:vreg_1024_align2 = V_MOV_B32_e32 128, implicit $exec
4289 %1.sub29:vreg_1024_align2 = V_MOV_B32_e32 129, implicit $exec
4290 %1.sub30:vreg_1024_align2 = V_MOV_B32_e32 130, implicit $exec
4291 %1.sub31:vreg_1024_align2 = V_MOV_B32_e32 131, implicit $exec
4292 S_NOP 0, implicit %1.sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_sub28_sub29_sub30_sub31
4294 undef %2.sub2:vreg_1024_align2 = V_MOV_B32_e32 22, implicit $exec
4295 %2.sub3:vreg_1024_align2 = V_MOV_B32_e32 23, implicit $exec
4296 %2.sub4:vreg_1024_align2 = V_MOV_B32_e32 24, implicit $exec
4297 %2.sub5:vreg_1024_align2 = V_MOV_B32_e32 25, implicit $exec
4298 %2.sub6:vreg_1024_align2 = V_MOV_B32_e32 26, implicit $exec
4299 %2.sub7:vreg_1024_align2 = V_MOV_B32_e32 27, implicit $exec
4300 %2.sub8:vreg_1024_align2 = V_MOV_B32_e32 28, implicit $exec
4301 %2.sub9:vreg_1024_align2 = V_MOV_B32_e32 29, implicit $exec
4302 %2.sub10:vreg_1024_align2 = V_MOV_B32_e32 210, implicit $exec
4303 %2.sub11:vreg_1024_align2 = V_MOV_B32_e32 211, implicit $exec
4304 %2.sub12:vreg_1024_align2 = V_MOV_B32_e32 212, implicit $exec
4305 %2.sub13:vreg_1024_align2 = V_MOV_B32_e32 213, implicit $exec
4306 %2.sub14:vreg_1024_align2 = V_MOV_B32_e32 214, implicit $exec
4307 %2.sub15:vreg_1024_align2 = V_MOV_B32_e32 215, implicit $exec
4308 %2.sub16:vreg_1024_align2 = V_MOV_B32_e32 216, implicit $exec
4309 %2.sub17:vreg_1024_align2 = V_MOV_B32_e32 217, implicit $exec
4310 S_NOP 0, implicit %2.sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16_sub17
4314 name: test_subregs_composition_sgpr_1024
4315 tracksRegLiveness: true
4318 ; CHECK-LABEL: name: test_subregs_composition_sgpr_1024
4319 ; CHECK: undef %2.sub0:sgpr_288 = S_MOV_B32 34
4320 ; CHECK-NEXT: %2.sub4:sgpr_288 = S_MOV_B32 38
4321 ; CHECK-NEXT: S_NOP 0, implicit %2.sub0_sub1_sub2_sub3_sub4
4322 ; CHECK-NEXT: S_NOP 0, implicit %2.sub4_sub5_sub6_sub7_sub8
4323 ; CHECK-NEXT: undef %3.sub0:sgpr_320 = S_MOV_B32 44
4324 ; CHECK-NEXT: %3.sub4:sgpr_320 = S_MOV_B32 48
4325 ; CHECK-NEXT: S_NOP 0, implicit %3.sub0_sub1_sub2_sub3_sub4_sub5
4326 ; CHECK-NEXT: S_NOP 0, implicit %3.sub4_sub5_sub6_sub7_sub8_sub9
4327 undef %3.sub4:sgpr_1024 = S_MOV_B32 34
4328 %3.sub8:sgpr_1024 = S_MOV_B32 38
4329 S_NOP 0, implicit %3.sub4_sub5_sub6_sub7_sub8
4330 S_NOP 0, implicit %3.sub8_sub9_sub10_sub11_sub12
4332 undef %4.sub4:sgpr_1024 = S_MOV_B32 44
4333 %4.sub8:sgpr_1024 = S_MOV_B32 48
4334 S_NOP 0, implicit %4.sub4_sub5_sub6_sub7_sub8_sub9
4335 S_NOP 0, implicit %4.sub8_sub9_sub10_sub11_sub12_sub13
4339 name: test_sgpr_64_w32
4340 tracksRegLiveness: true
4343 ; CHECK-LABEL: name: test_sgpr_64_w32
4344 ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
4345 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]
4346 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 11
4347 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]
4348 undef %0.sub0:sgpr_64 = S_MOV_B32 00
4349 S_NOP 0, implicit %0.sub0
4351 undef %1.sub1:sgpr_64 = S_MOV_B32 11
4352 S_NOP 0, implicit %1.sub1
4356 name: test_sgpr_96_w32
4357 tracksRegLiveness: true
4360 ; CHECK-LABEL: name: test_sgpr_96_w32
4361 ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
4362 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]
4363 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 11
4364 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]
4365 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 22
4366 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]
4367 undef %0.sub0:sgpr_96 = S_MOV_B32 00
4368 S_NOP 0, implicit %0.sub0
4370 undef %1.sub1:sgpr_96 = S_MOV_B32 11
4371 S_NOP 0, implicit %1.sub1
4373 undef %2.sub2:sgpr_96 = S_MOV_B32 22
4374 S_NOP 0, implicit %2.sub2
4377 # Skip test_sgpr_96_w64: the 64-bit subreg isn't fully supported for the regclass sgpr_96
4379 name: test_sgpr_128_w32
4380 tracksRegLiveness: true
4383 ; CHECK-LABEL: name: test_sgpr_128_w32
4384 ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
4385 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]
4386 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 11
4387 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]
4388 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 23
4389 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]
4390 undef %0.sub0:sgpr_128 = S_MOV_B32 00
4391 S_NOP 0, implicit %0.sub0
4393 undef %1.sub1:sgpr_128 = S_MOV_B32 11
4394 S_NOP 0, implicit %1.sub1
4396 undef %2.sub3:sgpr_128 = S_MOV_B32 23
4397 S_NOP 0, implicit %2.sub3
4401 name: test_sgpr_128_w64
4402 tracksRegLiveness: true
4405 ; CHECK-LABEL: name: test_sgpr_128_w64
4406 ; CHECK: undef %2.sub0:sgpr_64 = S_MOV_B32 0
4407 ; CHECK-NEXT: %2.sub1:sgpr_64 = S_MOV_B32 1
4408 ; CHECK-NEXT: S_NOP 0, implicit %2
4409 ; CHECK-NEXT: undef %3.sub0:sgpr_64 = S_MOV_B32 12
4410 ; CHECK-NEXT: %3.sub1:sgpr_64 = S_MOV_B32 13
4411 ; CHECK-NEXT: S_NOP 0, implicit %3
4412 undef %0.sub0:sgpr_128 = S_MOV_B32 00
4413 %0.sub1:sgpr_128 = S_MOV_B32 01
4414 S_NOP 0, implicit %0.sub0_sub1
4416 undef %1.sub2:sgpr_128 = S_MOV_B32 12
4417 %1.sub3:sgpr_128 = S_MOV_B32 13
4418 S_NOP 0, implicit %1.sub2_sub3
4421 # Skip test_sgpr_128_w96: the 96-bit subreg isn't fully supported for the regclass sgpr_128
4423 name: test_sgpr_160_w32
4424 tracksRegLiveness: true
4427 ; CHECK-LABEL: name: test_sgpr_160_w32
4428 ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
4429 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]
4430 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 11
4431 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]
4432 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 24
4433 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]
4434 undef %0.sub0:sgpr_160 = S_MOV_B32 00
4435 S_NOP 0, implicit %0.sub0
4437 undef %1.sub1:sgpr_160 = S_MOV_B32 11
4438 S_NOP 0, implicit %1.sub1
4440 undef %2.sub4:sgpr_160 = S_MOV_B32 24
4441 S_NOP 0, implicit %2.sub4
4444 # Skip test_sgpr_160_w64: the 64-bit subreg isn't fully supported for the regclass sgpr_160
4445 # Skip test_sgpr_160_w96: the 96-bit subreg isn't fully supported for the regclass sgpr_160
4446 # Skip test_sgpr_160_w128: the 128-bit subreg isn't fully supported for the regclass sgpr_160
4448 name: test_sgpr_192_w32
4449 tracksRegLiveness: true
4452 ; CHECK-LABEL: name: test_sgpr_192_w32
4453 ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
4454 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]
4455 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 11
4456 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]
4457 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 25
4458 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]
4459 undef %0.sub0:sgpr_192 = S_MOV_B32 00
4460 S_NOP 0, implicit %0.sub0
4462 undef %1.sub1:sgpr_192 = S_MOV_B32 11
4463 S_NOP 0, implicit %1.sub1
4465 undef %2.sub5:sgpr_192 = S_MOV_B32 25
4466 S_NOP 0, implicit %2.sub5
4470 name: test_sgpr_192_w64
4471 tracksRegLiveness: true
4474 ; CHECK-LABEL: name: test_sgpr_192_w64
4475 ; CHECK: undef %3.sub0:sgpr_64 = S_MOV_B32 0
4476 ; CHECK-NEXT: %3.sub1:sgpr_64 = S_MOV_B32 1
4477 ; CHECK-NEXT: S_NOP 0, implicit %3
4478 ; CHECK-NEXT: undef %4.sub0:sgpr_64 = S_MOV_B32 12
4479 ; CHECK-NEXT: %4.sub1:sgpr_64 = S_MOV_B32 13
4480 ; CHECK-NEXT: S_NOP 0, implicit %4
4481 ; CHECK-NEXT: undef %5.sub0:sgpr_64 = S_MOV_B32 24
4482 ; CHECK-NEXT: %5.sub1:sgpr_64 = S_MOV_B32 25
4483 ; CHECK-NEXT: S_NOP 0, implicit %5
4484 undef %0.sub0:sgpr_192 = S_MOV_B32 00
4485 %0.sub1:sgpr_192 = S_MOV_B32 01
4486 S_NOP 0, implicit %0.sub0_sub1
4488 undef %1.sub2:sgpr_192 = S_MOV_B32 12
4489 %1.sub3:sgpr_192 = S_MOV_B32 13
4490 S_NOP 0, implicit %1.sub2_sub3
4492 undef %2.sub4:sgpr_192 = S_MOV_B32 24
4493 %2.sub5:sgpr_192 = S_MOV_B32 25
4494 S_NOP 0, implicit %2.sub4_sub5
4497 # Skip test_sgpr_192_w96: the 96-bit subreg isn't fully supported for the regclass sgpr_192
4498 # Skip test_sgpr_192_w128: the 128-bit subreg isn't fully supported for the regclass sgpr_192
4499 # Skip test_sgpr_192_w160: the 160-bit subreg isn't fully supported for the regclass sgpr_192
4501 name: test_sgpr_224_w32
4502 tracksRegLiveness: true
4505 ; CHECK-LABEL: name: test_sgpr_224_w32
4506 ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
4507 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]
4508 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 11
4509 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]
4510 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 26
4511 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]
4512 undef %0.sub0:sgpr_224 = S_MOV_B32 00
4513 S_NOP 0, implicit %0.sub0
4515 undef %1.sub1:sgpr_224 = S_MOV_B32 11
4516 S_NOP 0, implicit %1.sub1
4518 undef %2.sub6:sgpr_224 = S_MOV_B32 26
4519 S_NOP 0, implicit %2.sub6
4522 # Skip test_sgpr_224_w64: the 64-bit subreg isn't fully supported for the regclass sgpr_224
4523 # Skip test_sgpr_224_w96: the 96-bit subreg isn't fully supported for the regclass sgpr_224
4524 # Skip test_sgpr_224_w128: the 128-bit subreg isn't fully supported for the regclass sgpr_224
4525 # Skip test_sgpr_224_w160: the 160-bit subreg isn't fully supported for the regclass sgpr_224
4526 # Skip test_sgpr_224_w192: the 192-bit subreg isn't fully supported for the regclass sgpr_224
4528 name: test_sgpr_256_w32
4529 tracksRegLiveness: true
4532 ; CHECK-LABEL: name: test_sgpr_256_w32
4533 ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
4534 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]
4535 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 11
4536 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]
4537 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 27
4538 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]
4539 undef %0.sub0:sgpr_256 = S_MOV_B32 00
4540 S_NOP 0, implicit %0.sub0
4542 undef %1.sub1:sgpr_256 = S_MOV_B32 11
4543 S_NOP 0, implicit %1.sub1
4545 undef %2.sub7:sgpr_256 = S_MOV_B32 27
4546 S_NOP 0, implicit %2.sub7
4550 name: test_sgpr_256_w64
4551 tracksRegLiveness: true
4554 ; CHECK-LABEL: name: test_sgpr_256_w64
4555 ; CHECK: undef %3.sub0:sgpr_64 = S_MOV_B32 0
4556 ; CHECK-NEXT: %3.sub1:sgpr_64 = S_MOV_B32 1
4557 ; CHECK-NEXT: S_NOP 0, implicit %3
4558 ; CHECK-NEXT: undef %4.sub0:sgpr_64 = S_MOV_B32 12
4559 ; CHECK-NEXT: %4.sub1:sgpr_64 = S_MOV_B32 13
4560 ; CHECK-NEXT: S_NOP 0, implicit %4
4561 ; CHECK-NEXT: undef %5.sub0:sgpr_64 = S_MOV_B32 26
4562 ; CHECK-NEXT: %5.sub1:sgpr_64 = S_MOV_B32 27
4563 ; CHECK-NEXT: S_NOP 0, implicit %5
4564 undef %0.sub0:sgpr_256 = S_MOV_B32 00
4565 %0.sub1:sgpr_256 = S_MOV_B32 01
4566 S_NOP 0, implicit %0.sub0_sub1
4568 undef %1.sub2:sgpr_256 = S_MOV_B32 12
4569 %1.sub3:sgpr_256 = S_MOV_B32 13
4570 S_NOP 0, implicit %1.sub2_sub3
4572 undef %2.sub6:sgpr_256 = S_MOV_B32 26
4573 %2.sub7:sgpr_256 = S_MOV_B32 27
4574 S_NOP 0, implicit %2.sub6_sub7
4577 # Skip test_sgpr_256_w96: the 96-bit subreg isn't fully supported for the regclass sgpr_256
4579 name: test_sgpr_256_w128
4580 tracksRegLiveness: true
4583 ; CHECK-LABEL: name: test_sgpr_256_w128
4584 ; CHECK: undef %2.sub0:sgpr_128 = S_MOV_B32 0
4585 ; CHECK-NEXT: %2.sub1:sgpr_128 = S_MOV_B32 1
4586 ; CHECK-NEXT: %2.sub2:sgpr_128 = S_MOV_B32 2
4587 ; CHECK-NEXT: %2.sub3:sgpr_128 = S_MOV_B32 3
4588 ; CHECK-NEXT: S_NOP 0, implicit %2
4589 ; CHECK-NEXT: undef %3.sub0:sgpr_128 = S_MOV_B32 14
4590 ; CHECK-NEXT: %3.sub1:sgpr_128 = S_MOV_B32 15
4591 ; CHECK-NEXT: %3.sub2:sgpr_128 = S_MOV_B32 16
4592 ; CHECK-NEXT: %3.sub3:sgpr_128 = S_MOV_B32 17
4593 ; CHECK-NEXT: S_NOP 0, implicit %3
4594 undef %0.sub0:sgpr_256 = S_MOV_B32 00
4595 %0.sub1:sgpr_256 = S_MOV_B32 01
4596 %0.sub2:sgpr_256 = S_MOV_B32 02
4597 %0.sub3:sgpr_256 = S_MOV_B32 03
4598 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3
4600 undef %1.sub4:sgpr_256 = S_MOV_B32 14
4601 %1.sub5:sgpr_256 = S_MOV_B32 15
4602 %1.sub6:sgpr_256 = S_MOV_B32 16
4603 %1.sub7:sgpr_256 = S_MOV_B32 17
4604 S_NOP 0, implicit %1.sub4_sub5_sub6_sub7
4607 # Skip test_sgpr_256_w160: the 160-bit subreg isn't fully supported for the regclass sgpr_256
4608 # Skip test_sgpr_256_w192: the 192-bit subreg isn't fully supported for the regclass sgpr_256
4610 name: test_sgpr_288_w32
4611 tracksRegLiveness: true
4614 ; CHECK-LABEL: name: test_sgpr_288_w32
4615 ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
4616 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]
4617 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 11
4618 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]
4619 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 28
4620 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]
4621 undef %0.sub0:sgpr_288 = S_MOV_B32 00
4622 S_NOP 0, implicit %0.sub0
4624 undef %1.sub1:sgpr_288 = S_MOV_B32 11
4625 S_NOP 0, implicit %1.sub1
4627 undef %2.sub8:sgpr_288 = S_MOV_B32 28
4628 S_NOP 0, implicit %2.sub8
4631 # Skip test_sgpr_288_w64: the 64-bit subreg isn't fully supported for the regclass sgpr_288
4632 # Skip test_sgpr_288_w96: the 96-bit subreg isn't fully supported for the regclass sgpr_288
4633 # Skip test_sgpr_288_w128: the 128-bit subreg isn't fully supported for the regclass sgpr_288
4635 name: test_sgpr_288_w160
4636 tracksRegLiveness: true
4639 ; CHECK-LABEL: name: test_sgpr_288_w160
4640 ; CHECK: undef %2.sub0:sgpr_160 = S_MOV_B32 0
4641 ; CHECK-NEXT: %2.sub1:sgpr_160 = S_MOV_B32 1
4642 ; CHECK-NEXT: %2.sub2:sgpr_160 = S_MOV_B32 2
4643 ; CHECK-NEXT: %2.sub3:sgpr_160 = S_MOV_B32 3
4644 ; CHECK-NEXT: %2.sub4:sgpr_160 = S_MOV_B32 4
4645 ; CHECK-NEXT: S_NOP 0, implicit %2
4646 ; CHECK-NEXT: undef %3.sub0:sgpr_160 = S_MOV_B32 14
4647 ; CHECK-NEXT: %3.sub1:sgpr_160 = S_MOV_B32 15
4648 ; CHECK-NEXT: %3.sub2:sgpr_160 = S_MOV_B32 16
4649 ; CHECK-NEXT: %3.sub3:sgpr_160 = S_MOV_B32 17
4650 ; CHECK-NEXT: %3.sub4:sgpr_160 = S_MOV_B32 18
4651 ; CHECK-NEXT: S_NOP 0, implicit %3
4652 undef %0.sub0:sgpr_288 = S_MOV_B32 00
4653 %0.sub1:sgpr_288 = S_MOV_B32 01
4654 %0.sub2:sgpr_288 = S_MOV_B32 02
4655 %0.sub3:sgpr_288 = S_MOV_B32 03
4656 %0.sub4:sgpr_288 = S_MOV_B32 04
4657 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4
4659 undef %1.sub4:sgpr_288 = S_MOV_B32 14
4660 %1.sub5:sgpr_288 = S_MOV_B32 15
4661 %1.sub6:sgpr_288 = S_MOV_B32 16
4662 %1.sub7:sgpr_288 = S_MOV_B32 17
4663 %1.sub8:sgpr_288 = S_MOV_B32 18
4664 S_NOP 0, implicit %1.sub4_sub5_sub6_sub7_sub8
4667 # Skip test_sgpr_288_w192: the 192-bit subreg isn't fully supported for the regclass sgpr_288
4668 # Skip test_sgpr_288_w256: the 256-bit subreg isn't fully supported for the regclass sgpr_288
4670 name: test_sgpr_320_w32
4671 tracksRegLiveness: true
4674 ; CHECK-LABEL: name: test_sgpr_320_w32
4675 ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
4676 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]
4677 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 11
4678 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]
4679 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 29
4680 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]
4681 undef %0.sub0:sgpr_320 = S_MOV_B32 00
4682 S_NOP 0, implicit %0.sub0
4684 undef %1.sub1:sgpr_320 = S_MOV_B32 11
4685 S_NOP 0, implicit %1.sub1
4687 undef %2.sub9:sgpr_320 = S_MOV_B32 29
4688 S_NOP 0, implicit %2.sub9
4692 name: test_sgpr_320_w64
4693 tracksRegLiveness: true
4696 ; CHECK-LABEL: name: test_sgpr_320_w64
4697 ; CHECK: undef %3.sub0:sgpr_64 = S_MOV_B32 0
4698 ; CHECK-NEXT: %3.sub1:sgpr_64 = S_MOV_B32 1
4699 ; CHECK-NEXT: S_NOP 0, implicit %3
4700 ; CHECK-NEXT: undef %4.sub0:sgpr_64 = S_MOV_B32 12
4701 ; CHECK-NEXT: %4.sub1:sgpr_64 = S_MOV_B32 13
4702 ; CHECK-NEXT: S_NOP 0, implicit %4
4703 ; CHECK-NEXT: undef %5.sub0:sgpr_64 = S_MOV_B32 28
4704 ; CHECK-NEXT: %5.sub1:sgpr_64 = S_MOV_B32 29
4705 ; CHECK-NEXT: S_NOP 0, implicit %5
4706 undef %0.sub0:sgpr_320 = S_MOV_B32 00
4707 %0.sub1:sgpr_320 = S_MOV_B32 01
4708 S_NOP 0, implicit %0.sub0_sub1
4710 undef %1.sub2:sgpr_320 = S_MOV_B32 12
4711 %1.sub3:sgpr_320 = S_MOV_B32 13
4712 S_NOP 0, implicit %1.sub2_sub3
4714 undef %2.sub8:sgpr_320 = S_MOV_B32 28
4715 %2.sub9:sgpr_320 = S_MOV_B32 29
4716 S_NOP 0, implicit %2.sub8_sub9
4719 # Skip test_sgpr_320_w96: the 96-bit subreg isn't fully supported for the regclass sgpr_320
4720 # Skip test_sgpr_320_w128: the 128-bit subreg isn't fully supported for the regclass sgpr_320
4721 # Skip test_sgpr_320_w160: the 160-bit subreg isn't fully supported for the regclass sgpr_320
4723 name: test_sgpr_320_w192
4724 tracksRegLiveness: true
4727 ; CHECK-LABEL: name: test_sgpr_320_w192
4728 ; CHECK: undef %2.sub0:sgpr_192 = S_MOV_B32 0
4729 ; CHECK-NEXT: %2.sub1:sgpr_192 = S_MOV_B32 1
4730 ; CHECK-NEXT: %2.sub2:sgpr_192 = S_MOV_B32 2
4731 ; CHECK-NEXT: %2.sub3:sgpr_192 = S_MOV_B32 3
4732 ; CHECK-NEXT: %2.sub4:sgpr_192 = S_MOV_B32 4
4733 ; CHECK-NEXT: %2.sub5:sgpr_192 = S_MOV_B32 5
4734 ; CHECK-NEXT: S_NOP 0, implicit %2
4735 ; CHECK-NEXT: undef %3.sub0:sgpr_192 = S_MOV_B32 14
4736 ; CHECK-NEXT: %3.sub1:sgpr_192 = S_MOV_B32 15
4737 ; CHECK-NEXT: %3.sub2:sgpr_192 = S_MOV_B32 16
4738 ; CHECK-NEXT: %3.sub3:sgpr_192 = S_MOV_B32 17
4739 ; CHECK-NEXT: %3.sub4:sgpr_192 = S_MOV_B32 18
4740 ; CHECK-NEXT: %3.sub5:sgpr_192 = S_MOV_B32 19
4741 ; CHECK-NEXT: S_NOP 0, implicit %3
4742 undef %0.sub0:sgpr_320 = S_MOV_B32 00
4743 %0.sub1:sgpr_320 = S_MOV_B32 01
4744 %0.sub2:sgpr_320 = S_MOV_B32 02
4745 %0.sub3:sgpr_320 = S_MOV_B32 03
4746 %0.sub4:sgpr_320 = S_MOV_B32 04
4747 %0.sub5:sgpr_320 = S_MOV_B32 05
4748 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5
4750 undef %1.sub4:sgpr_320 = S_MOV_B32 14
4751 %1.sub5:sgpr_320 = S_MOV_B32 15
4752 %1.sub6:sgpr_320 = S_MOV_B32 16
4753 %1.sub7:sgpr_320 = S_MOV_B32 17
4754 %1.sub8:sgpr_320 = S_MOV_B32 18
4755 %1.sub9:sgpr_320 = S_MOV_B32 19
4756 S_NOP 0, implicit %1.sub4_sub5_sub6_sub7_sub8_sub9
4759 # Skip test_sgpr_320_w256: the 256-bit subreg isn't fully supported for the regclass sgpr_320
4761 name: test_sgpr_352_w32
4762 tracksRegLiveness: true
4765 ; CHECK-LABEL: name: test_sgpr_352_w32
4766 ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
4767 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]
4768 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 11
4769 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]
4770 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 210
4771 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]
4772 undef %0.sub0:sgpr_352 = S_MOV_B32 00
4773 S_NOP 0, implicit %0.sub0
4775 undef %1.sub1:sgpr_352 = S_MOV_B32 11
4776 S_NOP 0, implicit %1.sub1
4778 undef %2.sub10:sgpr_352 = S_MOV_B32 210
4779 S_NOP 0, implicit %2.sub10
4782 # Skip test_sgpr_352_w64: the 64-bit subreg isn't fully supported for the regclass sgpr_352
4783 # Skip test_sgpr_352_w96: the 96-bit subreg isn't fully supported for the regclass sgpr_352
4784 # Skip test_sgpr_352_w128: the 128-bit subreg isn't fully supported for the regclass sgpr_352
4785 # Skip test_sgpr_352_w160: the 160-bit subreg isn't fully supported for the regclass sgpr_352
4786 # Skip test_sgpr_352_w192: the 192-bit subreg isn't fully supported for the regclass sgpr_352
4787 # Skip test_sgpr_352_w256: the 256-bit subreg isn't fully supported for the regclass sgpr_352
4789 name: test_sgpr_384_w32
4790 tracksRegLiveness: true
4793 ; CHECK-LABEL: name: test_sgpr_384_w32
4794 ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
4795 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]
4796 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 11
4797 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]
4798 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 211
4799 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]
4800 undef %0.sub0:sgpr_384 = S_MOV_B32 00
4801 S_NOP 0, implicit %0.sub0
4803 undef %1.sub1:sgpr_384 = S_MOV_B32 11
4804 S_NOP 0, implicit %1.sub1
4806 undef %2.sub11:sgpr_384 = S_MOV_B32 211
4807 S_NOP 0, implicit %2.sub11
4811 name: test_sgpr_384_w64
4812 tracksRegLiveness: true
4815 ; CHECK-LABEL: name: test_sgpr_384_w64
4816 ; CHECK: undef %3.sub0:sgpr_64 = S_MOV_B32 0
4817 ; CHECK-NEXT: %3.sub1:sgpr_64 = S_MOV_B32 1
4818 ; CHECK-NEXT: S_NOP 0, implicit %3
4819 ; CHECK-NEXT: undef %4.sub0:sgpr_64 = S_MOV_B32 110
4820 ; CHECK-NEXT: %4.sub1:sgpr_64 = S_MOV_B32 111
4821 ; CHECK-NEXT: S_NOP 0, implicit %4
4822 ; CHECK-NEXT: undef %5.sub0:sgpr_64 = S_MOV_B32 22
4823 ; CHECK-NEXT: %5.sub1:sgpr_64 = S_MOV_B32 23
4824 ; CHECK-NEXT: S_NOP 0, implicit %5
4825 undef %0.sub0:sgpr_384 = S_MOV_B32 00
4826 %0.sub1:sgpr_384 = S_MOV_B32 01
4827 S_NOP 0, implicit %0.sub0_sub1
4829 undef %1.sub10:sgpr_384 = S_MOV_B32 110
4830 %1.sub11:sgpr_384 = S_MOV_B32 111
4831 S_NOP 0, implicit %1.sub10_sub11
4833 undef %2.sub2:sgpr_384 = S_MOV_B32 22
4834 %2.sub3:sgpr_384 = S_MOV_B32 23
4835 S_NOP 0, implicit %2.sub2_sub3
4838 # Skip test_sgpr_384_w96: the 96-bit subreg isn't fully supported for the regclass sgpr_384
4840 name: test_sgpr_384_w128
4841 tracksRegLiveness: true
4844 ; CHECK-LABEL: name: test_sgpr_384_w128
4845 ; CHECK: undef %3.sub0:sgpr_128 = S_MOV_B32 0
4846 ; CHECK-NEXT: %3.sub1:sgpr_128 = S_MOV_B32 1
4847 ; CHECK-NEXT: %3.sub2:sgpr_128 = S_MOV_B32 2
4848 ; CHECK-NEXT: %3.sub3:sgpr_128 = S_MOV_B32 3
4849 ; CHECK-NEXT: S_NOP 0, implicit %3
4850 ; CHECK-NEXT: undef %4.sub0:sgpr_128 = S_MOV_B32 14
4851 ; CHECK-NEXT: %4.sub1:sgpr_128 = S_MOV_B32 15
4852 ; CHECK-NEXT: %4.sub2:sgpr_128 = S_MOV_B32 16
4853 ; CHECK-NEXT: %4.sub3:sgpr_128 = S_MOV_B32 17
4854 ; CHECK-NEXT: S_NOP 0, implicit %4
4855 ; CHECK-NEXT: undef %5.sub0:sgpr_128 = S_MOV_B32 28
4856 ; CHECK-NEXT: %5.sub1:sgpr_128 = S_MOV_B32 29
4857 ; CHECK-NEXT: %5.sub2:sgpr_128 = S_MOV_B32 210
4858 ; CHECK-NEXT: %5.sub3:sgpr_128 = S_MOV_B32 211
4859 ; CHECK-NEXT: S_NOP 0, implicit %5
4860 undef %0.sub0:sgpr_384 = S_MOV_B32 00
4861 %0.sub1:sgpr_384 = S_MOV_B32 01
4862 %0.sub2:sgpr_384 = S_MOV_B32 02
4863 %0.sub3:sgpr_384 = S_MOV_B32 03
4864 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3
4866 undef %1.sub4:sgpr_384 = S_MOV_B32 14
4867 %1.sub5:sgpr_384 = S_MOV_B32 15
4868 %1.sub6:sgpr_384 = S_MOV_B32 16
4869 %1.sub7:sgpr_384 = S_MOV_B32 17
4870 S_NOP 0, implicit %1.sub4_sub5_sub6_sub7
4872 undef %2.sub8:sgpr_384 = S_MOV_B32 28
4873 %2.sub9:sgpr_384 = S_MOV_B32 29
4874 %2.sub10:sgpr_384 = S_MOV_B32 210
4875 %2.sub11:sgpr_384 = S_MOV_B32 211
4876 S_NOP 0, implicit %2.sub8_sub9_sub10_sub11
4879 # Skip test_sgpr_384_w160: the 160-bit subreg isn't fully supported for the regclass sgpr_384
4880 # Skip test_sgpr_384_w192: the 192-bit subreg isn't fully supported for the regclass sgpr_384
4882 name: test_sgpr_384_w256
4883 tracksRegLiveness: true
4886 ; CHECK-LABEL: name: test_sgpr_384_w256
4887 ; CHECK: undef %2.sub0:sgpr_256 = S_MOV_B32 0
4888 ; CHECK-NEXT: %2.sub1:sgpr_256 = S_MOV_B32 1
4889 ; CHECK-NEXT: %2.sub2:sgpr_256 = S_MOV_B32 2
4890 ; CHECK-NEXT: %2.sub3:sgpr_256 = S_MOV_B32 3
4891 ; CHECK-NEXT: %2.sub4:sgpr_256 = S_MOV_B32 4
4892 ; CHECK-NEXT: %2.sub5:sgpr_256 = S_MOV_B32 5
4893 ; CHECK-NEXT: %2.sub6:sgpr_256 = S_MOV_B32 6
4894 ; CHECK-NEXT: %2.sub7:sgpr_256 = S_MOV_B32 7
4895 ; CHECK-NEXT: S_NOP 0, implicit %2
4896 ; CHECK-NEXT: undef %3.sub0:sgpr_256 = S_MOV_B32 14
4897 ; CHECK-NEXT: %3.sub1:sgpr_256 = S_MOV_B32 15
4898 ; CHECK-NEXT: %3.sub2:sgpr_256 = S_MOV_B32 16
4899 ; CHECK-NEXT: %3.sub3:sgpr_256 = S_MOV_B32 17
4900 ; CHECK-NEXT: %3.sub4:sgpr_256 = S_MOV_B32 18
4901 ; CHECK-NEXT: %3.sub5:sgpr_256 = S_MOV_B32 19
4902 ; CHECK-NEXT: %3.sub6:sgpr_256 = S_MOV_B32 110
4903 ; CHECK-NEXT: %3.sub7:sgpr_256 = S_MOV_B32 111
4904 ; CHECK-NEXT: S_NOP 0, implicit %3
4905 undef %0.sub0:sgpr_384 = S_MOV_B32 00
4906 %0.sub1:sgpr_384 = S_MOV_B32 01
4907 %0.sub2:sgpr_384 = S_MOV_B32 02
4908 %0.sub3:sgpr_384 = S_MOV_B32 03
4909 %0.sub4:sgpr_384 = S_MOV_B32 04
4910 %0.sub5:sgpr_384 = S_MOV_B32 05
4911 %0.sub6:sgpr_384 = S_MOV_B32 06
4912 %0.sub7:sgpr_384 = S_MOV_B32 07
4913 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7
4915 undef %1.sub4:sgpr_384 = S_MOV_B32 14
4916 %1.sub5:sgpr_384 = S_MOV_B32 15
4917 %1.sub6:sgpr_384 = S_MOV_B32 16
4918 %1.sub7:sgpr_384 = S_MOV_B32 17
4919 %1.sub8:sgpr_384 = S_MOV_B32 18
4920 %1.sub9:sgpr_384 = S_MOV_B32 19
4921 %1.sub10:sgpr_384 = S_MOV_B32 110
4922 %1.sub11:sgpr_384 = S_MOV_B32 111
4923 S_NOP 0, implicit %1.sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11
4927 name: test_sgpr_512_w32
4928 tracksRegLiveness: true
4931 ; CHECK-LABEL: name: test_sgpr_512_w32
4932 ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
4933 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]
4934 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 11
4935 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]
4936 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 215
4937 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]
4938 undef %0.sub0:sgpr_512 = S_MOV_B32 00
4939 S_NOP 0, implicit %0.sub0
4941 undef %1.sub1:sgpr_512 = S_MOV_B32 11
4942 S_NOP 0, implicit %1.sub1
4944 undef %2.sub15:sgpr_512 = S_MOV_B32 215
4945 S_NOP 0, implicit %2.sub15
4949 name: test_sgpr_512_w64
4950 tracksRegLiveness: true
4953 ; CHECK-LABEL: name: test_sgpr_512_w64
4954 ; CHECK: undef %3.sub0:sgpr_64 = S_MOV_B32 0
4955 ; CHECK-NEXT: %3.sub1:sgpr_64 = S_MOV_B32 1
4956 ; CHECK-NEXT: S_NOP 0, implicit %3
4957 ; CHECK-NEXT: undef %4.sub0:sgpr_64 = S_MOV_B32 114
4958 ; CHECK-NEXT: %4.sub1:sgpr_64 = S_MOV_B32 115
4959 ; CHECK-NEXT: S_NOP 0, implicit %4
4960 ; CHECK-NEXT: undef %5.sub0:sgpr_64 = S_MOV_B32 22
4961 ; CHECK-NEXT: %5.sub1:sgpr_64 = S_MOV_B32 23
4962 ; CHECK-NEXT: S_NOP 0, implicit %5
4963 undef %0.sub0:sgpr_512 = S_MOV_B32 00
4964 %0.sub1:sgpr_512 = S_MOV_B32 01
4965 S_NOP 0, implicit %0.sub0_sub1
4967 undef %1.sub14:sgpr_512 = S_MOV_B32 114
4968 %1.sub15:sgpr_512 = S_MOV_B32 115
4969 S_NOP 0, implicit %1.sub14_sub15
4971 undef %2.sub2:sgpr_512 = S_MOV_B32 22
4972 %2.sub3:sgpr_512 = S_MOV_B32 23
4973 S_NOP 0, implicit %2.sub2_sub3
4976 # Skip test_sgpr_512_w96: the 96-bit subreg isn't fully supported for the regclass sgpr_512
4978 name: test_sgpr_512_w128
4979 tracksRegLiveness: true
4982 ; CHECK-LABEL: name: test_sgpr_512_w128
4983 ; CHECK: undef %3.sub0:sgpr_128 = S_MOV_B32 0
4984 ; CHECK-NEXT: %3.sub1:sgpr_128 = S_MOV_B32 1
4985 ; CHECK-NEXT: %3.sub2:sgpr_128 = S_MOV_B32 2
4986 ; CHECK-NEXT: %3.sub3:sgpr_128 = S_MOV_B32 3
4987 ; CHECK-NEXT: S_NOP 0, implicit %3
4988 ; CHECK-NEXT: undef %4.sub0:sgpr_128 = S_MOV_B32 112
4989 ; CHECK-NEXT: %4.sub1:sgpr_128 = S_MOV_B32 113
4990 ; CHECK-NEXT: %4.sub2:sgpr_128 = S_MOV_B32 114
4991 ; CHECK-NEXT: %4.sub3:sgpr_128 = S_MOV_B32 115
4992 ; CHECK-NEXT: S_NOP 0, implicit %4
4993 ; CHECK-NEXT: undef %5.sub0:sgpr_128 = S_MOV_B32 24
4994 ; CHECK-NEXT: %5.sub1:sgpr_128 = S_MOV_B32 25
4995 ; CHECK-NEXT: %5.sub2:sgpr_128 = S_MOV_B32 26
4996 ; CHECK-NEXT: %5.sub3:sgpr_128 = S_MOV_B32 27
4997 ; CHECK-NEXT: S_NOP 0, implicit %5
4998 undef %0.sub0:sgpr_512 = S_MOV_B32 00
4999 %0.sub1:sgpr_512 = S_MOV_B32 01
5000 %0.sub2:sgpr_512 = S_MOV_B32 02
5001 %0.sub3:sgpr_512 = S_MOV_B32 03
5002 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3
5004 undef %1.sub12:sgpr_512 = S_MOV_B32 112
5005 %1.sub13:sgpr_512 = S_MOV_B32 113
5006 %1.sub14:sgpr_512 = S_MOV_B32 114
5007 %1.sub15:sgpr_512 = S_MOV_B32 115
5008 S_NOP 0, implicit %1.sub12_sub13_sub14_sub15
5010 undef %2.sub4:sgpr_512 = S_MOV_B32 24
5011 %2.sub5:sgpr_512 = S_MOV_B32 25
5012 %2.sub6:sgpr_512 = S_MOV_B32 26
5013 %2.sub7:sgpr_512 = S_MOV_B32 27
5014 S_NOP 0, implicit %2.sub4_sub5_sub6_sub7
5017 # Skip test_sgpr_512_w160: the 160-bit subreg isn't fully supported for the regclass sgpr_512
5018 # Skip test_sgpr_512_w192: the 192-bit subreg isn't fully supported for the regclass sgpr_512
5020 name: test_sgpr_512_w256
5021 tracksRegLiveness: true
5024 ; CHECK-LABEL: name: test_sgpr_512_w256
5025 ; CHECK: undef %3.sub0:sgpr_256 = S_MOV_B32 0
5026 ; CHECK-NEXT: %3.sub1:sgpr_256 = S_MOV_B32 1
5027 ; CHECK-NEXT: %3.sub2:sgpr_256 = S_MOV_B32 2
5028 ; CHECK-NEXT: %3.sub3:sgpr_256 = S_MOV_B32 3
5029 ; CHECK-NEXT: %3.sub4:sgpr_256 = S_MOV_B32 4
5030 ; CHECK-NEXT: %3.sub5:sgpr_256 = S_MOV_B32 5
5031 ; CHECK-NEXT: %3.sub6:sgpr_256 = S_MOV_B32 6
5032 ; CHECK-NEXT: %3.sub7:sgpr_256 = S_MOV_B32 7
5033 ; CHECK-NEXT: S_NOP 0, implicit %3
5034 ; CHECK-NEXT: undef %4.sub0:sgpr_256 = S_MOV_B32 14
5035 ; CHECK-NEXT: %4.sub1:sgpr_256 = S_MOV_B32 15
5036 ; CHECK-NEXT: %4.sub2:sgpr_256 = S_MOV_B32 16
5037 ; CHECK-NEXT: %4.sub3:sgpr_256 = S_MOV_B32 17
5038 ; CHECK-NEXT: %4.sub4:sgpr_256 = S_MOV_B32 18
5039 ; CHECK-NEXT: %4.sub5:sgpr_256 = S_MOV_B32 19
5040 ; CHECK-NEXT: %4.sub6:sgpr_256 = S_MOV_B32 110
5041 ; CHECK-NEXT: %4.sub7:sgpr_256 = S_MOV_B32 111
5042 ; CHECK-NEXT: S_NOP 0, implicit %4
5043 ; CHECK-NEXT: undef %5.sub0:sgpr_256 = S_MOV_B32 28
5044 ; CHECK-NEXT: %5.sub1:sgpr_256 = S_MOV_B32 29
5045 ; CHECK-NEXT: %5.sub2:sgpr_256 = S_MOV_B32 210
5046 ; CHECK-NEXT: %5.sub3:sgpr_256 = S_MOV_B32 211
5047 ; CHECK-NEXT: %5.sub4:sgpr_256 = S_MOV_B32 212
5048 ; CHECK-NEXT: %5.sub5:sgpr_256 = S_MOV_B32 213
5049 ; CHECK-NEXT: %5.sub6:sgpr_256 = S_MOV_B32 214
5050 ; CHECK-NEXT: %5.sub7:sgpr_256 = S_MOV_B32 215
5051 ; CHECK-NEXT: S_NOP 0, implicit %5
5052 undef %0.sub0:sgpr_512 = S_MOV_B32 00
5053 %0.sub1:sgpr_512 = S_MOV_B32 01
5054 %0.sub2:sgpr_512 = S_MOV_B32 02
5055 %0.sub3:sgpr_512 = S_MOV_B32 03
5056 %0.sub4:sgpr_512 = S_MOV_B32 04
5057 %0.sub5:sgpr_512 = S_MOV_B32 05
5058 %0.sub6:sgpr_512 = S_MOV_B32 06
5059 %0.sub7:sgpr_512 = S_MOV_B32 07
5060 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7
5062 undef %1.sub4:sgpr_512 = S_MOV_B32 14
5063 %1.sub5:sgpr_512 = S_MOV_B32 15
5064 %1.sub6:sgpr_512 = S_MOV_B32 16
5065 %1.sub7:sgpr_512 = S_MOV_B32 17
5066 %1.sub8:sgpr_512 = S_MOV_B32 18
5067 %1.sub9:sgpr_512 = S_MOV_B32 19
5068 %1.sub10:sgpr_512 = S_MOV_B32 110
5069 %1.sub11:sgpr_512 = S_MOV_B32 111
5070 S_NOP 0, implicit %1.sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11
5072 undef %2.sub8:sgpr_512 = S_MOV_B32 28
5073 %2.sub9:sgpr_512 = S_MOV_B32 29
5074 %2.sub10:sgpr_512 = S_MOV_B32 210
5075 %2.sub11:sgpr_512 = S_MOV_B32 211
5076 %2.sub12:sgpr_512 = S_MOV_B32 212
5077 %2.sub13:sgpr_512 = S_MOV_B32 213
5078 %2.sub14:sgpr_512 = S_MOV_B32 214
5079 %2.sub15:sgpr_512 = S_MOV_B32 215
5080 S_NOP 0, implicit %2.sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15
5084 name: test_sgpr_1024_w32
5085 tracksRegLiveness: true
5088 ; CHECK-LABEL: name: test_sgpr_1024_w32
5089 ; CHECK: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
5090 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]
5091 ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 11
5092 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_1]]
5093 ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 231
5094 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_2]]
5095 undef %0.sub0:sgpr_1024 = S_MOV_B32 00
5096 S_NOP 0, implicit %0.sub0
5098 undef %1.sub1:sgpr_1024 = S_MOV_B32 11
5099 S_NOP 0, implicit %1.sub1
5101 undef %2.sub31:sgpr_1024 = S_MOV_B32 231
5102 S_NOP 0, implicit %2.sub31
5106 name: test_sgpr_1024_w64
5107 tracksRegLiveness: true
5110 ; CHECK-LABEL: name: test_sgpr_1024_w64
5111 ; CHECK: undef %3.sub0:sgpr_64 = S_MOV_B32 0
5112 ; CHECK-NEXT: %3.sub1:sgpr_64 = S_MOV_B32 1
5113 ; CHECK-NEXT: S_NOP 0, implicit %3
5114 ; CHECK-NEXT: undef %4.sub0:sgpr_64 = S_MOV_B32 12
5115 ; CHECK-NEXT: %4.sub1:sgpr_64 = S_MOV_B32 13
5116 ; CHECK-NEXT: S_NOP 0, implicit %4
5117 ; CHECK-NEXT: undef %5.sub0:sgpr_64 = S_MOV_B32 230
5118 ; CHECK-NEXT: %5.sub1:sgpr_64 = S_MOV_B32 231
5119 ; CHECK-NEXT: S_NOP 0, implicit %5
5120 undef %0.sub0:sgpr_1024 = S_MOV_B32 00
5121 %0.sub1:sgpr_1024 = S_MOV_B32 01
5122 S_NOP 0, implicit %0.sub0_sub1
5124 undef %1.sub2:sgpr_1024 = S_MOV_B32 12
5125 %1.sub3:sgpr_1024 = S_MOV_B32 13
5126 S_NOP 0, implicit %1.sub2_sub3
5128 undef %2.sub30:sgpr_1024 = S_MOV_B32 230
5129 %2.sub31:sgpr_1024 = S_MOV_B32 231
5130 S_NOP 0, implicit %2.sub30_sub31
5133 # Skip test_sgpr_1024_w96: the 96-bit subreg isn't fully supported for the regclass sgpr_1024
5135 name: test_sgpr_1024_w128
5136 tracksRegLiveness: true
5139 ; CHECK-LABEL: name: test_sgpr_1024_w128
5140 ; CHECK: undef %3.sub0:sgpr_128 = S_MOV_B32 0
5141 ; CHECK-NEXT: %3.sub1:sgpr_128 = S_MOV_B32 1
5142 ; CHECK-NEXT: %3.sub2:sgpr_128 = S_MOV_B32 2
5143 ; CHECK-NEXT: %3.sub3:sgpr_128 = S_MOV_B32 3
5144 ; CHECK-NEXT: S_NOP 0, implicit %3
5145 ; CHECK-NEXT: undef %4.sub0:sgpr_128 = S_MOV_B32 128
5146 ; CHECK-NEXT: %4.sub1:sgpr_128 = S_MOV_B32 129
5147 ; CHECK-NEXT: %4.sub2:sgpr_128 = S_MOV_B32 130
5148 ; CHECK-NEXT: %4.sub3:sgpr_128 = S_MOV_B32 131
5149 ; CHECK-NEXT: S_NOP 0, implicit %4
5150 ; CHECK-NEXT: undef %5.sub0:sgpr_128 = S_MOV_B32 24
5151 ; CHECK-NEXT: %5.sub1:sgpr_128 = S_MOV_B32 25
5152 ; CHECK-NEXT: %5.sub2:sgpr_128 = S_MOV_B32 26
5153 ; CHECK-NEXT: %5.sub3:sgpr_128 = S_MOV_B32 27
5154 ; CHECK-NEXT: S_NOP 0, implicit %5
5155 undef %0.sub0:sgpr_1024 = S_MOV_B32 00
5156 %0.sub1:sgpr_1024 = S_MOV_B32 01
5157 %0.sub2:sgpr_1024 = S_MOV_B32 02
5158 %0.sub3:sgpr_1024 = S_MOV_B32 03
5159 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3
5161 undef %1.sub28:sgpr_1024 = S_MOV_B32 128
5162 %1.sub29:sgpr_1024 = S_MOV_B32 129
5163 %1.sub30:sgpr_1024 = S_MOV_B32 130
5164 %1.sub31:sgpr_1024 = S_MOV_B32 131
5165 S_NOP 0, implicit %1.sub28_sub29_sub30_sub31
5167 undef %2.sub4:sgpr_1024 = S_MOV_B32 24
5168 %2.sub5:sgpr_1024 = S_MOV_B32 25
5169 %2.sub6:sgpr_1024 = S_MOV_B32 26
5170 %2.sub7:sgpr_1024 = S_MOV_B32 27
5171 S_NOP 0, implicit %2.sub4_sub5_sub6_sub7
5174 # Skip test_sgpr_1024_w160: the 160-bit subreg isn't fully supported for the regclass sgpr_1024
5175 # Skip test_sgpr_1024_w192: the 192-bit subreg isn't fully supported for the regclass sgpr_1024
5177 name: test_sgpr_1024_w256
5178 tracksRegLiveness: true
5181 ; CHECK-LABEL: name: test_sgpr_1024_w256
5182 ; CHECK: undef %3.sub0:sgpr_256 = S_MOV_B32 0
5183 ; CHECK-NEXT: %3.sub1:sgpr_256 = S_MOV_B32 1
5184 ; CHECK-NEXT: %3.sub2:sgpr_256 = S_MOV_B32 2
5185 ; CHECK-NEXT: %3.sub3:sgpr_256 = S_MOV_B32 3
5186 ; CHECK-NEXT: %3.sub4:sgpr_256 = S_MOV_B32 4
5187 ; CHECK-NEXT: %3.sub5:sgpr_256 = S_MOV_B32 5
5188 ; CHECK-NEXT: %3.sub6:sgpr_256 = S_MOV_B32 6
5189 ; CHECK-NEXT: %3.sub7:sgpr_256 = S_MOV_B32 7
5190 ; CHECK-NEXT: S_NOP 0, implicit %3
5191 ; CHECK-NEXT: undef %4.sub0:sgpr_256 = S_MOV_B32 124
5192 ; CHECK-NEXT: %4.sub1:sgpr_256 = S_MOV_B32 125
5193 ; CHECK-NEXT: %4.sub2:sgpr_256 = S_MOV_B32 126
5194 ; CHECK-NEXT: %4.sub3:sgpr_256 = S_MOV_B32 127
5195 ; CHECK-NEXT: %4.sub4:sgpr_256 = S_MOV_B32 128
5196 ; CHECK-NEXT: %4.sub5:sgpr_256 = S_MOV_B32 129
5197 ; CHECK-NEXT: %4.sub6:sgpr_256 = S_MOV_B32 130
5198 ; CHECK-NEXT: %4.sub7:sgpr_256 = S_MOV_B32 131
5199 ; CHECK-NEXT: S_NOP 0, implicit %4
5200 ; CHECK-NEXT: undef %5.sub0:sgpr_256 = S_MOV_B32 24
5201 ; CHECK-NEXT: %5.sub1:sgpr_256 = S_MOV_B32 25
5202 ; CHECK-NEXT: %5.sub2:sgpr_256 = S_MOV_B32 26
5203 ; CHECK-NEXT: %5.sub3:sgpr_256 = S_MOV_B32 27
5204 ; CHECK-NEXT: %5.sub4:sgpr_256 = S_MOV_B32 28
5205 ; CHECK-NEXT: %5.sub5:sgpr_256 = S_MOV_B32 29
5206 ; CHECK-NEXT: %5.sub6:sgpr_256 = S_MOV_B32 210
5207 ; CHECK-NEXT: %5.sub7:sgpr_256 = S_MOV_B32 211
5208 ; CHECK-NEXT: S_NOP 0, implicit %5
5209 undef %0.sub0:sgpr_1024 = S_MOV_B32 00
5210 %0.sub1:sgpr_1024 = S_MOV_B32 01
5211 %0.sub2:sgpr_1024 = S_MOV_B32 02
5212 %0.sub3:sgpr_1024 = S_MOV_B32 03
5213 %0.sub4:sgpr_1024 = S_MOV_B32 04
5214 %0.sub5:sgpr_1024 = S_MOV_B32 05
5215 %0.sub6:sgpr_1024 = S_MOV_B32 06
5216 %0.sub7:sgpr_1024 = S_MOV_B32 07
5217 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7
5219 undef %1.sub24:sgpr_1024 = S_MOV_B32 124
5220 %1.sub25:sgpr_1024 = S_MOV_B32 125
5221 %1.sub26:sgpr_1024 = S_MOV_B32 126
5222 %1.sub27:sgpr_1024 = S_MOV_B32 127
5223 %1.sub28:sgpr_1024 = S_MOV_B32 128
5224 %1.sub29:sgpr_1024 = S_MOV_B32 129
5225 %1.sub30:sgpr_1024 = S_MOV_B32 130
5226 %1.sub31:sgpr_1024 = S_MOV_B32 131
5227 S_NOP 0, implicit %1.sub24_sub25_sub26_sub27_sub28_sub29_sub30_sub31
5229 undef %2.sub4:sgpr_1024 = S_MOV_B32 24
5230 %2.sub5:sgpr_1024 = S_MOV_B32 25
5231 %2.sub6:sgpr_1024 = S_MOV_B32 26
5232 %2.sub7:sgpr_1024 = S_MOV_B32 27
5233 %2.sub8:sgpr_1024 = S_MOV_B32 28
5234 %2.sub9:sgpr_1024 = S_MOV_B32 29
5235 %2.sub10:sgpr_1024 = S_MOV_B32 210
5236 %2.sub11:sgpr_1024 = S_MOV_B32 211
5237 S_NOP 0, implicit %2.sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11
5241 name: test_sgpr_1024_w512
5242 tracksRegLiveness: true
5245 ; CHECK-LABEL: name: test_sgpr_1024_w512
5246 ; CHECK: undef %3.sub0:sgpr_512 = S_MOV_B32 0
5247 ; CHECK-NEXT: %3.sub1:sgpr_512 = S_MOV_B32 1
5248 ; CHECK-NEXT: %3.sub2:sgpr_512 = S_MOV_B32 2
5249 ; CHECK-NEXT: %3.sub3:sgpr_512 = S_MOV_B32 3
5250 ; CHECK-NEXT: %3.sub4:sgpr_512 = S_MOV_B32 4
5251 ; CHECK-NEXT: %3.sub5:sgpr_512 = S_MOV_B32 5
5252 ; CHECK-NEXT: %3.sub6:sgpr_512 = S_MOV_B32 6
5253 ; CHECK-NEXT: %3.sub7:sgpr_512 = S_MOV_B32 7
5254 ; CHECK-NEXT: %3.sub8:sgpr_512 = S_MOV_B32 8
5255 ; CHECK-NEXT: %3.sub9:sgpr_512 = S_MOV_B32 9
5256 ; CHECK-NEXT: %3.sub10:sgpr_512 = S_MOV_B32 10
5257 ; CHECK-NEXT: %3.sub11:sgpr_512 = S_MOV_B32 11
5258 ; CHECK-NEXT: %3.sub12:sgpr_512 = S_MOV_B32 12
5259 ; CHECK-NEXT: %3.sub13:sgpr_512 = S_MOV_B32 13
5260 ; CHECK-NEXT: %3.sub14:sgpr_512 = S_MOV_B32 14
5261 ; CHECK-NEXT: %3.sub15:sgpr_512 = S_MOV_B32 15
5262 ; CHECK-NEXT: S_NOP 0, implicit %3
5263 ; CHECK-NEXT: undef %4.sub0:sgpr_512 = S_MOV_B32 116
5264 ; CHECK-NEXT: %4.sub1:sgpr_512 = S_MOV_B32 117
5265 ; CHECK-NEXT: %4.sub2:sgpr_512 = S_MOV_B32 118
5266 ; CHECK-NEXT: %4.sub3:sgpr_512 = S_MOV_B32 119
5267 ; CHECK-NEXT: %4.sub4:sgpr_512 = S_MOV_B32 120
5268 ; CHECK-NEXT: %4.sub5:sgpr_512 = S_MOV_B32 121
5269 ; CHECK-NEXT: %4.sub6:sgpr_512 = S_MOV_B32 122
5270 ; CHECK-NEXT: %4.sub7:sgpr_512 = S_MOV_B32 123
5271 ; CHECK-NEXT: %4.sub8:sgpr_512 = S_MOV_B32 124
5272 ; CHECK-NEXT: %4.sub9:sgpr_512 = S_MOV_B32 125
5273 ; CHECK-NEXT: %4.sub10:sgpr_512 = S_MOV_B32 126
5274 ; CHECK-NEXT: %4.sub11:sgpr_512 = S_MOV_B32 127
5275 ; CHECK-NEXT: %4.sub12:sgpr_512 = S_MOV_B32 128
5276 ; CHECK-NEXT: %4.sub13:sgpr_512 = S_MOV_B32 129
5277 ; CHECK-NEXT: %4.sub14:sgpr_512 = S_MOV_B32 130
5278 ; CHECK-NEXT: %4.sub15:sgpr_512 = S_MOV_B32 131
5279 ; CHECK-NEXT: S_NOP 0, implicit %4
5280 ; CHECK-NEXT: undef %5.sub0:sgpr_512 = S_MOV_B32 24
5281 ; CHECK-NEXT: %5.sub1:sgpr_512 = S_MOV_B32 25
5282 ; CHECK-NEXT: %5.sub2:sgpr_512 = S_MOV_B32 26
5283 ; CHECK-NEXT: %5.sub3:sgpr_512 = S_MOV_B32 27
5284 ; CHECK-NEXT: %5.sub4:sgpr_512 = S_MOV_B32 28
5285 ; CHECK-NEXT: %5.sub5:sgpr_512 = S_MOV_B32 29
5286 ; CHECK-NEXT: %5.sub6:sgpr_512 = S_MOV_B32 210
5287 ; CHECK-NEXT: %5.sub7:sgpr_512 = S_MOV_B32 211
5288 ; CHECK-NEXT: %5.sub8:sgpr_512 = S_MOV_B32 212
5289 ; CHECK-NEXT: %5.sub9:sgpr_512 = S_MOV_B32 213
5290 ; CHECK-NEXT: %5.sub10:sgpr_512 = S_MOV_B32 214
5291 ; CHECK-NEXT: %5.sub11:sgpr_512 = S_MOV_B32 215
5292 ; CHECK-NEXT: %5.sub12:sgpr_512 = S_MOV_B32 216
5293 ; CHECK-NEXT: %5.sub13:sgpr_512 = S_MOV_B32 217
5294 ; CHECK-NEXT: %5.sub14:sgpr_512 = S_MOV_B32 218
5295 ; CHECK-NEXT: %5.sub15:sgpr_512 = S_MOV_B32 219
5296 ; CHECK-NEXT: S_NOP 0, implicit %5
5297 undef %0.sub0:sgpr_1024 = S_MOV_B32 00
5298 %0.sub1:sgpr_1024 = S_MOV_B32 01
5299 %0.sub2:sgpr_1024 = S_MOV_B32 02
5300 %0.sub3:sgpr_1024 = S_MOV_B32 03
5301 %0.sub4:sgpr_1024 = S_MOV_B32 04
5302 %0.sub5:sgpr_1024 = S_MOV_B32 05
5303 %0.sub6:sgpr_1024 = S_MOV_B32 06
5304 %0.sub7:sgpr_1024 = S_MOV_B32 07
5305 %0.sub8:sgpr_1024 = S_MOV_B32 08
5306 %0.sub9:sgpr_1024 = S_MOV_B32 09
5307 %0.sub10:sgpr_1024 = S_MOV_B32 010
5308 %0.sub11:sgpr_1024 = S_MOV_B32 011
5309 %0.sub12:sgpr_1024 = S_MOV_B32 012
5310 %0.sub13:sgpr_1024 = S_MOV_B32 013
5311 %0.sub14:sgpr_1024 = S_MOV_B32 014
5312 %0.sub15:sgpr_1024 = S_MOV_B32 015
5313 S_NOP 0, implicit %0.sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15
5315 undef %1.sub16:sgpr_1024 = S_MOV_B32 116
5316 %1.sub17:sgpr_1024 = S_MOV_B32 117
5317 %1.sub18:sgpr_1024 = S_MOV_B32 118
5318 %1.sub19:sgpr_1024 = S_MOV_B32 119
5319 %1.sub20:sgpr_1024 = S_MOV_B32 120
5320 %1.sub21:sgpr_1024 = S_MOV_B32 121
5321 %1.sub22:sgpr_1024 = S_MOV_B32 122
5322 %1.sub23:sgpr_1024 = S_MOV_B32 123
5323 %1.sub24:sgpr_1024 = S_MOV_B32 124
5324 %1.sub25:sgpr_1024 = S_MOV_B32 125
5325 %1.sub26:sgpr_1024 = S_MOV_B32 126
5326 %1.sub27:sgpr_1024 = S_MOV_B32 127
5327 %1.sub28:sgpr_1024 = S_MOV_B32 128
5328 %1.sub29:sgpr_1024 = S_MOV_B32 129
5329 %1.sub30:sgpr_1024 = S_MOV_B32 130
5330 %1.sub31:sgpr_1024 = S_MOV_B32 131
5331 S_NOP 0, implicit %1.sub16_sub17_sub18_sub19_sub20_sub21_sub22_sub23_sub24_sub25_sub26_sub27_sub28_sub29_sub30_sub31
5333 undef %2.sub4:sgpr_1024 = S_MOV_B32 24
5334 %2.sub5:sgpr_1024 = S_MOV_B32 25
5335 %2.sub6:sgpr_1024 = S_MOV_B32 26
5336 %2.sub7:sgpr_1024 = S_MOV_B32 27
5337 %2.sub8:sgpr_1024 = S_MOV_B32 28
5338 %2.sub9:sgpr_1024 = S_MOV_B32 29
5339 %2.sub10:sgpr_1024 = S_MOV_B32 210
5340 %2.sub11:sgpr_1024 = S_MOV_B32 211
5341 %2.sub12:sgpr_1024 = S_MOV_B32 212
5342 %2.sub13:sgpr_1024 = S_MOV_B32 213
5343 %2.sub14:sgpr_1024 = S_MOV_B32 214
5344 %2.sub15:sgpr_1024 = S_MOV_B32 215
5345 %2.sub16:sgpr_1024 = S_MOV_B32 216
5346 %2.sub17:sgpr_1024 = S_MOV_B32 217
5347 %2.sub18:sgpr_1024 = S_MOV_B32 218
5348 %2.sub19:sgpr_1024 = S_MOV_B32 219
5349 S_NOP 0, implicit %2.sub4_sub5_sub6_sub7_sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15_sub16_sub17_sub18_sub19