| blob | 9c5214338c54a79e6390f2abf0298b88c9fe21df |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=tahiti < %s | FileCheck --check-prefix=GFX6 %s
3 ; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=fiji < %s | FileCheck --check-prefix=GFX8 %s
4 ; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck --check-prefix=GFX9 %s
5 ; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 < %s | FileCheck --check-prefixes=GFX10PLUS,GFX10 %s
6 ; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck --check-prefixes=GFX10PLUS,GFX11 %s
8 define i8 @v_saddsat_i8(i8 %lhs, i8 %rhs) {
9 ; GFX6-LABEL: v_saddsat_i8:
10 ; GFX6: ; %bb.0:
11 ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
12 ; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 8
13 ; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 8
14 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
15 ; GFX6-NEXT: s_movk_i32 s4, 0xff80
16 ; GFX6-NEXT: v_mov_b32_e32 v1, 0x7f
17 ; GFX6-NEXT: v_med3_i32 v0, v0, s4, v1
18 ; GFX6-NEXT: s_setpc_b64 s[30:31]
19 ;
20 ; GFX8-LABEL: v_saddsat_i8:
21 ; GFX8: ; %bb.0:
22 ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
23 ; GFX8-NEXT: v_add_u16_sdwa v0, sext(v0), sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
24 ; GFX8-NEXT: v_min_i16_e32 v0, 0x7f, v0
25 ; GFX8-NEXT: v_max_i16_e32 v0, 0xff80, v0
26 ; GFX8-NEXT: s_setpc_b64 s[30:31]
27 ;
28 ; GFX9-LABEL: v_saddsat_i8:
29 ; GFX9: ; %bb.0:
30 ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
31 ; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1
32 ; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v0
33 ; GFX9-NEXT: v_add_i16 v0, v0, v1 clamp
34 ; GFX9-NEXT: v_ashrrev_i16_e32 v0, 8, v0
35 ; GFX9-NEXT: s_setpc_b64 s[30:31]
36 ;
37 ; GFX10PLUS-LABEL: v_saddsat_i8:
38 ; GFX10PLUS: ; %bb.0:
39 ; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
40 ; GFX10PLUS-NEXT: v_lshlrev_b16 v1, 8, v1
41 ; GFX10PLUS-NEXT: v_lshlrev_b16 v0, 8, v0
42 ; GFX10PLUS-NEXT: v_add_nc_i16 v0, v0, v1 clamp
43 ; GFX10PLUS-NEXT: v_ashrrev_i16 v0, 8, v0
44 ; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
45 %result = call i8 @llvm.sadd.sat.i8(i8 %lhs, i8 %rhs)
46 ret i8 %result
47 }
49 define i16 @v_saddsat_i16(i16 %lhs, i16 %rhs) {
50 ; GFX6-LABEL: v_saddsat_i16:
51 ; GFX6: ; %bb.0:
52 ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
53 ; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16
54 ; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16
55 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
56 ; GFX6-NEXT: s_movk_i32 s4, 0x8000
57 ; GFX6-NEXT: v_mov_b32_e32 v1, 0x7fff
58 ; GFX6-NEXT: v_med3_i32 v0, v0, s4, v1
59 ; GFX6-NEXT: s_setpc_b64 s[30:31]
60 ;
61 ; GFX8-LABEL: v_saddsat_i16:
62 ; GFX8: ; %bb.0:
63 ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
64 ; GFX8-NEXT: v_cmp_gt_i16_e32 vcc, 0, v1
65 ; GFX8-NEXT: v_add_u16_e32 v1, v0, v1
66 ; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], v1, v0
67 ; GFX8-NEXT: v_ashrrev_i16_e32 v0, 15, v1
68 ; GFX8-NEXT: v_xor_b32_e32 v0, 0xffff8000, v0
69 ; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
70 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
71 ; GFX8-NEXT: s_setpc_b64 s[30:31]
72 ;
73 ; GFX9-LABEL: v_saddsat_i16:
74 ; GFX9: ; %bb.0:
75 ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
76 ; GFX9-NEXT: v_add_i16 v0, v0, v1 clamp
77 ; GFX9-NEXT: s_setpc_b64 s[30:31]
78 ;
79 ; GFX10PLUS-LABEL: v_saddsat_i16:
80 ; GFX10PLUS: ; %bb.0:
81 ; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
82 ; GFX10PLUS-NEXT: v_add_nc_i16 v0, v0, v1 clamp
83 ; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
84 %result = call i16 @llvm.sadd.sat.i16(i16 %lhs, i16 %rhs)
85 ret i16 %result
86 }
88 define i32 @v_saddsat_i32(i32 %lhs, i32 %rhs) {
89 ; GFX6-LABEL: v_saddsat_i32:
90 ; GFX6: ; %bb.0:
91 ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
92 ; GFX6-NEXT: v_cmp_gt_i32_e32 vcc, 0, v1
93 ; GFX6-NEXT: v_add_i32_e64 v1, s[4:5], v0, v1
94 ; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v1, v0
95 ; GFX6-NEXT: v_ashrrev_i32_e32 v0, 31, v1
96 ; GFX6-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
97 ; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5]
98 ; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
99 ; GFX6-NEXT: s_setpc_b64 s[30:31]
100 ;
101 ; GFX8-LABEL: v_saddsat_i32:
102 ; GFX8: ; %bb.0:
103 ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
104 ; GFX8-NEXT: v_cmp_gt_i32_e32 vcc, 0, v1
105 ; GFX8-NEXT: v_add_u32_e64 v1, s[4:5], v0, v1
106 ; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v1, v0
107 ; GFX8-NEXT: v_ashrrev_i32_e32 v0, 31, v1
108 ; GFX8-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
109 ; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
110 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
111 ; GFX8-NEXT: s_setpc_b64 s[30:31]
112 ;
113 ; GFX9-LABEL: v_saddsat_i32:
114 ; GFX9: ; %bb.0:
115 ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
116 ; GFX9-NEXT: v_add_i32 v0, v0, v1 clamp
117 ; GFX9-NEXT: s_setpc_b64 s[30:31]
118 ;
119 ; GFX10PLUS-LABEL: v_saddsat_i32:
120 ; GFX10PLUS: ; %bb.0:
121 ; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
122 ; GFX10PLUS-NEXT: v_add_nc_i32 v0, v0, v1 clamp
123 ; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
124 %result = call i32 @llvm.sadd.sat.i32(i32 %lhs, i32 %rhs)
125 ret i32 %result
126 }
128 define <2 x i16> @v_saddsat_v2i16(<2 x i16> %lhs, <2 x i16> %rhs) {
129 ; GFX6-LABEL: v_saddsat_v2i16:
130 ; GFX6: ; %bb.0:
131 ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
132 ; GFX6-NEXT: v_bfe_i32 v2, v2, 0, 16
133 ; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16
134 ; GFX6-NEXT: v_bfe_i32 v3, v3, 0, 16
135 ; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16
136 ; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v3
137 ; GFX6-NEXT: s_movk_i32 s4, 0x8000
138 ; GFX6-NEXT: v_mov_b32_e32 v3, 0x7fff
139 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
140 ; GFX6-NEXT: v_med3_i32 v1, v1, s4, v3
141 ; GFX6-NEXT: v_med3_i32 v0, v0, s4, v3
142 ; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v1
143 ; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
144 ; GFX6-NEXT: v_or_b32_e32 v0, v0, v4
145 ; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1
146 ; GFX6-NEXT: s_setpc_b64 s[30:31]
147 ;
148 ; GFX8-LABEL: v_saddsat_v2i16:
149 ; GFX8: ; %bb.0:
150 ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
151 ; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v1
152 ; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v0
153 ; GFX8-NEXT: v_add_u16_e32 v4, v3, v2
154 ; GFX8-NEXT: v_cmp_lt_i16_e32 vcc, v4, v3
155 ; GFX8-NEXT: v_cmp_gt_i16_e64 s[4:5], 0, v2
156 ; GFX8-NEXT: v_ashrrev_i16_e32 v2, 15, v4
157 ; GFX8-NEXT: v_xor_b32_e32 v2, 0xffff8000, v2
158 ; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc
159 ; GFX8-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
160 ; GFX8-NEXT: v_cmp_gt_i16_e32 vcc, 0, v1
161 ; GFX8-NEXT: v_add_u16_e32 v1, v0, v1
162 ; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], v1, v0
163 ; GFX8-NEXT: v_ashrrev_i16_e32 v0, 15, v1
164 ; GFX8-NEXT: v_xor_b32_e32 v0, 0xffff8000, v0
165 ; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
166 ; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v2
167 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
168 ; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
169 ; GFX8-NEXT: s_setpc_b64 s[30:31]
170 ;
171 ; GFX9-LABEL: v_saddsat_v2i16:
172 ; GFX9: ; %bb.0:
173 ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
174 ; GFX9-NEXT: v_pk_add_i16 v0, v0, v1 clamp
175 ; GFX9-NEXT: s_setpc_b64 s[30:31]
176 ;
177 ; GFX10PLUS-LABEL: v_saddsat_v2i16:
178 ; GFX10PLUS: ; %bb.0:
179 ; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
180 ; GFX10PLUS-NEXT: v_pk_add_i16 v0, v0, v1 clamp
181 ; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
182 %result = call <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
183 ret <2 x i16> %result
184 }
186 define <3 x i16> @v_saddsat_v3i16(<3 x i16> %lhs, <3 x i16> %rhs) {
187 ; GFX6-LABEL: v_saddsat_v3i16:
188 ; GFX6: ; %bb.0:
189 ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
190 ; GFX6-NEXT: v_bfe_i32 v3, v3, 0, 16
191 ; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16
192 ; GFX6-NEXT: v_bfe_i32 v4, v4, 0, 16
193 ; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16
194 ; GFX6-NEXT: v_bfe_i32 v5, v5, 0, 16
195 ; GFX6-NEXT: v_bfe_i32 v2, v2, 0, 16
196 ; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v4
197 ; GFX6-NEXT: s_movk_i32 s4, 0x8000
198 ; GFX6-NEXT: v_mov_b32_e32 v4, 0x7fff
199 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v3
200 ; GFX6-NEXT: v_med3_i32 v1, v1, s4, v4
201 ; GFX6-NEXT: v_med3_i32 v0, v0, s4, v4
202 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v5
203 ; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
204 ; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
205 ; GFX6-NEXT: v_med3_i32 v3, v2, s4, v4
206 ; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
207 ; GFX6-NEXT: v_or_b32_e32 v2, 0xffff0000, v3
208 ; GFX6-NEXT: v_alignbit_b32 v1, v3, v1, 16
209 ; GFX6-NEXT: s_setpc_b64 s[30:31]
210 ;
211 ; GFX8-LABEL: v_saddsat_v3i16:
212 ; GFX8: ; %bb.0:
213 ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
214 ; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v2
215 ; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v0
216 ; GFX8-NEXT: v_add_u16_e32 v6, v5, v4
217 ; GFX8-NEXT: v_cmp_lt_i16_e32 vcc, v6, v5
218 ; GFX8-NEXT: v_cmp_gt_i16_e64 s[4:5], 0, v4
219 ; GFX8-NEXT: v_ashrrev_i16_e32 v4, 15, v6
220 ; GFX8-NEXT: v_xor_b32_e32 v4, 0xffff8000, v4
221 ; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc
222 ; GFX8-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc
223 ; GFX8-NEXT: v_cmp_gt_i16_e32 vcc, 0, v3
224 ; GFX8-NEXT: v_add_u16_e32 v3, v1, v3
225 ; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], v3, v1
226 ; GFX8-NEXT: v_ashrrev_i16_e32 v1, 15, v3
227 ; GFX8-NEXT: v_xor_b32_e32 v1, 0xffff8000, v1
228 ; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
229 ; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
230 ; GFX8-NEXT: v_cmp_gt_i16_e32 vcc, 0, v2
231 ; GFX8-NEXT: v_add_u16_e32 v2, v0, v2
232 ; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], v2, v0
233 ; GFX8-NEXT: v_ashrrev_i16_e32 v0, 15, v2
234 ; GFX8-NEXT: v_xor_b32_e32 v0, 0xffff8000, v0
235 ; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
236 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
237 ; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v4
238 ; GFX8-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
239 ; GFX8-NEXT: s_setpc_b64 s[30:31]
240 ;
241 ; GFX9-LABEL: v_saddsat_v3i16:
242 ; GFX9: ; %bb.0:
243 ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
244 ; GFX9-NEXT: v_pk_add_i16 v1, v1, v3 clamp
245 ; GFX9-NEXT: v_pk_add_i16 v0, v0, v2 clamp
246 ; GFX9-NEXT: s_setpc_b64 s[30:31]
247 ;
248 ; GFX10PLUS-LABEL: v_saddsat_v3i16:
249 ; GFX10PLUS: ; %bb.0:
250 ; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
251 ; GFX10PLUS-NEXT: v_pk_add_i16 v0, v0, v2 clamp
252 ; GFX10PLUS-NEXT: v_pk_add_i16 v1, v1, v3 clamp
253 ; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
254 %result = call <3 x i16> @llvm.sadd.sat.v3i16(<3 x i16> %lhs, <3 x i16> %rhs)
255 ret <3 x i16> %result
256 }
258 define <2 x float> @v_saddsat_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
259 ; GFX6-LABEL: v_saddsat_v4i16:
260 ; GFX6: ; %bb.0:
261 ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
262 ; GFX6-NEXT: v_bfe_i32 v4, v4, 0, 16
263 ; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 16
264 ; GFX6-NEXT: v_bfe_i32 v5, v5, 0, 16
265 ; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 16
266 ; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v5
267 ; GFX6-NEXT: s_movk_i32 s4, 0x8000
268 ; GFX6-NEXT: v_mov_b32_e32 v5, 0x7fff
269 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v4
270 ; GFX6-NEXT: v_med3_i32 v1, v1, s4, v5
271 ; GFX6-NEXT: v_med3_i32 v0, v0, s4, v5
272 ; GFX6-NEXT: v_bfe_i32 v6, v6, 0, 16
273 ; GFX6-NEXT: v_bfe_i32 v2, v2, 0, 16
274 ; GFX6-NEXT: v_bfe_i32 v7, v7, 0, 16
275 ; GFX6-NEXT: v_bfe_i32 v3, v3, 0, 16
276 ; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
277 ; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0
278 ; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
279 ; GFX6-NEXT: v_add_i32_e32 v1, vcc, v3, v7
280 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v6
281 ; GFX6-NEXT: v_med3_i32 v1, v1, s4, v5
282 ; GFX6-NEXT: v_med3_i32 v2, v2, s4, v5
283 ; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
284 ; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v2
285 ; GFX6-NEXT: v_or_b32_e32 v1, v2, v1
286 ; GFX6-NEXT: s_setpc_b64 s[30:31]
287 ;
288 ; GFX8-LABEL: v_saddsat_v4i16:
289 ; GFX8: ; %bb.0:
290 ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
291 ; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v2
292 ; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v0
293 ; GFX8-NEXT: v_add_u16_e32 v6, v5, v4
294 ; GFX8-NEXT: v_cmp_lt_i16_e32 vcc, v6, v5
295 ; GFX8-NEXT: v_cmp_gt_i16_e64 s[4:5], 0, v4
296 ; GFX8-NEXT: v_ashrrev_i16_e32 v4, 15, v6
297 ; GFX8-NEXT: v_xor_b32_e32 v4, 0xffff8000, v4
298 ; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc
299 ; GFX8-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc
300 ; GFX8-NEXT: v_cmp_gt_i16_e32 vcc, 0, v2
301 ; GFX8-NEXT: v_add_u16_e32 v2, v0, v2
302 ; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], v2, v0
303 ; GFX8-NEXT: v_ashrrev_i16_e32 v0, 15, v2
304 ; GFX8-NEXT: v_xor_b32_e32 v0, 0xffff8000, v0
305 ; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
306 ; GFX8-NEXT: v_lshlrev_b32_e32 v4, 16, v4
307 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
308 ; GFX8-NEXT: v_or_b32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
309 ; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v3
310 ; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v1
311 ; GFX8-NEXT: v_add_u16_e32 v5, v4, v2
312 ; GFX8-NEXT: v_cmp_lt_i16_e32 vcc, v5, v4
313 ; GFX8-NEXT: v_cmp_gt_i16_e64 s[4:5], 0, v2
314 ; GFX8-NEXT: v_ashrrev_i16_e32 v2, 15, v5
315 ; GFX8-NEXT: v_xor_b32_e32 v2, 0xffff8000, v2
316 ; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc
317 ; GFX8-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc
318 ; GFX8-NEXT: v_cmp_gt_i16_e32 vcc, 0, v3
319 ; GFX8-NEXT: v_add_u16_e32 v3, v1, v3
320 ; GFX8-NEXT: v_cmp_lt_i16_e64 s[4:5], v3, v1
321 ; GFX8-NEXT: v_ashrrev_i16_e32 v1, 15, v3
322 ; GFX8-NEXT: v_xor_b32_e32 v1, 0xffff8000, v1
323 ; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
324 ; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v2
325 ; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
326 ; GFX8-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
327 ; GFX8-NEXT: s_setpc_b64 s[30:31]
328 ;
329 ; GFX9-LABEL: v_saddsat_v4i16:
330 ; GFX9: ; %bb.0:
331 ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
332 ; GFX9-NEXT: v_pk_add_i16 v0, v0, v2 clamp
333 ; GFX9-NEXT: v_pk_add_i16 v1, v1, v3 clamp
334 ; GFX9-NEXT: s_setpc_b64 s[30:31]
335 ;
336 ; GFX10PLUS-LABEL: v_saddsat_v4i16:
337 ; GFX10PLUS: ; %bb.0:
338 ; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
339 ; GFX10PLUS-NEXT: v_pk_add_i16 v0, v0, v2 clamp
340 ; GFX10PLUS-NEXT: v_pk_add_i16 v1, v1, v3 clamp
341 ; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
342 %result = call <4 x i16> @llvm.sadd.sat.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
343 %cast = bitcast <4 x i16> %result to <2 x float>
344 ret <2 x float> %cast
345 }
347 define <2 x i32> @v_saddsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
348 ; GFX6-LABEL: v_saddsat_v2i32:
349 ; GFX6: ; %bb.0:
350 ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
351 ; GFX6-NEXT: v_cmp_gt_i32_e32 vcc, 0, v2
352 ; GFX6-NEXT: v_add_i32_e64 v2, s[4:5], v0, v2
353 ; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v2, v0
354 ; GFX6-NEXT: v_ashrrev_i32_e32 v0, 31, v2
355 ; GFX6-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
356 ; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5]
357 ; GFX6-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
358 ; GFX6-NEXT: v_add_i32_e64 v2, s[4:5], v1, v3
359 ; GFX6-NEXT: v_cmp_gt_i32_e32 vcc, 0, v3
360 ; GFX6-NEXT: v_cmp_lt_i32_e64 s[4:5], v2, v1
361 ; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v2
362 ; GFX6-NEXT: v_xor_b32_e32 v1, 0x80000000, v1
363 ; GFX6-NEXT: s_xor_b64 vcc, vcc, s[4:5]
364 ; GFX6-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
365 ; GFX6-NEXT: s_setpc_b64 s[30:31]
366 ;
367 ; GFX8-LABEL: v_saddsat_v2i32:
368 ; GFX8: ; %bb.0:
369 ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
370 ; GFX8-NEXT: v_cmp_gt_i32_e32 vcc, 0, v2
371 ; GFX8-NEXT: v_add_u32_e64 v2, s[4:5], v0, v2
372 ; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v2, v0
373 ; GFX8-NEXT: v_ashrrev_i32_e32 v0, 31, v2
374 ; GFX8-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
375 ; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
376 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
377 ; GFX8-NEXT: v_add_u32_e64 v2, s[4:5], v1, v3
378 ; GFX8-NEXT: v_cmp_gt_i32_e32 vcc, 0, v3
379 ; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v2, v1
380 ; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v2
381 ; GFX8-NEXT: v_xor_b32_e32 v1, 0x80000000, v1
382 ; GFX8-NEXT: s_xor_b64 vcc, vcc, s[4:5]
383 ; GFX8-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
384 ; GFX8-NEXT: s_setpc_b64 s[30:31]
385 ;
386 ; GFX9-LABEL: v_saddsat_v2i32:
387 ; GFX9: ; %bb.0:
388 ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
389 ; GFX9-NEXT: v_add_i32 v0, v0, v2 clamp
390 ; GFX9-NEXT: v_add_i32 v1, v1, v3 clamp
391 ; GFX9-NEXT: s_setpc_b64 s[30:31]
392 ;
393 ; GFX10PLUS-LABEL: v_saddsat_v2i32:
394 ; GFX10PLUS: ; %bb.0:
395 ; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
396 ; GFX10PLUS-NEXT: v_add_nc_i32 v0, v0, v2 clamp
397 ; GFX10PLUS-NEXT: v_add_nc_i32 v1, v1, v3 clamp
398 ; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
399 %result = call <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
400 ret <2 x i32> %result
401 }
403 define i64 @v_saddsat_i64(i64 %lhs, i64 %rhs) {
404 ; GFX6-LABEL: v_saddsat_i64:
405 ; GFX6: ; %bb.0:
406 ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
407 ; GFX6-NEXT: v_add_i32_e32 v4, vcc, v0, v2
408 ; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v1, v3, vcc
409 ; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, v[4:5], v[0:1]
410 ; GFX6-NEXT: v_cmp_gt_i64_e64 s[4:5], 0, v[2:3]
411 ; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v5
412 ; GFX6-NEXT: s_xor_b64 vcc, s[4:5], vcc
413 ; GFX6-NEXT: v_cndmask_b32_e32 v0, v4, v1, vcc
414 ; GFX6-NEXT: v_xor_b32_e32 v1, 0x80000000, v1
415 ; GFX6-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
416 ; GFX6-NEXT: s_setpc_b64 s[30:31]
417 ;
418 ; GFX8-LABEL: v_saddsat_i64:
419 ; GFX8: ; %bb.0:
420 ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
421 ; GFX8-NEXT: v_add_u32_e32 v4, vcc, v0, v2
422 ; GFX8-NEXT: v_addc_u32_e32 v5, vcc, v1, v3, vcc
423 ; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, v[4:5], v[0:1]
424 ; GFX8-NEXT: v_cmp_gt_i64_e64 s[4:5], 0, v[2:3]
425 ; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v5
426 ; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc
427 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v1, vcc
428 ; GFX8-NEXT: v_xor_b32_e32 v1, 0x80000000, v1
429 ; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
430 ; GFX8-NEXT: s_setpc_b64 s[30:31]
431 ;
432 ; GFX9-LABEL: v_saddsat_i64:
433 ; GFX9: ; %bb.0:
434 ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
435 ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v0, v2
436 ; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v1, v3, vcc
437 ; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[4:5], v[0:1]
438 ; GFX9-NEXT: v_cmp_gt_i64_e64 s[4:5], 0, v[2:3]
439 ; GFX9-NEXT: v_ashrrev_i32_e32 v1, 31, v5
440 ; GFX9-NEXT: s_xor_b64 vcc, s[4:5], vcc
441 ; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v1, vcc
442 ; GFX9-NEXT: v_xor_b32_e32 v1, 0x80000000, v1
443 ; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
444 ; GFX9-NEXT: s_setpc_b64 s[30:31]
445 ;
446 ; GFX10-LABEL: v_saddsat_i64:
447 ; GFX10: ; %bb.0:
448 ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
449 ; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, v0, v2
450 ; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, v1, v3, vcc_lo
451 ; GFX10-NEXT: v_cmp_gt_i64_e64 s4, 0, v[2:3]
452 ; GFX10-NEXT: v_ashrrev_i32_e32 v6, 31, v5
453 ; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[4:5], v[0:1]
454 ; GFX10-NEXT: v_xor_b32_e32 v1, 0x80000000, v6
455 ; GFX10-NEXT: s_xor_b32 vcc_lo, s4, vcc_lo
456 ; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v6, vcc_lo
457 ; GFX10-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo
458 ; GFX10-NEXT: s_setpc_b64 s[30:31]
459 ;
460 ; GFX11-LABEL: v_saddsat_i64:
461 ; GFX11: ; %bb.0:
462 ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
463 ; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v0, v2
464 ; GFX11-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, v1, v3, vcc_lo
465 ; GFX11-NEXT: v_cmp_gt_i64_e64 s0, 0, v[2:3]
466 ; GFX11-NEXT: v_ashrrev_i32_e32 v6, 31, v5
467 ; GFX11-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[4:5], v[0:1]
468 ; GFX11-NEXT: v_xor_b32_e32 v1, 0x80000000, v6
469 ; GFX11-NEXT: s_xor_b32 vcc_lo, s0, vcc_lo
470 ; GFX11-NEXT: v_dual_cndmask_b32 v0, v4, v6 :: v_dual_cndmask_b32 v1, v5, v1
471 ; GFX11-NEXT: s_setpc_b64 s[30:31]
472 %result = call i64 @llvm.sadd.sat.i64(i64 %lhs, i64 %rhs)
473 ret i64 %result
474 }
476 declare i8 @llvm.sadd.sat.i8(i8, i8) #0
477 declare i16 @llvm.sadd.sat.i16(i16, i16) #0
478 declare <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16>, <2 x i16>) #0
479 declare <3 x i16> @llvm.sadd.sat.v3i16(<3 x i16>, <3 x i16>) #0
480 declare <4 x i16> @llvm.sadd.sat.v4i16(<4 x i16>, <4 x i16>) #0
481 declare i32 @llvm.sadd.sat.i32(i32, i32) #0
482 declare <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32>, <2 x i32>) #0
483 declare i64 @llvm.sadd.sat.i64(i64, i64) #0