1 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -mattr=-flat-for-global -enable-ipra=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CIVI %s
2 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -enable-ipra=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CIVI %s
3 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=-flat-for-global -enable-ipra=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s
4 target datalayout = "A5"
6 ; FIXME: Why is this commuted only sometimes?
7 ; GCN-LABEL: {{^}}i32_fastcc_i32_i32:
8 ; GCN: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
9 ; CIVI-NEXT: v_add_{{i|u}}32_e32 v0, vcc, v0, v1
10 ; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
11 ; GCN-NEXT: s_setpc_b64
12 define fastcc i32 @i32_fastcc_i32_i32(i32 %arg0, i32 %arg1) #1 {
13 %add0 = add i32 %arg0, %arg1
17 ; GCN-LABEL: {{^}}i32_fastcc_i32_i32_stack_object:
18 ; GCN: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
19 ; GCN-NEXT: v_mov_b32_e32 [[K:v[0-9]+]], 9
20 ; CIVI-NEXT: v_add_{{i|u}}32_e32 v0, vcc, v0, v1
21 ; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
22 ; GCN: buffer_store_dword [[K]], off, s[0:3], s32 offset:20
23 ; GCN: s_waitcnt vmcnt(0)
25 ; GCN: ; ScratchSize: 68
26 define fastcc i32 @i32_fastcc_i32_i32_stack_object(i32 %arg0, i32 %arg1) #1 {
27 %alloca = alloca [16 x i32], align 4, addrspace(5)
28 %gep = getelementptr inbounds [16 x i32], ptr addrspace(5) %alloca, i32 0, i32 5
29 store volatile i32 9, ptr addrspace(5) %gep
30 %add0 = add i32 %arg0, %arg1
34 ; GCN-LABEL: {{^}}sibling_call_i32_fastcc_i32_i32:
35 define hidden fastcc i32 @sibling_call_i32_fastcc_i32_i32(i32 %a, i32 %b, i32 %c) #1 {
37 %ret = tail call fastcc i32 @i32_fastcc_i32_i32(i32 %a, i32 %b)
41 ; GCN-LABEL: {{^}}sibling_call_i32_fastcc_i32_i32_stack_object:
42 ; GCN: v_mov_b32_e32 [[NINE:v[0-9]+]], 9
43 ; GCN: buffer_store_dword [[NINE]], off, s[0:3], s32 offset:20
45 ; GCN: ; ScratchSize: 68
46 define fastcc i32 @sibling_call_i32_fastcc_i32_i32_stack_object(i32 %a, i32 %b, i32 %c) #1 {
48 %alloca = alloca [16 x i32], align 4, addrspace(5)
49 %gep = getelementptr inbounds [16 x i32], ptr addrspace(5) %alloca, i32 0, i32 5
50 store volatile i32 9, ptr addrspace(5) %gep
51 %ret = tail call fastcc i32 @i32_fastcc_i32_i32(i32 %a, i32 %b)
55 ; GCN-LABEL: {{^}}sibling_call_i32_fastcc_i32_i32_callee_stack_object:
56 ; GCN: v_mov_b32_e32 [[NINE:v[0-9]+]], 9
57 ; GCN: buffer_store_dword [[NINE]], off, s[0:3], s32 offset:20
59 ; GCN: ; ScratchSize: 136
60 define fastcc i32 @sibling_call_i32_fastcc_i32_i32_callee_stack_object(i32 %a, i32 %b, i32 %c) #1 {
62 %alloca = alloca [16 x i32], align 4, addrspace(5)
63 %gep = getelementptr inbounds [16 x i32], ptr addrspace(5) %alloca, i32 0, i32 5
64 store volatile i32 9, ptr addrspace(5) %gep
65 %ret = tail call fastcc i32 @i32_fastcc_i32_i32_stack_object(i32 %a, i32 %b)
69 ; GCN-LABEL: {{^}}sibling_call_i32_fastcc_i32_i32_unused_result:
70 define fastcc void @sibling_call_i32_fastcc_i32_i32_unused_result(i32 %a, i32 %b, i32 %c) #1 {
72 %ret = tail call fastcc i32 @i32_fastcc_i32_i32(i32 %a, i32 %b)
76 ; It doesn't make sense to do a tail from a kernel
77 ; GCN-LABEL: {{^}}kernel_call_i32_fastcc_i32_i32_unused_result:
78 ;define amdgpu_kernel void @kernel_call_i32_fastcc_i32_i32_unused_result(i32 %a, i32 %b, i32 %c) #1 {
79 define amdgpu_kernel void @kernel_call_i32_fastcc_i32_i32_unused_result(i32 %a, i32 %b, i32 %c) #1 {
81 %ret = tail call fastcc i32 @i32_fastcc_i32_i32(i32 %a, i32 %b)
85 ; GCN-LABEL: {{^}}i32_fastcc_i32_byval_i32:
87 ; GCN-NEXT: buffer_load_dword v1, off, s[0:3], s32{{$}}
88 ; GCN-NEXT: s_waitcnt vmcnt(0)
90 ; CIVI-NEXT: v_add_{{i|u}}32_e32 v0, vcc, v0, v1
91 ; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
93 ; GCN-NEXT: s_setpc_b64 s[30:31]
94 define hidden fastcc i32 @i32_fastcc_i32_byval_i32(i32 %arg0, ptr addrspace(5) byval(i32) align 4 %arg1) #1 {
95 %arg1.load = load i32, ptr addrspace(5) %arg1, align 4
96 %add0 = add i32 %arg0, %arg1.load
100 ; Tail call disallowed with byval in parent.
101 ; GCN-LABEL: {{^}}sibling_call_i32_fastcc_i32_byval_i32_byval_parent:
102 ; GCN-NOT: v_writelane_b32 v{{[0-9]+}}, s32
103 ; GCN: buffer_store_dword v{{[0-9]+}}, off, s[0:3], s32{{$}}
105 ; GCN-NOT: v_readlane_b32 s32
107 define fastcc i32 @sibling_call_i32_fastcc_i32_byval_i32_byval_parent(i32 %a, ptr addrspace(5) byval(i32) %b.byval, i32 %c) #1 {
109 %ret = tail call fastcc i32 @i32_fastcc_i32_byval_i32(i32 %a, ptr addrspace(5) byval(i32) %b.byval)
113 ; Tail call disallowed with byval in parent, not callee. The stack
114 ; usage of incoming arguments must be <= the outgoing stack
117 ; GCN-LABEL: {{^}}sibling_call_i32_fastcc_i32_byval_i32:
120 ; GCN: buffer_load_dword v1, off, s[0:3], 0 offset:16
121 ; GCN: buffer_store_dword v1, off, s[0:3], s32{{$}}
122 ; GCN-NEXT: s_setpc_b64
123 define fastcc i32 @sibling_call_i32_fastcc_i32_byval_i32(i32 %a, [32 x i32] %large) #1 {
125 %ret = tail call fastcc i32 @i32_fastcc_i32_byval_i32(i32 %a, ptr addrspace(5) byval(i32) inttoptr (i32 16 to ptr addrspace(5)))
129 ; GCN-LABEL: {{^}}i32_fastcc_i32_i32_a32i32:
130 ; GCN: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
131 ; GCN-DAG: buffer_load_dword [[LOAD_0:v[0-9]+]], off, s[0:3], s32 offset:4{{$}}
132 ; GCN-DAG: buffer_load_dword [[LOAD_1:v[0-9]+]], off, s[0:3], s32 offset:8{{$}}
134 ; CIVI-NEXT: v_add_{{i|u}}32_e32 v0, vcc, v0, v1
135 ; CIVI: v_add_{{i|u}}32_e32 v0, vcc, v0, [[LOAD_0]]
136 ; CIVI: v_add_{{i|u}}32_e32 v0, vcc, v0, [[LOAD_1]]
139 ; GFX9-NEXT: v_add_u32_e32 v0, v0, v1
140 ; GFX9: v_add3_u32 v0, v0, v3, v2
142 ; GCN-NEXT: s_setpc_b64
143 define fastcc i32 @i32_fastcc_i32_i32_a32i32(i32 %arg0, i32 %arg1, [32 x i32] %large) #1 {
144 %val_firststack = extractvalue [32 x i32] %large, 30
145 %val_laststack = extractvalue [32 x i32] %large, 31
146 %add0 = add i32 %arg0, %arg1
147 %add1 = add i32 %add0, %val_firststack
148 %add2 = add i32 %add1, %val_laststack
152 ; FIXME: Why load and store same location for stack args?
153 ; GCN-LABEL: {{^}}sibling_call_i32_fastcc_i32_i32_a32i32:
155 ; GCN-DAG: buffer_load_dword [[LOAD_0:v[0-9]+]], off, s[0:3], s32{{$}}
156 ; GCN-DAG: buffer_load_dword [[LOAD_1:v[0-9]+]], off, s[0:3], s32 offset:4
157 ; GCN-DAG: buffer_load_dword [[LOAD_2:v[0-9]+]], off, s[0:3], s32 offset:8
161 ; GCN-DAG: buffer_store_dword [[LOAD_0]], off, s[0:3], s32{{$}}
162 ; GCN-DAG: buffer_store_dword [[LOAD_1]], off, s[0:3], s32 offset:4
163 ; GCN-DAG: buffer_store_dword [[LOAD_2]], off, s[0:3], s32 offset:8
167 define fastcc i32 @sibling_call_i32_fastcc_i32_i32_a32i32(i32 %a, i32 %b, [32 x i32] %c) #1 {
169 %ret = tail call fastcc i32 @i32_fastcc_i32_i32_a32i32(i32 %a, i32 %b, [32 x i32] %c)
173 ; GCN-LABEL: {{^}}sibling_call_i32_fastcc_i32_i32_a32i32_stack_object:
174 ; GCN-DAG: v_mov_b32_e32 [[NINE:v[0-9]+]], 9
175 ; GCN: buffer_store_dword [[NINE]], off, s[0:3], s32 offset:32
177 define fastcc i32 @sibling_call_i32_fastcc_i32_i32_a32i32_stack_object(i32 %a, i32 %b, [32 x i32] %c) #1 {
179 %alloca = alloca [16 x i32], align 4, addrspace(5)
180 %gep = getelementptr inbounds [16 x i32], ptr addrspace(5) %alloca, i32 0, i32 5
181 store volatile i32 9, ptr addrspace(5) %gep
182 %ret = tail call fastcc i32 @i32_fastcc_i32_i32_a32i32(i32 %a, i32 %b, [32 x i32] %c)
186 ; If the callee requires more stack argument space than the caller,
187 ; don't do a tail call.
188 ; TODO: Do we really need this restriction?
190 ; GCN-LABEL: {{^}}no_sibling_call_callee_more_stack_space:
193 define fastcc i32 @no_sibling_call_callee_more_stack_space(i32 %a, i32 %b) #1 {
195 %ret = tail call fastcc i32 @i32_fastcc_i32_i32_a32i32(i32 %a, i32 %b, [32 x i32] zeroinitializer)
199 ; Have another non-tail in the function
200 ; GCN-LABEL: {{^}}sibling_call_i32_fastcc_i32_i32_other_call:
201 ; GCN: s_mov_b32 [[FP_SCRATCH_COPY:s[0-9]+]], s33
202 ; GCN-NEXT: s_mov_b32 s33, s32
203 ; GCN-NEXT: s_or_saveexec_b64 s{{\[[0-9]+:[0-9]+\]}}, -1
204 ; GCN-NEXT: buffer_store_dword [[CSRV:v[0-9]+]], off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
205 ; GCN-NEXT: s_mov_b64 exec
206 ; GCN-DAG: s_addk_i32 s32, 0x400
207 ; GCN: v_writelane_b32 [[CSRV]], [[FP_SCRATCH_COPY]], 2
209 ; GCN-DAG: s_getpc_b64 s[4:5]
210 ; GCN-DAG: s_add_u32 s4, s4, i32_fastcc_i32_i32@gotpcrel32@lo+4
211 ; GCN-DAG: s_addc_u32 s5, s5, i32_fastcc_i32_i32@gotpcrel32@hi+12
213 ; GCN-DAG: v_writelane_b32 [[CSRV]], s30, 0
214 ; GCN-DAG: buffer_store_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
215 ; GCN-DAG: buffer_store_dword v42, off, s[0:3], s33 ; 4-byte Folded Spill
216 ; GCN-DAG: v_writelane_b32 [[CSRV]], s31, 1
221 ; GCN-DAG: buffer_load_dword v42, off, s[0:3], s33 ; 4-byte Folded Reload
222 ; GCN-DAG: buffer_load_dword v41, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload
224 ; GCN: s_getpc_b64 s[4:5]
225 ; GCN-NEXT: s_add_u32 s4, s4, sibling_call_i32_fastcc_i32_i32@rel32@lo+4
226 ; GCN-NEXT: s_addc_u32 s5, s5, sibling_call_i32_fastcc_i32_i32@rel32@hi+12
227 ; GCN-NEXT: v_readlane_b32 s31, [[CSRV]], 1
228 ; GCN-NEXT: v_readlane_b32 s30, [[CSRV]], 0
229 ; GCN-NEXT: v_readlane_b32 [[FP_SCRATCH_COPY:s[0-9]+]], [[CSRV]], 2
230 ; GCN-NEXT: s_or_saveexec_b64 s[8:9], -1
231 ; GCN-NEXT: buffer_load_dword [[CSRV]], off, s[0:3], s33 offset:8 ; 4-byte Folded Reload
232 ; GCN-NEXT: s_mov_b64 exec, s[8:9]
233 ; GCN-NEXT: s_addk_i32 s32, 0xfc00
234 ; GCN-NEXT: s_mov_b32 s33, [[FP_SCRATCH_COPY]]
235 ; GCN-NEXT: s_setpc_b64 s[4:5]
236 define fastcc i32 @sibling_call_i32_fastcc_i32_i32_other_call(i32 %a, i32 %b, i32 %c) #1 {
238 %other.call = tail call fastcc i32 @i32_fastcc_i32_i32(i32 %a, i32 %b)
239 %ret = tail call fastcc i32 @sibling_call_i32_fastcc_i32_i32(i32 %a, i32 %b, i32 %other.call)
243 ; Have stack object in caller and stack passed arguments. SP should be
244 ; in same place at function exit.
246 ; GCN-LABEL: {{^}}sibling_call_stack_objecti32_fastcc_i32_i32_a32i32:
248 ; GCN: buffer_load_dword v{{[0-9]+}}, off, s[0:3], s32 offset:
252 ; GCN: buffer_store_dword v{{[0-9]+}}, off, s[0:3], s32 offset:
253 ; GCN: s_setpc_b64 s[4:5]
254 define fastcc i32 @sibling_call_stack_objecti32_fastcc_i32_i32_a32i32(i32 %a, i32 %b, [32 x i32] %c) #1 {
256 %alloca = alloca [16 x i32], align 4, addrspace(5)
257 %gep = getelementptr inbounds [16 x i32], ptr addrspace(5) %alloca, i32 0, i32 5
258 store volatile i32 9, ptr addrspace(5) %gep
259 %ret = tail call fastcc i32 @i32_fastcc_i32_i32_a32i32(i32 %a, i32 %b, [32 x i32] %c)
263 ; GCN-LABEL: {{^}}sibling_call_stack_objecti32_fastcc_i32_i32_a32i32_larger_arg_area:
265 ; GCN: buffer_store_dword v{{[0-9]+}}, off, s[0:3], s32 offset:48
268 ; GCN: s_setpc_b64 s[4:5]
269 define fastcc i32 @sibling_call_stack_objecti32_fastcc_i32_i32_a32i32_larger_arg_area(i32 %a, i32 %b, [36 x i32] %c) #1 {
271 %alloca = alloca [16 x i32], align 4, addrspace(5)
272 %gep = getelementptr inbounds [16 x i32], ptr addrspace(5) %alloca, i32 0, i32 5
273 store volatile i32 9, ptr addrspace(5) %gep
274 %ret = tail call fastcc i32 @i32_fastcc_i32_i32_a32i32(i32 %a, i32 %b, [32 x i32] zeroinitializer)
278 @func_ptr_gv = external unnamed_addr addrspace(4) constant ptr, align 4
280 ; Do support tail calls with a uniform, but unknown, callee.
281 ; GCN-LABEL: {{^}}indirect_uniform_sibling_call_i32_fastcc_i32_i32:
282 ; GCN: s_load_dwordx2 [[GV_ADDR:s\[[0-9]+:[0-9]+\]]]
283 ; GCN: s_load_dwordx2 [[FUNC_PTR:s\[[0-9]+:[0-9]+\]]], [[GV_ADDR]]
284 ; GCN: s_setpc_b64 [[FUNC_PTR]]
285 define hidden fastcc i32 @indirect_uniform_sibling_call_i32_fastcc_i32_i32(i32 %a, i32 %b, i32 %c) #1 {
287 %func.ptr.load = load ptr, ptr addrspace(4) @func_ptr_gv
288 %ret = tail call fastcc i32 %func.ptr.load(i32 %a, i32 %b)
292 ; We can't support a tail call to a divergent target. Use a waterfall
293 ; loop around a regular call
294 ; GCN-LABEL: {{^}}indirect_divergent_sibling_call_i32_fastcc_i32_i32:
295 ; GCN: v_readfirstlane_b32
296 ; GCN: v_readfirstlane_b32
297 ; GCN: s_and_saveexec_b64
299 ; GCN: s_cbranch_execnz
301 define hidden fastcc i32 @indirect_divergent_sibling_call_i32_fastcc_i32_i32(ptr %func.ptr, i32 %a, i32 %b, i32 %c) #1 {
303 %add = add i32 %b, %c
304 %ret = tail call fastcc i32 %func.ptr(i32 %a, i32 %add)
308 declare hidden void @void_fastcc_multi_byval(i32 %a, ptr addrspace(5) byval([3 x i32]) align 16, ptr addrspace(5) byval([2 x i64]))
310 ; GCN-LABEL: {{^}}sibling_call_fastcc_multi_byval:
311 ; GCN-DAG: s_getpc_b64 [[TARGET_ADDR:s\[[0-9]+:[0-9]+\]]]
312 ; GCN-DAG: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0
313 ; GCN-DAG: v_mov_b32_e32 [[NINE:v[0-9]+]], 9
315 ; GCN-DAG: buffer_store_dword [[NINE]], off, s[0:3], s32 offset:144
316 ; GCN-DAG: buffer_store_dword [[NINE]], off, s[0:3], s32 offset:148
317 ; GCN-DAG: buffer_store_dword [[NINE]], off, s[0:3], s32 offset:152
319 ; GCN-DAG: buffer_store_dword [[NINE]], off, s[0:3], s32{{$}}
320 ; GCN-DAG: buffer_store_dword [[NINE]], off, s[0:3], s32 offset:4{{$}}
321 ; GCN-DAG: buffer_store_dword [[NINE]], off, s[0:3], s32 offset:8{{$}}
323 ; GCN-DAG: buffer_store_dword [[ZERO]], off, s[0:3], s32 offset:160
324 ; GCN-DAG: buffer_store_dword [[ZERO]], off, s[0:3], s32 offset:164
325 ; GCN-DAG: buffer_store_dword [[ZERO]], off, s[0:3], s32 offset:168
326 ; GCN-DAG: buffer_store_dword [[ZERO]], off, s[0:3], s32 offset:172
327 ; GCN-DAG: buffer_store_dword [[ZERO]], off, s[0:3], s32 offset:16{{$}}
328 ; GCN-DAG: buffer_store_dword [[ZERO]], off, s[0:3], s32 offset:20{{$}}
329 ; GCN-DAG: buffer_store_dword [[ZERO]], off, s[0:3], s32 offset:24{{$}}
330 ; GCN-DAG: buffer_store_dword [[ZERO]], off, s[0:3], s32 offset:28{{$}}
332 ; GCN: s_setpc_b64 [[TARGET_ADDR]]
333 define fastcc void @sibling_call_fastcc_multi_byval(i32 %a, [64 x i32]) #1 {
335 %alloca0 = alloca [3 x i32], align 16, addrspace(5)
336 %alloca1 = alloca [2 x i64], align 8, addrspace(5)
337 store [3 x i32] [i32 9, i32 9, i32 9], ptr addrspace(5) %alloca0
338 store [2 x i64] zeroinitializer, ptr addrspace(5) %alloca1
339 tail call fastcc void @void_fastcc_multi_byval(i32 %a, ptr addrspace(5) byval([3 x i32]) %alloca0, ptr addrspace(5) byval([2 x i64]) %alloca1)
343 declare hidden void @void_fastcc_byval_and_stack_passed(ptr addrspace(5) byval([3 x i32]) align 16, [32 x i32], i32)
345 ; Callee has a byval and non-byval stack passed argument
346 ; GCN-LABEL: {{^}}sibling_call_byval_and_stack_passed:
347 ; GCN: v_mov_b32_e32 [[NINE:v[0-9]+]], 9
349 ; GCN-DAG: buffer_store_dword [[NINE]], off, s[0:3], s32 offset:144
350 ; GCN-DAG: buffer_store_dword [[NINE]], off, s[0:3], s32 offset:148
351 ; GCN-DAG: buffer_store_dword [[NINE]], off, s[0:3], s32 offset:152
352 ; GCN-DAG: buffer_store_dword [[NINE]], off, s[0:3], s32{{$}}
353 ; GCN-DAG: buffer_store_dword [[NINE]], off, s[0:3], s32 offset:4{{$}}
354 ; GCN-DAG: buffer_store_dword [[NINE]], off, s[0:3], s32 offset:8{{$}}
355 ; GCN-DAG: buffer_store_dword [[NINE]], off, s[0:3], s32 offset:12{{$}}
356 ; GCN-DAG: buffer_store_dword v0, off, s[0:3], s32 offset:16
358 ; GCN: v_mov_b32_e32 v0, 0
359 ; GCN: v_mov_b32_e32 v30, 0
361 ; GCN: s_getpc_b64 [[TARGET_ADDR:s\[[0-9]+:[0-9]+\]]]
362 ; GCN-NEXT: s_add_u32
363 ; GCN-NEXT: s_addc_u32
364 ; GCN-NEXT: s_setpc_b64 [[TARGET_ADDR]]
365 define fastcc void @sibling_call_byval_and_stack_passed(i32 %stack.out.arg, [64 x i32]) #1 {
367 %alloca = alloca [3 x i32], align 16, addrspace(5)
368 store [3 x i32] [i32 9, i32 9, i32 9], ptr addrspace(5) %alloca
369 tail call fastcc void @void_fastcc_byval_and_stack_passed(ptr addrspace(5) byval([3 x i32]) %alloca, [32 x i32] zeroinitializer, i32 %stack.out.arg)
373 declare hidden fastcc i64 @i64_fastcc_i64(i64 %arg0)
375 ; GCN-LABEL: {{^}}sibling_call_i64_fastcc_i64:
377 ; GCN-NEXT: s_getpc_b64
378 ; GCN-NEXT: s_add_u32
379 ; GCN-NEXT: s_addc_u32
380 ; GCN-NEXT: s_setpc_b64
381 define hidden fastcc i64 @sibling_call_i64_fastcc_i64(i64 %a) #1 {
383 %ret = tail call fastcc i64 @i64_fastcc_i64(i64 %a)
387 declare hidden fastcc ptr addrspace(1) @p1i8_fastcc_p1i8(ptr addrspace(1) %arg0)
389 ; GCN-LABEL: {{^}}sibling_call_p1i8_fastcc_p1i8:
391 ; GCN-NEXT: s_getpc_b64
392 ; GCN-NEXT: s_add_u32
393 ; GCN-NEXT: s_addc_u32
394 ; GCN-NEXT: s_setpc_b64
395 define hidden fastcc ptr addrspace(1) @sibling_call_p1i8_fastcc_p1i8(ptr addrspace(1) %a) #1 {
397 %ret = tail call fastcc ptr addrspace(1) @p1i8_fastcc_p1i8(ptr addrspace(1) %a)
398 ret ptr addrspace(1) %ret
401 declare hidden fastcc i16 @i16_fastcc_i16(i16 %arg0)
403 ; GCN-LABEL: {{^}}sibling_call_i16_fastcc_i16:
405 ; GCN-NEXT: s_getpc_b64
406 ; GCN-NEXT: s_add_u32
407 ; GCN-NEXT: s_addc_u32
408 ; GCN-NEXT: s_setpc_b64
409 define hidden fastcc i16 @sibling_call_i16_fastcc_i16(i16 %a) #1 {
411 %ret = tail call fastcc i16 @i16_fastcc_i16(i16 %a)
415 declare hidden fastcc half @f16_fastcc_f16(half %arg0)
417 ; GCN-LABEL: {{^}}sibling_call_f16_fastcc_f16:
419 ; GCN-NEXT: s_getpc_b64
420 ; GCN-NEXT: s_add_u32
421 ; GCN-NEXT: s_addc_u32
422 ; GCN-NEXT: s_setpc_b64
423 define hidden fastcc half @sibling_call_f16_fastcc_f16(half %a) #1 {
425 %ret = tail call fastcc half @f16_fastcc_f16(half %a)
429 declare hidden fastcc <3 x i16> @v3i16_fastcc_v3i16(<3 x i16> %arg0)
431 ; GCN-LABEL: {{^}}sibling_call_v3i16_fastcc_v3i16:
433 ; GCN-NEXT: s_getpc_b64
434 ; GCN-NEXT: s_add_u32
435 ; GCN-NEXT: s_addc_u32
436 ; GCN-NEXT: s_setpc_b64
437 define hidden fastcc <3 x i16> @sibling_call_v3i16_fastcc_v3i16(<3 x i16> %a) #1 {
439 %ret = tail call fastcc <3 x i16> @v3i16_fastcc_v3i16(<3 x i16> %a)
443 declare hidden fastcc <4 x i16> @v4i16_fastcc_v4i16(<4 x i16> %arg0)
445 ; GCN-LABEL: {{^}}sibling_call_v4i16_fastcc_v4i16:
447 ; GCN-NEXT: s_getpc_b64
448 ; GCN-NEXT: s_add_u32
449 ; GCN-NEXT: s_addc_u32
450 ; GCN-NEXT: s_setpc_b64
451 define hidden fastcc <4 x i16> @sibling_call_v4i16_fastcc_v4i16(<4 x i16> %a) #1 {
453 %ret = tail call fastcc <4 x i16> @v4i16_fastcc_v4i16(<4 x i16> %a)
457 declare hidden fastcc <2 x i64> @v2i64_fastcc_v2i64(<2 x i64> %arg0)
459 ; GCN-LABEL: {{^}}sibling_call_v2i64_fastcc_v2i64:
461 ; GCN-NEXT: s_getpc_b64
462 ; GCN-NEXT: s_add_u32
463 ; GCN-NEXT: s_addc_u32
464 ; GCN-NEXT: s_setpc_b64
465 define hidden fastcc <2 x i64> @sibling_call_v2i64_fastcc_v2i64(<2 x i64> %a) #1 {
467 %ret = tail call fastcc <2 x i64> @v2i64_fastcc_v2i64(<2 x i64> %a)
471 attributes #0 = { nounwind }
472 attributes #1 = { nounwind noinline }