| blob | cad1b7d5e2a4136e7ff5d34f3b9ce08934576703 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX6 %s
3 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX8 %s
4 ; RUN: llc -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX11 %s
6 ; FIXME: This should be merged with uint_to_fp.ll, but s_uint_to_fp_v2i64 crashes on r600
8 define amdgpu_kernel void @s_uint_to_fp_i64_to_f16(ptr addrspace(1) %out, i64 %in) #0 {
9 ; GFX6-LABEL: s_uint_to_fp_i64_to_f16:
10 ; GFX6: ; %bb.0:
11 ; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
12 ; GFX6-NEXT: s_mov_b32 s7, 0xf000
13 ; GFX6-NEXT: s_mov_b32 s6, -1
14 ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
15 ; GFX6-NEXT: s_mov_b32 s4, s0
16 ; GFX6-NEXT: s_mov_b32 s5, s1
17 ; GFX6-NEXT: s_flbit_i32_b32 s0, s3
18 ; GFX6-NEXT: s_min_u32 s8, s0, 32
19 ; GFX6-NEXT: s_lshl_b64 s[0:1], s[2:3], s8
20 ; GFX6-NEXT: s_min_u32 s0, s0, 1
21 ; GFX6-NEXT: s_or_b32 s0, s1, s0
22 ; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s0
23 ; GFX6-NEXT: s_sub_i32 s0, 32, s8
24 ; GFX6-NEXT: v_ldexp_f32_e64 v0, v0, s0
25 ; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
26 ; GFX6-NEXT: buffer_store_short v0, off, s[4:7], 0
27 ; GFX6-NEXT: s_endpgm
28 ;
29 ; GFX8-LABEL: s_uint_to_fp_i64_to_f16:
30 ; GFX8: ; %bb.0:
31 ; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
32 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
33 ; GFX8-NEXT: s_flbit_i32_b32 s4, s3
34 ; GFX8-NEXT: s_min_u32 s4, s4, 32
35 ; GFX8-NEXT: s_lshl_b64 s[2:3], s[2:3], s4
36 ; GFX8-NEXT: s_min_u32 s2, s2, 1
37 ; GFX8-NEXT: s_or_b32 s2, s3, s2
38 ; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s2
39 ; GFX8-NEXT: s_sub_i32 s2, 32, s4
40 ; GFX8-NEXT: v_mov_b32_e32 v1, s1
41 ; GFX8-NEXT: v_ldexp_f32 v0, v0, s2
42 ; GFX8-NEXT: v_cvt_f16_f32_e32 v2, v0
43 ; GFX8-NEXT: v_mov_b32_e32 v0, s0
44 ; GFX8-NEXT: flat_store_short v[0:1], v2
45 ; GFX8-NEXT: s_endpgm
46 ;
47 ; GFX11-LABEL: s_uint_to_fp_i64_to_f16:
48 ; GFX11: ; %bb.0:
49 ; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
50 ; GFX11-NEXT: v_mov_b32_e32 v1, 0
51 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
52 ; GFX11-NEXT: s_clz_i32_u32 s4, s3
53 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
54 ; GFX11-NEXT: s_min_u32 s4, s4, 32
55 ; GFX11-NEXT: s_lshl_b64 s[2:3], s[2:3], s4
56 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
57 ; GFX11-NEXT: s_min_u32 s2, s2, 1
58 ; GFX11-NEXT: s_or_b32 s2, s3, s2
59 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
60 ; GFX11-NEXT: v_cvt_f32_u32_e32 v0, s2
61 ; GFX11-NEXT: s_sub_i32 s2, 32, s4
62 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
63 ; GFX11-NEXT: v_ldexp_f32 v0, v0, s2
64 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
65 ; GFX11-NEXT: v_cvt_f16_f32_e32 v0, v0
66 ; GFX11-NEXT: global_store_b16 v1, v0, s[0:1]
67 ; GFX11-NEXT: s_nop 0
68 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
69 ; GFX11-NEXT: s_endpgm
70 %result = uitofp i64 %in to half
71 store half %result, ptr addrspace(1) %out
72 ret void
73 }
75 define amdgpu_kernel void @v_uint_to_fp_i64_to_f16(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
76 ; GFX6-LABEL: v_uint_to_fp_i64_to_f16:
77 ; GFX6: ; %bb.0:
78 ; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
79 ; GFX6-NEXT: s_mov_b32 s7, 0xf000
80 ; GFX6-NEXT: s_mov_b32 s6, 0
81 ; GFX6-NEXT: v_lshlrev_b32_e32 v1, 3, v0
82 ; GFX6-NEXT: v_mov_b32_e32 v2, 0
83 ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
84 ; GFX6-NEXT: s_mov_b64 s[4:5], s[2:3]
85 ; GFX6-NEXT: buffer_load_dwordx2 v[3:4], v[1:2], s[4:7], 0 addr64
86 ; GFX6-NEXT: v_lshlrev_b32_e32 v1, 1, v0
87 ; GFX6-NEXT: s_mov_b64 s[2:3], s[6:7]
88 ; GFX6-NEXT: s_waitcnt vmcnt(0)
89 ; GFX6-NEXT: v_ffbh_u32_e32 v0, v4
90 ; GFX6-NEXT: v_min_u32_e32 v0, 32, v0
91 ; GFX6-NEXT: v_lshl_b64 v[3:4], v[3:4], v0
92 ; GFX6-NEXT: v_min_u32_e32 v3, 1, v3
93 ; GFX6-NEXT: v_or_b32_e32 v3, v4, v3
94 ; GFX6-NEXT: v_cvt_f32_u32_e32 v3, v3
95 ; GFX6-NEXT: v_sub_i32_e32 v0, vcc, 32, v0
96 ; GFX6-NEXT: v_ldexp_f32_e32 v0, v3, v0
97 ; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
98 ; GFX6-NEXT: buffer_store_short v0, v[1:2], s[0:3], 0 addr64
99 ; GFX6-NEXT: s_endpgm
100 ;
101 ; GFX8-LABEL: v_uint_to_fp_i64_to_f16:
102 ; GFX8: ; %bb.0:
103 ; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
104 ; GFX8-NEXT: v_lshlrev_b32_e32 v1, 3, v0
105 ; GFX8-NEXT: v_lshlrev_b32_e32 v0, 1, v0
106 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
107 ; GFX8-NEXT: v_mov_b32_e32 v2, s3
108 ; GFX8-NEXT: v_add_u32_e32 v1, vcc, s2, v1
109 ; GFX8-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc
110 ; GFX8-NEXT: flat_load_dwordx2 v[1:2], v[1:2]
111 ; GFX8-NEXT: s_waitcnt vmcnt(0)
112 ; GFX8-NEXT: v_ffbh_u32_e32 v3, v2
113 ; GFX8-NEXT: v_min_u32_e32 v3, 32, v3
114 ; GFX8-NEXT: v_lshlrev_b64 v[1:2], v3, v[1:2]
115 ; GFX8-NEXT: v_sub_u32_e32 v3, vcc, 32, v3
116 ; GFX8-NEXT: v_min_u32_e32 v1, 1, v1
117 ; GFX8-NEXT: v_or_b32_e32 v1, v2, v1
118 ; GFX8-NEXT: v_cvt_f32_u32_e32 v1, v1
119 ; GFX8-NEXT: v_mov_b32_e32 v2, s1
120 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v0
121 ; GFX8-NEXT: v_ldexp_f32 v1, v1, v3
122 ; GFX8-NEXT: v_cvt_f16_f32_e32 v3, v1
123 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc
124 ; GFX8-NEXT: flat_store_short v[0:1], v3
125 ; GFX8-NEXT: s_endpgm
126 ;
127 ; GFX11-LABEL: v_uint_to_fp_i64_to_f16:
128 ; GFX11: ; %bb.0:
129 ; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
130 ; GFX11-NEXT: v_lshlrev_b32_e32 v1, 3, v0
131 ; GFX11-NEXT: v_lshlrev_b32_e32 v0, 1, v0
132 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
133 ; GFX11-NEXT: global_load_b64 v[1:2], v1, s[2:3]
134 ; GFX11-NEXT: s_waitcnt vmcnt(0)
135 ; GFX11-NEXT: v_clz_i32_u32_e32 v3, v2
136 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
137 ; GFX11-NEXT: v_min_u32_e32 v3, 32, v3
138 ; GFX11-NEXT: v_lshlrev_b64 v[1:2], v3, v[1:2]
139 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
140 ; GFX11-NEXT: v_min_u32_e32 v1, 1, v1
141 ; GFX11-NEXT: v_or_b32_e32 v1, v2, v1
142 ; GFX11-NEXT: v_sub_nc_u32_e32 v2, 32, v3
143 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
144 ; GFX11-NEXT: v_cvt_f32_u32_e32 v1, v1
145 ; GFX11-NEXT: v_ldexp_f32 v1, v1, v2
146 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
147 ; GFX11-NEXT: v_cvt_f16_f32_e32 v1, v1
148 ; GFX11-NEXT: global_store_b16 v0, v1, s[0:1]
149 ; GFX11-NEXT: s_nop 0
150 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
151 ; GFX11-NEXT: s_endpgm
152 %tid = call i32 @llvm.amdgcn.workitem.id.x()
153 %in.gep = getelementptr i64, ptr addrspace(1) %in, i32 %tid
154 %out.gep = getelementptr half, ptr addrspace(1) %out, i32 %tid
155 %val = load i64, ptr addrspace(1) %in.gep
156 %result = uitofp i64 %val to half
157 store half %result, ptr addrspace(1) %out.gep
158 ret void
159 }
161 define amdgpu_kernel void @s_uint_to_fp_i64_to_f32(ptr addrspace(1) %out, i64 %in) #0 {
162 ; GFX6-LABEL: s_uint_to_fp_i64_to_f32:
163 ; GFX6: ; %bb.0:
164 ; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
165 ; GFX6-NEXT: s_mov_b32 s7, 0xf000
166 ; GFX6-NEXT: s_mov_b32 s6, -1
167 ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
168 ; GFX6-NEXT: s_mov_b32 s4, s0
169 ; GFX6-NEXT: s_mov_b32 s5, s1
170 ; GFX6-NEXT: s_flbit_i32_b32 s0, s3
171 ; GFX6-NEXT: s_min_u32 s8, s0, 32
172 ; GFX6-NEXT: s_lshl_b64 s[0:1], s[2:3], s8
173 ; GFX6-NEXT: s_min_u32 s0, s0, 1
174 ; GFX6-NEXT: s_or_b32 s0, s1, s0
175 ; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s0
176 ; GFX6-NEXT: s_sub_i32 s0, 32, s8
177 ; GFX6-NEXT: v_ldexp_f32_e64 v0, v0, s0
178 ; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
179 ; GFX6-NEXT: s_endpgm
180 ;
181 ; GFX8-LABEL: s_uint_to_fp_i64_to_f32:
182 ; GFX8: ; %bb.0:
183 ; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
184 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
185 ; GFX8-NEXT: s_flbit_i32_b32 s4, s3
186 ; GFX8-NEXT: s_min_u32 s4, s4, 32
187 ; GFX8-NEXT: s_lshl_b64 s[2:3], s[2:3], s4
188 ; GFX8-NEXT: s_min_u32 s2, s2, 1
189 ; GFX8-NEXT: s_or_b32 s2, s3, s2
190 ; GFX8-NEXT: v_cvt_f32_u32_e32 v2, s2
191 ; GFX8-NEXT: v_mov_b32_e32 v0, s0
192 ; GFX8-NEXT: s_sub_i32 s0, 32, s4
193 ; GFX8-NEXT: v_mov_b32_e32 v1, s1
194 ; GFX8-NEXT: v_ldexp_f32 v2, v2, s0
195 ; GFX8-NEXT: flat_store_dword v[0:1], v2
196 ; GFX8-NEXT: s_endpgm
197 ;
198 ; GFX11-LABEL: s_uint_to_fp_i64_to_f32:
199 ; GFX11: ; %bb.0:
200 ; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
201 ; GFX11-NEXT: v_mov_b32_e32 v1, 0
202 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
203 ; GFX11-NEXT: s_clz_i32_u32 s4, s3
204 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
205 ; GFX11-NEXT: s_min_u32 s4, s4, 32
206 ; GFX11-NEXT: s_lshl_b64 s[2:3], s[2:3], s4
207 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
208 ; GFX11-NEXT: s_min_u32 s2, s2, 1
209 ; GFX11-NEXT: s_or_b32 s2, s3, s2
210 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
211 ; GFX11-NEXT: v_cvt_f32_u32_e32 v0, s2
212 ; GFX11-NEXT: s_sub_i32 s2, 32, s4
213 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
214 ; GFX11-NEXT: v_ldexp_f32 v0, v0, s2
215 ; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
216 ; GFX11-NEXT: s_nop 0
217 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
218 ; GFX11-NEXT: s_endpgm
219 %result = uitofp i64 %in to float
220 store float %result, ptr addrspace(1) %out
221 ret void
222 }
224 define amdgpu_kernel void @v_uint_to_fp_i64_to_f32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
225 ; GFX6-LABEL: v_uint_to_fp_i64_to_f32:
226 ; GFX6: ; %bb.0:
227 ; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
228 ; GFX6-NEXT: s_mov_b32 s7, 0xf000
229 ; GFX6-NEXT: s_mov_b32 s6, 0
230 ; GFX6-NEXT: v_lshlrev_b32_e32 v1, 3, v0
231 ; GFX6-NEXT: v_mov_b32_e32 v2, 0
232 ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
233 ; GFX6-NEXT: s_mov_b64 s[4:5], s[2:3]
234 ; GFX6-NEXT: buffer_load_dwordx2 v[3:4], v[1:2], s[4:7], 0 addr64
235 ; GFX6-NEXT: v_lshlrev_b32_e32 v1, 2, v0
236 ; GFX6-NEXT: s_mov_b64 s[2:3], s[6:7]
237 ; GFX6-NEXT: s_waitcnt vmcnt(0)
238 ; GFX6-NEXT: v_ffbh_u32_e32 v0, v4
239 ; GFX6-NEXT: v_min_u32_e32 v0, 32, v0
240 ; GFX6-NEXT: v_lshl_b64 v[3:4], v[3:4], v0
241 ; GFX6-NEXT: v_min_u32_e32 v3, 1, v3
242 ; GFX6-NEXT: v_or_b32_e32 v3, v4, v3
243 ; GFX6-NEXT: v_cvt_f32_u32_e32 v3, v3
244 ; GFX6-NEXT: v_sub_i32_e32 v0, vcc, 32, v0
245 ; GFX6-NEXT: v_ldexp_f32_e32 v0, v3, v0
246 ; GFX6-NEXT: buffer_store_dword v0, v[1:2], s[0:3], 0 addr64
247 ; GFX6-NEXT: s_endpgm
248 ;
249 ; GFX8-LABEL: v_uint_to_fp_i64_to_f32:
250 ; GFX8: ; %bb.0:
251 ; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
252 ; GFX8-NEXT: v_lshlrev_b32_e32 v1, 3, v0
253 ; GFX8-NEXT: v_lshlrev_b32_e32 v3, 2, v0
254 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
255 ; GFX8-NEXT: v_mov_b32_e32 v2, s3
256 ; GFX8-NEXT: v_add_u32_e32 v1, vcc, s2, v1
257 ; GFX8-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc
258 ; GFX8-NEXT: flat_load_dwordx2 v[1:2], v[1:2]
259 ; GFX8-NEXT: s_waitcnt vmcnt(0)
260 ; GFX8-NEXT: v_ffbh_u32_e32 v0, v2
261 ; GFX8-NEXT: v_min_u32_e32 v4, 32, v0
262 ; GFX8-NEXT: v_lshlrev_b64 v[0:1], v4, v[1:2]
263 ; GFX8-NEXT: v_mov_b32_e32 v2, s1
264 ; GFX8-NEXT: v_min_u32_e32 v0, 1, v0
265 ; GFX8-NEXT: v_or_b32_e32 v0, v1, v0
266 ; GFX8-NEXT: v_cvt_f32_u32_e32 v5, v0
267 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v3
268 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc
269 ; GFX8-NEXT: v_sub_u32_e32 v2, vcc, 32, v4
270 ; GFX8-NEXT: v_ldexp_f32 v2, v5, v2
271 ; GFX8-NEXT: flat_store_dword v[0:1], v2
272 ; GFX8-NEXT: s_endpgm
273 ;
274 ; GFX11-LABEL: v_uint_to_fp_i64_to_f32:
275 ; GFX11: ; %bb.0:
276 ; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
277 ; GFX11-NEXT: v_lshlrev_b32_e32 v1, 3, v0
278 ; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
279 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
280 ; GFX11-NEXT: global_load_b64 v[1:2], v1, s[2:3]
281 ; GFX11-NEXT: s_waitcnt vmcnt(0)
282 ; GFX11-NEXT: v_clz_i32_u32_e32 v3, v2
283 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
284 ; GFX11-NEXT: v_min_u32_e32 v3, 32, v3
285 ; GFX11-NEXT: v_lshlrev_b64 v[1:2], v3, v[1:2]
286 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
287 ; GFX11-NEXT: v_min_u32_e32 v1, 1, v1
288 ; GFX11-NEXT: v_or_b32_e32 v1, v2, v1
289 ; GFX11-NEXT: v_sub_nc_u32_e32 v2, 32, v3
290 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
291 ; GFX11-NEXT: v_cvt_f32_u32_e32 v1, v1
292 ; GFX11-NEXT: v_ldexp_f32 v1, v1, v2
293 ; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
294 ; GFX11-NEXT: s_nop 0
295 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
296 ; GFX11-NEXT: s_endpgm
297 %tid = call i32 @llvm.amdgcn.workitem.id.x()
298 %in.gep = getelementptr i64, ptr addrspace(1) %in, i32 %tid
299 %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid
300 %val = load i64, ptr addrspace(1) %in.gep
301 %result = uitofp i64 %val to float
302 store float %result, ptr addrspace(1) %out.gep
303 ret void
304 }
306 define amdgpu_kernel void @s_uint_to_fp_v2i64_to_v2f32(ptr addrspace(1) %out, <2 x i64> %in) #0{
307 ; GFX6-LABEL: s_uint_to_fp_v2i64_to_v2f32:
308 ; GFX6: ; %bb.0:
309 ; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xd
310 ; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
311 ; GFX6-NEXT: s_mov_b32 s3, 0xf000
312 ; GFX6-NEXT: s_mov_b32 s2, -1
313 ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
314 ; GFX6-NEXT: s_flbit_i32_b32 s8, s7
315 ; GFX6-NEXT: s_flbit_i32_b32 s9, s5
316 ; GFX6-NEXT: s_min_u32 s8, s8, 32
317 ; GFX6-NEXT: s_min_u32 s9, s9, 32
318 ; GFX6-NEXT: s_lshl_b64 s[6:7], s[6:7], s8
319 ; GFX6-NEXT: s_sub_i32 s8, 32, s8
320 ; GFX6-NEXT: s_lshl_b64 s[4:5], s[4:5], s9
321 ; GFX6-NEXT: s_sub_i32 s9, 32, s9
322 ; GFX6-NEXT: s_min_u32 s6, s6, 1
323 ; GFX6-NEXT: s_min_u32 s4, s4, 1
324 ; GFX6-NEXT: s_or_b32 s6, s7, s6
325 ; GFX6-NEXT: s_or_b32 s4, s5, s4
326 ; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s6
327 ; GFX6-NEXT: v_cvt_f32_u32_e32 v2, s4
328 ; GFX6-NEXT: v_ldexp_f32_e64 v1, v0, s8
329 ; GFX6-NEXT: v_ldexp_f32_e64 v0, v2, s9
330 ; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
331 ; GFX6-NEXT: s_endpgm
332 ;
333 ; GFX8-LABEL: s_uint_to_fp_v2i64_to_v2f32:
334 ; GFX8: ; %bb.0:
335 ; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34
336 ; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
337 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
338 ; GFX8-NEXT: s_flbit_i32_b32 s2, s7
339 ; GFX8-NEXT: s_flbit_i32_b32 s3, s5
340 ; GFX8-NEXT: s_min_u32 s8, s2, 32
341 ; GFX8-NEXT: s_min_u32 s9, s3, 32
342 ; GFX8-NEXT: s_lshl_b64 s[2:3], s[6:7], s8
343 ; GFX8-NEXT: s_min_u32 s2, s2, 1
344 ; GFX8-NEXT: s_lshl_b64 s[4:5], s[4:5], s9
345 ; GFX8-NEXT: s_or_b32 s2, s3, s2
346 ; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s2
347 ; GFX8-NEXT: s_min_u32 s2, s4, 1
348 ; GFX8-NEXT: s_or_b32 s2, s5, s2
349 ; GFX8-NEXT: v_cvt_f32_u32_e32 v2, s2
350 ; GFX8-NEXT: s_sub_i32 s2, 32, s8
351 ; GFX8-NEXT: v_ldexp_f32 v1, v0, s2
352 ; GFX8-NEXT: s_sub_i32 s2, 32, s9
353 ; GFX8-NEXT: v_ldexp_f32 v0, v2, s2
354 ; GFX8-NEXT: v_mov_b32_e32 v3, s1
355 ; GFX8-NEXT: v_mov_b32_e32 v2, s0
356 ; GFX8-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
357 ; GFX8-NEXT: s_endpgm
358 ;
359 ; GFX11-LABEL: s_uint_to_fp_v2i64_to_v2f32:
360 ; GFX11: ; %bb.0:
361 ; GFX11-NEXT: s_clause 0x1
362 ; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x34
363 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
364 ; GFX11-NEXT: v_mov_b32_e32 v3, 0
365 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
366 ; GFX11-NEXT: s_clz_i32_u32 s2, s7
367 ; GFX11-NEXT: s_clz_i32_u32 s3, s5
368 ; GFX11-NEXT: s_min_u32 s8, s2, 32
369 ; GFX11-NEXT: s_min_u32 s9, s3, 32
370 ; GFX11-NEXT: s_lshl_b64 s[2:3], s[6:7], s8
371 ; GFX11-NEXT: s_lshl_b64 s[4:5], s[4:5], s9
372 ; GFX11-NEXT: s_min_u32 s2, s2, 1
373 ; GFX11-NEXT: s_min_u32 s4, s4, 1
374 ; GFX11-NEXT: s_or_b32 s2, s3, s2
375 ; GFX11-NEXT: s_or_b32 s3, s5, s4
376 ; GFX11-NEXT: v_cvt_f32_u32_e32 v0, s2
377 ; GFX11-NEXT: v_cvt_f32_u32_e32 v2, s3
378 ; GFX11-NEXT: s_sub_i32 s2, 32, s8
379 ; GFX11-NEXT: s_sub_i32 s3, 32, s9
380 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
381 ; GFX11-NEXT: v_ldexp_f32 v1, v0, s2
382 ; GFX11-NEXT: v_ldexp_f32 v0, v2, s3
383 ; GFX11-NEXT: global_store_b64 v3, v[0:1], s[0:1]
384 ; GFX11-NEXT: s_nop 0
385 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
386 ; GFX11-NEXT: s_endpgm
387 %result = uitofp <2 x i64> %in to <2 x float>
388 store <2 x float> %result, ptr addrspace(1) %out
389 ret void
390 }
392 define amdgpu_kernel void @v_uint_to_fp_v4i64_to_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
393 ; GFX6-LABEL: v_uint_to_fp_v4i64_to_v4f32:
394 ; GFX6: ; %bb.0:
395 ; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
396 ; GFX6-NEXT: s_mov_b32 s7, 0xf000
397 ; GFX6-NEXT: s_mov_b32 s6, 0
398 ; GFX6-NEXT: v_lshlrev_b32_e32 v8, 5, v0
399 ; GFX6-NEXT: v_mov_b32_e32 v9, 0
400 ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
401 ; GFX6-NEXT: s_mov_b64 s[4:5], s[2:3]
402 ; GFX6-NEXT: buffer_load_dwordx4 v[1:4], v[8:9], s[4:7], 0 addr64 offset:16
403 ; GFX6-NEXT: buffer_load_dwordx4 v[5:8], v[8:9], s[4:7], 0 addr64
404 ; GFX6-NEXT: v_lshlrev_b32_e32 v10, 4, v0
405 ; GFX6-NEXT: v_mov_b32_e32 v11, v9
406 ; GFX6-NEXT: s_mov_b64 s[2:3], s[6:7]
407 ; GFX6-NEXT: s_waitcnt vmcnt(1)
408 ; GFX6-NEXT: v_ffbh_u32_e32 v0, v4
409 ; GFX6-NEXT: v_ffbh_u32_e32 v9, v2
410 ; GFX6-NEXT: s_waitcnt vmcnt(0)
411 ; GFX6-NEXT: v_ffbh_u32_e32 v12, v8
412 ; GFX6-NEXT: v_ffbh_u32_e32 v13, v6
413 ; GFX6-NEXT: v_min_u32_e32 v0, 32, v0
414 ; GFX6-NEXT: v_min_u32_e32 v9, 32, v9
415 ; GFX6-NEXT: v_min_u32_e32 v12, 32, v12
416 ; GFX6-NEXT: v_min_u32_e32 v13, 32, v13
417 ; GFX6-NEXT: v_lshl_b64 v[3:4], v[3:4], v0
418 ; GFX6-NEXT: v_sub_i32_e32 v14, vcc, 32, v0
419 ; GFX6-NEXT: v_lshl_b64 v[0:1], v[1:2], v9
420 ; GFX6-NEXT: v_sub_i32_e32 v2, vcc, 32, v9
421 ; GFX6-NEXT: v_lshl_b64 v[7:8], v[7:8], v12
422 ; GFX6-NEXT: v_sub_i32_e32 v9, vcc, 32, v12
423 ; GFX6-NEXT: v_lshl_b64 v[5:6], v[5:6], v13
424 ; GFX6-NEXT: v_sub_i32_e32 v12, vcc, 32, v13
425 ; GFX6-NEXT: v_min_u32_e32 v3, 1, v3
426 ; GFX6-NEXT: v_min_u32_e32 v0, 1, v0
427 ; GFX6-NEXT: v_min_u32_e32 v7, 1, v7
428 ; GFX6-NEXT: v_min_u32_e32 v5, 1, v5
429 ; GFX6-NEXT: v_or_b32_e32 v3, v4, v3
430 ; GFX6-NEXT: v_or_b32_e32 v0, v1, v0
431 ; GFX6-NEXT: v_or_b32_e32 v1, v8, v7
432 ; GFX6-NEXT: v_or_b32_e32 v4, v6, v5
433 ; GFX6-NEXT: v_cvt_f32_u32_e32 v3, v3
434 ; GFX6-NEXT: v_cvt_f32_u32_e32 v0, v0
435 ; GFX6-NEXT: v_cvt_f32_u32_e32 v1, v1
436 ; GFX6-NEXT: v_cvt_f32_u32_e32 v4, v4
437 ; GFX6-NEXT: v_ldexp_f32_e32 v3, v3, v14
438 ; GFX6-NEXT: v_ldexp_f32_e32 v2, v0, v2
439 ; GFX6-NEXT: v_ldexp_f32_e32 v1, v1, v9
440 ; GFX6-NEXT: v_ldexp_f32_e32 v0, v4, v12
441 ; GFX6-NEXT: buffer_store_dwordx4 v[0:3], v[10:11], s[0:3], 0 addr64
442 ; GFX6-NEXT: s_endpgm
443 ;
444 ; GFX8-LABEL: v_uint_to_fp_v4i64_to_v4f32:
445 ; GFX8: ; %bb.0:
446 ; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
447 ; GFX8-NEXT: v_lshlrev_b32_e32 v1, 5, v0
448 ; GFX8-NEXT: v_lshlrev_b32_e32 v0, 4, v0
449 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
450 ; GFX8-NEXT: v_mov_b32_e32 v2, s3
451 ; GFX8-NEXT: v_add_u32_e32 v5, vcc, s2, v1
452 ; GFX8-NEXT: v_addc_u32_e32 v6, vcc, 0, v2, vcc
453 ; GFX8-NEXT: flat_load_dwordx4 v[1:4], v[5:6]
454 ; GFX8-NEXT: v_add_u32_e32 v5, vcc, 16, v5
455 ; GFX8-NEXT: v_addc_u32_e32 v6, vcc, 0, v6, vcc
456 ; GFX8-NEXT: flat_load_dwordx4 v[5:8], v[5:6]
457 ; GFX8-NEXT: v_add_u32_e32 v9, vcc, s0, v0
458 ; GFX8-NEXT: v_mov_b32_e32 v10, s1
459 ; GFX8-NEXT: v_addc_u32_e32 v10, vcc, 0, v10, vcc
460 ; GFX8-NEXT: s_waitcnt vmcnt(1)
461 ; GFX8-NEXT: v_ffbh_u32_e32 v0, v4
462 ; GFX8-NEXT: v_ffbh_u32_e32 v11, v2
463 ; GFX8-NEXT: v_min_u32_e32 v0, 32, v0
464 ; GFX8-NEXT: v_min_u32_e32 v11, 32, v11
465 ; GFX8-NEXT: v_lshlrev_b64 v[3:4], v0, v[3:4]
466 ; GFX8-NEXT: s_waitcnt vmcnt(0)
467 ; GFX8-NEXT: v_ffbh_u32_e32 v12, v8
468 ; GFX8-NEXT: v_ffbh_u32_e32 v13, v6
469 ; GFX8-NEXT: v_min_u32_e32 v12, 32, v12
470 ; GFX8-NEXT: v_min_u32_e32 v13, 32, v13
471 ; GFX8-NEXT: v_sub_u32_e32 v14, vcc, 32, v0
472 ; GFX8-NEXT: v_lshlrev_b64 v[0:1], v11, v[1:2]
473 ; GFX8-NEXT: v_lshlrev_b64 v[7:8], v12, v[7:8]
474 ; GFX8-NEXT: v_lshlrev_b64 v[5:6], v13, v[5:6]
475 ; GFX8-NEXT: v_min_u32_e32 v3, 1, v3
476 ; GFX8-NEXT: v_min_u32_e32 v0, 1, v0
477 ; GFX8-NEXT: v_min_u32_e32 v7, 1, v7
478 ; GFX8-NEXT: v_min_u32_e32 v5, 1, v5
479 ; GFX8-NEXT: v_or_b32_e32 v3, v4, v3
480 ; GFX8-NEXT: v_or_b32_e32 v0, v1, v0
481 ; GFX8-NEXT: v_or_b32_e32 v1, v8, v7
482 ; GFX8-NEXT: v_or_b32_e32 v4, v6, v5
483 ; GFX8-NEXT: v_cvt_f32_u32_e32 v3, v3
484 ; GFX8-NEXT: v_cvt_f32_u32_e32 v0, v0
485 ; GFX8-NEXT: v_cvt_f32_u32_e32 v5, v1
486 ; GFX8-NEXT: v_cvt_f32_u32_e32 v4, v4
487 ; GFX8-NEXT: v_sub_u32_e32 v2, vcc, 32, v11
488 ; GFX8-NEXT: v_sub_u32_e32 v11, vcc, 32, v12
489 ; GFX8-NEXT: v_sub_u32_e32 v12, vcc, 32, v13
490 ; GFX8-NEXT: v_ldexp_f32 v1, v3, v14
491 ; GFX8-NEXT: v_ldexp_f32 v0, v0, v2
492 ; GFX8-NEXT: v_ldexp_f32 v3, v5, v11
493 ; GFX8-NEXT: v_ldexp_f32 v2, v4, v12
494 ; GFX8-NEXT: flat_store_dwordx4 v[9:10], v[0:3]
495 ; GFX8-NEXT: s_endpgm
496 ;
497 ; GFX11-LABEL: v_uint_to_fp_v4i64_to_v4f32:
498 ; GFX11: ; %bb.0:
499 ; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
500 ; GFX11-NEXT: v_lshlrev_b32_e32 v5, 5, v0
501 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
502 ; GFX11-NEXT: s_clause 0x1
503 ; GFX11-NEXT: global_load_b128 v[1:4], v5, s[2:3] offset:16
504 ; GFX11-NEXT: global_load_b128 v[5:8], v5, s[2:3]
505 ; GFX11-NEXT: s_waitcnt vmcnt(1)
506 ; GFX11-NEXT: v_clz_i32_u32_e32 v9, v4
507 ; GFX11-NEXT: v_clz_i32_u32_e32 v10, v2
508 ; GFX11-NEXT: s_waitcnt vmcnt(0)
509 ; GFX11-NEXT: v_clz_i32_u32_e32 v11, v8
510 ; GFX11-NEXT: v_clz_i32_u32_e32 v12, v6
511 ; GFX11-NEXT: v_min_u32_e32 v9, 32, v9
512 ; GFX11-NEXT: v_min_u32_e32 v10, 32, v10
513 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
514 ; GFX11-NEXT: v_min_u32_e32 v11, 32, v11
515 ; GFX11-NEXT: v_min_u32_e32 v12, 32, v12
516 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
517 ; GFX11-NEXT: v_lshlrev_b64 v[3:4], v9, v[3:4]
518 ; GFX11-NEXT: v_lshlrev_b64 v[1:2], v10, v[1:2]
519 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
520 ; GFX11-NEXT: v_lshlrev_b64 v[7:8], v11, v[7:8]
521 ; GFX11-NEXT: v_lshlrev_b64 v[5:6], v12, v[5:6]
522 ; GFX11-NEXT: v_sub_nc_u32_e32 v9, 32, v9
523 ; GFX11-NEXT: v_sub_nc_u32_e32 v10, 32, v10
524 ; GFX11-NEXT: v_min_u32_e32 v3, 1, v3
525 ; GFX11-NEXT: v_min_u32_e32 v1, 1, v1
526 ; GFX11-NEXT: v_min_u32_e32 v7, 1, v7
527 ; GFX11-NEXT: v_min_u32_e32 v5, 1, v5
528 ; GFX11-NEXT: v_sub_nc_u32_e32 v11, 32, v11
529 ; GFX11-NEXT: v_or_b32_e32 v3, v4, v3
530 ; GFX11-NEXT: v_or_b32_e32 v1, v2, v1
531 ; GFX11-NEXT: v_or_b32_e32 v2, v8, v7
532 ; GFX11-NEXT: v_or_b32_e32 v4, v6, v5
533 ; GFX11-NEXT: v_sub_nc_u32_e32 v5, 32, v12
534 ; GFX11-NEXT: v_cvt_f32_u32_e32 v3, v3
535 ; GFX11-NEXT: v_cvt_f32_u32_e32 v1, v1
536 ; GFX11-NEXT: v_cvt_f32_u32_e32 v6, v2
537 ; GFX11-NEXT: v_cvt_f32_u32_e32 v4, v4
538 ; GFX11-NEXT: v_lshlrev_b32_e32 v7, 4, v0
539 ; GFX11-NEXT: v_ldexp_f32 v3, v3, v9
540 ; GFX11-NEXT: v_ldexp_f32 v2, v1, v10
541 ; GFX11-NEXT: v_ldexp_f32 v1, v6, v11
542 ; GFX11-NEXT: v_ldexp_f32 v0, v4, v5
543 ; GFX11-NEXT: global_store_b128 v7, v[0:3], s[0:1]
544 ; GFX11-NEXT: s_nop 0
545 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
546 ; GFX11-NEXT: s_endpgm
547 %tid = call i32 @llvm.amdgcn.workitem.id.x()
548 %in.gep = getelementptr <4 x i64>, ptr addrspace(1) %in, i32 %tid
549 %out.gep = getelementptr <4 x float>, ptr addrspace(1) %out, i32 %tid
550 %value = load <4 x i64>, ptr addrspace(1) %in.gep
551 %result = uitofp <4 x i64> %value to <4 x float>
552 store <4 x float> %result, ptr addrspace(1) %out.gep
553 ret void
554 }
556 define amdgpu_kernel void @s_uint_to_fp_v2i64_to_v2f16(ptr addrspace(1) %out, <2 x i64> %in) #0{
557 ; GFX6-LABEL: s_uint_to_fp_v2i64_to_v2f16:
558 ; GFX6: ; %bb.0:
559 ; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xd
560 ; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
561 ; GFX6-NEXT: s_mov_b32 s3, 0xf000
562 ; GFX6-NEXT: s_mov_b32 s2, -1
563 ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
564 ; GFX6-NEXT: s_flbit_i32_b32 s8, s7
565 ; GFX6-NEXT: s_flbit_i32_b32 s9, s5
566 ; GFX6-NEXT: s_min_u32 s8, s8, 32
567 ; GFX6-NEXT: s_min_u32 s9, s9, 32
568 ; GFX6-NEXT: s_lshl_b64 s[6:7], s[6:7], s8
569 ; GFX6-NEXT: s_sub_i32 s8, 32, s8
570 ; GFX6-NEXT: s_lshl_b64 s[4:5], s[4:5], s9
571 ; GFX6-NEXT: s_sub_i32 s9, 32, s9
572 ; GFX6-NEXT: s_min_u32 s6, s6, 1
573 ; GFX6-NEXT: s_min_u32 s4, s4, 1
574 ; GFX6-NEXT: s_or_b32 s6, s7, s6
575 ; GFX6-NEXT: s_or_b32 s4, s5, s4
576 ; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s6
577 ; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s4
578 ; GFX6-NEXT: v_ldexp_f32_e64 v0, v0, s8
579 ; GFX6-NEXT: v_ldexp_f32_e64 v1, v1, s9
580 ; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
581 ; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
582 ; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1
583 ; GFX6-NEXT: v_or_b32_e32 v0, v1, v0
584 ; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
585 ; GFX6-NEXT: s_endpgm
586 ;
587 ; GFX8-LABEL: s_uint_to_fp_v2i64_to_v2f16:
588 ; GFX8: ; %bb.0:
589 ; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34
590 ; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
591 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
592 ; GFX8-NEXT: s_flbit_i32_b32 s2, s7
593 ; GFX8-NEXT: s_flbit_i32_b32 s3, s5
594 ; GFX8-NEXT: s_min_u32 s8, s2, 32
595 ; GFX8-NEXT: s_min_u32 s9, s3, 32
596 ; GFX8-NEXT: s_lshl_b64 s[2:3], s[6:7], s8
597 ; GFX8-NEXT: s_min_u32 s2, s2, 1
598 ; GFX8-NEXT: s_or_b32 s2, s3, s2
599 ; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s2
600 ; GFX8-NEXT: s_lshl_b64 s[2:3], s[4:5], s9
601 ; GFX8-NEXT: s_min_u32 s2, s2, 1
602 ; GFX8-NEXT: s_or_b32 s2, s3, s2
603 ; GFX8-NEXT: v_cvt_f32_u32_e32 v1, s2
604 ; GFX8-NEXT: s_sub_i32 s6, 32, s8
605 ; GFX8-NEXT: s_sub_i32 s2, 32, s9
606 ; GFX8-NEXT: v_ldexp_f32 v0, v0, s6
607 ; GFX8-NEXT: v_ldexp_f32 v1, v1, s2
608 ; GFX8-NEXT: v_cvt_f16_f32_sdwa v0, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
609 ; GFX8-NEXT: v_cvt_f16_f32_e32 v1, v1
610 ; GFX8-NEXT: v_or_b32_e32 v2, v1, v0
611 ; GFX8-NEXT: v_mov_b32_e32 v0, s0
612 ; GFX8-NEXT: v_mov_b32_e32 v1, s1
613 ; GFX8-NEXT: flat_store_dword v[0:1], v2
614 ; GFX8-NEXT: s_endpgm
615 ;
616 ; GFX11-LABEL: s_uint_to_fp_v2i64_to_v2f16:
617 ; GFX11: ; %bb.0:
618 ; GFX11-NEXT: s_clause 0x1
619 ; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x34
620 ; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
621 ; GFX11-NEXT: v_mov_b32_e32 v2, 0
622 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
623 ; GFX11-NEXT: s_clz_i32_u32 s2, s7
624 ; GFX11-NEXT: s_clz_i32_u32 s3, s5
625 ; GFX11-NEXT: s_min_u32 s8, s2, 32
626 ; GFX11-NEXT: s_min_u32 s9, s3, 32
627 ; GFX11-NEXT: s_lshl_b64 s[2:3], s[6:7], s8
628 ; GFX11-NEXT: s_lshl_b64 s[4:5], s[4:5], s9
629 ; GFX11-NEXT: s_min_u32 s2, s2, 1
630 ; GFX11-NEXT: s_min_u32 s4, s4, 1
631 ; GFX11-NEXT: s_or_b32 s2, s3, s2
632 ; GFX11-NEXT: s_or_b32 s3, s5, s4
633 ; GFX11-NEXT: v_cvt_f32_u32_e32 v0, s2
634 ; GFX11-NEXT: v_cvt_f32_u32_e32 v1, s3
635 ; GFX11-NEXT: s_sub_i32 s2, 32, s8
636 ; GFX11-NEXT: s_sub_i32 s3, 32, s9
637 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
638 ; GFX11-NEXT: v_ldexp_f32 v0, v0, s2
639 ; GFX11-NEXT: v_ldexp_f32 v1, v1, s3
640 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
641 ; GFX11-NEXT: v_cvt_f16_f32_e32 v0, v0
642 ; GFX11-NEXT: v_cvt_f16_f32_e32 v1, v1
643 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
644 ; GFX11-NEXT: v_pack_b32_f16 v0, v1, v0
645 ; GFX11-NEXT: global_store_b32 v2, v0, s[0:1]
646 ; GFX11-NEXT: s_nop 0
647 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
648 ; GFX11-NEXT: s_endpgm
649 %result = uitofp <2 x i64> %in to <2 x half>
650 store <2 x half> %result, ptr addrspace(1) %out
651 ret void
652 }
654 define amdgpu_kernel void @v_uint_to_fp_v4i64_to_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
655 ; GFX6-LABEL: v_uint_to_fp_v4i64_to_v4f16:
656 ; GFX6: ; %bb.0:
657 ; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
658 ; GFX6-NEXT: s_mov_b32 s7, 0xf000
659 ; GFX6-NEXT: s_mov_b32 s6, 0
660 ; GFX6-NEXT: v_lshlrev_b32_e32 v8, 5, v0
661 ; GFX6-NEXT: v_mov_b32_e32 v9, 0
662 ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
663 ; GFX6-NEXT: s_mov_b64 s[4:5], s[2:3]
664 ; GFX6-NEXT: buffer_load_dwordx4 v[1:4], v[8:9], s[4:7], 0 addr64 offset:16
665 ; GFX6-NEXT: buffer_load_dwordx4 v[5:8], v[8:9], s[4:7], 0 addr64
666 ; GFX6-NEXT: v_lshlrev_b32_e32 v10, 3, v0
667 ; GFX6-NEXT: v_mov_b32_e32 v11, v9
668 ; GFX6-NEXT: s_mov_b64 s[2:3], s[6:7]
669 ; GFX6-NEXT: s_waitcnt vmcnt(1)
670 ; GFX6-NEXT: v_ffbh_u32_e32 v0, v4
671 ; GFX6-NEXT: v_ffbh_u32_e32 v9, v2
672 ; GFX6-NEXT: s_waitcnt vmcnt(0)
673 ; GFX6-NEXT: v_ffbh_u32_e32 v12, v8
674 ; GFX6-NEXT: v_ffbh_u32_e32 v13, v6
675 ; GFX6-NEXT: v_min_u32_e32 v0, 32, v0
676 ; GFX6-NEXT: v_min_u32_e32 v9, 32, v9
677 ; GFX6-NEXT: v_min_u32_e32 v12, 32, v12
678 ; GFX6-NEXT: v_min_u32_e32 v13, 32, v13
679 ; GFX6-NEXT: v_lshl_b64 v[3:4], v[3:4], v0
680 ; GFX6-NEXT: v_sub_i32_e32 v14, vcc, 32, v0
681 ; GFX6-NEXT: v_lshl_b64 v[0:1], v[1:2], v9
682 ; GFX6-NEXT: v_sub_i32_e32 v2, vcc, 32, v9
683 ; GFX6-NEXT: v_lshl_b64 v[7:8], v[7:8], v12
684 ; GFX6-NEXT: v_sub_i32_e32 v9, vcc, 32, v12
685 ; GFX6-NEXT: v_lshl_b64 v[5:6], v[5:6], v13
686 ; GFX6-NEXT: v_sub_i32_e32 v12, vcc, 32, v13
687 ; GFX6-NEXT: v_min_u32_e32 v3, 1, v3
688 ; GFX6-NEXT: v_min_u32_e32 v0, 1, v0
689 ; GFX6-NEXT: v_min_u32_e32 v7, 1, v7
690 ; GFX6-NEXT: v_min_u32_e32 v5, 1, v5
691 ; GFX6-NEXT: v_or_b32_e32 v3, v4, v3
692 ; GFX6-NEXT: v_or_b32_e32 v0, v1, v0
693 ; GFX6-NEXT: v_or_b32_e32 v1, v8, v7
694 ; GFX6-NEXT: v_or_b32_e32 v4, v6, v5
695 ; GFX6-NEXT: v_cvt_f32_u32_e32 v3, v3
696 ; GFX6-NEXT: v_cvt_f32_u32_e32 v0, v0
697 ; GFX6-NEXT: v_cvt_f32_u32_e32 v1, v1
698 ; GFX6-NEXT: v_cvt_f32_u32_e32 v4, v4
699 ; GFX6-NEXT: v_ldexp_f32_e32 v3, v3, v14
700 ; GFX6-NEXT: v_ldexp_f32_e32 v0, v0, v2
701 ; GFX6-NEXT: v_ldexp_f32_e32 v1, v1, v9
702 ; GFX6-NEXT: v_ldexp_f32_e32 v2, v4, v12
703 ; GFX6-NEXT: v_cvt_f16_f32_e32 v3, v3
704 ; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
705 ; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1
706 ; GFX6-NEXT: v_cvt_f16_f32_e32 v2, v2
707 ; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3
708 ; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v1
709 ; GFX6-NEXT: v_or_b32_e32 v1, v0, v3
710 ; GFX6-NEXT: v_or_b32_e32 v0, v2, v4
711 ; GFX6-NEXT: buffer_store_dwordx2 v[0:1], v[10:11], s[0:3], 0 addr64
712 ; GFX6-NEXT: s_endpgm
713 ;
714 ; GFX8-LABEL: v_uint_to_fp_v4i64_to_v4f16:
715 ; GFX8: ; %bb.0:
716 ; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
717 ; GFX8-NEXT: v_lshlrev_b32_e32 v1, 5, v0
718 ; GFX8-NEXT: v_lshlrev_b32_e32 v9, 3, v0
719 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
720 ; GFX8-NEXT: v_mov_b32_e32 v2, s3
721 ; GFX8-NEXT: v_add_u32_e32 v5, vcc, s2, v1
722 ; GFX8-NEXT: v_addc_u32_e32 v6, vcc, 0, v2, vcc
723 ; GFX8-NEXT: flat_load_dwordx4 v[1:4], v[5:6]
724 ; GFX8-NEXT: v_add_u32_e32 v5, vcc, 16, v5
725 ; GFX8-NEXT: v_addc_u32_e32 v6, vcc, 0, v6, vcc
726 ; GFX8-NEXT: flat_load_dwordx4 v[5:8], v[5:6]
727 ; GFX8-NEXT: v_mov_b32_e32 v10, s1
728 ; GFX8-NEXT: s_waitcnt vmcnt(1)
729 ; GFX8-NEXT: v_ffbh_u32_e32 v0, v4
730 ; GFX8-NEXT: v_ffbh_u32_e32 v11, v2
731 ; GFX8-NEXT: v_min_u32_e32 v0, 32, v0
732 ; GFX8-NEXT: v_min_u32_e32 v11, 32, v11
733 ; GFX8-NEXT: v_lshlrev_b64 v[3:4], v0, v[3:4]
734 ; GFX8-NEXT: s_waitcnt vmcnt(0)
735 ; GFX8-NEXT: v_ffbh_u32_e32 v12, v8
736 ; GFX8-NEXT: v_ffbh_u32_e32 v13, v6
737 ; GFX8-NEXT: v_min_u32_e32 v12, 32, v12
738 ; GFX8-NEXT: v_min_u32_e32 v13, 32, v13
739 ; GFX8-NEXT: v_sub_u32_e32 v14, vcc, 32, v0
740 ; GFX8-NEXT: v_lshlrev_b64 v[0:1], v11, v[1:2]
741 ; GFX8-NEXT: v_lshlrev_b64 v[7:8], v12, v[7:8]
742 ; GFX8-NEXT: v_lshlrev_b64 v[5:6], v13, v[5:6]
743 ; GFX8-NEXT: v_min_u32_e32 v3, 1, v3
744 ; GFX8-NEXT: v_min_u32_e32 v0, 1, v0
745 ; GFX8-NEXT: v_min_u32_e32 v7, 1, v7
746 ; GFX8-NEXT: v_min_u32_e32 v5, 1, v5
747 ; GFX8-NEXT: v_or_b32_e32 v3, v4, v3
748 ; GFX8-NEXT: v_or_b32_e32 v0, v1, v0
749 ; GFX8-NEXT: v_or_b32_e32 v1, v8, v7
750 ; GFX8-NEXT: v_or_b32_e32 v4, v6, v5
751 ; GFX8-NEXT: v_cvt_f32_u32_e32 v3, v3
752 ; GFX8-NEXT: v_cvt_f32_u32_e32 v0, v0
753 ; GFX8-NEXT: v_cvt_f32_u32_e32 v1, v1
754 ; GFX8-NEXT: v_cvt_f32_u32_e32 v4, v4
755 ; GFX8-NEXT: v_sub_u32_e32 v2, vcc, 32, v11
756 ; GFX8-NEXT: v_sub_u32_e32 v11, vcc, 32, v12
757 ; GFX8-NEXT: v_sub_u32_e32 v12, vcc, 32, v13
758 ; GFX8-NEXT: v_ldexp_f32 v3, v3, v14
759 ; GFX8-NEXT: v_ldexp_f32 v0, v0, v2
760 ; GFX8-NEXT: v_ldexp_f32 v1, v1, v11
761 ; GFX8-NEXT: v_ldexp_f32 v2, v4, v12
762 ; GFX8-NEXT: v_cvt_f16_f32_sdwa v3, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
763 ; GFX8-NEXT: v_cvt_f16_f32_e32 v4, v0
764 ; GFX8-NEXT: v_cvt_f16_f32_sdwa v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
765 ; GFX8-NEXT: v_cvt_f16_f32_e32 v6, v2
766 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v9
767 ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v10, vcc
768 ; GFX8-NEXT: v_or_b32_e32 v2, v4, v3
769 ; GFX8-NEXT: v_or_b32_e32 v3, v6, v5
770 ; GFX8-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
771 ; GFX8-NEXT: s_endpgm
772 ;
773 ; GFX11-LABEL: v_uint_to_fp_v4i64_to_v4f16:
774 ; GFX11: ; %bb.0:
775 ; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
776 ; GFX11-NEXT: v_lshlrev_b32_e32 v5, 5, v0
777 ; GFX11-NEXT: s_waitcnt lgkmcnt(0)
778 ; GFX11-NEXT: s_clause 0x1
779 ; GFX11-NEXT: global_load_b128 v[1:4], v5, s[2:3] offset:16
780 ; GFX11-NEXT: global_load_b128 v[5:8], v5, s[2:3]
781 ; GFX11-NEXT: s_waitcnt vmcnt(1)
782 ; GFX11-NEXT: v_clz_i32_u32_e32 v9, v4
783 ; GFX11-NEXT: v_clz_i32_u32_e32 v10, v2
784 ; GFX11-NEXT: s_waitcnt vmcnt(0)
785 ; GFX11-NEXT: v_clz_i32_u32_e32 v11, v8
786 ; GFX11-NEXT: v_clz_i32_u32_e32 v12, v6
787 ; GFX11-NEXT: v_min_u32_e32 v9, 32, v9
788 ; GFX11-NEXT: v_min_u32_e32 v10, 32, v10
789 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
790 ; GFX11-NEXT: v_min_u32_e32 v11, 32, v11
791 ; GFX11-NEXT: v_min_u32_e32 v12, 32, v12
792 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
793 ; GFX11-NEXT: v_lshlrev_b64 v[3:4], v9, v[3:4]
794 ; GFX11-NEXT: v_lshlrev_b64 v[1:2], v10, v[1:2]
795 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
796 ; GFX11-NEXT: v_lshlrev_b64 v[7:8], v11, v[7:8]
797 ; GFX11-NEXT: v_lshlrev_b64 v[5:6], v12, v[5:6]
798 ; GFX11-NEXT: v_sub_nc_u32_e32 v9, 32, v9
799 ; GFX11-NEXT: v_sub_nc_u32_e32 v10, 32, v10
800 ; GFX11-NEXT: v_min_u32_e32 v3, 1, v3
801 ; GFX11-NEXT: v_min_u32_e32 v1, 1, v1
802 ; GFX11-NEXT: v_min_u32_e32 v7, 1, v7
803 ; GFX11-NEXT: v_min_u32_e32 v5, 1, v5
804 ; GFX11-NEXT: v_sub_nc_u32_e32 v11, 32, v11
805 ; GFX11-NEXT: v_or_b32_e32 v3, v4, v3
806 ; GFX11-NEXT: v_or_b32_e32 v1, v2, v1
807 ; GFX11-NEXT: v_or_b32_e32 v2, v8, v7
808 ; GFX11-NEXT: v_or_b32_e32 v4, v6, v5
809 ; GFX11-NEXT: v_sub_nc_u32_e32 v5, 32, v12
810 ; GFX11-NEXT: v_cvt_f32_u32_e32 v3, v3
811 ; GFX11-NEXT: v_cvt_f32_u32_e32 v1, v1
812 ; GFX11-NEXT: v_cvt_f32_u32_e32 v2, v2
813 ; GFX11-NEXT: v_cvt_f32_u32_e32 v4, v4
814 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
815 ; GFX11-NEXT: v_ldexp_f32 v3, v3, v9
816 ; GFX11-NEXT: v_ldexp_f32 v1, v1, v10
817 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
818 ; GFX11-NEXT: v_ldexp_f32 v2, v2, v11
819 ; GFX11-NEXT: v_ldexp_f32 v4, v4, v5
820 ; GFX11-NEXT: v_lshlrev_b32_e32 v5, 3, v0
821 ; GFX11-NEXT: v_cvt_f16_f32_e32 v3, v3
822 ; GFX11-NEXT: v_cvt_f16_f32_e32 v1, v1
823 ; GFX11-NEXT: v_cvt_f16_f32_e32 v2, v2
824 ; GFX11-NEXT: v_cvt_f16_f32_e32 v4, v4
825 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
826 ; GFX11-NEXT: v_pack_b32_f16 v1, v1, v3
827 ; GFX11-NEXT: v_pack_b32_f16 v0, v4, v2
828 ; GFX11-NEXT: global_store_b64 v5, v[0:1], s[0:1]
829 ; GFX11-NEXT: s_nop 0
830 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
831 ; GFX11-NEXT: s_endpgm
832 %tid = call i32 @llvm.amdgcn.workitem.id.x()
833 %in.gep = getelementptr <4 x i64>, ptr addrspace(1) %in, i32 %tid
834 %out.gep = getelementptr <4 x half>, ptr addrspace(1) %out, i32 %tid
835 %value = load <4 x i64>, ptr addrspace(1) %in.gep
836 %result = uitofp <4 x i64> %value to <4 x half>
837 store <4 x half> %result, ptr addrspace(1) %out.gep
838 ret void
839 }
841 declare i32 @llvm.amdgcn.workitem.id.x() #1
843 attributes #0 = { nounwind }
844 attributes #1 = { nounwind readnone }