| blob | 8673ce765a9476b81e82f8cd366d464a2bc5d166 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
2 ; RUN: llc -march=amdgcn -mcpu=gfx906 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX906 %s
3 declare float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32>, i32, i32, i32 immarg) #0
4 declare void @llvm.amdgcn.raw.buffer.store.f32(float, <4 x i32>, i32, i32, i32 immarg) #1
6 ; Check that the compiler doesn't crash with a "undefined physical register" error;
7 ; bb.0 sets SCC bit in s_cmp_eq_u32 s0, 1
8 ; bb.1 overrides it
9 ; bb.2 uses the value from bb.0
10 ; Preserve SCC across bb.1 with s_cselect_b32 s5, 1, 0 -> s_cmp_lg_u32 s5, 0
11 ; Otherwise, we will see the following error.
12 ;*** Bad machine code: Using an undefined physical register ***
13 ;- function: foo
14 ;- basic block: %bb.3 (0x53198c0)
15 ;- instruction: %33.sub1:sgpr_128 = S_CSELECT_B32 1072693248, 0, implicit $scc
16 ;- operand 3: implicit $scc
18 define amdgpu_kernel void @foo(i1 %cmp1) {
19 ; GFX906-LABEL: foo:
20 ; GFX906: ; %bb.0: ; %entry
21 ; GFX906-NEXT: s_mov_b32 s8, SCRATCH_RSRC_DWORD0
22 ; GFX906-NEXT: s_mov_b32 s9, SCRATCH_RSRC_DWORD1
23 ; GFX906-NEXT: s_mov_b32 s10, -1
24 ; GFX906-NEXT: s_mov_b32 s11, 0xe00000
25 ; GFX906-NEXT: s_add_u32 s8, s8, s3
26 ; GFX906-NEXT: s_addc_u32 s9, s9, 0
27 ; GFX906-NEXT: buffer_load_dword v3, off, s[8:11], 0
28 ; GFX906-NEXT: buffer_load_dword v4, off, s[8:11], 0 offset:4
29 ; GFX906-NEXT: buffer_load_dword v5, off, s[8:11], 0 offset:8
30 ; GFX906-NEXT: buffer_load_dword v6, off, s[8:11], 0 offset:12
31 ; GFX906-NEXT: s_load_dword s4, s[0:1], 0x24
32 ; GFX906-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x1c
33 ; GFX906-NEXT: s_waitcnt lgkmcnt(0)
34 ; GFX906-NEXT: s_bitcmp1_b32 s4, 0
35 ; GFX906-NEXT: s_mul_i32 s0, s2, s3
36 ; GFX906-NEXT: v_mul_u32_u24_e32 v1, s3, v1
37 ; GFX906-NEXT: v_mad_u32_u24 v0, s0, v0, v1
38 ; GFX906-NEXT: v_add_lshl_u32 v2, v0, v2, 4
39 ; GFX906-NEXT: v_mov_b32_e32 v0, 0
40 ; GFX906-NEXT: s_mov_b32 s4, 0
41 ; GFX906-NEXT: v_mov_b32_e32 v1, v0
42 ; GFX906-NEXT: s_cselect_b32 s5, 1, 0
43 ; GFX906-NEXT: s_mov_b64 s[2:3], exec
44 ; GFX906-NEXT: ds_write_b64 v2, v[0:1]
45 ; GFX906-NEXT: .LBB0_1: ; =>This Inner Loop Header: Depth=1
46 ; GFX906-NEXT: s_waitcnt vmcnt(3)
47 ; GFX906-NEXT: v_readfirstlane_b32 s0, v3
48 ; GFX906-NEXT: s_waitcnt vmcnt(2)
49 ; GFX906-NEXT: v_readfirstlane_b32 s1, v4
50 ; GFX906-NEXT: v_cmp_eq_u64_e32 vcc, s[0:1], v[3:4]
51 ; GFX906-NEXT: s_waitcnt vmcnt(1)
52 ; GFX906-NEXT: v_readfirstlane_b32 s0, v5
53 ; GFX906-NEXT: s_waitcnt vmcnt(0)
54 ; GFX906-NEXT: v_readfirstlane_b32 s1, v6
55 ; GFX906-NEXT: v_cmp_eq_u64_e64 s[0:1], s[0:1], v[5:6]
56 ; GFX906-NEXT: s_and_b64 s[0:1], vcc, s[0:1]
57 ; GFX906-NEXT: s_and_saveexec_b64 s[0:1], s[0:1]
58 ; GFX906-NEXT: ; implicit-def: $vgpr3_vgpr4_vgpr5_vgpr6
59 ; GFX906-NEXT: s_xor_b64 exec, exec, s[0:1]
60 ; GFX906-NEXT: s_cbranch_execnz .LBB0_1
61 ; GFX906-NEXT: ; %bb.2:
62 ; GFX906-NEXT: s_cmp_lg_u32 s5, 0
63 ; GFX906-NEXT: s_mov_b64 exec, s[2:3]
64 ; GFX906-NEXT: s_cselect_b32 s5, 0x3ff00000, 0
65 ; GFX906-NEXT: v_cvt_f32_f64_e32 v0, s[4:5]
66 ; GFX906-NEXT: s_mov_b32 s5, s4
67 ; GFX906-NEXT: s_mov_b32 s6, s4
68 ; GFX906-NEXT: s_mov_b32 s7, s4
69 ; GFX906-NEXT: buffer_store_dword v0, off, s[4:7], 0
70 ; GFX906-NEXT: s_endpgm
71 entry:
72 %wbr = alloca <4 x i32>, align 16, addrspace(5)
73 store ptr null, ptr addrspace(5) %wbr, align 16
74 %wbr_1 = load <4 x i32>, ptr addrspace(5) null, align 16
75 %call1 = tail call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %wbr_1, i32 0, i32 0, i32 0)
76 %0 = fpext float %call1 to double
77 %sel1 = select i1 %cmp1, double 1.000000e+00, double 0.000000e+00
78 %sel2 = select i1 %cmp1, double %0, double 0.000000e+00
79 %mul = fmul double %sel2, 0.000000e+00
80 %fptruncate = fptrunc double %sel1 to float
81 tail call void @llvm.amdgcn.raw.buffer.store.f32(float %fptruncate, <4 x i32> zeroinitializer, i32 0, i32 0, i32 0)
82 ret void
83 }