| blob | 87f7edb2b7132344e6d7bdd15c7f3bccffcdba63 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips2 | FileCheck %s \
3 ; RUN: -check-prefix=MIPS
4 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32 | FileCheck %s \
5 ; RUN: -check-prefix=MIPS
6 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r2 | FileCheck %s \
7 ; RUN: -check-prefix=MIPS32R2
8 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r3 | FileCheck %s \
9 ; RUN: -check-prefix=MIPS32R2
10 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r5 | FileCheck %s \
11 ; RUN: -check-prefix=MIPS32R2
12 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r6 | FileCheck %s \
13 ; RUN: -check-prefix=MIPS32R6
14 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips3 | FileCheck %s \
15 ; RUN: -check-prefix=MIPS64
16 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips4 | FileCheck %s \
17 ; RUN: -check-prefix=MIPS64
18 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64 | FileCheck %s \
19 ; RUN: -check-prefix=MIPS64
20 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r2 | FileCheck %s \
21 ; RUN: -check-prefix=MIPS64R2
22 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r3 | FileCheck %s \
23 ; RUN: -check-prefix=MIPS64R2
24 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r5 | FileCheck %s \
25 ; RUN: -check-prefix=MIPS64R2
26 ; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r6 | FileCheck %s \
27 ; RUN: -check-prefix=MIPS64R6
28 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \
29 ; RUN: -check-prefix=MM32R3
30 ; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
31 ; RUN: -check-prefix=MM32R6
33 define signext i1 @and_i1(i1 signext %a, i1 signext %b) {
34 ; MIPS-LABEL: and_i1:
35 ; MIPS: # %bb.0: # %entry
36 ; MIPS-NEXT: jr $ra
37 ; MIPS-NEXT: and $2, $4, $5
38 ;
39 ; MIPS32R2-LABEL: and_i1:
40 ; MIPS32R2: # %bb.0: # %entry
41 ; MIPS32R2-NEXT: jr $ra
42 ; MIPS32R2-NEXT: and $2, $4, $5
43 ;
44 ; MIPS32R6-LABEL: and_i1:
45 ; MIPS32R6: # %bb.0: # %entry
46 ; MIPS32R6-NEXT: jr $ra
47 ; MIPS32R6-NEXT: and $2, $4, $5
48 ;
49 ; MIPS64-LABEL: and_i1:
50 ; MIPS64: # %bb.0: # %entry
51 ; MIPS64-NEXT: and $1, $4, $5
52 ; MIPS64-NEXT: jr $ra
53 ; MIPS64-NEXT: sll $2, $1, 0
54 ;
55 ; MIPS64R2-LABEL: and_i1:
56 ; MIPS64R2: # %bb.0: # %entry
57 ; MIPS64R2-NEXT: and $1, $4, $5
58 ; MIPS64R2-NEXT: jr $ra
59 ; MIPS64R2-NEXT: sll $2, $1, 0
60 ;
61 ; MIPS64R6-LABEL: and_i1:
62 ; MIPS64R6: # %bb.0: # %entry
63 ; MIPS64R6-NEXT: and $1, $4, $5
64 ; MIPS64R6-NEXT: jr $ra
65 ; MIPS64R6-NEXT: sll $2, $1, 0
66 ;
67 ; MM32R3-LABEL: and_i1:
68 ; MM32R3: # %bb.0: # %entry
69 ; MM32R3-NEXT: and16 $4, $5
70 ; MM32R3-NEXT: move $2, $4
71 ; MM32R3-NEXT: jrc $ra
72 ;
73 ; MM32R6-LABEL: and_i1:
74 ; MM32R6: # %bb.0: # %entry
75 ; MM32R6-NEXT: and $2, $4, $5
76 ; MM32R6-NEXT: jrc $ra
77 entry:
78 %r = and i1 %a, %b
79 ret i1 %r
80 }
82 define signext i8 @and_i8(i8 signext %a, i8 signext %b) {
83 ; MIPS-LABEL: and_i8:
84 ; MIPS: # %bb.0: # %entry
85 ; MIPS-NEXT: jr $ra
86 ; MIPS-NEXT: and $2, $4, $5
87 ;
88 ; MIPS32R2-LABEL: and_i8:
89 ; MIPS32R2: # %bb.0: # %entry
90 ; MIPS32R2-NEXT: jr $ra
91 ; MIPS32R2-NEXT: and $2, $4, $5
92 ;
93 ; MIPS32R6-LABEL: and_i8:
94 ; MIPS32R6: # %bb.0: # %entry
95 ; MIPS32R6-NEXT: jr $ra
96 ; MIPS32R6-NEXT: and $2, $4, $5
97 ;
98 ; MIPS64-LABEL: and_i8:
99 ; MIPS64: # %bb.0: # %entry
100 ; MIPS64-NEXT: and $1, $4, $5
101 ; MIPS64-NEXT: jr $ra
102 ; MIPS64-NEXT: sll $2, $1, 0
103 ;
104 ; MIPS64R2-LABEL: and_i8:
105 ; MIPS64R2: # %bb.0: # %entry
106 ; MIPS64R2-NEXT: and $1, $4, $5
107 ; MIPS64R2-NEXT: jr $ra
108 ; MIPS64R2-NEXT: sll $2, $1, 0
109 ;
110 ; MIPS64R6-LABEL: and_i8:
111 ; MIPS64R6: # %bb.0: # %entry
112 ; MIPS64R6-NEXT: and $1, $4, $5
113 ; MIPS64R6-NEXT: jr $ra
114 ; MIPS64R6-NEXT: sll $2, $1, 0
115 ;
116 ; MM32R3-LABEL: and_i8:
117 ; MM32R3: # %bb.0: # %entry
118 ; MM32R3-NEXT: and16 $4, $5
119 ; MM32R3-NEXT: move $2, $4
120 ; MM32R3-NEXT: jrc $ra
121 ;
122 ; MM32R6-LABEL: and_i8:
123 ; MM32R6: # %bb.0: # %entry
124 ; MM32R6-NEXT: and $2, $4, $5
125 ; MM32R6-NEXT: jrc $ra
126 entry:
127 %r = and i8 %a, %b
128 ret i8 %r
129 }
131 define signext i16 @and_i16(i16 signext %a, i16 signext %b) {
132 ; MIPS-LABEL: and_i16:
133 ; MIPS: # %bb.0: # %entry
134 ; MIPS-NEXT: jr $ra
135 ; MIPS-NEXT: and $2, $4, $5
136 ;
137 ; MIPS32R2-LABEL: and_i16:
138 ; MIPS32R2: # %bb.0: # %entry
139 ; MIPS32R2-NEXT: jr $ra
140 ; MIPS32R2-NEXT: and $2, $4, $5
141 ;
142 ; MIPS32R6-LABEL: and_i16:
143 ; MIPS32R6: # %bb.0: # %entry
144 ; MIPS32R6-NEXT: jr $ra
145 ; MIPS32R6-NEXT: and $2, $4, $5
146 ;
147 ; MIPS64-LABEL: and_i16:
148 ; MIPS64: # %bb.0: # %entry
149 ; MIPS64-NEXT: and $1, $4, $5
150 ; MIPS64-NEXT: jr $ra
151 ; MIPS64-NEXT: sll $2, $1, 0
152 ;
153 ; MIPS64R2-LABEL: and_i16:
154 ; MIPS64R2: # %bb.0: # %entry
155 ; MIPS64R2-NEXT: and $1, $4, $5
156 ; MIPS64R2-NEXT: jr $ra
157 ; MIPS64R2-NEXT: sll $2, $1, 0
158 ;
159 ; MIPS64R6-LABEL: and_i16:
160 ; MIPS64R6: # %bb.0: # %entry
161 ; MIPS64R6-NEXT: and $1, $4, $5
162 ; MIPS64R6-NEXT: jr $ra
163 ; MIPS64R6-NEXT: sll $2, $1, 0
164 ;
165 ; MM32R3-LABEL: and_i16:
166 ; MM32R3: # %bb.0: # %entry
167 ; MM32R3-NEXT: and16 $4, $5
168 ; MM32R3-NEXT: move $2, $4
169 ; MM32R3-NEXT: jrc $ra
170 ;
171 ; MM32R6-LABEL: and_i16:
172 ; MM32R6: # %bb.0: # %entry
173 ; MM32R6-NEXT: and $2, $4, $5
174 ; MM32R6-NEXT: jrc $ra
175 entry:
176 %r = and i16 %a, %b
177 ret i16 %r
178 }
180 define signext i32 @and_i32(i32 signext %a, i32 signext %b) {
181 ; MIPS-LABEL: and_i32:
182 ; MIPS: # %bb.0: # %entry
183 ; MIPS-NEXT: jr $ra
184 ; MIPS-NEXT: and $2, $4, $5
185 ;
186 ; MIPS32R2-LABEL: and_i32:
187 ; MIPS32R2: # %bb.0: # %entry
188 ; MIPS32R2-NEXT: jr $ra
189 ; MIPS32R2-NEXT: and $2, $4, $5
190 ;
191 ; MIPS32R6-LABEL: and_i32:
192 ; MIPS32R6: # %bb.0: # %entry
193 ; MIPS32R6-NEXT: jr $ra
194 ; MIPS32R6-NEXT: and $2, $4, $5
195 ;
196 ; MIPS64-LABEL: and_i32:
197 ; MIPS64: # %bb.0: # %entry
198 ; MIPS64-NEXT: jr $ra
199 ; MIPS64-NEXT: and $2, $4, $5
200 ;
201 ; MIPS64R2-LABEL: and_i32:
202 ; MIPS64R2: # %bb.0: # %entry
203 ; MIPS64R2-NEXT: jr $ra
204 ; MIPS64R2-NEXT: and $2, $4, $5
205 ;
206 ; MIPS64R6-LABEL: and_i32:
207 ; MIPS64R6: # %bb.0: # %entry
208 ; MIPS64R6-NEXT: jr $ra
209 ; MIPS64R6-NEXT: and $2, $4, $5
210 ;
211 ; MM32R3-LABEL: and_i32:
212 ; MM32R3: # %bb.0: # %entry
213 ; MM32R3-NEXT: and16 $4, $5
214 ; MM32R3-NEXT: move $2, $4
215 ; MM32R3-NEXT: jrc $ra
216 ;
217 ; MM32R6-LABEL: and_i32:
218 ; MM32R6: # %bb.0: # %entry
219 ; MM32R6-NEXT: and $2, $4, $5
220 ; MM32R6-NEXT: jrc $ra
221 entry:
222 %r = and i32 %a, %b
223 ret i32 %r
224 }
226 define signext i64 @and_i64(i64 signext %a, i64 signext %b) {
227 ; MIPS-LABEL: and_i64:
228 ; MIPS: # %bb.0: # %entry
229 ; MIPS-NEXT: and $2, $4, $6
230 ; MIPS-NEXT: jr $ra
231 ; MIPS-NEXT: and $3, $5, $7
232 ;
233 ; MIPS32R2-LABEL: and_i64:
234 ; MIPS32R2: # %bb.0: # %entry
235 ; MIPS32R2-NEXT: and $2, $4, $6
236 ; MIPS32R2-NEXT: jr $ra
237 ; MIPS32R2-NEXT: and $3, $5, $7
238 ;
239 ; MIPS32R6-LABEL: and_i64:
240 ; MIPS32R6: # %bb.0: # %entry
241 ; MIPS32R6-NEXT: and $2, $4, $6
242 ; MIPS32R6-NEXT: jr $ra
243 ; MIPS32R6-NEXT: and $3, $5, $7
244 ;
245 ; MIPS64-LABEL: and_i64:
246 ; MIPS64: # %bb.0: # %entry
247 ; MIPS64-NEXT: jr $ra
248 ; MIPS64-NEXT: and $2, $4, $5
249 ;
250 ; MIPS64R2-LABEL: and_i64:
251 ; MIPS64R2: # %bb.0: # %entry
252 ; MIPS64R2-NEXT: jr $ra
253 ; MIPS64R2-NEXT: and $2, $4, $5
254 ;
255 ; MIPS64R6-LABEL: and_i64:
256 ; MIPS64R6: # %bb.0: # %entry
257 ; MIPS64R6-NEXT: jr $ra
258 ; MIPS64R6-NEXT: and $2, $4, $5
259 ;
260 ; MM32R3-LABEL: and_i64:
261 ; MM32R3: # %bb.0: # %entry
262 ; MM32R3-NEXT: and16 $4, $6
263 ; MM32R3-NEXT: and16 $5, $7
264 ; MM32R3-NEXT: move $2, $4
265 ; MM32R3-NEXT: move $3, $5
266 ; MM32R3-NEXT: jrc $ra
267 ;
268 ; MM32R6-LABEL: and_i64:
269 ; MM32R6: # %bb.0: # %entry
270 ; MM32R6-NEXT: and $2, $4, $6
271 ; MM32R6-NEXT: and $3, $5, $7
272 ; MM32R6-NEXT: jrc $ra
273 entry:
274 %r = and i64 %a, %b
275 ret i64 %r
276 }
278 define signext i128 @and_i128(i128 signext %a, i128 signext %b) {
279 ; MIPS-LABEL: and_i128:
280 ; MIPS: # %bb.0: # %entry
281 ; MIPS-NEXT: lw $1, 20($sp)
282 ; MIPS-NEXT: lw $2, 16($sp)
283 ; MIPS-NEXT: and $2, $4, $2
284 ; MIPS-NEXT: and $3, $5, $1
285 ; MIPS-NEXT: lw $1, 24($sp)
286 ; MIPS-NEXT: and $4, $6, $1
287 ; MIPS-NEXT: lw $1, 28($sp)
288 ; MIPS-NEXT: jr $ra
289 ; MIPS-NEXT: and $5, $7, $1
290 ;
291 ; MIPS32R2-LABEL: and_i128:
292 ; MIPS32R2: # %bb.0: # %entry
293 ; MIPS32R2-NEXT: lw $1, 20($sp)
294 ; MIPS32R2-NEXT: lw $2, 16($sp)
295 ; MIPS32R2-NEXT: and $2, $4, $2
296 ; MIPS32R2-NEXT: and $3, $5, $1
297 ; MIPS32R2-NEXT: lw $1, 24($sp)
298 ; MIPS32R2-NEXT: and $4, $6, $1
299 ; MIPS32R2-NEXT: lw $1, 28($sp)
300 ; MIPS32R2-NEXT: jr $ra
301 ; MIPS32R2-NEXT: and $5, $7, $1
302 ;
303 ; MIPS32R6-LABEL: and_i128:
304 ; MIPS32R6: # %bb.0: # %entry
305 ; MIPS32R6-NEXT: lw $1, 20($sp)
306 ; MIPS32R6-NEXT: lw $2, 16($sp)
307 ; MIPS32R6-NEXT: and $2, $4, $2
308 ; MIPS32R6-NEXT: and $3, $5, $1
309 ; MIPS32R6-NEXT: lw $1, 24($sp)
310 ; MIPS32R6-NEXT: and $4, $6, $1
311 ; MIPS32R6-NEXT: lw $1, 28($sp)
312 ; MIPS32R6-NEXT: jr $ra
313 ; MIPS32R6-NEXT: and $5, $7, $1
314 ;
315 ; MIPS64-LABEL: and_i128:
316 ; MIPS64: # %bb.0: # %entry
317 ; MIPS64-NEXT: and $2, $4, $6
318 ; MIPS64-NEXT: jr $ra
319 ; MIPS64-NEXT: and $3, $5, $7
320 ;
321 ; MIPS64R2-LABEL: and_i128:
322 ; MIPS64R2: # %bb.0: # %entry
323 ; MIPS64R2-NEXT: and $2, $4, $6
324 ; MIPS64R2-NEXT: jr $ra
325 ; MIPS64R2-NEXT: and $3, $5, $7
326 ;
327 ; MIPS64R6-LABEL: and_i128:
328 ; MIPS64R6: # %bb.0: # %entry
329 ; MIPS64R6-NEXT: and $2, $4, $6
330 ; MIPS64R6-NEXT: jr $ra
331 ; MIPS64R6-NEXT: and $3, $5, $7
332 ;
333 ; MM32R3-LABEL: and_i128:
334 ; MM32R3: # %bb.0: # %entry
335 ; MM32R3-NEXT: lwp $2, 16($sp)
336 ; MM32R3-NEXT: and16 $2, $4
337 ; MM32R3-NEXT: and16 $3, $5
338 ; MM32R3-NEXT: lw $4, 24($sp)
339 ; MM32R3-NEXT: and16 $4, $6
340 ; MM32R3-NEXT: lw $5, 28($sp)
341 ; MM32R3-NEXT: and16 $5, $7
342 ; MM32R3-NEXT: jrc $ra
343 ;
344 ; MM32R6-LABEL: and_i128:
345 ; MM32R6: # %bb.0: # %entry
346 ; MM32R6-NEXT: lw $1, 20($sp)
347 ; MM32R6-NEXT: lw $2, 16($sp)
348 ; MM32R6-NEXT: and $2, $4, $2
349 ; MM32R6-NEXT: and $3, $5, $1
350 ; MM32R6-NEXT: lw $1, 24($sp)
351 ; MM32R6-NEXT: and $4, $6, $1
352 ; MM32R6-NEXT: lw $1, 28($sp)
353 ; MM32R6-NEXT: and $5, $7, $1
354 ; MM32R6-NEXT: jrc $ra
355 entry:
356 %r = and i128 %a, %b
357 ret i128 %r
358 }
360 define signext i1 @and_i1_4(i1 signext %b) {
361 ; MIPS-LABEL: and_i1_4:
362 ; MIPS: # %bb.0: # %entry
363 ; MIPS-NEXT: jr $ra
364 ; MIPS-NEXT: addiu $2, $zero, 0
365 ;
366 ; MIPS32R2-LABEL: and_i1_4:
367 ; MIPS32R2: # %bb.0: # %entry
368 ; MIPS32R2-NEXT: jr $ra
369 ; MIPS32R2-NEXT: addiu $2, $zero, 0
370 ;
371 ; MIPS32R6-LABEL: and_i1_4:
372 ; MIPS32R6: # %bb.0: # %entry
373 ; MIPS32R6-NEXT: jr $ra
374 ; MIPS32R6-NEXT: addiu $2, $zero, 0
375 ;
376 ; MIPS64-LABEL: and_i1_4:
377 ; MIPS64: # %bb.0: # %entry
378 ; MIPS64-NEXT: jr $ra
379 ; MIPS64-NEXT: addiu $2, $zero, 0
380 ;
381 ; MIPS64R2-LABEL: and_i1_4:
382 ; MIPS64R2: # %bb.0: # %entry
383 ; MIPS64R2-NEXT: jr $ra
384 ; MIPS64R2-NEXT: addiu $2, $zero, 0
385 ;
386 ; MIPS64R6-LABEL: and_i1_4:
387 ; MIPS64R6: # %bb.0: # %entry
388 ; MIPS64R6-NEXT: jr $ra
389 ; MIPS64R6-NEXT: addiu $2, $zero, 0
390 ;
391 ; MM32R3-LABEL: and_i1_4:
392 ; MM32R3: # %bb.0: # %entry
393 ; MM32R3-NEXT: li16 $2, 0
394 ; MM32R3-NEXT: jrc $ra
395 ;
396 ; MM32R6-LABEL: and_i1_4:
397 ; MM32R6: # %bb.0: # %entry
398 ; MM32R6-NEXT: li16 $2, 0
399 ; MM32R6-NEXT: jrc $ra
400 entry:
401 %r = and i1 4, %b
402 ret i1 %r
403 }
405 define signext i8 @and_i8_4(i8 signext %b) {
406 ; MIPS-LABEL: and_i8_4:
407 ; MIPS: # %bb.0: # %entry
408 ; MIPS-NEXT: jr $ra
409 ; MIPS-NEXT: andi $2, $4, 4
410 ;
411 ; MIPS32R2-LABEL: and_i8_4:
412 ; MIPS32R2: # %bb.0: # %entry
413 ; MIPS32R2-NEXT: jr $ra
414 ; MIPS32R2-NEXT: andi $2, $4, 4
415 ;
416 ; MIPS32R6-LABEL: and_i8_4:
417 ; MIPS32R6: # %bb.0: # %entry
418 ; MIPS32R6-NEXT: jr $ra
419 ; MIPS32R6-NEXT: andi $2, $4, 4
420 ;
421 ; MIPS64-LABEL: and_i8_4:
422 ; MIPS64: # %bb.0: # %entry
423 ; MIPS64-NEXT: jr $ra
424 ; MIPS64-NEXT: andi $2, $4, 4
425 ;
426 ; MIPS64R2-LABEL: and_i8_4:
427 ; MIPS64R2: # %bb.0: # %entry
428 ; MIPS64R2-NEXT: jr $ra
429 ; MIPS64R2-NEXT: andi $2, $4, 4
430 ;
431 ; MIPS64R6-LABEL: and_i8_4:
432 ; MIPS64R6: # %bb.0: # %entry
433 ; MIPS64R6-NEXT: jr $ra
434 ; MIPS64R6-NEXT: andi $2, $4, 4
435 ;
436 ; MM32R3-LABEL: and_i8_4:
437 ; MM32R3: # %bb.0: # %entry
438 ; MM32R3-NEXT: andi16 $2, $4, 4
439 ; MM32R3-NEXT: jrc $ra
440 ;
441 ; MM32R6-LABEL: and_i8_4:
442 ; MM32R6: # %bb.0: # %entry
443 ; MM32R6-NEXT: andi16 $2, $4, 4
444 ; MM32R6-NEXT: jrc $ra
445 entry:
446 %r = and i8 4, %b
447 ret i8 %r
448 }
450 define signext i16 @and_i16_4(i16 signext %b) {
451 ; MIPS-LABEL: and_i16_4:
452 ; MIPS: # %bb.0: # %entry
453 ; MIPS-NEXT: jr $ra
454 ; MIPS-NEXT: andi $2, $4, 4
455 ;
456 ; MIPS32R2-LABEL: and_i16_4:
457 ; MIPS32R2: # %bb.0: # %entry
458 ; MIPS32R2-NEXT: jr $ra
459 ; MIPS32R2-NEXT: andi $2, $4, 4
460 ;
461 ; MIPS32R6-LABEL: and_i16_4:
462 ; MIPS32R6: # %bb.0: # %entry
463 ; MIPS32R6-NEXT: jr $ra
464 ; MIPS32R6-NEXT: andi $2, $4, 4
465 ;
466 ; MIPS64-LABEL: and_i16_4:
467 ; MIPS64: # %bb.0: # %entry
468 ; MIPS64-NEXT: jr $ra
469 ; MIPS64-NEXT: andi $2, $4, 4
470 ;
471 ; MIPS64R2-LABEL: and_i16_4:
472 ; MIPS64R2: # %bb.0: # %entry
473 ; MIPS64R2-NEXT: jr $ra
474 ; MIPS64R2-NEXT: andi $2, $4, 4
475 ;
476 ; MIPS64R6-LABEL: and_i16_4:
477 ; MIPS64R6: # %bb.0: # %entry
478 ; MIPS64R6-NEXT: jr $ra
479 ; MIPS64R6-NEXT: andi $2, $4, 4
480 ;
481 ; MM32R3-LABEL: and_i16_4:
482 ; MM32R3: # %bb.0: # %entry
483 ; MM32R3-NEXT: andi16 $2, $4, 4
484 ; MM32R3-NEXT: jrc $ra
485 ;
486 ; MM32R6-LABEL: and_i16_4:
487 ; MM32R6: # %bb.0: # %entry
488 ; MM32R6-NEXT: andi16 $2, $4, 4
489 ; MM32R6-NEXT: jrc $ra
490 entry:
491 %r = and i16 4, %b
492 ret i16 %r
493 }
495 define signext i32 @and_i32_4(i32 signext %b) {
496 ; MIPS-LABEL: and_i32_4:
497 ; MIPS: # %bb.0: # %entry
498 ; MIPS-NEXT: jr $ra
499 ; MIPS-NEXT: andi $2, $4, 4
500 ;
501 ; MIPS32R2-LABEL: and_i32_4:
502 ; MIPS32R2: # %bb.0: # %entry
503 ; MIPS32R2-NEXT: jr $ra
504 ; MIPS32R2-NEXT: andi $2, $4, 4
505 ;
506 ; MIPS32R6-LABEL: and_i32_4:
507 ; MIPS32R6: # %bb.0: # %entry
508 ; MIPS32R6-NEXT: jr $ra
509 ; MIPS32R6-NEXT: andi $2, $4, 4
510 ;
511 ; MIPS64-LABEL: and_i32_4:
512 ; MIPS64: # %bb.0: # %entry
513 ; MIPS64-NEXT: jr $ra
514 ; MIPS64-NEXT: andi $2, $4, 4
515 ;
516 ; MIPS64R2-LABEL: and_i32_4:
517 ; MIPS64R2: # %bb.0: # %entry
518 ; MIPS64R2-NEXT: jr $ra
519 ; MIPS64R2-NEXT: andi $2, $4, 4
520 ;
521 ; MIPS64R6-LABEL: and_i32_4:
522 ; MIPS64R6: # %bb.0: # %entry
523 ; MIPS64R6-NEXT: jr $ra
524 ; MIPS64R6-NEXT: andi $2, $4, 4
525 ;
526 ; MM32R3-LABEL: and_i32_4:
527 ; MM32R3: # %bb.0: # %entry
528 ; MM32R3-NEXT: andi16 $2, $4, 4
529 ; MM32R3-NEXT: jrc $ra
530 ;
531 ; MM32R6-LABEL: and_i32_4:
532 ; MM32R6: # %bb.0: # %entry
533 ; MM32R6-NEXT: andi16 $2, $4, 4
534 ; MM32R6-NEXT: jrc $ra
535 entry:
536 %r = and i32 4, %b
537 ret i32 %r
538 }
540 define signext i64 @and_i64_4(i64 signext %b) {
541 ; MIPS-LABEL: and_i64_4:
542 ; MIPS: # %bb.0: # %entry
543 ; MIPS-NEXT: andi $3, $5, 4
544 ; MIPS-NEXT: jr $ra
545 ; MIPS-NEXT: addiu $2, $zero, 0
546 ;
547 ; MIPS32R2-LABEL: and_i64_4:
548 ; MIPS32R2: # %bb.0: # %entry
549 ; MIPS32R2-NEXT: andi $3, $5, 4
550 ; MIPS32R2-NEXT: jr $ra
551 ; MIPS32R2-NEXT: addiu $2, $zero, 0
552 ;
553 ; MIPS32R6-LABEL: and_i64_4:
554 ; MIPS32R6: # %bb.0: # %entry
555 ; MIPS32R6-NEXT: andi $3, $5, 4
556 ; MIPS32R6-NEXT: jr $ra
557 ; MIPS32R6-NEXT: addiu $2, $zero, 0
558 ;
559 ; MIPS64-LABEL: and_i64_4:
560 ; MIPS64: # %bb.0: # %entry
561 ; MIPS64-NEXT: jr $ra
562 ; MIPS64-NEXT: andi $2, $4, 4
563 ;
564 ; MIPS64R2-LABEL: and_i64_4:
565 ; MIPS64R2: # %bb.0: # %entry
566 ; MIPS64R2-NEXT: jr $ra
567 ; MIPS64R2-NEXT: andi $2, $4, 4
568 ;
569 ; MIPS64R6-LABEL: and_i64_4:
570 ; MIPS64R6: # %bb.0: # %entry
571 ; MIPS64R6-NEXT: jr $ra
572 ; MIPS64R6-NEXT: andi $2, $4, 4
573 ;
574 ; MM32R3-LABEL: and_i64_4:
575 ; MM32R3: # %bb.0: # %entry
576 ; MM32R3-NEXT: andi16 $3, $5, 4
577 ; MM32R3-NEXT: li16 $2, 0
578 ; MM32R3-NEXT: jrc $ra
579 ;
580 ; MM32R6-LABEL: and_i64_4:
581 ; MM32R6: # %bb.0: # %entry
582 ; MM32R6-NEXT: andi16 $3, $5, 4
583 ; MM32R6-NEXT: li16 $2, 0
584 ; MM32R6-NEXT: jrc $ra
585 entry:
586 %r = and i64 4, %b
587 ret i64 %r
588 }
590 define signext i128 @and_i128_4(i128 signext %b) {
591 ; MIPS-LABEL: and_i128_4:
592 ; MIPS: # %bb.0: # %entry
593 ; MIPS-NEXT: andi $5, $7, 4
594 ; MIPS-NEXT: addiu $2, $zero, 0
595 ; MIPS-NEXT: addiu $3, $zero, 0
596 ; MIPS-NEXT: jr $ra
597 ; MIPS-NEXT: addiu $4, $zero, 0
598 ;
599 ; MIPS32R2-LABEL: and_i128_4:
600 ; MIPS32R2: # %bb.0: # %entry
601 ; MIPS32R2-NEXT: andi $5, $7, 4
602 ; MIPS32R2-NEXT: addiu $2, $zero, 0
603 ; MIPS32R2-NEXT: addiu $3, $zero, 0
604 ; MIPS32R2-NEXT: jr $ra
605 ; MIPS32R2-NEXT: addiu $4, $zero, 0
606 ;
607 ; MIPS32R6-LABEL: and_i128_4:
608 ; MIPS32R6: # %bb.0: # %entry
609 ; MIPS32R6-NEXT: andi $5, $7, 4
610 ; MIPS32R6-NEXT: addiu $2, $zero, 0
611 ; MIPS32R6-NEXT: addiu $3, $zero, 0
612 ; MIPS32R6-NEXT: jr $ra
613 ; MIPS32R6-NEXT: addiu $4, $zero, 0
614 ;
615 ; MIPS64-LABEL: and_i128_4:
616 ; MIPS64: # %bb.0: # %entry
617 ; MIPS64-NEXT: andi $3, $5, 4
618 ; MIPS64-NEXT: jr $ra
619 ; MIPS64-NEXT: daddiu $2, $zero, 0
620 ;
621 ; MIPS64R2-LABEL: and_i128_4:
622 ; MIPS64R2: # %bb.0: # %entry
623 ; MIPS64R2-NEXT: andi $3, $5, 4
624 ; MIPS64R2-NEXT: jr $ra
625 ; MIPS64R2-NEXT: daddiu $2, $zero, 0
626 ;
627 ; MIPS64R6-LABEL: and_i128_4:
628 ; MIPS64R6: # %bb.0: # %entry
629 ; MIPS64R6-NEXT: andi $3, $5, 4
630 ; MIPS64R6-NEXT: jr $ra
631 ; MIPS64R6-NEXT: daddiu $2, $zero, 0
632 ;
633 ; MM32R3-LABEL: and_i128_4:
634 ; MM32R3: # %bb.0: # %entry
635 ; MM32R3-NEXT: andi16 $5, $7, 4
636 ; MM32R3-NEXT: li16 $2, 0
637 ; MM32R3-NEXT: li16 $3, 0
638 ; MM32R3-NEXT: li16 $4, 0
639 ; MM32R3-NEXT: jrc $ra
640 ;
641 ; MM32R6-LABEL: and_i128_4:
642 ; MM32R6: # %bb.0: # %entry
643 ; MM32R6-NEXT: andi16 $5, $7, 4
644 ; MM32R6-NEXT: li16 $2, 0
645 ; MM32R6-NEXT: li16 $3, 0
646 ; MM32R6-NEXT: li16 $4, 0
647 ; MM32R6-NEXT: jrc $ra
648 entry:
649 %r = and i128 4, %b
650 ret i128 %r
651 }
653 define signext i1 @and_i1_31(i1 signext %b) {
654 ; MIPS-LABEL: and_i1_31:
655 ; MIPS: # %bb.0: # %entry
656 ; MIPS-NEXT: jr $ra
657 ; MIPS-NEXT: move $2, $4
658 ;
659 ; MIPS32R2-LABEL: and_i1_31:
660 ; MIPS32R2: # %bb.0: # %entry
661 ; MIPS32R2-NEXT: jr $ra
662 ; MIPS32R2-NEXT: move $2, $4
663 ;
664 ; MIPS32R6-LABEL: and_i1_31:
665 ; MIPS32R6: # %bb.0: # %entry
666 ; MIPS32R6-NEXT: jr $ra
667 ; MIPS32R6-NEXT: move $2, $4
668 ;
669 ; MIPS64-LABEL: and_i1_31:
670 ; MIPS64: # %bb.0: # %entry
671 ; MIPS64-NEXT: jr $ra
672 ; MIPS64-NEXT: move $2, $4
673 ;
674 ; MIPS64R2-LABEL: and_i1_31:
675 ; MIPS64R2: # %bb.0: # %entry
676 ; MIPS64R2-NEXT: jr $ra
677 ; MIPS64R2-NEXT: move $2, $4
678 ;
679 ; MIPS64R6-LABEL: and_i1_31:
680 ; MIPS64R6: # %bb.0: # %entry
681 ; MIPS64R6-NEXT: jr $ra
682 ; MIPS64R6-NEXT: move $2, $4
683 ;
684 ; MM32R3-LABEL: and_i1_31:
685 ; MM32R3: # %bb.0: # %entry
686 ; MM32R3-NEXT: move $2, $4
687 ; MM32R3-NEXT: jrc $ra
688 ;
689 ; MM32R6-LABEL: and_i1_31:
690 ; MM32R6: # %bb.0: # %entry
691 ; MM32R6-NEXT: move $2, $4
692 ; MM32R6-NEXT: jrc $ra
693 entry:
694 %r = and i1 31, %b
695 ret i1 %r
696 }
698 define signext i8 @and_i8_31(i8 signext %b) {
699 ; MIPS-LABEL: and_i8_31:
700 ; MIPS: # %bb.0: # %entry
701 ; MIPS-NEXT: jr $ra
702 ; MIPS-NEXT: andi $2, $4, 31
703 ;
704 ; MIPS32R2-LABEL: and_i8_31:
705 ; MIPS32R2: # %bb.0: # %entry
706 ; MIPS32R2-NEXT: jr $ra
707 ; MIPS32R2-NEXT: andi $2, $4, 31
708 ;
709 ; MIPS32R6-LABEL: and_i8_31:
710 ; MIPS32R6: # %bb.0: # %entry
711 ; MIPS32R6-NEXT: jr $ra
712 ; MIPS32R6-NEXT: andi $2, $4, 31
713 ;
714 ; MIPS64-LABEL: and_i8_31:
715 ; MIPS64: # %bb.0: # %entry
716 ; MIPS64-NEXT: jr $ra
717 ; MIPS64-NEXT: andi $2, $4, 31
718 ;
719 ; MIPS64R2-LABEL: and_i8_31:
720 ; MIPS64R2: # %bb.0: # %entry
721 ; MIPS64R2-NEXT: jr $ra
722 ; MIPS64R2-NEXT: andi $2, $4, 31
723 ;
724 ; MIPS64R6-LABEL: and_i8_31:
725 ; MIPS64R6: # %bb.0: # %entry
726 ; MIPS64R6-NEXT: jr $ra
727 ; MIPS64R6-NEXT: andi $2, $4, 31
728 ;
729 ; MM32R3-LABEL: and_i8_31:
730 ; MM32R3: # %bb.0: # %entry
731 ; MM32R3-NEXT: andi16 $2, $4, 31
732 ; MM32R3-NEXT: jrc $ra
733 ;
734 ; MM32R6-LABEL: and_i8_31:
735 ; MM32R6: # %bb.0: # %entry
736 ; MM32R6-NEXT: andi16 $2, $4, 31
737 ; MM32R6-NEXT: jrc $ra
738 entry:
739 %r = and i8 31, %b
740 ret i8 %r
741 }
743 define signext i16 @and_i16_31(i16 signext %b) {
744 ; MIPS-LABEL: and_i16_31:
745 ; MIPS: # %bb.0: # %entry
746 ; MIPS-NEXT: jr $ra
747 ; MIPS-NEXT: andi $2, $4, 31
748 ;
749 ; MIPS32R2-LABEL: and_i16_31:
750 ; MIPS32R2: # %bb.0: # %entry
751 ; MIPS32R2-NEXT: jr $ra
752 ; MIPS32R2-NEXT: andi $2, $4, 31
753 ;
754 ; MIPS32R6-LABEL: and_i16_31:
755 ; MIPS32R6: # %bb.0: # %entry
756 ; MIPS32R6-NEXT: jr $ra
757 ; MIPS32R6-NEXT: andi $2, $4, 31
758 ;
759 ; MIPS64-LABEL: and_i16_31:
760 ; MIPS64: # %bb.0: # %entry
761 ; MIPS64-NEXT: jr $ra
762 ; MIPS64-NEXT: andi $2, $4, 31
763 ;
764 ; MIPS64R2-LABEL: and_i16_31:
765 ; MIPS64R2: # %bb.0: # %entry
766 ; MIPS64R2-NEXT: jr $ra
767 ; MIPS64R2-NEXT: andi $2, $4, 31
768 ;
769 ; MIPS64R6-LABEL: and_i16_31:
770 ; MIPS64R6: # %bb.0: # %entry
771 ; MIPS64R6-NEXT: jr $ra
772 ; MIPS64R6-NEXT: andi $2, $4, 31
773 ;
774 ; MM32R3-LABEL: and_i16_31:
775 ; MM32R3: # %bb.0: # %entry
776 ; MM32R3-NEXT: andi16 $2, $4, 31
777 ; MM32R3-NEXT: jrc $ra
778 ;
779 ; MM32R6-LABEL: and_i16_31:
780 ; MM32R6: # %bb.0: # %entry
781 ; MM32R6-NEXT: andi16 $2, $4, 31
782 ; MM32R6-NEXT: jrc $ra
783 entry:
784 %r = and i16 31, %b
785 ret i16 %r
786 }
788 define signext i32 @and_i32_31(i32 signext %b) {
789 ; MIPS-LABEL: and_i32_31:
790 ; MIPS: # %bb.0: # %entry
791 ; MIPS-NEXT: jr $ra
792 ; MIPS-NEXT: andi $2, $4, 31
793 ;
794 ; MIPS32R2-LABEL: and_i32_31:
795 ; MIPS32R2: # %bb.0: # %entry
796 ; MIPS32R2-NEXT: jr $ra
797 ; MIPS32R2-NEXT: andi $2, $4, 31
798 ;
799 ; MIPS32R6-LABEL: and_i32_31:
800 ; MIPS32R6: # %bb.0: # %entry
801 ; MIPS32R6-NEXT: jr $ra
802 ; MIPS32R6-NEXT: andi $2, $4, 31
803 ;
804 ; MIPS64-LABEL: and_i32_31:
805 ; MIPS64: # %bb.0: # %entry
806 ; MIPS64-NEXT: jr $ra
807 ; MIPS64-NEXT: andi $2, $4, 31
808 ;
809 ; MIPS64R2-LABEL: and_i32_31:
810 ; MIPS64R2: # %bb.0: # %entry
811 ; MIPS64R2-NEXT: jr $ra
812 ; MIPS64R2-NEXT: andi $2, $4, 31
813 ;
814 ; MIPS64R6-LABEL: and_i32_31:
815 ; MIPS64R6: # %bb.0: # %entry
816 ; MIPS64R6-NEXT: jr $ra
817 ; MIPS64R6-NEXT: andi $2, $4, 31
818 ;
819 ; MM32R3-LABEL: and_i32_31:
820 ; MM32R3: # %bb.0: # %entry
821 ; MM32R3-NEXT: andi16 $2, $4, 31
822 ; MM32R3-NEXT: jrc $ra
823 ;
824 ; MM32R6-LABEL: and_i32_31:
825 ; MM32R6: # %bb.0: # %entry
826 ; MM32R6-NEXT: andi16 $2, $4, 31
827 ; MM32R6-NEXT: jrc $ra
828 entry:
829 %r = and i32 31, %b
830 ret i32 %r
831 }
833 define signext i64 @and_i64_31(i64 signext %b) {
834 ; MIPS-LABEL: and_i64_31:
835 ; MIPS: # %bb.0: # %entry
836 ; MIPS-NEXT: andi $3, $5, 31
837 ; MIPS-NEXT: jr $ra
838 ; MIPS-NEXT: addiu $2, $zero, 0
839 ;
840 ; MIPS32R2-LABEL: and_i64_31:
841 ; MIPS32R2: # %bb.0: # %entry
842 ; MIPS32R2-NEXT: andi $3, $5, 31
843 ; MIPS32R2-NEXT: jr $ra
844 ; MIPS32R2-NEXT: addiu $2, $zero, 0
845 ;
846 ; MIPS32R6-LABEL: and_i64_31:
847 ; MIPS32R6: # %bb.0: # %entry
848 ; MIPS32R6-NEXT: andi $3, $5, 31
849 ; MIPS32R6-NEXT: jr $ra
850 ; MIPS32R6-NEXT: addiu $2, $zero, 0
851 ;
852 ; MIPS64-LABEL: and_i64_31:
853 ; MIPS64: # %bb.0: # %entry
854 ; MIPS64-NEXT: jr $ra
855 ; MIPS64-NEXT: andi $2, $4, 31
856 ;
857 ; MIPS64R2-LABEL: and_i64_31:
858 ; MIPS64R2: # %bb.0: # %entry
859 ; MIPS64R2-NEXT: jr $ra
860 ; MIPS64R2-NEXT: andi $2, $4, 31
861 ;
862 ; MIPS64R6-LABEL: and_i64_31:
863 ; MIPS64R6: # %bb.0: # %entry
864 ; MIPS64R6-NEXT: jr $ra
865 ; MIPS64R6-NEXT: andi $2, $4, 31
866 ;
867 ; MM32R3-LABEL: and_i64_31:
868 ; MM32R3: # %bb.0: # %entry
869 ; MM32R3-NEXT: andi16 $3, $5, 31
870 ; MM32R3-NEXT: li16 $2, 0
871 ; MM32R3-NEXT: jrc $ra
872 ;
873 ; MM32R6-LABEL: and_i64_31:
874 ; MM32R6: # %bb.0: # %entry
875 ; MM32R6-NEXT: andi16 $3, $5, 31
876 ; MM32R6-NEXT: li16 $2, 0
877 ; MM32R6-NEXT: jrc $ra
878 entry:
879 %r = and i64 31, %b
880 ret i64 %r
881 }
883 define signext i128 @and_i128_31(i128 signext %b) {
884 ; MIPS-LABEL: and_i128_31:
885 ; MIPS: # %bb.0: # %entry
886 ; MIPS-NEXT: andi $5, $7, 31
887 ; MIPS-NEXT: addiu $2, $zero, 0
888 ; MIPS-NEXT: addiu $3, $zero, 0
889 ; MIPS-NEXT: jr $ra
890 ; MIPS-NEXT: addiu $4, $zero, 0
891 ;
892 ; MIPS32R2-LABEL: and_i128_31:
893 ; MIPS32R2: # %bb.0: # %entry
894 ; MIPS32R2-NEXT: andi $5, $7, 31
895 ; MIPS32R2-NEXT: addiu $2, $zero, 0
896 ; MIPS32R2-NEXT: addiu $3, $zero, 0
897 ; MIPS32R2-NEXT: jr $ra
898 ; MIPS32R2-NEXT: addiu $4, $zero, 0
899 ;
900 ; MIPS32R6-LABEL: and_i128_31:
901 ; MIPS32R6: # %bb.0: # %entry
902 ; MIPS32R6-NEXT: andi $5, $7, 31
903 ; MIPS32R6-NEXT: addiu $2, $zero, 0
904 ; MIPS32R6-NEXT: addiu $3, $zero, 0
905 ; MIPS32R6-NEXT: jr $ra
906 ; MIPS32R6-NEXT: addiu $4, $zero, 0
907 ;
908 ; MIPS64-LABEL: and_i128_31:
909 ; MIPS64: # %bb.0: # %entry
910 ; MIPS64-NEXT: andi $3, $5, 31
911 ; MIPS64-NEXT: jr $ra
912 ; MIPS64-NEXT: daddiu $2, $zero, 0
913 ;
914 ; MIPS64R2-LABEL: and_i128_31:
915 ; MIPS64R2: # %bb.0: # %entry
916 ; MIPS64R2-NEXT: andi $3, $5, 31
917 ; MIPS64R2-NEXT: jr $ra
918 ; MIPS64R2-NEXT: daddiu $2, $zero, 0
919 ;
920 ; MIPS64R6-LABEL: and_i128_31:
921 ; MIPS64R6: # %bb.0: # %entry
922 ; MIPS64R6-NEXT: andi $3, $5, 31
923 ; MIPS64R6-NEXT: jr $ra
924 ; MIPS64R6-NEXT: daddiu $2, $zero, 0
925 ;
926 ; MM32R3-LABEL: and_i128_31:
927 ; MM32R3: # %bb.0: # %entry
928 ; MM32R3-NEXT: andi16 $5, $7, 31
929 ; MM32R3-NEXT: li16 $2, 0
930 ; MM32R3-NEXT: li16 $3, 0
931 ; MM32R3-NEXT: li16 $4, 0
932 ; MM32R3-NEXT: jrc $ra
933 ;
934 ; MM32R6-LABEL: and_i128_31:
935 ; MM32R6: # %bb.0: # %entry
936 ; MM32R6-NEXT: andi16 $5, $7, 31
937 ; MM32R6-NEXT: li16 $2, 0
938 ; MM32R6-NEXT: li16 $3, 0
939 ; MM32R6-NEXT: li16 $4, 0
940 ; MM32R6-NEXT: jrc $ra
941 entry:
942 %r = and i128 31, %b
943 ret i128 %r
944 }
946 define signext i1 @and_i1_255(i1 signext %b) {
947 ; MIPS-LABEL: and_i1_255:
948 ; MIPS: # %bb.0: # %entry
949 ; MIPS-NEXT: jr $ra
950 ; MIPS-NEXT: move $2, $4
951 ;
952 ; MIPS32R2-LABEL: and_i1_255:
953 ; MIPS32R2: # %bb.0: # %entry
954 ; MIPS32R2-NEXT: jr $ra
955 ; MIPS32R2-NEXT: move $2, $4
956 ;
957 ; MIPS32R6-LABEL: and_i1_255:
958 ; MIPS32R6: # %bb.0: # %entry
959 ; MIPS32R6-NEXT: jr $ra
960 ; MIPS32R6-NEXT: move $2, $4
961 ;
962 ; MIPS64-LABEL: and_i1_255:
963 ; MIPS64: # %bb.0: # %entry
964 ; MIPS64-NEXT: jr $ra
965 ; MIPS64-NEXT: move $2, $4
966 ;
967 ; MIPS64R2-LABEL: and_i1_255:
968 ; MIPS64R2: # %bb.0: # %entry
969 ; MIPS64R2-NEXT: jr $ra
970 ; MIPS64R2-NEXT: move $2, $4
971 ;
972 ; MIPS64R6-LABEL: and_i1_255:
973 ; MIPS64R6: # %bb.0: # %entry
974 ; MIPS64R6-NEXT: jr $ra
975 ; MIPS64R6-NEXT: move $2, $4
976 ;
977 ; MM32R3-LABEL: and_i1_255:
978 ; MM32R3: # %bb.0: # %entry
979 ; MM32R3-NEXT: move $2, $4
980 ; MM32R3-NEXT: jrc $ra
981 ;
982 ; MM32R6-LABEL: and_i1_255:
983 ; MM32R6: # %bb.0: # %entry
984 ; MM32R6-NEXT: move $2, $4
985 ; MM32R6-NEXT: jrc $ra
986 entry:
987 %r = and i1 255, %b
988 ret i1 %r
989 }
991 define signext i8 @and_i8_255(i8 signext %b) {
992 ; MIPS-LABEL: and_i8_255:
993 ; MIPS: # %bb.0: # %entry
994 ; MIPS-NEXT: jr $ra
995 ; MIPS-NEXT: move $2, $4
996 ;
997 ; MIPS32R2-LABEL: and_i8_255:
998 ; MIPS32R2: # %bb.0: # %entry
999 ; MIPS32R2-NEXT: jr $ra
1000 ; MIPS32R2-NEXT: move $2, $4
1001 ;
1002 ; MIPS32R6-LABEL: and_i8_255:
1003 ; MIPS32R6: # %bb.0: # %entry
1004 ; MIPS32R6-NEXT: jr $ra
1005 ; MIPS32R6-NEXT: move $2, $4
1006 ;
1007 ; MIPS64-LABEL: and_i8_255:
1008 ; MIPS64: # %bb.0: # %entry
1009 ; MIPS64-NEXT: jr $ra
1010 ; MIPS64-NEXT: move $2, $4
1011 ;
1012 ; MIPS64R2-LABEL: and_i8_255:
1013 ; MIPS64R2: # %bb.0: # %entry
1014 ; MIPS64R2-NEXT: jr $ra
1015 ; MIPS64R2-NEXT: move $2, $4
1016 ;
1017 ; MIPS64R6-LABEL: and_i8_255:
1018 ; MIPS64R6: # %bb.0: # %entry
1019 ; MIPS64R6-NEXT: jr $ra
1020 ; MIPS64R6-NEXT: move $2, $4
1021 ;
1022 ; MM32R3-LABEL: and_i8_255:
1023 ; MM32R3: # %bb.0: # %entry
1024 ; MM32R3-NEXT: move $2, $4
1025 ; MM32R3-NEXT: jrc $ra
1026 ;
1027 ; MM32R6-LABEL: and_i8_255:
1028 ; MM32R6: # %bb.0: # %entry
1029 ; MM32R6-NEXT: move $2, $4
1030 ; MM32R6-NEXT: jrc $ra
1031 entry:
1032 %r = and i8 255, %b
1033 ret i8 %r
1034 }
1036 define signext i16 @and_i16_255(i16 signext %b) {
1037 ; MIPS-LABEL: and_i16_255:
1038 ; MIPS: # %bb.0: # %entry
1039 ; MIPS-NEXT: jr $ra
1040 ; MIPS-NEXT: andi $2, $4, 255
1041 ;
1042 ; MIPS32R2-LABEL: and_i16_255:
1043 ; MIPS32R2: # %bb.0: # %entry
1044 ; MIPS32R2-NEXT: jr $ra
1045 ; MIPS32R2-NEXT: andi $2, $4, 255
1046 ;
1047 ; MIPS32R6-LABEL: and_i16_255:
1048 ; MIPS32R6: # %bb.0: # %entry
1049 ; MIPS32R6-NEXT: jr $ra
1050 ; MIPS32R6-NEXT: andi $2, $4, 255
1051 ;
1052 ; MIPS64-LABEL: and_i16_255:
1053 ; MIPS64: # %bb.0: # %entry
1054 ; MIPS64-NEXT: jr $ra
1055 ; MIPS64-NEXT: andi $2, $4, 255
1056 ;
1057 ; MIPS64R2-LABEL: and_i16_255:
1058 ; MIPS64R2: # %bb.0: # %entry
1059 ; MIPS64R2-NEXT: jr $ra
1060 ; MIPS64R2-NEXT: andi $2, $4, 255
1061 ;
1062 ; MIPS64R6-LABEL: and_i16_255:
1063 ; MIPS64R6: # %bb.0: # %entry
1064 ; MIPS64R6-NEXT: jr $ra
1065 ; MIPS64R6-NEXT: andi $2, $4, 255
1066 ;
1067 ; MM32R3-LABEL: and_i16_255:
1068 ; MM32R3: # %bb.0: # %entry
1069 ; MM32R3-NEXT: andi16 $2, $4, 255
1070 ; MM32R3-NEXT: jrc $ra
1071 ;
1072 ; MM32R6-LABEL: and_i16_255:
1073 ; MM32R6: # %bb.0: # %entry
1074 ; MM32R6-NEXT: andi16 $2, $4, 255
1075 ; MM32R6-NEXT: jrc $ra
1076 entry:
1077 %r = and i16 255, %b
1078 ret i16 %r
1079 }
1081 define signext i32 @and_i32_255(i32 signext %b) {
1082 ; MIPS-LABEL: and_i32_255:
1083 ; MIPS: # %bb.0: # %entry
1084 ; MIPS-NEXT: jr $ra
1085 ; MIPS-NEXT: andi $2, $4, 255
1086 ;
1087 ; MIPS32R2-LABEL: and_i32_255:
1088 ; MIPS32R2: # %bb.0: # %entry
1089 ; MIPS32R2-NEXT: jr $ra
1090 ; MIPS32R2-NEXT: andi $2, $4, 255
1091 ;
1092 ; MIPS32R6-LABEL: and_i32_255:
1093 ; MIPS32R6: # %bb.0: # %entry
1094 ; MIPS32R6-NEXT: jr $ra
1095 ; MIPS32R6-NEXT: andi $2, $4, 255
1096 ;
1097 ; MIPS64-LABEL: and_i32_255:
1098 ; MIPS64: # %bb.0: # %entry
1099 ; MIPS64-NEXT: jr $ra
1100 ; MIPS64-NEXT: andi $2, $4, 255
1101 ;
1102 ; MIPS64R2-LABEL: and_i32_255:
1103 ; MIPS64R2: # %bb.0: # %entry
1104 ; MIPS64R2-NEXT: jr $ra
1105 ; MIPS64R2-NEXT: andi $2, $4, 255
1106 ;
1107 ; MIPS64R6-LABEL: and_i32_255:
1108 ; MIPS64R6: # %bb.0: # %entry
1109 ; MIPS64R6-NEXT: jr $ra
1110 ; MIPS64R6-NEXT: andi $2, $4, 255
1111 ;
1112 ; MM32R3-LABEL: and_i32_255:
1113 ; MM32R3: # %bb.0: # %entry
1114 ; MM32R3-NEXT: andi16 $2, $4, 255
1115 ; MM32R3-NEXT: jrc $ra
1116 ;
1117 ; MM32R6-LABEL: and_i32_255:
1118 ; MM32R6: # %bb.0: # %entry
1119 ; MM32R6-NEXT: andi16 $2, $4, 255
1120 ; MM32R6-NEXT: jrc $ra
1121 entry:
1122 %r = and i32 255, %b
1123 ret i32 %r
1124 }
1126 define signext i64 @and_i64_255(i64 signext %b) {
1127 ; MIPS-LABEL: and_i64_255:
1128 ; MIPS: # %bb.0: # %entry
1129 ; MIPS-NEXT: andi $3, $5, 255
1130 ; MIPS-NEXT: jr $ra
1131 ; MIPS-NEXT: addiu $2, $zero, 0
1132 ;
1133 ; MIPS32R2-LABEL: and_i64_255:
1134 ; MIPS32R2: # %bb.0: # %entry
1135 ; MIPS32R2-NEXT: andi $3, $5, 255
1136 ; MIPS32R2-NEXT: jr $ra
1137 ; MIPS32R2-NEXT: addiu $2, $zero, 0
1138 ;
1139 ; MIPS32R6-LABEL: and_i64_255:
1140 ; MIPS32R6: # %bb.0: # %entry
1141 ; MIPS32R6-NEXT: andi $3, $5, 255
1142 ; MIPS32R6-NEXT: jr $ra
1143 ; MIPS32R6-NEXT: addiu $2, $zero, 0
1144 ;
1145 ; MIPS64-LABEL: and_i64_255:
1146 ; MIPS64: # %bb.0: # %entry
1147 ; MIPS64-NEXT: jr $ra
1148 ; MIPS64-NEXT: andi $2, $4, 255
1149 ;
1150 ; MIPS64R2-LABEL: and_i64_255:
1151 ; MIPS64R2: # %bb.0: # %entry
1152 ; MIPS64R2-NEXT: jr $ra
1153 ; MIPS64R2-NEXT: andi $2, $4, 255
1154 ;
1155 ; MIPS64R6-LABEL: and_i64_255:
1156 ; MIPS64R6: # %bb.0: # %entry
1157 ; MIPS64R6-NEXT: jr $ra
1158 ; MIPS64R6-NEXT: andi $2, $4, 255
1159 ;
1160 ; MM32R3-LABEL: and_i64_255:
1161 ; MM32R3: # %bb.0: # %entry
1162 ; MM32R3-NEXT: andi16 $3, $5, 255
1163 ; MM32R3-NEXT: li16 $2, 0
1164 ; MM32R3-NEXT: jrc $ra
1165 ;
1166 ; MM32R6-LABEL: and_i64_255:
1167 ; MM32R6: # %bb.0: # %entry
1168 ; MM32R6-NEXT: andi16 $3, $5, 255
1169 ; MM32R6-NEXT: li16 $2, 0
1170 ; MM32R6-NEXT: jrc $ra
1171 entry:
1172 %r = and i64 255, %b
1173 ret i64 %r
1174 }
1176 define signext i128 @and_i128_255(i128 signext %b) {
1177 ; MIPS-LABEL: and_i128_255:
1178 ; MIPS: # %bb.0: # %entry
1179 ; MIPS-NEXT: andi $5, $7, 255
1180 ; MIPS-NEXT: addiu $2, $zero, 0
1181 ; MIPS-NEXT: addiu $3, $zero, 0
1182 ; MIPS-NEXT: jr $ra
1183 ; MIPS-NEXT: addiu $4, $zero, 0
1184 ;
1185 ; MIPS32R2-LABEL: and_i128_255:
1186 ; MIPS32R2: # %bb.0: # %entry
1187 ; MIPS32R2-NEXT: andi $5, $7, 255
1188 ; MIPS32R2-NEXT: addiu $2, $zero, 0
1189 ; MIPS32R2-NEXT: addiu $3, $zero, 0
1190 ; MIPS32R2-NEXT: jr $ra
1191 ; MIPS32R2-NEXT: addiu $4, $zero, 0
1192 ;
1193 ; MIPS32R6-LABEL: and_i128_255:
1194 ; MIPS32R6: # %bb.0: # %entry
1195 ; MIPS32R6-NEXT: andi $5, $7, 255
1196 ; MIPS32R6-NEXT: addiu $2, $zero, 0
1197 ; MIPS32R6-NEXT: addiu $3, $zero, 0
1198 ; MIPS32R6-NEXT: jr $ra
1199 ; MIPS32R6-NEXT: addiu $4, $zero, 0
1200 ;
1201 ; MIPS64-LABEL: and_i128_255:
1202 ; MIPS64: # %bb.0: # %entry
1203 ; MIPS64-NEXT: andi $3, $5, 255
1204 ; MIPS64-NEXT: jr $ra
1205 ; MIPS64-NEXT: daddiu $2, $zero, 0
1206 ;
1207 ; MIPS64R2-LABEL: and_i128_255:
1208 ; MIPS64R2: # %bb.0: # %entry
1209 ; MIPS64R2-NEXT: andi $3, $5, 255
1210 ; MIPS64R2-NEXT: jr $ra
1211 ; MIPS64R2-NEXT: daddiu $2, $zero, 0
1212 ;
1213 ; MIPS64R6-LABEL: and_i128_255:
1214 ; MIPS64R6: # %bb.0: # %entry
1215 ; MIPS64R6-NEXT: andi $3, $5, 255
1216 ; MIPS64R6-NEXT: jr $ra
1217 ; MIPS64R6-NEXT: daddiu $2, $zero, 0
1218 ;
1219 ; MM32R3-LABEL: and_i128_255:
1220 ; MM32R3: # %bb.0: # %entry
1221 ; MM32R3-NEXT: andi16 $5, $7, 255
1222 ; MM32R3-NEXT: li16 $2, 0
1223 ; MM32R3-NEXT: li16 $3, 0
1224 ; MM32R3-NEXT: li16 $4, 0
1225 ; MM32R3-NEXT: jrc $ra
1226 ;
1227 ; MM32R6-LABEL: and_i128_255:
1228 ; MM32R6: # %bb.0: # %entry
1229 ; MM32R6-NEXT: andi16 $5, $7, 255
1230 ; MM32R6-NEXT: li16 $2, 0
1231 ; MM32R6-NEXT: li16 $3, 0
1232 ; MM32R6-NEXT: li16 $4, 0
1233 ; MM32R6-NEXT: jrc $ra
1234 entry:
1235 %r = and i128 255, %b
1236 ret i128 %r
1237 }
1239 define signext i1 @and_i1_32768(i1 signext %b) {
1240 ; MIPS-LABEL: and_i1_32768:
1241 ; MIPS: # %bb.0: # %entry
1242 ; MIPS-NEXT: jr $ra
1243 ; MIPS-NEXT: addiu $2, $zero, 0
1244 ;
1245 ; MIPS32R2-LABEL: and_i1_32768:
1246 ; MIPS32R2: # %bb.0: # %entry
1247 ; MIPS32R2-NEXT: jr $ra
1248 ; MIPS32R2-NEXT: addiu $2, $zero, 0
1249 ;
1250 ; MIPS32R6-LABEL: and_i1_32768:
1251 ; MIPS32R6: # %bb.0: # %entry
1252 ; MIPS32R6-NEXT: jr $ra
1253 ; MIPS32R6-NEXT: addiu $2, $zero, 0
1254 ;
1255 ; MIPS64-LABEL: and_i1_32768:
1256 ; MIPS64: # %bb.0: # %entry
1257 ; MIPS64-NEXT: jr $ra
1258 ; MIPS64-NEXT: addiu $2, $zero, 0
1259 ;
1260 ; MIPS64R2-LABEL: and_i1_32768:
1261 ; MIPS64R2: # %bb.0: # %entry
1262 ; MIPS64R2-NEXT: jr $ra
1263 ; MIPS64R2-NEXT: addiu $2, $zero, 0
1264 ;
1265 ; MIPS64R6-LABEL: and_i1_32768:
1266 ; MIPS64R6: # %bb.0: # %entry
1267 ; MIPS64R6-NEXT: jr $ra
1268 ; MIPS64R6-NEXT: addiu $2, $zero, 0
1269 ;
1270 ; MM32R3-LABEL: and_i1_32768:
1271 ; MM32R3: # %bb.0: # %entry
1272 ; MM32R3-NEXT: li16 $2, 0
1273 ; MM32R3-NEXT: jrc $ra
1274 ;
1275 ; MM32R6-LABEL: and_i1_32768:
1276 ; MM32R6: # %bb.0: # %entry
1277 ; MM32R6-NEXT: li16 $2, 0
1278 ; MM32R6-NEXT: jrc $ra
1279 entry:
1280 %r = and i1 32768, %b
1281 ret i1 %r
1282 }
1284 define signext i8 @and_i8_32768(i8 signext %b) {
1285 ; MIPS-LABEL: and_i8_32768:
1286 ; MIPS: # %bb.0: # %entry
1287 ; MIPS-NEXT: jr $ra
1288 ; MIPS-NEXT: addiu $2, $zero, 0
1289 ;
1290 ; MIPS32R2-LABEL: and_i8_32768:
1291 ; MIPS32R2: # %bb.0: # %entry
1292 ; MIPS32R2-NEXT: jr $ra
1293 ; MIPS32R2-NEXT: addiu $2, $zero, 0
1294 ;
1295 ; MIPS32R6-LABEL: and_i8_32768:
1296 ; MIPS32R6: # %bb.0: # %entry
1297 ; MIPS32R6-NEXT: jr $ra
1298 ; MIPS32R6-NEXT: addiu $2, $zero, 0
1299 ;
1300 ; MIPS64-LABEL: and_i8_32768:
1301 ; MIPS64: # %bb.0: # %entry
1302 ; MIPS64-NEXT: jr $ra
1303 ; MIPS64-NEXT: addiu $2, $zero, 0
1304 ;
1305 ; MIPS64R2-LABEL: and_i8_32768:
1306 ; MIPS64R2: # %bb.0: # %entry
1307 ; MIPS64R2-NEXT: jr $ra
1308 ; MIPS64R2-NEXT: addiu $2, $zero, 0
1309 ;
1310 ; MIPS64R6-LABEL: and_i8_32768:
1311 ; MIPS64R6: # %bb.0: # %entry
1312 ; MIPS64R6-NEXT: jr $ra
1313 ; MIPS64R6-NEXT: addiu $2, $zero, 0
1314 ;
1315 ; MM32R3-LABEL: and_i8_32768:
1316 ; MM32R3: # %bb.0: # %entry
1317 ; MM32R3-NEXT: li16 $2, 0
1318 ; MM32R3-NEXT: jrc $ra
1319 ;
1320 ; MM32R6-LABEL: and_i8_32768:
1321 ; MM32R6: # %bb.0: # %entry
1322 ; MM32R6-NEXT: li16 $2, 0
1323 ; MM32R6-NEXT: jrc $ra
1324 entry:
1325 %r = and i8 32768, %b
1326 ret i8 %r
1327 }
1329 define signext i16 @and_i16_32768(i16 signext %b) {
1330 ; MIPS-LABEL: and_i16_32768:
1331 ; MIPS: # %bb.0: # %entry
1332 ; MIPS-NEXT: addiu $1, $zero, -32768
1333 ; MIPS-NEXT: jr $ra
1334 ; MIPS-NEXT: and $2, $4, $1
1335 ;
1336 ; MIPS32R2-LABEL: and_i16_32768:
1337 ; MIPS32R2: # %bb.0: # %entry
1338 ; MIPS32R2-NEXT: addiu $1, $zero, -32768
1339 ; MIPS32R2-NEXT: jr $ra
1340 ; MIPS32R2-NEXT: and $2, $4, $1
1341 ;
1342 ; MIPS32R6-LABEL: and_i16_32768:
1343 ; MIPS32R6: # %bb.0: # %entry
1344 ; MIPS32R6-NEXT: addiu $1, $zero, -32768
1345 ; MIPS32R6-NEXT: jr $ra
1346 ; MIPS32R6-NEXT: and $2, $4, $1
1347 ;
1348 ; MIPS64-LABEL: and_i16_32768:
1349 ; MIPS64: # %bb.0: # %entry
1350 ; MIPS64-NEXT: addiu $1, $zero, -32768
1351 ; MIPS64-NEXT: jr $ra
1352 ; MIPS64-NEXT: and $2, $4, $1
1353 ;
1354 ; MIPS64R2-LABEL: and_i16_32768:
1355 ; MIPS64R2: # %bb.0: # %entry
1356 ; MIPS64R2-NEXT: addiu $1, $zero, -32768
1357 ; MIPS64R2-NEXT: jr $ra
1358 ; MIPS64R2-NEXT: and $2, $4, $1
1359 ;
1360 ; MIPS64R6-LABEL: and_i16_32768:
1361 ; MIPS64R6: # %bb.0: # %entry
1362 ; MIPS64R6-NEXT: addiu $1, $zero, -32768
1363 ; MIPS64R6-NEXT: jr $ra
1364 ; MIPS64R6-NEXT: and $2, $4, $1
1365 ;
1366 ; MM32R3-LABEL: and_i16_32768:
1367 ; MM32R3: # %bb.0: # %entry
1368 ; MM32R3-NEXT: addiu $2, $zero, -32768
1369 ; MM32R3-NEXT: and16 $2, $4
1370 ; MM32R3-NEXT: jrc $ra
1371 ;
1372 ; MM32R6-LABEL: and_i16_32768:
1373 ; MM32R6: # %bb.0: # %entry
1374 ; MM32R6-NEXT: addiu $1, $zero, -32768
1375 ; MM32R6-NEXT: and $2, $4, $1
1376 ; MM32R6-NEXT: jrc $ra
1377 entry:
1379 %r = and i16 32768, %b
1380 ret i16 %r
1381 }
1383 define signext i32 @and_i32_32768(i32 signext %b) {
1384 ; MIPS-LABEL: and_i32_32768:
1385 ; MIPS: # %bb.0: # %entry
1386 ; MIPS-NEXT: jr $ra
1387 ; MIPS-NEXT: andi $2, $4, 32768
1388 ;
1389 ; MIPS32R2-LABEL: and_i32_32768:
1390 ; MIPS32R2: # %bb.0: # %entry
1391 ; MIPS32R2-NEXT: jr $ra
1392 ; MIPS32R2-NEXT: andi $2, $4, 32768
1393 ;
1394 ; MIPS32R6-LABEL: and_i32_32768:
1395 ; MIPS32R6: # %bb.0: # %entry
1396 ; MIPS32R6-NEXT: jr $ra
1397 ; MIPS32R6-NEXT: andi $2, $4, 32768
1398 ;
1399 ; MIPS64-LABEL: and_i32_32768:
1400 ; MIPS64: # %bb.0: # %entry
1401 ; MIPS64-NEXT: jr $ra
1402 ; MIPS64-NEXT: andi $2, $4, 32768
1403 ;
1404 ; MIPS64R2-LABEL: and_i32_32768:
1405 ; MIPS64R2: # %bb.0: # %entry
1406 ; MIPS64R2-NEXT: jr $ra
1407 ; MIPS64R2-NEXT: andi $2, $4, 32768
1408 ;
1409 ; MIPS64R6-LABEL: and_i32_32768:
1410 ; MIPS64R6: # %bb.0: # %entry
1411 ; MIPS64R6-NEXT: jr $ra
1412 ; MIPS64R6-NEXT: andi $2, $4, 32768
1413 ;
1414 ; MM32R3-LABEL: and_i32_32768:
1415 ; MM32R3: # %bb.0: # %entry
1416 ; MM32R3-NEXT: andi16 $2, $4, 32768
1417 ; MM32R3-NEXT: jrc $ra
1418 ;
1419 ; MM32R6-LABEL: and_i32_32768:
1420 ; MM32R6: # %bb.0: # %entry
1421 ; MM32R6-NEXT: andi16 $2, $4, 32768
1422 ; MM32R6-NEXT: jrc $ra
1423 entry:
1424 %r = and i32 32768, %b
1425 ret i32 %r
1426 }
1428 define signext i64 @and_i64_32768(i64 signext %b) {
1429 ; MIPS-LABEL: and_i64_32768:
1430 ; MIPS: # %bb.0: # %entry
1431 ; MIPS-NEXT: andi $3, $5, 32768
1432 ; MIPS-NEXT: jr $ra
1433 ; MIPS-NEXT: addiu $2, $zero, 0
1434 ;
1435 ; MIPS32R2-LABEL: and_i64_32768:
1436 ; MIPS32R2: # %bb.0: # %entry
1437 ; MIPS32R2-NEXT: andi $3, $5, 32768
1438 ; MIPS32R2-NEXT: jr $ra
1439 ; MIPS32R2-NEXT: addiu $2, $zero, 0
1440 ;
1441 ; MIPS32R6-LABEL: and_i64_32768:
1442 ; MIPS32R6: # %bb.0: # %entry
1443 ; MIPS32R6-NEXT: andi $3, $5, 32768
1444 ; MIPS32R6-NEXT: jr $ra
1445 ; MIPS32R6-NEXT: addiu $2, $zero, 0
1446 ;
1447 ; MIPS64-LABEL: and_i64_32768:
1448 ; MIPS64: # %bb.0: # %entry
1449 ; MIPS64-NEXT: jr $ra
1450 ; MIPS64-NEXT: andi $2, $4, 32768
1451 ;
1452 ; MIPS64R2-LABEL: and_i64_32768:
1453 ; MIPS64R2: # %bb.0: # %entry
1454 ; MIPS64R2-NEXT: jr $ra
1455 ; MIPS64R2-NEXT: andi $2, $4, 32768
1456 ;
1457 ; MIPS64R6-LABEL: and_i64_32768:
1458 ; MIPS64R6: # %bb.0: # %entry
1459 ; MIPS64R6-NEXT: jr $ra
1460 ; MIPS64R6-NEXT: andi $2, $4, 32768
1461 ;
1462 ; MM32R3-LABEL: and_i64_32768:
1463 ; MM32R3: # %bb.0: # %entry
1464 ; MM32R3-NEXT: andi16 $3, $5, 32768
1465 ; MM32R3-NEXT: li16 $2, 0
1466 ; MM32R3-NEXT: jrc $ra
1467 ;
1468 ; MM32R6-LABEL: and_i64_32768:
1469 ; MM32R6: # %bb.0: # %entry
1470 ; MM32R6-NEXT: andi16 $3, $5, 32768
1471 ; MM32R6-NEXT: li16 $2, 0
1472 ; MM32R6-NEXT: jrc $ra
1473 entry:
1474 %r = and i64 32768, %b
1475 ret i64 %r
1476 }
1478 define signext i128 @and_i128_32768(i128 signext %b) {
1479 ; MIPS-LABEL: and_i128_32768:
1480 ; MIPS: # %bb.0: # %entry
1481 ; MIPS-NEXT: andi $5, $7, 32768
1482 ; MIPS-NEXT: addiu $2, $zero, 0
1483 ; MIPS-NEXT: addiu $3, $zero, 0
1484 ; MIPS-NEXT: jr $ra
1485 ; MIPS-NEXT: addiu $4, $zero, 0
1486 ;
1487 ; MIPS32R2-LABEL: and_i128_32768:
1488 ; MIPS32R2: # %bb.0: # %entry
1489 ; MIPS32R2-NEXT: andi $5, $7, 32768
1490 ; MIPS32R2-NEXT: addiu $2, $zero, 0
1491 ; MIPS32R2-NEXT: addiu $3, $zero, 0
1492 ; MIPS32R2-NEXT: jr $ra
1493 ; MIPS32R2-NEXT: addiu $4, $zero, 0
1494 ;
1495 ; MIPS32R6-LABEL: and_i128_32768:
1496 ; MIPS32R6: # %bb.0: # %entry
1497 ; MIPS32R6-NEXT: andi $5, $7, 32768
1498 ; MIPS32R6-NEXT: addiu $2, $zero, 0
1499 ; MIPS32R6-NEXT: addiu $3, $zero, 0
1500 ; MIPS32R6-NEXT: jr $ra
1501 ; MIPS32R6-NEXT: addiu $4, $zero, 0
1502 ;
1503 ; MIPS64-LABEL: and_i128_32768:
1504 ; MIPS64: # %bb.0: # %entry
1505 ; MIPS64-NEXT: andi $3, $5, 32768
1506 ; MIPS64-NEXT: jr $ra
1507 ; MIPS64-NEXT: daddiu $2, $zero, 0
1508 ;
1509 ; MIPS64R2-LABEL: and_i128_32768:
1510 ; MIPS64R2: # %bb.0: # %entry
1511 ; MIPS64R2-NEXT: andi $3, $5, 32768
1512 ; MIPS64R2-NEXT: jr $ra
1513 ; MIPS64R2-NEXT: daddiu $2, $zero, 0
1514 ;
1515 ; MIPS64R6-LABEL: and_i128_32768:
1516 ; MIPS64R6: # %bb.0: # %entry
1517 ; MIPS64R6-NEXT: andi $3, $5, 32768
1518 ; MIPS64R6-NEXT: jr $ra
1519 ; MIPS64R6-NEXT: daddiu $2, $zero, 0
1520 ;
1521 ; MM32R3-LABEL: and_i128_32768:
1522 ; MM32R3: # %bb.0: # %entry
1523 ; MM32R3-NEXT: andi16 $5, $7, 32768
1524 ; MM32R3-NEXT: li16 $2, 0
1525 ; MM32R3-NEXT: li16 $3, 0
1526 ; MM32R3-NEXT: li16 $4, 0
1527 ; MM32R3-NEXT: jrc $ra
1528 ;
1529 ; MM32R6-LABEL: and_i128_32768:
1530 ; MM32R6: # %bb.0: # %entry
1531 ; MM32R6-NEXT: andi16 $5, $7, 32768
1532 ; MM32R6-NEXT: li16 $2, 0
1533 ; MM32R6-NEXT: li16 $3, 0
1534 ; MM32R6-NEXT: li16 $4, 0
1535 ; MM32R6-NEXT: jrc $ra
1536 entry:
1537 %r = and i128 32768, %b
1538 ret i128 %r
1539 }
1541 define signext i1 @and_i1_65(i1 signext %b) {
1542 ; MIPS-LABEL: and_i1_65:
1543 ; MIPS: # %bb.0: # %entry
1544 ; MIPS-NEXT: jr $ra
1545 ; MIPS-NEXT: move $2, $4
1546 ;
1547 ; MIPS32R2-LABEL: and_i1_65:
1548 ; MIPS32R2: # %bb.0: # %entry
1549 ; MIPS32R2-NEXT: jr $ra
1550 ; MIPS32R2-NEXT: move $2, $4
1551 ;
1552 ; MIPS32R6-LABEL: and_i1_65:
1553 ; MIPS32R6: # %bb.0: # %entry
1554 ; MIPS32R6-NEXT: jr $ra
1555 ; MIPS32R6-NEXT: move $2, $4
1556 ;
1557 ; MIPS64-LABEL: and_i1_65:
1558 ; MIPS64: # %bb.0: # %entry
1559 ; MIPS64-NEXT: jr $ra
1560 ; MIPS64-NEXT: move $2, $4
1561 ;
1562 ; MIPS64R2-LABEL: and_i1_65:
1563 ; MIPS64R2: # %bb.0: # %entry
1564 ; MIPS64R2-NEXT: jr $ra
1565 ; MIPS64R2-NEXT: move $2, $4
1566 ;
1567 ; MIPS64R6-LABEL: and_i1_65:
1568 ; MIPS64R6: # %bb.0: # %entry
1569 ; MIPS64R6-NEXT: jr $ra
1570 ; MIPS64R6-NEXT: move $2, $4
1571 ;
1572 ; MM32R3-LABEL: and_i1_65:
1573 ; MM32R3: # %bb.0: # %entry
1574 ; MM32R3-NEXT: move $2, $4
1575 ; MM32R3-NEXT: jrc $ra
1576 ;
1577 ; MM32R6-LABEL: and_i1_65:
1578 ; MM32R6: # %bb.0: # %entry
1579 ; MM32R6-NEXT: move $2, $4
1580 ; MM32R6-NEXT: jrc $ra
1581 entry:
1582 %r = and i1 65, %b
1583 ret i1 %r
1584 }
1586 define signext i8 @and_i8_65(i8 signext %b) {
1587 ; MIPS-LABEL: and_i8_65:
1588 ; MIPS: # %bb.0: # %entry
1589 ; MIPS-NEXT: jr $ra
1590 ; MIPS-NEXT: andi $2, $4, 65
1591 ;
1592 ; MIPS32R2-LABEL: and_i8_65:
1593 ; MIPS32R2: # %bb.0: # %entry
1594 ; MIPS32R2-NEXT: jr $ra
1595 ; MIPS32R2-NEXT: andi $2, $4, 65
1596 ;
1597 ; MIPS32R6-LABEL: and_i8_65:
1598 ; MIPS32R6: # %bb.0: # %entry
1599 ; MIPS32R6-NEXT: jr $ra
1600 ; MIPS32R6-NEXT: andi $2, $4, 65
1601 ;
1602 ; MIPS64-LABEL: and_i8_65:
1603 ; MIPS64: # %bb.0: # %entry
1604 ; MIPS64-NEXT: jr $ra
1605 ; MIPS64-NEXT: andi $2, $4, 65
1606 ;
1607 ; MIPS64R2-LABEL: and_i8_65:
1608 ; MIPS64R2: # %bb.0: # %entry
1609 ; MIPS64R2-NEXT: jr $ra
1610 ; MIPS64R2-NEXT: andi $2, $4, 65
1611 ;
1612 ; MIPS64R6-LABEL: and_i8_65:
1613 ; MIPS64R6: # %bb.0: # %entry
1614 ; MIPS64R6-NEXT: jr $ra
1615 ; MIPS64R6-NEXT: andi $2, $4, 65
1616 ;
1617 ; MM32R3-LABEL: and_i8_65:
1618 ; MM32R3: # %bb.0: # %entry
1619 ; MM32R3-NEXT: jr $ra
1620 ; MM32R3-NEXT: andi $2, $4, 65
1621 ;
1622 ; MM32R6-LABEL: and_i8_65:
1623 ; MM32R6: # %bb.0: # %entry
1624 ; MM32R6-NEXT: andi $2, $4, 65
1625 ; MM32R6-NEXT: jrc $ra
1626 entry:
1627 %r = and i8 65, %b
1628 ret i8 %r
1629 }
1631 define signext i16 @and_i16_65(i16 signext %b) {
1632 ; MIPS-LABEL: and_i16_65:
1633 ; MIPS: # %bb.0: # %entry
1634 ; MIPS-NEXT: jr $ra
1635 ; MIPS-NEXT: andi $2, $4, 65
1636 ;
1637 ; MIPS32R2-LABEL: and_i16_65:
1638 ; MIPS32R2: # %bb.0: # %entry
1639 ; MIPS32R2-NEXT: jr $ra
1640 ; MIPS32R2-NEXT: andi $2, $4, 65
1641 ;
1642 ; MIPS32R6-LABEL: and_i16_65:
1643 ; MIPS32R6: # %bb.0: # %entry
1644 ; MIPS32R6-NEXT: jr $ra
1645 ; MIPS32R6-NEXT: andi $2, $4, 65
1646 ;
1647 ; MIPS64-LABEL: and_i16_65:
1648 ; MIPS64: # %bb.0: # %entry
1649 ; MIPS64-NEXT: jr $ra
1650 ; MIPS64-NEXT: andi $2, $4, 65
1651 ;
1652 ; MIPS64R2-LABEL: and_i16_65:
1653 ; MIPS64R2: # %bb.0: # %entry
1654 ; MIPS64R2-NEXT: jr $ra
1655 ; MIPS64R2-NEXT: andi $2, $4, 65
1656 ;
1657 ; MIPS64R6-LABEL: and_i16_65:
1658 ; MIPS64R6: # %bb.0: # %entry
1659 ; MIPS64R6-NEXT: jr $ra
1660 ; MIPS64R6-NEXT: andi $2, $4, 65
1661 ;
1662 ; MM32R3-LABEL: and_i16_65:
1663 ; MM32R3: # %bb.0: # %entry
1664 ; MM32R3-NEXT: jr $ra
1665 ; MM32R3-NEXT: andi $2, $4, 65
1666 ;
1667 ; MM32R6-LABEL: and_i16_65:
1668 ; MM32R6: # %bb.0: # %entry
1669 ; MM32R6-NEXT: andi $2, $4, 65
1670 ; MM32R6-NEXT: jrc $ra
1671 entry:
1672 %r = and i16 65, %b
1673 ret i16 %r
1674 }
1676 define signext i32 @and_i32_65(i32 signext %b) {
1677 ; MIPS-LABEL: and_i32_65:
1678 ; MIPS: # %bb.0: # %entry
1679 ; MIPS-NEXT: jr $ra
1680 ; MIPS-NEXT: andi $2, $4, 65
1681 ;
1682 ; MIPS32R2-LABEL: and_i32_65:
1683 ; MIPS32R2: # %bb.0: # %entry
1684 ; MIPS32R2-NEXT: jr $ra
1685 ; MIPS32R2-NEXT: andi $2, $4, 65
1686 ;
1687 ; MIPS32R6-LABEL: and_i32_65:
1688 ; MIPS32R6: # %bb.0: # %entry
1689 ; MIPS32R6-NEXT: jr $ra
1690 ; MIPS32R6-NEXT: andi $2, $4, 65
1691 ;
1692 ; MIPS64-LABEL: and_i32_65:
1693 ; MIPS64: # %bb.0: # %entry
1694 ; MIPS64-NEXT: jr $ra
1695 ; MIPS64-NEXT: andi $2, $4, 65
1696 ;
1697 ; MIPS64R2-LABEL: and_i32_65:
1698 ; MIPS64R2: # %bb.0: # %entry
1699 ; MIPS64R2-NEXT: jr $ra
1700 ; MIPS64R2-NEXT: andi $2, $4, 65
1701 ;
1702 ; MIPS64R6-LABEL: and_i32_65:
1703 ; MIPS64R6: # %bb.0: # %entry
1704 ; MIPS64R6-NEXT: jr $ra
1705 ; MIPS64R6-NEXT: andi $2, $4, 65
1706 ;
1707 ; MM32R3-LABEL: and_i32_65:
1708 ; MM32R3: # %bb.0: # %entry
1709 ; MM32R3-NEXT: jr $ra
1710 ; MM32R3-NEXT: andi $2, $4, 65
1711 ;
1712 ; MM32R6-LABEL: and_i32_65:
1713 ; MM32R6: # %bb.0: # %entry
1714 ; MM32R6-NEXT: andi $2, $4, 65
1715 ; MM32R6-NEXT: jrc $ra
1716 entry:
1717 %r = and i32 65, %b
1718 ret i32 %r
1719 }
1721 define signext i64 @and_i64_65(i64 signext %b) {
1722 ; MIPS-LABEL: and_i64_65:
1723 ; MIPS: # %bb.0: # %entry
1724 ; MIPS-NEXT: andi $3, $5, 65
1725 ; MIPS-NEXT: jr $ra
1726 ; MIPS-NEXT: addiu $2, $zero, 0
1727 ;
1728 ; MIPS32R2-LABEL: and_i64_65:
1729 ; MIPS32R2: # %bb.0: # %entry
1730 ; MIPS32R2-NEXT: andi $3, $5, 65
1731 ; MIPS32R2-NEXT: jr $ra
1732 ; MIPS32R2-NEXT: addiu $2, $zero, 0
1733 ;
1734 ; MIPS32R6-LABEL: and_i64_65:
1735 ; MIPS32R6: # %bb.0: # %entry
1736 ; MIPS32R6-NEXT: andi $3, $5, 65
1737 ; MIPS32R6-NEXT: jr $ra
1738 ; MIPS32R6-NEXT: addiu $2, $zero, 0
1739 ;
1740 ; MIPS64-LABEL: and_i64_65:
1741 ; MIPS64: # %bb.0: # %entry
1742 ; MIPS64-NEXT: jr $ra
1743 ; MIPS64-NEXT: andi $2, $4, 65
1744 ;
1745 ; MIPS64R2-LABEL: and_i64_65:
1746 ; MIPS64R2: # %bb.0: # %entry
1747 ; MIPS64R2-NEXT: jr $ra
1748 ; MIPS64R2-NEXT: andi $2, $4, 65
1749 ;
1750 ; MIPS64R6-LABEL: and_i64_65:
1751 ; MIPS64R6: # %bb.0: # %entry
1752 ; MIPS64R6-NEXT: jr $ra
1753 ; MIPS64R6-NEXT: andi $2, $4, 65
1754 ;
1755 ; MM32R3-LABEL: and_i64_65:
1756 ; MM32R3: # %bb.0: # %entry
1757 ; MM32R3-NEXT: li16 $2, 0
1758 ; MM32R3-NEXT: jr $ra
1759 ; MM32R3-NEXT: andi $3, $5, 65
1760 ;
1761 ; MM32R6-LABEL: and_i64_65:
1762 ; MM32R6: # %bb.0: # %entry
1763 ; MM32R6-NEXT: andi $3, $5, 65
1764 ; MM32R6-NEXT: li16 $2, 0
1765 ; MM32R6-NEXT: jrc $ra
1766 entry:
1767 %r = and i64 65, %b
1768 ret i64 %r
1769 }
1771 define signext i128 @and_i128_65(i128 signext %b) {
1772 ; MIPS-LABEL: and_i128_65:
1773 ; MIPS: # %bb.0: # %entry
1774 ; MIPS-NEXT: andi $5, $7, 65
1775 ; MIPS-NEXT: addiu $2, $zero, 0
1776 ; MIPS-NEXT: addiu $3, $zero, 0
1777 ; MIPS-NEXT: jr $ra
1778 ; MIPS-NEXT: addiu $4, $zero, 0
1779 ;
1780 ; MIPS32R2-LABEL: and_i128_65:
1781 ; MIPS32R2: # %bb.0: # %entry
1782 ; MIPS32R2-NEXT: andi $5, $7, 65
1783 ; MIPS32R2-NEXT: addiu $2, $zero, 0
1784 ; MIPS32R2-NEXT: addiu $3, $zero, 0
1785 ; MIPS32R2-NEXT: jr $ra
1786 ; MIPS32R2-NEXT: addiu $4, $zero, 0
1787 ;
1788 ; MIPS32R6-LABEL: and_i128_65:
1789 ; MIPS32R6: # %bb.0: # %entry
1790 ; MIPS32R6-NEXT: andi $5, $7, 65
1791 ; MIPS32R6-NEXT: addiu $2, $zero, 0
1792 ; MIPS32R6-NEXT: addiu $3, $zero, 0
1793 ; MIPS32R6-NEXT: jr $ra
1794 ; MIPS32R6-NEXT: addiu $4, $zero, 0
1795 ;
1796 ; MIPS64-LABEL: and_i128_65:
1797 ; MIPS64: # %bb.0: # %entry
1798 ; MIPS64-NEXT: andi $3, $5, 65
1799 ; MIPS64-NEXT: jr $ra
1800 ; MIPS64-NEXT: daddiu $2, $zero, 0
1801 ;
1802 ; MIPS64R2-LABEL: and_i128_65:
1803 ; MIPS64R2: # %bb.0: # %entry
1804 ; MIPS64R2-NEXT: andi $3, $5, 65
1805 ; MIPS64R2-NEXT: jr $ra
1806 ; MIPS64R2-NEXT: daddiu $2, $zero, 0
1807 ;
1808 ; MIPS64R6-LABEL: and_i128_65:
1809 ; MIPS64R6: # %bb.0: # %entry
1810 ; MIPS64R6-NEXT: andi $3, $5, 65
1811 ; MIPS64R6-NEXT: jr $ra
1812 ; MIPS64R6-NEXT: daddiu $2, $zero, 0
1813 ;
1814 ; MM32R3-LABEL: and_i128_65:
1815 ; MM32R3: # %bb.0: # %entry
1816 ; MM32R3-NEXT: li16 $2, 0
1817 ; MM32R3-NEXT: li16 $3, 0
1818 ; MM32R3-NEXT: li16 $4, 0
1819 ; MM32R3-NEXT: jr $ra
1820 ; MM32R3-NEXT: andi $5, $7, 65
1821 ;
1822 ; MM32R6-LABEL: and_i128_65:
1823 ; MM32R6: # %bb.0: # %entry
1824 ; MM32R6-NEXT: andi $5, $7, 65
1825 ; MM32R6-NEXT: li16 $2, 0
1826 ; MM32R6-NEXT: li16 $3, 0
1827 ; MM32R6-NEXT: li16 $4, 0
1828 ; MM32R6-NEXT: jrc $ra
1829 entry:
1830 %r = and i128 65, %b
1831 ret i128 %r
1832 }
1834 define signext i1 @and_i1_256(i1 signext %b) {
1835 ; MIPS-LABEL: and_i1_256:
1836 ; MIPS: # %bb.0: # %entry
1837 ; MIPS-NEXT: jr $ra
1838 ; MIPS-NEXT: addiu $2, $zero, 0
1839 ;
1840 ; MIPS32R2-LABEL: and_i1_256:
1841 ; MIPS32R2: # %bb.0: # %entry
1842 ; MIPS32R2-NEXT: jr $ra
1843 ; MIPS32R2-NEXT: addiu $2, $zero, 0
1844 ;
1845 ; MIPS32R6-LABEL: and_i1_256:
1846 ; MIPS32R6: # %bb.0: # %entry
1847 ; MIPS32R6-NEXT: jr $ra
1848 ; MIPS32R6-NEXT: addiu $2, $zero, 0
1849 ;
1850 ; MIPS64-LABEL: and_i1_256:
1851 ; MIPS64: # %bb.0: # %entry
1852 ; MIPS64-NEXT: jr $ra
1853 ; MIPS64-NEXT: addiu $2, $zero, 0
1854 ;
1855 ; MIPS64R2-LABEL: and_i1_256:
1856 ; MIPS64R2: # %bb.0: # %entry
1857 ; MIPS64R2-NEXT: jr $ra
1858 ; MIPS64R2-NEXT: addiu $2, $zero, 0
1859 ;
1860 ; MIPS64R6-LABEL: and_i1_256:
1861 ; MIPS64R6: # %bb.0: # %entry
1862 ; MIPS64R6-NEXT: jr $ra
1863 ; MIPS64R6-NEXT: addiu $2, $zero, 0
1864 ;
1865 ; MM32R3-LABEL: and_i1_256:
1866 ; MM32R3: # %bb.0: # %entry
1867 ; MM32R3-NEXT: li16 $2, 0
1868 ; MM32R3-NEXT: jrc $ra
1869 ;
1870 ; MM32R6-LABEL: and_i1_256:
1871 ; MM32R6: # %bb.0: # %entry
1872 ; MM32R6-NEXT: li16 $2, 0
1873 ; MM32R6-NEXT: jrc $ra
1874 entry:
1875 %r = and i1 256, %b
1876 ret i1 %r
1877 }
1879 define signext i8 @and_i8_256(i8 signext %b) {
1880 ; MIPS-LABEL: and_i8_256:
1881 ; MIPS: # %bb.0: # %entry
1882 ; MIPS-NEXT: jr $ra
1883 ; MIPS-NEXT: addiu $2, $zero, 0
1884 ;
1885 ; MIPS32R2-LABEL: and_i8_256:
1886 ; MIPS32R2: # %bb.0: # %entry
1887 ; MIPS32R2-NEXT: jr $ra
1888 ; MIPS32R2-NEXT: addiu $2, $zero, 0
1889 ;
1890 ; MIPS32R6-LABEL: and_i8_256:
1891 ; MIPS32R6: # %bb.0: # %entry
1892 ; MIPS32R6-NEXT: jr $ra
1893 ; MIPS32R6-NEXT: addiu $2, $zero, 0
1894 ;
1895 ; MIPS64-LABEL: and_i8_256:
1896 ; MIPS64: # %bb.0: # %entry
1897 ; MIPS64-NEXT: jr $ra
1898 ; MIPS64-NEXT: addiu $2, $zero, 0
1899 ;
1900 ; MIPS64R2-LABEL: and_i8_256:
1901 ; MIPS64R2: # %bb.0: # %entry
1902 ; MIPS64R2-NEXT: jr $ra
1903 ; MIPS64R2-NEXT: addiu $2, $zero, 0
1904 ;
1905 ; MIPS64R6-LABEL: and_i8_256:
1906 ; MIPS64R6: # %bb.0: # %entry
1907 ; MIPS64R6-NEXT: jr $ra
1908 ; MIPS64R6-NEXT: addiu $2, $zero, 0
1909 ;
1910 ; MM32R3-LABEL: and_i8_256:
1911 ; MM32R3: # %bb.0: # %entry
1912 ; MM32R3-NEXT: li16 $2, 0
1913 ; MM32R3-NEXT: jrc $ra
1914 ;
1915 ; MM32R6-LABEL: and_i8_256:
1916 ; MM32R6: # %bb.0: # %entry
1917 ; MM32R6-NEXT: li16 $2, 0
1918 ; MM32R6-NEXT: jrc $ra
1919 entry:
1920 %r = and i8 256, %b
1921 ret i8 %r
1922 }
1924 define signext i16 @and_i16_256(i16 signext %b) {
1925 ; MIPS-LABEL: and_i16_256:
1926 ; MIPS: # %bb.0: # %entry
1927 ; MIPS-NEXT: jr $ra
1928 ; MIPS-NEXT: andi $2, $4, 256
1929 ;
1930 ; MIPS32R2-LABEL: and_i16_256:
1931 ; MIPS32R2: # %bb.0: # %entry
1932 ; MIPS32R2-NEXT: jr $ra
1933 ; MIPS32R2-NEXT: andi $2, $4, 256
1934 ;
1935 ; MIPS32R6-LABEL: and_i16_256:
1936 ; MIPS32R6: # %bb.0: # %entry
1937 ; MIPS32R6-NEXT: jr $ra
1938 ; MIPS32R6-NEXT: andi $2, $4, 256
1939 ;
1940 ; MIPS64-LABEL: and_i16_256:
1941 ; MIPS64: # %bb.0: # %entry
1942 ; MIPS64-NEXT: jr $ra
1943 ; MIPS64-NEXT: andi $2, $4, 256
1944 ;
1945 ; MIPS64R2-LABEL: and_i16_256:
1946 ; MIPS64R2: # %bb.0: # %entry
1947 ; MIPS64R2-NEXT: jr $ra
1948 ; MIPS64R2-NEXT: andi $2, $4, 256
1949 ;
1950 ; MIPS64R6-LABEL: and_i16_256:
1951 ; MIPS64R6: # %bb.0: # %entry
1952 ; MIPS64R6-NEXT: jr $ra
1953 ; MIPS64R6-NEXT: andi $2, $4, 256
1954 ;
1955 ; MM32R3-LABEL: and_i16_256:
1956 ; MM32R3: # %bb.0: # %entry
1957 ; MM32R3-NEXT: jr $ra
1958 ; MM32R3-NEXT: andi $2, $4, 256
1959 ;
1960 ; MM32R6-LABEL: and_i16_256:
1961 ; MM32R6: # %bb.0: # %entry
1962 ; MM32R6-NEXT: andi $2, $4, 256
1963 ; MM32R6-NEXT: jrc $ra
1964 entry:
1965 %r = and i16 256, %b
1966 ret i16 %r
1967 }
1969 define signext i32 @and_i32_256(i32 signext %b) {
1970 ; MIPS-LABEL: and_i32_256:
1971 ; MIPS: # %bb.0: # %entry
1972 ; MIPS-NEXT: jr $ra
1973 ; MIPS-NEXT: andi $2, $4, 256
1974 ;
1975 ; MIPS32R2-LABEL: and_i32_256:
1976 ; MIPS32R2: # %bb.0: # %entry
1977 ; MIPS32R2-NEXT: jr $ra
1978 ; MIPS32R2-NEXT: andi $2, $4, 256
1979 ;
1980 ; MIPS32R6-LABEL: and_i32_256:
1981 ; MIPS32R6: # %bb.0: # %entry
1982 ; MIPS32R6-NEXT: jr $ra
1983 ; MIPS32R6-NEXT: andi $2, $4, 256
1984 ;
1985 ; MIPS64-LABEL: and_i32_256:
1986 ; MIPS64: # %bb.0: # %entry
1987 ; MIPS64-NEXT: jr $ra
1988 ; MIPS64-NEXT: andi $2, $4, 256
1989 ;
1990 ; MIPS64R2-LABEL: and_i32_256:
1991 ; MIPS64R2: # %bb.0: # %entry
1992 ; MIPS64R2-NEXT: jr $ra
1993 ; MIPS64R2-NEXT: andi $2, $4, 256
1994 ;
1995 ; MIPS64R6-LABEL: and_i32_256:
1996 ; MIPS64R6: # %bb.0: # %entry
1997 ; MIPS64R6-NEXT: jr $ra
1998 ; MIPS64R6-NEXT: andi $2, $4, 256
1999 ;
2000 ; MM32R3-LABEL: and_i32_256:
2001 ; MM32R3: # %bb.0: # %entry
2002 ; MM32R3-NEXT: jr $ra
2003 ; MM32R3-NEXT: andi $2, $4, 256
2004 ;
2005 ; MM32R6-LABEL: and_i32_256:
2006 ; MM32R6: # %bb.0: # %entry
2007 ; MM32R6-NEXT: andi $2, $4, 256
2008 ; MM32R6-NEXT: jrc $ra
2009 entry:
2010 %r = and i32 256, %b
2011 ret i32 %r
2012 }
2014 define signext i64 @and_i64_256(i64 signext %b) {
2015 ; MIPS-LABEL: and_i64_256:
2016 ; MIPS: # %bb.0: # %entry
2017 ; MIPS-NEXT: andi $3, $5, 256
2018 ; MIPS-NEXT: jr $ra
2019 ; MIPS-NEXT: addiu $2, $zero, 0
2020 ;
2021 ; MIPS32R2-LABEL: and_i64_256:
2022 ; MIPS32R2: # %bb.0: # %entry
2023 ; MIPS32R2-NEXT: andi $3, $5, 256
2024 ; MIPS32R2-NEXT: jr $ra
2025 ; MIPS32R2-NEXT: addiu $2, $zero, 0
2026 ;
2027 ; MIPS32R6-LABEL: and_i64_256:
2028 ; MIPS32R6: # %bb.0: # %entry
2029 ; MIPS32R6-NEXT: andi $3, $5, 256
2030 ; MIPS32R6-NEXT: jr $ra
2031 ; MIPS32R6-NEXT: addiu $2, $zero, 0
2032 ;
2033 ; MIPS64-LABEL: and_i64_256:
2034 ; MIPS64: # %bb.0: # %entry
2035 ; MIPS64-NEXT: jr $ra
2036 ; MIPS64-NEXT: andi $2, $4, 256
2037 ;
2038 ; MIPS64R2-LABEL: and_i64_256:
2039 ; MIPS64R2: # %bb.0: # %entry
2040 ; MIPS64R2-NEXT: jr $ra
2041 ; MIPS64R2-NEXT: andi $2, $4, 256
2042 ;
2043 ; MIPS64R6-LABEL: and_i64_256:
2044 ; MIPS64R6: # %bb.0: # %entry
2045 ; MIPS64R6-NEXT: jr $ra
2046 ; MIPS64R6-NEXT: andi $2, $4, 256
2047 ;
2048 ; MM32R3-LABEL: and_i64_256:
2049 ; MM32R3: # %bb.0: # %entry
2050 ; MM32R3-NEXT: li16 $2, 0
2051 ; MM32R3-NEXT: jr $ra
2052 ; MM32R3-NEXT: andi $3, $5, 256
2053 ;
2054 ; MM32R6-LABEL: and_i64_256:
2055 ; MM32R6: # %bb.0: # %entry
2056 ; MM32R6-NEXT: andi $3, $5, 256
2057 ; MM32R6-NEXT: li16 $2, 0
2058 ; MM32R6-NEXT: jrc $ra
2059 entry:
2060 %r = and i64 256, %b
2061 ret i64 %r
2062 }
2064 define signext i128 @and_i128_256(i128 signext %b) {
2065 ; MIPS-LABEL: and_i128_256:
2066 ; MIPS: # %bb.0: # %entry
2067 ; MIPS-NEXT: andi $5, $7, 256
2068 ; MIPS-NEXT: addiu $2, $zero, 0
2069 ; MIPS-NEXT: addiu $3, $zero, 0
2070 ; MIPS-NEXT: jr $ra
2071 ; MIPS-NEXT: addiu $4, $zero, 0
2072 ;
2073 ; MIPS32R2-LABEL: and_i128_256:
2074 ; MIPS32R2: # %bb.0: # %entry
2075 ; MIPS32R2-NEXT: andi $5, $7, 256
2076 ; MIPS32R2-NEXT: addiu $2, $zero, 0
2077 ; MIPS32R2-NEXT: addiu $3, $zero, 0
2078 ; MIPS32R2-NEXT: jr $ra
2079 ; MIPS32R2-NEXT: addiu $4, $zero, 0
2080 ;
2081 ; MIPS32R6-LABEL: and_i128_256:
2082 ; MIPS32R6: # %bb.0: # %entry
2083 ; MIPS32R6-NEXT: andi $5, $7, 256
2084 ; MIPS32R6-NEXT: addiu $2, $zero, 0
2085 ; MIPS32R6-NEXT: addiu $3, $zero, 0
2086 ; MIPS32R6-NEXT: jr $ra
2087 ; MIPS32R6-NEXT: addiu $4, $zero, 0
2088 ;
2089 ; MIPS64-LABEL: and_i128_256:
2090 ; MIPS64: # %bb.0: # %entry
2091 ; MIPS64-NEXT: andi $3, $5, 256
2092 ; MIPS64-NEXT: jr $ra
2093 ; MIPS64-NEXT: daddiu $2, $zero, 0
2094 ;
2095 ; MIPS64R2-LABEL: and_i128_256:
2096 ; MIPS64R2: # %bb.0: # %entry
2097 ; MIPS64R2-NEXT: andi $3, $5, 256
2098 ; MIPS64R2-NEXT: jr $ra
2099 ; MIPS64R2-NEXT: daddiu $2, $zero, 0
2100 ;
2101 ; MIPS64R6-LABEL: and_i128_256:
2102 ; MIPS64R6: # %bb.0: # %entry
2103 ; MIPS64R6-NEXT: andi $3, $5, 256
2104 ; MIPS64R6-NEXT: jr $ra
2105 ; MIPS64R6-NEXT: daddiu $2, $zero, 0
2106 ;
2107 ; MM32R3-LABEL: and_i128_256:
2108 ; MM32R3: # %bb.0: # %entry
2109 ; MM32R3-NEXT: li16 $2, 0
2110 ; MM32R3-NEXT: li16 $3, 0
2111 ; MM32R3-NEXT: li16 $4, 0
2112 ; MM32R3-NEXT: jr $ra
2113 ; MM32R3-NEXT: andi $5, $7, 256
2114 ;
2115 ; MM32R6-LABEL: and_i128_256:
2116 ; MM32R6: # %bb.0: # %entry
2117 ; MM32R6-NEXT: andi $5, $7, 256
2118 ; MM32R6-NEXT: li16 $2, 0
2119 ; MM32R6-NEXT: li16 $3, 0
2120 ; MM32R6-NEXT: li16 $4, 0
2121 ; MM32R6-NEXT: jrc $ra
2122 entry:
2123 %r = and i128 256, %b
2124 ret i128 %r
2125 }